Solar cell and method for manufacturing solar cell

Abstract

To provide a solar cell and a method for manufacturing the solar cell.SOLUTION: A solar cell includes a substrate having a first surface and a second surface facing each other along a first direction, a tunnel oxide layer provided on the first surface and / or the second surface, a doped polycrystalline silicon layer disposed on the surface of the tunnel oxide layer remote from the substrate, a barrier layer provided in an electrode region of the solar cell and in contact with the doped polycrystalline silicon layer, and having the same doping type as the doped polycrystalline silicon layer, and an electrode in contact with the barrier layer. The solar cell according to an embodiment of the present application reduces the risk of the electrode burning through the doped polycrystalline silicon layer by providing a barrier layer in contact with the doped polycrystalline silicon layer in the electrode region. In addition, the thickness of the doped polycrystalline silicon layer can be further reduced, thereby reducing the absorption of incident light by the doped polycrystalline silicon layer and improving the utilization rate of the incident light of the solar cell.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates mainly to the field of solar cells, and more particularly to a type of solar cell and a method for manufacturing the solar cell. [Background technology]

[0002] The tunnel oxide solar cell (Tunnel Oxide Passivating Contacts, TOPCon) was proposed in 2014. The solar cell includes a tunnel oxide layer and a doped polysilicon layer, where the tunnel oxide can selectively transport carriers and the doped polysilicon layer functions as field passivation. The solar cell's electrodes contact the doped polysilicon layer through a functional layer (e.g., an anti-reflection layer) located in the electrode region.

[0003] The doped polysilicon layer in a solar cell has optical parasitic effects, which reduce the solar cell's utilization rate of incident light. By reducing the thickness of the doped polysilicon layer, the doped polysilicon layer's absorption of incident light can be reduced, thereby increasing the solar cell's utilization rate of incident light. However, reducing the thickness of the doped polysilicon layer increases the risk of the electrode contacting the substrate after burning through the polysilicon layer. Contact between the electrode and the substrate will increase the combined current density, which will severely affect the solar cell's efficiency.

[0004] Therefore, an issue that needs to be resolved urgently is how to balance the benefits of reducing the thickness of the doped polysilicon layer in terms of increased utilization of incident light with the drawback of reducing the thickness of the doped polysilicon layer in terms of increased risk of the electrode burning through the doped polysilicon layer. Summary of the Invention [Problem to be solved by the invention]

[0005] The technical problem to be solved by the present application is to provide a solar cell and a method for manufacturing the solar cell that can reduce the thickness of the doped polycrystalline silicon layer while preventing an electrode from burning through the doped polycrystalline silicon layer. [Means for solving the problem]

[0006] In order to solve the above technical problems, the technical solution adopted by the present application is a solar cell, the solar cell comprising: a substrate having a first surface and a second surface opposite to each other along a first direction; a tunnel oxide layer formed on the first surface and / or the second surface; a doped polycrystalline silicon layer formed on a surface of the tunnel oxide layer remote from the substrate; a barrier layer formed in an electrode region of the solar cell and in contact with the doped polycrystalline silicon layer, the barrier layer having the same doping type as the doped polycrystalline silicon layer; and an electrode in contact with the barrier layer, wherein the first direction is a thickness direction of the substrate.

[0007] In one embodiment of the present application, the barrier layer is provided on a surface of the doped polycrystalline silicon layer remote from the substrate.

[0008] In one embodiment of the present application, the barrier layer extends along the first direction to a predetermined depth in the doped polysilicon layer, wherein the predetermined depth is equal to or less than a thickness of the doped polysilicon layer.

[0009] In one embodiment of the present application, the barrier layer is provided on the surface of the tunnel oxide layer remote from the substrate.

[0010] In one embodiment of the present application, the surface of the barrier layer facing away from the substrate is flush with the surface of the doped polycrystalline silicon layer facing away from the substrate, or is closer to the substrate than the surface of the doped polycrystalline silicon layer facing away from the substrate, or is farther from the substrate than the surface of the doped polycrystalline silicon layer facing away from the substrate.

[0011] In one embodiment of the present application, the material of the barrier layer includes one or more of polycrystalline silicon, silicon carbide, and zinc oxide.

[0012] In one embodiment of the present application, the crystallinity of the polycrystalline silicon is greater than the crystallinity of the doped polycrystalline silicon layer.

[0013] In one embodiment of the present application, the polycrystalline silicon has a crystallinity of 90% or more, and the doped polycrystalline silicon layer has a crystallinity of 80% to 95%.

[0014] In one embodiment of the present application, the combined current density of the electrode regions is 100 fA / cm 2 The following is the result.

[0015] In one embodiment of the present application, the device further comprises a dielectric layer provided on the surface of the doped polycrystalline silicon layer and the barrier layer remote from the substrate.

[0016] In one embodiment of the present application, the electrode penetrates the dielectric layer and contacts the barrier layer.

[0017] In one embodiment of the present application, the thickness of the doped polycrystalline silicon layer is 3 nm or more and 200 nm or less.

[0018] To solve the above technical problems, the present application proposes a method for manufacturing a solar cell, which includes the steps of: providing a substrate having a first surface and a second surface opposite to each other along a first direction; forming a tunnel oxide layer on the first surface and / or the second surface; forming a doped polycrystalline silicon layer on a surface of the tunnel oxide layer away from the substrate; forming a barrier layer in contact with the doped polycrystalline silicon layer and having the same doping type as the doped polycrystalline silicon layer in an electrode region of the solar cell; and forming an electrode in contact with the barrier layer, wherein the first direction is a thickness direction of the substrate.

[0019] In one embodiment of the present application, a method for forming a barrier layer comprises cleaning a surface of the doped polycrystalline silicon layer and forming a barrier layer in contact with a surface of the doped polycrystalline silicon layer remote from the substrate in the electrode region.

[0020] In one embodiment of the present application, the material of the barrier layer includes one or more of polycrystalline silicon, silicon carbide, and zinc oxide.

[0021] In one embodiment of the present application, a method for forming a barrier layer includes: etching a doped polysilicon layer in the electrode region along a first direction to form a groove having a predetermined depth; and forming the barrier layer in the groove, wherein the predetermined depth is equal to or less than a thickness of the doped polysilicon layer.

[0022] In one embodiment of the present application, a method for forming a barrier layer comprises performing a heat treatment on a doped polycrystalline silicon layer located in the electrode region to form the barrier layer, and / or performing a thinning treatment on the doped polycrystalline silicon layer and / or the barrier layer.

[0023] In one embodiment of the present application, the polycrystalline silicon has a crystallinity of 90% or more, and the doped polycrystalline silicon layer has a crystallinity of 80% to 95%.

[0024] In one embodiment of the present application, the combined current density of the electrode regions is 100 fA / cm2 or less.

[0025] In one embodiment of the present application, the thickness of the doped polycrystalline silicon layer is 3 nm or more and 200 nm or less.

[0026] The solar cell and the method for manufacturing the solar cell of the present application provide a barrier layer in contact with the doped polysilicon layer in the electrode region, thereby reducing the risk of the electrode burning through the doped polysilicon layer, and further reducing the thickness of the doped polysilicon layer, thereby reducing the absorption of incident light by the doped polysilicon layer and improving the utilization rate of the incident light of the solar cell.

[0027] In order to make the above objects, features and advantages of the present application more clearly comprehensible, specific embodiments of the present application will be described in detail below with reference to the accompanying drawings. [Brief explanation of the drawings]

[0028] [Figure 1] 1 is a schematic front view of a solar cell according to an embodiment of the present application. [Figure 2A] FIG. 2 is a front view of a solar cell according to another embodiment of the present application. [Figure 2B] FIG. 2B is an enlarged view of a partial structure in FIG. 2A. [Figure 3] 1 is a schematic front view of a solar cell according to an embodiment of the present application. [Figure 4A] 1 is a front view of a solar cell according to an embodiment of the present application; [Figure 4B] 1 is a front view of a solar cell according to an embodiment of the present application; [Figure 5] 1 is a flowchart of a method for manufacturing a solar cell according to an embodiment of the present application. [Figure 6] 1A-1C are intermediate products in the method of manufacturing a solar cell according to different embodiments of the present application. [Figure 7] 1A-1C are intermediate products in the method of manufacturing a solar cell according to different embodiments of the present application. DETAILED DESCRIPTION OF THE INVENTION

[0029] In order to make the above objects, features and advantages of the present application more clearly comprehensible, specific embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0030] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application; however, the present application may also be practiced in other ways other than those described herein, and therefore the present application is not limited to the specific embodiments disclosed below.

[0031] As set forth in this application and the claims, unless the context clearly indicates otherwise, terms such as "a," "one," "one," "a kind," and / or "the" do not specifically refer to the singular but may also include the plural. Generally, the terms "comprising" and "including" only indicate the inclusion of explicitly identified steps and elements, and do not constitute an exclusive list of these steps and elements; a method or apparatus may include other steps or elements.

[0032] Furthermore, the use of terms such as "first" and "second" to limit components is merely for the purpose of making it easier to distinguish the relevant components, and unless otherwise stated, the terms do not have any special meaning and should not be understood as limiting the scope of protection of the present application. Furthermore, although the terms used in this application are selected from well-known technical terms, some terms described in the specification of this application have been selected by the applicant at his / her own discretion, and their detailed meanings will be explained in the relevant parts of the description of this specification. It is necessary to understand this application not only through the actual terms used but also through the meanings contained in each term.

[0033] Flowcharts are used herein to describe operations performed by systems according to embodiments of the present application. It should be understood that the operations described above or below are not necessarily performed in exact order. Conversely, various steps may be processed in reverse order or simultaneously. Also, additional operations may be added to these procedures, or operations of one or more steps may be removed from these procedures.

[0034] Next, the solar cell and the method for manufacturing the solar cell according to the present application will be described with reference to specific embodiments.

[0035] FIG. 1 is a schematic front view of a solar cell according to one embodiment. As shown in FIG. 1, the solar cell includes a substrate 110, a tunnel oxide layer 120, a doped polycrystalline silicon layer 130, a barrier layer 140, and an electrode 150. The substrate 110 has a first surface 111 and a second surface 112 facing each other in a first direction D1 (which is also the thickness direction of the substrate 110). The first surface 111 and the second surface 112 may be polished or may be pyramidal. The tunnel oxide layer 120 is provided on the first surface 111, and the doped polycrystalline silicon layer 130 is provided on a surface of the tunnel oxide layer 120 away from the substrate 110 in the first direction D1. The tunnel oxide layer 120 and the doped polycrystalline silicon layer 130 together form a tunnel oxide layer-doped polycrystalline silicon layer passivation structure. It should be noted that in other embodiments, the tunnel oxide layer 120 may be formed on the second surface 112, or alternatively, may be formed on the first surface 111 and the second surface 112 simultaneously.

[0036] The substrate 110 may be a silicon substrate, for example, a single crystal silicon substrate or a polycrystalline silicon substrate. The substrate 110 may be doped, for example, by N-type doping or P-type doping. The material of the tunnel oxide layer 120 may be silicon oxide (SiO x), and the thickness of the tunnel oxide layer 120 may be any value between 1 nm and 3 nm, for example, 1 nm, 1.5 nm, 2 nm, 2.5 nm, or 3 nm. The tunnel oxide layer 120 serves to selectively collect carriers. The material of the doped polycrystalline silicon layer 130 may be selected from polycrystalline silicon, and the present application does not limit the crystal grain size of the polycrystalline silicon. The doping type of the doped polycrystalline silicon layer 130 may be the same as that of the substrate 110 or may be opposite to that of the substrate 110.

[0037] A solar cell has an electrode area, which is indicated in Figure 1 by a dashed rectangular frame 160. The electrodes of the solar cell are located in the electrode area, and the electrodes are used to collect electrical energy generated by the solar cell and transmit the electrical energy to the outside.

[0038] 1 , the barrier layer 140 is disposed in the electrode region and contacts the doped polycrystalline silicon layer 130, and the doping type of the barrier layer 140 is the same as that of the doped polycrystalline silicon layer 130. For example, the doping types of the doped polycrystalline silicon layer 130 and the barrier layer 140 may both be N-type, and the corresponding doping element may be selected from one or more of Group V elements, such as phosphorus (P), bismuth (Bi), antimony (Sb), and arsenic (As). The doping types of the doped polycrystalline silicon layer 130 and the barrier layer 140 may both be P-type, and the corresponding doping element may be selected from one or more of Group III elements, such as boron (B), aluminum (Al), gallium (Ga), and indium (In).

[0039] Continuing to show in Figure 1, electrode 150 is in contact with barrier layer 140. It should be noted that the number of electrode areas and electrodes 150 in the solar cell is not limited to the one shown in Figure 1, and the solar cell may include a certain number of electrode areas and electrodes 150 arranged at intervals along the second direction D2, which are not shown in Figure 1 due to limitations of the drawing size.

[0040] 1 further includes a dielectric layer 170. The dielectric layer 170 is disposed on surfaces of the doped polycrystalline silicon layer 130 and the barrier layer 140 that are away from the substrate 110 along the first direction D1. Alternatively, the dielectric layer 170 covers the exposed surfaces of the doped polycrystalline silicon layer 130 and the barrier layer 140. The electrode 150 penetrates the dielectric layer 170 and contacts the barrier layer 140. The dielectric layer 170 may be a laminated passivation film that has a passivation effect on the solar cell, and the dielectric layer 170 may be an anti-reflection film.

[0041] 1, the barrier layer 140 is provided on a surface of the doped polycrystalline silicon layer 130 that is away from the substrate 110 along the first direction D1. The electrode 150 is brought into contact with the barrier layer 140 by a firing process, thereby forming an electrical connection between the barrier layer 140 and the doped polycrystalline silicon layer 130 (the contact forms an electrical connection between the doped polycrystalline silicon layer 130 and the barrier layer 140). In FIG. 1, the electrode 150 penetrates the barrier layer 140 but does not penetrate the doped polycrystalline silicon layer 130. In some other embodiments, the electrode 150 can penetrate through the barrier layer 140 and further penetrate into the doped polycrystalline silicon layer 130.

[0042] The firing process has an ablative effect on the barrier layer 140 and the doped polysilicon layer 130, which can cause the electrode 150 to burn through the doped polysilicon layer 130 and contact the substrate 110. When the electrode 150 contacts the substrate 110, the combined current density in the electrode region increases dramatically, thereby reducing the efficiency of the solar cell.

[0043] In the present application, a barrier layer 140 is formed in contact with the doped polycrystalline silicon layer 130 in the electrode region (where the electrode 150 is fired), and when the electrode 150 is fired, the doped polycrystalline silicon layer 130 is further ablated after the electrode 150 burns through the barrier layer 140. Therefore, the barrier layer 140 reduces the risk that the electrode 150 burns through the doped polycrystalline silicon layer 130.

[0044] In one embodiment, the material of the barrier layer 140 is selected from a material that is more ablation-resistant than the doped polycrystalline silicon layer 130, such as silicon carbide and / or zinc oxide. Alternatively, the material of the barrier layer 140 may be polycrystalline silicon with a higher crystallinity than the doped polycrystalline silicon layer 130, where the higher crystallinity polycrystalline silicon is more ablation-resistant than the lower crystallinity polycrystalline silicon. In some embodiments, the crystallinity of the polycrystalline silicon in the barrier layer 140 is 90% or greater, and the crystallinity of the doped polycrystalline silicon layer 130 is 80% to 95%. For example, the crystallinity of the polycrystalline silicon in the barrier layer 140 may be 90%, 95%, 99%, or 100%, and the crystallinity of the doped polycrystalline silicon layer 130 may be 80%, 85%, 90%, or 95%. In some embodiments, the crystallinity of the polycrystalline silicon in the barrier layer 140 decreases as the distance from the substrate 110 in the first direction D1 decreases.

[0045] The material of the barrier layer 140 may be a mixture of two or more of silicon carbide, zinc oxide, and polycrystalline silicon. In some embodiments, when the barrier layer 140 is polycrystalline silicon, the polycrystalline silicon may be doped with carbon (C) and / or oxygen (O).

[0046] Here, the technical effect that "the barrier layer 140 can prevent the electrode 150 from burning through the doped polycrystalline silicon layer 130" will be summarized. In FIG. 1 , the barrier layer 140 is disposed on the surface of the doped polycrystalline silicon layer 130 away from the substrate 110, thereby increasing the length of the path along which the electrode 150 burns through the doped polycrystalline silicon layer 130 and further preventing the electrode 150 from burning through the doped polycrystalline silicon layer 130. At the same time, if the barrier layer 140 is selected from an ablation-resistant material, the barrier layer 140 can also prevent the electrode 150 from burning through the doped polycrystalline silicon layer 130 due to its own ablation-resistant properties. In short, the barrier layer 140 can prevent the electrode 150 from burning through the doped polycrystalline silicon layer 130 due to both "increasing the burn-through path" and "its own ablation-resistant properties." It should be understood that the barrier layer 140 does not have to utilize both of the above at the same time, but only one of them can prevent the polysilicon layer 130 from being burned through by the electrode 150.

[0047] Furthermore, the doped polysilicon layer 130 has optical parasitic effects, which reduce the solar cell's utilization rate for incident light. Reducing the thickness of the doped polysilicon layer 130 can reduce the absorption of incident light. However, in the prior art, reducing the thickness of the doped polysilicon layer 130 had the side effect of increasing the risk of the electrode 150 burning through the tunnel oxide layer 120. The present invention's technology of providing a barrier layer 140 in the electrode region increases the likelihood that the electrode 150 will burn through the doped polysilicon layer 130. Therefore, even if the thickness of the doped polysilicon layer 130 is reduced, the electrode 150 will not burn through the doped polysilicon layer 130. This reduces the absorption of incident light by the doped polysilicon layer 130 and increases the solar cell's utilization rate for incident light. In some embodiments, the thickness of the doped polycrystalline silicon layer 130 is 3 nm or more and 200 nm or less. For example, the thickness of the doped polycrystalline silicon layer 130 may be 3 nm, 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, 110 nm, 120 nm, 130 nm, 140 nm, 150 nm, 160 nm, 170 nm, 180 nm, 190 nm, or 200 nm. A thickness of 3 nm or more for the doped polycrystalline silicon layer 130 can ensure lateral carrier transport capability and satisfy requirements for field passivation for the substrate 110. The "thickness of the doped polycrystalline silicon layer 130" refers to the size of the doped polycrystalline silicon layer 130 in the first direction D1.

[0048] 1, the barrier layer 140 is disposed on a surface of the doped polycrystalline silicon layer 130 that is away from the substrate 110 along the first direction D1. The positional relationship between the barrier layer 140 and the doped polycrystalline silicon layer 130 in the present application is not limited to that shown in FIG. 1, and will be described below.

[0049] 2A is a schematic front view of a solar cell according to another embodiment, and FIG. 2B is an enlarged view of a partial structure in FIG. 2A. As shown in FIGS. 2A and 2B, unlike FIG. 1, the barrier layer 140 in FIGS. 2A and 2B extends in the first direction D1 to a predetermined depth d1 within the doped polycrystalline silicon layer 130. Here, the predetermined depth d1 is equal to or less than the thickness d2 of the doped polycrystalline silicon layer 130. The present application does not limit the predetermined depth d1, and it can be 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, 90%, or 100% of the thickness d2. It should be understood that when the predetermined depth d1 is equal to the thickness d2 of the doped polycrystalline silicon layer 130, the bottom surface 141 of the barrier layer 140 contacts the surface of the tunnel oxide layer 120 that is away from the surface of the substrate 110 in the first direction D1. In other words, the barrier layer 140 is disposed on the surface of the tunnel oxide layer 120 away from the substrate 110 in the first direction D1, as shown in FIG.

[0050] 4A and 4B are schematic front views of solar cells according to two embodiments. As shown in FIG. 4A, the barrier layer 140 is disposed on a surface of the tunnel oxide layer 120 that is away from the substrate 110 in the first direction D1, i.e., the bottom surface 141 of the barrier layer 140 contacts the tunnel oxide layer 120. The barrier layer 140 has a top surface 142 that is away from the substrate 110 along the first direction D1, and the doped polycrystalline silicon layer 130 has a surface 131 that is away from the substrate 110 along the first direction D1. In FIG. 4A, the top surface 142 of the barrier layer 140 is flush with the surface 131 of the doped polycrystalline silicon layer 130. As shown in FIG. 4B, the difference between FIG. 4B and FIG. 4A is that the top surface 142 of the barrier layer 140 in FIG. 4B is closer to the substrate 110 than the surface 131 of the doped polycrystalline silicon layer 130. In other embodiments, the upper surface 142 may be farther from the substrate 110 in the first direction D1 than the surface 131, i.e., the barrier layer 140 may protrude toward the surface 131, facing away from the substrate 110.

[0051] 1, a bottom surface 141 of the barrier layer 140 is in contact with the doped polycrystalline silicon layer 130. In FIGS. 2A to 4B, the side surfaces of the barrier layer 140 other than the bottom surface 141 are in contact with the doped polycrystalline silicon layer 130. Taking FIG. 3 as an example, the barrier layer 140 has a first side surface 143 and a second side surface 144 that face each other along the second direction D2, as shown in FIG. 3, and both the first side surface 143 and the second side surface 144 are in contact with the doped polycrystalline silicon layer 130. Increasing the contact area between the barrier layer 140 and the doped polycrystalline silicon layer 130 is advantageous for reducing resistance.

[0052] In one embodiment, the combined current density of the electrode regions of FIGS. 1-4B is 100 fA / cm 2 The reduction in the combined current density contributes to the improvement of the solar cell efficiency. 2 One of the main reasons for this is to avoid electrode 150 contacting substrate 110 without burning through doped polycrystalline silicon layer 130. In another embodiment, an ohmic contact is formed between electrode 150 and barrier layer 140, and the contact resistance between them is 1 mΩ cm. 2 The magnitude of the contact resistance can be adjusted by adjusting the doping concentration of the barrier layer 140, for example, the contact resistance can be reduced by increasing the doping concentration.

[0053] The solar cell in the above embodiment of the present application has a barrier layer in contact with the doped polysilicon layer in the electrode region, which reduces the risk of the electrode burning through the doped polysilicon layer, and the thickness of the doped polysilicon layer can be further reduced, thereby reducing the absorption of incident light by the doped polysilicon layer and improving the utilization rate of the incident light of the solar cell.

[0054] Another aspect of the present application also proposes a method for manufacturing a solar cell, which will be described subsequently.

[0055] FIG. 5 is a flowchart of a method for manufacturing a solar cell according to one embodiment. As shown in FIG. 5, the manufacturing method according to this embodiment includes the following steps.

[0056] Step S210: providing a substrate having a first surface and a second surface facing each other along a first direction; Step S220: forming a tunnel oxide layer on the first surface and / or the second surface; Step S230: forming a doped polycrystalline silicon layer on the surface of the tunnel oxide layer away from the substrate; Step S240: Form a barrier layer in the electrode region of the solar cell, the barrier layer contacts the doped polycrystalline silicon layer, and the doping type of the barrier layer is the same as that of the doped polycrystalline silicon layer; Step S250: An electrode is formed and brought into contact with the barrier layer.

[0057] Next, steps S210 to S250 will be described.

[0058] As shown in FIG. 1 , in step S210, a substrate 110 is provided. The substrate 110 has a first surface 111 and a second surface 112 that face each other along a first direction D1. In step S220, a tunnel oxide layer 120 is formed on the first surface 111. In some other embodiments, the tunnel oxide layer may be formed on the second surface 112, or on both the first surface 111 and the second surface 112. In step S230, a doped polysilicon layer 130 is formed on the surface of the tunnel oxide layer 120 that faces away from the substrate 110 along the first direction D1. Methods for forming the tunnel oxide layer 120 and the doped polysilicon layer 130 include chemical vapor deposition (CVD), physical vapor deposition (PVD), and thermal oxidation. For other descriptions of the substrate 110, the tunnel oxide layer 120, and the doped polysilicon layer 130, please refer to the relevant sections above. These descriptions will not be expanded here.

[0059] In some embodiments, the thickness of the doped polysilicon layer 130 is 3 nm or more and 200 nm or less, for example, the thickness of the doped polysilicon layer 130 may be 3 nm, 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, 110 nm, 120 nm, 130 nm, 140 nm, 150 nm, 160 nm, 170 nm, 180 nm, 190 nm, or 200 nm. Having a thickness of 3 nm or more for the doped polysilicon layer 130 can ensure lateral carrier transport capability and satisfy requirements for field passivation for the substrate 110.

[0060] 1, in step S240, a barrier layer 140 is formed in the electrode region of the solar cell, the barrier layer 140 contacts the doped polysilicon layer 130, and the doping type of the barrier layer 140 is the same as that of the doped polysilicon layer 130. Both the barrier layer 140 and the doped polysilicon layer 130 may be N-type doped or P-type doped.

[0061] In one embodiment, a method for forming the barrier layer 140 in FIG. 1 includes the following steps.

[0062] Step 11: Clean the surface of the doped polycrystalline silicon layer 130. This surface includes the surface of the doped polycrystalline silicon layer 130 that is away from the substrate 110 along the first direction D1. The cleaning process can remove contaminants from the surface of the doped polycrystalline silicon layer 130.

[0063] Step 12: A barrier layer 140 is formed in the electrode region, contacting the surface of the doped polycrystalline silicon layer 130 away from the substrate 110 along the first direction D1.

[0064] Methods for forming the barrier layer 140 in step 12 include chemical vapor deposition and physical vapor deposition. Materials for the barrier layer 140 include one or more of polycrystalline silicon, silicon carbide, and zinc oxide.

[0065] Referring to the intermediate products in the manufacturing process of the solar cell shown in FIGS. 2A, 2B and 6, in one embodiment, a method for forming the barrier layer 140 in FIGS. 2A and 2B includes the following steps.

[0066] Step 21: Etch the doped polycrystalline silicon layer 130 in the electrode region along the first direction D1 to form a groove 180 having a preset depth d3.

[0067] Step 22: Form a barrier layer 140 in the trench 180, where the preset depth d3 is equal to or less than the thickness d4 of the doped polycrystalline silicon layer 130.

[0068] 2A and 2B, the barrier layer 140 protrudes away from the substrate 110 relative to the doped polycrystalline silicon layer 130. In some other embodiments, the surface of the barrier layer 140 away from the substrate 110 can be flush with the surface of the doped polycrystalline silicon layer 130 away from the substrate 110.

[0069] As shown in Figures 3 and 6, when the preset depth d3 is equal to the thickness d4 of the doped polycrystalline silicon layer 130, the barrier layer 140 formed in the groove 180 contacts the surface of the tunnel oxide layer 120 away from the substrate 110.

[0070] Referring to the intermediate products in the manufacturing process of the solar cell shown in FIG. 4B and FIG. 7, the method for forming the barrier layer 140 in FIG. 4A includes the following steps.

[0071] Step 31: The initial barrier layer 132 (ie, the doped polycrystalline silicon layer located in the electrode region) is subjected to a heat treatment to form a barrier layer 140.

[0072] Specifically, as shown in FIG. 7, the initial barrier layer 132 can be heat-treated by a laser, and after the heat treatment, the crystallization rate of the initial barrier layer 132 can be improved, thereby converting the initial barrier layer 132 into the barrier layer 140 of FIG. 3.

[0073] In one embodiment, before step 31, a step of performing a high-temperature crystallization treatment on the doped polycrystalline silicon layer 130 can be further included. The high-temperature crystallization treatment can improve the crystallinity of the doped polycrystalline silicon layer 130. Based on this, step 31 performs a heat treatment on the initial barrier layer 132 to obtain a barrier layer 140 with a higher crystallinity. Methods of performing the high-temperature crystallization treatment on the doped polycrystalline silicon layer 130 include performing the high-temperature crystallization treatment on the polycrystalline silicon layer 130 using a tube furnace and performing the high-temperature crystallization treatment on the polycrystalline silicon layer 130 using a laser. In some embodiments, the crystallinity of the barrier layer 140 is greater than that of the doped polycrystalline silicon layer 130, and the crystallinity of the barrier layer 140 is 90% or more, and the crystallinity of the doped polycrystalline silicon layer 130 is 80% to 95%.

[0074] 4B, the surface of the barrier layer 140 away from the substrate 110 in the first direction D1 is closer to the substrate 110 than the surface of the doped polycrystalline silicon layer 130 away from the substrate 110 in the first direction D1. This is because the volume of the initial barrier layer 132 shrinks after the laser heat treatment.

[0075] 4A, compared with FIG. 4B, the surface of the barrier layer 140 in FIG. 4A that is away from the substrate 110 in the first direction D1 is flush with the surface of the doped polycrystalline silicon layer 130 that is away from the substrate 110 in the first direction D1. The method for forming the barrier layer 140 in FIG. 4A includes the following steps.

[0076] Step 32: A thinning process is performed on the doped polycrystalline silicon layer 130 of Fig. 4B. By performing the thinning process on the doped polycrystalline silicon layer 130, the doped polycrystalline silicon layer 130 can be made flush with the barrier layer 140 and damage to the surface of the doped polycrystalline silicon layer 130 caused by the laser heat treatment can be removed.

[0077] In some embodiments, the doped polycrystalline silicon layer 130 and the barrier layer 140 can be simultaneously thinned to achieve the target thickness of the doped polycrystalline silicon layer 130 and the barrier layer 140. By thinning the barrier layer 140, damage to the surface of the barrier layer 140 caused by the laser thermal treatment can be removed. In other embodiments, the doped polycrystalline silicon layer 130 alone can be thinned to position the surface 131 of the doped polycrystalline silicon layer 130 above the upper surface 142 of the barrier layer 140 in the first direction D1. In other embodiments, the barrier layer 140 alone can be thinned to achieve the target thickness of the barrier layer 140.

[0078] In one embodiment, the combined current density at the electrode regions is 100 fA / cm 2 The reduction in the combined current density contributes to the improvement of the efficiency of the solar cell.

[0079] Referring back to FIG. 5 , in step S250, an electrode is formed and contacts the barrier layer. Taking FIG. 1 as an example, in FIG. 1, an electrode 150 is formed in contact with the barrier layer 140. An electrical connection is established between the barrier layer 140 and the electrode 150 through the contact. The electrode 150 in contact with the barrier layer 140 can be formed by a firing method. The present application does not limit the depth to which the electrode 150 penetrates the barrier layer 140. In some embodiments, the electrode 150 can also penetrate through the barrier layer 140 and further into the doped polysilicon layer 130, but the electrode 150 does not penetrate the polysilicon layer 130.

[0080] 1, in some embodiments, before step S250, a step of forming a dielectric layer 170 covering a surface of the doped polycrystalline silicon layer 130 remote from the substrate 110 and a surface of the barrier layer 140 remote from the substrate 110 is further included. In step S250, the electrode 150 penetrates the dielectric layer 170 into the barrier layer 140.

[0081] The manufacturing method of the above embodiment of the present application provides a barrier layer in contact with the doped polysilicon layer in the electrode region, reducing the risk of the electrode burning through the doped polysilicon layer, and further reducing the thickness of the doped polysilicon layer, thereby reducing the absorption of incident light by the doped polysilicon layer and improving the utilization rate of the incident light of the solar cell.

[0082] Although the basic concepts have been described above, it will be apparent to those skilled in the art that the above disclosure is merely illustrative and not limiting of the present application. Although not explicitly stated herein, those skilled in the art may make various modifications, improvements, and amendments to the present application. Such modifications, improvements, and amendments are proposed herein and therefore fall within the spirit and scope of the exemplary embodiments of the present application.

[0083] At the same time, the present application uses specific terms to describe embodiments of the present application. For example, "one embodiment," "an embodiment," and / or "some embodiments" refer to features, configurations, or characteristics associated with at least one embodiment of the present application. Therefore, it should be emphasized and noted that "one embodiment," "one embodiment," or "one alternative embodiment" mentioned two or more times in different places in this specification do not necessarily refer to the same embodiment. Furthermore, some features, configurations, or characteristics in one or more embodiments of the present application may be combined as appropriate.

[0084] In some embodiments, numbers describing the number of components or attributes are used; however, it should be understood that the numbers describing such embodiments are, in some instances, modified using the modifiers "about," "approximately," or "approximately." Unless otherwise specified, "about," "approximately," or "approximately" means that the numerical value can vary by ±20%. Accordingly, in some embodiments, the numerical parameters used in the specification and claims are approximations, and these approximations may vary depending on the characteristics required for particular embodiments. In some embodiments, the numerical parameters should be calculated using a given number of significant digits and common digit preservation techniques. In some embodiments, the numerical fields and parameters used to determine the breadth of their ranges are approximations; however, in certain embodiments, such numerical values are set as precisely as possible within the ranges possible. [Explanation of symbols]

[0085] 110 Substrate 111 First Surface 112 Second Surface 120 Tunnel oxide layer 130 doped polycrystalline silicon layer 131 Surface 132 Initial Barrier Layer 140 Barrier Layer 141 bottom 142 Top surface 143 First Aspect 144 Second Aspect 150 electrodes 160 electrode area 170 Dielectric Layer 180 Groove

Claims

1. a substrate (110) having a first surface (111) and a second surface (112) facing each other along a first direction; a tunnel oxide layer (120) provided on the first surface and / or the second surface; a doped polycrystalline silicon layer (130) disposed on a surface of the tunnel oxide layer remote from the substrate; a barrier layer (140) disposed in the electrode region (160) of the solar cell and in contact with the doped polycrystalline silicon layer, the barrier layer having the same doping type as the doped polycrystalline silicon layer; an electrode (150) provided in the electrode region and in contact with the barrier layer; the first direction is a thickness direction of the substrate, the barrier layer is formed in a groove of a predetermined depth obtained by etching the doped polycrystalline silicon layer in the electrode region along a first direction; the predetermined depth is equal to or less than the thickness of the doped polycrystalline silicon layer; A solar cell, wherein the material of the barrier layer contains silicon carbide and / or zinc oxide.

2. the barrier layer extends along the first direction to a predetermined depth in the doped polycrystalline silicon layer; 2. The solar cell of claim 1, wherein the predetermined depth is equal to or less than the thickness of the doped polycrystalline silicon layer.

3. The barrier layer is provided on a surface of the tunnel oxide layer away from the substrate. The solar cell according to claim 1 .

4. 4. The solar cell of claim 3, wherein the surface of the barrier layer away from the substrate is flush with the surface of the doped polycrystalline silicon layer away from the substrate, or is closer to the substrate than the surface of the doped polycrystalline silicon layer away from the substrate, or is farther from the substrate than the surface of the doped polycrystalline silicon layer away from the substrate.

5. The combined current density of the electrode regions is 100 fA / cm ２ 2. The solar cell according to claim 1, wherein:

6. 2. The solar cell of claim 1, further comprising a dielectric layer provided on a surface of the doped polycrystalline silicon layer and the barrier layer remote from the substrate.

7. 7. The solar cell of claim 6, wherein the electrode penetrates the dielectric layer and contacts the barrier layer.

8. 2. The solar cell according to claim 1, wherein the thickness of the doped polycrystalline silicon layer is 3 nm or more and 200 nm or less.

9. providing a substrate having a first surface and a second surface opposed along a first direction; forming a tunnel oxide layer on the first surface and / or the second surface; forming a doped polycrystalline silicon layer on a surface of the tunnel oxide layer remote from the substrate; forming a barrier layer in contact with the doped polycrystalline silicon layer in the electrode region of the solar cell and having the same doping type as the doped polycrystalline silicon layer; forming an electrode in contact with the barrier layer; the first direction is a thickness direction of the substrate, The method for forming the barrier layer includes the steps of: etching the doped polycrystalline silicon layer in the electrode region along a first direction to form a groove having a predetermined depth; and forming the barrier layer in the groove; the predetermined depth is equal to or less than the thickness of the doped polycrystalline silicon layer; 10. A method for manufacturing a solar cell, wherein the material of the barrier layer contains silicon carbide and / or zinc oxide.

10. The step of forming the barrier layer includes: cleaning the surface of the doped polycrystalline silicon layer; 10. The method of claim 9, further comprising the step of: forming a barrier layer in contact with the surface of the doped polycrystalline silicon layer remote from the substrate in the electrode region.

11. The combined current density of the electrode regions is 100 fA / cm ２ 10. The method for producing a solar cell according to claim 9, wherein the following is true:

12. 10. The method for manufacturing a solar cell according to claim 9, wherein the thickness of the doped polycrystalline silicon layer is 3 nm or more and 200 nm or less.

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