Booster circuit and non-volatile memory device

Abstract

To suppress a drop in the voltage generated by a booster circuit.SOLUTION: A booster circuit (11) comprises: a charge pump circuit (5) which generates and outputs a boost voltage using a first voltage (VREG); a first line (LN1) connected to an output terminal of the charge pump circuit and having a second voltage (VP) applied thereto; a second line (LN2) to which a power supply voltage (VDD) is applied; a voltage generation circuit (2, R5, C2, 3, 4, CS2) which generates the first voltage according to an error between a feedback voltage (FB) based on the second voltage and a reference voltage (REF) or a soft-start voltage (VSF) gradually increasing during startup, whichever is lower; a detection circuit (CS3, R6, 7) which detects that the first voltage reached or exceeded a predetermined value; and a release circuit (6) which cancels the short-circuit state between the first line and the second line when the detection circuit detects that the first voltage reached or exceeded the predetermined value.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a voltage boost circuit and a nonvolatile memory device. [Background technology]

[0002] BACKGROUND ART Conventionally, a charge pump circuit that outputs a boosted voltage is known (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-336753

[0004] [overview] When a load (a specified circuit) is connected to the output terminal of the charge pump circuit disclosed in Patent Document 1, a voltage that gradually increases from the ground voltage is supplied from the charge pump circuit to the load at startup, which may cause the load to malfunction.

[0005] Here, it is conceivable that malfunctions of the load (specific circuit) can be suppressed by supplying the power supply voltage to the load at the beginning of startup, and then switching from the power supply voltage to a voltage boosted by a charge pump circuit during startup and supplying this to the load.

[0006] However, if the timing for switching from the power supply voltage to the voltage boosted by the charge pump circuit during startup is inappropriate, the voltage supplied to the load at that timing will temporarily drop.

[0007] The boost circuit of the present disclosure includes a charge pump circuit configured to generate and output a boosted voltage using a first voltage, a first line connected to the output terminal of the charge pump circuit and configured to receive a second voltage, a second line configured to receive a power supply voltage, a voltage generation circuit configured to generate the first voltage according to the error between a feedback voltage based on the second voltage and the lower of a reference voltage and a soft-start voltage that gradually rises during startup, a detection circuit configured to detect when the first voltage has reached a predetermined value or higher, and a release circuit configured to release the short state between the first line and the second line when the detection circuit detects that the first voltage has reached the predetermined value or higher.

[0008] The nonvolatile memory device according to the present disclosure includes the boost circuit having the above configuration. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a diagram showing the configuration of a nonvolatile memory device according to a first embodiment of the present disclosure. [Figure 2] FIG. 2 is a diagram showing the gate-source voltage dependence of the drain current of a data element. [Figure 3] FIG. 3 is a diagram showing an example of voltage application to a memory element during a program operation. [Figure 4] FIG. 4 is a cross-sectional view of the vertical structure of the memory element corresponding to FIG. [Figure 5] FIG. 5 is a diagram showing an example of voltage application to a memory element during a read operation. [Figure 6] FIG. 6 is a cross-sectional view of the vertical structure of the memory element corresponding to FIG. [Figure 7] FIG. 7 is a timing chart showing an example of a drive signal. [Figure 8] FIG. 8 is a time chart of various voltages at startup. [Figure 9] FIG. 9 is a diagram showing the configuration of a nonvolatile memory device according to the second embodiment of the present disclosure.

[0010] [Detailed explanation] First Embodiment 1 is a diagram showing the configuration of a nonvolatile memory device according to a first embodiment of the present disclosure. The nonvolatile memory device 1 according to the first embodiment of the present disclosure (hereinafter referred to as nonvolatile memory device 1) includes a first voltage application unit 10, a boost circuit 11 which is a second voltage application unit, a first data element Md1, a second data element Md2, a switch SW1, and a sense amplifier SA.

[0011] The combination of the first data element Md1 and the second data element Md2 stores data "0" or "1".

[0012] The first data element Md1 and the second data element Md2 are both configured as memory elements, and more specifically, are configured by NMOS transistors (N-channel MOSFETs (Metal-Oxide-Semiconductor Field Effect Transistors)). Memory elements are elements that can perform program operations by changing the characteristics of the transistor through hot carrier injection, and are also called OTP (One Time Programmable) elements. Note that the data elements Md1 and Md2 may be elements other than NMOS transistors as long as they are elements that can perform program operations.

[0013] Here, with respect to transistors, the concept of "structure" includes the size of the transistor. Therefore, for any plurality of transistors, "the same structure" means that the sizes of the plurality of transistors are also the same. When certain transistors have the same structure, if hot carrier injection into the plurality of transistors by a program operation has not been performed on the plurality of transistors, the electrical characteristics (including gate threshold voltage, etc.) of the plurality of transistors will also be the same. However, "the same structure and electrical characteristics of any plurality of transistors" means that they are the same in terms of design, and may actually include errors (i.e., "same" is understood to be a concept that includes errors).

[0014] The nonvolatile memory device 100 can perform a read operation for reading out data stored in the data elements Md1 and Md2, and a program operation (write operation) for rewriting the data (logical values) stored in the data elements Md1 and Md2.

[0015] During the program operation, hot carriers are injected into the data elements Md1 and Md2, changing their electrical characteristics. This change causes the gate threshold voltages of the data elements Md1 and Md2 to rise. In Figure 2, the solid waveform INI represents the gate-source voltage dependence of the drain currents of the data elements Md1 and Md2 before the program operation, and the dotted waveform PRG represents the gate-source voltage dependence of the drain currents of the data elements Md1 and Md2 after the program operation. In this way, the program operation causes the gate threshold voltage Vth to rise.

[0016] Fig. 3 is a diagram showing voltage application to a memory element MT (NMOS transistor) during a program operation. Fig. 4 is a cross-sectional view of the vertical structure of the memory element MT corresponding to Fig. 3. The memory element MT is used for the above-mentioned data elements Md1 and Md2 (Fig. 1).

[0017] As shown in FIGS. 3 and 4, during a program operation, a high voltage Vpp is applied to the gate G of the memory element MT, a high voltage Vpp is applied to the source S, and a ground potential Vss (=0V) is applied to the drain D.

[0018] Such voltage application generates hot carriers (electrons) that flow from the drain D to the source S directly below the gate G, as indicated by the arrows in Fig. 4. The hot carriers are attracted to the high voltage Vpp (positive voltage) applied to the gate G and trapped in the sidewall SSw on the source S side that is provided along the side of the gate G (trapped hot carriers E are shown in Fig. 4).

[0019] Fig. 5 is a diagram showing voltage application to memory elements MT1 and MT2 (NMOS transistors) during a read operation. Fig. 6 is a cross-sectional view of the vertical structure of memory elements MT1 and MT2 corresponding to Fig. 5. Memory elements MT1 and MT2 correspond to the above-mentioned data elements Md1 and Md2 (Fig. 1).

[0020] As shown in Figures 5 and 6, during a read operation, gate voltages Vg1 and Vg2 are applied to the gates G of memory elements MT1 and MT2, drain voltages Vd1 and Vd2 are applied to the drains D, and a ground potential Vs (=0V) is applied to the sources.

[0021] 5 and 6 show, as an example, a case where the memory device MT1 is in a state before a program operation is executed (unprogrammed state) and the memory device MT2 is in a state after a program operation is executed. That is, the memory device MT2 corresponds to the memory device MT shown in FIGS. 3 and 4.

[0022] 6, in the memory element MT2 after the program operation has been performed, hot carriers E are trapped in the sidewall SSw, so the electric field due to the gate voltage Vg2 does not reach directly below the sidewall SSw, and the channel CN2 is cut off on the side of the source S. Therefore, the gate threshold voltage becomes high, and it is difficult for the drain current to flow.

[0023] On the other hand, as shown in FIG. 6, the memory element MT1 in which the program operation is not executed is in the ON state, and a drain current flows.

[0024] During a program operation, the first voltage application unit 10 applies a power supply voltage VDD between the source and drain of each of the data elements Md1 and Md2. The power supply voltage VDD is, for example, +5 V. During a program operation, the boost circuit 11 applies a voltage VP to the gates of each of the data elements Md1 and Md2.

[0025] The boost circuit 11 includes an error amplifier 2, an operational amplifier 3, a PMOS transistor 4, a charge pump circuit 5, a PMOS transistor (switch) 6, level shifters 7 and 8, a drive signal generator 9, capacitors C1 to C4, resistors R1 to R6, constant current sources CS1 to CS3, and lines L1 and L2.

[0026] The constant current source CS1 is connected between the application terminal of the power supply voltage VDD and the first terminal of the capacitor C1. The second terminal of the capacitor C1 is connected to the application terminal of the ground potential. A node N0 to which the constant current source CS1 and the capacitor C1 are connected is connected to the first non-inverting input terminal of the error amplifier 2. A soft-start voltage VSF that gradually rises during startup is generated at the node N0.

[0027] Resistors R1 and R2 are connected in series between a reference voltage VREF and a terminal to which ground potential is applied. The reference voltage VREF is, for example, +2 V and is generated based on a power supply voltage VDD. A node N1 to which the resistors R1 and R2 are connected is connected to a second non-inverting input terminal of the error amplifier 2. A reference voltage REF, which is a divided voltage of the reference voltage VREF, is generated at the node N1.

[0028] Resistors R3 and R4 are connected in series between a line LN1 to which voltage VP is applied and a terminal to which ground potential is applied. A node N2 to which resistors R3 and R4 are connected is connected to the inverting input terminal of an error amplifier 2. A feedback voltage FB, which is a divided voltage of voltage VP, is generated at node N2.

[0029] The charge pump circuit 5 includes inverters 5A to 5C, capacitors 5D to 5F, and NMOS transistors 5G and 5H. The output terminal of the inverter 5A is connected to the gate of the NMOS transistor 5G via a capacitor 5D. The drain of the NMOS transistor 5G (the output terminal of the charge pump circuit 5) is connected to a line LN1 to which a voltage VP is applied. The output terminal of the inverter 5B is connected to the source of the NMOS transistor 5G via a capacitor 5E. The drain of the NMOS transistor 5GH is connected to the source of the NMOS transistor 5G. The output terminal of the inverter 5C is connected to the gate of the NMOS transistor 5H via a capacitor 5F. The drain of the NMOS transistor 5H is connected to the source of the NMOS transistor 5G. The power supply voltage VDD is applied to the source of the NMOS transistor 5H.

[0030] Capacitors 5D and 5F are used for level shifting for switching NMOS transistors 5G and 5H. An internal power supply voltage VREG, which will be described later, is supplied to inverters 5A to 5C. The inverters 5A to 5C are driven based on drive signals output from a drive signal generating unit 9.

[0031] FIG. 7 is a timing chart showing an example of the drive signals SA, SB, and SC input to each of the inverters 5A to 5C. The drive signals SA, SB, and SC are pulse signals. As shown in FIG. 7, after the drive signal SC rises to a high level, the drive signal SB falls to a low level after a delay time D1 has elapsed. Then, the drive signal SA falls to a low level after a delay time D2 has elapsed. After the drive signal SA rises to a high level, the drive signal SB rises to a high level after a delay time D3 has elapsed. Then, the drive signal SC falls to a low level after a delay time D4 has elapsed. By providing this delay time, a dead time (a period when both are simultaneously off) is provided between the NMOS transistors 5G and 5H. By controlling the on / off of the NMOS transistors 5G and 5H, charge accumulates in the capacitor 5E, and the power supply voltage VDD is boosted to the voltage VP. In the configuration of the charge pump circuit 5 shown in FIG. 1, the power supply voltage VDD is boosted by a factor of two. However, the boost factor of the charge pump is not limited to two. Furthermore, the charge pump circuit is not limited to the synchronous rectification type shown in FIG. 1, and may be configured using diodes.

[0032] The output terminal of the error amplifier 2 is connected to a first terminal of a resistor R5 and an inverting input terminal of an operational amplifier 3. The second terminal of the resistor R5 is connected to a first terminal of a capacitor C2. The second terminal of the capacitor C2 is connected to a terminal to which a ground potential is applied. The output terminal of the operational amplifier 3 is connected to the gate of a PMOS transistor 4. The source of the PMOS transistor 4 is connected to a terminal to which a power supply voltage VDD is applied. The drain of the PMOS transistor 4 is connected to the non-inverting input terminal of the operational amplifier 3, a first terminal of a constant current source CS2, and a first terminal of a capacitor C3. The second terminal of the constant current source CS2 and the second terminal of the capacitor C3 are connected to a terminal to which a ground potential is applied. An internal power supply voltage VREG generated at a node N3 to which the operational amplifier 3, the PMOS transistor 4, the constant current source CS2, and the capacitor C3 are connected is supplied to a charge pump circuit 5 and a level shifter 7.

[0033] The error amplifier 2 is a current-output transconductance amplifier. The output terminal of the error amplifier 2 is connected to the line LN3. The error amplifier 2 outputs and receives charge from the line LN3 due to an error current signal corresponding to the difference between the lower of the soft-start voltage VSF supplied to the first non-inverting input terminal and the reference voltage REF supplied to the second non-inverting input terminal and the feedback voltage FB supplied to the inverting input terminal. This generates an error voltage on the line LN3 corresponding to the difference between the lower of the soft-start voltage VSF supplied to the first non-inverting input terminal and the reference voltage REF supplied to the second non-inverting input terminal and the feedback voltage FB supplied to the inverting input terminal. Resistor R5 and capacitor C2 function as a phase compensation unit and cooperate with the error amplifier 2 to generate the error voltage on the line LN3.

[0034] A buffer unit configured by an operational amplifier 3, a PMOS transistor 4, and a constant current source CS2 buffers the error voltage, and the internal power supply voltage VREG is output from the buffer unit.

[0035] The drain of the PMOS transistor 6 is connected to a line LN2 to which a power supply voltage VDD is applied. The source of the PMOS transistor 6 is connected to a line LN1 to which a voltage VP is applied. The gate of the PMOS transistor 6 is connected to the output terminal of a level shifter 7. The level shifter 7 can output the voltage VP or VP minus the gate breakdown voltage of the PMOS transistor 6, and the on / off of the PMOS transistor 6 is controlled by the output of the level shifter 7. The level shifter 7 outputs a voltage corresponding to the result of comparing the internal power supply voltage VREG with a constant voltage Va (e.g., +0.8 V) generated by a constant current source CS3 and a resistor R6. The level shifter 7 turns off the PMOS transistor 6 when the internal power supply voltage VREG is equal to or greater than the constant voltage (e.g., +0.8 V) generated by the constant current source CS3 and the resistor R6. The level shifter 7 turns on the PMOS transistor 6 when the internal power supply voltage VREG is less than the constant voltage (e.g., +0.8 V) generated by the constant current source CS3 and the resistor R6.

[0036] When the PMOS transistor 6 is in the off state, the PMOS transistor 6 releases the short state between the line LN1 to which the voltage VP is applied and the line LN2 to which the power supply voltage VDD is applied, and when the PMOS transistor 6 is in the on state, the PMOS transistor 6 shorts the line LN1 to which the voltage VP is applied and the line LN2 to which the power supply voltage VDD is applied.

[0037] A first terminal of the constant current source CS3 is connected to the terminal to which the power supply voltage VDD is applied. A second terminal of the constant current source CS3 is connected to the first terminal of the resistor R6. A second terminal of the resistor R6 is connected to the terminal to which the ground potential is applied. A first terminal of the capacitor C4 is connected to the line LN1 to which the voltage VP is applied. A second terminal of the capacitor C4 is connected to the terminal to which the ground potential is applied.

[0038] The gates of the data elements Md1 and Md2 are connected to the output terminal of the level shifter 8. The level shifter 8 is capable of outputting a voltage VP or ground potential. The sources of the data elements Md1 and Md2 are connected to a terminal to which the ground potential is applied via a switch SW1. The sources of the data elements Md1 and Md2 are connected to a terminal to which the power supply voltage VDD is applied via a switch SW4. The drain of the first data element Md1 is connected to a terminal to which the ground potential is applied via a switch SW3. The drain of the second data element Md2 is connected to a terminal to which the ground potential is applied via a switch SW2. The sense amplifier SA reads out data based on the magnitude relationship of the drain currents flowing through the data elements Md1 and Md2.

[0039] During program operation, the PMOS transistor 6 is in the off state, and the charge pump circuit 5 is operated by the drive signal generator 9. The error amplifier 2 amplifies the error between the lower of the soft-start voltage VSF supplied to the first non-inverting input terminal and the reference voltage REF supplied to the second non-inverting input terminal, and the feedback voltage FB supplied to the inverting input terminal. As a result, at the beginning of startup, the error between the soft-start voltage VSF and the feedback voltage FB is amplified by the error amplifier 2. The charge pump circuit 5 is controlled so that the feedback voltage FB approaches the soft-start voltage VSF.

[0040] When the soft-start voltage VSF rises and exceeds the reference voltage REF, the error between the reference voltage REF and the feedback voltage FB is thereafter amplified by the error amplifier 2. Therefore, the charge pump circuit 5 is controlled so that the feedback voltage FB approaches the reference voltage REF. The output voltage of the charge pump circuit 5 is controlled to a voltage higher than the power supply voltage VDD; for example, if VDD is +5V, the output voltage of the charge pump circuit 5 after boosting is completed is controlled to +9V.

[0041] After startup, the voltage VP, which is equal to the output voltage of the charge pump circuit 5 after boosting is complete, is applied to the gates of the data elements Md1 and Md2 by the level shifter 8. At this time, switch SW1 is off and SW4 is on. Only the switches SW2 and SW3 corresponding to the data element to be programmed are turned on. As a result, for the data element Md1 or Md2 to be programmed, a high voltage VP is applied to the gate, power supply voltage VDD is applied to the source, and ground potential is applied to the drain. Voltage VP is controlled to a voltage higher than power supply voltage VDD. Therefore, for the data element to be programmed, the voltage applied to the gate (voltage VP) is higher than the source-drain voltage (power supply voltage VDD). Applying a high voltage to the gate improves programming efficiency. Since the gate breakdown voltage is higher than the source-drain breakdown voltage, this does not pose a problem, and the increase in source-drain current is also suppressed. Therefore, there is no need to apply a high voltage between the drain and source, and the programming time required to achieve the same programming depth can be shortened. For example, the programming time can be reduced from 10 ms to 100 μs.

[0042] On the other hand, during a read operation, the PMOS transistor 6 is turned on, and the drive signal generation unit 9 is stopped, thereby stopping the charge pump circuit 5. Therefore, the power supply voltage VDD becomes the voltage VP via the PMOS transistor 6. The voltage VP is applied to the gates of the data elements Md1 and Md2 by the level shifter 8. At this time, the switch SW1 is turned on, and the switches SW2 to SW4 are turned off. As a result, the ground potential is applied to the sources of the data elements Md1 and Md2, and a voltage for the read operation (for example, +0.5 V) is applied to the drains of the data elements Md1 and Md2 by the sense amplifier SA.

[0043] 8 is a time chart of various voltages at the start of the boost circuit 11. At the start timing TM0 of the boost circuit 11, the internal power supply voltage VREG is at ground potential and the PMOS transistor (switch) 6 is on, so the voltage VP matches the power supply voltage VDD. After that, the soft-start voltage VSF gradually increases, but if the lower of the soft-start voltage VSF and the reference voltage REF is lower than the feedback voltage FB, the error amplifier 2 determines that there is no need to increase the feedback voltage FB, so the internal power supply voltage VREG remains at ground potential. Because the internal power supply voltage VREG is at ground potential, the charge pump circuit 5 is stopped.

[0044] Thereafter, at time TM1, when the lower of the soft-start voltage VSF and the reference voltage REF becomes equal to or greater than the feedback voltage FB, the error amplifier 2 determines that the feedback voltage FB needs to be increased, and the internal power supply voltage VREG begins to rise. Then, at time TM2, when the internal power supply voltage VREG becomes equal to or greater than the constant voltage Va, the PMOS transistor (switch) 6 switches from the ON state to the OFF state, and the voltage VP may become higher than the power supply voltage VDD. At this time, the internal power supply voltage VREG has risen to a level that allows the charge pump circuit 5 to operate, and the charge pump circuit 5 begins operating. Therefore, from time TM2 onward, the voltage VP becomes the boosted voltage output from the charge pump circuit 5 and becomes higher than the power supply voltage VDD.

[0045] In other words, the level shifter 7 detects signs of a drop in the voltage VP, and when a sign of a drop in the voltage VP is detected, the short state between the line LN1 and the line LN2 is released by the PMOS transistor (switch) 6, thereby suppressing the drop in the voltage VP.

[0046] However, if the time between timing TM1 and timing TM2 is long, there is a risk that the drop in voltage VP may not be sufficiently suppressed depending on the state of the load connected to line LN1.

[0047] Second Embodiment The nonvolatile memory device according to the second embodiment of the present disclosure is a nonvolatile memory device that can prevent the time between timing TM1 and timing TM2 from becoming long.

[0048] 9 is a diagram showing the configuration of a nonvolatile memory device according to a second embodiment of the present disclosure. A nonvolatile memory device 1X according to the second embodiment of the present disclosure (hereinafter referred to as nonvolatile memory device 1X) differs from the nonvolatile memory device 1 in that resistor R4 is a variable resistor.

[0049] In the nonvolatile memory device 1X, the voltage division ratio of the voltage divider circuit formed by resistors R3 and R4 can be adjusted. For example, the ratio of the feedback voltage FB to the voltage VP when the PMOS transistor (switch) 6 is in the on state can be made larger than the ratio of the feedback voltage FB to the voltage VP when the PMOS transistor (switch) 6 is in the off state. By adjusting the voltage division ratio in this way, the period between timing TM1 and timing TM2 can be shortened, thereby further suppressing the drop in voltage VP.

[0050] <Other> The above-described embodiments should be considered to be illustrative in all respects and not restrictive. The technical scope of the present disclosure is indicated by the claims, not by the description of the above-described embodiments, and should be understood to include all modifications that fall within the meaning and scope equivalent to the claims.

[0051] For example, in the first or second embodiment, it is desirable that the responsiveness of the error amplifier 2 when the PMOS transistor (switch) 6 is in the on state be higher than the responsiveness of the error amplifier 2 when the PMOS transistor (switch) 6 is in the off state. Specifically, it is desirable that the error amplifier 2 is configured to vary the magnitude of its drive current, and that the drive current of the error amplifier 2 when the PMOS transistor (switch) 6 is in the on state be higher than the drive current of the error amplifier 2 when the PMOS transistor (switch) 6 is in the off state. Such a setting regarding the responsiveness of the error amplifier 2 can shorten the period between timing TM1 and timing TM2, thereby further suppressing the drop in voltage VP.

[0052] <Additional Notes> A supplementary note will be provided for the present disclosure, the specific configuration examples of which have been shown in the above-described embodiments.

[0053] The boost circuit (11) of the present disclosure has a configuration (first configuration) including a charge pump circuit (5) configured to generate and output a boosted voltage using a first voltage (VREG), a first line (LN1) connected to the output terminal of the charge pump circuit and configured to apply a second voltage (VP), a second line (LN2) configured to apply a power supply voltage (VDD), a feedback voltage (FB) based on the second voltage, and a voltage generation circuit (2, R5, C2, 3, 4, CS2) configured to generate the first voltage according to the error between the reference voltage (REF) and the lower of a soft start voltage (VSF) that gradually increases at startup, a detection circuit (CS3, R6, 7) configured to detect that the first voltage has reached a predetermined value or higher, and a release circuit (6) configured to release a short state between the first line and the second line when the detection circuit detects that the first voltage has reached the predetermined value or higher.

[0054] According to the boost circuit of the first configuration, the detection circuit detects signs of a drop in the second voltage, and when signs of a drop in the second voltage are detected, the short state between the first line and the second line is released, thereby suppressing the drop in the second voltage.

[0055] The boost circuit of the first configuration may be configured (second configuration) to include a voltage divider circuit (R3, R4) configured to divide the second voltage to generate the feedback voltage and to have an adjustable voltage division ratio.

[0056] In the boost circuit of the second configuration described above, the voltage divider circuit may be configured to make the ratio of the feedback voltage to the second voltage when the release circuit has not released the short state greater than the ratio of the feedback voltage to the second voltage when the release circuit has released the short state (third configuration).

[0057] In the boost circuit of any of the first to third configurations, the voltage generation circuit may include an error amplifier (2) configured to output an error signal corresponding to the error between a feedback voltage based on the second voltage and the lower of a reference voltage and a soft-start voltage that gradually rises at startup, and may be configured (fourth configuration) such that the responsiveness of the error amplifier when the release circuit has not released the short-circuit state is higher than the responsiveness of the error amplifier when the release circuit has released the short-circuit state.

[0058] In the boost circuit of the fourth configuration, a configuration (fifth configuration) may be adopted in which the drive current of the error amplifier when the release circuit has not released the short state is larger than the drive current of the error amplifier when the release circuit has released the short state.

[0059] The nonvolatile memory device (1, 1X) according to the present disclosure has a configuration (sixth configuration) including a boost circuit having any one of the first to fifth configurations. [Explanation of symbols]

[0060] 1. Nonvolatile memory device according to the first embodiment of the present disclosure 1X Nonvolatile memory device according to a second embodiment of the present disclosure 2 Error Amplifier 3 Operational Amplifiers 4 PMOS transistors 5 Charge pump circuit 5A~5C inverter 5D~5F capacitor 5G, 5H NMOS transistors 6 PMOS transistors (switches) 7, 8 Level shifter 9. Drive signal generator 10 First voltage application unit 11 Boost circuit Md1 First data element Md2 Second data element R1~R6 resistance C1~C4 capacitors CS1~CS3 Constant current source SA Sense Amplifier SW1 switch

Claims

1. a charge pump circuit configured to generate and output a boosted voltage using the first voltage; a first line connected to an output terminal of the charge pump circuit and configured to receive a second voltage; a second line configured to have a power supply voltage applied thereto; a voltage generating circuit configured to generate the first voltage according to an error between a feedback voltage based on the second voltage and a reference voltage or a soft-start voltage that gradually increases at startup, whichever is lower; a detection circuit configured to detect when the first voltage is equal to or greater than a predetermined value; a release circuit configured to release a short-circuit state between the first line and the second line when the detection circuit detects that the first voltage has reached or exceeded the predetermined value; A boost circuit comprising:

2. 2. The boost circuit according to claim 1, further comprising a voltage divider circuit configured to divide the second voltage to generate the feedback voltage, the voltage divider circuit having an adjustable voltage division ratio.

3. 3. The boost circuit according to claim 2, wherein the voltage divider circuit is configured to make a ratio of the feedback voltage to the second voltage when the release circuit has not released the short-circuit state larger than a ratio of the feedback voltage to the second voltage when the release circuit has released the short-circuit state.

4. the voltage generating circuit includes an error amplifier configured to output an error signal corresponding to an error between a feedback voltage based on the second voltage and a reference voltage or a soft-start voltage that gradually increases at startup, whichever is lower; 2. The boost circuit according to claim 1, wherein the responsiveness of the error amplifier when the release circuit has not released the short-circuit state is higher than the responsiveness of the error amplifier when the release circuit has released the short-circuit state.

5. 5. The boost circuit according to claim 4, wherein a drive current of said error amplifier when said release circuit has not released said short-circuit state is larger than a drive current of said error amplifier when said release circuit has released said short-circuit state.

6. A nonvolatile memory device comprising the boost circuit according to any one of claims 1 to 5.

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