Capacitor self-checking circuit, charge pump system and self-checking method

Abstract

The invention provides a capacitor self-checking circuit, a charge pump system and a self-checking method. The capacitor self-checking circuit is characterized in that the output end of a charge pump unit is connected with an upper pole plate of a second capacitor through a current source and a first mode switching switch in sequence; the first resistor and the second mode change-over switch are connected in series between the upper pole plate and the lower pole plate of the first capacitor; the second resistor and the third mode change-over switch are connected in series between the upper pole plate of the first capacitor and the ground; the third resistor and the fourth mode change-over switch are connected in series between the upper pole plate of the second capacitor and the ground; the first comparator is connected with the upper and lower polar plates of the first capacitor and outputs a first detection result; and the second comparator is connected with the upper and lower polar plates of the second capacitor and outputs a second detection result. According to the capacitance self-checking circuit and method of the charge pump, detection items are more comprehensive, the detection time is short, the efficiency is high, the power consumption is low, and the cost is low; after the detection is completed, the system can be started immediately without an additional pre-charging link.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and in particular to a capacitor self-checking circuit, a charge pump system and a self-checking method. Background Art

[0002] A charge pump is a DC-DC converter that uses capacitors to store and transfer charge, thereby increasing or decreasing voltage. As one of the core components of a charge pump, capacitor performance directly affects the charge pump's output voltage, efficiency, ripple, and long-term reliability. Therefore, testing the capacitors before use is a critical step in ensuring circuit stability and reliability.

[0003] A method for implementing a capacitor self-checking and soft-starting circuit of a charge pump comprises: independently merging the self-checking and soft-starting circuits of the charge pump in 2:1 charger and 1:1 charger modes, merging the self-checking and soft-starting circuits of the charge pump in 2:1 forward voltage converter and 1:1 forward direct switch mode, and merging the self-checking and soft-starting circuits of the charge pump in 1:2 reverse voltage converter and 1:1 reverse direct switch mode; its main detection items include: CFLY upper and lower plate short circuit detection, CFLY open circuit detection, CBOOT upper and lower plate short circuit detection, CBOOT open circuit detection, and CFLY pre-charging compliance detection. Although the above detection can ensure the stable operation of the charge pump to a certain extent, there are still risks in this solution because ① there is no detection circuit for the short circuit of the lower plate of the CFLY capacitor to the ground; ② during the short circuit detection of the upper and lower plates of CBOOT, the internal charge pump with 3 times the VOUT voltage is required to operate. In the forward 1:1, reverse 1:1, and reverse 1:2 modes, there is no fixed 2 times the VOUT voltage, and a multi-stage internal charge pump is required to boost the voltage. However, a multi-stage charge pump is not required in normal operation, so additional expenses and costs are required; ③ during the short circuit detection of the upper and lower plates of CBOOT, the 30mA pull-down current is too large. If the CBOOT capacitor is short-circuited, it will cause the circuit to burn out; ④ the short circuit detection step of the upper and lower plates of CBOOT is delayed, which will cause the charge of the CFLY capacitor to be discharged during the short circuit detection of the upper and lower plates of CBOOT, resulting in a long detection time and substandard pre-charge conditions.

[0004] Therefore, it is necessary to propose a detection circuit and method with more comprehensive detection items, lower cost, shorter detection time, and no impact on startup, which has become one of the urgent problems to be solved by those skilled in the art.

[0005] It should be noted that the above technical background is merely provided to provide a clear and complete description of the technical solutions of the present invention and to facilitate understanding by those skilled in the art. Simply because these solutions are described in the technical background section of the present invention, it should not be assumed that the above technical solutions are well known to those skilled in the art. Summary of the Invention

[0006] In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a capacitor self-checking circuit, a charge pump system and a self-checking method, which are used to solve the problems of the capacitor detection circuit and method of the charge pump in the prior art, such as incomplete detection items, high cost, long detection time, and impact on startup.

[0007] To achieve the above-mentioned object and other related objects, the present invention provides a capacitor self-checking circuit for checking a first capacitor and a second capacitor connected in series in a charge pump module, wherein the upper plate of the first capacitor is connected to the lower plate of the second capacitor, and the capacitor self-checking circuit includes: a first detection module consisting of at least a first mode switching switch, a second mode switching switch, a third mode switching switch, a fourth mode switching switch, a current source, a charge pump unit, a first resistor, a second resistor, a third resistor, a first comparator, and a second comparator;

[0008] The output end of the charge pump unit is connected to the upper plate of the second capacitor via the current source and the first mode switching switch connected in series;

[0009] The first resistor and the second mode switch are connected in series between the upper plate and the lower plate of the first capacitor;

[0010] The second resistor and the third mode switch are connected in series between the upper plate of the first capacitor and the ground;

[0011] The third resistor and the fourth mode switch are connected in series between the upper plate of the second capacitor and the ground;

[0012] The first input terminal and the second input terminal of the first comparator are respectively connected to the upper plate and the lower plate of the first capacitor and output a first detection result;

[0013] The first input terminal and the second input terminal of the second comparator are respectively connected to the upper plate and the lower plate of the second capacitor and output a second detection result.

[0014] Optionally, the resistance values ​​of the first resistor, the second resistor and the third resistor increase sequentially.

[0015] Optionally, the capacitor self-checking circuit of the charge pump further includes a second detection module; the second detection module is used to detect whether the lower plate of the first capacitor is short-circuited to the ground.

[0016] More optionally, the second detection module includes a fourth resistor, a fifth mode switching switch and a third comparator; the fourth resistor and the fifth mode switching switch are connected in series between the voltage output end of the charge pump module and the lower plate of the first capacitor; the first input end and the second input end of the third comparator are respectively connected to the lower plate of the first capacitor and the first set voltage, and outputs a third detection result.

[0017] To achieve the above objectives and other related objectives, the present invention further provides a charge pump system, the charge pump system comprising at least: a first power switch, N charge pump modules, and N capacitor self-check circuits, wherein N is a natural number greater than or equal to 1;

[0018] One end of the first power switch is connected to the power supply end of the charge pump module, and the other end is connected to the DC bus end;

[0019] Each capacitor self-checking circuit is connected to a charge pump module in a one-to-one correspondence, and detects the capacitor in the corresponding charge pump module;

[0020] The charge pump module includes a first charge and discharge control switch, a second charge and discharge control switch, a third charge and discharge control switch, a fourth charge and discharge control switch, a second power switch, a first capacitor, and a second capacitor;

[0021] The first capacitor and the second capacitor are connected in series, the first charge and discharge control switch is connected between the lower plate of the first capacitor and the ground, the second charge and discharge control switch and the third charge and discharge control switch are connected in series between the upper plate and the lower plate of the first capacitor, the fourth charge and discharge control switch is connected between the power supply end and the lower plate of the second capacitor, the second power switch is connected between the power supply end of the charge pump module and the upper plate of the second capacitor; the intermediate node of the second charge and discharge control switch and the third charge and discharge control switch is connected to the voltage output end.

[0022] Optionally, the capacity of the first capacitor is at least 10 times greater than the capacity of the second capacitor.

[0023] To achieve the above-mentioned object and other related objects, the present invention further provides a charge pump capacitance self-checking method, which is implemented based on the above-mentioned charge pump system. The charge pump capacitance self-checking method comprises: sequentially performing the following steps:

[0024] Step 1) detecting whether the upper and lower plates of the second capacitor are short-circuited, and if the upper and lower plates of the second capacitor are not short-circuited, executing the next step; otherwise, terminating the detection;

[0025] Step 2) detecting whether the first capacitor is open-circuited, and if the first capacitor is not open-circuited, executing the next step; otherwise, terminating the detection;

[0026] Step 3) Detecting whether the upper and lower plates of the first capacitor are short-circuited. If the upper and lower plates of the first capacitor are not short-circuited, the detection ends; otherwise, the detection is terminated.

[0027] Optionally, the method for detecting whether the upper and lower plates of the second capacitor are short-circuited includes: closing the second mode switch, the third mode switch, and the fourth mode switch, and obtaining a voltage on the second capacitor based on a second comparator; if the voltage on the second capacitor is less than a second set voltage, determining that the upper and lower plates of the second capacitor are short-circuited; otherwise, determining that the upper and lower plates of the second capacitor are not short-circuited;

[0028] In which, when working in a 2:1 forward charging mode, the upper plate of the second capacitor is powered by the power supply end; when working in a 1:1 forward charging mode, a 1:2 reverse discharge mode or a 1:1 reverse discharge mode, the upper plate of the second capacitor is powered by the corresponding charge pump unit.

[0029] Optionally, the method for detecting whether the first capacitor is open includes: limiting the current to turn on the first charge and discharge control switch, turning on the third charge and discharge control switch, and obtaining the voltage on the first capacitor based on the first comparator; if the voltage on the first capacitor is greater than the third set voltage, determining that the first capacitor is open; otherwise, determining that the first capacitor is not open.

[0030] More optionally, the method for detecting whether the upper and lower plates of the first capacitor are short-circuited includes: after a set time based on step 2), if the voltage on the first capacitor drops to less than a fourth set voltage, then it is determined that the upper and lower plates of the first capacitor are short-circuited; otherwise, it is determined that the upper and lower plates of the first capacitor are not short-circuited.

[0031] Optionally, when operating in the 2:1 forward charging mode or the 1:2 reverse discharging mode, step 4) is further performed before the detection ends to detect whether the second capacitor is open-circuited. If the second capacitor is not open-circuited, the detection ends; otherwise, the detection is terminated.

[0032] More optionally, the method for detecting whether the second capacitor is open includes: turning on the second charge and discharge control switch, the fourth charge and discharge control switch, and the fourth mode switching switch, obtaining the voltage on the second capacitor based on the second comparator, and if the voltage on the second capacitor is less than the fifth set voltage, then determining that the second capacitor is open; otherwise, determining that the second capacitor is not open; wherein, when the charge pump operates in the 1:2 reverse discharge mode, before turning on the second charge and discharge control switch, the fourth charge and discharge control switch, and the fourth mode switching switch, the first charge and discharge control switch and the second charge and discharge control switch are repeatedly and asynchronously turned on to ensure that the second capacitor has sufficient charging time.

[0033] Optionally, the charge pump capacitance self-checking method further includes executing step 5) after the detection is completed to detect the voltage across the first capacitor to determine whether the pre-charging of the first capacitor meets the standard.

[0034] Optionally, in at least one mode, before performing short-circuit detection on the upper and lower plates of the second capacitor, the method further includes a step of detecting whether the lower plate of the first capacitor is short-circuited to the ground.

[0035] More optionally, the method for detecting whether the lower plate of the first capacitor is short-circuited to the ground includes connecting the output voltage terminal to the lower plate of the first capacitor through a resistor, and monitoring the voltage of the lower plate of the first capacitor. If the voltage of the lower plate of the first capacitor is less than a first set voltage, it is determined that the lower plate of the first capacitor is short-circuited to the ground; otherwise, it is determined that the lower plate of the first capacitor is not short-circuited to the ground.

[0036] As described above, the capacitor self-checking circuit, charge pump system, and self-checking method of the present invention have the following beneficial effects:

[0037] 1. The capacitor self-checking circuit, charge pump system and self-checking method of the present invention add a detection function for whether the lower plate of the CFLY capacitor is short-connected to the ground, which makes the detection items more comprehensive and the reliability higher.

[0038] 2. The capacitor self-check circuit, charge pump system, and self-check method of the present invention eliminate the need to detect an open circuit in the CBOOT capacitor in both the forward 1:1 charging mode and the reverse 1:1 discharging mode, shortening the detection time. In this operating mode, even if the CBOOT capacitor is open, it will not affect the normal operation of the entire circuit (or chip).

[0039] 3. In the capacitor self-checking circuit, charge pump system and self-checking method of the present invention, during the short-circuit detection process of the upper and lower plates of the CBOOT capacitor, the charge pump unit only needs to provide 2 times the VOUT voltage to charge CBOOT, and the charge pump unit required for normal operation can be used without additional overhead.

[0040] 4. In the capacitor self-checking circuit, charge pump system and self-checking method of the present invention, during the short-circuit detection process of the upper and lower plates of the CBOOT capacitor, the pull-down current is limited by the corresponding first charge and discharge control switch, which will not cause damage to the entire circuit (or chip).

[0041] 5. The capacitor self-checking circuit, charge pump system and self-checking method of the present invention realize pre-charging of the CFLY capacitor during the detection process, without the need for a separate pre-charging step, and thus greatly improving efficiency.

[0042] 6. The capacitor self-checking circuit, charge pump system and self-checking method of the present invention move the step of detecting the short circuit between the upper and lower plates of the CBOOT capacitor forward to avoid adverse effects on subsequent normal startup.

[0043] 7. In the capacitor self-checking circuit, charge pump system and self-checking method of the present invention, after the short-circuit detection of the CFLY capacitor, it is possible to ensure that the voltage on the CFLY capacitor reaches the target value. The subsequent open-circuit detection of the CBOOT capacitor only consumes the charge on the CBOOT capacitor (the CBOOT capacitor is a non-power capacitor, usually much smaller than the CFLY capacitor, and a certain voltage drop is normal and has no effect on the circuit operation), and the detection time is short, which will not affect the startup. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 Shown is a structural schematic diagram of the capacitor self-checking circuit and charge pump system of the present invention.

[0045] Figure 2 FIG. 1 is a schematic diagram showing the operation timing of the capacitance self-checking method of the charge pump of the present invention in a 2:1 forward charging mode.

[0046] Figure 3 Schematic diagram showing voltage waveforms at the CFL terminal, the CFH terminal, and the CBT terminal in a 2:1 forward charging mode according to the capacitor self-checking method of the charge pump of the present invention.

[0047] Figure 4 FIG. 1 is a schematic diagram showing the operation timing of the capacitance self-checking method of the charge pump of the present invention in a 1:1 forward charging mode.

[0048] Figure 5 Schematic diagram showing voltage waveforms at the CFL terminal, the CFH terminal, and the CBT terminal in a 1:1 forward charging mode according to the capacitor self-checking method of the charge pump of the present invention.

[0049] Figure 6 FIG. 1 is a schematic diagram showing the operation timing of the capacitance self-checking method of the charge pump of the present invention in a 1:2 reverse charging mode.

[0050] Figure 7Schematic diagram showing voltage waveforms at the CFL terminal, the CFH terminal, and the CBT terminal in a 1:2 reverse charging mode according to the capacitor self-checking method of the charge pump of the present invention.

[0051] Figure 8 FIG. 1 is a schematic diagram showing the operation timing of the capacitance self-checking method of the charge pump of the present invention in a 1:1 reverse charging mode.

[0052] Figure 9 Schematic diagram showing voltage waveforms at the CFL terminal, the CFH terminal, and the CBT terminal in a 1:1 reverse charging mode according to the capacitor self-checking method of the charge pump of the present invention.

[0053] Component number description

[0054] 1. Capacitor self-check circuit

[0055] 1a First capacitor self-check circuit

[0056] 1b Second capacitor self-check circuit

[0057] 11First detection module

[0058] 12 Second detection module

[0059] 2a First charge pump module

[0060] 2b Second charge pump module DETAILED DESCRIPTION

[0061] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0062] See also Figures 1 to 9 It should be noted that the diagrams provided in this embodiment are merely schematic illustrations of the basic concept of the present invention. Therefore, the diagrams only show components related to the present invention and are not drawn according to the number, shape, and size of components in actual implementation. In actual implementation, the type, quantity, and proportion of each component may be changed arbitrarily, and the component layout may also be more complex.

[0063] like Figure 1 As shown, the present invention provides a capacitance self-checking circuit 1 for checking a first capacitor CFLY and a second capacitor CBOOT connected in series in a charge pump module, wherein the upper plate of the first capacitor CFLY is connected to the lower plate of the second capacitor CBOOT. The capacitance self-checking circuit 1 of the charge pump includes a first detection module 11.

[0064] like Figure 1 As shown, the first detection module 11 is used to detect the capacitance in the charge pump module, including a first mode switching switch K1, a second mode switching switch K2, a third mode switching switch K3, a fourth mode switching switch K4, a current source I, a charge pump unit CP, a first resistor R1, a second resistor R2, a third resistor R3, a first comparator CMP1 and a second comparator CMP2.

[0065] Specifically, the output of the charge pump unit CP is connected to the top plate of the second capacitor CBOOT via a current source I and a first mode switch K1 (the order of the two is interchangeable). The first mode switch K1 is controlled by a first switch control signal. The first resistor R1 is connected in series with the second mode switch K2 and connected between the top plate and bottom plate of the first capacitor CFLY. The second mode switch K2 is controlled by a second switch control signal. The second resistor R2 is connected in series with the third mode switch K3 and connected between the top plate of the first capacitor CFLY and ground. The third mode switch K3 is controlled by a third switch control signal. The third resistor R3 is connected in series with the fourth mode switch K4 and connected between the top plate of the second capacitor CBOOT and ground. The fourth mode switch K4 is controlled by a fourth switch control signal. The first input and second input of the first comparator CMP1 are respectively connected to the top plate and bottom plate of the first capacitor CFLY, and outputs a first detection result DET1. The first input terminal and the second input terminal of the second comparator CMP2 are respectively connected to the upper plate and the lower plate of the second capacitor CBOOT, and output a second detection result DET2. In different operating modes, the first detection result can be used to implement open circuit detection and upper and lower plate short circuit detection of the first capacitor CFLY, and the second detection result can be used to implement open circuit detection and upper and lower plate short circuit detection of the second capacitor CBOOT.

[0066] More specifically, in this embodiment, the capacity of the first capacitor CFLY is at least 10 times greater than the capacity of the second capacitor CBOOT, including but not limited to 50 times, 70 times, 100 times, or 150 times greater, as required. In this case, the resistance values ​​of the first resistor R1, the second resistor R2, and the third resistor R3 are set to increase in sequence. As an example, the resistance value of the first resistor R1 is set to 1K, the resistance value of the second resistor R2 is set to 10K, and the resistance value of the third resistor R3 is set to 1M. In actual use, the specific resistance value of each resistor is configured based on the first capacitor CFLY, the second capacitor CBOOT, and test requirements, and is not limited to this embodiment.

[0067] like Figure 1As shown, as another implementation of the present invention, the capacitor self-checking circuit 1 further includes a second detection module 12. The second detection module 12 is used to detect whether the lower plate of the first capacitor CFLY in the charge pump module is short-circuited to the ground.

[0068] Specifically, in this embodiment, the second detection module 12 includes a fourth resistor R4, a fifth mode switch K5, and a third comparator CMP3. The fourth resistor R4 and the fifth mode switch K5 are connected in series and connected between the voltage output terminal OUT and the lower plate of the first capacitor CFLY. The fifth mode switch K5 is controlled by a fifth switch control signal. The first input terminal and the second input terminal of the third comparator CMP3 are respectively connected to the lower plate of the first capacitor CFLY and the first set voltage Vset1, and output a third detection result DET3. The third detection result is used to detect whether the lower plate of the first capacitor CFLY is short-circuited to ground. The resistance value of the fourth resistor R4 can be set as needed. In this example, the resistance value of the fourth resistor R4 is set to 10K.

[0069] like Figure 1 As shown, the present invention further provides a charge pump system, comprising: a first power switch M1, N charge pump modules and N capacitor self-checking circuits 1 of the present invention, wherein N is a natural number greater than or equal to 1.

[0070] Specifically, in this embodiment, N is set to 2, denoted as the first capacitance self-checking circuit 1a, the second capacitance self-checking circuit 1b, and the corresponding first charge pump module 2a and second charge pump module 2b. The components in the first capacitance self-checking circuit 1a and the second capacitance self-checking circuit 1b can be configured with the same parameters or slightly different parameters, as long as they can achieve the capacitance detection function in the corresponding charge pump. A detailed description is omitted here. In actual use, N can be set to 1, 3, or more than 3, and is not limited to this embodiment.

[0071] like Figure 1 As shown, the power supply terminals of the first charge pump module 2a and the second charge pump module 2b are connected together as the power midpoint MIDBUS, and the voltage output terminals OUT (external battery) are connected together and share a common ground. The first terminal of the first power switch M1 is connected to the power midpoint MIDBUS, and the second terminal is connected to the DC bus terminal BUS, and is controlled by the control signal QRB_ON.

[0072] Specifically, in this embodiment, the first power switch M1 is implemented using an NMOS transistor, and the first terminal of the first power switch M1 is a source, the second terminal is a drain, and the control terminal is a gate. In actual use, the corresponding device type can be selected as needed, and is not limited to this embodiment.

[0073] Specifically, each charge pump module (2a, 2b) includes a first charge and discharge control switch Q1, a second charge and discharge control switch Q2, a third charge and discharge control switch Q3, a fourth charge and discharge control switch Q4, a second power switch M2, a first capacitor CFLY and a second capacitor CBOOT; in this embodiment, each charge and discharge control switch and the second power switch are implemented using NMOS tubes. In actual use, the corresponding type of device can be selected as needed, and the applicability of the corresponding connection port can be adjusted. They will not be described one by one here. The upper plate (CFH end) of the first capacitor CFLY is connected to the lower plate (CFH end) of the second capacitor CBOOT; the source of the first charge and discharge control switch Q1 is grounded, and the drain is connected to the lower plate (CFL end) of the first capacitor CFLY; the source of the second charge and discharge control switch Q2 is connected to the lower plate of the first capacitor CFLY, and the drain is connected to the source of the third charge and discharge control switch Q3 and connected to the voltage output end OUT; the drain of the third charge and discharge control switch Q3 is connected to the upper plate of the first capacitor CFLY and the lower plate of the second capacitor CBOOT; the source of the fourth charge and discharge control switch Q4 is connected to the upper plate of the first capacitor CFLY and the lower plate of the second capacitor CBOOT, and the drain is connected to the power midpoint MIDBUS; the source of the second power switch M2 is connected to the power midpoint MIDBUS, and the drain is connected to the upper plate (CBT end) of the second capacitor CBOOT. Among them, the gate of the first charge and discharge control switch Q1 in the first charge pump module 2a receives the control signal QA1, the gate of the second charge and discharge control switch Q2 receives the control signal QB1, the gate of the third charge and discharge control switch Q3 receives the control signal QC1, and the gate of the fourth charge and discharge control switch Q4 receives the control signal QD1; the gate of the first charge and discharge control switch Q1 in the second charge pump module 2b receives the control signal QA2, the gate of the second charge and discharge control switch Q2 receives the control signal QB2, the gate of the third charge and discharge control switch Q3 receives the control signal QC2, and the gate of the fourth charge and discharge control switch Q4 receives the control signal QD2; the gates of the second power switches M2 in both the first charge pump module 2a and the second charge pump module 2b receive the control signal QBT.

[0074] Similarly, the components in the first charge pump module 2a and the second charge pump module 2b can be set to the same parameters or slightly different parameters as long as they can achieve the charge pump function, which will not be described in detail here.

[0075] like Figure 1 As shown, each capacitor self-test circuit is connected to a charge pump module in a one-to-one correspondence and detects the capacitance in the corresponding charge pump module. The structure of each capacitor self-test circuit is described above. In this example, the detection results output by the second capacitor self-test circuit 1b are correspondingly recorded as DET1', DET2', and DET3', which are not detailed here.

[0076] The present invention further provides a charge pump capacitance self-checking method, which is implemented based on the charge pump system of the present invention. The charge pump capacitance self-checking method comprises sequentially performing:

[0077] Step 1) detecting whether the upper and lower plates of the second capacitor CBOOT are short-circuited, and if the upper and lower plates of the second capacitor CBOOT are not short-circuited, executing the next step; otherwise, the detection is terminated;

[0078] Step 2) detecting whether the first capacitor CFLY is open; if the first capacitor CFLY is not open, executing the next step; otherwise, terminating the detection;

[0079] Step 3) Detect whether the upper and lower plates of the first capacitor CFLY are short-circuited. If the upper and lower plates of the first capacitor CFLY are not short-circuited, the detection ends; otherwise, the detection is terminated.

[0080] As an example, the working mode of the charge pump module includes but is not limited to a 2:1 forward charging mode, a 1:1 forward charging mode, a 1:2 reverse discharge mode and a 1:1 reverse discharge mode. As another implementation of the present invention, when working in a 2:1 forward charging mode or a 1:2 reverse discharge mode, step 4) is also performed before the end of the detection to detect whether the second capacitor CBOOT is open. If the second capacitor CBOOT is not open, the detection ends, otherwise, the detection is terminated. At this time, when working in a 2:1 forward charging mode or a 1:2 reverse discharge mode, steps 1), step 2), step 3), and step 4) are performed in sequence; when working in a 1:1 forward charging mode or a 1:1 reverse discharge mode, steps 1), step 2), and step 3) are performed in sequence.

[0081] As another implementation of the present invention, before performing short-circuit detection on the upper and lower plates of the second capacitor CBOOT, a step is also included to detect whether the lower plate of the first capacitor CFLY is short-circuited to the ground; at this time, the output voltage end is connected to the lower plate of the first capacitor CFLY through a resistor, and the voltage of the lower plate of the first capacitor CFLY is monitored. If the voltage of the lower plate of the first capacitor CFLY is less than the first set voltage Vset1, it is determined that the lower plate of the first capacitor CFLY is short-circuited to the ground; otherwise, it is determined that the lower plate of the first capacitor CFLY is not short-circuited to the ground.

[0082] As another implementation of the present invention, the method further includes executing step 5) after the detection is completed to detect the voltage across the first capacitor CFLY to determine whether the pre-charge of the first capacitor CFLY meets the standard.

[0083] The following is a detailed description based on each working mode.

[0084] In 2:1 forward charging mode (power supply voltage VBUS is 2*VOUT):

[0085] Step 10) Detect whether the lower plate of the first capacitor CFLY is short-circuited to the ground. Specifically, Figure 1 and Figure 2 As shown, the first detection enable signal CN_SHORT_TEST_EN is valid, the fifth mode switching switch K5 is closed, and the other switches are in the open state; at this time, the voltage output terminal OUT is short-circuited to the CFL terminal through the fourth resistor R4. After a period of time, at time t0, the third comparator CMP3 detects the voltage of the CFL terminal. If the voltage at the CFL terminal is lower than the first set voltage Vset1, it means that the CFL terminal is short-circuited to the ground, and the detection is terminated (the charge pump cannot work stably). If the voltage at the CFL terminal is higher than the first set voltage Vset1, it means that the CFL terminal is not short-circuited to the ground, and subsequent detection can continue. The first set voltage Vset1 is set based on the voltage when the CFL terminal is actually short-circuited (between 0 and the voltage at the voltage output terminal), which are not listed here one by one. As an example, the first set voltage Vset1 is set to 1.2V. As Figure 3 As shown, in this example, in the initial state, the CFL terminal is 0V, and the voltages on the first capacitor CFLY and the second capacitor CBOOT are both about 3V. Subsequently, under the power supply of the voltage output terminal VOUT, the voltage of the CFL terminal is raised to 3.5V, the CFH terminal is raised to about 8V, and the CBT terminal is raised to about 8.5V; since the CFL terminal voltage is greater than the first set voltage (1.2V), the lower plate of the first capacitor CFLY is not short-circuited to the ground.

[0086] Step 11) Detect whether the upper and lower plates of the second capacitor CBOOT are short-circuited. Specifically, Figure 1 and Figure 2As shown, the first detection enable signal CN_SHORT_TEST_EN jumps to the invalid state, and the fifth mode switch K5 is disconnected; the control signal QRB_ON is valid, and the first power switch M1 is turned on; then the second detection enable signal CBT_PN_SHORT_TEST_EN is valid, the second mode switch K2, the third mode switch K3 and the fourth mode switch K4 are closed, and the remaining switches are in the open state; at this time, the CFH terminal and the CFL terminal are short-circuited through the first resistor R1, the CFH terminal and the ground are short-circuited through the second resistor R2, and the CBT terminal and the ground are short-circuited through the third resistor R3. The CFH terminal is powered by the voltage of the voltage output terminal OUT through the body diode of the third charge and discharge control switch Q3; the CBT terminal is powered by the voltage of the power supply terminal BUS through the first power switch M1 to the power midpoint MIDBUS, and then through the body diode of the second power switch M2. After a period of time, the CBT terminal voltage is approximately equal to 2*VOUT, the CFH terminal voltage is approximately equal to VOUT, and the CFL terminal voltage is approximately equal to the CFH terminal voltage. At time t1, the first comparator CMP1 detects the voltage on the first capacitor CFLY. If the voltage (CBT-CFH) on the second capacitor CBOOT is less than the second set voltage, it means that the upper and lower plates of the second capacitor CBOOT are short-circuited, and the detection is terminated. If the voltage (CBT-CFH) on the second capacitor CBOOT is greater than the second set voltage, it means that the upper and lower plates of the second capacitor CBOOT are not short-circuited, and subsequent detection can continue. The second set voltage is set based on the voltage when the upper and lower plates of the second capacitor are actually short-circuited, and they are not listed here one by one. As an example, the second set voltage is set to 1.2V. Figure 3 As shown in this example, after each switch is actuated, the voltage at the CFL terminal drops to 0V and slowly rises to 4V, the voltage at the CFH terminal drops to 3.5V and remains at 3.5V, and the voltage at the CBT terminal remains at 8.5V. Since the voltage difference between the CBT and CFH terminals is 5V, which is greater than the second set voltage (1.2V), the upper and lower plates of the second capacitor CBOOT are not short-circuited. After the test result is obtained, the second test enable signal CBT_PN_SHORT_TEST_EN jumps to the inactive state, and the second mode switch K2, the third mode switch K3, and the fourth mode switch K4 are disconnected.

[0087] Step 12) Detect whether the first capacitor CFLY is open. Specifically, Figure 1 and Figure 2As shown, the third detection enable signal CF_PRECHG_EN is valid, the control signal QBT is valid, and the second power switch M2 is turned on; the current limiting turns on the first charge and discharge control switch Q1, and the control signals QC1 and QC2 jump to a high level, fully turning on the third charge and discharge control switch Q3, and all switches are disconnected. The voltage at the voltage output terminal OUT forms a charging circuit through the third charge and discharge control switch Q3, the first capacitor CFLY and the first charge and discharge control switch Q1. After a period of time, at time t2, the first comparator CMP1 detects the voltage on the first capacitor CFLY. If the voltage (CFH-CFL) on the first capacitor CFLY is greater than the third set voltage, it means that the first capacitor CFLY is open, and the detection is terminated. If the voltage (CFH-CFL) on the first capacitor CFLY is less than the third set voltage, it means that the first capacitor CFLY is not open, and subsequent detection can continue. The third set voltage is set based on the voltage when the first capacitor is actually open, and they are not listed here one by one. As an example, the third set voltage is set to 2V. Figure 3 As shown, in this example, after the charging loop is formed, the voltage at the CFL terminal slowly decreases, the CFH terminal slightly rises and maintains at around 4.5V, the CBT terminal stabilizes at 8.5V, and at time t2, the CFL terminal is 3V; since the voltage difference between the CFH terminal and the CFL terminal is 1V, which is less than the third set voltage (2V), the first capacitor CFLY is not open.

[0088] Step 11) Detect whether the upper and lower plates of the first capacitor CFLY are short-circuited. Specifically, Figure 1 and Figure 2 As shown, based on step 12), continue to wait, and after the set time, at time t3, the first comparator CMP1 detects the voltage on the first capacitor CFLY. If the voltage on the first capacitor CFLY drops to less than the fourth set voltage, it means that the upper and lower plates of the first capacitor CFLY are short-circuited, and the detection is terminated. If the voltage on the first capacitor CFLY is greater than the fourth set voltage, it means that the upper and lower plates of the first capacitor CFLY are not short-circuited, and subsequent detection can continue. The fourth set voltage is set based on the voltage when the upper and lower plates of the first capacitor are actually short-circuited, and they are not listed here one by one. As an example, the fourth set voltage is set to 2V. Figure 3 As shown, in this example, based on step 12), the voltage at the CFL terminal continues to decrease until it stabilizes at 0V, the CFH terminal stabilizes at 4.5V, and the CBT terminal stabilizes at 8.5V. Since the voltage difference between the CFH terminal and the CFL terminal is 4.5V, which is greater than the fourth set voltage (2V), the upper and lower plates of the first capacitor CFLY are not short-circuited. After obtaining the detection result, the third detection enable signal CF_PRECHG_EN jumps to the inactive state, and the first charge and discharge control switch Q1, the third charge and discharge control switch Q3, and the second power switch M2 are also turned off.

[0089] Step 14) Detect whether the second capacitor CBOOT is open. Specifically, Figure 1 and Figure 2 As shown, the fourth detection enable signal CBT_OPEN_TEST_EN is valid, the control signals QD1, QB1, QD2, and QB2 jump to a high level, the fourth mode switching switch K4 is closed, the second charge and discharge control switch Q2 and the fourth charge and discharge control switch Q4 are turned on, and the CBT end is connected to the ground through the third resistor R3; after a period of time, at time t4, the second comparator CMP2 detects the voltage on the second capacitor CBOOT. If the voltage on the second capacitor CBOOT is less than the fifth set voltage, it means that the second capacitor CBOOT is open, and the detection is terminated. If the voltage on the second capacitor CBOOT is greater than the fifth set voltage, it means that the second capacitor CBOOT is not open, then the detection is completed and the operation can continue. The fifth set voltage is set based on the voltage when the second capacitor is actually open, and they are not listed here one by one. As an example, the fifth set voltage is set to 1.2V. As Figure 3 As shown in this example, after the second charge and discharge control switch Q2 and the fourth charge and discharge control switch Q4 are turned on, the CFL terminal is raised to 4V, the CFH terminal is raised to 8V, and the CBT terminal is raised to 12V. Since the voltage difference between the CBT terminal and the CFH terminal is 4V, which is greater than the fifth set voltage (1.2V), the second capacitor CBOOT is not open-circuited. After the test result is obtained, at time t5, the fourth test enable signal CBT_OPEN_TEST_EN jumps to the invalid state, and the test ends.

[0090] Step 15) After both the short-circuit and open-circuit tests are normal, the voltage across the first capacitor CFLY is detected using the first comparator CMP1 to determine whether the pre-charge of the first capacitor CFLY meets the required level. In this example, this step is performed between time t4 and time t5, after which the charge pump begins operating. In actual use, this step can also be performed after time t5, before the charge pump officially begins operating. This step is not detailed here.

[0091] In 1:1 forward charging mode (power supply voltage VBUS is VOUT):

[0092] Step 20) Detect whether the lower plate of the first capacitor CFLY is short-circuited to the ground. The specific steps are the same as step 10), see Figure 1 and Figure 4 , I will not elaborate on them here. Figure 5As shown, in this example, in the initial state, the CFL terminal is 0V, the CFH terminal and the CBT terminal are both 3.25V, and then under the power supply of the voltage output terminal OUT, the CFL terminal voltage is raised to 2.5V, and the CFH terminal and the CBT terminal are raised to 6.5V; since the CFL terminal voltage is greater than the first set voltage (1.2V), the lower plate of the first capacitor CFLY is not short-circuited to the ground.

[0093] Step 11) Detect whether the upper and lower plates of the second capacitor CBOOT are short-circuited. Specifically, Figure 1 and Figure 4 As shown, the first detection enable signal CN_SHORT_TEST_EN jumps to the invalid state, and the fifth mode switch K5 is disconnected; the control signal QRB_ON is valid, and the first power switch M1 is turned on; then the second detection enable signal CBT_PN_SHORT_TEST_EN is valid, and the first mode switch K1, the second mode switch K2, the third mode switch K3 and the fourth mode switch K4 are closed; at this time, the CFH terminal and the CFL terminal are short-circuited through the first resistor R1, the CFH terminal and the ground are short-circuited through the second resistor R2, and the CBT terminal and the ground are short-circuited through the third resistor R3. The CFH terminal is powered by the voltage of the voltage output terminal OUT through the body diode of the third charge and discharge control switch Q3; the CBT terminal is powered by the charge pump CP (2*VOUT). After a period of time, the voltage of the CBT terminal is approximately equal to 2*VOUT, the voltage of the CFH terminal is approximately equal to VOUT, and the voltage of the CFL terminal is approximately equal to the voltage of the CFH terminal. At time t1, the first comparator CMP1 detects the voltage on the first capacitor CFLY; the specific judgment basis is the same as step 11) and will not be repeated here. Figure 5 As shown, in this example, after each switch is actuated, the CFL terminal drops to 0V, rises to 0.75V and stabilizes for a period of time before dropping to -0.3V, and then slowly rises to 3V; the CFH terminal drops to 3.5V, rises to 4.5V and stabilizes for a period of time before dropping and stabilizing at 3.5V; the CBT terminal rises to 7V, then drops to 5.7V, then slowly rises and stabilizes at 7V; since the voltage difference between the CBT terminal and the CFH terminal is 3.5V, which is greater than the second set voltage (1.2V), the upper and lower plates of the second capacitor CBOOT are not short-circuited.

[0094] Step 12) Detect whether the first capacitor CFLY is open. The specific steps are the same as step 12), see Figure 1 and Figure 4 , I will not elaborate on them here. Figure 5As shown, in this example, after the charging loop is formed, the voltage at the CFL terminal slowly drops from 3.5V, the CFH terminal slightly rises and maintains at around 4V, the CBT terminal drops and stabilizes at 5V, and at time t2, the CFL terminal is 2.5V; since the voltage difference between the CFH terminal and the CFL terminal is 1.5V, which is less than the third set voltage (2V), the first capacitor CFLY is not open.

[0095] Step 23) Detect whether the upper and lower plates of the first capacitor CFLY are short-circuited. When the control signal QC_FULL is low and the control signals QC1 and QC2 are high, the third charge and discharge control switch Q3 is weakly open; when the control signal QC_FULL is high and the control signals QC1 and QC2 are high, the third charge and discharge control switch Q3 is fully open; other steps are similar to step 11), see Figure 1 and Figure 4 , I will not elaborate on them here. Figure 5 As shown, in this example, based on step 12), the voltage at the CFL terminal continues to decrease until it stabilizes at 0V, the CFH terminal stabilizes at about 4V, and the CBT terminal stabilizes at 5V; since the voltage difference between the CFH terminal and the CFL terminal is 4V, which is greater than the fourth set voltage (2V), the upper and lower plates of the first capacitor CFLY are not short-circuited.

[0096] In this working mode, the detection of whether the second capacitor CBOOT is open is not performed.

[0097] Step 25) detects whether the pre-charge of the first capacitor CFLY meets the standard. The specific steps are the same as step 15) and will not be repeated here.

[0098] In 1:2 reverse discharge mode (power supply terminal BUS is connected to load resistor):

[0099] Step 30) Detect whether the lower plate of the first capacitor CFLY is short-circuited to the ground. The specific steps are the same as step 10), see Figure 1 and Figure 6 , I will not elaborate on them here. Figure 7 As shown, in this example, in the initial state, the CFL terminal is 0V, the CFH terminal and the CBT terminal are both 3V, and then under the power supply of the voltage output terminal OUT, the CFL terminal voltage is raised to 2V, and the CFH terminal and the CBT terminal are raised to 5.5V; since the CFL terminal voltage is greater than the first set voltage (1.2V), the lower plate of the first capacitor CFLY is not short-circuited to the ground.

[0100] Step 31) detects whether the upper and lower plates of the second capacitor CBOOT are short-circuited. The specific steps are similar to step 11), except that the control signal QRB_ON remains in an invalid state, and the first power switch M1 is not turned on. Figure 1 and Figure 6 , I will not elaborate on them here. Figure 7 As shown, in this example, after each switch is actuated, the CFL terminal drops to 1V and then rises back to 2V, maintains for a period of time, then drops to 0V, and then slowly rises to 3V; the CFH terminal drops to 4.5V and then rises back to 5.5V, maintains for a period of time, then drops and remains at 3V; the CBT terminal drops to 4.5V and then rises back to 6V, maintains for a period of time, then drops to 4.5V, and then slowly rises to 6V; since the voltage difference between the CBT terminal and the CFL terminal is 3V, which is greater than the second set voltage (1.2V), the upper and lower plates of the second capacitor CBOOT are not short-circuited.

[0101] Step 32) Detect whether the first capacitor CFLY is open. The specific steps are the same as step 12), see Figure 1 and Figure 6 , I will not elaborate on them here. Figure 7 As shown, in this example, after the charging loop is formed, the voltage at the CFL terminal slowly drops from 3V, the CFH terminal slightly rises and maintains at around 3.5V, the CBT terminal drops and stabilizes at around 5V, and at time t2, the CFL terminal is 1.8V; since the voltage difference between the CFH terminal and the CFL terminal is 1.7V, which is less than the third set voltage (2V), the first capacitor CFLY is not open-circuited.

[0102] Step 33) Detect whether the upper and lower plates of the first capacitor CFLY are short-circuited. The specific steps are similar to step 23), see Figure 1 and Figure 6 , I will not elaborate on them here. Figure 7 As shown, in this example, based on step 32), the voltage at the CFL terminal continues to decrease until it stabilizes at 0V, the CFH terminal stabilizes at about 3.5V, and the CBT terminal stabilizes at 5.5V; since the voltage difference between the CFH terminal and the CFL terminal is 3.5V, which is greater than the fourth set voltage (2V), the upper and lower plates of the first capacitor CFLY are not short-circuited.

[0103] Step 34) detects whether the second capacitor CBOOT is open. Specifically, Figure 1 and Figure 6As shown, based on step 33) (the third charge-discharge control switch Q3 is turned on and the voltage at the CFH terminal is equal to VOUT), the control signals QA1 and QA2 are first changed to a high level, turning on the first charge-discharge control switch Q1, grounding the CFL terminal, and charging the first capacitor CFLY. Then, the control signals QD1 and QD2 are changed to a high level, but the control signal QD_FULL is low. The fourth charge-discharge control switch Q4 is weakly turned on, and the CFH terminal charges the power midpoint MIDBUS. Subsequently, the control signal QD_FULL is changed to a high level, fully turning on the fourth charge-discharge control switch Q4, and the voltage at the power midpoint MIDBUS is approximately equal to VOUT. Then QRB_ON is valid. After a period of time, the control signals QD_FULL and QC_FULL jump to low level, the control signals QA1 and QB1 are reverse signals, the control signals QA2 and QB2 are reverse signals, the control signals QA1 and QA2 are reverse signals, the control signals QB1 and QB2 are reverse signals, and they switch repeatedly between high and low levels, so that the first charge and discharge control switch Q1 and the second charge and discharge control switch Q2 in the same charge pump module are repeatedly turned on asynchronously, the switching states of the first charge and discharge control switches Q1 in different charge pump modules are opposite, and the switching states of different charge pump modules are opposite. The switching state of the second charge and discharge control switch Q2 in the charge pump module is also opposite, thereby ensuring that each second capacitor CBOOT has sufficient charging time; then the fourth detection enable signal CBT_OPEN_TEST_EN is valid, and the control signals QD1, QB1, QD2, and QB2 jump to a high level, the fourth mode switching switch K4 is closed, the second charge and discharge control switch Q2 and the fourth charge and discharge control switch Q4 are turned on, and the CBT end is connected to the ground through the third resistor R3; after a period of time, at time t4, the second comparator CMP2 detects the voltage on the second capacitor CBOOT. If the voltage on the second capacitor CBOOT is less than the fifth set voltage, it means that the second capacitor CBOOT is open, and the detection is terminated. If the voltage on the second capacitor CBOOT is greater than the fifth set voltage, it means that the second capacitor CBOOT is not open, then the detection is completed and the operation can continue. The fifth set voltage is set based on the voltage when the second capacitor is actually open, and they are not listed here one by one. As an example, the fifth set voltage is set to 1.2V. Figure 7 As shown, in this example, after the second charge and discharge control switch Q2 and the fourth charge and discharge control switch Q4 are turned on, the CFL terminal is raised to 4V, the CFH terminal is raised to 7V, and the CBT terminal is raised to 10.5V; since the voltage difference between the CBT terminal and the CFH terminal is 3.5V, which is greater than the fifth set voltage (1.2V), the second capacitor CBOOT is not open.

[0104] Step 35) detects whether the pre-charge of the first capacitor CFLY meets the standard. The specific steps are the same as step 15) and will not be repeated here.

[0105] In 1:1 reverse discharge mode (power supply voltage VBUS is VOUT):

[0106] Step 40) Detect whether the lower plate of the first capacitor CFLY is short-circuited to the ground. The specific steps are the same as step 10), see Figure 1 and Figure 8 , I will not elaborate on them here. Figure 9 As shown, in this example, in the initial state, the CFL terminal is 0V, the CFH terminal and the CBT terminal are both 2.7V, and then under the power supply of the voltage output terminal OUT, the CFL terminal voltage is raised to 2V, and the CFH terminal and the CBT terminal are raised to 5.5V; since the CFL terminal voltage is greater than the first set voltage (1.2V), the lower plate of the first capacitor CFLY is not short-circuited to the ground.

[0107] Step 41) detects whether the upper and lower plates of the second capacitor CBOOT are short-circuited. The specific steps are the same as step 31), see Figure 1 and Figure 8 , I will not elaborate on them here. Figure 9 As shown, in this example, after each switch is actuated, the CFL terminal drops to 1V, rises back to 2V and stabilizes for a period of time before dropping to -0.5V, and then slowly rises to 2.5V; the CFH terminal drops to 4.5V, rises back to 5.5V and stabilizes for a period of time before dropping and stabilizing at 3V; the CBT terminal rises to 6V, then drops to 4.5V, then slowly rises and stabilizes at 6.25V; since the voltage difference between the CBT terminal and the CFH terminal is 3.25V, which is greater than the second set voltage (1.2V), the upper and lower plates of the second capacitor CBOOT are not short-circuited.

[0108] Step 42) detects whether the first capacitor CFLY is open. The specific steps are the same as step 12), see Figure 1 and Figure 8 , I will not elaborate on them here. Figure 9 As shown, in this example, after the charging loop is formed, the voltage at the CFL terminal slowly drops from 3V, the CFH terminal slightly rises and maintains at around 3.5V, the CBT terminal drops to 5V and then slowly rises. At time t2, the CFL terminal is 1.7V; since the voltage difference between the CFH terminal and the CFL terminal is 1.8V, which is less than the third set voltage (2V), the first capacitor CFLY is not open.

[0109] Step 43) detects whether the upper and lower plates of the first capacitor CFLY are short-circuited. The specific steps are the same as step 23), see Figure 1 and Figure 8 , I will not elaborate on them here. Figure 9As shown, in this example, based on step 12), the voltage at the CFL terminal continues to decrease until it stabilizes at 0V, the CFH terminal stabilizes at about 3.5V, and the CBT terminal rises to about 6V; since the voltage difference between the CFH terminal and the CFL terminal is 3.5V, which is greater than the fourth set voltage (2V), the upper and lower plates of the first capacitor CFLY are not short-circuited.

[0110] In this working mode, the detection of whether the second capacitor CBOOT is open is not performed.

[0111] Step 45) detects whether the pre-charge of the first capacitor CFLY meets the standard. The specific steps are the same as step 15) and will not be repeated here.

[0112] In summary, the present invention provides a capacitor self-checking circuit, a charge pump system and a self-checking method, wherein the self-checking circuit includes first, second, third and fourth mode switching switches, a current source, a charge pump unit, first, second and third resistors, a first comparator, and a second comparator; the output end of the charge pump unit is connected to the upper plate of the second capacitor via the current source and the first mode switching switch in sequence; the first resistor and the second mode switching switch are connected in series between the upper plate and the lower plate of the first capacitor; the second resistor and the third mode switching switch are connected in series between the upper plate and the ground of the first capacitor; the third resistor and the fourth mode switching switch are connected in series between the upper plate and the ground of the second capacitor; the first input end and the second input end of the first comparator are respectively connected to the upper plate and the lower plate of the first capacitor, and output a first detection result; the first input end and the second input end of the second comparator are respectively connected to the upper plate and the lower plate of the second capacitor, and output a second detection result. The capacitor self-checking circuit and self-checking method of the charge pump of the present invention have more comprehensive detection items, short detection time, high efficiency, low power consumption, low cost, and can be started immediately after the detection is completed without the need for an additional pre-charging link. Therefore, the present invention effectively overcomes various shortcomings of the prior art and has high industrial utilization value.

[0113] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A capacitor self-checking circuit for checking a first capacitor and a second capacitor connected in series in a charge pump module, wherein: The upper plate of the first capacitor is connected to the lower plate of the second capacitor, and the capacitor self-checking circuit includes: a first detection module consisting of at least a first mode switching switch, a second mode switching switch, a third mode switching switch, a fourth mode switching switch, a current source, a charge pump unit, a first resistor, a second resistor, a third resistor, a first comparator, and a second comparator; The output end of the charge pump unit is connected to the upper plate of the second capacitor via the current source and the first mode switching switch connected in series; The first resistor and the second mode switch are connected in series between the upper plate and the lower plate of the first capacitor; The second resistor and the third mode switch are connected in series between the upper plate of the first capacitor and the ground; The third resistor and the fourth mode switch are connected in series between the upper plate of the second capacitor and the ground; The first input terminal and the second input terminal of the first comparator are respectively connected to the upper plate and the lower plate of the first capacitor, and output a first detection result; The first input terminal and the second input terminal of the second comparator are respectively connected to the upper plate and the lower plate of the second capacitor, and outputs a second detection result.

2. The capacitance self-checking circuit according to claim 1, wherein: The resistance values ​​of the first resistor, the second resistor and the third resistor increase in sequence.

3. The capacitance self-checking circuit according to claim 1, wherein: The capacitor self-checking circuit of the charge pump further includes a second detection module; the second detection module is used to detect whether the lower plate of the first capacitor is short-circuited to the ground.

4. The capacitance self-checking circuit according to claim 3, wherein: The second detection module includes a fourth resistor, a fifth mode switching switch and a third comparator; the fourth resistor and the fifth mode switching switch are connected in series between the voltage output end of the charge pump module and the lower plate of the first capacitor; the first input end and the second input end of the third comparator are respectively connected to the lower plate of the first capacitor and the first set voltage, and outputs a third detection result.

5. A charge pump system, characterized in that: The charge pump system comprises at least: a first power switch, N charge pump modules, and N capacitance self-check circuits according to any one of claims 1 to 4, wherein N is a natural number greater than or equal to 1; One end of the first power switch is connected to the power supply end of the charge pump module, and the other end is connected to the DC bus end; Each capacitor self-checking circuit is connected to a charge pump module in a one-to-one correspondence, and detects the first capacitor and the second capacitor in the corresponding charge pump module; The charge pump module includes a first charge and discharge control switch, a second charge and discharge control switch, a third charge and discharge control switch, a fourth charge and discharge control switch, a second power switch, a first capacitor, and a second capacitor; The first capacitor and the second capacitor are connected in series, the first charge and discharge control switch is connected between the lower plate of the first capacitor and the ground, the second charge and discharge control switch and the third charge and discharge control switch are connected in series between the upper plate and the lower plate of the first capacitor, the fourth charge and discharge control switch is connected between the power supply end and the lower plate of the second capacitor, the second power switch is connected between the power supply end of the charge pump module and the upper plate of the second capacitor; and the intermediate node between the second charge and discharge control switch and the third charge and discharge control switch is connected to the voltage output end.

6. The charge pump system according to claim 5, wherein: The capacity of the first capacitor is at least 10 times greater than the capacity of the second capacitor.

7. A method for self-checking capacitance of a charge pump, implemented based on the charge pump system according to any one of claims 5 to 6, characterized in that: The charge pump capacitance self-checking method comprises: performing the following steps in sequence: Step 1) detecting whether the upper and lower plates of the second capacitor are short-circuited, and if the upper and lower plates of the second capacitor are not short-circuited, executing the next step; otherwise, terminating the detection; Step 2) detecting whether the first capacitor is open-circuited, and if the first capacitor is not open-circuited, executing the next step; otherwise, terminating the detection; Step 3) Detecting whether the upper and lower plates of the first capacitor are short-circuited. If the upper and lower plates of the first capacitor are not short-circuited, the detection ends; otherwise, the detection is terminated.

8. The charge pump capacitance self-checking method according to claim 7, wherein: The method for detecting whether the upper and lower plates of the second capacitor are short-circuited includes: closing the second mode switch, the third mode switch, and the fourth mode switch, and obtaining a voltage on the second capacitor based on a second comparator; if the voltage on the second capacitor is less than a second set voltage, determining that the upper and lower plates of the second capacitor are short-circuited; otherwise, determining that the upper and lower plates of the second capacitor are not short-circuited; In which, when working in a 2:1 forward charging mode, the upper plate of the second capacitor is powered by the power supply end; when working in a 1:1 forward charging mode, a 1:2 reverse discharge mode or a 1:1 reverse discharge mode, the upper plate of the second capacitor is powered by the corresponding charge pump unit.

9. The charge pump capacitance self-checking method according to claim 7, wherein: The method for detecting whether the first capacitor is open includes: limiting the current and turning on the first charge and discharge control switch, turning on the third charge and discharge control switch, and obtaining a voltage on the first capacitor based on the first comparator; if the voltage on the first capacitor is greater than a third set voltage, determining that the first capacitor is open; otherwise, determining that the first capacitor is not open.

10. The charge pump capacitance self-checking method according to claim 7, wherein: The method for detecting whether the upper and lower plates of the first capacitor are short-circuited includes: after a set time based on step 2), if the voltage on the first capacitor drops to less than a fourth set voltage, then it is determined that the upper and lower plates of the first capacitor are short-circuited; otherwise, it is determined that the upper and lower plates of the first capacitor are not short-circuited.

11. The charge pump capacitance self-checking method according to claim 7, wherein: When operating in the 2:1 forward charging mode or the 1:2 reverse discharging mode, step 4) is further performed before the end of the detection to detect whether the second capacitor is open-circuited. If the second capacitor is not open-circuited, the detection ends; otherwise, the detection is terminated.

12. The charge pump capacitance self-checking method according to claim 11, wherein: The method for detecting whether the second capacitor is open-circuited includes: turning on the second charge and discharge control switch, the fourth charge and discharge control switch, and the fourth mode switching switch, obtaining a voltage on the second capacitor based on the second comparator, and determining that the second capacitor is open-circuited if the voltage on the second capacitor is less than a fifth set voltage; otherwise, determining that the second capacitor is not open-circuited; wherein, when operating in a 1:2 reverse discharge mode, before turning on the second charge and discharge control switch, the fourth charge and discharge control switch, and the fourth mode switching switch, the first charge and discharge control switch and the second charge and discharge control switch are repeatedly and asynchronously turned on to ensure that the second capacitor has sufficient charging time.

13. The charge pump capacitance self-checking method according to any one of claims 7 to 12, characterized in that: The charge pump capacitance self-checking method further includes executing step 5) after the detection is completed to detect the voltage across the first capacitor to determine whether the pre-charging of the first capacitor meets the standard.

14. The charge pump capacitance self-checking method according to any one of claims 7 to 12, characterized in that: Before performing short-circuit detection on the upper and lower plates of the second capacitor, the method further includes a step of detecting whether the lower plate of the first capacitor is short-circuited to the ground.

15. The charge pump capacitance self-checking method according to claim 14, wherein: The method for detecting whether the lower plate of the first capacitor is short-circuited to the ground includes connecting the output voltage terminal to the lower plate of the first capacitor through a resistor, and monitoring the voltage of the lower plate of the first capacitor. If the voltage of the lower plate of the first capacitor is less than a first set voltage, it is determined that the lower plate of the first capacitor is short-circuited to the ground; otherwise, it is determined that the lower plate of the first capacitor is not short-circuited to the ground.

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