Booster circuit and non-volatile memory device

Abstract

To allow for high-speed startup at low cost.SOLUTION: A booster circuit (11) comprises: a charge pump circuit (5) configured to generate a boost voltage (VP); a comparator (1) configured to compare a first voltage based on the boost voltage with a first reference voltage (VREF1); and an adjustment circuit (2, 9, A1) configured to adjust the boost voltage by determining whether there is a pulse to be supplied to the charge pump circuit according to the comparison results of the comparator. The charge pump circuit is configured to generate the boost voltage using a second voltage (VREG) generated by a regulator (CS1, C1, 3, R3, C2, 4, CS2, C3) having a soft-start function.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a voltage boost circuit and a nonvolatile memory device. [Background technology]

[0002] BACKGROUND ART Conventionally, a charge pump circuit that outputs a boosted voltage is known (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-336753

[0004] [overview] In the case of a charge pump circuit controlled by a regulator, such as the charge pump circuit disclosed in Patent Document 1, the soft start speed must be increased to achieve fast startup. However, increasing the soft start speed requires increasing the speed of the entire system, including the error amplifier in the regulator, which increases costs.

[0005] Furthermore, if there is no or small fluctuation in the load connected to the charge pump circuit, there is no need to increase the response speed of the charge pump circuit and there is no need to speed up the entire system, so speeding up the entire system to achieve fast startup is not desirable from the perspective of the costs mentioned above.

[0006] Charge pump circuits controlled by devices other than a regulator also require a soft start to suppress overshoot in the output of the charge pump circuit. However, the need for additional circuitry to achieve the soft start results in increased costs.

[0007] A boost circuit according to the present disclosure includes a charge pump circuit configured to generate a boosted voltage, a comparator configured to compare a first voltage based on the boosted voltage with a first reference voltage, and an adjustment circuit configured to adjust the boosted voltage by determining whether or not to supply a pulse to the charge pump circuit depending on the comparison result of the comparator, wherein the charge pump circuit is configured to generate the boosted voltage using a second voltage generated by a regulator having a soft start function.

[0008] The nonvolatile memory device according to the present disclosure includes the boost circuit having the above configuration. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a diagram showing the configuration of a nonvolatile memory device according to an embodiment of the present disclosure. [Figure 2] FIG. 2 is a diagram showing the gate-source voltage dependence of the drain current of a data element. [Figure 3] FIG. 3 is a diagram showing an example of voltage application to a memory element during a program operation. [Figure 4] FIG. 4 is a cross-sectional view of the vertical structure of the memory element corresponding to FIG. [Figure 5] FIG. 5 is a diagram showing an example of voltage application to a memory element during a read operation. [Figure 6] FIG. 6 is a cross-sectional view of the vertical structure of the memory element corresponding to FIG. [Figure 7] FIG. 7 is a timing chart showing an example of a drive signal. [Figure 8] FIG. 8 is a time chart of various voltages at startup.

[0010] [Detailed explanation] First Embodiment 1 is a diagram showing the configuration of a nonvolatile memory device according to an embodiment of the present disclosure. The nonvolatile memory device 100 according to an embodiment of the present disclosure (hereinafter referred to as nonvolatile memory device 100) includes a first voltage application unit 10, a boost circuit 11 which is a second voltage application unit, a first data element Md1, a second data element Md2, a switch SW1, and a sense amplifier SA.

[0011] The combination of the first data element Md1 and the second data element Md2 stores data "0" or "1".

[0012] The first data element Md1 and the second data element Md2 are both configured as memory elements, and more specifically, are configured by NMOS transistors (N-channel MOSFETs (Metal-Oxide-Semiconductor Field Effect Transistors)). Memory elements are elements that can perform program operations by changing the characteristics of the transistor through hot carrier injection, and are also called OTP (One Time Programmable) elements. Note that the data elements Md1 and Md2 may be elements other than NMOS transistors as long as they are elements that can perform program operations.

[0013] Here, with respect to transistors, the concept of "structure" includes the size of the transistor. Therefore, for any plurality of transistors, "the same structure" means that the sizes of the plurality of transistors are also the same. When certain transistors have the same structure, if hot carrier injection into the plurality of transistors by a program operation has not been performed on the plurality of transistors, the electrical characteristics (including gate threshold voltage, etc.) of the plurality of transistors will also be the same. However, "the same structure and electrical characteristics of any plurality of transistors" means that they are the same in terms of design, and may actually include errors (i.e., "same" is understood to be a concept that includes errors).

[0014] The nonvolatile memory device 100 can perform a read operation for reading out data stored in the data elements Md1 and Md2, and a program operation (write operation) for rewriting the data (logical values) stored in the data elements Md1 and Md2.

[0015] During the program operation, hot carriers are injected into the data elements Md1 and Md2, changing their electrical characteristics. This change causes the gate threshold voltages of the data elements Md1 and Md2 to rise. In Figure 2, the solid waveform INI represents the gate-source voltage dependence of the drain currents of the data elements Md1 and Md2 before the program operation, and the dotted waveform PRG represents the gate-source voltage dependence of the drain currents of the data elements Md1 and Md2 after the program operation. In this way, the program operation causes the gate threshold voltage Vth to rise.

[0016] Fig. 3 is a diagram showing voltage application to a memory element MT (NMOS transistor) during a program operation. Fig. 4 is a cross-sectional view of the vertical structure of the memory element MT corresponding to Fig. 3. The memory element MT is used for the above-mentioned data elements Md1 and Md2 (Fig. 1).

[0017] As shown in FIGS. 3 and 4, during a program operation, a high voltage Vpp is applied to the gate G of the memory element MT, a high voltage Vpp is applied to the source S, and a ground potential Vss (=0V) is applied to the drain D.

[0018] Such voltage application generates hot carriers (electrons) that flow from the drain D to the source S directly below the gate G, as indicated by the arrows in Fig. 4. The hot carriers are attracted to the high voltage Vpp (positive voltage) applied to the gate G and trapped in the sidewall SSw on the source S side that is provided along the side of the gate G (trapped hot carriers E are shown in Fig. 4).

[0019] Fig. 5 is a diagram showing voltage application to memory elements MT1 and MT2 (NMOS transistors) during a read operation. Fig. 6 is a cross-sectional view of the vertical structure of memory elements MT1 and MT2 corresponding to Fig. 5. Memory elements MT1 and MT2 correspond to the above-mentioned data elements Md1 and Md2 (Fig. 1).

[0020] As shown in Figures 5 and 6, during a read operation, gate voltages Vg1 and Vg2 are applied to the gates G of memory elements MT1 and MT2, drain voltages Vd1 and Vd2 are applied to the drains D, and a ground potential Vs (=0V) is applied to the sources.

[0021] 5 and 6 show, as an example, a case where the memory device MT1 is in a state before a program operation is executed (unprogrammed state) and the memory device MT2 is in a state after a program operation is executed. That is, the memory device MT2 corresponds to the memory device MT shown in FIGS. 3 and 4.

[0022] 6, in the memory element MT2 after the program operation has been performed, hot carriers E are trapped in the sidewall SSw, so the electric field due to the gate voltage Vg2 does not reach directly below the sidewall SSw, and the channel CN2 is cut off on the side of the source S. Therefore, the gate threshold voltage becomes high, and it is difficult for the drain current to flow.

[0023] On the other hand, as shown in FIG. 6, the memory element MT1 in which the program operation is not executed is in the ON state, and a drain current flows.

[0024] During a program operation, the first voltage application unit 10 applies a power supply voltage VDD between the source and drain of each of the data elements Md1 and Md2. The power supply voltage VDD is, for example, +5 V. During a program operation, the boost circuit 11 applies a voltage VP to the gates of each of the data elements Md1 and Md2.

[0025] The boost circuit 11 includes a comparator 1, a latch circuit 2, an error amplifier 3, a PMOS transistor 4, a charge pump circuit 5, a PMOS transistor (switch) 6, level shifters 7 and 8, a drive signal generator 9, capacitors C1 to C4, resistors R1 to R4, constant current sources CS1 to CS3, and an AND gate A1.

[0026] Resistors R1 and R2 are connected in series between a line LN1 to which a voltage VP is applied and a terminal to which a ground potential is applied. A node N0 to which the resistors R1 and R2 are connected is connected to the inverting input terminal of a comparator 1. A divided voltage of the voltage VP is generated at the node N0. A first reference voltage VREF1 is applied to the non-inverting input terminal of the comparator 1.

[0027] The comparator 1 compares the divided voltage of the voltage VP with the first reference voltage VREF1 and supplies the comparison result to the data input terminal of the latch circuit 2. If the divided voltage of the voltage VP is higher than the first reference voltage VREF1, the comparison result of the comparator 1 is a low-level signal, and if the divided voltage of the voltage VP is lower than the first reference voltage VREF1, the comparison result of the comparator 1 is a high-level signal.

[0028] The latch circuit 2 synchronizes with the inverted clock signal CLK and latches the comparison result of the comparator 1. The inverted clock signal CLK is an inverted version of a clock signal, which will be described later.

[0029] AND gate A1 outputs the logical AND of the output of latch circuit 2 and drive signal generator 9. An adjustment circuit formed by the output of latch circuit 2, drive signal generator 9, and AND gate A1 adjusts voltage VP by determining whether or not to supply a pulse to charge pump circuit 5 in accordance with the comparison result of comparator 1. Because the adjustment circuit adjusts voltage VP depending on the presence or absence of a pulse, high-speed startup and high-speed response of boost circuit 11 are possible.

[0030] The constant current source CS1 is connected between the application terminal of the power supply voltage VDD and the first terminal of the capacitor C1. The second terminal of the capacitor C1 is connected to the application terminal of the ground potential. A node N1 to which the constant current source CS1 and the capacitor C1 are connected is connected to the first inverting input terminal of the error amplifier 3. A soft-start voltage VSF that gradually rises during startup is generated at the node N1.

[0031] A second reference voltage VREF2 is supplied to a second inverting input terminal of the error amplifier 3. The value of the second reference voltage VREF2 may be the same as the value of the first reference voltage VREF1, or may be different from the value of the first reference voltage VREF1.

[0032] An internal power supply voltage VREG, which will be described later, is fed back to the non-inverting input terminal of the error amplifier 3. Unlike the present embodiment, a divided voltage of the internal power supply voltage VREG, which will be described later, may be fed back to the non-inverting input terminal of the error amplifier 3.

[0033] The charge pump circuit 5 includes inverters 5A to 5C, capacitors 5D to 5F, and NMOS transistors 5G and 5H. The output terminal of the inverter 5A is connected to the gate of the NMOS transistor 5G via a capacitor 5D. The drain of the NMOS transistor 5G (the output terminal of the charge pump circuit 5) is connected to a line LN1 to which a voltage VP is applied. The output terminal of the inverter 5B is connected to the source of the NMOS transistor 5G via a capacitor 5E. The drain of the NMOS transistor 5GH is connected to the source of the NMOS transistor 5G. The output terminal of the inverter 5C is connected to the gate of the NMOS transistor 5H via a capacitor 5F. The drain of the NMOS transistor 5H is connected to the source of the NMOS transistor 5G. A power supply voltage VDD is applied to the source of the NMOS transistor 5H.

[0034] Capacitors 5D and 5F are used for level shifting for switching NMOS transistors 5G and 5H. An internal power supply voltage VREG, which will be described later, is supplied to inverters 5A to 5C. The inverters 5A to 5C are driven based on the output of an AND gate A1 (a pulse that is the logical product of the drive signal output from the drive signal generation unit 9 and the output of the latch circuit 2). The inverters 5A to 5C receive the output of the AND gate A1 (a pulse that is the logical product of the drive signal output from the drive signal generation unit 9 and the output of the latch circuit 2), use the internal power supply voltage VREG as a power supply voltage, and output an output pulse based on the output of the AND gate A1. Therefore, the lower the internal power supply voltage VREG, the lower the peak value of the output pulses output from the inverters 5A to 5C. The drive signal generating unit 9 generates a drive signal based on a clock signal.

[0035] FIG. 7 is a timing chart showing an example of the drive signals SA, SB, and SC input to each of the inverters 5A to 5C. The drive signals SA, SB, and SC are pulse signals. The drive signal generator 9 outputs, as the drive signal SA, a clock signal supplied to the drive signal generator 9 from, for example, an external source. As shown in FIG. 7, after the drive signal SC rises to a high level, the drive signal SB falls to a low level after a delay time D1 has elapsed. Then, the drive signal SA falls to a low level after a delay time D2 has elapsed. After the drive signal SA rises to a high level, the drive signal SB rises to a high level after a delay time D3 has elapsed. Then, the drive signal SC falls to a low level after a delay time D4 has elapsed. By providing this delay time, a dead time (a period when the NMOS transistors 5G and 5H are simultaneously turned off) is provided between the NMOS transistors 5G and 5H. By controlling the on / off of the NMOS transistors 5G and 5H, charge accumulates in the capacitor 5E, and the power supply voltage VDD is boosted to a voltage VP. The configuration of the charge pump circuit 5 shown in FIG. 1 boosts the power supply voltage VDD by two times. However, the boost factor of the charge pump is not limited to 2. Furthermore, the charge pump circuit is not limited to the synchronous rectification type shown in Figure 1, and may be configured using diodes.

[0036] The output terminal of the error amplifier 3 is connected to a first terminal of a resistor R3 and the gate of a PMOS transistor 4. The second terminal of the resistor R3 is connected to a first terminal of a capacitor C2. The second terminal of the capacitor C2 is connected to a terminal to which a ground potential is applied. The source of the PMOS transistor 4 is connected to a terminal to which a power supply voltage VDD is applied. The drain of the PMOS transistor 4 is connected to a non-inverting input terminal of the error amplifier 3, a first terminal of a constant current source CS2, and a first terminal of a capacitor C3. The second terminals of the constant current source CS2 and the capacitor C3 are connected to a terminal to which a ground potential is applied. An internal power supply voltage VREG generated at a node N2 to which the error amplifier 3, the PMOS transistor 4, the constant current source CS2, and the capacitor C3 are connected is supplied to a charge pump circuit 5 and a level shifter 7.

[0037] The error amplifier 3 is a current-output transconductance amplifier. The output terminal of the error amplifier 3 is connected to the line LN2. The error amplifier 3 inputs and outputs charge from the line LN2 based on an error current signal corresponding to the difference between the lower of the soft-start voltage VSF supplied to the first inverting input terminal and the second reference voltage VREF2 supplied to the second inverting input terminal and the internal power supply voltage VREG supplied to the non-inverting input terminal. This generates an error voltage on the line LN2 corresponding to the difference between the lower of the soft-start voltage VSF supplied to the first inverting input terminal and the second reference voltage VREF2 supplied to the second inverting input terminal and the internal power supply voltage VREG supplied to the non-inverting input terminal. The resistor R3 and the capacitor C2 function as a phase compensation unit and cooperate with the error amplifier 3 to generate the error voltage on the line LN2.

[0038] The circuit formed by the constant current source CS1, capacitor C1, error amplifier 3, resistor R3, capacitor C2, PMOS transistor 4, constant current source CS2, and capacitor C3 is an example of a regulator with a soft start function.

[0039] The drain of the PMOS transistor 6 is connected to a line LN3 to which a power supply voltage VDD is applied. The source of the PMOS transistor 6 is connected to a line LN1 to which a voltage VP is applied. The gate of the PMOS transistor 6 is connected to the output terminal of a level shifter 7. The level shifter 7 can output the voltage VP or VP minus the gate breakdown voltage of the PMOS transistor 6, and the on / off of the PMOS transistor 6 is controlled by the output of the level shifter 7. The level shifter 7 outputs a voltage corresponding to the result of comparing the internal power supply voltage VREG with a constant voltage Va (e.g., +0.8 V) generated by a constant current source CS3 and resistor R4. The level shifter 7 turns off the PMOS transistor 6 when the internal power supply voltage VREG exceeds the constant voltage (e.g., +0.8 V) generated by the constant current source CS3 and resistor R4. The level shifter 7 turns on the PMOS transistor 6 when the internal power supply voltage VREG is less than the constant voltage (e.g., +0.8 V) generated by the constant current source CS3 and resistor R4.

[0040] When the PMOS transistor 6 is in the off state, it releases the short state between the line LN1 to which the voltage VP is applied and the line LN3 to which the power supply voltage VDD is applied, and when the PMOS transistor 6 is in the on state, it shorts the line LN1 to which the voltage VP is applied and the line LN3 to which the power supply voltage VDD is applied.

[0041] A first terminal of the constant current source CS3 is connected to the terminal to which the power supply voltage VDD is applied. A second terminal of the constant current source CS3 is connected to the first terminal of the resistor R4. A second terminal of the resistor R4 is connected to the terminal to which the ground potential is applied. A first terminal of the capacitor C4 is connected to the line LN1 to which the voltage VP is applied. A second terminal of the capacitor C4 is connected to the terminal to which the ground potential is applied.

[0042] The gates of the data elements Md1 and Md2 are connected to the output terminal of the level shifter 8. The level shifter 8 is capable of outputting a voltage VP or ground potential. The sources of the data elements Md1 and Md2 are connected to a terminal to which the ground potential is applied via a switch SW1. The sources of the data elements Md1 and Md2 are connected to a terminal to which the power supply voltage VDD is applied via a switch SW4. The drain of the first data element Md1 is connected to a terminal to which the ground potential is applied via a switch SW3. The drain of the second data element Md2 is connected to a terminal to which the ground potential is applied via a switch SW2. The sense amplifier SA reads out data based on the magnitude relationship of the drain currents flowing through the data elements Md1 and Md2.

[0043] During programming, the PMOS transistor 6 is off, and the drive signal generator 9 activates the charge pump circuit 5. The error amplifier 3 amplifies the error between the lower of the soft-start voltage VSF supplied to the first inverting input terminal and the second reference voltage VREF2 supplied to the second inverting input terminal, and the internal power supply voltage VREG supplied to the non-inverting input terminal. Thus, at the initial stage of startup, the error amplifier 3 amplifies the error between the soft-start voltage VSF and the internal power supply voltage VREG. The charge pump circuit 5 is controlled to limit the amount of charge per charge pump so that the internal power supply voltage VREG approaches the soft-start voltage VSF. Because the voltage VP is generated using the internal power supply voltage VREG generated by a regulator with a soft-start function, there is no need to add additional components to the adjustment circuit, which is composed of the output of the latch circuit 2, the drive signal generator 9, and the AND gate A1, to provide the adjustment circuit with a soft-start function. This eliminates the need for cost reduction in the boost circuit 11.

[0044] When the soft-start voltage VSF rises and exceeds the second reference voltage VREF2, the error between the second reference voltage VREF2 and the internal power supply voltage VREG is thereafter amplified by the error amplifier 3. Therefore, the charge pump circuit 5 is controlled so that the internal power supply voltage VREG approaches the second reference voltage VREF2. The output voltage of the charge pump circuit 5 is controlled to a voltage higher than the power supply voltage VDD; for example, if VDD is +5V, the output voltage of the charge pump circuit 5 after the boosting is completed is controlled to +9V.

[0045] After startup, the voltage VP, which is equal to the output voltage of the charge pump circuit 5 after boosting is complete, is applied to the gates of the data elements Md1 and Md2 by the level shifter 8. At this time, switch SW1 is off and SW4 is on. Only the switches SW2 and SW3 corresponding to the data element to be programmed are turned on. As a result, for the data element Md1 or Md2 to be programmed, a high voltage VP is applied to the gate, power supply voltage VDD is applied to the source, and ground potential is applied to the drain. Voltage VP is controlled to a voltage higher than power supply voltage VDD. Therefore, for the data element to be programmed, the voltage applied to the gate (voltage VP) is higher than the source-drain voltage (power supply voltage VDD). Applying a high voltage to the gate improves programming efficiency. Since the gate breakdown voltage is higher than the source-drain breakdown voltage, this does not pose a problem, and the increase in source-drain current is also suppressed. Therefore, there is no need to apply a high voltage between the drain and source, and the programming time required to achieve the same programming depth can be shortened. For example, the programming time can be reduced from 10 ms to 100 μs.

[0046] On the other hand, during a read operation, the PMOS transistor 6 is turned on, and the drive signal generation unit 9 is stopped, thereby stopping the charge pump circuit 5. Therefore, the power supply voltage VDD becomes the voltage VP via the PMOS transistor 6. The voltage VP is applied to the gates of the data elements Md1 and Md2 by the level shifter 8. At this time, the switch SW1 is turned on, and the switches SW2 to SW4 are turned off. As a result, the ground potential is applied to the sources of the data elements Md1 and Md2, and a voltage for the read operation (for example, +0.5 V) is applied to the drains of the data elements Md1 and Md2 by the sense amplifier SA.

[0047] 8 is a time chart of various voltages at the start of the boost circuit 11. At the start of the boost circuit 11, the internal power supply voltage VREG is at ground potential and the PMOS transistor (switch) 6 is on, so the voltage VP matches the power supply voltage VDD. Thereafter, as the soft-start voltage VSF gradually increases, the internal power supply voltage VREG also gradually increases. Therefore, the peak values of the output pulses output from the inverters 5A to 5C also gradually increase.

[0048] Thereafter, when the soft-start voltage VSF becomes higher than the second reference voltage VREF2, the internal power supply voltage VREG is stabilized so as to approach the second reference voltage VREF2. Therefore, the peak values of the output pulses output from the inverters 5A to 5C are also stabilized to the value of the second reference voltage VREF2.

[0049] <Other> The above-described embodiments should be considered to be illustrative in all respects and not restrictive. The technical scope of the present disclosure is indicated by the claims, not by the description of the above-described embodiments, and should be understood to include all modifications that fall within the meaning and scope equivalent to the claims.

[0050] <Additional Notes> A supplementary note will be provided for the present disclosure, the specific configuration examples of which have been shown in the above-described embodiments.

[0051] The boost circuit (11) of the present disclosure includes a charge pump circuit (5) configured to generate a boosted voltage (VP), a comparator (1) configured to compare a first voltage based on the boosted voltage with a first reference voltage (VREF1), and an adjustment circuit (2, 9, A1) configured to adjust the boosted voltage by determining whether or not to supply a pulse to the charge pump circuit depending on the comparison result of the comparator, and the charge pump circuit is configured to generate the boosted voltage using a second voltage (VREG) generated by a regulator (CS1, C1, 3, R3, C2, 4, CS2, C3) having a soft start function (first configuration).

[0052] The boost circuit of the first configuration described above adjusts the boost voltage depending on whether or not a pulse is present, enabling fast startup and fast response. Furthermore, the boost circuit of the first configuration generates the boost voltage using the second voltage generated by a regulator with a soft-start function, eliminating the need to provide the adjustment circuit with additional components to provide the adjustment circuit with a soft-start function. Therefore, the boost circuit of the first configuration described above can achieve fast startup at low cost.

[0053] In the boost circuit of the first configuration, the regulator may be configured to generate the second voltage according to the error between a third voltage based on the second voltage and the lower of a second reference voltage and a soft-start voltage that gradually increases at startup (second configuration).

[0054] In the boost circuit of the first or second configuration, the charge pump circuit may be configured (third configuration) to include elements (5A to 5C) configured to receive the pulse, use the second voltage as a power supply voltage, and output an output pulse based on the pulse.

[0055] The booster circuit of the third configuration may be configured so that the peak value of the output pulse gradually increases at startup (fourth configuration).

[0056] The nonvolatile memory device (100) according to the present disclosure has a configuration (fifth configuration) including a boost circuit having any one of the first to fourth configurations. [Explanation of symbols]

[0057] 100 Non-volatile memory device according to an embodiment of the present disclosure 1 Comparator 2 Latch circuit 3 Error Amplifier 4 PMOS transistors 5 Charge pump circuit 5A~5C inverter 5D~5F capacitor 5G, 5H NMOS transistors 6 PMOS transistors (switches) 7, 8 Level shifter 9. Drive signal generator 10 First voltage application unit 11 Boost circuit Md1 First data element Md2 Second data element LN1~LN3 lines N0~N2 nodes R1~R4 resistance C1~C4 capacitors CS1~CS3 Constant current source SA Sense Amplifier SW1 switch

Claims

1. a charge pump circuit configured to generate a boosted voltage; a comparator configured to compare a first voltage based on the boosted voltage with a first reference voltage; an adjusting circuit configured to adjust the boosted voltage by determining whether or not to supply a pulse to the charge pump circuit in accordance with a comparison result of the comparator; Equipped with The charge pump circuit is configured to generate the boosted voltage using a second voltage generated by a regulator having a soft start function.

2. 2. The boost circuit according to claim 1, wherein the regulator is configured to generate the second voltage according to an error between a third voltage based on the second voltage and a second reference voltage or a soft-start voltage that gradually increases at startup, whichever is lower.

3. 2. The boost circuit of claim 1, wherein the charge pump circuit includes an element configured to receive the pulse, use the second voltage as a power supply voltage, and output an output pulse based on the pulse.

4. 4. The booster circuit according to claim 3, wherein the peak value of said output pulse gradually increases at startup.

5. A nonvolatile memory device comprising the boost circuit according to any one of claims 1 to 4.

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