Electronic system and method for operating electronic system

Abstract

To provide an electronic system and a method for operating the electronic system in which update operations are not limited by a transmission distance.SOLUTION: An electronic system 100 includes a programmable circuit 110, a memory circuit 120, a controller 130, and a switching circuit 140. The controller provides a first control signal SC1. The switching circuit has a control terminal TC, a first terminal T1, a second terminal T2, and a third terminal T3. The first terminal is coupled to the programmable circuit. The second terminal is coupled to the memory circuit. The control terminal and the third terminal are coupled to the controller. The switching circuit receives the first control signal via the control terminal and connects the second terminal to the third terminal to store update data SUD in the memory circuit.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to electronic systems and methods of operating electronic systems. [Background technology]

[0002] The electronic system can include a controller and a field programmable gate array (FPGA). The controller can update firmware in the FPGA using a transmission method that complies with the Joint Test Action Group (JTAG) specification.

[0003] However, the transmission method conforming to the JTAG specification has a limit on the transmission distance. Generally, the effective transmission distance of the above transmission method is about 1 meter. This means that if the distance between the controller and the FPGA is long, the controller cannot use the above transmission method to update the firmware of the FPGA. Summary of the Invention [Problem to be solved by the invention]

[0004] The present invention provides an electronic system and a method of operating an electronic system that allows remote update operations to be performed on programmable circuitry in the electronic system. [Means for solving the problem]

[0005] The electronic system of the present invention includes a programmable circuit, a memory circuit, a controller, and a switching circuit. The controller provides a first control signal. The switching circuit has a control terminal, a first terminal, a second terminal, and a third terminal. The first terminal is coupled to the programmable circuit. The second terminal is coupled to the memory circuit. The control terminal and the third terminal are coupled to the controller. The switching circuit receives the first control signal via the control terminal and connects the second terminal to the third terminal to store updated data in the memory circuit.

[0006] The operating method of the present invention is used in an electronic system. The electronic system includes a programmable circuit, a memory circuit, a switching circuit, and a controller. The switching circuit has a control terminal, a first terminal, a second terminal, and a third terminal. The first terminal is coupled to the programmable circuit. The second terminal is coupled to the memory circuit. The control terminal and the third terminal are coupled to the controller. The operating method includes the controller providing a first control signal; the switching circuit receiving the control signal via the control terminal and connecting the third terminal to the second terminal; and the controller storing updated data in the memory circuit via the third terminal. [Effects of the Invention]

[0007] Based on the above, the switching circuit receives the update data and writes the update data to the memory circuit. The present invention does not require the controller to update the programmable circuit using a transmission method compliant with the Joint Test Action Group (JTAG) specification. Therefore, the update operation of the present invention is not limited by the transmission distance. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a schematic diagram of an electronic system according to one embodiment of the present invention. [Figure 2] FIG. 2 is a flow diagram of a method of operation according to one embodiment of the present invention. [Figure 3] 1 is a schematic diagram of an electronic system according to one embodiment of the present invention. [Figure 4] FIG. 2 is a flow diagram of a method of operation according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that reference numerals of components referred to in the following description are treated as identical or similar components even when shown in different drawings. These embodiments are merely a part of the disclosure and do not disclose all possible implementations of the present invention. Rather, these embodiments are merely examples within the scope of the claims of the present invention.

[0010] Referring to FIG. 1, FIG. 1 is a schematic diagram of an electronic system according to an embodiment of the present invention. In this embodiment, electronic system 100 includes programmable circuitry 110, memory circuitry 120, controller 130, and switching circuitry 140. For example, electronic system 100 may be, for example, a server rack including multiple servers or a facility including a server rack, although the present invention is not limited thereto. For example, programmable circuitry 110 may be, for example, a field programmable gate array (FPGA) or may be used to configure the boot settings of at least one server in the server rack, although the present invention is not limited thereto.

[0011] In this embodiment, the switching circuit 140 includes a control terminal TC, a first terminal T1, a second terminal T2, and a third terminal T3. The first terminal T1 is coupled to the programmable circuit 110. The second terminal T2 is coupled to the memory circuit 120. The control terminal TC and the third terminal T3 are coupled to the controller 130.

[0012] In this embodiment, the controller 130 controls the connection states between the first terminal T1, the second terminal T2, and the third terminal T3 of the switching circuit 140. The controller 130 provides a first control signal SC1. The switching circuit 140 receives the first control signal SC1 via the control terminal TC. The switching circuit 140 receives update data SUD via the third terminal T3. The switching circuit 140 connects the third terminal T3 and the second terminal T2 in response to the first control signal SC1. Therefore, the switching circuit 140 writes (burns) the received update data SUD into the memory circuit 120 via the third terminal T3.

[0013] In this embodiment, the controller 130 provides a second control signal SC2 based on the fact that the memory circuit 120 has already stored update data SUD. The switching circuit 140 receives the second control signal SC2 via the control terminal TC and connects the second terminal T2 to the first terminal T1. Therefore, the update data SUD stored in the memory circuit 120 is loaded into the programmable circuit 110. Therefore, the programmable circuit 110 can perform an update operation using the update data SUD stored in the memory circuit 120.

[0014] The switching circuit 140 receives the update data SUD via a third terminal T3 and writes the update data SUD to the SUD memory circuit 120. The controller 130 is not connected to the programmable circuit 110 using a transmission method compliant with the Joint Test Action Group (JTAG) specification and then connected to the memory circuit 120, but is connected to the memory circuit 120 via the switching circuit 140. That is, the update data SUD is transmitted to the memory circuit 120 via the switch circuit 140, not to the programmable circuit 110. The programmable circuit 110 receives the update data SUD using a transmission method compliant with the JTAG specification, and does not need to record the update data SUD in the memory circuit 120. Therefore, the update operation performed by the controller 130 on the programmable circuit 110 is not limited by the transmission distance.

[0015] In this embodiment, the controller 130 provides a second control signal SC2. A control terminal TC of the switching circuit 140 receives the second control signal SC2. The switching circuit 140 connects the second terminal T2 and the first terminal T1 in response to the second control signal SC2. Therefore, the programmable circuit 110 is connected to the memory circuit 120 via the switching circuit 140. Therefore, the update data SUD stored in the memory circuit 120 is loaded into the programmable circuit 110.

[0016] In this embodiment, the update data SUD may be provided by the controller 130. In some embodiments, the update data SUD may be provided by other circuits.

[0017] In this embodiment, the controller 130 may provide the first control signal SC1 when the update data SUD is about to be loaded. For example, while the servers in the server rack are operating, the switching circuit 140 writes the received update data SUD to the memory circuit 120. The controller 130 may provide the second control signal SC2 when the update data SUD is being updated and stored in the memory circuit 120 and the programmable circuit 110. For example, the controller may provide the second control signal SC2 when the servers in the server rack are booting. While the servers in the server rack are booting, the programmable circuit 110 performs an update operation using the update data SUD stored in the memory circuit 120.

[0018] In this embodiment, the memory circuit 120 may include an electrically erasable programmable read-only memory (EEPROM) or other storage devices known to those skilled in the art.

[0019] In this embodiment, the controller 130 may include, for example, a Board Management Controller (BMC) for monitoring at least one server rack in the facility.

[0020] Referring simultaneously to FIGS. 1 and 2, FIG. 2 is a flow diagram of an operating method according to an embodiment of the present invention. In this embodiment, the operating method S100 can be used in the electronic system 100. The operating method S100 includes steps S110 to S160. In step S110, the controller 130 provides a first control signal SC1. In step S120, the switching circuit 140 receives the first control signal SC1 via the control terminal TC and connects the third terminal T3 and the second terminal T2. In step S130, the controller 130 stores update data SUD in the memory circuit 120 via the third terminal T3. In step S140, the controller 130 provides a second control signal SC2 based on the memory circuit 120 having already stored the update data. In step S150, the switching circuit 140 receives the second control signal SC2 via the control terminal TC and connects the second terminal T2 and the first terminal T1. In step S160, the update data SUD stored in the memory circuit 120 is loaded into the programmable circuit 110.

[0021] Referring to FIG. 3, FIG. 3 is a schematic diagram of an electronic system according to an embodiment of the present invention. In this embodiment, electronic system 200 includes programmable circuit 210, memory circuit 220, controller 230, switching circuit 240, and converter 250. For example, electronic system 200 may be, for example, a server rack including multiple servers or a facility including a server rack, although the present invention is not limited thereto. For example, programmable circuit 210 may be, for example, a field programmable gate array (FPGA) or may be used to configure the boot settings of at least one server in the server rack, although the present invention is not limited thereto.

[0022] In this embodiment, the switching circuit 240 includes a first terminal T1, a second terminal T2, a third terminal T3, and a control terminal TC. The first terminal T1 is coupled to the programmable circuit 210. The second terminal T2 is coupled to the memory circuit 220. The control terminal TC is coupled to the controller 230. The converter 250 is coupled to the controller 230 and the third terminal T3. More specifically, the converter 250 is coupled to the controller 230 via a first communication protocol FT1 and to the third terminal T3 via a second communication protocol FT2. The converter 250 converts the interfaces of the two different communication protocols. The controller 230 provides update data SUD to the third terminal T3 via the converter 250. The converter 250 receives the update data SUD provided by the controller 230 via the first communication protocol FT1 and provides it to the third terminal T3 of the switching circuit 240 via the second communication protocol FT2. The first communication protocol FT1 is, for example, an Inter-Integrated Circuit (I2C) interface, and the second communication protocol FT2 is, for example, a Serial Peripheral Interface Bus (SPI).

[0023] The controller 230 provides a first control signal SC1. The control terminal TC of the switching circuit 240 receives the first control signal SC1. The switching circuit 240 connects the third terminal T3 to the second terminal T2 in response to the first control signal SC1. Therefore, the switching circuit 240 writes the received update data SUD to the memory circuit 220.

[0024] In this embodiment, the controller 230 can further provide a second control signal SC2. A control terminal TC of the switching circuit 240 receives the second control signal SC2. The switching circuit 240 connects the second terminal T2 to the first terminal T1 in response to the second control signal SC2. Therefore, the programmable circuit 210 is connected to the memory circuit 220 via the switching circuit 240. Therefore, the update data SUD stored in the memory circuit 220 is loaded into the programmable circuit 210.

[0025] In this embodiment, the controller 230 is disposed on a first circuit board CB1. The programmable circuit 210 is disposed on a second circuit board CB2. The controller 230 can update the programmable circuit 210 over a long distance. Therefore, the controller 230 can transmit update data SUD to the converter 250 at a remote location via a bus L1 conforming to an I2C interface, for example. The controller 230 can also be connected to a control terminal TC of the switching circuit 240 via a connection line L2 conforming to a general-purpose input / output (GPIO) communication protocol, for example. Therefore, the controller 230 can control the switching operation of the switching circuit 240 at a remote location via the connection line L2, for example. For example, the first circuit board CB1 including the controller 230 can be disposed at a first location. The second circuit board CB2 including the programmable circuit 210, the memory circuit 220, the switching circuit 240, and the converter 250 can be disposed in equipment at a second location. The distance between the first location and the second location is more than one meter, so the controller 230 performs update operations on the programmable circuit 210 remotely.

[0026] In this embodiment, the first terminal T1 may be connected to the programmable circuit 210 via, for example, a serial peripheral interface bus LSPI1. The second terminal T2 may be connected to the memory circuit 220 via, for example, an SPI bus LSPI2. The converter 250 may be connected to the third terminal T3 via, for example, an SPI bus LSPI3. However, the switching circuit 240 of the present invention is not limited to the above-mentioned connection methods.

[0027] 3 and 4, FIG. 4 is a flow diagram of an operating method according to one embodiment of the present invention. In this embodiment, the operating method S200 is applied to the electronic system 200. The operating method S200 includes steps S210 to S270. In step S210, the controller 230 provides a first control signal SC1. In step S220, the controller 230 provides update data SUD to the third terminal T3 via the converter 250. In step S230, the switching circuit 240 receives the first control signal SC1 through the control terminal TC and connects the third terminal T3 and the second terminal T2. In this embodiment, steps S220 and S230 can be performed simultaneously. In some embodiments, step S220 precedes step S230. In some embodiments, step S220 follows step S230.

[0028] In step S240, the controller 230 stores the update data SUD in the memory circuit 220 via the third terminal T3. In step S250, the controller 230 provides a second control signal SC2 based on the memory circuit 220 already storing the update data. In step S260, the switching circuit 240 receives the second control signal SC2 via the control terminal TC and connects the second terminal T2 and the first terminal T1. In step S270, the update data SUD stored in the memory circuit 220 is loaded into the programmable circuit 210.

[0029] In summary, the switching circuit receives update data and writes the update data to the memory circuit. The present invention does not require the controller to update the FPGA using a transmission method compliant with the JTAG specification. Therefore, the update operation of the present invention is not limited by the transmission distance.

[0030] Although the present invention has been disclosed in the form of embodiments as above, they are not intended to limit the present invention, and those skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope of the attached patent application. [Industrial Applicability]

[0031] The present invention provides an electronic system and a method for operating the electronic system, which can perform remote update operations on the programmable circuit of the electronic system. The update operations performed on the programmable circuit in the present invention are not limited by the transmission distance. [Explanation of symbols]

[0032] 100, 200: Electronic Systems 110, 210: Programmable circuits 120, 220: Memory circuit 130, 230: Controller 140, 240: Switching circuit 250: Converter CB1: First circuit board CB2: Second circuit board FT1: First communication protocol FT2: Second communication protocol L1: A bus compatible with the I2C interface L2: Connection line LSPI1, LSPI2, LSPI3: SPI bus S100, S200: How it works S110~S160, S210~S270: Process SC1: First control signal SC2: Second control signal SUD:Update data T1: First terminal T2: Second terminal T3: Third terminal TC: Control terminal

Claims

1. A programmable circuit; A memory circuit; a controller adapted to provide a first control signal; a switching circuit having a control terminal, a first terminal, a second terminal, and a third terminal, the first terminal being coupled to the programmable circuit, the second terminal being coupled to the memory circuit, and the control terminal and the third terminal being coupled to the controller; Equipped with the switching circuit is adapted to receive the first control signal via the control terminal and connect the second terminal to the third terminal to store updated data in the memory circuit; Electronic systems.

2. the controller further provides the update data, and when the switching circuit receives the first control signal via the control terminal, the update data is stored in the memory circuit via the second terminal and the third terminal. The electronic system of claim 1 .

3. the controller provides a second control signal based on the memory circuit already storing the update data; the switching circuit is adapted to receive the second control signal via the control terminal and to connect the second terminal and the first terminal, thereby loading the update data stored in the memory circuit into the programmable circuit; The electronic system of claim 1 .

4. the programmable circuit comprises a field programmable gate array (FPGA); The electronic system of claim 1 .

5. the controller includes a general-purpose input / output (GPIO) pin, and the controller is coupled to the control terminal of the switching circuit via the GPIO pin; The electronic system of claim 1 .

6. the controller is located on a first circuit board and the programmable circuit is located on a second circuit board; The electronic system of claim 1 .

7. a converter coupled to the controller via a first communication protocol and to the third terminal via a second communication protocol, the controller providing the update data to the third terminal via the converter; further comprising: The electronic system of claim 1 .

8. the first communication protocol includes an Inter-Integrated Circuit (I2C) interface, and the second communication protocol includes a Serial Peripheral Interface (SPI); 8. The electronic system of claim 7.

9. 1. A method of operating an electronic system, comprising: the electronic system includes a programmable circuit, a memory circuit, a switching circuit, and a controller, the switching circuit having a control terminal, a first terminal, a second terminal, and a third terminal, the first terminal coupled to the programmable circuit, the second terminal coupled to the memory circuit, and the control terminal and the third terminal coupled to the controller; The operating method includes: the controller providing a first control signal; the switching circuit receives the first control signal via the control terminal and connects the third terminal and the second terminal; the controller stores update data in the memory circuit via the third terminal; Including, How electronic systems operate.

10. Further comprising an updating operation step, The updating operation step includes: the controller providing a second control signal based on the memory circuit already storing the update data; the switching circuit is adapted to receive the second control signal via the control terminal and connect the second terminal to the first terminal to load the update data stored in the memory circuit into the programmable circuit; Including, 10. The method of claim 9.

11. the electronic system further includes a converter; the converter is coupled to the controller via a first communication protocol and to the third terminal via a second communication protocol; The operating method includes: the controller providing the update data to the third terminal via the converter; further comprising:

10. The method of claim 9.

Images