Multilayer capacitor

Abstract

To provide a multilayer capacitor with improved material properties and improved geometry.SOLUTION: A multilayer capacitor 1 includes multiple capacitor elements 2 each having at least two segments 2A, 2B. Each segment includes ceramic dielectric layers 5 and different electrodes 3, 4 each arranged between the dielectric layers. The different electrodes overlap in active regions 9A but not in passive regions 9B. Multiple segments are arranged one above the other in a stack direction. The outermost dielectric layers form a connection region 12 in which the segments are fixedly connected to each other parallel to layer planes. A stress relief region 13 in the connection region occupies at least the entire passive region. The multiple capacitor elements are connected to each other so as to be assembled and disassembled at contact surfaces.SELECTED DRAWING: Figure 16

Description

[Technical Field]

[0001] The present invention relates to a ceramic-based multilayer capacitor including dielectric layers and electrodes disposed therebetween. [Background technology]

[0002] Examples of stacked capacitors are known to those skilled in the art from the prior art.

[0003] In ceramic-based multilayer capacitors having piezoelectric properties, application of a capacitor voltage generally causes deformation of the electroceramic material.

[0004] Cyclic deformation can lead to material fatigue and consequent failure of the ceramic material.

[0005] Furthermore, known multilayer capacitors present various additional technical challenges in use. Summary of the Invention [Problem to be solved by the invention]

[0006] SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a multilayer capacitor having improved material properties and an improved geometry. [Means for solving the problem]

[0007] The problem is at least partly solved by the multilayer capacitor disclosed in claim 1.

[0008] Further embodiments can be seen from the further claims.

[0009] A multilayer capacitor is disclosed that includes a capacitor element having at least two segments, each having a ceramic dielectric layer and an electrode layer disposed therebetween, the electrode layers being arranged one above the other in a layered order, where the electrode layers include different electrodes, including at least a first and a second electrode.

[0010] Different electrodes, i.e., the first and second electrodes, overlap in active areas. Areas where different electrodes do not overlap are called passive areas.

[0011] In the passive region, for example, only electrodes of the same type, ie only first electrodes or only second electrodes or any other uniform type, overlap.

[0012] Additionally or alternatively, a passive region can be a region of the capacitor element where no electrodes are located, such as a peripheral region adjacent to the outer surface of the capacitor element, since the electrodes often do not extend across the entire width of the capacitor element.

[0013] The capacitor element includes a plurality of segments stacked in the stacking direction, and the outermost dielectric layers of two segments form a bonding region where the segments are firmly bonded to each other parallel to the layer plane, for example, by the bottom dielectric layer of the upper segment and the top dielectric layer of the lower segment.

[0014] The two dielectric layers are firmly bonded to one another, for example, by sintering. By sintering the overlapping segments together, the adjacent dielectric layers are physically and chemically bonded to one another.

[0015] Any number of segments may be bonded together, with one bonded region formed between every two segments.

[0016] The bonding region includes a stress relief region disposed in a plane parallel to the electrodes, the stress relief region occupying at least the entire passive area of the capacitor.

[0017] In the stress relief region, the bond between the segments is weakened or interrupted, and the stress relief region keeps the mechanical stresses within the stacked capacitor low, preferably such that the thickness of the segments is small enough that the mechanical stresses within the segments do not lead to cracks in the capacitor.

[0018] Preferably, this weakening is significant in the stacking direction corresponding to the magnetic field direction of the capacitor. The weakening can be achieved by forming gaps or by using a material with a different elastic modulus, preferably a material with a lower elastic modulus value. Alternatively, the weakening can be achieved by inserting a material that is harder or more brittle compared to the ceramic. When a load is applied, this material may break.

[0019] Such mechanical stresses occur, for example, when a capacitor voltage is applied. In particular, mechanical stresses can be expected between the active and passive areas, since they are electrically loaded differently. If no stress relief regions were provided inside the capacitor, such voltages would add up unimpeded across the entire capacitor.

[0020] The weakening or interruption of the bond between the segments prevents mechanical stresses, especially in the passive areas, from being added in a way that could cause breaks or cracks in the capacitor.

[0021] In one embodiment, the stress relief regions are formed as regions parallel to the layer plane between the segments, in which the segments are not rigidly bonded to one another.

[0022] This makes it possible to easily achieve the aforementioned weakening of the bonds between the segments.

[0023] In one embodiment, the stress relief zone is structured, in particular it can have at least one recess, for example in which a bonding zone is formed, in which the segments are firmly bonded to one another, in particular firmly sintered to one another.

[0024] In one embodiment, the stress relief regions are formed as gaps between the segments.

[0025] In particular, the dielectric layers of different segments can be separated from one another in the stress relief region, and the dielectric layers can be adjacent to one another in the stress relief region and not bonded to one another, or only partially bonded, or bonded only with reduced adhesive strength.

[0026] In at least one embodiment, the width of the gap between the segments is less than the thickness of the dielectric layer. The individual layer planes of the capacitor element typically each have the same layer thickness.

[0027] In one embodiment of the stacked capacitor, the stress relief region comprises a material whose modulus of elasticity is different from the modulus of elasticity of the dielectric layer.

[0028] To manufacture a multilayer capacitor, green sheets, particularly ceramic green sheets, are prepared to form dielectric layers. A first paste, e.g., including an organic or inorganic material, is applied, e.g., printed, onto at least one green sheet that will later form the outer dielectric layer of the segment. The first paste is preferably applied only to the areas where the stress relief regions will be provided.

[0029] A second metal paste for the electrode material is printed onto another green sheet that will later form the inner dielectric layer of the segment. The printing and layering can be done so that the electrodes in the stack are applied alternately and slightly offset from each other, so that they can later be brought into contact, in a comb-like pattern, on one side of each outlet face.

[0030] The green sheets are arranged to form a laminate, and the laminate is sintered. Preferably, the first paste is formed to completely or partially prevent co-sintering of the dielectric layers at the location where the first paste is applied, thereby forming a stress relief region thereat.

[0031] The layered and pressed laminate can then be subdivided into individual capacitors for a mass production process.

[0032] After cutting, the binder is first baked out of the separated capacitors (debinding). This is followed by a firing process (sintering). In this process, the ceramic powder is sintered at temperatures preferably between 900°C and 1200°C to obtain its final, mainly crystalline structure. The individual dielectric layers bond together during the process to form a monolithic structure. The dielectric layers of overlapping segments are also firmly bonded to each other.

[0033] It is only through this firing process that the ceramic acquires its desired dielectric properties. The firing process is followed by a cleaning step and, in at least one embodiment, the application of external contacts.

[0034] In one embodiment, stress relief regions are formed in at least all areas adjacent to the outer surface of the capacitor element.

[0035] In one embodiment, the depth that the stress relief region extends from the outer surface into the capacitor element is approximately equal to the stack height of the segments adjacent to the stress relief region, or the dimension between the top and bottom electrodes in the adjacent segments. Adjacent segments typically each have the same stack height.

[0036] In a further embodiment, the depth of the passive region on the outer surface of the capacitor is approximately equal to the stack height of adjacent segments.

[0037] The depth of the stress relief region from the outer surface into the capacitor element is, in one embodiment, twice the depth of the passive region on the outer surface of the capacitor, and therefore depends on the depth of the passive region.

[0038] Such dimensions of the stress relief region prevent mechanical stresses from being applied in such a way that cracks or similar fatigue phenomena occur in the capacitor.

[0039] Additionally or alternatively, the stress relief region may, in one embodiment, include further sections that are not formed directly on the outer surface of the capacitor element. The dimensions of the stress relief region should again correspond at least to the dimensions set forth in the previous paragraph.

[0040] In one embodiment, the stress relief regions are at least partially located in the areas where different electrodes overlap, i.e., the stress relief regions are formed at least partially in the active areas of the capacitor elements.

[0041] The stress relief region in this embodiment further includes all areas of the bonding region that are disposed on the passive region of the capacitor element.

[0042] Such an enlarged stress relief region further reduces the mechanical stress between the individual segments.

[0043] In one embodiment, the stress relief region has at least one section that is not adjacent to the outer surface of the capacitor element.

[0044] In one embodiment, the bond region includes a plurality of stress relief regions bounded by one another.

[0045] In one embodiment, the bond region includes a plurality of stress relief regions bounded by one another, at least in part not adjacent to the outer surface of the capacitor element.

[0046] The last three embodiments are particularly advantageous when the capacitor diameter is large.

[0047] Such an enlarged stress relief region or multiple stress relief regions within a bonded region further reduces mechanical stresses between the individual segments.

[0048] In one embodiment of the stacked capacitor, the first and second electrodes at least partially overlap.

[0049] In the overlapping region, the first and second electrodes form an active area in which an electric field acts and thus a mechanical stress is generated within the dielectric layer.

[0050] In one embodiment, the electrodes comprise one or more of the group consisting of copper, silver, nickel, platinum, and palladium. These metals are suitable, among other things, because of their high electrical conductivity.

[0051] For ease and cheap manufacturing, it is preferable to sinter the entire stacked capacitor in one step, as mentioned above, so the sintering process is carried out after the individual layers have been stacked.

[0052] To enable such a method, the sintering temperature of the ceramic used in the dielectric layer must not exceed the melting temperature of the metal used in the electrodes, which can be achieved by selecting the appropriate electrode metal or the appropriate ceramic.

[0053] In at least one embodiment, two separate external contacts for contacting the first and second electrodes are applied to the exit surface on the outer surface of the capacitor element, on which the electrodes exit the capacitor element.

[0054] The external contacts are preferably applied to opposite outer surfaces of the stacked capacitor.

[0055] A possible third or further electrode, on the other hand, is not contacted by an external contact.

[0056] In one embodiment of the stacked capacitor, each segment includes at least three different types of electrode layers, where a first electrode layer has first and second electrodes formed opposite each other and separated by a dielectric section, a second electrode layer has only the first electrode formed therein, and a third electrode layer has only the second electrode formed therein, and the first electrode layers form the outermost electrode layers in the stacking direction of each segment, respectively.

[0057] The first and second electrodes face each other in a direction perpendicular to the stacking direction of the multilayer capacitor in the first electrode layer, and a dielectric layer is formed between the electrode layers.

[0058] An advantage of the above-described embodiment is that no electric field is generated in the outer sections of the segments or between the two segments, because the first and second electrodes each have the same electric polarization as the adjacent outer contacts.

[0059] Furthermore, the electrodes of the first electrode layer are partially adjacent to electrodes of the same electric polarization even within the segment, so that no electric field is formed over a relatively large area, and therefore the individual layers within the active area of the segment also have no electric field.

[0060] Therefore, the unwanted migration of charged particles from the outside to the inside of the capacitor can be avoided, which has the advantage of higher stability against moisture-induced material changes.

[0061] In one embodiment, the stacked capacitor includes at least one third electrode layer that is not in contact with any of the external contacts, the third electrode layer overlapping the first and second electrodes.

[0062] Such electrodes are also called "floating" electrodes ("schwebende" electrodes in German).

[0063] In one embodiment, the stacked capacitor includes at least one third electrode that is not adjacent to any of the outer surfaces of the capacitor elements.

[0064] Preferably, the multilayer capacitor, and in particular each segment of the multilayer capacitor, has a number of first electrodes, a number of second electrodes, and a number of third electrodes.

[0065] In one embodiment, the capacitor has at least one series connection of two capacitances, in particular, a first capacitance formed by overlapping at least one first electrode with at least one third electrode, and a second capacitance formed by overlapping at least one second electrode with at least one third electrode.

[0066] In one embodiment, the stacked capacitor includes an additional electrode located in a passive region of the capacitor and not overlapping the electrode of the opposite polarity.

[0067] Therefore, no electric field is generated between these electrodes, and such electrodes are called passive or dummy electrodes.

[0068] Such dummy electrodes typically reduce mechanical stresses that occur within the capacitor element between areas with electrodes and areas without electrodes.

[0069] Therefore, the combined use of dummy electrodes and stress relief regions can minimize mechanical stresses within the stacked capacitor and improve the robustness of the capacitor, thereby optimizing the thermomechanical and electrical load capability of the stacked capacitor.

[0070] In a further embodiment, the external contact comprises multiple sputtered layers, including layers of chromium, nickel, and at least one of silver or gold, applied in that order onto the exit face.

[0071] The chromium layer applied directly onto the exit surface allows the sputtered layer to adhere well to the exit surface. The silver or gold layer has high electrical conductivity and therefore serves primarily to provide electrical contact between the electrodes. By means of the sputtered layer, all electrodes of one type can be electrically connected to each other and thus connected in parallel.

[0072] The nickel intermediate layer acts as a diffusion barrier.

[0073] For example, all of the first electrodes emerging from the capacitor elements on the same first side can be electrically connected to each other via a first sputtered layer, and all of the second electrodes emerging from the second side can be electrically connected or connected in parallel via a further second sputtered layer, so that, for example, the entire stack including all of the first electrodes and all of the second electrodes forms a single stacked capacitor.

[0074] In one embodiment, the external contacts further include a fine copper grid applied over the sputtered layer.

[0075] The copper grid covers the entire sputtered layer and can therefore avoid the formation of cracks in the sputtered layer or even its spalling in the event of mechanical deformation of the capacitor element.

[0076] In one embodiment, the external contacts further comprise a metal sheet through which the capacitor element is contacted to the outside, the metal sheet being attached on top of the sputtered layer.

[0077] In one embodiment, the metal sheet is attached onto the sputtered layer by a soldered connection.

[0078] In a further embodiment, the metal sheet is coated with a sintered silver layer over the sputtered layer.

[0079] The sputtered layer described above typically has a thickness in the nanometer range, while the silver layer has a thickness in the micrometer range. Such a sintered silver layer covering the entire sputtered layer binds the sputtered layer together when the capacitor element is deformed, thereby preventing, for example, the sputtered layer from peeling off.

[0080] The silver layer also secures the metal sheet to the sputtered layer, so no additional soldering is required. For this purpose, silver is applied to the sputtered layer, and the metal sheet is placed directly on top of it. Only after the metal sheet is placed is the silver layer sintered at the lowest possible pressure.

[0081] In at least one embodiment, the silver layer is sintered at a low pressure such that a residual porosity of about 35% is achieved.

[0082] Such porosity is small enough to only slightly reduce the electrical and thermal conductivity of silver. Due to its high electrical and thermal conductivity, the silver layer also allows for good electrical connection to the sputtered layer of the metal sheet. However, in addition, silver with the above-mentioned porosity has a sufficiently high ductility to ensure thermomechanical stress relaxation.

[0083] Furthermore, sintered silver layers exhibit less material fatigue when subjected to mechanical or thermomechanical loads compared to, for example, soldered layers.

[0084] Since the process temperatures for sintering are generally lower than for soldering, furthermore, lower thermomechanical stresses are generated and the process is relatively easy and cheap to carry out.

[0085] The high melting point of the sintered silver, up to 962° C. for pure silver, ensures high temperature stability of the silver layer, which allows further process steps at high temperatures.

[0086] In one embodiment, the metal sheet includes two copper layers with an Invar layer disposed therebetween.

[0087] Copper has particularly good electrical and thermal conductivity.

[0088] An iron-nickel alloy with approximately one-third nickel and two-thirds iron is called Invar. This material has a particularly low coefficient of thermal expansion, in particular, close to that of ceramics. In combination with copper, sufficient electrical conductivity of the connection contacts can be ensured despite the low electrical conductivity of Invar.

[0089] Instead of Invar, other iron-nickel or iron-nickel-cobalt alloys may be used.

[0090] To manufacture the above-mentioned metal sheet, for example, a copper layer is laid down on an Invar sheet.

[0091] The outer surface of the copper layer may be silver plated to improve the connection between the copper and the sintered silver layer. In one embodiment, the silver plating is applied by electroplating.

[0092] In one embodiment, the metal sheet of the external contacts comprises a copper layer having a serpentine geometry.

[0093] A copper layer is applied directly on the silver layer. The copper layer preferably has a serpentine lattice-like geometric shape. The copper layer can also be silver-plated. The silver plating is preferably performed by electroplating. The copper layer can be sintered directly with the silver layer.

[0094] Copper is preferably used for the external contacts of the capacitor due to its excellent thermal and electrical conductivity.

[0095] In one embodiment, the stacked capacitor comprises separable capacitor elements that can be optionally assembled and disassembled with contact surfaces that are oriented perpendicular to the layer planes and external contacts.

[0096] Therefore, multilayer capacitors of any size can be flexibly constructed. The capacitor elements described above can be mass-produced in standardized sizes and then assembled as required.

[0097] The fixing of the individual capacitor elements can be achieved, for example, via a sintered silver layer attached to the outer surface, which silver layer extends over the outer surfaces of all the capacitor elements and thus binds them together.

[0098] In one embodiment, the ceramic is an antiferroelectric.

[0099] The dielectric layers can exhibit piezoelectric or electrostrictive behavior, resulting in deformation of the layers when a voltage is applied to the stacked capacitor.

[0100] In one embodiment, the ceramic comprises lead zirconate titanate, which typically crystallizes in the perovskite structure. Such ceramics are antiferroelectrics that can be advantageously used in the stacked capacitors described above.

[0101] In one embodiment, the ceramic has the following composition, which has advantageous properties when used in a capacitor: Pb (y-1.5a-0.5b+c+0.5d-0.5e-f) Ca a A b (Zr 1-x Ti x ) (1-c-d-e-f) E c Fe d Nb e W f O3 wherein A is selected from the group consisting of Na, K, and Ag; E is selected from the group consisting of Cu, Ni, Hf, Si, and Mn; and 0.05≦x≦0.3; 0 <a<0.14; 0 ≤ b ≤ 0.12; 0 ≤ c ≤ 0.12; 0 ≤ d ≤ 0.12; 0 ≤ e ≤ 0.12; 0 ≤ f ≤ 0.12; 0.9≦y≦1.5, and 0.001 <b+c+d+e+f holds true.

[0102] The above-mentioned ceramics have a low sintering temperature of 900° C. to 1200° C. Furthermore, ceramics are characterized by high stability and low material fatigue.

[0103] In one embodiment, the ceramic has the following composition, which has similar advantageous properties when used in a capacitor: Pb (1-1.5a-0.5b+1.5d+e+0.5f) A a E b (Zr 1-x Ti x ) (1-c-d-e-f) Li d G e Fef Si c O3+ y PbO where: A is selected from the group consisting of La, Nd, Y, Eu, Gd, Tb, Dy, Ho, Er, and Yb; E is selected from the group consisting of Na, K, and Ag; G is selected from the group consisting of Cu, Ni, Co, and Mn; and, 0.1≦x≦0.3; 0 <a≦0.12; 0 ≤ b ≤ 0.12; 0 ≤ c ≤ 0.12; 0 ≤ d ≤ 0.12; 0 <e≦0.12; 0 ≤ f ≤ 0.12; 0≦y≦1, and 0 <b+d+e+f holds true.

[0104] In a further embodiment, the ceramic has the following composition, which has similar advantageous properties when used in a capacitor: Pb (1-1.5a+e) A a (Zr 1-x Ti x ) (1-c-e) E e Si c O3+ y PbO where: A is selected from the group consisting of La, Nd, Y, Eu, Gd, Tb, Dy, Ho, Er, and Yb; E is selected from the group consisting of Cu and Ni; and, 0.05≦x≦0.3; 0 <a≦0.12; 0 ≤ c ≤ 0.12; 0.001≦e≦0.12, and 0≦y<1 holds true.

[0105] In a further embodiment, the ceramic contains sodium strontium titanate. Such a ceramic is also, preferably, an antiferroelectric that can be used in the multilayer capacitor described above.

[0106] In one embodiment, the ceramic has the following composition, which has advantageous properties when used in a capacitor: [Pb (1-r) (Ba x Sr y Ca z ) r (1-1.5a-1.5b-0.5c) (X a Y b )A c (Zr 1-d Ti d )O3 Here, X and Y each represent a rare earth metal selected from the group consisting of La, Nd, Y, Eu, Gd, Tb, Dy, Ho, Er and / or Yb; A represents a monovalent ion; x + y + z = 1 0 ≦ x; 0 ≦ y; 0 ≦ z; 0 < r ≦ 0.3; 0 < d ≦ 1; 0 < a ≦ 0.2; 0 ≦ b ≦ 0.2, and 0 < c ≦ 0.2 hold true.

[0107] In a further embodiment, the ceramic has the following composition, which also has advantageous properties when used in a capacitor: (Bi a Na b Sr c )(Mg d Ti 1-d )O3 Here, 0.10 ≦ a ≦ 0.65; 0 < b ≦ 0.45; 0 < c ≦ 0.85; 0 < d < 0.20, and 0.95 ≦ a + b + c ≦ 1.05 hold true.​

[0108] In a further embodiment, the ceramic has the following composition, which also has advantageous properties when used in a capacitor: (Bi a Na b Sr c )(Zn d Ti 1-d )O3 where 0.09 ≦ a ≦ 0.58, 0.09 ≦ b ≦ 0.42, 0.05 ≦ c ≦ 0.84; 0 < d < 0.08, and 0.95 ≦ a + b + c ≦ 1.05 holds.

[0109] In addition to the above-described composition, further compositions that are not explicitly described are possible.

[0110] A capacitor having the above characteristics is suitable for use as a DC link capacitor or a snubber capacitor.

[0111] Due to the characteristics of the capacitor, it is possible in some applications to omit an additional snubber capacitor when used as a DC link capacitor.

[0112] A further use of the above-described capacitor is as a filter capacitor. Due to its high-frequency characteristics, interference signals can be sufficiently attenuated and filtered up to the MHz range.

[0113] In the following, the present invention will be described in detail based on examples. The present invention is not limited to the described examples.

Brief Description of the Drawings

[0114] [Figure 1] 1 is a schematic side view of a first embodiment of a multilayer capacitor according to the present invention that does not include first and second electrodes in one segment. [Figure 2] 10 is a schematic side view of a second embodiment of a multilayer capacitor including first and second electrodes in two segments. FIG. [Figure 3] 1 is a schematic top view of a second embodiment of a stacked capacitor including first and second electrodes in two segments. FIG. [Figure 4] FIG. 10 is a schematic side view of a third embodiment of a multilayer capacitor including first and second electrodes in two segments. [Figure 5] FIG. 10 is a schematic top view of a third embodiment of a stacked capacitor including first and second electrodes in two segments. [Figure 6] FIG. 10 is a schematic side view of a fourth embodiment of a multilayer capacitor including first, second and third electrodes in two segments. [Figure 7] FIG. 10 is a schematic top view of a fourth embodiment of a stacked capacitor including first, second and third electrodes in two segments. [Figure 8] FIG. 10 is a schematic side view of a fifth embodiment of a multilayer capacitor including first and second electrodes in two segments. [Figure 9] FIG. 10 is a schematic top view of a fifth embodiment of a multilayer capacitor including first and second electrodes in two segments. [Figure 10] FIG. 10 is a schematic side view of a sixth embodiment of a multilayer capacitor including first and second electrodes in two segments. [Figure 11] FIG. 10 is a schematic top view of a sixth embodiment of a multilayer capacitor including first and second electrodes in two segments. [Figure 12] FIG. 10 is a schematic side view of a seventh embodiment of a multilayer capacitor in which two segments include first to sixth electrodes. [Figure 13] FIG. 10 is a schematic top view of a seventh embodiment of a multilayer capacitor including first to sixth electrodes in two segments. [Figure 14] FIG. 10 is a schematic side view of an eighth embodiment of a multilayer capacitor including first and second electrodes and fourth and fifth electrodes in two segments. [Figure 15]FIG. 10 is a schematic top view of an eighth embodiment of a multilayer capacitor including first and second electrodes and fourth and fifth electrodes in two segments. [Figure 16] FIG. 13 is a schematic side view of a ninth embodiment of a multilayer capacitor including external contacts. [Figure 17] FIG. 13 is a schematic side view of a metal sheet of an external contact of a ninth embodiment of the multilayer capacitor. DETAILED DESCRIPTION OF THE INVENTION

[0115] Figure 1 shows a first embodiment of a multilayer capacitor 1. The figure is substantially limited to depicting a capacitor element 2. Further components such as external contacts are not shown in Figure 1.

[0116] The illustrated capacitor 1 is constructed similarly to the present example of a stacked capacitor, but does not include bonding regions and stress relief regions.

[0117] The capacitor element 2 includes a stack of three first electrodes 3, three second electrodes 4, and a dielectric layer 5 disposed between or around the electrodes. The layers are arranged one on top of the other in a defined stacking direction.

[0118] The first electrode 3 and the second electrode 4 exit the rectangular parallelepiped capacitor element 2 at two opposite sides, which are called the first and second exit faces 6 / 7. The exit faces 6 / 7 are arranged perpendicular to the stacking direction.

[0119] At the exit face 6 / 7, the electrodes of each pair are connected to one another via electrically conductive external contacts 8. The external contacts 8 each cover a large portion of the exit face 6 / 7. In other embodiments, the external contacts 8 may cover a smaller portion of the exit face 6 / 7 or the entire exit face 6 / 7.

[0120] The electrodes 3 / 4 do not reach the respective opposite exit faces 7 / 6, resulting in two distinct regions within the multilayer capacitor 1. In the central region of the capacitor element 2, the first and second electrodes 3 / 4 overlap. These regions are called active regions 9A. In the regions adjacent to the exit faces, only the first electrode 3 or only the second electrode 4, respectively, is present. These regions are called passive regions 9B.

[0121] The two sides of the capacitor element 2 perpendicular to the outlet face 6 / 7 and perpendicular to the stacking direction are each flanked by an electrode-free region, which is also called the passive region 9B (see FIG. 3).

[0122] The overlapping electrodes 3 / 4 function as a capacitor when a voltage is applied via the external contacts 8. The voltage between the first and second electrodes 3 / 4 creates an electric field across the active area 9A of the multilayer capacitor 1.

[0123] It should be noted that even in the active area 9A, the electric field does not necessarily exist over the entire stack height. Rather, the electric field acts only between electrodes of different electric polarization, i.e., within the dielectric layer 5 located between the first and second electrodes 3 / 4, for example. An electric field is also generated between the internal electrodes and the external contacts, provided that the electric polarizations are different.

[0124] The dielectric layer 5 of the multilayer capacitor 1 is made of an antiferroelectric ceramic material. In an electric field, polarization of the domains in the crystalline structure of the ceramic is induced.

[0125] The electrodes are made of a conductive material such as copper, silver, nickel, palladium or platinum.

[0126] Polarization causes lattice deformations in the ceramic, which in turn generate mechanical stresses inside the multilayer capacitor 1. Due to the small stack height, these mechanical stresses can be neglected in the first example.

[0127] The ceramic material in the embodiment is a perovskite ceramic. Perovskite ceramics usually have antiferroelectric properties. The ceramic composition according to any one of claims 17 to 24 further allows achieving advantageous properties for the capacitor, such as high mechanical stability and a long service life.

[0128] The multilayer capacitor 1 shown in Figures 2a and 2b substantially corresponds to the multilayer capacitor 1 of the first example.

[0129] In the top view of FIG. 3, the previously introduced side faces 10 / 11 of the capacitor element 2, perpendicular to the exit faces 6 / 7 and perpendicular to the stacking direction, are also depicted.

[0130] In addition to the capacitor shown in Figure 1, the capacitors of Figures 2 and 3 have second segments, which are arranged one above the other in the stacking direction. The individual segments of the second example correspond to the segments of the first example.

[0131] The segments are bonded via bonding regions 12. Within bonding regions 12, stress relief regions 13 exist. Therefore, the second example is an embodiment of the claimed invention. The features and characteristics of the second example, which correspond to the multilayer capacitor 1 of the first example, will not be described again.

[0132] Bonding region 12 comprises the same dielectric ceramic material as the dielectric layers of segments 2A and 2B of capacitor element 2.

[0133] The bonding region 12 includes the bottom dielectric layer of the first segment 2A and the top dielectric layer of the second segment 2B, which are arranged one above the other in the stacking direction. There are no electrodes inside the bonding region 12.

[0134] At the edge of the bonding region, there is a continuous stress relief region 13 along the entire periphery of the capacitor element 2. The stress relief region 13 is located between the bottom dielectric layer of the first segment 2A and the top dielectric layer of the second segment 2B.

[0135] The depth of the stress relief region 13 measured from the outer surface of the capacitor element 2 to the innermost part of the capacitor element 2 preferably corresponds to the stack height of the segments.

[0136] It can therefore be ensured that mechanical stresses resulting from deformation of the ceramic in the electric field do not add up across segments and result in, for example, cracks in the material.

[0137] The stress relief region 13 includes all passive regions 9B of the multilayer capacitor 1. That is, the stress relief region 13 is arranged parallel to all sections within the segment that include only one type of electrode or no electrodes within the bonding region 12. Furthermore, the stress relief region 13 partially extends into the active region 9A of the capacitor element 2.

[0138] When viewed from the stacking direction, the active region 9A has a rectangular shape, as shown in Figure 3. The passive region 9B forms a rectangular frame surrounding the active region 9A. The stress relief region 13 surrounds the passive region 9B and also forms a rectangular frame that partially overlaps with the active region 9A.

[0139] The stress relief regions 13 are regions where the stacked dielectric layers 5 are only partially, but not firmly, bonded to one another.

[0140] To manufacture such a multilayer capacitor 1 according to the second embodiment, ceramic green sheets containing a perovskite material are prepared for forming the dielectric layer 5. A first paste containing an organic material is printed on the topmost green sheet of the second segment 2B.

[0141] A second metal paste is printed onto additional green sheets in the desired areas to form electrodes, and the green sheets are arranged into a stack, which is then sintered.

[0142] The first organic paste is formed so as to completely or partially prevent co-sintering of the dielectric layer 5 at the location where the first paste is applied, thereby forming a stress relief region 13 there.

[0143] 4 and 5 show a further embodiment of the multilayer capacitor 1 according to the invention.

[0144] The essential features of Example 3 correspond to those of Example 2. These features will not be described again.

[0145] In this example, the stress relief region 13 includes an outer section 13A along the periphery of the capacitor element 2, as well as an inner section 13B extending between the outer surfaces parallel to the outlet face 6 / 7 of the capacitor element 2. The width of this inner section can be varied as desired. In this example, the width of the inner section is greater than the width of the outer section.

[0146] The inner section of the stress relief region 13 is positioned completely parallel to the active area 9 A of the multilayer capacitor 1 .

[0147] By means of such an additional inner section of the stress relief region 13, additive mechanical stresses occurring within the capacitor 1 can be effectively avoided even if the dimensions of the individual layers are large or the stack height is high.

[0148] When viewed in the stacking direction, the stress relief region 13 has the shape of a rectangular frame whose long sides are connected by cross beams. The cross beams correspond to the inner sections of the stress relief region 13.

[0149] It should be noted that in the illustrated structure of the third embodiment of the capacitor 1, unwanted migration of charged particles from the exterior to the interior of the capacitor can occur. The charged particles can be, for example, protons present on the exterior surface of the capacitor 1 due to moisture. This is because an electric field can form in the outermost dielectric layer 5A of the capacitor 1 between the uppermost second electrode 4A and the first external contact. This effect can be further intensified if the external contact also covers part of the top surface 1A of the capacitor 1 due to, for example, coating errors.

[0150] 6 and 7 show a fourth embodiment of the multilayer capacitor 1, the features of which partially coincide with those of the previous embodiments, and these features will not be described again.

[0151] Unlike the previous examples, the multilayer capacitor 1 in the fourth embodiment further includes a third electrode 14 in addition to the first and second electrodes. The third electrode 14 is an inner so-called floating electrode that is not adjacent to the outer surface of the capacitor element 2. Therefore, the third electrode 14 is not contacted from the outside.

[0152] Unlike the previous embodiment, the first and second electrodes 3 / 4 are respectively arranged in the same layer plane, but are further separated by a dielectric section.

[0153] Between the layer planes containing the first and second electrodes, a layer plane containing a third electrode 14 is arranged.

[0154] In this way, a multilayer capacitor 1 is formed that includes two capacitors connected in series: a first capacitor 1B formed between the first and third electrodes, and a second capacitor 1C formed between the third and second electrodes.

[0155] Between the two active areas 9A of the capacitors 1B and 1C there is a passive area 9B in which only the third electrode 14 is present, so that there is no overlap of different types of electrodes.

[0156] In this embodiment, the stress relief region 13 is embodied in the same manner as in the third embodiment, and therefore includes an outer section along the outer periphery of the capacitor element 2 and an inner section.

[0157] The additional inner section further ensures that the entire passive area 9B of the capacitor element 2 is covered by the stress relief region 13. Furthermore, the stress relief region 13 also extends to areas outside the two active areas 9A of the capacitors 1B and 1C.

[0158] A further advantage of the fourth embodiment described above is that no electric field is generated between the outermost first or second electrode 3A / 4A of each segment 2A / 2B of the capacitor 1 and the adjacent external contact, since they each have the same electric polarization, and therefore the individual layers within the active area 9A also have no electric field.

[0159] It is therefore possible to avoid undesired migration of charged particles from the outside to the inside of the capacitor 1. Such charged particles may be, for example, protons that may be present on the outer surface of the capacitor 1 due to moisture.

[0160] 8 and 9 show a fifth example of the multilayer capacitor 1. Features corresponding to the above-described embodiments will not be described again.

[0161] The illustrated multilayer capacitor 1 also includes only first and second electrodes. However, the electrodes have different dimensions. In the first layer plane, the first and second electrodes are formed opposite each other and separated by a dielectric section. These first layer planes are embodied in the same manner as in the fourth embodiment.

[0162] The first layer planes form the first and last layer planes of each segment, respectively. Since the first and second electrodes 3B, 4B each have the same electric polarization as the adjacent external contacts, no electric field is now generated in the outer sections of the segments 2A / 2B or between the two segments.

[0163] Furthermore, unlike electrodes 3A and 4A, electrodes 3B and 4B are not adjacent to electrodes of opposite electric polarization within capacitor 1. Therefore, an electric field is not formed over a relatively large area. Therefore, the individual layers within active area 9A also do not have an electric field.

[0164] The above-described embodiment is also advantageous in that no electric field is generated between the outermost first or second electrodes 3A / 4A / 3B / 4B of each segment 2A / 2B of the capacitor 1 and the adjacent external contacts, since they have the same electric polarization, thus avoiding undesired migration of charged particles from the outside to the interior of the capacitor 1.

[0165] This has the advantage of greater stability against moisture-induced material changes.

[0166] The distance between the first and second electrodes in the first layer plane corresponds to at least the thickness of the dielectric layer 5 in the stacking direction. Preferably, the distance is 1.5 to 3 times this thickness. This makes it possible to prevent, for example, a direct current from the first electrode 3B to the opposing second electrode 4A.

[0167] This spacing defines the maximum dimension of the electrodes in the first layer plane, the minimum dimension of which corresponds to the depth of the passive area 9B around the periphery of the capacitor, and preferably corresponds to at least twice this depth.

[0168] Additionally, there is a second layer plane in which only the first electrode 3 is present, and a third layer plane in which only the second electrode 4 is present. In these layer planes, each electrode extends approximately to the opposite exit face. The distance of the electrode to the opposite exit face corresponds to the depth of the passive region along the periphery of the layer plane. These layer planes are fabricated in the same manner as in the third embodiment.

[0169] The second and third layer planes are arranged one on top of the other, with a dielectric layer 5 between them.

[0170] The bonding area 12 and stress relief area 13 are embodied in the same manner as in the previous example. The stress relief area 13 includes an outer frame-like section and an inner crossbeam-like section.

[0171] The outer passive area 9B and part of the inner active area 9A are covered by a stress relief area 13, as shown in FIG.

[0172] Unlike the fourth embodiment, here there is no passive area 9B in the center of the capacitor element 2.

[0173] 10 and 11 show a sixth embodiment of the multilayer capacitor 1. The individual segments are embodied in the same manner as in the fourth embodiment. However, the sixth embodiment differs from the fourth embodiment in the configuration of the stress relief regions 13.

[0174] While in the fourth embodiment there is only a single section of stress relief region 13B inside the capacitor, in addition to the outer section of stress relief region 13A, the sixth embodiment has many different sections 13B inside. All of these sections 13B are connected to each other or to the outer section 13A of the stress relief region. They are preferably embodied to allow for uniform relief of mechanical stress. The inner sections 13B of the stress relief region can be arranged parallel to each other or can intersect. The number of sections and their shape and dimensions can be varied as desired.

[0175] 12 and 13 show further embodiments of the multilayer capacitor 1. Embodiment 7 substantially corresponds to embodiment 4. It comprises first, second and third electrodes 3, 4 and 14.

[0176] Unlike the fourth embodiment, the seventh embodiment further includes fourth, fifth, and sixth electrodes 15, 16, and 17. These are dummy electrodes that fill the passive area 9B without forming an active area 9A by themselves.

[0177] The fourth and fifth electrodes 15 and 16 are located in the passive area outside the capacitor element 2. They are located near the external contacts and can be contacted by them. The fourth and fifth electrodes do not generate an electric field because they only overlap electrodes of the same polarity.

[0178] The fourth electrode 15 in contact with the first external contact overlaps only with that very fourth electrode 15 or the first electrode 3 .

[0179] The fifth electrode 16 in contact with the second external contact overlaps only with that very fifth electrode 16 or the second electrode 4 .

[0180] The sixth electrode 17 is arranged in the center of the capacitor element 2 between the first and second electrodes 3 and 4, in the same layer plane as the first and second electrodes. The sixth electrode 17 overlaps only with the further sixth electrode 17 and the third electrode 14. This area is therefore also a passive area 9B of the capacitor element 2, since there is no overlap of different electrodes of different polarities. In this example, the sixth electrodes are arranged flush with each other in the stacking direction.

[0181] The distance of the dummy electrode to the active electrode in the direction perpendicular to the electric field corresponds to at least the thickness of the dielectric layer 5, and preferably 1.5 to 3 times the thickness of the dielectric layer 5.

[0182] By using dummy electrodes, the mechanical stresses and strains that typically occur between areas with electrodes and areas without electrodes are reduced.

[0183] Therefore, by using the dummy electrodes and stress relief regions, it is possible to minimize the mechanical stress in the multilayer capacitor 1 and improve the robustness of the capacitor, thereby optimizing the thermomechanical and electrical load capacity of the multilayer capacitor 1.

[0184] 14 and 15 show an eighth embodiment of the multilayer capacitor 1, which essentially corresponds to a combination of the fifth and seventh embodiments.

[0185] In addition to the first and second electrodes 3 and 4, this embodiment also includes fourth and fifth electrodes 15 and 16 along the periphery of the electrode layer, which are also on the same layer as the first and second electrodes 3 and 4.

[0186] The fourth and fifth electrodes 15, 16 are formed as dummy electrodes, similar to Example 7. They overlap only with electrodes of the same polarity, respectively. The distances of the fourth and fifth electrodes 15, 16 to the active electrodes are preferably 1.5 to 3 times the thickness of the dielectric layer 5, but at least correspond to the thickness of the dielectric layer 5, in order to avoid current flow between the active electrodes and the opposing dummy electrodes.

[0187] Thus, electrodes 15A and 16B of the outermost segment layers, respectively, serve the same purpose as electrodes 3A and 4B of the fifth embodiment, but are embodied at the minimum appropriate depth.

[0188] The layers containing the first and fourth electrodes or the second and fifth electrodes always have the same electrode shape, or the electrodes are simply mirror images of each other, so that the same stencil can be used each time to print the electrode layer.

[0189] 16 shows a ninth embodiment of the multilayer capacitor 1. The capacitor element 2 can be embodied according to one of the previous examples.

[0190] An external contact 8 is further applied onto the exit faces of electrodes 6 and 7. The external contact 8 comprises several layers. Directly on top of the exit face 6 / 7 is applied a sputtered layer 8A which covers the entire exit face 6 / 7. The sputtered layer 8A comprises three layers of chromium, nickel and silver.

[0191] By means of the above-mentioned sputtered layer 8A, all of the first electrodes or all of the second electrodes, respectively, can be electrically connected to one another and therefore connected in parallel.

[0192] On top of the sputtered layer 8A, a metal sheet 18 for external contact is applied with a sintered silver layer 19.

[0193] Sintered silver layer 19 covering the entire sputtered layer 8A binds together sputtered layer 8A when capacitor element 2 is deformed, and prevents, for example, sputtered layer 8A from peeling off.

[0194] In this embodiment, the silver layer 19 has a thickness of about 20 μm to 30 μm, and the porosity of the silver in the layer is 35%.

[0195] The silver layer 19 also secures the metal sheet 18 to the sputtered layer 8A. Therefore, no soldering connection is required. For this purpose, silver is applied onto the sputtered layer, and the metal sheet 18 is placed directly on top of it. Only after the metal sheet 18 has been placed is the silver layer 19 sintered.

[0196] Due to its high electrical conductivity, the silver layer 19 also allows a good electrical connection of the metal sheet 18 to the sputtered layer 8A.

[0197] To improve adhesion of the metal sheet 18 to the silver layer 19, the surface of the metal sheet 18 is silver-plated in this embodiment. Preferably, the surface is electrolytically silver-plated. Thus, an electroplated silver layer 20 is formed on the surface of the metal sheet 18, and is disposed between the metal sheet 18 and the silver layer 19. The thickness of the electroplated silver layer 20 is 5 μm to 10 μm.

[0198] The metal sheet 18 of the external contact in this embodiment comprises two copper layers 18B with an Invar layer 18A disposed therebetween, as shown in the detailed view of Figure 17. Instead of Invar, the middle layer can also comprise other iron-nickel alloys or iron-nickel-cobalt alloys.

[0199] The central Invar layer provides the necessary mechanical strength to the metal sheet 18. The low thermal expansion of Invar prevents the creation of mechanical stresses during temperature changes, thus significantly preventing crack formation in the ceramic or external contacts of the capacitor.

[0200] An outer copper layer 18B is applied onto the Invar layer 18A, preferably rolled down. The copper layer 18B has high thermal and electrical conductivity, and therefore can provide an external contact that has, on the one hand, a small coefficient of thermal expansion and therefore high mechanical stability, and, on the other hand, high thermal and electrical conductivity.

[0201] Copper layers 18B are applied to both sides of the Invar layer 18A with equal thicknesses. Applying copper evenly to both sides avoids the formation of a bimetallic strip, which has unfavorable properties for this application. The copper-Invar-copper layer thickness ratio is preferably 1:3:1. In this example, a metal sheet with a total thickness of 0.15 mm is used. The Invar layer 18A is 90 μm thick, and the copper layers 18B are each 30 μm thick.

[0202] By using substantially silver and copper in the above-described layer structure of the external contacts, an external contact having high electrical and thermal conductivity is achieved.

[0203] The layer structure described above further allows for matching the thermal expansion coefficients, increasing the thermomechanical load capacity and therefore the durability, and improving the maximum current carrying capacity, which results in an optimized fault tolerance during operation.

[0204] Capacitors with the above properties are suitable for use as DC link capacitors or snubber capacitors. The small parasitic capacitance, especially the low equivalent series inductance, and the ability to mount the capacitor close to the semiconductors allow the rectifier circuit to be kept small, so that induced overvoltages can be well attenuated during the switch-off process. Due to the capacitor's properties, it is possible in some applications to omit an additional snubber capacitor when used as a DC link capacitor.

[0205] A further application of the above mentioned capacitors is their use as filter capacitors: due to their high frequency characteristics, interference signals can be well attenuated and filtered, up to the MHz range, far beyond the operating frequency of the power converter.

[0206] In a further embodiment not shown, instead of the metal sheet 18, a copper layer is applied onto the silver layer 19. In this example, the copper layer has a serpentine lattice geometry. The copper layer is again silver-plated. The silver plating is carried out by electroplating. The copper layer is sintered directly together with the silver layer. [Explanation of symbols]

[0207] 1. Multilayer capacitor Top of 1A capacitor 1B First Capacitor 1C Second Capacitor 2 Capacitor elements 2A, 2B segments 3, 3A, 3B First electrode 4, 4A, 4B Second electrode 5 Dielectric Layer 6 First Exit Plane 7 Second Exit Plane 8 External Contacts 8A sputtered layer 9A Active Area 9B Passive Area 10,11 Side 12 Combined area 13 Stress relaxation region 13A Outer section of stress relief area 13B Inner section of stress relief area 14 Third electrode 15A, 15B Fourth electrode 16A, 16B Fifth electrode 17 Sixth Electrode 18 Metal Sheet 18A Invar layer 18B copper layer 19 Silver layer 20 electroplated silver layer

Claims

[Claim 1] a plurality of capacitor elements (2) each having at least two segments (2A, 2B), each segment including a dielectric layer (5) made of ceramic and an electrode layer disposed therebetween, and including a plurality of layer planes arranged one above the other in a layering order, the electrode layers including different electrodes including at least first and second electrodes (3, 4), the different electrodes overlapping in an active region (9A) and not overlapping in a passive region (9B), the plurality of segments arranged overlapping in a stacking direction, the outermost dielectric layers of the two segments forming a bonding region (12) in which the segments are firmly bonded to each other parallel to the layer planes, the bonding region including a stress relief region (13), the stress relief region occupying at least the entire passive region of the multilayer capacitor, and the plurality of capacitor elements (2) being bonded to each other at contact surfaces (10, 11) so as to be able to be assembled and disassembled.

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