Display device

Abstract

To embody a high-resolution, zero-bezel display device by reducing the bezel area of the display device.SOLUTION: A display device according to one embodiment of the present specification includes: a substrate on which a plurality of light-emitting elements are arranged; a transistor located on the substrate; a plurality of signal wirings arranged on the substrate, a plurality of link wirings arranged beneath the substrate, and a plurality of upper pads arranged on the substrate and connected to the plurality of signal wirings. The plurality of upper pads are arranged so that these overlap at least one of the plurality of signal wirings and a plurality of transistors.SELECTED DRAWING: Figure 3b

Description

[Technical Field]

[0001] TECHNICAL FIELD This disclosure relates to displays, and more particularly to displays with reduced bezel area. [Background technology]

[0002] Display devices used in computer monitors, TVs, mobile phones, etc. include organic light-emitting displays (OLEDs), which emit light themselves, and liquid crystal displays (LCDs), which require a separate light source.

[0003] Display devices are now used in a wide range of applications, from computer monitors and TVs to personal portable devices, and research is underway to develop display devices that have a large display area while being reduced in volume and weight.

[0004] In recent years, displays that include LEDs (Light Emitting Diodes) have been attracting attention as the next generation of display devices. LEDs are made of inorganic materials, not organic materials, and are therefore highly reliable and have a longer lifespan than LCDs and OLEDs. LEDs not only have a fast lighting speed, but also have excellent luminous efficiency, strong shock resistance, excellent stability, and can display high-brightness images. Summary of the Invention [Problem to be solved by the invention]

[0005] The problem to be solved by this specification is to provide a display device with a reduced bezel area.

[0006] The present disclosure provides a display device that has a reduced bezel area and can achieve high resolution.

[0007] Another problem to be solved by the present specification is to provide a display device in which the problem of multiple pads being disconnected from each other is reduced.

[0008] Another problem to be solved by the present invention is to provide a display device that solves the problem of a material constituting a side wiring not being applied to a side surface of a substrate of the display device.

[0009] The objects of this specification are not limited to the objects mentioned above, and other objects not mentioned will be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0010] A display device according to an embodiment of the present disclosure includes a substrate on which a plurality of light emitting elements are disposed, transistors disposed on the substrate, a plurality of signal wirings disposed on the substrate, a plurality of link wirings disposed under the substrate, and a plurality of upper pads disposed on the substrate and connected to the plurality of signal wirings, the plurality of upper pads being arranged to overlap at least one of the plurality of signal wirings and the plurality of transistors, thereby reducing a bezel area of ​​the display device and realizing a high-resolution zero-bezel display device.

[0011] Further details of the embodiments are included in the detailed description and drawings. [Effects of the Invention]

[0012] In the present specification, the bezel area of ​​the display device can be reduced by arranging the wiring so as to overlap with at least one of the plurality of signal lines and the plurality of transistors.

[0013] The present disclosure makes it possible to reduce the bezel area and implement a high-resolution display device.

[0014] This specification can improve the problem of multiple pads being disconnected due to physical impact.

[0015] In the present specification, the side wirings arranged on the side surfaces of the substrate can be arranged uniformly.

[0016] The effects of this specification are not limited to the examples given above, and various other effects are included within this specification. [Brief explanation of the drawings]

[0017] [Figure 1] 1 is a schematic plan view of a display device according to an embodiment of the present specification; [Figure 2a] FIG. 2 is a schematic plan view of a display device according to an embodiment of the present specification in a state before a grinding process; [Figure 2b] 2b is a schematic cross-sectional view of the display device taken along II-II' in FIG. 2a; [Figure 3a] 1 is a schematic plan view of a display device according to an embodiment of the present specification; [Figure 3b] 3b is a schematic cross-sectional view of the display device taken along III-III' in FIG. 3a; [Figure 4a] FIG. 10 is a schematic cross-sectional view of a display device according to another embodiment of the present specification in a state before a grinding process of the display device. [Figure 4b] FIG. 10 is a schematic cross-sectional view of a display device according to another embodiment of the present specification. [Figure 5] FIG. 10 is a schematic cross-sectional view of a display device according to still another embodiment of the present specification. DETAILED DESCRIPTION OF THE INVENTION

[0018] The advantages and features of the present invention, and methods for achieving them, will become more apparent from the following detailed description of the embodiments in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, and may be embodied in various different forms. The embodiments are provided solely so that this disclosure will be complete and will fully convey the scope of the invention to those skilled in the art.

[0019] The shapes, areas, ratios, angles, numbers, etc. disclosed in the drawings for illustrating the embodiments of this specification are illustrative only and are not intended to limit the scope of this specification. The same reference symbols refer to the same elements throughout this specification. Furthermore, when describing this specification, if it is deemed that a detailed description of related prior art would unnecessarily obscure the gist of this specification, such a detailed description will be omitted. When using words such as "include," "have," and "be made" in this specification, other parts may be added unless "only" is used. When describing an element in the singular, this also includes the plural unless otherwise explicitly stated.

[0020] When interpreting elements, they are interpreted as including a margin of error even if there is no other explicit description.

[0021] When describing a positional relationship, for example, when describing the positional relationship of two parts using "above," "at the top," "below," "next to," etc., one or more other parts may be located between the two parts, as long as "immediately" or "directly" is not used.

[0022] When an element or layer is referred to as "on" another element or layer, it includes the case where the element or layer is directly on top of the other element or layer, or where there are other layers or elements interposed therebetween.

[0023] Furthermore, although terms such as "first," "second," etc. are used to describe various components, these components are not limited by these terms. These terms are used merely to distinguish one component from another. Therefore, a first component referred to below may be a second component within the technical concept of this specification.

[0024] Like reference numbers refer to like elements throughout the specification.

[0025] The area and thickness of each component shown in the drawings are shown for convenience of explanation, and the present specification is not necessarily limited to the area and thickness of the components shown.

[0026] The features of the various embodiments of this specification may be partially or wholly combined or combined with each other, may be technically interlocked and driven in various ways, and each embodiment may be implemented independently of the other or may be implemented together in a related relationship.

[0027] Various embodiments of the present specification will now be described in detail with reference to the accompanying drawings.

[0028] 1 is a plan view of a display device according to an embodiment of the present disclosure. For convenience of explanation, only a substrate 110, data lines DL, scan lines SL, a plurality of sub-pixels SP, and an upper pad PAD1 of the display device 100 are shown in FIG.

[0029] 1, the substrate 110 is a substrate that supports components disposed on the upper portion of the display device 100 and may be an insulating substrate. For example, the substrate 110 may be made of glass or resin. The substrate 110 may also include a polymer or plastic. In some embodiments, the substrate 110 may be made of a flexible plastic material.

[0030] The substrate 110 may be defined with a display area AA and a non-display area NA surrounding the display area AA.

[0031] The display area AA is an area where an image is displayed on the display device 100. In the display area AA, a plurality of sub-pixels SP constituting a plurality of pixels and circuits for driving the sub-pixels SP may be arranged.

[0032] The sub-pixels SP are the minimum units constituting the display area AA, and each of the sub-pixels SP may include a light-emitting element, a thin-film transistor for driving the light-emitting element, etc. The sub-pixels SP will be described in more detail below with reference to Figures 2a to 3b.

[0033] A plurality of signal lines are arranged in the display area AA to transmit various signals to the subpixels SP. For example, the signal lines may include a plurality of data lines DL that supply data voltages to the subpixels SP, a plurality of scan lines SL that supply scan voltages to the subpixels SP, etc. A more detailed description of the signal lines will be provided below with reference to Figures 2a to 3b.

[0034] The non-display area NA is an area where no image is displayed and may be defined as an area surrounding the display area AA. Link wiring and pad electrodes for transmitting signals to the sub-pixels SP of the display area AA, as well as driving ICs such as gate driver ICs and data driver ICs may be arranged in the non-display area NA.

[0035] A plurality of upper pads PAD1 are arranged in the non-display area NA to transmit various signals to a plurality of sub-pixels SP on the substrate 110. The plurality of upper pads PAD1 are arranged to overlap a plurality of signal lines, which will be described later. The plurality of upper pads PAD1 are also electrically connected to the side lines and a plurality of signal lines in the display area AA, and can transmit signals to the sub-pixels SP from a plurality of flexible films and a printed circuit board arranged on the rear surface of the substrate 110. A more detailed description of the plurality of upper pads PAD1 will be given later with reference to FIGS. 2a to 3b.

[0036] Meanwhile, the upper pads PAD1 may not overlap the signal wirings. For example, the upper pads PAD1 may be arranged alternately with the signal wirings on a plane. In this case, the upper pads PAD1 and the signal wirings may be electrically connected to the side of the substrate 110 through side wirings arranged on the side of the substrate 110. In addition, the side wirings may extend from the side of the substrate 110 to cover ends of the upper pads PAD1 and ends of the side wirings, but are not limited thereto.

[0037] Meanwhile, although it has been described herein that a display area AA and a non-display area NA are defined on the front surface of the display device 100, the front surface of the display device 100 may be defined as having no non-display area NA, and the present invention is not limited thereto. When a plurality of display devices 100 according to an embodiment of the present invention are connected to implement a tiled display having a large screen, the distance between the outermost sub-pixel SP of one display device 100 and the outermost sub-pixel SP of another adjacent display device 100 may be implemented to be the same as the distance between the plurality of sub-pixels SP within one display device 100, thereby implementing a zero bezel, which essentially has no bezel area. Therefore, only the display area AA where an image is displayed may be defined on the front surface of the display device 100, and the present invention is not limited thereto.

[0038] Fig. 2a is a schematic plan view of a display device according to an embodiment of the present disclosure before a grinding process. Fig. 2b is a schematic cross-sectional view of the display device taken along line II-II' in Fig. 2a. Fig. 2a is an enlarged plan view of region X in Fig. 1. Fig. 2a only shows a plurality of upper pads PAD1, a plurality of signal wirings, a plurality of light-emitting elements LEDs, and a plurality of pixels P on a substrate 110.

[0039] Referring to FIG. 2a, a plurality of display modules include a plurality of signal lines and a plurality of pixels P.

[0040] The plurality of pixels P may include a first subpixel SP1, a second subpixel SP2, and a third subpixel SP3. The first subpixel SP1, the second subpixel SP2, and the third subpixel SP3 may be subpixels that emit different colors. For example, the first subpixel SP1, the second subpixel SP2, and the third subpixel SP3 may be, but are not limited to, a red subpixel that emits red, a green subpixel that emits green, and a blue subpixel that emits blue, respectively. For example, the plurality of pixels P may further include a white subpixel that emits white.

[0041] Each of the sub-pixels SP1, SP2, and SP3 may include a light-emitting region and a circuit region. The light-emitting region may be defined as a region through which light emitted from the light-emitting element LED can travel to the outside. The light-emitting region is a region that can independently emit light of one color, and the light-emitting element LED may be arranged in the light-emitting region. For example, the first sub-pixel SP1 may be arranged with a first light-emitting element LED1 that emits red light, the second sub-pixel SP2 may be arranged with a second light-emitting element LED2 that emits green light, and the third sub-pixel SP3 may be arranged with a third light-emitting element LED3 that emits blue light.

[0042] The circuit region is the remaining region excluding the light-emitting region, and may include a driving circuit for driving the light-emitting elements LED, such as a driving circuit including a transistor TR and a storage capacitor SC.

[0043] A plurality of signal wirings are disposed on the substrate 110. Sides of the plurality of signal wirings may be disposed on the same plane as a side of the first line L1 at which the grinding process of the substrate 110 is completed.

[0044] The multiple signal wirings are wirings that transmit various signals to the drive circuit, and may include scan wirings SL, data wirings DL, high potential voltage wirings VDDL, reference wirings RL, and low potential voltage wirings VSSL, etc., but are not limited to these.

[0045] The data lines DL are lines that transmit data signals to the subpixels SP1, SP2, and SP3, respectively. The data lines DL are arranged in the column direction between the subpixels SP1, SP2, and SP3, and may include a first data line DL1, a second data line DL2, and a third data line DL3. The first data line DL1, the second data line DL2, and the third data line DL3 can transmit data voltages to the subpixels SP1, SP2, and SP3, respectively. For example, the first data line DL1 can transmit a data voltage to the first subpixel SP1, the second data line DL2 can transmit a data voltage to the second subpixel SP2, and the third data line DL3 can transmit a data voltage to the third subpixel SP3.

[0046] The plurality of high-potential power supply lines VDDL are lines that transmit a high-potential power supply voltage to each of the plurality of sub-pixels SP1, SP2, and SP3. The plurality of high-potential power supply lines VDDL can extend in the column direction.

[0047] The subpixels SP1, SP2, and SP3 can share one high-potential power supply line VDDL. For example, one high-potential power supply line VDDL is disposed between the first subpixel SP1 and the third subpixel SP3, and can supply a high-potential power supply voltage to each of the first subpixel SP1, the second subpixel SP2, and the third subpixel SP3.

[0048] The plurality of reference lines RL extend in the column direction and transmit a reference voltage to each of the plurality of subpixels SP1, SP2, and SP3. The plurality of subpixels SP1, SP2, and SP3 can share a single reference line RL. For example, the single reference line RL is disposed between the third subpixel SP3 and the first subpixel SP1 and can transmit a reference voltage to each of the first subpixel SP1, the second subpixel SP2, and the third subpixel SP3.

[0049] The low-potential voltage line VSSL is a line that applies a low-potential voltage to multiple pixels P. The low-potential voltage line VSSL can extend in the column direction. The subpixels SP1, SP2, and SP3 can share one low-potential voltage line VSSL. For example, one low-potential voltage line VSSL is disposed between the first subpixel SP1 and the third subpixel SP3, and can supply a low-potential power supply voltage to each of the first subpixel SP1, the second subpixel SP2, and the third subpixel SP3.

[0050] Reference is now also made to FIG. 2b for a more detailed description of the various components of the display device 100.

[0051] Referring also to FIG. 2b, the display device 100 may be provided with a substrate 110 for supporting various components disposed on the display device 100.

[0052] The substrate 110 may include a first substrate 101 and a second substrate 102 .

[0053] The first substrate 101 is a substrate that supports components disposed on the upper portion of the display device 100 and may be an insulating substrate. For example, the first substrate 101 may be made of glass, resin, or the like. The first substrate 101 may also be made of a polymer or plastic.

[0054] The second substrate 102 is disposed below the first substrate 101. The second substrate 102 is a substrate that supports components disposed at the bottom of the display device 100 and may be an insulating substrate. For example, the second substrate 102 may be made of glass, resin, or the like. The second substrate 102 may also include a polymer or plastic. The second substrate 102 may be made of the same material as the first substrate 101.

[0055] A bonding layer 121 is disposed between the first substrate 101 and the second substrate 102. The bonding layer 121 may be made of a material that can be cured through various curing methods to bond the first substrate 101 and the second substrate 102. The bonding layer 121 may be disposed only in a portion of the area between the first substrate 101 and the second substrate 102, or may be disposed over the entire area.

[0056] Referring to FIG. 2 b , a light-shielding layer LS is disposed on the first substrate 101 . The light-shielding layer LS is disposed to overlap the active layer ACT of the transistor TR and can block light incident on the active layer ACT. If light is irradiated onto the active layer ACT, leakage current will occur, which may reduce the reliability of the transistor TR, which is a driving transistor. In this case, if the light-shielding layer LS is made of an opaque conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, and is disposed to overlap the active layer ACT, it can block light incident on the active layer ACT from below the display module 110, thereby improving the reliability of the transistor TR.

[0057] A buffer layer 111 is disposed on the first substrate 101 and the light-shielding layer LS. The buffer layer 111 can reduce the penetration of moisture or impurities through the first substrate 101. For example, the buffer layer 111 can be formed of a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto. Furthermore, the buffer layer 111 may be omitted depending on the type of the first substrate 101 or the type of the transistor TR, but is not limited thereto.

[0058] A transistor TR is disposed on the buffer layer 111 in each of the plurality of sub-pixels SP1, SP2, and SP3.

[0059] The transistor TR includes an active layer ACT, a gate electrode GE, a source electrode SE, and a drain electrode DE.

[0060] An active layer ACT is disposed on the buffer layer 111. The active layer ACT may be made of a semiconductor material such as, but not limited to, an oxide semiconductor, amorphous silicon, or polysilicon. For example, if the active layer ACT is made of an oxide semiconductor, the active layer ACT may include a channel region, a source region, and a drain region, and the source region and the drain region may be conductive regions, but are not limited to this.

[0061] A gate insulating layer 112 is disposed on the active layer ACT. The gate insulating layer 112 is a layer for insulating the gate electrode GE from the active layer ACT and may be made of an insulating material. For example, the gate insulating layer 112 may be made of a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0062] The gate insulating layer 112 and the gate electrode GE may be formed in the same pattern, but are not limited thereto. The gate insulating layer 112 may be formed on the front surface of the first substrate 101 .

[0063] A gate electrode GE is disposed on the gate insulating layer 112. The gate electrode GE may be disposed so as to overlap the gate insulating layer 112, and may be made of a conductive material such as, but not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0064] An interlayer insulating layer 113 is disposed on the gate electrode GE and the buffer layer 111. The interlayer insulating layer 113 is a layer for insulating the gate electrode GE from the source electrode SE and the drain electrode DE, and may be made of an inorganic material similar to the gate insulating layer 112. For example, the interlayer insulating layer 113 may be made of a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0065] A source electrode SE and a drain electrode DE are disposed on the interlayer insulating layer 113 and are spaced apart from each other. The source electrode SE and the drain electrode DE may be electrically connected to the active layer ACT through via holes formed in the interlayer insulating layer 113. The source electrode SE and the drain electrode DE may be disposed in the same layer as the gate electrode GE and may be formed of the same conductive material, but are not limited thereto. For example, the source electrode SE and the drain electrode DE may be formed of, but are not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0066] The drain electrode DE is electrically connected to the low potential power line VSSL. For example, the drain electrodes DE of the second and third sub-pixels SP2 and SP3 may be electrically connected to the low potential power line VSSL on the left side of the first sub-pixel SP1.

[0067] The source electrode SE may be electrically connected to the light-shielding layer LS through a via hole formed in the interlayer insulating layer 113 and the buffer layer 111. If the light-shielding layer LS were floating, the threshold voltage of the transistor TR would fluctuate, which could affect the operation of the display device 100. Therefore, by electrically connecting the light-shielding layer LS to the source electrode SE, a voltage can be applied to the light-shielding layer LS without affecting the operation of the transistor TR. However, this is not limited thereto, and both the active layer ACT and the source electrode SE may be in direct contact with the light-shielding layer LS. A plurality of signal lines may be disposed on the interlayer insulating layer 113. For example, the plurality of signal lines may include, but is not limited to, a plurality of scan lines SL, a plurality of high-potential power lines VDDL, a plurality of data lines DL, and a plurality of reference lines RL. The plurality of signal lines may be disposed on the same layer on the first substrate 101 and may be made of the same conductive material.

[0068] The plurality of scan lines SL, the plurality of high potential power supply lines VDDL, the plurality of data lines DL, and the plurality of reference lines RL may be made of a conductive material such as, but not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof. However, without being limited thereto, the plurality of signal lines may be arranged on different layers on the first substrate 101 and made of different conductive materials. Furthermore, the plurality of signal lines may be made of the same material as the drain electrode DE and the source electrode SE. Meanwhile, the plurality of signal lines may be arranged on different layers on the first substrate 101 and made of different conductive materials. In this case, each of the plurality of signal lines may be made of the same material in the same layer as any one of the components constituting the transistor TR.

[0069] Meanwhile, the plurality of signal wirings may include at least two signal wirings arranged to overlap each other. In this case, the two signal wirings may be electrically connected through a contact hole in an insulating layer arranged between the two signal wirings. Also, the plurality of signal wirings and the upper pad PAD1 may be connected through a contact hole in an insulating layer arranged between the plurality of signal wirings and the upper pad PAD1.

[0070] A storage capacitor SC is disposed in each circuit region of the sub-pixels SP1, SP2, and SP3. The storage capacitor SC stores a voltage between the gate electrode GE and the source electrode SE of the transistor TR so that the light emitting element LED maintains the same state during one frame. The storage capacitor SC includes a first capacitor electrode SC1 and a second capacitor electrode SC2.

[0071] In each of the plurality of subpixels SP, a first capacitor electrode SC1 is disposed between the first substrate 101 and the buffer layer 111. The first capacitor electrode SC1 may be disposed closest to the first substrate 101 among the conductive components disposed on the first substrate 101. The first capacitor electrode SC1 may be integrated with the light-shielding layer LS and may be electrically connected to the source electrode SE through the light-shielding layer LS.

[0072] A buffer layer 111 and a gate insulating layer 112 are disposed on the first capacitor electrode SC1, and a second capacitor electrode SC2 is disposed on the buffer layer 111 and the gate insulating layer 112. The second capacitor electrode SC2 may be disposed to overlap the first capacitor electrode SC1. The second capacitor electrode SC2 may be made of the same material as the gate electrode GE. For example, a semiconductor material may be formed on the gate insulating layer 112, and a portion of the semiconductor material may be patterned to form the gate electrode GE and the second capacitor electrode SC2.

[0073] A passivation layer 114 is disposed on the transistor TR and the storage capacitor SC. The passivation layer 114 is an insulating layer for protecting the components below the passivation layer 114. For example, the passivation layer 114 may be formed of a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto. Also, the passivation layer 114 may be omitted depending on the embodiment.

[0074] A plurality of reflective layers 117 are disposed on the passivation layer 114. The reflective layers 117 are disposed to overlap with a light-emitting region including the light-emitting element LED, and can reflect light incident from the light-emitting element LED toward an upper side of the light-emitting element LED, thereby increasing the light efficiency of the display device 100. However, if the display device 100 is a rear-emitting type, the reflective layers 117 may be omitted or may be disposed above the light-emitting element LED.

[0075] An adhesive layer 118 is disposed on the reflective layer 117 to cover the reflective layer 117. The adhesive layer 118 is used to adhere the light-emitting element LED to the reflective layer 117, and can also insulate the reflective layer 117, which is made of a metal material, from the light-emitting element LED. The adhesive layer 118 may be made of a thermosetting material or a photo-curing material, but is not limited thereto. Although FIG. 2b illustrates the adhesive layer 118 being disposed to cover only the reflective layer 117, the location of the adhesive layer 118 is not limited thereto.

[0076] A plurality of light-emitting elements LEDs are disposed on the adhesive layer 118. The plurality of light-emitting elements LEDs are disposed so as to overlap with a plurality of reflective layers 117.

[0077] Each of the plurality of light-emitting elements LEDs may include an active layer made of an inorganic material. The plurality of light-emitting elements LEDs may be micro light-emitting diodes (LEDs).

[0078] The plurality of light-emitting elements LEDs include an n-type layer 131, an active layer 132, a p-type layer 133, an n-electrode 135, and a p-electrode 134. The n-electrode 135 or the p-electrode 134 may be disposed on top of the light-emitting element LED. The n-electrode 135 or the p-electrode 134 may be disposed spaced apart in the horizontal direction.

[0079] In the following description, it is assumed that a light emitting element LED having a lateral structure is used as the light emitting element LED, but the structure of the light emitting element LED is not limited thereto.

[0080] Specifically, the n-type layer NL of the light emitting device LED is disposed on the adhesive layer 118. The n-type layer NL may be formed by doping n-type impurities into gallium nitride, which has excellent crystallinity. The active layer EL is disposed on the n-type layer NL. The active layer EL is a light emitting layer that emits light in the light emitting device LED and may be made of a nitride semiconductor, for example, indium gallium nitride. The p-type layer PL is disposed on the active layer EL. The p-type layer PL may be formed by doping p-type impurities into gallium nitride. However, the constituent materials of the n-type layer NL, the active layer EL, and the p-type layer PL are not limited thereto.

[0081] A p-electrode PE is disposed on the p-type layer PL of the light emitting element LED. An n-electrode NE is disposed on the n-type layer NL of the light emitting element LED. The n-electrode NE is disposed spaced apart from the p-electrode PE. Specifically, the light emitting element LED may be manufactured by sequentially stacking the n-type layer NL, the active layer EL, and the p-type layer PL, and then etching predetermined portions of the active layer EL and the p-type layer PL to form the n-electrode NE and the p-electrode PE. The predetermined portions are spaces for separating the n-electrode NE from the p-electrode PE, and may be etched to expose a portion of the n-type layer NL. In other words, the surfaces of the light emitting element LED on which the n-electrode NE and the p-electrode PE are disposed may have different height levels rather than being flat. Therefore, the p-electrode PE is disposed on the p-type layer PL, and the n-electrode NE is disposed on the n-type layer NL, and the p-electrode PE and the n-electrode NE are disposed spaced apart from each other at different height levels. Therefore, the n-electrode NE may be disposed adjacent to the adhesive layer 118 relative to the p-electrode PE. The n-electrode NE and the p-electrode PE may be made of a conductive material, for example, a transparent conductive oxide, or may be made of the same material, but are not limited thereto.

[0082] A first planarization layer 115a is disposed on the transistor TR. The first planarization layer 115a may be disposed to planarize the upper surface of the transistor TR in a region other than the region where the light emitting element LED is disposed.

[0083] The first planarization layer 115a may be made of an organic material, for example, a single layer or multiple layers of polyimide or photo acrylic, but is not limited thereto.

[0084] A second planarization layer 115b is disposed on the first planarization layer 115a and the light-emitting element LED. The second planarization layer 115b is a layer that planarizes the upper surfaces of the transistor TR and the light-emitting element LED. Although FIG. 2b illustrates the first planarization layer 115a and the second planarization layer 115b, the present invention is not limited thereto, and a single planarization layer may be formed. Disposing a single planarization layer can prevent an excessive increase in the time required for the process. The planarization layer may also be composed of two or more layers. The second planarization layer 115b may be made of the same material as the first planarization layer 115a, but is not limited thereto.

[0085] The first electrode CE1 electrically connects the transistor TR and the light emitting element LED. The first electrode CE1 is connected to the n-electrode NE of the light emitting element LED through a via hole formed in the second planarization layer 115b. The first electrode CE1 is also connected to the source electrode SE of the transistor TR through a via hole formed in the planarization layers 115a and 115b and the passivation layer 114. However, the present invention is not limited thereto, and the first electrode CE1 may be connected to the drain electrode DE of the transistor TR depending on the type of the transistor TR.

[0086] The second electrode CE2 is an electrode that electrically connects the light emitting element LED to the high potential voltage line VDDL. Specifically, the second electrode CE2 is connected to the high potential voltage line VDDL through a via hole formed in the planarization layers 115a and 115b and the passivation layer 114, and is connected to the p-electrode PE of the light emitting element LED through a via hole formed in the second planarization layer 115b. Therefore, the high potential voltage line VDDL and the p-electrode PE of the light emitting element LED are electrically connected.

[0087] The first electrode CE1 and the second electrode CE2 are spaced apart from each other. Meanwhile, the second planarization layer 115b and the third planarization layer 115c can insulate the first electrode CE1 from the second electrode CE2. For example, the first electrode CE1 and the second electrode CE2 can be disposed on the first planarization layer 115a and the second planarization layer 115b, and the third planarization layer 115c can be disposed on the first electrode CE1 and the second electrode CE2. In this case, the third planarization layer 115c can cover the upper surface of the second planarization layer 115b exposed between the first electrode CE1 and the second electrode CE2, thereby insulating the first electrode CE1 from the second electrode CE2.

[0088] The bank 119 is disposed on the second planarization layer 115b, the first electrode CE1, and the second electrode CE2. The bank 119 is an insulating layer that defines a light-emitting region. The bank 119 may be made of an organic insulating material, which may be the same material as the planarization layers 115a and 115b. The bank 119 may also be made of a light-absorbing material, such as a black material, to prevent color mixing caused by light emitted from the light-emitting element LED being transmitted to adjacent sub-pixels SP1, SP2, and SP3.

[0089] The banks 119 may extend to the edges of the display device 100. The banks 119 may be disposed on the electrostatic discharge circuit and may overlap a part or the whole of the electrostatic discharge circuit. Therefore, the banks 119 can prevent external light from being reflected by the electrostatic discharge circuit. This allows the edges of the display device 100 to have the same appearance as the regions between the subpixels SP.

[0090] In addition, the bank 119 may overlap some or all of the signal wirings and / or the upper pad PAD1 and / or the lower pad PAD2 at the edge of the display device 100. Therefore, the bank 119 can prevent external light from being reflected by the upper pad PAD1 and / or the signal wirings.

[0091] The bank 119 may have an inclined surface. Specifically, the side surface of the bank 119 may be formed as an inclined surface having a certain slope. The bank 119 may also overlap the upper pad PAD1 or the lower pad PAD2. The bank 119 may cover the area where the upper pad PAD1 and the lower pad PAD2 are arranged.

[0092] A third planarization layer 115c is disposed on the bank 119. The third planarization layer 115c can planarize the upper surface of the first substrate 101 and protect the structure below the third planarization layer 115c. The third planarization layer 115c can be made of an organic insulating material, for example, but is not limited to, a single layer or multiple layers of polyimide or photo acrylic.

[0093] 2b, a plurality of signal lines are arranged on the first substrate 101 at an end of the first substrate 101. The plurality of signal lines may include a plurality of scan lines SL, a plurality of high potential power supply lines VDDL, a plurality of low potential power supply lines VSSL, a plurality of data lines DL, and a plurality of reference lines RL. For convenience of explanation, FIG. 2b shows a second data line DL2 among the plurality of signal lines.

[0094] The second data wiring DL2 may include a first layer DL2-1, a second layer DL2-2, and a third layer DL2-3.

[0095] The second data wiring DL2 may have a jumping line structure through a first layer DL2-1, a second layer DL2-2, and a third layer DL2-3. For example, at least one of the first layer DL2-1, the second layer DL2-2, and the third layer DL2-3 may be a jumping wiring. The first layer DL2-1, the second layer DL2-2, the third layer DL2-3, and the upper pad PAD1 may be connected in parallel to each other through contact holes in an insulating layer disposed between the first layer DL2-1, the second layer DL2-2, the third layer DL2-3, and the upper pad PAD1. This may reduce the resistance of the second data wiring DL2.

[0096] The first layer DL2-1 may be disposed in the same layer as the light-shielding layer LS and may be made of the same conductive material as the light-shielding layer LS, but is not limited thereto.

[0097] A buffer layer 111 and a second layer DL2-2 are disposed on the first layer DL2-1.

[0098] The second layer DL2-2 may be disposed in the same layer as the gate electrode GE and may be formed of the same conductive material as the gate electrode GE, but is not limited thereto.

[0099] The outer end of the second layer DL2-2 may be flush with the outer end of the first layer DL2-1, for example, the outer end of the second layer DL2-2 may overlap with the first line L1 shown in Figures 2A and 2B.

[0100] In addition, the second layer DL2-2 may be arranged to overlap the first layer DL2-1 arranged below. In Fig. 2b, the second layer DL2-2 is shown to be arranged to overlap a portion of the first layer DL2-1, but is not limited thereto, and the second layer DL2-2 may be arranged to completely overlap the front surface of the first layer DL2-1.

[0101] The second layer DL2-2 may be electrically connected to the first layer DL2-1 through a contact hole formed in the buffer layer 111. Thus, the second layer DL2-2 may be connected in parallel with the first layer DL2-1, thereby reducing the resistance of the second data line DL2.

[0102] An interlayer insulating layer 113 and a third layer DL2-3 are disposed on the second layer DL2-2. The third layer DL2-3 may be disposed so as to overlap with the plurality of upper pads PAD1 disposed thereon.

[0103] The third layer DL2-3 may be disposed in the same layer as the source electrode SE and the drain electrode DE and may be formed of the same conductive material as the source electrode SE and the drain electrode DE, but is not limited thereto.

[0104] The outer end of the third layer DL2-3 may be located on the same plane as the ends of the first layer DL2-1 and the second layer DL2-2. For example, the outer end of the third layer DL2-3 may overlap the first line L1 shown in FIGS. 2A and 2B. The third layer DL2-3 may also be located to overlap the second layer DL2-2 and the first layer DL2-1. Although FIG. 2B illustrates the inner end of the third layer DL2-3 as being located between the ends of the second layer DL2-2 and the first layer DL2-1, the location of the inner end of the third layer DL2-3 is not limited thereto.

[0105] The third layer DL2-3 may be electrically connected to the second layer DL2-2 through a contact hole formed in the interlayer insulating layer 113. Therefore, the second layer DL2-2 and the third layer DL2-3 may be implemented in a parallel-connected structure, thereby reducing the resistance of the second data line DL2.

[0106] Meanwhile, an electrostatic discharge circuit may be disposed on the substrate 110 to overlap the plurality of upper pads PAD1. The electrostatic discharge circuit may be disposed in a region between the plurality of upper pads PAD1 and the display area AA. The electrostatic discharge circuit may be electrically connected to the plurality of signal lines through the side lines 140. For example, the electrostatic discharge circuit may be electrically connected to the second data line DL2. When static electricity flows in through the second data line DL2, the electrostatic discharge circuit is turned on to discharge the static electricity to the ground line, thereby blocking the static electricity. Thus, the electrostatic discharge circuit may block or discharge the flow of overcurrent caused by static electricity, thereby preventing damage to the display device 100. That is, the electrostatic discharge circuit may be selectively connected to the ground line and electrically connected to the plurality of signal lines, for example, the second data line DL2, but is not limited thereto.

[0107] In addition, the electrostatic discharge circuit is arranged so as to overlap the upper pad PAD1 and / or the lower pad PAD2, so that the bezel area of ​​the display device 100 can be reduced or eliminated.

[0108] A passivation layer 114 and a plurality of upper pads PAD1 are disposed on the third layer DL2-3.

[0109] The sides of the upper pads PAD1 may be flush with the sides of the signal lines including the second data lines DL2. For example, the outer ends of the upper pads PAD1 may overlap the first lines L1 shown in FIGS. 2A and 2B.

[0110] On the other hand, in FIG. 2b, the plurality of upper pads PAD1 are shown overlapping only with the second data wiring DL2, which is a signal wiring, but each of the plurality of upper pads PAD1 can be arranged to overlap with at least one of the plurality of signal wirings and the plurality of transistors TR.

[0111] The upper pads PAD1 may overlap the second data wirings DL2 or the transistors TR. Therefore, the area between the light-emitting elements LEDs and the edge of the display device 100 may be reduced. For example, the distance between the light-emitting elements LEDs and the edge of the display device 100 may be half the distance between adjacent light-emitting elements LEDs. Therefore, the size of the bezel of the display device 100 may be reduced or the bezel may be eliminated.

[0112] The plurality of upper pads PAD1 are electrically connected to the side wiring 140 described below and the plurality of signal wirings in the display area AA, and can transmit signals to the plurality of sub-pixels SP from the plurality of flexible films and printed circuit boards arranged on the back surface of the substrate 110.

[0113] A plurality of lower pads PAD2 are arranged on the lower surface of the second substrate 102.

[0114] The plurality of lower pads PAD2 can transmit signals from a driver arranged on the rear side of the second substrate 102 to the plurality of side wirings 140, the first substrate 101, the plurality of upper pads PAD1, and the plurality of signal wirings. The plurality of lower pads PAD2 can be arranged at the end of the second substrate 102 in the non-display area NA and electrically connected to the side wirings 140 covering the side surfaces of the second substrate 102.

[0115] The plurality of lower pads PAD2 may be arranged at positions overlapping the plurality of upper pads PAD1, and the plurality of upper pads PAD1 and the plurality of lower pads PAD2 overlapping each other may be electrically connected through side wiring 140. Meanwhile, although not shown in Fig. 2b, a plurality of link wirings and a driving unit including a plurality of flexible films and a printed circuit board may be arranged under the second substrate 102.

[0116] The plurality of link wires can transmit various signals and voltages from the driver to the plurality of signal wires of the display device 100. For example, the plurality of link wires can directly connect the driver to the side wires 140, or can electrically connect the driver to the side wires 140 through other components such as a plurality of upper pads PAD1 and a plurality of lower pads PAD2. The plurality of link wires can include, but are not limited to, a plurality of gate link wires, a plurality of data link wires, a plurality of high potential voltage link wires, a plurality of low potential voltage link wires, and a reference voltage link wire.

[0117] The flexible films are ductile base films on which various components such as gate driver ICs and data driver ICs are arranged, and are components that supply signals to the sub-pixels SP.

[0118] The printed circuit board is a component electrically connected to the flexible films and supplies signals to the driving IC. Various components may be arranged on the printed circuit board to supply various signals, such as driving signals and data signals, to the driving IC. For example, the lower pads PAD2 may be electrically connected to the flexible films or the printed circuit board through link wires, and the flexible films may supply various signals to the side wires 140, the upper pads PAD1, the signal wires, and the sub-pixels SP through the lower pads PAD2 and link wires. Thus, signals from the driving unit may be transmitted to the signal wires and the sub-pixels SP on the front surface of the first substrate 101 through the lower pads PAD2 and side wires 140 of the second substrate 102 and the upper pads PAD1 of the first substrate 101.

[0119] Signals from a driving unit disposed in the lower part of the substrate 110 may be transmitted to a plurality of sub-pixels SP disposed in the upper part of the substrate 110 through the side wiring 140. The side wiring 140 is connected to the driving unit through the lower pad PAD2, and the side wiring 140 may be directly connected to a plurality of signal lines or may be connected to signal lines through the upper pad PAD1.

[0120] Referring to FIG. 2b, after the first substrate 101 and the second substrate 102 are bonded together through the bonding layer 121, the first substrate 101 and the second substrate 102 can be ground up to the first line L1.

[0121] The grinder GR disposed outside the first substrate 101 and the second substrate 102 can grind the side surfaces of the first substrate 101 and the second substrate 102 while rotating around a rotation axis. The grinder GR can grind the side surfaces of the first substrate 101 and the second substrate 102 by moving to a first line L1 that overlaps with the side surfaces of the signal wirings and the pads PAD including the upper pad PAD1 and the lower pad PAD2. Thus, a polished surface formed by the grinder GR can be formed on the side surfaces of the first substrate 101 and the second substrate 102. However, the present invention is not limited thereto, and the side surfaces of the first substrate 101 and the second substrate 102 disposed outside the first line L1 can be removed using various methods such as cutting, sanding, filing, etc.

[0122] In the drawings, for ease of explanation, the multiple pads PADs remaining on the substrate 110 after grinding are shown to have a large area, but in reality, the area of ​​the multiple pads PADs remaining on the substrate 110 may be very small in order to reduce the bezel area and eliminate the sense of difference between adjacent display devices 100 when implementing a tiling display.

[0123] For example, when a tiled display having a large screen is implemented by connecting a plurality of display devices 100, the distance between the sub-pixels SP and the edge of the display device 100 may be half the distance between adjacent sub-pixels SP. Therefore, when a tiled display having a large screen is implemented by connecting a plurality of display devices 100, the difference in distance between the plurality of sub-pixels SP at the boundary of the display device 100 can be prevented from being visible, thereby reducing the sense of difference between the display devices 100.

[0124] The polished surfaces of the first substrate 101 and the second substrate 102 formed by the grinder GR may have a linear shape depending on the shape of the grinder GR. Hereinafter, the side surfaces of the first substrate 101 and the second substrate 102 will be described with reference to Figures 3a and 3b.

[0125] FIG. 3a is a plan view of a subpixel of a display device according to an embodiment of the present disclosure. FIG. 3b is a schematic cross-sectional view of the display device taken along line III-III' of FIG. 3a. FIGS. 3a and 3b are schematic cross-sectional views of a state after a grinding process is completed. FIG. 3a shows only a plurality of upper pads PAD1, a plurality of signal wirings, a plurality of light-emitting elements LED, a plurality of side wirings 140, and a plurality of pixels P on a substrate 110. The display device 100 after the grinding process has been completed has a plurality of side wirings 140 and a side insulating layer 150 added compared to before the grinding process, and the configuration is substantially the same except for the substrate 110, so a redundant description will be omitted.

[0126] 3a and 3b, the side surfaces of the first substrate 101 and the second substrate 102 of the display device 100 are arranged in a linear shape. The side surfaces of the first substrate 101 and the second substrate 102 are arranged in the same plane as the side surfaces of the components of the display device 100 arranged above and below the substrate 110. For example, the side surface of the first substrate 101 may be arranged in the same plane as the side surfaces of the plurality of signal wirings and the plurality of upper pads PAD1, and may be arranged in the same plane as the side surfaces of the plurality of insulating layers arranged on the first substrate 101. The side surface of the second substrate 102 may also be arranged in the same plane as the side surfaces of the plurality of lower pads PAD2 arranged below the second substrate 102.

[0127] Next, a plurality of side wirings 140 are arranged on the side surfaces of the first substrate 101 and the second substrate 102. The plurality of side wirings 140 can electrically connect a plurality of upper pads PAD1 formed on the top surface of the first substrate 101 to a plurality of lower pads PAD2 formed on the rear surface of the second substrate 102, and can connect a plurality of signal wirings formed on the top surface of the first substrate 101 to a plurality of link wirings formed on the rear surface of the second substrate 102.

[0128] Alternatively, the signal lines and the link lines may be connected through the side lines 140 without the need for the lower pads PAD2. The side wirings 140 may be arranged to surround the side surfaces of the display device 100. In this case, the side wirings 140 may not overlap each other and may be spaced apart from each other.

[0129] Each of the multiple side wirings 140 may contact the side surfaces of the multiple upper pads PAD1 at the end of the first substrate 101, the side surfaces of the multiple signal wirings, the side surfaces of the first substrate 101, the side surfaces of the second substrate 102, and the side surfaces of the multiple lower pads PAD2 arranged at the end of the second substrate 102. In this case, if the side surfaces of the substrate 110 are arranged in a direction perpendicular to the top surface of the substrate 110, the multiple side wirings 140 may also be arranged along a direction perpendicular to the top surface of the substrate 110.

[0130] The side wirings 140 may be formed by pad printing using conductive ink, for example, conductive ink containing silver (Ag), copper (Cu), molybdenum (Mo), chromium (Cr), or the like.

[0131] A side insulating layer 150 is disposed to cover the multiple side wirings 140. The side insulating layer 150 may be formed on the top surface of the first substrate 101, the side surface of the first substrate 101, the side surface of the second substrate 102, and the rear surface of the second substrate 102 to cover the side wirings 140. The side insulating layer 150 can protect the multiple side wirings 140.

[0132] On the other hand, if the plurality of side wirings 140 are made of a metal material, problems may occur in that external light is reflected by the plurality of side wirings 140 or light emitted from the light emitting element LED is reflected by the plurality of side wirings 140 and is visible to the user. Therefore, the side insulating layer 150 is configured to include a black material to suppress external light reflection. For example, the side insulating layer 150 may be formed by a pad printing method using an insulating material including a black material, for example, black ink.

[0133] 3a and 3b, a sealing member and an optical film may be further disposed to cover the side insulating layer 150. The sealing member is disposed to surround the side of the display device 100 and can protect the display device 100 from external impacts, moisture, oxygen, etc. For example, the sealing member may be made of an insulating material such as polyimide (PI), polyurethane, epoxy, or acrylic, but is not limited thereto.

[0134] An optical film may be disposed on the sealing member, the side insulating layer 150, and the protective layer 116. The optical film may be a functional film that realizes a higher quality image while protecting the display device 100. For example, the optical film may include, but is not limited to, an anti-glare film, an anti-reflecting film, a low-reflecting film, an OLED transmittance controllable film, or a polarizer.

[0135] In the non-display region of the display device, a plurality of pads for transmitting various signals to a plurality of sub-pixels are arranged on the upper and lower sides of the substrate. The plurality of pads are connected between the side wirings and the plurality of signal wirings in the display region, and can transmit signals to the plurality of sub-pixels from the plurality of flexible films and printed circuit boards arranged below the substrate. In this case, the plurality of pads are arranged in the outer periphery, i.e., bezel region, of the display device. In addition, since the plurality of pads are arranged outside the plurality of signal wirings and the plurality of transistors, a separate area is required for the arrangement of the plurality of pads, which creates a restriction on the reduction of the bezel of the display device.

[0136] Meanwhile, a tiling display has been implemented by arranging a plurality of panels in a tiled form, with the distance between the outermost light emitting element LED of one panel and the outermost light emitting element LED of another adjacent panel being the same as the distance between the light emitting elements LED within one panel. Therefore, if the bezel area of ​​the display device is larger than the distance between the light emitting elements within one display panel due to limitations in reducing the size of the pads, the boundary between the display modules may be visible to the user, which may cause a sense of discontinuity in the displayed image, and in particular, may impose limitations on implementing a large panel through tiling.

[0137] Therefore, in the display device 100 according to one embodiment of the present specification, the pads PAD are arranged to overlap with at least one of the signal wirings and the transistors TR, thereby eliminating a separate area for arranging the pads PAD from the design and reducing the bezel area of ​​the display device 100.

[0138] In addition, in the display device 100 according to an embodiment of the present specification, the side wirings 140 can be formed on the side surfaces of the first upper pad PAD1 and the plurality of lower pads PAD2, and the side surfaces of the substrate 110 can be ground into straight lines. That is, in order to more smoothly connect the gate lines GL and data lines DL on the top surface of the first substrate 101 to the plurality of link lines on the back surface of the second substrate 102, the side surfaces of the substrate 110 can be formed without grinding the side surfaces of the substrate 110 into diagonal lines, which can further simplify the manufacturing process.

[0139] Furthermore, in the display device 100 according to an embodiment of the present specification, the side surface of the substrate 110 is not diagonally ground, and problems that occur when the side surface of the substrate 110 is diagonally ground can be reduced.

[0140] First, defects that may occur in the side wiring 140 and the pads during grinding can be prevented. When a grinding process is performed on the corners of the first and second substrates using a grinder, the side wiring 140 and the pads disposed on the upper and lower portions of the substrates are partially removed along with the substrates, resulting in disconnection of the side wiring 140 and the pads. Furthermore, cracks may be generated and propagate from the grinded side surfaces. Therefore, in the display device 100 according to an embodiment of the present specification, the grinding process is not performed on the side surfaces of the substrate 110, thereby preventing defects that may occur in the side wiring 140 and the pads.

[0141] In addition, the side insulating layer 150 covering the side wirings 140 may be coated from the bottom of the substrate 110 and then filled toward the side and top surfaces 110 of the substrate 110. When the side surfaces of the substrate are diagonally ground, the side insulating layer may not be uniformly formed on the side surfaces of the substrate due to the inclined surfaces formed on the side surfaces of the substrate. Therefore, the side insulating layer may not cover a portion of the top surface and the entire side surfaces of the substrate, resulting in some areas being left unfilled. This may result in problems such as the side wirings being exposed at the unfilled areas, causing external light to be reflected by the side wirings or light emitted from the light emitting device to be reflected by the side wirings and be visible to the user. Therefore, in the display device 100 according to an embodiment of the present specification, the grinding process does not form inclined surfaces on the side surfaces of the substrate 110, allowing the side insulating layer 150 to be uniformly disposed on the side surfaces of the substrate 110, thereby preventing external light reflection from the side wirings 140 at the unfilled areas of the side insulating layer 150.

[0142] 4a is a schematic cross-sectional view of a display device according to another embodiment of the present disclosure before a grinding process. FIG. 4b is a schematic cross-sectional view of a display device according to another embodiment of the present disclosure. A display device 400 according to another embodiment of the present disclosure has substantially the same configuration as the display device 100 according to the embodiment of the present disclosure except for a substrate 410, a plurality of side wirings 440, and a plurality of pads PADs, and therefore, a redundant description will be omitted.

[0143] Referring to FIG. 4a, the side surfaces of the first substrate 101 and the second substrate 402 may be ground. The grinder GR moves to the first line L1 to grind the side surfaces of the first substrate 101 and the second substrate 402. Thus, a ground surface may be formed on the side surfaces of the first substrate 101 and the second substrate 402 by the grinder GR. At this time, the ground surface of the first substrate 101 formed by the grinder GR may be linear according to the shape of the grinder GR. Meanwhile, the side surface of the second substrate 402 may be formed in a different plane from the side surface of the first substrate 101.

[0144] In the following, the side surfaces of the first substrate 101 and the second substrate 402 will be described with reference to FIG. 4b.

[0145] 4b, the substrate 410 of the display device 400 includes side surfaces that are inclined relative to the top surface of the substrate 410. That is, some of the side surfaces of the substrate 410 may be inclined relative to the top surface of the substrate 410.

[0146] First, the side of the first substrate 101 of the display device 400 is disposed in the same plane as the side of the components of the display device 400 disposed on the substrate 410. For example, the side of the first substrate 101 may be disposed in the same plane as the side of each of the signal wirings and the upper pads PAD1, and may be disposed in the same plane as the side of each of the insulating layers disposed on the first substrate 101. In this case, the side of the first substrate 101 may be a plane perpendicular to the upper surface of the substrate 110.

[0147] The side surfaces of the second substrate 402 may be in a different direction from the side surfaces of the components of the display device 400 disposed on the upper surface of the substrate 410. For example, some of the side surfaces of the second substrate 402 may be inclined with respect to the upper surface of the substrate 110.

[0148] Meanwhile, the side surfaces of the plurality of link wirings and the plurality of lower pads PAD2 disposed under the second substrate 402 may include inclined surfaces formed at the same angle as the side surfaces of the second substrate 402. Therefore, as shown in FIG. 4b, the ends of the plurality of link wirings and the plurality of lower pads PAD2 disposed under the second substrate 402 may be disposed inside the end of the substrate 410.

[0149] Next, a plurality of side wirings 440 are arranged on the side surfaces of the first substrate 101 and the second substrate 402. The plurality of side wirings 440 may connect a plurality of upper pads PAD1 having linear side surfaces to a plurality of lower pads PAD2 having inclined side surfaces. In this case, the plurality of side wirings 440 may contact the side surfaces of the first substrate 101 and the inclined side surfaces of the second substrate 402. Therefore, when the plurality of lower pads PAD2 are arranged inside the side surfaces of the second substrate 402, the plurality of side wirings 440 may also contact the lower surface of the substrate 410.

[0150] A side insulating layer 450 is disposed to cover the plurality of side wirings 440. The side insulating layer 450 may be formed to cover the side wirings 440 on the top of the first substrate 101, the side surfaces of the first substrate 101, the side surfaces of the second substrate 402, and the bottom surface of the second substrate 402. The side insulating layer 450 may protect the plurality of side wirings 440.

[0151] In a display device 400 according to another embodiment of the present specification, the bezel area of ​​the display device 400 can be reduced by arranging the pads PAD so as to overlap with at least one of the signal lines and the transistors TR.

[0152] In addition, in a display device 400 according to another embodiment of the present disclosure, the side surface of the substrate 410 may be inclined to reduce contact resistance between the pads. When the side surface of the substrate 410 is inclined, the contact area between the pads and the side wirings 440 may increase. Therefore, the resistance between the signal wirings and the pads may decrease.

[0153] 5 is a schematic cross-sectional view of a display device according to another embodiment of the present specification. The display device 500 according to another embodiment of the present specification has substantially the same configuration as the display device 100 according to the first embodiment of the present specification, except for a plurality of signal lines and a plurality of pads PAD, and therefore, a duplicated description will be omitted.

[0154] 5, a plurality of signal wirings are arranged on the first substrate 101 at the end of the first substrate 101. For convenience of explanation, in FIG. 5, the second data wiring DL2 is shown among the plurality of signal wirings.

[0155] The second data wiring DL2 may include a first layer DL2-1, a second layer DL2-2, and a third layer DL2-3, which are the same as the first layer DL2-1, the second layer DL2-2, and the third layer DL2-3 described with reference to FIGS.

[0156] A passivation layer 114 and a first planarization layer 115a are disposed on the third layer DL2-3.

[0157] Meanwhile, at least one of the first layer DL2-1, the second layer DL2-2, and the third layer DL2-3 constituting the second data wiring DL2 is electrically connected to the plurality of lower pads PAD2 through the side wiring 140, and can supply various signals to the plurality of sub-pixels SP. Therefore, at least one of the first layer DL2-1, the second layer DL2-2, and the third layer DL2-3 constituting the second data wiring DL2 can be referred to as an upper pad, and the plurality of upper pads can be part of the plurality of signal wirings.

[0158] 5 shows that the side surface of the substrate 110 is flush with the side surfaces of the components of the display device 500 disposed on the substrate 110, but some of the side surfaces of the substrate 110 may be inclined with respect to the upper surface of the substrate 110. For example, the side surface of the substrate 110 may include an inclined surface like the side surface of the substrate 410 in FIG. 4B, and the plurality of side wirings 140 may contact the side surfaces of the plurality of signal wirings.

[0159] In the display device 500 according to another embodiment of the present specification, the side wirings 140 can be formed without diagonally grinding the side surface of the substrate 110, which can further simplify the manufacturing process.

[0160] In addition, in a display device 500 according to another embodiment of the present specification, the side of the substrate 110 is not grinded diagonally, and the problem of the side wiring 140 and the plurality of pads PAD being partially removed during grinding, which causes the side wiring 140 and the plurality of pads PAD to be disconnected, can be prevented.

[0161] In addition, in a display device 500 according to another embodiment of the present specification, an inclined surface is not formed on the side of the substrate 110 during the grinding process, and the side insulating layer 150 can be uniformly disposed on the side of the substrate 110, thereby preventing external light reflection from the side wiring 140.

[0162] In addition, in the display device 500 according to another embodiment of the present specification, some of the signal lines can be used as pads without disposing separate pads at the ends of the display device 500. In the display device 500 according to another embodiment of the present specification, the side lines 140 can contact the sides of the signal lines. Therefore, signals applied from the driving unit can be transmitted to the pixels SP without disposing conductive material for forming pads. Therefore, in the display device 500 according to another embodiment of the present specification, a separate process for forming conductive material for forming pads is not performed, thereby simplifying the manufacturing process of the display device and reducing costs.

[0163] A display device according to an embodiment of the present specification can be described as follows.

[0164] A display device according to one embodiment of the present specification includes a substrate on which a plurality of light-emitting elements are arranged, transistors arranged on the substrate, a plurality of signal wirings arranged on the substrate, a plurality of link wirings arranged below the substrate, and a plurality of upper pads arranged on the substrate and connected to the plurality of signal wirings, the plurality of upper pads being arranged to overlap at least one of the plurality of signal wirings and the plurality of transistors.

[0165] According to another feature of the present disclosure, the semiconductor device may further include a plurality of side wirings connecting the plurality of signal wirings and the plurality of link wirings, and the plurality of upper pads and the plurality of signal wirings may be in contact with the plurality of side wirings.

[0166] According to another feature of the present disclosure, the side surfaces of the plurality of upper pads may be disposed flush with the side surfaces of the plurality of signal wirings.

[0167] According to yet another feature of the present disclosure, the plurality of side wirings may contact the side and bottom surfaces of the substrate.

[0168] According to another feature of the present specification, the semiconductor device may further include a plurality of lower pads arranged on the lower surface of the substrate and connected to the plurality of link wirings, and the plurality of lower pads may be arranged in positions overlapping the plurality of upper pads.

[0169] According to another feature of the present specification, a portion of the side surface of the substrate is an inclined surface inclined with respect to the upper surface of the substrate, and the plurality of side wirings can cover a portion of the side surface and the lower surface of the substrate.

[0170] According to another feature of the present specification, the substrate includes a first substrate and a second substrate disposed below the first substrate, and a portion of a side surface of the second substrate may be an inclined surface inclined with respect to an upper surface of the substrate.

[0171] According to another feature of the present disclosure, the semiconductor device may further include a plurality of lower pads disposed on a lower surface of the substrate and connected to the plurality of link wirings, and ends of the lower pads may be located inward from an end of the substrate.

[0172] According to another feature of the present specification, the semiconductor device may further include a plurality of insulating layers disposed on the substrate and above or below the plurality of signal wirings and the plurality of upper pads, and sides of the insulating layers may be disposed flush with sides of the substrate.

[0173] According to another feature of the present disclosure, the side surfaces of the insulating layers and the side surfaces of the upper pads may be disposed on the same plane.

[0174] According to yet another feature of the present disclosure, the plurality of upper pads may be part of a plurality of signal traces.

[0175] According to still another feature of the present disclosure, the device may further include an electrostatic discharge circuit disposed on the substrate so as to overlap the plurality of upper pads.

[0176] Although the embodiments of the present specification have been described in more detail above with reference to the accompanying drawings, the present specification is not necessarily limited to such embodiments. Therefore, the embodiments disclosed in the present specification are not intended to limit the technical concept of the present specification. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not limiting. The present specification should be interpreted within the scope of the following claims and all technical concepts within the scope equivalent thereto.

Claims

1. substrate; a plurality of light-emitting elements disposed on the substrate; a plurality of transistors disposed on the substrate; a plurality of signal wirings disposed on the substrate; a plurality of link wires disposed beneath the substrate; and a plurality of upper pads disposed on the substrate; A display device, wherein each of the plurality of upper pads is arranged so as to overlap with at least one of the plurality of signal wirings and / or the plurality of transistors.

2. The display device according to claim 1 , wherein a side surface of the substrate is disposed on the same plane as a side surface of the plurality of signal wirings.

3. Further comprising a plurality of side wirings arranged on the side surfaces of the substrate; 3. The display device according to claim 1, wherein each of the plurality of side wirings connects a corresponding one of the plurality of link wirings to a corresponding one of the plurality of signal wirings.

4. The display device according to claim 3 , wherein the plurality of side wirings are in contact with side surfaces of the substrate and selectively in contact with a lower surface of the substrate.

5. a plurality of lower pads disposed on a lower surface of the substrate and overlapping corresponding upper pads among the plurality of upper pads; The display device of claim 3 , wherein the plurality of side wirings connect the plurality of lower pads to the plurality of upper pads and / or the plurality of side wirings.

6. Further comprising a side insulating layer covering the plurality of side wirings, The display device of claim 3 , wherein the side insulating layer selectively includes a light-shielding material and / or a black material.

7. a part of a side surface of the substrate is an inclined surface inclined with respect to an upper surface of the substrate, The display device according to claim 3 , wherein the plurality of side wirings cover a part of the side surface of the substrate and selectively cover a part of the lower surface of the substrate.

8. the substrate includes a first substrate and a second substrate disposed below the first substrate; The display device according to claim 7 , wherein a part of the side surface of the second substrate is an inclined surface inclined with respect to the upper surface of the substrate.

9. The display device according to claim 3 , wherein each of the plurality of side wirings is in contact with a corresponding one of the plurality of upper pads and / or a corresponding one of the plurality of signal wirings.

10. Each of the plurality of upper pads is electrically connected to a corresponding one of the plurality of signal wirings; or The display device according to claim 1 , wherein the side surfaces of the upper pads are arranged on the same plane as the side surfaces of the signal wirings.

11. a plurality of lower pads disposed on a lower surface of the substrate and connected to corresponding link wires among the plurality of link wires; Each of the plurality of lower pads is disposed to overlap a corresponding one of the plurality of upper pads; or The display device according to claim 1 , wherein ends of the plurality of lower pads are disposed inside an end of the substrate.

12. further comprising a plurality of insulating layers disposed on the substrate; the insulating layers are disposed above or below the upper pads and / or the signal wirings; The display device according to claim 1 , wherein the side surfaces of the insulating layers are arranged flush with the side surfaces of the substrate and / or the side surfaces of the upper pads.

13. the plurality of light-emitting elements are micro LEDs including an inorganic active layer; or Each of the plurality of light emitting elements comprises: n-type layer; an active layer on the n-type layer; a p-type layer on the active layer; an n-electrode on the n-type layer; and a p-electrode disposed on the p-type layer and spaced apart from the p-type layer; The display device of claim 1 , wherein the p-electrode and the n-electrode have different height levels.

14. The display device of claim 13 , further comprising a first electrode connected to the n-electrode and a second electrode connected to the p-electrode.

15. first planarization layer; a second planarization layer on the first planarization layer; and further comprising a third planarization layer on the second planarization layer; the first electrode and the second electrode are spaced apart from each other, and the third planarization layer is disposed between the first electrode and the second electrode; The display device of claim 14 , wherein the second planarization layer and the third planarization layer are selectively in contact with each other in a region between the first electrode and the second electrode.

16. further comprising a bank disposed on the first electrode and the second electrode; the bank overlaps a portion of at least one of the plurality of upper pads; 16. The display device according to claim 14, wherein the bank selectively contains a light-shielding material and / or a black material.

17. Further comprising a reflective layer corresponding to each of the plurality of light-emitting elements, The display device according to claim 13 , wherein the plurality of light-emitting elements overlap the reflective layer.

18. further comprising an electrostatic discharge circuit disposed on the substrate and selectively connecting the plurality of signal lines and a ground line; the electrostatic discharge circuit is disposed between the plurality of upper pads and a display area in which a plurality of sub-pixels are disposed; or The display device of claim 1 , wherein the display device overlaps the plurality of upper pads.

19. each of the plurality of signal lines includes at least two signal lines connected in parallel to overlap each other; Optionally, the signal wiring further includes an insulating layer disposed between the at least two signal wirings; The display device of claim 1 , wherein the insulating layer includes a contact hole connecting the at least two signal lines.

20. the plurality of signal lines are connected in parallel to corresponding upper pads among the plurality of upper pads; Optionally, the insulating layer may be disposed between the upper pads and the signal wirings; The display device of claim 1 , wherein the insulating layer includes contact holes electrically connecting the signal lines and the upper pads.

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