Display device

Abstract

To provide a display device capable of improving its image quality.SOLUTION: The display device has a plurality of pixel blocks in a display area, and the pixel block includes one first circuit and a plurality of second circuits. The first circuit has a function of adding plural pieces of data supplied from a source driver. The second circuit includes a display element and a function of performing displaying according to the added data. One pixel is configured to include one second circuit and an element of the first circuit shared. Sharing the first circuit with the plurality of pixels improves a numerical aperture.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] One aspect of the present invention relates to a display device.

[0002] Note that one embodiment of the present invention is not limited to the above technical fields. The technical field of one aspect relates to an article, a method, or a manufacturing method. One aspect of the present invention is a process, machine, manufacture, or composition. Therefore, the invention disclosed herein more specifically relates to The technical field of one aspect of the present invention is a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a lighting device, device, power storage device, storage device, imaging device, operation method thereof, or manufacturing method thereof One example can be mentioned.

[0003] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. The term generally refers to a semiconductor device. A transistor and a semiconductor circuit are examples of a semiconductor device. A display device, an imaging device, or an electronic device may include a semiconductor device. [Background technology]

[0004] A technology for constructing a transistor using a metal oxide formed on a substrate has been attracting attention. For example, a transistor using zinc oxide or In-Ga-Zn oxide is used for the display of a display device. The technology used for the basic switching elements is disclosed in Patent Document 1 and Patent Document 2. .

[0005] In addition, a memory device having a structure in which a transistor with extremely low off-state current is used as a memory cell is disclosed in a patent document. This is disclosed in reference 3.

[0006] Furthermore, various improvements and applications have been attempted for liquid crystal display devices. Patent Document 4 discloses a transparent display that displays images by sequential operations. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-123861 [Patent Document 2] Japanese Patent Application Laid-Open No. 2007-96055 [Patent Document 3] Japanese Patent Application Laid-Open No. 2011-119674 [Patent Document 4] Japanese Patent Application Publication No. 2018-21974 Summary of the Invention [Problem to be solved by the invention]

[0008] Display devices are becoming increasingly high-resolution, with 8K4K (pixel count: 7680 x 4320) resolution or Hardware that can display at higher resolutions is being developed. The introduction of HDR (High Dynamic Range) display technology, which improves image quality through adjustments, is also progressing. There is.

[0009] To display clear gradations, the range of data potentials that can be supplied to the display elements must be wide. On the other hand, for example, the output voltage of a source driver for a liquid crystal display device is about 15V. To supply a voltage higher than this to the display element, a high-output source driver must be used. High-output source drivers consume a lot of power, so a new driver IC must be developed. Sometimes it has to be.

[0010] In addition, to display moving images more smoothly, it is necessary to increase the frame frequency. As the number of pixels increases, the horizontal period becomes shorter, making it difficult to increase the frame frequency. By realizing a configuration that makes it easy to increase the frame frequency, field sequential This also makes it easier to apply to liquid crystal display devices.

[0011] While it is desirable to solve the above problems, increasing the number of components in the pixel circuit reduces the aperture ratio. Therefore, it is preferable to configure the pixel circuit with fewer elements.

[0012] Therefore, one aspect of the present invention is to provide a display device that can improve image quality. One of the purposes is to supply a voltage to the display element that is equal to or higher than the output voltage of the source driver. It is another object of the present invention to provide a display device capable of displaying an image with high brightness. It is an object of the present invention to provide a display device that can improve the image quality. It is an object of the present invention to provide a display device capable of increasing the wave number of pixels. An object of the present invention is to provide a display device that can increase the aperture ratio.

[0013] Another object is to provide a display device with low power consumption. One of the purposes is to provide a new display device. Another object of the present invention is to provide a method for driving the display device. Another object is to provide a novel semiconductor device or the like.

[0014] The description of these problems does not preclude the existence of other problems. It is not necessary for the present invention to solve all of these problems. The above will be made clear from the description, drawings, claims, etc. It is possible to extract other issues from the descriptions in the patent, claims, etc. [Means for solving the problem]

[0015] One aspect of the present invention relates to a display device capable of improving image quality.

[0016] One aspect of the present invention is a display device having a plurality of pixel blocks, The first circuit and the second circuits are electrically connected. The first circuit adds the first data and the second data to generate third data. a second circuit having a function of holding third data and a function of outputting a second signal in response to the third data; It is a display device that has a display function.

[0017] The first circuit includes a first transistor, a second transistor, and a first capacitor. One of the source and drain of the first transistor is connected to one electrode of the first capacitor. The other electrode of the first capacitor is electrically connected to the source or can be electrically connected to the other of the drains.

[0018] The third transistor is further provided, and one of the source and drain of the third transistor is , the other electrode of the first capacitor element, and the source or The other of the drains and the other of the source or drain of the second transistor are electrically connected It may be done.

[0019] The second circuit has a third transistor and a third circuit, and the third transistor One of the source and drain of the first transistor is electrically connected to one of the source and drain of the second transistor. The other of the source and drain of the third transistor is electrically connected to the third circuit. The third circuit may be electrically connected to the display element.

[0020] The third circuit includes a fourth transistor, a second capacitor, and a light-emitting element that functions as a display element. and a gate of the fourth transistor is connected to the source or drain of the third transistor. The other of the source and drain of the fourth transistor is electrically connected to The first electrode of the light-emitting element is electrically connected to the second capacitor element. The other electrode of the second capacitor is electrically connected to one electrode of the fourth transistor. It may be configured to be electrically connected to the gate.

[0021] The fifth transistor is further provided, and one of the source and drain of the fifth transistor is , electrically connected to one electrode of the light-emitting element, and the source or drain of the fifth transistor The other terminal of the first transistor is electrically connected to one of the source and drain of the fourth transistor. The other of the source and drain of the fifth transistor is electrically connected to one electrode of the second capacitor element. The power supply may be electrically connected.

[0022] Alternatively, the third circuit has a liquid crystal element as a display element, and one electrode of the liquid crystal element is connected to the third The gate electrode may be electrically connected to one of the source and the drain of the transistor. The liquid crystal display device further includes a third capacitor element, and one electrode of the third capacitor element is connected to one electrode of the liquid crystal element. They may be electrically connected.

[0023] The fourth circuit may further include a fourth circuit and a fifth circuit. The fifth circuit may have a function of controlling the second circuit, and the fifth circuit may have a function of controlling the second circuit.

[0024] The pixel block has a plurality of pixels, and any one of the plurality of pixels is a first circuit A pixel having a plurality of elements of the first circuit has a vertical length longer than other pixels. It may also be large.

[0025] The transistor included in the pixel block has a metal oxide in a channel formation region, The materials are In, Zn, and M (M is Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd or Hf). [Effects of the Invention]

[0026] To provide a display device capable of improving image quality by using one embodiment of the present invention. Alternatively, a voltage higher than the output voltage of the source driver can be supplied to the display element. Alternatively, it is possible to provide a display device that can increase the brightness of a displayed image. Alternatively, a display device capable of increasing the frame frequency can be provided. Alternatively, a display device capable of increasing the aperture ratio of a pixel can be provided. It is possible.

[0027] Alternatively, a display device with low power consumption can be provided. Alternatively, a novel display device or the like can be provided. Furthermore, a method for operating the display device can be provided. Alternatively, a novel semiconductor device or the like can be provided. It can be provided. [Brief explanation of the drawings]

[0028] [Figure 1] 1A and 1B are diagrams illustrating a display device. [Figure 2] FIG. 2 is a diagram illustrating a pixel block. [Figure 3] FIG. 2 is a diagram illustrating a selection circuit. [Figure 4] FIG. 2 is a diagram illustrating a pixel block. [Figure 5] 4 is a timing chart illustrating the operation of a pixel block. [Figure 6] 1A and 1B are diagrams illustrating pixel blocks. [Figure 7] 4 is a timing chart illustrating the operation of a pixel block. [Figure 8] 1A to 1D are diagrams illustrating circuit blocks. [Figure 9] 1A to 1D are diagrams illustrating circuit blocks. [Figure 10] 1A to 1C are diagrams illustrating circuit blocks. [Figure 11] 1A and 1B are diagrams illustrating pixel blocks. [Figure 12] FIG. 1 is a diagram illustrating a gate driver. [Figure 13] FIG. 1 is a diagram illustrating a gate driver. [Figure 14] FIG. 1 is a diagram illustrating a gate driver. [Figure 15] (A) and (B) Schematics explaining the gate driver. [Figure 16] (A) and (B) Schematics explaining the gate driver. [Figure 17] (A) and (B) Schematics explaining the gate driver. [Figure 18] FIG. 2 is a diagram illustrating the configuration of a pixel block used in a simulation. [Figure 19] 1 is a timing chart used in a simulation. [Figure 20] (A) and (B) Schematic illustrating the simulation results. [Figure 21]FIG. 2 is a diagram illustrating a pixel layout. [Figure 22] (A) and (B) are diagrams illustrating pixel layouts. [Figure 23] FIG. 10 is a diagram illustrating the results of calculation of the aperture ratio. [Figure 24] 1A to 1C are diagrams illustrating a display device. [Figure 25] (A) and (B) are diagrams illustrating the touch panel. [Figure 26] 1A and 1B are diagrams illustrating a display device. [Figure 27] 1A and 1B are diagrams illustrating a display device. [Figure 28] 1A and 1B are diagrams illustrating a display device. [Figure 29] 1A and 1B are diagrams illustrating a display device. [Figure 30] 1A to 1E are diagrams illustrating a display device. [Figure 31] 1A to 1C are diagrams illustrating a transistor. [Figure 32] 1A to 1C are diagrams illustrating a transistor. [Figure 33] 1A to 1C are diagrams illustrating a transistor. [Figure 34] 1A to 1C are diagrams illustrating a transistor. [Figure 35] (A) to (F) are diagrams illustrating electronic devices. DETAILED DESCRIPTION OF THE INVENTION

[0029] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. The present invention may be modified in various forms and details without departing from the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that the present invention can be modified in various ways. The present invention is not limited to the above-described embodiments. In the drawings, the same reference numerals are used to designate the same parts or parts having similar functions. The same elements in the drawings are used interchangeably, and repeated explanations may be omitted. In some cases, the timing may be omitted or changed as appropriate between different drawings.

[0030] In addition, even if a circuit diagram shows a single element, there may be functional problems. If there is no need for a single element, the element may be composed of multiple elements. For example, a transistor that operates as a switch may be used. In some cases, multiple resistors may be connected in series or in parallel. In some cases, the sensor may be divided and placed in multiple positions.

[0031] In addition, when one conductor has multiple functions such as wiring, electrode, and terminal, In this specification, the same element may be referred to by multiple names. Even if the circuit diagram shows direct connections between elements, In some cases, the elements are connected via multiple conductors, and in this specification, Even configurations such as this are included in the category of direct connection.

[0032] (Embodiment 1) In this embodiment, a display device which is one embodiment of the present invention will be described with reference to drawings.

[0033] One embodiment of the present invention is a display device having a plurality of pixel blocks in a display area. The lock has a first circuit and a plurality of second circuits electrically connected to the first circuit. The first circuit has a function of adding multiple pieces of data supplied from the source driver. Therefore, it is possible to generate a voltage equal to or higher than the output of the source driver.

[0034] The second circuit has a display element and has a function of displaying the added data. One pixel is configured to include one second circuit and the elements of the shared first circuit. The first circuit has more components (including wiring) and occupies a larger area than the second circuit. Therefore, the aperture ratio can be improved by sharing the first circuit among a plurality of pixels.

[0035] FIG. 1 illustrates a display device according to one embodiment of the present invention. The display device includes a pixel block 12. The display device includes a source driver 13, gate drivers 14a and 14b, and a circuit 15. Although an example in which two gate drivers are provided is shown, one gate driver may be provided.

[0036] The display area is made up of a plurality of regularly arranged pixel blocks 12. 2 has a circuit 11 and n circuits 10 (n is a natural number of 2 or more). The circuit 11 and one circuit 10 function as one pixel. That is, the circuit 11 is configured to be shared by a plurality of pixels.

[0037] The circuit 10 adds the second data to the first data by capacitive coupling to generate the third data. The circuit 10 has a display element, a function of storing third data, and a function of generating a third image. 3. The display element has the function of displaying the image according to the data.

[0038] The circuit 10 included in one pixel block 12 is arranged in the direction in which the source lines extend (vertical direction). The more circuits 10 there are, the more the elements of the circuit 11 can be arranged in the occupied area of ​​each pixel. By distributing the electrodes in a distributed manner, the aperture ratio can be improved.

[0039] The more circuits 10 a pixel block 12 has, the higher the aperture ratio becomes. Considering the reading time, it is preferable to arrange multiple pixel blocks per line. .

[0040] In the case of a display device with high resolution, it is necessary to write in a short horizontal period. If the number of wirings is too large, the capacitance of the wiring connecting the circuit 11 and the circuit 10 increases. This results in a defect where writing cannot be completed within the period. The circuit 10 included in the block has an aperture ratio, a resolution (horizontal period), and a circuit 11 connected to the circuit 10. It is preferable to set an appropriate number in consideration of several conditions such as the capacitance of the wiring to be connected.

[0041] If you want to efficiently increase the aperture ratio, the simulation results described later suggest that n should be between 5 and 10. 0 or less, preferably 10 to 50, more preferably 20 to 40. In this range, it is estimated that the capacitance of the wiring connecting the circuit 11 and the circuit 10 is sufficiently small. Since the horizontal period is long enough, the effect of the horizontal period can be ignored. If possible, n may be set to about 100 to 1000.

[0042] 2 shows a specific example of the pixel block 12. The pixel block 12 includes a circuit 11 and a plurality of circuits. The circuit 10 (circuits 10[1] to [n]) has: The area in which one of them is arranged is defined as pixels 20[1] to [n].

[0043] The circuit 11 includes a transistor 101, a transistor 102, and a capacitor 104. One of the source and the drain of the transistor 101 can be connected to a capacitor. The other electrode of the capacitor 104 is electrically connected to one electrode of the transistor 104. The transistor 102 is electrically connected to either the source or the drain of the transistor 102 .

[0044] The circuit 10 may include a transistor 103 and a circuit block 110. The circuit block 110 includes a transistor, a capacitance element, a display element, and the like. One of the source and drain of the transistor 103 can be a transistor. The source or drain of the transistor 103 is electrically connected to the source or drain of the transistor 101. The other of the source and drain is electrically connected to the circuit block 110 .

[0045] Here, one of the source and drain of the transistor 101 and one of the capacitors 104 The wiring connecting the electrode and either the source or the drain of the transistor 103 is referred to as a node N The other of the source and drain of the transistor 103 and the circuit block 1 The wiring connecting the two nodes 10 and 11 is called node NP. Node NP can be floating. At this time, the display element included in the circuit block 110 operates in accordance with the potential of the node NP.

[0046] The elements of the circuit 10 and the circuit 11 and the connections between the elements and the various wirings will be described. The gate of the transistor 101 is electrically connected to a wiring 121. The gate of the transistor 102 is electrically connected to a wiring 122. The gate of the transistor 103 is electrically connected to a wiring 123. The other of the source and the drain of the transistor 101 is electrically connected to a wiring 125. The other of the source and the drain of the transistor 102 is electrically connected to the wiring 126. is connected to.

[0047] The wirings 121, 122, and 123 (123[1] to [n]) function as gate lines. For example, the wirings 121 and 122 are electrically connected to the gate driver 14a. The wiring 123 is electrically connected to the gate driver 14b. It functions as a source line and is electrically connected to the source driver 13 via the circuit 15. (See Figure 1.)

[0048] The circuit 15 can be configured as shown in Fig. 3. The circuit 15 serves as a selection circuit. The potential input from the source driver 13 is output to the wiring 125 or the wiring 126. In addition, the wiring 126 can be supplied with a potential “V ref (For example, a base such as 0V The output control of each potential is controlled by the transistors connected to each wiring. Transistor connected to signal V ref _EN, 125_EN, and 126_EN In addition, the circuit 15 may not be provided.

[0049] In the circuit 11, first, the first data (weight: W) is written to the node NM. The other electrode of the capacitor 104 is connected to a “V ref " is supplied to the capacitor element 104, and "WV re f Next, the node NM is set to a floating state, and the other potential of the capacitor 104 is set to a When the second data (data: D) is supplied to the node NM, the potential of the node NM becomes " WV ref +D”.

[0050] Here, “W” = “D”, “V ref ”=0V and the capacitance of node NM is sufficiently small. If the voltage of the node NM is "2D" or "2W", the voltage of the output of the source driver 13 is "2D" or "2W". This means that approximately twice the potential can be output to node NM. Applications that require high voltage even when used (for example, liquid crystal elements that require high voltage for gradation control) It can be used for driving general liquid crystal elements, light emitting elements, etc. Therefore, the voltage supplied from the source driver 13 can be reduced to about half, Power consumption can be reduced.

[0051] In addition, correction data may be supplied as the first data (weight: W). Correcting the brightness variations inherent to the display device by adding correct data to the image data It is also possible to correct the brightness on a pixel-by-pixel basis, so it can be used for HDR display. In addition, when a light-emitting element is used as a display element, the display quality is affected by the driving transistor. Since the threshold voltage of the transistor is affected by variations in the threshold voltage, the threshold voltage correction data of the transistor is The first data (weight: W) may be supplied to improve the display quality. The data (weight: W) and the second data (data: D) may be interchanged.

[0052] In one aspect of the present invention, the transistors of a particular circuit 10 are connected in accordance with the above-described potential addition operation. The potential of the node NP (=the potential of the node NM) is determined by keeping the node 103 conductive. By performing such an operation sequentially from the circuit 10[1] to the circuit 10[n], The potential of the node NP can be determined, i.e., different image data can be provided to each pixel. can be provided.

[0053] The nodes NM and NP act as storage nodes. By turning on the transistor, data can be written to each node. By making the transistor non-conductive, the data can be held in each node. By using a transistor with extremely low off-state current as the resistor, leakage current can be suppressed. This makes it possible to hold the potential of each node for a long time. In this paper, we use a transistor (hereinafter referred to as OS transistor) that uses a metal oxide for the channel formation region. You can be there.

[0054] Specifically, OS transistors can be used as the transistors 101, 102, and 103. It is also preferable to use OS transistors for the elements included in the circuit block 110. In addition, when operating within an allowable range of leakage current, Si is used in the channel formation region. Alternatively, a transistor having a silicon nitride film (hereinafter referred to as a silicon transistor) may be used. The Si transistor may be used in combination with a silicon transistor. , amorphous silicon transistors, crystalline silicon (typically low-temperature poly Examples include transistors using silicon (polysilicon, single crystal silicon).

[0055] The semiconductor material used for the OS transistor has an energy gap of 2 eV or more. Metal oxides having a specific resistance of 2.5 eV or more, more preferably 3 eV or more, can be used. A typical example is an oxide semiconductor containing indium, for example, a CAAC -OS or CAC-OS can be used. CAAC-OS forms a crystal. The atoms are stable, making it suitable for transistors where reliability is important. Because it exhibits high mobility, it is suitable for use in transistors that operate at high speed.

[0056] Since the energy gap of the semiconductor layer of an OS transistor is large, the current is several yA / μm (channel The OS transistor exhibits extremely low off-state current characteristics (current value per 1 μm of transistor width). The stan- dard is free from impact ionization, avalanche breakdown, and short channel effects. These features differ from those of Si transistors, making it possible to form highly reliable circuits. In addition, the variation in electrical characteristics caused by the non-uniformity of crystallinity, which is a problem in Si transistors, This is less likely to occur with OS transistors.

[0057] The semiconductor layer of the OS transistor is made of, for example, indium, zinc, and M (aluminum). , titanium, gallium, germanium, yttrium, zirconium, lanthanum, cerium In-M-Zn oxides containing metals such as tin, neodymium, or hafnium The film can be made of a material such as a silicon dioxide film.

[0058] When the oxide semiconductor constituting the semiconductor layer is an In-M-Zn oxide, The atomic ratio of the metal elements in the sputtering target used to form a film is In≧M It is preferable that Zn≧M is satisfied. The atomic ratios were In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In :M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4. 1, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5: The atomic ratio of the semiconductor layers to be formed is preferably 1:8 or the like. This includes a ±40% variation in the atomic ratio of metal elements contained in the ring target.

[0059] The semiconductor layer is made of an oxide semiconductor with a low carrier density. Carrier density is 1×10 17 / cm 3 Less than 1 × 10 15 / cm 3 Further details are as follows: Preferably 1 x 10 13 / cm 3 Less than or equal to 1×10 11 / cm 3 Below, further Preferably 1 x 10 10 / cm 3 Less than 1 x 10 -9 / cm 3 More than career secrets Such an oxide semiconductor can be a highly pure intrinsic or This oxide semiconductor has a low density of defect states and is stable. It can be said that this oxide semiconductor has stable characteristics.

[0060] However, the semiconductor characteristics and electrical characteristics (field effect) of the required transistors are not limited to these. It is sufficient to use an appropriate composition depending on the required properties (e.g., the mobility, threshold voltage, etc.). In order to obtain the semiconductor characteristics of a transistor, the carrier density, impurity concentration, and defect density of the semiconductor layer must be carefully considered. It is preferable to appropriately set the density, atomic ratio of metal element to oxygen, interatomic distance, density, etc. stomach.

[0061] In the oxide semiconductor that constitutes the semiconductor layer, silicon and carbon, which are group 14 elements, If oxygen is contained, oxygen vacancies increase, causing the semiconductor layer to become n-type. The concentrations of phosphate and carbon (obtained by secondary ion mass spectrometry) were measured at 2 × 10 18 atom s / cm 3 Less than or equal to 2 x 1017 atoms / cm 3 The following applies.

[0062] In addition, alkali metals and alkaline earth metals generate carriers when bonded with oxide semiconductors. This may result in an increase in the off-state current of the transistor. The concentration of alkali metals or alkaline earth metals in the conductor layer (measured by secondary ion mass spectrometry) The concentration obtained is 1 x 10 18 atoms / cm 3 Less than or equal to 2 x 10 16 a toms / cm 3 Do the following:

[0063] In addition, if nitrogen is contained in the oxide semiconductor that constitutes the semiconductor layer, electrons, which are carriers, This increases the carrier density and makes it easier to become n-type. Transistors using conductors tend to be normally-on. The nitrogen concentration (obtained by secondary ion mass spectrometry) was 5 x 10 18 atoms / cm 3 It is preferable to do the following:

[0064] In addition, if hydrogen is contained in the oxide semiconductor that constitutes the semiconductor layer, the oxide that bonds with the metal atoms Since the oxygen reacts with oxygen to form water, oxygen vacancies may be formed in the oxide semiconductor. If the channel formation region in the conductor contains oxygen vacancies, the transistor will be normally on. Furthermore, defects in which hydrogen has entered the oxygen vacancies act as donors, In addition, some of the hydrogen atoms bond with the metal atoms, resulting in the generation of carrier electrons. It may combine with hydrogen to generate electrons, which are carriers. A transistor including an oxide semiconductor having such a structure tends to be normally on.

[0065] A defect in which hydrogen is inserted into an oxygen vacancy can function as a donor in an oxide semiconductor. However, it is difficult to quantitatively evaluate the defects. Therefore, in this specification, the acid As a parameter of the compound semiconductor, we assume a state in which no electric field is applied, rather than the donor concentration. In other words, the "carrier concentration" described in this specification and the like is This can sometimes be rephrased as "donor concentration."

[0066] Therefore, it is preferable that the amount of hydrogen in the oxide semiconductor be reduced as much as possible. In oxide semiconductors, secondary ion mass spectrometry (SIMS) The hydrogen concentration obtained by mass spectrometry was calculated as 1×10 20 a toms / cm 3 Less than 1 x 10 19 atoms / cm 3 Less than, more preferably is 5 x 10 18 atoms / cm 3 less than 1×10 18 atoms / c m 3 The oxide semiconductor in which impurities such as hydrogen are sufficiently reduced is used as the transistor chip. By using it in the channel forming region, stable electrical characteristics can be imparted.

[0067] The semiconductor layer may also have a non-single crystal structure, for example. The non-single crystal structure may have a c-axis orientation. CAAC-OS (C-Axis Aligned Crystalline ne Oxide Semiconductor), polycrystalline, microcrystalline, or non-crystalline Among non-single crystalline structures, the amorphous structure has the highest defect level density and CAA C-OS has the lowest density of defect states.

[0068] An amorphous oxide semiconductor film has, for example, a disordered atomic arrangement and does not contain crystalline components. Alternatively, the amorphous oxide film may have a completely amorphous structure and no crystalline portion. stomach.

[0069] The semiconductor layer may have an amorphous structure, a microcrystalline structure, a polycrystalline structure, or a CAAC structure. The film may be a mixed film having two or more of the -OS region and the single crystal structure region. The film may have a single layer structure including two or more of the above-mentioned regions, or a laminated structure. It may have a structure.

[0070] Hereinafter, we will discuss CAC (Cloud-Aligned C), which is one type of non-single-crystal semiconductor layer. This section explains the structure of the .NET composite OS.

[0071] CAC-OS is a type of oxide semiconductor in which the elements constituting the oxide semiconductor are 0.5 nm to 10 nm thick. Preferably, the material is unevenly distributed in a size range of 1 nm to 2 nm or in the vicinity thereof. In the following, it is assumed that one or more metal elements are contained in the oxide semiconductor. The region containing the metal element is unevenly distributed and has a size of 0.5 nm to 10 nm, preferably 1 nm A mixed state of particles with sizes of 2 nm or less or close to that size is called a mosaic or patch state. It is also called.

[0072] Note that the oxide semiconductor preferably contains at least indium. In addition to these, aluminum, gallium, yttrium, and zinc are preferably contained. Thorium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium Rumanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, Contains one or more selected from tantalum, tungsten, magnesium, etc. It may be included.

[0073] For example, CAC-OS made of In-Ga-Zn oxide (In-Ga-Zn oxide among CAC-OS) α-Zn oxide may be specifically referred to as CAC-IGZO. (Hereinafter, InO X1 (X1 is a real number greater than 0) or indium zinc oxide compound (hereinafter referred to as In X2 Zn Y2 O Z2 (X2, Y2, and Z2 are real numbers greater than 0) ) and gallium oxide (hereinafter referred to as GaO X3 (X3 is a real number greater than 0) . ), or gallium zinc oxide (Ga X4 Zn Y4 O Z4 (X4, Y4, and Z4 is a real number greater than 0.) The material is separated into two parts, forming a mosaic pattern. Mosaic InO X1 , or In X2 Zn Y2 O Z2 is uniformly distributed in the film This is a cloud-like configuration (hereinafter also referred to as "cloud-like").

[0074] In other words, CAC-OS is X3 The region where In is the main component and X2 Zn Y2 O Z2 , or InO X1A composite oxide semiconductor having a structure in which a region in which In this specification, for example, the atomic ratio of In to the element M in the first region is is greater than the atomic ratio of In to the element M in the second region. Compared to region 2, the concentration of In is higher.

[0075] IGZO is a common name and refers to a compound of In, Ga, Zn, and O. A typical example is InGaO3(ZnO) m1 (m1 is a natural number), or In ( 1+x0) Ga (1-x0) O3(ZnO) m0 (-1≦x0≦1, m0 is an arbitrary number) Examples of such crystalline compounds include:

[0076] The crystalline compound has a single crystal structure, a polycrystalline structure, or a CAAC structure. The CAAC structure is a structure in which multiple IGZO nanocrystals have a c-axis orientation and are aligned in the ab plane. is a non-oriented connected crystal structure.

[0077] On the other hand, CAC-OS refers to the material structure of an oxide semiconductor. In a material composition containing Ga, Zn, and O, some nanoparticles with Ga as the main component were observed. The region where the In nanoparticles are observed is shown in part. This refers to a structure in which the pixels are randomly distributed in a mosaic pattern. The crystal structure is a secondary factor.

[0078] It should be noted that the CAC-OS does not include a laminated structure of two or more films with different compositions. For example, a structure consisting of two layers, one containing In as the main component and the other containing Ga as the main component, is not included. do not have.

[0079] In addition, GaO X3 The region where In is the main component and X2 Zn Y2 O Z2 , or InO X1 but In some cases, a clear boundary between the main component region and the main component region cannot be observed.

[0080] Instead of gallium, aluminum, yttrium, copper, vanadium, and beryllium can be used. , boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum , lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium If one or more selected elements such as sodium are included, CAC-OS will The nanoparticle-like regions are observed in the region where the metal element is the main component, and the region where In is the main component. The nanoparticle-like regions are randomly dispersed in a mosaic pattern. say.

[0081] CAC-OS is formed by sputtering without intentionally heating the substrate. In addition, when the CAC-OS is formed by a sputtering method, the deposition gas is The gas is selected from an inert gas (typically argon), oxygen gas, and nitrogen gas. One or more of these may be used. The lower the flow rate ratio of the gas, the more preferable. For example, the flow rate ratio of oxygen gas is preferably 0% or more and less than 30%. It is more preferable to set the content to 0% or more and 10% or less.

[0082] CAC-OS is a type of X-ray diffraction (XRD) measurement method. When measured using the θ / 2θ scan by the out-of-plane method, In other words, from the X-ray diffraction measurement, It can be seen that the orientation of the regions in the ab plane direction and the c axis direction is not observed.

[0083] In addition, CAC-OS uses an electron beam with a probe diameter of 1 nm (also called a nanobeam electron beam). In the electron diffraction pattern obtained by irradiating the sample, a ring-shaped area of ​​high brightness (phosphor) is formed. The electron diffraction pattern is Therefore, the crystal structure of CAC-OS does not have orientation in the planar direction and the cross-sectional direction. It can be seen that it has a nano-crystal structure.

[0084] For example, in the CAC-OS of In-Ga-Zn oxide, energy dispersive X Energy Dispersive X-ray spectroscopy (EDX) EDX mapping obtained using scopy revealed that GaO X3 The region where is the principal component And, In X2 Zn Y2 O Z2 , or InO X1 The area where the main component is unevenly distributed and mixed It can be confirmed that the compound has a structure similar to that of the compound shown in FIG.

[0085] CAC-OS has a structure different from that of IGZO compounds, in which metal elements are uniformly distributed. CAC-OS has different properties from ZO compounds. X3 The main ingredients are In a certain area, X2 Zn Y2 O Z2 , or InO X1 The region where is the principal component and The phases are separated into two, and the regions containing each element as the main component are arranged in a mosaic pattern.

[0086] Here, In X2 Zn Y2 O Z2 , or InO X1 The region where is the main component is GaO X3 This region has higher conductivity than the region where In is the main component. X2 Zn Y 2O Z2 , or InO X1 The carriers flow through the region where the main component is oxidized. Therefore, the conductivity of In is expressed as a semiconductor. X2 Zn Y2 O Z2 , or In O X1 The region where the main component is distributed in a cloud-like shape in the oxide semiconductor allows for a high electric field. Effective mobility (μ) can be achieved.

[0087] On the other hand, GaO X3 The region where the main components are In X2 Zn Y2 O Z2 , or InO X This region has higher insulating properties than the region where GaO is the main component. X3 etc. The distribution of the main component in the oxide semiconductor suppresses leakage current and provides good switching. Switching operation can be realized.

[0088] Therefore, when CAC-OS is used in a semiconductor device, GaO X3 Insulation caused by And, In X2 Zn Y2 O Z2 , or InO X1 The conductivity caused by the This results in a high on-state current (Ion ) and high field-effect mobility (μ) This can be done.

[0089] Furthermore, semiconductor devices using CAC-OS have high reliability. , and is suitable as a constituent material for various semiconductor devices.

[0090] In FIG. 2, the circuit 11 is arranged in the pixel 20[1]. Alternatively, the elements of circuit 11 may be distributed across multiple regions, as shown in FIG. It may also be arranged as follows.

[0091] For example, the pixel 20[1] is provided with a transistor 101, the pixel 20[2] is provided with a transistor 102, The divided capacitive element 104 can be arranged in the pixel 20[n-1] and the pixel 20[n]. In this way, by distributing the elements of the circuit 11, the transistors provided in each pixel can be This reduces the number of elements such as capacitors and capacitor elements, as well as the area they occupy, and increases the aperture ratio. This can be done.

[0092] Although not shown in FIG. 4, there may be pixels in which the elements of the circuit 11 are not arranged. Alternatively, a plurality of such elements may be arranged in one pixel. Alternatively, the number of divisions of the capacitance element may be increased to divide it into three or more pixels. It may be arranged.

[0093] Next, using the timing chart shown in FIG. 5, the pixel block 12 shown in FIG. In the following explanation, high potential is referred to as "H" and low potential is referred to as "L". The weight to be supplied to pixel 20[1] is represented as "W[1]" and the image data is represented as "D[1] ", the weight supplied to pixel 20[2] is "W[2]", the image data is "D[2]", pixel 2 The weight supplied to 0[n-1] is "W[n-1]", the image data is "D[n-1]", The weight supplied to 20[n] is "W[n]" and the image data is "D[n]". re f For example, 0V, GND potential, or a specific reference potential can be used as "."

[0094] In addition, in the distribution, coupling or loss of potential, the circuit configuration and operation timing, etc. The detailed changes due to the capacitive coupling using the capacitive element are not taken into consideration. Although it depends on the capacitance ratio between the capacitance element and the load connected to the capacitance element, for the sake of clarity, Therefore, the capacitance value of the circuit block 110 is assumed to be sufficiently small.

[0095] First, the write operation of "W[1]" in pixel 20[1] will be described.

[0096] At time T1, “W[1]” is connected to the wiring 125 and “V ref " and wiring When the potential of 121, 122, and 123[1] is set to “H”, the transistor 102 becomes conductive. The potential of the other electrode of the capacitor 104 is “V ref " This operation is performed after the addition operation ( This is a reset operation to perform capacitive coupling operation.

[0097] Also, the transistors 101 and 103 are turned on, and the potential of the wiring 125 is written to the node NP[1]. This operation is a weight write operation, and the potential of node NP[1] is "W[1 ]”

[0098] At time T2, the potentials of the wires 121 and 122 are set to "L" and the potential of the wire 123[1] is set to "H". Then, the transistors 101 and 102 are turned off. At this time, "W[1]" is held in the capacitor 104. ref " is held This completes the write operation of "W[1]" in pixel 20[1].

[0099] Next, the addition operation of "D[1]" in pixel 20[1] will be described.

[0100] At time T3, "D[1]" is supplied to the wiring 126, the potential of the wiring 121 is set to "L", and the potential of the wiring When the potential of 122 and 123[1] is set to “H”, the transistors 102 and 103 become conductive. At this time, the potential of the other electrode of the capacitor 104 becomes "D[1]", and "D[1]" is added to the potential of node NP[1]. This operation is an addition operation. The potential of the node NP[1] is “W[1]-V ref +D[1]”. At this time, “V ref If "=0, the potential of the node NP[1] becomes "W[1]+D[1]". The potential of P[1] is supplied to the display element, and display is performed.

[0101] At time T4, when the potential of the wiring 121, 122, and 123 [1] is set to "L", the transistor The potential of the node NP[1] is maintained until the operation of the next frame. The display continues. This concludes the description of the operation of pixel 20[1].

[0102] Next, the write operation of "W[2]" in pixel 20[2] will be described.

[0103] At time T5, the wiring 125 is connected to “W[2]” and the wiring 126 is connected to “V ref " and wiring When the potential of 121, 122, and 123[2] is set to “H”, the transistor 102 becomes conductive. The potential of the other electrode of the capacitor 104 is “V ref "

[0104] Also, the transistors 101 and 103 are turned on, and the potential of the wiring 125 is written to the node NP[2]. This operation is a weight write operation, and the potential of node NP[2] is "W[2 ]”

[0105] At time T6, the potentials of the wires 121 and 122 are set to "L" and the potential of the wire 123[2] is set to "H". Then, the transistors 101 and 102 are turned off. At this time, "W[2]" is stored in the capacitor 104. ref " is held This completes the write operation of "W[2]" in pixel 20[2].

[0106] Next, the addition operation of "D[2]" in pixel 20[2] will be described.

[0107] At time T7, "D[2]" is supplied to the wiring 126, the potential of the wiring 121 is set to "L", and the potential of the wiring When the potential of 122 and 123[1] is set to “H”, the transistors 102 and 103 become conductive. At this time, the potential of the other electrode of the capacitor 104 becomes "D[2]", and "D[2]" is added to the potential of node NP[1]. This operation is an addition operation. The potential of the node NP[1] is “W[2]-V ref +D[2]”. At this time, “V ref If "=0, the potential of node NP[2] becomes "W[2]+D[2]". The potential of P[2] is supplied to the display element, and display is performed.

[0108] At time T8, when the potential of the wiring 121, 122, and 123 [2] is set to "L", the transistor The potential of the node NP[2] is maintained until the operation of the next frame. The display continues. This concludes the description of the operation of pixel 20[2].

[0109] The potential of node NP[2] is supplied to the display element, and display is performed. The same operation is applied to pixel 20[n-1] at times T9 to T12. As a result, the pixel 20[n-1] displays a signal according to "W[n-1]+D[n-1]". The same operation is applied to pixel 20[n] at times T13 to T16. As a result, the pixel 20[n] can display according to "W[n]+D[n]". Cut.

[0110] The pixel block 12 can be operated in this manner.

[0111] The circuit 11 may have a configuration shown in FIG. 6A. The circuit 11 shown in FIG. 2 or 4 in that it has the transistor 105 and that it has one source line. This differs from the circuit 11 shown.

[0112] The gate of the transistor 105 is electrically connected to the wiring 122. One of the source and the drain of the capacitor 104 is electrically connected to the other electrode of the capacitor 104 . The other of the source and drain of the transistor 105 is connected to "V ref "By supplying The other of the source and the drain of the transistor 101 is electrically connected to a wiring. The other of the source and the drain of the transistor 102 is electrically connected to a wiring 125. can be.

[0113] In the configuration of the circuit 11 shown in FIG. 2 or FIG. 4, data (D) and “V ref ” However, in the configuration of the circuit 11 shown in FIG. 6(A), ref " In order to supply data from a dedicated route, weight (W) and data (D) are switched from wiring 125. Therefore, one source line can be reduced.

[0114] The operation when the circuit 11 shown in FIG. 6(A) is used in the pixel block 12 shown in FIG. 2 or FIG. 4. The operation will be explained using the timing chart shown in FIG.

[0115] At time T1, “W[1]” is supplied to the wiring 125, and the potential of the wirings 121 and 123[1] When the potential of the other electrode of the capacitor 104 is set to "H", the transistor 105 is turned on. “V ref This operation is a reset for the subsequent addition operation (capacitive coupling operation). It is an action.

[0116] Also, the transistors 101 and 103 are turned on, and the potential of the wiring 125 is written to the node NP[1]. This operation is a weight write operation, and the potential of node NP[1] is "W[1 ]”

[0117] At time T2, if the potential of the wiring 121 is "L" and the potential of the wiring 123[1] is "H", At this time, the node NP[1] receives "W[1 ]" is held in the capacitor 104. ref " is retained. This completes the write operation of "W[1]" in pixel 20[1].

[0118] At time T3, "D[1]" is supplied to the wiring 125, the potential of the wiring 121 is set to "L", and the potential of the wiring When the potential of 122 and 123[1] is set to “H”, the transistors 102 and 103 become conductive. At this time, the potential of the other electrode of the capacitor 104 becomes "D[1]", and "D[1]" is added to the potential of node NP[1]. This operation is an addition operation. The potential of the node NP[1] is “W[1]-V ref +D[1]”. At this time, “V ref If "=0, the potential of the node NP[1] becomes "W[1]+D[1]". The potential of P[1] is supplied to the display element, and display is performed.

[0119] At time T4, when the potential of the wiring 121, 122, and 123 [1] is set to "L", the transistor The potential of the node NP[1] is maintained until the operation of the next frame. The display continues. This concludes the description of the operation of pixel 20[1].

[0120] Similar operations are applied to pixel 20[2] at times T5 to T8, thereby In this case, you can display the data according to "W[2]+D[2]". By applying it to pixel 20[n-1] at times T9 to T12, , "W[n-1]+D[n-1]" can be displayed. is applied to pixel 20[n] at times T13 to T16, so that in pixel 20[n], It is possible to display according to "W[n]+D[n]".

[0121] The circuit 11 may have a configuration shown in FIG. 6B. The circuit 11 shown in FIG. 2 or 4 in that it includes the transistor 106 and the capacitor 107. is different from.

[0122] One electrode of the capacitor 107 is electrically connected to the node NM. One electrode is electrically connected to one of the source and drain of the transistor 106 . The gate of the transistor 106 is electrically connected to a wiring 127 that functions as a gate line. The other of the source and drain of the transistor 106 functions as a source line. The wiring 128 is electrically connected to the wiring 128.

[0123] The circuit 11 shown in FIG. 6B has two capacitors connected in parallel to the node NM. For example, the threshold voltage of the driving transistor of the light-emitting element can be corrected. The image is generated by writing data to one of the capacitance elements and brightness correction data to the other capacitance element. It can be used for correction, etc. Or, in the operation using the liquid crystal element, it can be used for inversion operation. By using different capacitance elements depending on the polarity of the corresponding signal, the charge accumulated on both electrodes of the capacitance element can be The polarity can be kept constant at all times. Therefore, the amount of charge supplied during the inversion operation can be reduced. This makes it possible to reduce the power consumption of the display device.

[0124] 8A to 8C are applicable to the circuit block 110 and include a light-emitting element as a display element. This is an example of a configuration that includes:

[0125] The structure shown in FIG. 8A includes a transistor 111, a capacitor 113, and a light-emitting element 114. One of the source and drain of the transistor 111 is connected to one of the light-emitting elements 114. One electrode of the light-emitting element 114 is electrically connected to one electrode of the capacitor 113. The other electrode of the capacitor 113 is electrically connected to the gate of the transistor 111. The gate of the transistor 111 is electrically connected to a node NP. do.

[0126] The other of the source and the drain of the transistor 111 is electrically connected to a wiring 128. The other electrode of the light emitting element 114 is electrically connected to the wiring 129. For example, the wiring 128 can supply high potential power. In addition, the wiring 129 can supply a low potential power supply.

[0127] In the configuration shown in FIG. 8A, the potential of the node NM is higher than the threshold voltage of the transistor 111. When this occurs, a current flows through the light emitting element 114. Therefore, the weight (W) of the node NP is The light emitting element 114 may start emitting light at the stage when the data is written, which may limit the use of the device. be.

[0128] Alternatively, as shown in FIG. 8B, one electrode of the light emitting element 114 is electrically connected to the wiring 128. The other electrode of the light emitting element 114 is connected to the other of the source or drain of the transistor 111. This configuration may be electrically connected to another circuit block 1 having a light emitting element 114. It can also be applied to 10.

[0129] FIG. 8C shows a configuration in which a transistor 112 is added to the configuration of FIG. 8A. One of the source or drain of transistor 112 is connected to the source or drain of transistor 111. The other of the source and drain of the transistor 112 is electrically connected to The gate of the transistor 112 is electrically connected to the wiring 127. The wiring 127 is a signal line that controls the conduction of the transistor 112. It can have a function.

[0130] In this configuration, the potential of the node NP is equal to or higher than the threshold voltage of the transistor 111. When the transistor 112 is conductive, a current flows through the light emitting element 114. Therefore, the weight ( The light emitting element 114 starts emitting light at an arbitrary timing after the addition of the data (W) and the data (D). This can be done.

[0131] FIG. 8D shows a configuration in which a transistor 115 is added to the configuration of FIG. 8C. One of the source or drain of transistor 115 is connected to the source or drain of transistor 111. The other of the source and drain of the transistor 115 is electrically connected to The gate of the transistor 115 is electrically connected to a wiring 132. The wiring 132 functions as a signal line that controls the conduction of the transistor 115. can have:

[0132] The wiring 131 can be electrically connected to a source of a specific potential such as a reference potential. A specific potential is applied to either the source or drain of transistor 111 from line 131. This also makes it possible to stabilize the writing of image data.

[0133] The wiring 131 can be connected to the circuit 120 and has a function as a monitor line. The circuit 120 can also be configured to control the specific potential source and the electrical characteristics of the transistor 111. The correction data generating unit may have one or more of the functions of acquiring the correction data and generating the correction data.

[0134] 9A to 9D are applicable to the circuit block 110 and include a liquid crystal element as a display element. This is an example of a configuration that includes:

[0135] The structure shown in FIG. 9A includes a capacitor 116 and a liquid crystal element 117. One electrode of the capacitor 7 is electrically connected to one electrode of the capacitor 116. One electrode of the transistor is electrically connected to a node NP.

[0136] The other electrode of the capacitor 116 is electrically connected to the wiring 133. One electrode is electrically connected to a wiring 134. The wirings 133 and 134 are used to supply power. For example, the wirings 133 and 134 may be connected to a reference potential such as GND or 0V or to an arbitrary potential. can be supplied.

[0137] Note that the capacitor 116 may be omitted as shown in FIG. In addition, an OS transistor can be used as the transistor connected to the node NP. Since the transistor has an extremely small leakage current, the capacitor 116 that functions as a storage capacitor Even if the transistor is omitted, the display can be maintained for a relatively long time. Even in cases where the display period can be shortened by high-speed operation, such as field sequential driving, It is effective to omit the capacitor element 116. By omitting the capacitor element 116, the aperture ratio can be improved. Alternatively, the transmittance of the pixel can be improved.

[0138] In the configurations of FIGS. 9A and 9B, when the potential of the node NP is higher than the operating threshold of the liquid crystal element 117, When the weight is determined, the liquid crystal element 117 starts to operate. The display operation may start when the data is written, and the usage may be limited. In the case of a transmissive liquid crystal display device, the timing at which the addition of weight (W) and data (D) is completed is By combining this with other operations such as turning off the backlight until the Even if the object is not visible, it is possible to suppress its visibility.

[0139] FIG. 9C shows a configuration in which a transistor 118 is added to the configuration of FIG. 9A. One of the source and drain of the capacitor 118 is electrically connected to one electrode of the capacitor element 116. The other of the source and drain of the transistor 118 is electrically connected to the node NP. The gate of the transistor 118 is electrically connected to the wiring 130. 30 can function as a signal line that controls the conduction of the transistor 118. .

[0140] In this configuration, when the transistor 118 is turned on, the potential of the node NP is applied to the liquid crystal element 117. Therefore, at any timing after the addition of weight (W) and data (D), The liquid crystal element can then start operating.

[0141] When the transistor 118 is off, the voltage supplied to the capacitor element 116 and the liquid crystal element 117 is Since the supplied potential is maintained, the capacitor element 116 and the It is preferable to reset the potential supplied to the liquid crystal element 117. For example, a reset potential is applied to the source line (for example, the wiring 125, 126, etc.) to which the pixel is connected. By supplying a voltage to the transistor 101 and the transistor 118, the transistor 101 and the transistor 118 are simultaneously turned on.

[0142] FIG. 9D shows a configuration in which a transistor 119 is added to the configuration of FIG. 9C. One of the source and drain of the transistor 119 is electrically connected to one electrode of the liquid crystal element 117. The other of the source and the drain of the transistor 119 is electrically connected to a wiring 131. The gate of the transistor 119 is electrically connected to the wiring 132. The reference numeral 32 can function as a signal line for controlling the conduction of the transistor 119 .

[0143] The circuit 120 electrically connected to the wiring 131 is the same as that described above with reference to FIG. In addition, the potential supplied to the capacitor element 116 and the liquid crystal element 117 is reset. It may be possible.

[0144] 10(A) to 10(C) are diagrams showing the "V ref Wiring equipment for supplying 10A is a diagram showing an example in which a light-emitting element is used as a display element. is "V ref The wiring 128 can be applied to the wiring for supplying "V re f " is preferably 0V, GND or a low potential, so the wiring 128 is The wiring 128 has a function of supplying one of these potentials to the node NP. At the timing of writing "V ref " is supplied to the light emitting element 114, and the timing at which the light emitting element 114 emits light is Alternatively, as shown in FIG. 10(B), a low potential may be supplied. Connect the wire 129 to the “V ref " may be applied as wiring for supplying ".

[0145] Also, as shown in FIG. 10(C), when a liquid crystal element is used as a display element, ref The wiring 133 can be applied to the wiring for supplying ". Alternatively, the wiring 134 can be applied. Regardless of the type of display element, "V ref Dedicated common distribution A line may be provided.

[0146] In one aspect of the present invention, as shown in FIGS. 11(A) and 11(B), The transistor included in the gate 12 may have a back gate. The back gate is electrically connected to the front gate, and the on-current is increased. FIG. 11B shows a back gate connected to a wiring 135 that can supply a constant potential. This shows a structure where the transistor is electrically connected, and the threshold voltage of the transistor can be controlled. do.

[0147] As shown in the timing chart of FIG. 4, the gate signal On the other hand, for the circuit 11, one circuit 10 It is necessary to input a gate signal "H" or "L" according to the operation period of the This operation is repeated as many times as the number of circuits 10 that the pixel block 12 has.

[0148] Therefore, as shown in FIG. 1, a gate driver 14a that controls the circuit 11 and a gate driver 14b that controls the circuit 10 It is preferable to provide a gate driver 14b for controlling the circuits 10 and 11. By providing individual gate drivers, the PWC (Pulse Width Control) required for operation can be Control) signals to be less than the number of circuits 10 that the pixel block 12 has. can be done.

[0149] For example, Figure 12 shows input and output signals of the gate drivers 14a and 14b. Here, the number of pixel rows is 1280, and the number of pixels (circuits 10) included in the pixel block 12 is 4. Let's say.

[0150] The signal input to the gate driver 14a is SPL (start buffer for the gate driver 14a). pulse signal), CLK[1:4]L (clock signal for gate driver 14a), PWC1, PWC2 (pulse width control signal of the gate signal), and its output is For GL1[1] to GL1

[0320] and GL2[1] to GL2

[0320] Here, GL1 corresponds to the wiring 125, and GL2 corresponds to the wiring 126. Also, 320 matches the number of pixel blocks 12 arranged in the vertical direction.

[0151] The signal input to the gate driver 14b is SPR (start pulse for the gate driver 14b). CLK[1:4]R (clock signal for the gate driver 14b) The output can be sent to the gate lines GL3[1] to GL3

[1280] . Here, GL3 corresponds to the wiring 123. Also, 1280 is set in the vertical direction. This corresponds to the number of pixels 20 that can be displayed.

[0152] FIG. 13 is an example of a block diagram of the gate driver 14a. The gate driver 14a A shift register circuit consisting of multiple set-reset flip-flops and a buffer One stage of the shift register circuit is represented by "SR" and a dummy stage is represented by "BuF". is represented by "DUM". RES is a reset signal, and when "H" is input, the shift register All outputs of the circuit can be set to "L".

[0153] "BuF" has an AND circuit, and the output signal of "SR" (SROUT signal), PWC1 signal and PWC2 signals to output signals to the gate lines (GL1 and / or GL2). It is possible.

[0154] "SR" is, for example, a block diagram shown in FIG. 15(A) and a circuit diagram shown in FIG. 15(B). Here, LIN is the shift signal input from the previous stage "SR". FO is the output signal that controls the transistor in "Buf", and RIN is the output signal of the "SR" in the subsequent stage. The input clock signal is, for example, CL A combination of K[1]L and CLK[3]L, or a combination of CLK[2]L and CLK[4]L It can be a combination.

[0155] The buffer circuit (BuF) is shown in the block diagram of FIG. 16(A) and the block diagram of FIG. 16(B). Here, FN is the signal input from "SR". (FO) and LN represent the signal (SROUT) input from "SR".

[0156] FIG. 14 is an example of a block diagram of the gate driver 14b. It has a shift register circuit consisting of flip-flops. One stage of the shift register circuit is represented by "SR", and the dummy stage is represented by "DUM". "SR" is, for example, The configuration can be as shown in the block diagram of FIG. 17A and the circuit diagram of FIG. 17B.

[0157] Next, the simulation results for pixel block 12 will be explained. The configuration of the pixel block 12 used in the simulation is shown in Figure 19. The pixel block 12 has four pixels, and the circuit block 110 The configuration (liquid crystal element and capacitor element) shown in Figure 9(A) was used. The voltage change at node NP was measured when the elements were operated sequentially.

[0158] The parameters used in the simulation are as follows, and the transistor size is L / W. =4 μm / 4 μm (transistors included in the pixel block 12), and the capacitance value of the capacitive element C1 is 500fF, the capacitance of the capacitance element Cs is 100fF, and the capacitance of the liquid crystal element Clc is 100fF The common electrodes VCOM and TCOM were set to 0 V. The voltage applied to the gate of the transistor was The voltages used were +15V for "H" and -10V for "L". SPICE was used as the simulation software. Parasitic capacitance is excluded from the parameters.

[0159] Figure 19 is a timing chart used in the simulation. Here, the weight (W[ The voltages of the data (D[1] to [4]) and the data (D[1] to [4]) were all set to 5V. re f " was set to 0V.

[0160] FIG. 20(A) shows the weights (W[1] to [4]) and data (D[1] to [4]) and set it to 5V, ref The horizontal axis shows the time. The vertical axis is the voltage of node NP. At each node NP, the weight (W) and data (D) are It was confirmed that the values ​​are added according to the capacity ratio.

[0161] Figure 20(B) shows the weight (W[1]) and data (D[2]) at 5V, weight (W[2]) and data (D[2]) to 2.5V, weight (W[3]) and data (D[3]) to - 2.5V, weight (W[4]) and data (D[4]) are set to -5V, and “V ref "of The simulation results are shown for the case where the voltage is 0V. It was confirmed that the data (D) is added according to the capacitance ratio. Since addition can be performed regardless of the weight and polarity of data within 12, gate line inversion It was confirmed that the application of the drive was also possible.

[0162] Therefore, the pixel block 12 according to one aspect of the present invention is not affected by the parasitic capacitance of the wiring PL. It was confirmed that the addition of weight (W) and data (D) can be performed normally within a small range.

[0163] Next, the simulation results for the pixel layout will be explained. The pixel block 12 is a basic configuration, and an example of a layout of three vertical pixels is shown in the m-th column and the m-th column. This is a diagram showing the +1 column.

[0164] In the layout shown in FIG. 21, Cs is omitted and only the pixel electrode PE corresponding to the node NP is connected. As an example of a transistor, a bottom gate type (back gate or The figure shows the

[0165] The transistors Tr1 and Tr2 are arranged so as to be included in the pixels in the first row of the pixel block 12. Therefore, the transistors in each row are as follows: the first row has transistors Tr1, T There are three in total, r2 and Tr3, and from the second row onwards there is only one transistor, Tr3. The size of transistors Tr1 and Tr2 is L / W=4μm / 30μm, and transistor Tr The size of 3 is assumed to be L / W = 4 μm / 10 μm. The pixel pitch is approximately 136 μm. (Different between the first line and the second line and onwards).

[0166] C1 is a conductive layer fabricated in the same process as the gate wiring and a source wiring. The two conductive layers are used as a pair of electrodes. and an area where they overlap with each other via an insulating layer (for example, a gate insulating film) in each pixel. That is, each pixel is provided with one capacitance element. are connected in parallel, and are therefore equivalent to one large capacitance element.

[0167] That is, since the capacitance element C1 is divided and arranged, the aperture ratio and transmittance of the pixel are improved. The conductive layers constituting the capacitor element can be electrically connected to each other by the following method. It is preferable to use a connection wiring BR that bridges the gate wiring. For example, the source wiring can be fabricated in the same process.

[0168] Here, the pixels in the first row have transistors Tr1 and Tr2 and their driving gate lines. Therefore, the number of elements is larger than that of pixels in other rows. In this way, when the vertical length of all pixels is unified to A, the pixel electrode PE1 is Therefore, the display in the first column is perceived as a dark line. This may happen.

[0169] Therefore, as shown in FIG. 22(B), the vertical length of all pixel electrodes is B, and the vertical length of the pixels in the first row is set to be shorter than the vertical length of the pixels in the second row and onwards. Alternatively, the pixel electrode PE1 may be larger than the pixel electrodes PE2 and PE3. The vertical length of each pixel may be adjusted as shown in the figure. It is possible to prevent the display from being visually recognized as a dark line.

[0170] Aperture when the pixel blocks of type 1 or type 2 shown in FIG. 22 are applied to the display area The calculated aperture ratio is shown in FIG. 23. The aperture ratio shown here is the ratio of the number of pixels in a pixel block to the number of pixels in a pixel block. In the calculation, the number of pixels in a pixel block is The value ranged from 1 to 4000. Note that all type 1 pixels were square pixels with a side length of 136 μm. In addition, in the case of Type 2, when the number of pixels is 1, one side is 136 μm. The pixel is a square, and when the number of pixels is 2 or more, the vertical length is adjusted so that the pixel electrodes are the same size. In order to be able to compare with Type 1, the vertical length of the pixel block is This is the same as when using 136 μm square pixels.

[0171] As shown in Figure 23, both Type 1 and Type 2 can accommodate up to about 10 pixels in a pixel block. The aperture ratio increases rapidly, reaching 81% at around 20. It then increases gradually, reaching 100. Therefore, if aperture ratio is important, the number of pixels in a pixel block should be It is preferable to have as many as possible. However, the efficiency of the pixel layout is important. Considering the effect, it is preferably about 5 to 100, more preferably about 10 to 50, and more preferably about 20 A value of 100 to 400 is more preferable.

[0172] The above simulation results confirmed the effect of one aspect of the present invention.

[0173] This embodiment mode can be implemented by appropriately combining with the configurations described in other embodiment modes. It is possible.

[0174] (Embodiment 2) In this embodiment, a configuration example of a display device using a liquid crystal element and a configuration example of a display device using a light-emitting element will be described. In this embodiment, the display described in the first embodiment is Description of the elements, operations and functions of the device will be omitted.

[0175] 24A to 24C show the structure of a display device to which one embodiment of the present invention can be applied. Figure.

[0176] In FIG. 24A, a display portion 215 provided on a first substrate 4001 is surrounded by a A sealant 4005 is provided, and the display portion 215 is attached to the sealant 4005 and the second substrate 4. Sealed by 006.

[0177] The display unit 215 can be provided with the pixel block 12 described in the first embodiment and the like. The scanning line driving circuit described below is a gate driver, and the signal line driving circuit is a source driver. Equivalent to Ba.

[0178] In FIG. 24A, a scanning line driving circuit 221a, a signal line driving circuit 231a, and a signal line driving circuit 232a and the common line driver circuit 241a are provided on a printed circuit board 4041. The integrated circuits 4042 are made of a single crystal semiconductor or a polycrystalline The common line driving circuit 241a is made of a semiconductor. , 129, 132, 133, 135, etc., and has the function of supplying a specified potential.

[0179] The scanning line driving circuit 221a, the common line driving circuit 241a, the signal line driving circuit 231a, and the signal Various signals and potentials given to the signal line driving circuit 232a are transmitted through an FPC (Flexible Printed Circuit). ble printed circuit)4018.

[0180] The integrated circuit 4042 included in the scanning line driver circuit 221a and the common line driver circuit 241a is The signal line driver circuit 231a and the signal line driver The integrated circuit 4042 included in the drive circuit 232a has a function of supplying image data to the display unit 215. The integrated circuit 4042 is surrounded by a sealant 4005 on the first substrate 4001. It is implemented in a different area from the area where it is installed.

[0181] The method of connecting the integrated circuit 4042 is not particularly limited, and may be wire bonding. COG (Chip On Glass) method, TCP (Tape Carrier Package method, COF (Chip On Film) method, etc. can be used. .

[0182] FIG. 24(B) shows an integrated circuit included in the signal line driver circuit 231a and the signal line driver circuit 232a. The circuit 4042 is implemented by the COG method. The display unit 215 and the display unit 216 can be integrally formed on the same substrate to form a system-on-panel. Cut.

[0183] In FIG. 24B, the scanning line driving circuit 221a and the common line driving circuit 241a are connected to the display unit 2. 15. The driving circuit is formed on the same substrate as the pixel circuit in the display unit 215. By forming the parts at the same time, the number of parts can be reduced, which increases productivity. can.

[0184] In FIG. 24B, the display portion 215 provided on the first substrate 4001 and the scanning line driver A sealant 4005 is provided to surround the common line driving circuit 221a and the common line driving circuit 241a. In addition, a display unit 215, a scanning line driving circuit 221a, and a common line driving circuit The second substrate 4006 is provided on the display unit 215, the scanning line driver 241a. The driving circuit 221a and the common line driving circuit 241a are mounted on the first substrate 4001 and the sealing material 40. The display element is sealed by the second substrate 4005 and the second substrate 4006 .

[0185] In addition, in FIG. 24B, the signal line driver circuit 231a and the signal line driver circuit 232a are separately 4001 and mounted on the first substrate 4001, but the present invention is not limited to this configuration. The scanning line driver circuit may be formed separately and mounted, or may be mounted as part of the signal line driver circuit or the scanning line driver circuit. A part of the driving circuit may be formed separately and mounted. The signal line driving circuit 231a and the signal line driving circuit 232a are formed on the same substrate as the display unit 215. That's fine.

[0186] The display device also includes a panel in which a display element is sealed, and a controller for the panel. This may also include a module in which an IC or the like including the above is mounted.

[0187] The display portion and the scanning line driver circuit provided on the first substrate have a plurality of transistors. The transistor described in the above embodiment can be used as the transistor. can be done.

[0188] The structure of the transistors in the peripheral driver circuits and the pixel circuits in the display area is The transistors in the peripheral driver circuit may be the same or different. The transistors may have the same structure, or may have two or more types of transistor structures. Similarly, the transistors in the pixel circuit may all have the same structure. Alternatively, the semiconductor device may have two or more transistor structures.

[0189] In addition, an input device 4200 can be provided over the second substrate 4006. The display device shown in any one of (a) to (c) provided with an input device 4200 functions as a touch panel. It can be done.

[0190] There is no limitation on the detection elements (also referred to as sensor elements) included in the touch panel of one embodiment of the present invention. We offer a variety of sensors that can detect the proximity or contact of a finger, stylus, or other object. , can be applied as a sensing element.

[0191] The sensor type may be, for example, a capacitance type, a resistive film type, a surface acoustic wave type, or an infrared type. Various methods can be used, such as a pressure-sensitive method, an optical method, or the like.

[0192] In this embodiment, a touch panel having a capacitance type detection element will be described as an example. .

[0193] The capacitance type includes a surface capacitance type, a projected capacitance type, etc. The capacitance type includes the self-capacitance type and the mutual capacitance type. This is preferable because it enables simultaneous multi-point detection.

[0194] The touch panel of one embodiment of the present invention is formed by bonding a display device and a sensing element that are separately manufactured. A detector element is formed on one or both of a substrate supporting a display element and an opposing substrate. Various configurations can be applied, such as a configuration in which electrodes or the like are provided.

[0195] 25(A) and (B) show examples of touch panels. FIG. 25(A) shows a touch panel 4 25(B) is a perspective view of the input device 4200. For clarity, only representative components are shown.

[0196] The touch panel 4210 is made by bonding a display device and a sensing element that are separately manufactured. be.

[0197] The touch panel 4210 has an input device 4200 and a display device, which are stacked on top of each other. It is being done.

[0198] The input device 4200 includes a substrate 4263, an electrode 4227, an electrode 4228, and a plurality of wirings 4237. , a plurality of wirings 4238 and a plurality of wirings 4239. For example, the electrode 4227 is The electrode 4228 can be electrically connected to the wiring 4237 or the wiring 4239. The FPC 4272b can be electrically connected to the wires 4239. and electrically connects to each of the plurality of wirings 4238. 3b can be provided.

[0199] Alternatively, a touch sensor may be provided between the first substrate 4001 and the second substrate 4006 of the display device. In the case where a touch sensor is provided between the first substrate 4001 and the second substrate 4006, In this case, in addition to capacitive touch sensors, optical touch sensors using photoelectric conversion elements are also available. may be applied.

[0200] 26(A) and (B) are cross-sectional views of the portion indicated by the chain line N1-N2 in FIG. 24(B). The display device shown in FIGS. 26(A) and 26(B) has an electrode 4015. The terminals of the FPC 4018 are electrically connected via the anisotropic conductive layer 4019. 26(A) and (B), the electrode 4015 is formed by insulating layers 4112 and 4111. and electrically connected to the wiring 4014 in an opening formed in the insulating layer 4110. do.

[0201] The electrode 4015 is formed from the same conductive layer as the first electrode layer 4030. The source and drain electrodes of the transistor 4010 and the transistor 4011 are the same. The same conductive layer is used.

[0202] The display portion 215 and the scanning line driver circuit 221a provided on the first substrate 4001 are 26(A) and 26(B), the transistors included in the display unit 215 are 4010 and a transistor 4011 included in the scanning line driver circuit 221a. 26(A) and 26(B), the transistor 4010 and the transistor Although a bottom-gate transistor is shown as an example of the transistor 4011, a top-gate transistor may also be used. It may also be a transistor.

[0203] In FIGS. 26A and 26B, an insulating layer is formed on the transistor 4010 and the transistor 4011. 26B, a partition wall 451 is provided over the insulating layer 4112. 0 is formed.

[0204] The transistor 4010 and the transistor 4011 are provided over an insulating layer 4102. The transistor 4010 and the transistor 4011 are formed by insulating layers 4111. The electrode 4017 is formed on the semiconductor substrate 401. The electrode 4017 functions as a back gate electrode. It is possible.

[0205] 26A and 26B includes a capacitor 4020. 020 is an electrode 4021 formed in the same process as the gate electrode of the transistor 4010, and an electrode formed in the same process as the source electrode and the drain electrode. The poles overlap with an insulating layer 4103 between them.

[0206] Generally, the capacitance of a capacitor provided in a pixel portion of a display device is determined by the capacitance of a transistor disposed in the pixel portion. The capacitance is set to be able to hold charge for a predetermined period, taking into consideration factors such as leakage current of the capacitor. The capacitance of the capacitor may be set in consideration of the off-state current of the transistor.

[0207] The transistor 4010 provided in the display portion 215 is electrically connected to a display element. (A) is an example of a liquid crystal display device using a liquid crystal element as a display element. In the liquid crystal display device, a liquid crystal element 4013 is a display element. 31, and a liquid crystal layer 4008. The second electrode layer 4031 is provided to sandwich the liquid crystal layer 4008. The first electrode layer 4030 and the second electrode layer 4031 are disposed on the second substrate 4006 side. Overlapping through layer 4008.

[0208] As the liquid crystal element 4013, liquid crystal elements to which various modes are applied can be used. For example, VA (Vertical Alignment) mode, TN (Twisted Nematic (IPS) mode, In-Plane-Switching (IPS) mode, A SM(Axially Symmetrically aligned Micro-cell) Mode, OCB (Optically Compensated Bend) Mode, F LC (Ferroelectric Liquid Crystal) mode, AFLC (AntiFerroelectric Liquid Crystal) mode, EC B(Electrically Controlled Birefringence) Use of LCD elements that use mode, VA-IPS mode, guest host mode, etc. can be done.

[0209] In addition, the liquid crystal display device shown in this embodiment may be a normally black liquid crystal display device, for example. A transmissive liquid crystal display device employing a vertical alignment (VA) mode may also be used. The code is MVA (Multi-Domain Vertical Alignment) nt) mode, PVA (Patterned Vertical Alignment) mode, ASV (Advanced Super View) mode, etc. can.

[0210] The liquid crystal element is an element that controls the transmission or non-transmission of light by the optical modulation action of the liquid crystal. The optical modulation effect of liquid crystals is due to the electric field (horizontal electric field, vertical electric field or The liquid crystal used in the liquid crystal element is thermoelectric. ropic liquid crystal, low molecular liquid crystal, polymer liquid crystal, polymer dispersed liquid crystal (PDLC) Dispersed Liquid Crystal, Ferroelectric Liquid Crystal, Antiferroelectric Liquid Crystal These liquid crystal materials can exhibit a cholesteric phase, a smectic phase, etc. depending on the conditions. These phases include nematic, cubic, chiral nematic, and isotropic phases.

[0211] FIG. 26 shows an example of a liquid crystal display device having a vertical electric field type liquid crystal element. Similarly, a liquid crystal display device having a liquid crystal element of the lateral electric field type can be applied. When the formula is adopted, a liquid crystal that exhibits a blue phase without using an alignment film may be used. When the temperature of cholesteric liquid crystal is increased, it changes from the cholesteric phase to the isotropic phase. The blue phase appears just before the transition to the In order to improve the optical field range, a liquid crystal composition containing 5% by weight or more of a chiral agent is mixed. 08. A liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a short response time. Furthermore, a liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent is No alignment treatment is required, and viewing angle dependency is small. This eliminates the need for rubbing, preventing electrostatic damage caused by rubbing. This makes it possible to reduce defects or damage to the liquid crystal display device during the manufacturing process.

[0212] The spacers 4035 are columnar spacers obtained by selectively etching an insulating layer. The distance (cell gap) between the first electrode layer 4030 and the second electrode layer 4031 is controlled. A spherical spacer may also be used.

[0213] If necessary, a black matrix (light-shielding layer), a colored layer (color filter), a polarizing Optical members (optical substrates) such as a member, a phase difference member, an anti-reflection member, etc. may be provided as appropriate. For example, circularly polarized light produced by a polarizing substrate and a retardation substrate may be used. A backlight, a sidelight, or the like may be used. Micro LEDs or the like may be used as the light.

[0214] In the display device shown in FIG. 26A, a light-shielding layer is provided between the substrate 4006 and the second electrode layer 4031. 4132, a colored layer 4131, and an insulating layer 4133 are provided.

[0215] Materials that can be used for the light-shielding layer include carbon black, titanium black, gold, Examples of the light-shielding layer include metals, metal oxides, and composite oxides including solid solutions of multiple metal oxides. The film may be a film containing a resin material, or may be a thin film made of an inorganic material such as a metal. For example, a laminated film of a film containing a material of a colored layer may be used as the light-shielding layer. A film containing a material used for a color layer that transmits light of a certain color and a material used for a color layer that transmits light of another color are used. By using the same material for the colored layer and the light-shielding layer, This is preferable because it allows the equipment to be standardized and the process to be simplified.

[0216] Materials that can be used for the coloring layer include metal materials, resin materials, pigments, and dyes. The light-shielding layer and the colored layer may be formed by, for example, an ink-jet method. It can be formed using:

[0217] The display device shown in FIGS. 26A and 26B includes an insulating layer 4111 and an insulating layer 4104. The insulating layer 4111 and the insulating layer 4104 are made of insulating layers that are not easily permeated by impurity elements. By sandwiching the semiconductor layer of the transistor between the insulating layer 4111 and the insulating layer 4104, It is possible to prevent the intrusion of impurities.

[0218] Furthermore, a light-emitting element can be used as a display element included in a display device. For example, an EL element that utilizes electroluminescence can be used. An EL element has a layer containing a light-emitting compound between a pair of electrodes (also called an "EL layer"). When a potential difference greater than the threshold voltage of the EL element is generated between the pair of electrodes, Holes are injected from the anode side and electrons are injected from the cathode side. The injected electrons and holes are The electrons recombine in the layer, causing the light-emitting material contained in the EL layer to emit light.

[0219] EL elements are also classified according to whether the light-emitting material is an organic compound or an inorganic compound. Generally, the former is called an organic EL element, and the latter is called an inorganic EL element.

[0220] When a voltage is applied to an organic EL element, electrons are emitted from one electrode and holes are emitted from the other electrode. are injected into the EL layer, and then the carriers (electrons and holes) recombine. By this, the light-emitting organic compound is excited and returns to the ground state. Due to this mechanism, such a light-emitting element is called a current-excited light-emitting element. It is called a child.

[0221] In addition to the light-emitting compound, the EL layer may contain a material having a high hole injection property and a material having a high hole transport property. , hole blocking material, material with high electron transporting ability, material with high electron injecting ability, or bipolar The layer may contain a highly functional substance (a substance having high electron-transporting and hole-transporting properties).

[0222] The EL layer can be formed by a variety of methods, including vapor deposition (including vacuum deposition), transfer, printing, inkjet, and coating. It can be formed in any way.

[0223] Inorganic EL elements are divided into dispersion-type inorganic EL elements and thin-film-type inorganic EL elements depending on the element structure. Dispersion-type inorganic EL elements have a light-emitting layer in which particles of a light-emitting material are dispersed in a binder. The emission mechanism is a donor-acceptor interaction that utilizes the donor and acceptor levels. Thin-film inorganic EL devices sandwich the light-emitting layer between dielectric layers. Furthermore, this structure is sandwiched between electrodes, and the light emission mechanism utilizes the inner-shell electron transition of metal ions. In this example, the light-emitting element is an organic EL element. do.

[0224] The light emitting element only needs to have at least one of the pair of electrodes transparent in order to extract light. The transistor and the light emitting element are formed on the substrate, and light is emitted from the surface opposite to the substrate. Top emission structure, which emits light from the top surface, and bottom emission structure, which emits light from the surface of the substrate. (bottom emission) structure and double-sided emission (dual emission) structure There are light emitting elements with a light-emitting structure, and any light emitting element with an emission structure can be applied.

[0225] FIG. 26(B) shows a light-emitting display device (also called an "EL display device") that uses light-emitting elements as display elements. The light-emitting element 4513 is an example of a display element. The light-emitting element 4513 is electrically connected to the transistor 4010. The electrode layer 4030, the light-emitting layer 4511, and the second electrode layer 4031 are laminated together. The light emitting element 4513 may be arranged in accordance with the direction of light to be extracted from the light emitting element 4513. The configuration of 13 can be changed as appropriate.

[0226] The partition wall 4510 is formed using an organic insulating material or an inorganic insulating material. An opening is formed on the first electrode layer 4030 using a resin material, and the side of the opening is It is preferable to form the inclined surface with a curvature.

[0227] The light-emitting layer 4511 may be composed of a single layer or a plurality of layers stacked. Either way is fine.

[0228] The light emitting element 4513 emits light in a variety of colors, including white, red, green, and blue, depending on the material that makes up the light emitting layer 4511. , cyan, magenta, or yellow, etc.

[0229] To achieve color display, a white light-emitting element 4513 is combined with a colored layer. There are two methods: one is to combine the two and the other is to provide a light emitting element 4513 with a different luminescent color for each pixel. The first method has higher productivity than the latter method. However, the latter method is less productive than the former method because it requires separate production. In addition to the latter method, it is possible to obtain an emission color with higher color purity than the former method. By adding a microcavity structure to the element 4513, color purity can be further improved. can be done.

[0230] The light-emitting layer 4511 may contain an inorganic compound such as quantum dots. By using the child dots in the light-emitting layer, they can also function as a light-emitting material.

[0231] The second electrode layer is formed to prevent oxygen, hydrogen, moisture, carbon dioxide, and the like from entering the light-emitting element 4513. A protective layer may be formed on the insulating layer 4031 and the partition wall 4510. The protective layer may be formed of silicon nitride. silicon nitride oxide, aluminum oxide, aluminum nitride, aluminum oxynitride, Forming aluminum oxide nitride, DLC (Diamond Like Carbon), etc. In addition, the first substrate 4001, the second substrate 4006, and the sealing material 4 The space sealed by 005 is sealed with a filler 4514. In addition, a protective film (laminating film) with high airtightness and low outgassing is used to prevent exposure to the outside air. It is preferable to package (enclose) the product in a protective film (film, ultraviolet curing resin film, etc.) or a cover material. Desirable.

[0232] Filler 4514 can be an inert gas such as nitrogen or argon, or an ultraviolet curing resin or Thermosetting resins can be used, such as PVC (polyvinyl chloride), acrylic resins, Polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral) or Ethylene vinyl acetate (EVA) can also be used. may contain a desiccant.

[0233] The sealing material 4005 is made of glass materials such as glass frit, or ordinary materials such as two-component mixed resin. Resin materials such as heat-curable resin, photo-curable resin, and thermosetting resin can be used. The sealing material 4005 may also contain a desiccant.

[0234] If necessary, a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate) may be attached to the light-emitting surface of the light-emitting element. Optical films such as retardation plates (λ / 4 plates, λ / 2 plates), color filters, etc. may be provided as needed. In addition, an anti-reflection film may be provided on the polarizing plate or the circular polarizing plate. Anti-glare treatment can be applied to further diffuse reflected light and reduce glare.

[0235] In addition, by using a microcavity structure for the light-emitting element, it is possible to extract light with high color purity. In addition, by combining a microcavity structure with a color filter, This reduces congestion and improves the visibility of the displayed image.

[0236] A first electrode layer and a second electrode layer (a pixel electrode layer, a common electrode layer, In the case of the counter electrode layer, the direction of the light to be extracted, the location of the electrode layer, and The light transmission property or reflectivity can be selected depending on the pattern structure of the electrode layer.

[0237] The first electrode layer 4030 and the second electrode layer 4031 are made of an indium oxide containing tungsten oxide. oxide, indium zinc oxide with tungsten oxide, indium oxide with titanium oxide Indium tin oxide, indium tin oxide containing titanium oxide, indium zinc oxide A conductive material having light-transmitting properties, such as indium tin oxide doped with silicon oxide, may be used. This can be done.

[0238] The first electrode layer 4030 and the second electrode layer 4031 are made of tungsten (W) and molybdenum. (Mo), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (N b), Tantalum (Ta), Chromium (Cr), Cobalt (Co), Nickel (Ni), Titanium Metals such as titanium (Ti), platinum (Pt), aluminum (Al), copper (Cu), and silver (Ag) or its alloy, or metal nitride thereof. .

[0239] The first electrode layer 4030 and the second electrode layer 4031 are made of a conductive polymer (conductive polymer). The conductive polymer can be formed using a conductive composition containing a conductive polymer. For example, a so-called π-electron conjugated conductive polymer can be used. or its derivatives, polypyrrole or its derivatives, polythiophene or its derivatives or a copolymer consisting of two or more of aniline, pyrrole and thiophene, or Its derivatives are also included.

[0240] In addition, since transistors are easily damaged by static electricity, a protection circuit for protecting the drive circuit is required. It is preferable that the protection circuit is configured using a non-linear element.

[0241] As shown in FIG. 27, the transistors and the capacitor elements are arranged so as to have an overlapping region in the height direction. For example, the transistor 4011 and the transistor 4020 which form the driver circuit may be By overlapping the transistor 4021 and the transistor 4022, a display device with a narrow frame can be obtained. The pixel circuit is made up of a transistor 4010, a transistor 4023, a capacitor element 402, and a If the pixels are arranged so that they overlap even partially, the aperture ratio and resolution can be improved. In addition, in FIG. 27, a stack structure is applied to the liquid crystal display device shown in FIG. 26(A). Although an example is shown, it may also be applied to the EL display device shown in FIG. 26(B).

[0242] In addition, in the pixel circuit, a transparent conductive film with high transparency to visible light is used for the electrodes and wiring. By doing so, it is possible to increase the light transmittance within the pixel, and it is possible to substantially improve the aperture ratio. In addition, when an OS transistor is used, the semiconductor layer also has a light-transmitting property. This allows for an increased aperture ratio. This is especially useful when transistors are not stacked. It is also effective in

[0243] Furthermore, a display device may be configured by combining a liquid crystal display device and a light emitting device.

[0244] The light emitting device is disposed on the opposite side of the display surface or at the edge of the display surface. The light-emitting device can also be called a backlight.

[0245] Here, the light emitting device is a plate-shaped or sheet-shaped light guide part (also called a light guide plate) and a light source that emits light of different colors. The light emitting element may be disposed near a side surface of the light guide portion. Then, light can be emitted from the side of the light guide to the inside. The light guide has a mechanism to change the light path ( This allows the light-emitting device to emit light to the pixel area of ​​the display panel. Alternatively, a light-emitting device can be placed directly under the pixel without providing a light guide section. It may also be configured to place

[0246] The light emitting device preferably has light emitting elements of three colors: red (R), green (G), and blue (B). Furthermore, it may have a white (W) light emitting element. It is preferable to use an LED (Light Emitting Diode). .

[0247] Furthermore, the light emitting element has a full width at half maximum (FWHM) of its emission spectrum. at Half Maximum) is 50 nm or less, preferably 40 nm or less, more preferably Preferably, the diameter is 30 nm or less, more preferably 20 nm or less, and the color purity is extremely high. It is preferable that the full width at half maximum of the emission spectrum is as small as possible. However, it can be set to, for example, 1 nm or more. It is possible to produce a vivid display with high color reproducibility.

[0248] In addition, the red light emitting element has a peak wavelength of 625 nm or more and 650 nm or less in the emission spectrum. It is preferable to use an element located within the range below. Use an element whose spectral peak wavelength is in the range of 515 nm to 540 nm. It is preferable that the blue light emitting element has an emission spectrum with a peak wavelength of 445 nm or more. It is preferable to use elements that lie within the 70 nm range or less.

[0249] The display device sequentially blinks the three color light emitting elements and drives the pixels in synchronization with this. The color display can be performed based on the sequential additive color mixing method. This can also be called sequential driving.

[0250] Field sequential driving allows for the display of vivid color images. By using the above driving method, it is possible to display smooth moving images. It is not necessary to configure a pixel with multiple sub-pixels of different colors, and the effective reflective area of ​​one pixel (effective surface area) The display area (also called the aperture ratio) can be increased, allowing for brighter displays. Since there is no need to provide a color filter to the pixel, the transmittance of the pixel can also be improved. Furthermore, the manufacturing process can be simplified and the manufacturing cost can be reduced. can be reduced.

[0251] 28(A) and 28(B) are schematic cross-sectional views of a display device capable of field sequential driving. The display device has a backlight on the substrate 4001 side that can emit light in each of the RGB colors. In field sequential driving, the time division of each RGB color is Since colors are expressed by split light, color filters are not required.

[0252] The backlight unit 4340a shown in FIG. 28(A) has a diffusion plate 4352 directly below the pixels. The light emitting element 4342 is provided in a plurality of layers. 42 to the substrate 4001 side, and the function of diffusing the light emitted from the substrate 4001 side to make the brightness uniform within the display surface. A polarizing plate may be provided between the light emitting element 4342 and the diffusion plate 4352 as needed. In addition, the diffusion plate 4352 may not be provided if it is not necessary. It may be omitted.

[0253] The backlight unit 4340a can be equipped with many light-emitting elements 4342. In addition, a light guide plate is not required, and the light efficiency of the light emitting element 4342 is If necessary, the light emitting element 4342 may be provided with a lens 43 for diffusing light. 44 may be provided.

[0254] The backlight unit 4340b shown in FIG. 28(B) has a diffusion plate 4352 directly below the pixels. The light guide plate 4341 is provided at the end of the light guide plate 4341. The light guide plate 4341 has an uneven shape on the side opposite to the diffusion plate 4352. The guided light can be scattered by the uneven surface and emitted in the direction of the diffusion plate 4352.

[0255] The light emitting element 4342 can be fixed to a printed circuit board 4347. ), the light emitting elements 4342 of each color of RGB are shown overlapping, but The light emitting elements 4342 of each color B can be arranged side by side. A reflective layer 4348 that reflects visible light is provided on the side opposite to the light emitting element 4342. It is okay to do so.

[0256] The backlight unit 4340b can reduce the number of light-emitting elements 4342. It can be made low cost and thin.

[0257] The liquid crystal element may be a light-scattering type liquid crystal element. It is preferable to use an element having a composite material of a liquid crystal and a polymer. For example, a polymer dispersed liquid crystal Alternatively, a polymer network liquid crystal (PNLC) A liquid crystal (LC) element may also be used.

[0258] The light-scattering liquid crystal element is a liquid crystal layer in a three-dimensional network structure of a resin part sandwiched between a pair of electrodes. The liquid crystal part is made of a material such as nematic liquid crystal. The resin portion can be made of a photo-curable resin. For example, monofunctional monomers such as acrylates and methacrylates, diacrylates, triacrylates, Multifunctional monomers such as acrylates, dimethacrylates, trimethacrylates, or A polymerizable compound in which these are mixed can be used.

[0259] Light-scattering liquid crystal elements utilize the anisotropy of the refractive index of the liquid crystal material to transmit or scatter light. The resin portion may also have anisotropy in refractive index. When the liquid crystal molecules are aligned in a certain direction according to the voltage applied to the element, the refraction of the liquid crystal part and the resin part A direction occurs in which the difference in the refractive index becomes smaller, and the light incident along this direction is scattered by the liquid crystal section. Therefore, the light-scattering liquid crystal element is visually perceived as transparent from this direction. On the other hand, when the alignment of the liquid crystal molecules becomes random according to the applied voltage, the liquid crystal part and the resin Since there is no significant change in the refractive index difference between the liquid crystal and the liquid crystal, the incident light is scattered by the liquid crystal. Therefore, the light-scattering liquid crystal element remains opaque regardless of the viewing direction.

[0260] FIG. 29(A) shows a case where the liquid crystal element 4013 of the display device of FIG. 28(A) is replaced with a light scattering type liquid crystal element 401 The light scattering type liquid crystal element 4016 has a liquid crystal portion and a resin portion. The field sequencer includes a composite layer 4009 and electrode layers 4030 and 4031. The elements related to the drive are the same as those in FIG. 28(A), but a light scattering type liquid crystal element 4016 is used. In this case, the alignment film and the polarizing plate are not required. 1, but may be columnar.

[0261] FIG. 29(B) shows a case where the liquid crystal element 4013 of the display device of FIG. 28(B) is replaced with a light scattering type liquid crystal element 401 28(B), the light scattering type liquid crystal element 4016 is replaced with a voltage It operates in a mode where it transmits light when no voltage is applied and scatters light when a voltage is applied. By adopting this configuration, the normal state (the state where no display is made) ) can be used to make a transparent display device. In this case, when the light scattering operation is performed, It is possible to display in color.

[0262] Modified examples of the display device shown in FIG. 29(B) are shown in FIGS. 30(A) to 30(E). In A) to E), for clarity, some elements of FIG. 29(B) are used, and other elements are is omitted and shown in the figure.

[0263] 30(A) shows a structure in which the substrate 4001 functions as a light guide plate. The outer surface of the light guide plate may be provided with an uneven shape. In addition, there is no attenuation of light due to the light guide plate. Therefore, the light emitted from the light emitting element 4342 can be used efficiently.

[0264] FIG. 30(B) shows a configuration in which light is incident from the vicinity of the end of the composite layer 4009. The total reflection at the interface between the composite layer 4009 and the substrate 4001 is By using the resin of the composite layer 4009, light can be emitted from the light-scattering liquid crystal element to the outside. The portion is made of a material having a refractive index greater than that of the substrate 4001 and the substrate 4006 .

[0265] Note that the light-emitting element 4342 is not only provided on one side of the display device, but also as shown in FIG. Alternatively, the light emitting element 43 may be provided on two sides facing each other. Furthermore, the light emitting element 43 may be provided on three or four sides. By providing 42 on multiple sides, it is possible to compensate for light attenuation and support large-area display elements. It is possible.

[0266] FIG. 30(D) shows a display device in which light emitted from a light emitting element 4342 passes through a mirror 4345. This configuration makes it easier to guide light to the display device from a certain angle. Therefore, total internal reflection can be efficiently achieved.

[0267] FIG. 30(E) shows a configuration having a stack of layers 4003 and 4004 on a composite layer 4009. One of the layer 4003 and the layer 4004 is a support such as a glass substrate, and the other is an inorganic The composite layer 40 may be formed of a film, an organic resin coating film, or a similar material. The resin portion of the layer 4009 is made of a material having a refractive index greater than that of the layer 4004. The layer 4002 uses a material having a refractive index higher than that of the layer 4003 .

[0268] A first interface is formed between composite layer 4009 and layer 4004, and layer 4004 and layer 400 A second interface is formed between the first interface and the second interface. The light that passes through can be totally reflected at the second interface and returned to the composite layer 4009. Therefore, the light emitted by the light emitting element 4342 can be used efficiently.

[0269] The configurations in FIG. 29(B) and FIG. 30(A) to (E) can be combined with each other. can be done.

[0270] This embodiment mode can be implemented by appropriately combining with the configurations described in other embodiment modes. It is possible.

[0271] (Embodiment 3) In this embodiment mode, the transistors described in the above embodiment modes can be replaced with An example of a transistor that can be used will be described with reference to the drawings.

[0272] The display device of one embodiment of the present invention includes a bottom-gate transistor and a top-gate transistor. The present invention can be fabricated using various types of transistors, such as a transistor having a MOSFET. The semiconductor layer materials and transistor structures used can be easily replaced to suit the production line. It is possible.

[0273] [Bottom-gate transistor] FIG. 31(A1) shows a channel protection transistor, which is a type of bottom gate transistor. 31(A1) is a cross-sectional view of the transistor 810 in the channel length direction. The transistor 810 is formed on the substrate 771. The electrode 746 is provided with an insulating layer 772 interposed therebetween. The semiconductor layer 742 is provided. The electrode 746 can function as a gate electrode. The insulating layer 726 is provided as a gate electrode. It can function as a gate insulating layer.

[0274] In addition, an insulating layer 741 is provided on a channel formation region of the semiconductor layer 742. Electrodes 744a and 744b are provided on the insulating layer 726 in contact with a portion of the insulating layer 726. 744a can function as either a source or drain electrode. It can function as the other of the source electrode and the drain electrode. A portion of the pole 744 b is formed on the insulating layer 741 .

[0275] The insulating layer 741 can function as a channel protection layer. By providing the electrode 744a and the electrode 744b, the exposure of the semiconductor layer 742 that occurs when the electrode 744a and the electrode 744b are formed can be prevented. Therefore, when the electrodes 744a and 744b are formed, the semiconductor layer This can prevent the channel formation region 742 from being etched. According to this, a transistor with good electrical characteristics can be realized.

[0276] The transistor 810 includes an electrode 744a, an electrode 744b, and an insulating layer 741. The insulating layer 729 is disposed on the insulating layer 728 .

[0277] When an oxide semiconductor is used for the semiconductor layer 742, at least one of the electrodes 744a and 744b At least in the area in contact with the semiconductor layer 742, oxygen is taken from a part of the semiconductor layer 742, and oxygen vacancies are formed. It is preferable to use a material that can generate oxygen vacancies in the semiconductor layer 742. The carrier concentration in the resulting region increases, and the region becomes n-type. + layer). Therefore, the region can function as a source region or a drain region. When an oxide semiconductor is used for the conductor layer 742, oxygen is taken from the semiconductor layer 742, and oxygen vacancies are eliminated. Examples of materials that can be used include tungsten and titanium. do.

[0278] The source and drain regions are formed in the semiconductor layer 742, forming an electrode 744a In addition, the contact resistance between the electrode 744b and the semiconductor layer 742 can be reduced. The electrical characteristics of the transistor, such as the effective mobility and threshold voltage, can be improved. can.

[0279] When a semiconductor such as silicon is used for the semiconductor layer 742, the semiconductor layer 742 and the electrode 744a and between the semiconductor layer 742 and the electrode 744b, as an n-type semiconductor or a p-type semiconductor. It is preferable to provide a layer that functions as an n-type semiconductor or a p-type semiconductor. It can function as a source or drain region of a transistor.

[0280] The insulating layer 729 has a function of preventing or reducing diffusion of impurities into the transistor from the outside. It is preferable to form the insulating layer 729 using a material having the above structure. You can also do this.

[0281] The transistor 811 shown in FIG. 31A2 has a back gate electrode over the insulating layer 729. The transistor 810 differs from the transistor 810 in that it has a functioning electrode 723. The electrode 723 is an electrode It can be formed using the same materials and methods as 746.

[0282] In general, the back gate electrode is formed of a conductive layer, and the gate electrode and the back gate electrode form a semiconductor. The back gate electrode is disposed so as to sandwich the channel forming region of the layer. The back gate electrode can be made to function in the same manner as the gate electrode. Alternatively, the potential may be set to ground potential (GND potential) or any other potential. By changing the potential of the gate electrode independently of the gate electrode, the threshold voltage of the transistor can be controlled. The voltage can be varied to any desired value.

[0283] In addition, both the electrode 746 and the electrode 723 can function as gate electrodes. Therefore, the insulating layer 726, the insulating layer 728, and the insulating layer 729 are gate insulating layers. The electrode 723 can function as a layer between the insulating layer 728 and the insulating layer 729. It may also be provided in.

[0284] When one of the electrodes 746 and 723 is referred to as a "gate electrode," the other is referred to as a "back electrode." For example, in the transistor 811, the electrode 723 is called a "gate electrode." When the term "electrode" is used, the electrode 746 is referred to as a "back gate electrode." When the transistor 811 is used as a top gate electrode, In addition, either the electrode 746 or the electrode 723 can be considered as a "first The first gate electrode is sometimes referred to as the "first gate electrode" and the other as the "second gate electrode."

[0285] By providing the electrode 746 and the electrode 723 with the semiconductor layer 742 interposed therebetween, the electrode 74 6 and the electrode 723 are set to the same potential, the region where carriers flow in the semiconductor layer 742 The area becomes larger in the film thickness direction, so the amount of carrier movement increases. As the on-current of the transistor 811 increases, the field effect mobility also increases.

[0286] Therefore, the transistor 811 is a transistor having a large on-state current relative to its area. That is, the area occupied by the transistor 811 is set to According to one embodiment of the present invention, the area occupied by a transistor can be reduced. Therefore, according to one embodiment of the present invention, a highly integrated semiconductor device can be realized. It is possible.

[0287] In addition, since the gate electrode and back gate electrode are formed from a conductive layer, they can be The function of preventing the electric field generated from acting on the semiconductor layer where the channel is formed (especially static electricity The back gate electrode has an electric field shielding function against the semiconductor layer. By forming a back gate electrode and covering the semiconductor layer with the back gate electrode, the electric field shielding function can be improved. .

[0288] In addition, by forming the back gate electrode using a conductive film having a light-shielding property, This prevents light from entering the semiconductor layer from the side. This can prevent degradation of electrical characteristics such as a shift in the threshold voltage of the transistor. .

[0289] According to one embodiment of the present invention, a highly reliable transistor can be provided. A highly reliable semiconductor device can be realized.

[0290] FIG. 31(B1) shows a channel protection type transistor 82 having a different configuration from that shown in FIG. 31(A1). 8 is a cross-sectional view of the transistor 820 in the channel length direction. It has a similar structure, but differs in that an insulating layer 741 covers the edge of a semiconductor layer 742. In addition, an opening formed by selectively removing a part of the insulating layer 729 overlapping the semiconductor layer 742 In this portion, the semiconductor layer 742 and the electrode 744a are electrically connected. In another opening formed by selectively removing a portion of the insulating layer 729 that overlaps with the semiconductor layer 42, The insulating layer 729 is electrically connected to the electrode 744b. The overlapping region can function as a channel protection layer.

[0291] The transistor 821 shown in FIG. 31B2 has a back gate electrode over the insulating layer 729. It differs from transistor 820 in that it has a functioning electrode 723 .

[0292] By providing the insulating layer 729, the semiconductor generated when the electrode 744a and the electrode 744b are formed can be prevented. Therefore, when forming the electrode 744a and the electrode 744b, the layer 742 can be prevented from being exposed. In addition, the semiconductor layer 742 can be prevented from becoming thin.

[0293] Also, the transistors 820 and 821 are the same as the transistors 810 and 821. The distance between the electrode 744a and the electrode 746 and the distance between the electrode 744b and the electrode 746 are smaller than the distance between the electrode 744a and the electrode 746 and the electrode 744b. Therefore, the distance between the electrodes 744a and 746 is increased. In addition, the parasitic capacitance generated between the electrode 744b and the electrode 746 can be reduced. According to one embodiment of the present invention, a transistor with favorable electrical characteristics can be realized. Cut.

[0294] The transistor 825 shown in FIG. 31C1 is a bottom-gate transistor. 8 is a cross-sectional view of a channel-etched transistor 825 in the channel length direction. The resistor 825 forms the electrodes 744a and 744b without using the insulating layer 729. Therefore, a part of the semiconductor layer 742 that is exposed when the electrodes 744a and 744b are formed is On the other hand, since the insulating layer 729 is not provided, the transistor production It can improve sexuality.

[0295] The transistor 825 shown in FIG. 31C2 has a back gate electrode over the insulating layer 729. It differs from transistor 820 in that it has a functioning electrode 723 .

[0296] Transistors 810, 811, 820, 821, 825, 826 are cross-sectional views in the channel width direction.

[0297] In the structures shown in Figures 32(B2) and (C2), the gate electrode and the back gate electrode are connected. The gate electrode and the back gate electrode have the same potential. It is sandwiched between a gate electrode and a back gate electrode.

[0298] The length of each of the gate electrode and the back gate electrode in the channel width direction is 2 in the channel width direction, and the entire channel width direction of the semiconductor layer 742 is 726, 741, 728, and 729 are sandwiched between the gate electrode or the back gate electrode. It is a structure that

[0299] With this structure, the semiconductor layer 742 included in the transistor can be used as a gate electrode and a barrier layer. The gate electrode can be electrically surrounded by the electric field of the gate electrode.

[0300] Like the transistor 821 or the transistor 826, the gate electrode and the back gate The electric field of the electrode electrically surrounds the semiconductor layer 742 in which the channel formation region is to be formed. The device structure of the transistor is called the Surrounded channel (S-channel el) structure.

[0301] By using an S-channel structure, either one of the gate electrode and the back gate electrode By both, an electric field is effectively applied to the semiconductor layer 742 to induce a channel. This improves the current driving capability of the transistor and makes it possible to obtain high on-current characteristics. In addition, since it is possible to increase the on-current, it is possible to miniaturize transistors. In addition, the S-channel structure allows for mechanical Strength can be increased.

[0302] [Top-gate transistor] The transistor 842 illustrated in FIG. 33A1 is a top-gate transistor. The transistor 842 is formed by forming the insulating layer 729 and then forming the electrode 744a and the electrode 744b. The transistor 830 and the transistor 840 differ from each other in that the electrode 744a is formed. The electrode 744b is formed by a semiconductor layer in an opening formed in the insulating layer 728 and the insulating layer 729. The conductive layer 742 is electrically connected to the conductive layer 742.

[0303] In addition, a part of the insulating layer 726 that does not overlap with the electrode 746 is removed, and the electrode 746 and the remaining insulating layer 726 as a mask, an impurity 755 is introduced into the semiconductor layer 742, The impurity region can be formed in a self-aligned manner in 742. Transistor 842 has an area where insulating layer 726 extends beyond the edge of electrode 746 . The impurity concentration in the region of the semiconductor layer 742 into which the impurity 755 is introduced via the insulating layer 726 is The region where the impurity 755 is introduced without the insulating layer 726 interposed therebetween is smaller than the region where the impurity 755 is introduced without the insulating layer 726 interposed therebetween. 2 is a lightly doped drain (LDD) in an area that does not overlap with the electrode 746. ) region is formed.

[0304] The transistor 843 shown in FIG. 33A2 has an electrode 723. 2. The transistor 843 has an electrode 723 formed on a substrate 771. The electrode 723 has a region overlapping with the semiconductor layer 742 with the insulating layer 772 interposed therebetween. can function as a back gate electrode.

[0305] In addition, the transistor 844 shown in FIG. 33(B1) and the transistor shown in FIG. 33(B2) As in the case of the electrode 845, the insulating layer 726 in the area that does not overlap with the electrode 746 may be entirely removed. In addition, the transistor 846 shown in FIG. 33(C1) and the transistor shown in FIG. 33(C2) The insulating layer 726 may remain, as may the insulating layer 847.

[0306] The transistors 842 to 847 are also formed with the electrode 746. As a result, the semiconductor layer 742 is doped with impurities 755 using the mask. According to one aspect of the present invention, an impurity region can be formed in a self-aligned manner. Furthermore, according to one aspect of the present invention, a transistor with good integration properties can be realized. Therefore, a highly reliable semiconductor device can be realized.

[0307] Transistors 842, 843, 844, 845, and 846 are shown in FIGS. 847 are cross-sectional views in the channel width direction.

[0308] The transistors 843, 845, and 847 are respectively However, the present invention is not limited to this, and the transistor 84 may have an S-channel structure. 3. Transistor 845 and transistor 847 should not be of S-channel structure. That's fine.

[0309] This embodiment mode can be implemented by appropriately combining with the configurations described in other embodiment modes. It is possible.

[0310] (Fourth embodiment) Examples of electronic devices that can use the display device according to one embodiment of the present invention include display devices, personal computers, and the like. a personal computer, an image storage device or image reproduction device equipped with a recording medium, a mobile phone, a mobile phone Game consoles, including those with a camcorder, portable data terminals, e-book terminals, video cameras, digital still cameras Cameras such as cameras, goggle-type displays (head-mounted displays), navigation systems, audio playback devices (car audio, digital audio players, etc.), copying machines, fax machines, printers, printer-combined machines, automated teller machines (ATMs), Examples of such electronic devices include vending machines. Specific examples of these electronic devices are shown in Figure 35.

[0311] FIG. 35(A) shows a digital camera, which includes a housing 961, a shutter button 962, a microphone 963, and a microphone 964. 63, speaker 967, display unit 965, operation keys 966, zoom lever 968, lens 9 By using the display device of one embodiment of the present invention for the display portion 965, various images can be displayed. The following display can be performed.

[0312] FIG. 35(B) shows a digital signage with a large display unit 922. The display device of one embodiment of the present invention is used for the display portion 922. Therefore, a high-quality display can be achieved.

[0313] FIG. 35C shows an example of a mobile phone, which includes a housing 951, a display unit 952, and an operation button 953. , an external connection port 954, a speaker 955, a microphone 956, a camera 957, etc. The mobile phone has a touch sensor on the display unit 952. All operations, such as inputting, can be performed by touching the display unit 952 with a finger or a stylus. The housing 901 and the display portion 952 are flexible and can be folded as shown in the figure. By using the display device of one embodiment of the present invention for the display portion 952, , various images can be displayed.

[0314] FIG. 35(D) shows a video camera, which includes a first housing 901, a second housing 902, a display unit 903, The operation key 904, the lens 905, the connection part 906, the speaker 907, etc. The lens 904 and the lens 905 are provided in the first housing 901, and the display unit 903 is provided in the second housing 902. By using the display device of one embodiment of the present invention for the display portion 903, various It is possible to display a clear image.

[0315] FIG. 35(E) shows a television, which includes a housing 971, a display unit 973, operation keys 974, and a speaker 975. The display unit 973 has a touch sensor 975, a communication connection terminal 976, an optical sensor 977, etc. The display device of one embodiment of the present invention is provided in the display portion 973. By using this, various images can be displayed.

[0316] FIG. 35(F) shows a portable data terminal, which includes a housing 911, a display portion 912, a speaker 913, a camera, and a camera body. The display unit 912 has a touch panel function for inputting and outputting information. By using the display device of one embodiment of the present invention for the display portion 912, various images can be displayed. The following display can be performed.

[0317] This embodiment mode can be implemented by appropriately combining with the configurations described in other embodiment modes. It is possible. [Explanation of symbols]

[0318] 10: circuit, 11: circuit, 12: pixel block, 13: source driver, 14a: gate Driver, 14b: gate driver, 15: circuit, 20: pixel, 101: transistor, 102: transistor, 103: transistor, 104: capacitance element, 105: transistor 106: transistor, 107: capacitance element, 110: circuit block, 111: 112: transistor, 113: capacitance element, 114: light emitting element, 115: 116: capacitance element; 117: liquid crystal element; 118: transistor; 119: Register, 120: Circuit, 121: Wiring, 122: Wiring, 123: Wiring, 125: Wiring, 1 26: Wiring, 127: Wiring, 128: Wiring, 129: Wiring, 130: Wiring, 131: Wiring , 132: Wiring, 133: Wiring, 134: Wiring, 135: Wiring, 215: Display, 221 a: scanning line driving circuit, 231a: signal line driving circuit, 232a: signal line driving circuit, 241a : common line driving circuit, 723: electrode, 726: insulating layer, 728: insulating layer, 729: insulating layer, 741: insulating layer, 742: semiconductor layer, 744a: electrode, 744b: electrode, 746: electrode, 755: impurity, 771: substrate, 772: insulating layer, 810: transistor, 811: transistor Transistor, 820: Transistor, 821: Transistor, 825: Transistor, 82 6: transistor, 830: transistor, 840: transistor, 842: transistor 843: transistor, 844: transistor, 845: transistor, 846: Transistor, 847: Transistor, 901: Housing, 902: Housing, 903: Display unit, 9 04: Operation keys, 905: Lens, 906: Connection part, 907: Speaker, 911: Housing, 912: Display unit, 913: Speaker, 919: Camera, 921: Pillar, 922: Display unit, 9 51: Housing, 952: Display unit, 953: Operation buttons, 954: External connection port, 955: Speaker, 956: Microphone, 957: Camera, 961: Housing, 962: Shutter button 963: microphone, 965: display, 966: operation keys, 967: speaker, 968: Arm lever, 969: Lens, 971: Housing, 973: Display, 974: Operation keys, 97 5: Speaker, 976: Communication connection terminal, 977: Optical sensor, 4001: Circuit board, 4003 : layer, 4004: layer, 4005: sealing material, 4006: substrate, 4008: liquid crystal layer, 400 9: composite layer, 4010: transistor, 4011: transistor, 4013: liquid crystal element, 4014: Wiring, 4015: Electrode, 4016: Light-scattering liquid crystal element, 4017: Electrode, 40 18: FPC, 4019: anisotropic conductive layer, 4020: capacitance element, 4021: electrode, 402 2: transistor, 4023: transistor, 4030: electrode layer, 4031: electrode layer, 4 032: Insulating layer, 4033: Insulating layer, 4035: Spacer, 4041: Printed circuit board, 4 042: Integrated circuit, 4102: Insulating layer, 4103: Insulating layer, 4104: Insulating layer, 4110 : insulating layer, 4111: insulating layer, 4112: insulating layer, 4131: colored layer, 4132: light-shielding layer , 4133: insulating layer, 4200: input device, 4210: touch panel, 4227: electrode, 4228: Electrode, 4237: Wiring, 4238: Wiring, 4239: Wiring, 4263: Substrate, 4272b: FPC, 4273b: IC, 4340a: Backlight unit, 4340 b: Backlight unit, 4341: Light guide plate, 4342: Light emitting element, 4344: Lens , 4345: mirror, 4347: printed circuit board, 4348: reflective layer, 4352: diffuser plate, 4510: partition wall, 4511: light-emitting layer, 4513: light-emitting element, 4514: filler

Claims

1. A source driver; a first circuit electrically connected to the source driver; a first transistor electrically connected to the first circuit; a second transistor electrically connected to the first transistor; and a first light-emitting element electrically connected to a gate of the second transistor and one of a source and a drain of the second transistor; a third transistor electrically connected to the first circuit, a fourth transistor electrically connected to the third transistor, and a second light-emitting element electrically connected to a gate of the fourth transistor and one of a source and a drain of the fourth transistor, the first circuit includes a fifth transistor, a sixth transistor, and a capacitor; one of the source and the drain of the fifth transistor is electrically connected to the source driver; the other of the source and the drain of the fifth transistor is electrically connected to a first electrode of the capacitor; one of a source and a drain of the sixth transistor is electrically connected to a second electrode of the capacitor; The display device, wherein the first circuit has a function of adding second data to first data supplied from the source driver.

2. In claim 1, The display device, wherein the first light-emitting element has a function of displaying based on data obtained by adding second data to the first data.

3. In claim 1 or claim 2, The second light-emitting element has a function of displaying based on data obtained by adding second data to the first data.

4. In any one of claims 1 to 3, the fifth transistor and the sixth transistor each have a metal oxide in a channel formation region; The display device, wherein the metal oxide contains In.

5. In any one of claims 1 to 4, the fifth transistor and the sixth transistor each have a metal oxide in a channel formation region; The display device, wherein the metal oxide comprises In, Zn, and M (M is Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd, or Hf).

Images