Charge pump, charge pump system and control method of charge pump

Abstract

To provide a charge pump for appropriately controlling an image sensor.SOLUTION: A charge pump comprises: a flying capacitor; a push-pull driver connected with one end of the flying capacitor; a first switch provided between the one end of the flying capacitor and a first reference conductor; a second switch provided between the other end of the flying capacitor and the first reference conductor; and a third switch provided between the other end of the flying capacitor and an output terminal, wherein the push-pull driver comprises fourth and fifth switches one end of each is connected with the one end of the flying capacitor, the other end of the fourth switch is connected with a second reference conductor different from the first reference conductor, and the other end of the fifth switch is connected with the first reference conductor.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present disclosure relates to charge pumps, charge pump systems, and charge pump control methods, and in particular to improvements therein. [Background technology]

[0002] Image sensors such as CMOS image sensors are widely used. Generally, image sensors have a structure in which multiple pixels are arranged across multiple rows. Each pixel uses a transistor. The pixel value of each pixel is controlled by individually controlling the transistor of each pixel using a drive circuit. A charge pump is used in the drive circuit, and a control voltage from the charge pump is output from the drive circuit to each pixel.

[0003] Charge pumps are disclosed as technologies related to the present disclosure in the following Patent Document 1 and Non-Patent Document 1. Non-Patent Document 2 discloses a technology for generating a control signal in feedback control according to the difference between two input voltages. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] U.S. Patent No. 5,546,296 [Non-patent literature]

[0005] [Non-Patent Document 1] JY Lee, et. al., “A Regulated Charge Pump With Small Ripple Voltage and Fast Start-Up,” in IEEE Journal of Solid-State Circuits, vol. 41, no. 2, Feb. 2006. [Non-patent document 2] R. Hogervorst, et. al, “A Compact Power-Efficient 3 V CMOS Rail-to-Rail Input / Output Operational Amplifier for VLSI Libraries,” IEEE Journal of Solid-State Circuits, vol. 29, no. 12, Dec. 1994. Summary of the Invention [Problem to be solved by the invention]

[0006] Typically, image sensors have multiple columns of readout signal lines for reading pixel values ​​from each pixel. The readout signal lines can be coupled to the conductors connecting each pixel to the driver circuitry through stray capacitance. In this case, the voltage on the readout signal lines can affect the operation of the driver circuitry and each pixel, resulting in artifacts in the image displayed by the image sensor.

[0007] One possible method to suppress artifacts is to use a drive circuit equipped with a charge pump to control the voltage output to each pixel. However, conventional charge pumps such as those described in Patent Document 1 and Non-Patent Document 1 cannot control the voltage output to each pixel in both positive and negative polarities relative to the potential of the ground conductor, making it difficult to achieve appropriate control.

[0008] An object of the present disclosure is to provide a charge pump for properly controlling an image sensor. [Means for solving the problem]

[0009] The charge pump according to the present disclosure comprises a flying capacitor, a push-pull driver provided at one end of the flying capacitor, a first switch provided between one end of the flying capacitor and a first reference conductor, a second switch provided between the other end of the flying capacitor and the first reference conductor, and a third switch provided between the other end of the flying capacitor and an output terminal, wherein the push-pull driver comprises a fourth switch and a fifth switch, each having one end connected to one end of the flying capacitor, the other end of the fourth switch being connected to a second reference conductor separate from the first reference conductor, and the other end of the fifth switch being connected to the first reference conductor.

[0010] Moreover, a charge pump system according to the present disclosure includes a plurality of charge pumps, each of which includes a flying capacitor, a push-pull driver provided at one end of the flying capacitor, a first switch provided between one end of the flying capacitor and a first reference conductor, a second switch provided between the other end of the flying capacitor and the first reference conductor, and a third switch provided between the other end of the flying capacitor and an output terminal, the push-pull driver includes a fourth switch and a fifth switch, each of which has one end connected to one end of the flying capacitor, the other end of the fourth switch being connected to a second reference conductor different from the first reference conductor, and the other end of the fifth switch being connected to the first reference conductor, the output terminals of the plurality of charge pumps being connected in common, a clock signal for controlling the fifth switch from the first switch provided in each of the plurality of charge pumps being input to each of the plurality of charge pumps, and the phase of the clock signal differs for each of the plurality of charge pumps.

[0011] Also, a control method for a charge pump according to the present disclosure includes the charge pump comprising: a flying capacitor; a push-pull driver provided at one end of the flying capacitor; a first switch provided between one end of the flying capacitor and a first reference conductor; a second switch provided between the other end of the flying capacitor and the first reference conductor; and a third switch provided between the other end of the flying capacitor and an output terminal; the push-pull driver comprises a fourth switch and a fifth switch, each having one end connected to one end of the flying capacitor, the other end of the fourth switch connected to a second reference conductor different from the first reference conductor, and the other end of the fifth switch connected to the first reference conductor; and the control method includes alternately turning on and off the first switch and the second switch, turning on and off the third switch together with the first switch, and turning on and off the fourth switch and the fifth switch together with the second switch. [Effects of the Invention]

[0012] According to the present disclosure, a charge pump for appropriately controlling an image sensor can be provided. [Brief explanation of the drawings]

[0013] [Figure 1] FIG. 1 is a diagram illustrating a charge pump according to a basic configuration of the present disclosure. [Figure 2] FIG. 10 is a diagram illustrating the relationship between an output voltage and time. [Figure 3] FIG. 10 is a diagram illustrating the control characteristics of a current source. [Figure 4] FIG. 1 illustrates a charge pump according to an embodiment of the present disclosure. [Figure 5] 3A and 3B are diagrams illustrating time waveforms of a clock signal and an inverted clock signal. [Figure 6] 3A and 3B are diagrams illustrating time waveforms of an offset clock signal and an offset inverted clock signal. [Figure 7] FIG. 1 is a diagram showing a push-pull driver together with a part of an error amplifier. [Figure 8] FIG. 10 is a diagram showing a configuration in which each voltage shift power supply is removed. [Figure 9] FIG. 10 is a diagram showing the relationship between the charging current and the control voltage of the flying capacitor. [Figure 10] FIG. 10 is a diagram showing the relationship between the charging current and the control voltage of the flying capacitor. [Figure 11] FIG. 1 is a diagram illustrating a voltage shift circuit. [Figure 12] FIG. 1 is a diagram illustrating a charge pump system according to a first application embodiment of the present disclosure. [Figure 13] FIG. 10 is a diagram illustrating a charge pump system according to a second application embodiment of the present disclosure. [Figure 14] FIG. 10 is a diagram illustrating a charge pump according to a modified example of the present disclosure. [Figure 15] FIG. 1 is a diagram illustrating a voltage shift circuit. DETAILED DESCRIPTION OF THE INVENTION

[0014] Embodiments of the present disclosure will be described with reference to the drawings. Identical components shown in multiple drawings are assigned the same reference numerals to simplify the description. Terms indicating directions such as up and down in this specification indicate directions in the drawings. These terms indicating directions are used for the convenience of explanation and do not limit the orientation of each component when it is arranged.

[0015] 1 shows a charge pump 100 according to the basic configuration of the present disclosure. The charge pump 100 includes a current source 20, a driver switch 10, a first switch 11, a flying capacitor 22, a second switch 12, a third switch 13, an output terminal 24, an error amplifier 26, and a controller 28.

[0016] The ground terminal of the current source 20 is connected to the ground conductor G. One end of the driver switch 10 is connected to the positive terminal of the current source 20. The other end of the driver switch 10 is connected to one end 36 of the flying capacitor 22.

[0017] A first switch 11 is connected between one end 36 of the flying capacitor 22 and the ground conductor G. A second switch 12 is connected between the other end 38 of the flying capacitor 22 and the ground conductor G. The load circuit 30 includes a load capacitor 32 and a load current source 34 connected in parallel. A third switch 13 is connected between the other end 38 of the flying capacitor 22 and the upper end of the load circuit 30.

[0018] The error amplifier 26 outputs the target voltage V TARGET A control voltage V that reduces the magnitude of the difference value obtained by subtracting the output voltage Vo at the upper end of the load circuit 30 from CTRL is output to the current source 20.

[0019] The controller 28 may include a processor as hardware that executes a program to control the charge pump 102. The controller 28 may include a memory that stores the program. The driver switch 10 and the second switch 12 control the charge pump 102 in response to a control signal Φ B The first switch 11 and the third switch 13 are controlled to be turned on or off simultaneously by a control signal Φ output from the controller 28. The pair of the driver switch 10 and the second switch 12 and the pair of the first switch 11 and the third switch 13 are alternately turned on and off. In the following description, the operating phase in which the driver switch 10 and the second switch 12 are on is referred to as Φ. B The operating phase in which the first switch 11 and the third switch 13 are on is called the Φ phase.

[0020] The operation of the charge pump 100 is as follows: Figure 2 shows the relationship between the output voltage Vo and time, where the horizontal axis represents time and the vertical axis represents the output voltage Vo. Φ B After the phase is maintained for a time Tc / 2, the operation phase becomes the Φ phase, and then the operation of maintaining the operation phase in the Φ phase for a time Tc / 2 is repeated. BIn the Φ phase, the output voltage Vo increases to Vo=-V1, and in the Φ phase, the output voltage Vo becomes Vo=-V2.

[0021] The capacitance of flying capacitor 22 is C F and the capacitance of the load capacitor 32 is C L Let Φ B The charge charged in the flying capacitor 22 during the F ·V F and the charge stored in the load capacitor 32 is C L V1, the voltage V across the terminals of the flying capacitor 22 F and a voltage V1 across the load capacitor 32 is assumed.

[0022] In addition, the charge charged in the flying capacitor 22 in the Φ phase is C F V2, and the charge stored in the load capacitor 32 is C L The voltage V2 across each of the flying capacitor 22 and the load capacitor 32 is assumed to be V2.

[0023] According to the law of conservation of charge, Φ B The sum C of the charge charged to the flying capacitor 22 and the charge charged to the load capacitor 32 in the phase F ·V F +C L V1 is the sum C of the charge charged in the flying capacitor 22 and the charge charged in the load capacitor 32 immediately after the start of the Φ phase. F V2+C L ·V2 is equal to V. Therefore, (Equation 1) holds.

[0024] (Number 1)C F ·V F +C L V1=C F V2+C L V2

[0025] By solving (Equation 1) for -V2, (Equation 2) is obtained.

[0026] (Number 2)-V2=-(C F ·V F +C L V1) / (C F +C L )

[0027] In this way, Φ B The output voltage Vo=-V2 in the Φ phase is expressed by the output voltage Vo=-V1 in the Φ phase.

[0028] The load current I flowing into the load current source 34 L When is not 0, Φ B The charge Q supplied to the load capacitor 32 during a phase is expressed by Equation 3.

[0029] (Math 3)Q=C L (-V1-(-V2))=C F ·(V F -V1)·C L / (C F +C L )

[0030] The charge Q is the change in output voltage Vo during time Tc, −V1−(−V2), multiplied by the capacitance C of load capacitor 32. L That is, a charge Q is supplied to the load capacitor 32 by the change in the terminal voltage of the load capacitor 32, and by dividing this charge Q by the time Tc, the load current I L is required.

[0031] (Number 4)I L =Q / Tc=C L C F ·(V F -V1) / (C F +C L ) / Tc

[0032] By solving (Equation 4) for -V1, Φ B The voltage −V1 that the output voltage Vo reaches in the phase is determined.

[0033] (Math 5)-V1≒-VF +I L Tc / C F

[0034] However, the capacitance C of the load capacitor 32 L is the capacitance C of the flying capacitor 22 F It is assumed that the value is sufficiently large compared to C L >>C F (5) is assumed to be true. The time Tc or the voltage V output by the current source 20 F This shows that by feedback controlling the output voltage Vo=-V1, it can be controlled to approach or match a certain voltage.

[0035] 3 shows the control characteristics of the current source 20. The horizontal axis represents the control voltage V CTRL The vertical axis represents the charging current I output from the current source 20. F The control voltage V CTRL However, the intermediate voltage V M When the charging current I F becomes 0. Control voltage V CTRL is the intermediate voltage V M If the control voltage V CTRL The discharge current of the flying capacitor 22 increases with the increase of the control voltage V CTRL is the intermediate voltage V M When the control voltage V CTRL The charging current I of the flying capacitor 22 increases in the negative direction. F increases.

[0036] The error amplifier 26 detects whether the output voltage Vo is equal to the target voltage V TARGET When the control voltage V CTRL By increasing the charging current I F , and the voltage V across the terminals of the flying capacitor 22 F The error amplifier 26 reduces the output voltage Vo to the target voltage V TARGET When the control voltage V CTRL Decrease the charging current I F, and the voltage V across the terminals of the flying capacitor 22 F The error amplifier 26 increases the output voltage Vo to the target voltage V TARGET When the control voltage V CTRL The intermediate voltage V M As the charging current I F is set to 0, and the terminal voltage V of the flying capacitor 22 F The error amplifier 26 may be a differential amplifier circuit, an operational amplifier, or the like that amplifies and outputs the difference between two input voltages. The control voltage V CTRL The output voltage Vo is set to the target voltage V TARGET Approaching or matching. ?

[0037] 4 shows a charge pump 102 according to an embodiment of the present disclosure. The charge pump 102 is connected to a ground conductor G as a first reference conductor and a power supply line 52 as a second reference conductor. A power supply voltage VDD is applied between the power supply line 52 and the ground conductor G, and power is supplied to the charge pump 102 from the power supply line 52.

[0038] In the charge pump 102, the current source 20 and the driver switch 10 in FIG. 1 are configured as a push-pull driver 50. The push-pull driver 50 includes a PMOS switch S4 as a fourth switch and an NMOS switch S5 as a fifth switch. The push-pull driver 50 further includes a PMOS transistor S6 as a first current adjustment device and an NMOS transistor S7 as a second current adjustment device. Note that PMOS is an abbreviation for p-channel metal-oxide-semiconductor, and NMOS is an abbreviation for n-channel metal-oxide-semiconductor.

[0039] The source of the PMOS transistor S6 is connected to the power supply line 52. The drain of the PMOS transistor S6 is connected to the source of the PMOS switch S4. The drain of the PMOS switch S4 is connected to the source of the NMOS switch S5, and the drain of the NMOS switch S5 is connected to the source of the NMOS transistor S7. The drain of the NMOS transistor S7 is connected to the ground conductor G.

[0040] In the charge pump 102, the first switch 11 is configured with an NMOS switch S1. The drain of the NMOS switch S1 is connected to one end of the flying capacitor 22, and the source is connected to the ground conductor G. The second switch 12 is configured with an NMOS switch S2. The drain of the NMOS switch S2 is connected to the other end of the flying capacitor 22, and the source is connected to the ground conductor G. The third switch 13 is configured with an NMOS switch S3. The drain of the NMOS switch S3 is connected to the other end of the flying capacitor 22, and the source is connected to the output terminal 24.

[0041] The controller 28 outputs a clock signal CK to a clock path 40 connected to the gate of the PMOS switch S4 and the gate of the NMOS switch S1. This causes the clock signal CK to be guided to the gates of the PMOS switch S4 and the NMOS switch S1. The controller 28 also outputs an inverted clock signal CKB to an inverted clock path 42 connected to the gate of the NMOS switch S5. The inverted clock signal CKB has a high-low relationship with the clock signal CK. This causes the inverted clock signal CKB to be guided to the gate of the NMOS switch S5.

[0042] A negative charge pump 54 serving as an auxiliary circuit is connected to the clock path 40 and the inverted clock path 42. The second clock path 44 and the second inverted clock path 46 are also connected to the negative charge pump 54. The negative charge pump 54 includes a first voltage shift capacitor C1, a second voltage shift capacitor C2, a first PMOS switch W1, a second PMOS switch W2, a first NMOS transistor Z1, and a second NMOS transistor Z2.

[0043] The upper end of the first voltage shift capacitor C1 is connected to the clock path 40, and the lower end of the first voltage shift capacitor C1 is connected to the second clock path 44. That is, the second clock path 44 is connected to the clock path 40 via the first voltage shift capacitor C1. The second clock path 44 is connected to the gate of the NMOS switch S3. The upper end of the second voltage shift capacitor C2 is connected to the inverted clock path 42, and the lower end of the second voltage shift capacitor C2 is connected to the second inverted clock path 46. That is, the second inverted clock path 46 is connected to the inverted clock path 42 via the second voltage shift capacitor C2. The second inverted clock path 46 is connected to the gate of the NMOS switch S2.

[0044] The source of the first PMOS switch W1 is connected to the lower end of the first voltage shift capacitor C1, the gate is connected to the lower end of the second voltage shift capacitor C2, and the source of the second PMOS switch W2 is connected to the lower end of the second voltage shift capacitor C2, the gate is connected to the lower end of the first voltage shift capacitor C1.

[0045] The drains of the first PMOS switch W1 and the second PMOS switch W2 are connected to the drain of the first NMOS transistor Z1, and the source of the first NMOS transistor Z1 is connected to the drain of the second NMOS transistor Z2. The source of the second NMOS transistor Z2 is connected to the ground conductor G. The gates of the first NMOS transistor Z1 and the second NMOS transistor Z2 are connected to their respective drains. This maintains the voltage at the drains of the first PMOS switch W1 and the second PMOS switch W2, i.e., the voltage at the drain of the first NMOS transistor Z1, at 2Vt.

[0046] Here, the voltage Vt is the voltage drop between the drain and source of each of the first NMOS transistor Z1 and the second NMOS transistor Z2.

[0047] The voltage across each terminal of the first voltage shift capacitor C1 and the second voltage shift capacitor C2 is maintained at VDD-2Vt, with the lower end being a positive voltage relative to the upper end. In this way, the negative charge pump 54 charges its own first voltage shift capacitor C1 and second voltage shift capacitor C2.

[0048] FIG. 5 shows an example of the time waveform of the clock signal CK and the time waveform of the inverted clock signal CKB. The clock signal CK is a signal that alternates between high voltage VDD and low voltage 0. The inverted clock signal CKB has an inverted high / low relationship with respect to the clock signal CK. FIG. 6 shows an example of the time waveform of the offset clock signal CKo and the time waveform of the offset inverted clock signal CKBo. The DC component of the offset clock signal CKo is offset to the low voltage side with respect to the clock signal CK, and the DC component of the offset inverted clock signal CKBo is offset to the low voltage side with respect to the inverted clock signal CKB. In other words, the voltage of the offset clock signal CKo is lower than that of the clock signal CK by VDD-2Vt, and the voltage of the offset inverted clock signal CKBo is lower than that of the inverted clock signal CKB by VDD-2Vt.

[0049] The offset clock signal CKo is conducted to the gate of the NMOS switch S3 by a second clock path 44. The offset inverted clock signal CKBo is conducted to the gate of the NMOS switch S2 by a second inverted clock path 46.

[0050] Generally, a PMOS switch is turned on when the potential of its gate, which acts as a control terminal, is below a threshold, and turned off when it exceeds the threshold. An NMOS switch is turned on when the potential of its gate, which acts as a control terminal, is above a threshold, and turned off when it is below the threshold. However, the reference potential is the source potential.

[0051] When the level of the clock signal CK is low (0) and the level of the inverted clock signal CKB is high (VDD), the PMOS switch S4 and the NMOS switch S5 are turned on, and the NMOS switch S2 is also turned on. The NMOS switch S1 and the NMOS switch S3 are turned off. That is, when the level of the clock signal CK is low (0) and the level of the inverted clock signal CKB is high (VDD), the operation phase of the charge pump 102 is Φ B It becomes a phase.

[0052] When the clock signal CK is at a high level (VDD) and the inverted clock signal CKB is at a low level (0), the PMOS switch S4 and the NMOS switch S5 are turned off, and the NMOS switch S2 is also turned off. The NMOS switches S1 and the NMOS switch S3 are turned on. That is, when the clock signal CK is at a high level (VDD) and the inverted clock signal CKB is at a low level (0), the operation phase of the charge pump 102 is the Φ phase.

[0053] In this way, the control method of the charge pump 102 executed by the controller 28 includes alternately turning on and off the NMOS switch S1 as the first switch 11 and the NMOS switch S2 as the second switch 12, turning on and off the NMOS switch S3 as the third switch 13 together with the NMOS switch S1, and turning on and off the PMOS switch S4 as the fourth switch and the NMOS switch S5 as the fifth switch together with the NMOS switch S2.

[0054] The negative charge pump 54, the first voltage shift capacitor C1, and the second voltage shift capacitor C2 generate an offset clock signal CKo whose voltage is lower by VDD-2 Vt than the clock signal CK, and the offset clock signal CKo is guided to the gate of the NMOS switch S3 via the second clock path 44. Also, an offset inverted clock signal CKBo whose voltage is lower by VDD-2 Vt than the inverted clock signal CKB is generated, and the offset inverted clock signal CKBo is guided to the gate of the NMOS switch S2 via the second inverted clock path 46. This ensures that the NMOS switches S2 and S3 are switched on reliably even when the output voltage Vo is close to 0 or is a negative voltage.

[0055] 7 shows a push-pull driver 50 together with a portion of the error amplifier 26. The push-pull driver 50 is configured to approximately realize the characteristics of the current source 20 shown in FIG. 3. The error amplifier 26 includes a control terminal 60, a voltage shift power supply 62, and a voltage shift power supply 64. The voltage shift power supply 62 and the voltage shift power supply 64 each output a voltage V BP and V BN Output.

[0056] Control terminal 60 is connected to the control voltage V CTRL As will be described below, a control voltage is output as a control signal from the error amplifier 26 to the gate of the PMOS transistor S6 and the gate of the NMOS transistor S7. CTRLVoltage shift to the output voltage V of the power supply 62 BP The voltage V CTRL +V BP The gate of the NMOS transistor S7 is connected to the control voltage V CTRL Voltage shift from the output voltage of the power supply 64 V BN The voltage V CTRL -V BN will be output.

[0057] Such an error amplifier 26 may be configured by the technique described in Non-Patent Document 2 above.

[0058] The PMOS switch S4 and the NMOS switch S5 are turned on. B In the phase, a current I flows from the power supply line 52 to the PMOS transistor S6 and the PMOS switch S4. FP flows in, and a current I flows from the drain of the PMOS switch S4 to one end of the flying capacitor 22. FP Also, a current I flows from the ground conductor G to the NMOS transistor S7 and the NMOS switch S5. FN flows from the source of the NMOS switch S5 to one end of the flying capacitor 22. FN Therefore, Φ B In the charging phase, a charging current I flows from the push-pull driver 50 to the flying capacitor 22. F =I FP +I FN is playing.

[0059] 8 shows a circuit in which the voltage shift power supply 62 and the voltage shift power supply 64 in the error amplifier 26 shown in FIG. 7 are short-circuited. A common control voltage is output as a common control signal from the error amplifier 26 to the gate of the PMOS transistor S6 and the gate of the NMOS transistor S7. FIG. 9 shows a circuit in which the charging current I flowing from the push-pull driver 50 shown in FIG. 8 toward the flying capacitor 22 is short-circuited. F and the control voltage V CTRL The relationship between the control voltage V CTRL VMAX As the charging current I F decreases linearly, and the control voltage V CTRL is the intermediate voltage V M When the charging current I F is 0. The control voltage V CTRL is the intermediate voltage V M When the charging current I F is positive, and the flying capacitor 22 is charged. Meanwhile, the control voltage V CTRL is the intermediate voltage V M When the charging current exceeds F is negative and the flying capacitor 22 discharges.

[0060] Control voltage V CTRL is the intermediate voltage V M When the current I flows through the PMOS transistor S6 and the PMOS switch S4, FP and the current I flowing through the NMOS transistor S7 and the NMOS switch S5. FN is not 0. These currents may cause power loss. That is, even though no current flows through the flying capacitor 22, a current flows through the push-pull driver 50, causing power loss.

[0061] Therefore, the error amplifier 26 according to this embodiment may be provided with a voltage shift power supply 62 and a voltage shift power supply 64 as shown in Fig. 7. A control voltage V CTRL Voltage shift to the output voltage V of the power supply 62 BP The voltage V CTRL +V BP is output, and the gate of the NMOS transistor S7 is supplied with a control voltage V CTRL Voltage shift from the output voltage of the power supply 64 V BP The voltage V CTRL -V BP This results in a current I FP is the negative voltage V BP and the current I FN is a positive voltage V BM The control voltage V CTRLis the intermediate voltage V M When FP and the current I flowing through the NMOS transistor S7 and the NMOS switch S5. FN is close to 0, and the power Losses are reduced.

[0062] In the above example, a negative charge pump 54 is connected to the clock path 40 and the inverted clock path 42, and the second clock path 44 and the second inverted clock path 46 are connected to the negative charge pump 54. Instead of the negative charge pump 54, a voltage shift circuit 70 as shown in FIG. 11 may be connected to the clock path 40 and the inverted clock path, and the second clock path 44 and the second inverted clock path 46 may be connected to the voltage shift circuit 70. The voltage shift circuit 70 includes a first voltage shift capacitor C1, a second voltage shift capacitor C2, and third to sixth NMOS transistors Z3 to Z6. The voltage shift circuit 70 is also an auxiliary circuit that charges its own first voltage shift capacitor C1 and second voltage shift capacitor C2.

[0063] The drain of the third NMOS transistor Z3 is connected to the lower end of the first voltage shift capacitor C1. The source of the third NMOS transistor Z3 is connected to the drain of the fourth NMOS transistor Z4. The source of the fourth NMOS transistor Z4 is connected to the ground conductor G. The drain of the fifth NMOS transistor Z5 is connected to the lower end of the second voltage shift capacitor C2. The source of the fifth NMOS transistor Z5 is connected to the drain of the sixth NMOS transistor Z6. The source of the sixth NMOS transistor Z6 is connected to the ground conductor G. The gates of the third to sixth NMOS transistors Z3 to Z6 are connected to their respective drains.

[0064] The voltage shift circuit 70 maintains the voltage across each terminal of the first voltage shift capacitor C1 and the second voltage shift capacitor C2 at VDD-2Vt, where the lower end is a positive voltage relative to the upper end. Therefore, when the clock signal CK and the inverted clock signal CKB shown in FIG. 5 are supplied to the clock path 40 and the inverted clock path 42, respectively, the offset clock signal CKo and the offset inverted clock signal CKBo shown in FIG. 6 are supplied to the second clock path 44 and the second inverted clock path 46, respectively.

[0065] The charge pump 102 according to this embodiment uses a push-pull driver 50 that charges or discharges the flying capacitor 22. The charging voltage V F can be either a positive or negative voltage. Therefore, when the output voltage Vo is higher than the target voltage V TARGET Whether the output voltage Vo is greater than or less than the target voltage V TARGET The output voltage Vo can be either a positive or negative voltage, which allows for proper control of the image sensor.

[0066] 12 shows the configuration of a charge pump system 400 according to a first application embodiment of the present disclosure. The charge pump system 400 includes an error amplifier 26 and a charge pump unit 200. The charge pump unit 200 includes a first charge pump 110 and a second charge pump 112. The first charge pump 110 and the second charge pump 112 have the same configuration as the charge pump 102 shown in FIG. 4. The output terminal 24 of the first charge pump 110 and the output terminal 24 of the second charge pump 112 are commonly connected.

[0067] A common clock signal CK and an inverted clock signal CKB are input to the first charge pump 110 and the second charge pump 112. The error amplifier 26 performs common control over the first charge pump 110 and the second charge pump 112. That is, the target voltage V TARGET The control voltage V that reduces the difference between the output voltage Vo and the CTRLP and V CTRLN to the first charge pump 110 and the second charge pump 112.

[0068] The control voltage V that the error amplifier 26 outputs to the first charge pump 110 and the second charge pump 112 CTRLP and V CTRLN The output voltage Vo is set to the target voltage V TARGET Approaching or matching.

[0069] 13 shows the configuration of a charge pump system 402 according to a second application embodiment of the present disclosure. The charge pump system 402 includes an error amplifier 26, a first charge pump unit 201, and a second charge pump unit 202. The first charge pump unit 201 and the second charge pump unit 202 have the same configuration as the charge pump unit 200 shown in Fig. 12. The output terminal 24 of the first charge pump unit 201 and the output terminal 24 of the second charge pump unit 202 are commonly connected.

[0070] The first charge pump unit 201 receives a clock signal CK and an inverted clock signal CKB. The second charge pump unit 202 receives a clock signal CK90° and a clock signal CK270° instead of the clock signal CK and the inverted clock signal CKB. The clock signal CK90° is a signal whose phase is delayed by 90° from the clock signal CK. The clock signal CK270° is a signal whose phase is delayed by 90° from the inverted clock signal CKB. The clock signal CK90° may be a signal whose phase is advanced by 90° from the clock signal CK, in which case the clock signal CK270° is a signal whose phase is advanced by 90° from the inverted clock signal CKB.

[0071] The error amplifier 26 performs common control on the first charge pump unit 201 and the second charge pump unit 202. That is, the target voltage V TARGET The control voltage V that reduces the difference between the output voltage Vo and the CTRLP and V CTRLN to the first charge pump unit 201 and the second charge pump unit 202.

[0072] The control voltage V output from the error amplifier 26 to the first charge pump unit 201 and the second charge pump unit 202 CTRLP and V CTRLN The output voltage Vo is set to the target voltage V TARGET Approaching or matching.

[0073] As described above, the charge pump system 400 according to the first application embodiment of the present disclosure and the charge pump system 402 according to the second application embodiment include a plurality of charge pumps 102 with the output terminals 24 commonly connected. A clock signal CK and an inverted clock signal CKB for controlling the switches included in each of the plurality of charge pumps 102 are input to each of the plurality of charge pumps 102. As can be seen in the charge pump system 402 according to the second application embodiment, the phases of the clock signal CK and the inverted clock signal CKB may be different for each of the plurality of charge pumps 102. By making the phases of the clock signal CK and the inverted clock signal CKB different for each of the plurality of charge pumps 102, the output voltage Vo can be adjusted to the target voltage V TARGET This ensures that the output voltage Vo is closer to the target voltage V TARGET Approaching or matching.

[0074] FIG. 14 shows a PN substitution charge pump 500 according to a modification of the present disclosure. The PN substitution charge pump 500 outputs a voltage higher than the power supply voltage VDD. In the PN substitution charge pump 500, the PMOS switches in the charge pump 102 shown in FIG. 4, which outputs a voltage lower than the voltage of the ground conductor G, are replaced with NMOS switches, and the NMOS switches in the charge pump 102 are replaced with PMOS switches. Furthermore, the PMOS transistors in the charge pump 102 are replaced with NMOS transistors, and the NMOS transistors in the charge pump 102 are replaced with PMOS transistors. Furthermore, the power supply line 52 in the charge pump 102 is replaced with the ground conductor G, and the ground conductor G is used as a second reference conductor. Furthermore, the ground conductor G in the charge pump 102 is replaced with the power supply line 52, and the power supply line 52 is used as a first reference conductor. In addition, the clock signal CK in the charge pump 102 is replaced with an inverted clock signal CKB, and the inverted clock signal CKB in the charge pump 102 is replaced with the clock signal CK. As a result, the offset clock signal CKo in the charge pump 102 is replaced with the offset inverted clock signal CKBo, and the offset inverted clock signal CKBo in the charge pump 102 is replaced with the offset clock signal CKo. CTRLP and V CTRLN and the control voltage V CTRLN and V CTRLP has been replaced by

[0075] Specifically, the NMOS switches S1 to S3 and S5 in the charge pump 102 are replaced with PMOS switches s1 to s3 and s5, respectively, in the PN replacement charge pump 500. The PMOS switch S4 in the charge pump 102 is replaced with an NMOS switch s4 in the PN replacement charge pump 500. The PMOS transistor S6 and NMOS transistor S7 in the charge pump 102 are replaced with an NMOS transistor s6 and a PMOS transistor s7, respectively, in the PN replacement charge pump 500. The negative charge pump 54 in the charge pump 102 is replaced with a negative charge pump 54A in the PN replacement charge pump 500. That is, the first PMOS switch W1 and the second PMOS switch W2 in the negative charge pump 54 are replaced with a first NMOS switch w1 and a second NMOS switch w2, respectively, in the negative charge pump 54A. The first NMOS transistor Z1 and the second NMOS transistor Z2 in the negative charge pump 54 are replaced by a first PMOS transistor z1 and a second PMOS transistor z2, respectively, in the negative charge pump 54A.

[0076] The voltage shift circuit 70 (FIG. 11) used in place of the negative charge pump 54 in the charge pump 102 is replaced with a voltage shift circuit 70A shown in FIG. 15. That is, the third NMOS transistor Z3 to the sixth NMOS transistor Z6 in the voltage shift circuit 70 are replaced with the third PMOS transistor z3 to the sixth PMOS transistor z6, respectively, in the voltage shift circuit 70A.

[0077] PN substitution charge pump 500 is a configuration in which the semiconductor elements using electrons as carriers are replaced with semiconductor elements using holes as carriers, and the semiconductor elements using holes as carriers are replaced with semiconductor elements using electrons as carriers, in charge pump 102. Therefore, PN substitution charge pump 500 operates in the same manner as charge pump 102. [Explanation of symbols]

[0078] 10 driver switch, 11 first switch, 12 second switch, 13 third switch, 20 current source, 22 flying capacitor, 24 output terminal, 26 error amplifier, 28 controller, 30 load circuit, 32 load capacitor, 34 load current source, 36 one end of flying capacitor, 38 other end of flying capacitor, 40 clock path, 42 inverted clock path, 44 second clock path, 46 second inverted clock path, 50 push-pull driver, 52 power supply line, 54, 54A negative charge pump, 60 control terminal, 62, 64 voltage shift power supply, 70, 70A voltage shift circuit, 100, 102 charge pump, 110 first charge pump, 112 second charge pump, 200 charge pump unit, 201 first charge pump unit, 202 second charge pump unit, 400, 402 charge pump system, 500 PN substitution type charge pump, C1 first voltage shift capacitor, C2 second voltage shift capacitor, S1, S2, S3, S5 NMOS switches, S4 PMOS switch, W1 first PMOS switch, W2 second PMOS switch, S6 PMOS transistor, S7 NMOS transistor, Z3 to Z6 third to sixth NMOS transistors, s1, s2, s3, s5 PMOS switches, s4 NMOS switch, w1 first NMOS switch, w2 second NMOS switch, s6 NMOS transistor, s7 PMOS transistor, z3 to z6 third to sixth PMOS transistors.

Claims

1. Flying capacitors, a push-pull driver provided at one end of the flying capacitor; a first switch provided between one end of the flying capacitor and a first reference conductor; a second switch provided between the other end of the flying capacitor and the first reference conductor; a third switch provided between the other end of the flying capacitor and an output terminal, The push-pull driver a fourth switch and a fifth switch, each having one end connected to one end of the flying capacitor; the other end of the fourth switch is connected to a second reference conductor separate from the first reference conductor, and the other end of the fifth switch is connected to the first reference conductor.

2. 2. The charge pump of claim 1, a controller configured to control the push-pull driver, the first switch, the second switch, and the third switch; The controller The first switch and the second switch are alternately turned on and off, turning on and off the third switch together with the first switch; The charge pump is configured to turn the fourth switch and the fifth switch on and off together with the second switch.

3. 2. The charge pump of claim 1, The push-pull driver a first current regulating device provided at the other end of the fourth switch; a second current regulating device provided at the other end of the fifth switch; The first current regulating device and the second current regulating device are configured to regulate a current through the flying capacitor.

4. 4. The charge pump of claim 3, outputting a common control signal to the first current regulating device and the second current regulating device according to a difference between an output voltage at the output terminal and a target voltage; a charge pump comprising an error amplifier configured to regulate a current through the first current regulating device and the fourth switch and a current through the second current regulating device and the fifth switch;

5. 4. The charge pump of claim 3, outputting a control signal to each of the first current regulating device and the second current regulating device in accordance with a difference between an output voltage at the output terminal and a target voltage; a charge pump comprising an error amplifier configured to regulate a current through the first current regulating device and the fourth switch and a current through the second current regulating device and the fifth switch;

6. 2. The charge pump of claim 1, a clock path that guides a clock signal to a control terminal of the fourth switch; an inverted clock path that guides an inverted clock signal, which has a high and low inverted relationship with respect to the clock signal, to a control terminal of the fifth switch; a second clock path coupled to the clock path via a first voltage shift capacitor; a second inverting clock path connected to the inverting clock path via a second voltage shift capacitor; an offset clock signal having a DC component offset from the clock signal is guided to a control terminal of the third switch by the second clock path; an offset inverted clock signal having a DC component offset from the inverted clock signal is guided to the control terminal of the second switch by the second inverted clock path;

7. 7. A charge pump according to claim 6, a sub-circuit including the first voltage shift capacitor and the second voltage shift capacitor, the sub-circuit having the second clock path and the second inverted clock path connected thereto; The auxiliary circuit includes: A charge pump charges the first voltage shift capacitor and the second voltage shift capacitor.

8. 2. The charge pump of claim 1, the first switch, the second switch, the third switch, and the fifth switch are NMOS switches; The fourth switch is a PMOS switch.

9. 9. A charge pump according to claim 8, the first reference conductor is a ground conductor; The second reference conductor is a power supply line.

10. 2. The charge pump of claim 1, the first switch, the second switch, the third switch, and the fifth switch are PMOS switches; The fourth switch is an NMOS switch.

11. 11. A charge pump according to claim 10, the first reference conductor is a power supply line, The second reference conductor is a ground conductor.

12. 1. A charge pump system comprising: A plurality of charge pumps are provided, Each of the plurality of charge pumps Flying capacitors, a push-pull driver provided at one end of the flying capacitor; a first switch provided between one end of the flying capacitor and a first reference conductor; a second switch provided between the other end of the flying capacitor and the first reference conductor; a third switch provided between the other end of the flying capacitor and an output terminal, The push-pull driver a fourth switch and a fifth switch, each having one end connected to one end of the flying capacitor; the other end of the fourth switch is connected to a second reference conductor different from the first reference conductor, and the other end of the fifth switch is connected to the first reference conductor; the output terminals of the plurality of charge pumps are commonly connected; a clock signal for controlling the first switch to the fifth switch included in each of the plurality of charge pumps is input to each of the plurality of charge pumps; A charge pump system, wherein the phase of the clock signal differs for each of the plurality of charge pumps.

13. 1. A method for controlling a charge pump, comprising: The charge pump Flying capacitors, a push-pull driver provided at one end of the flying capacitor; a first switch provided between one end of the flying capacitor and a first reference conductor; a second switch provided between the other end of the flying capacitor and the first reference conductor; a third switch provided between the other end of the flying capacitor and an output terminal, The push-pull driver a fourth switch and a fifth switch, each having one end connected to one end of the flying capacitor; the other end of the fourth switch is connected to a second reference conductor different from the first reference conductor, and the other end of the fifth switch is connected to the first reference conductor; The control method includes: The first switch and the second switch are alternately turned on and off, turning on and off the third switch together with the first switch; A control method including turning the fourth switch and the fifth switch on and off together with the second switch.

14. 14. The control method according to claim 13, The push-pull driver a first current regulating device provided at the other end of the fourth switch; a second current regulating device provided at the other end of the fifth switch; The control method includes: The control method includes causing the first current regulating device and the second current regulating device to regulate a current through the flying capacitor.

15. 15. The control method of claim 14, outputting a common control signal to the first current regulating device and the second current regulating device according to a difference between an output voltage at the output terminal and a target voltage; A control method comprising regulating a current through the first current regulating device and the fourth switch and a current through the second current regulating device and the fifth switch.

16. 15. The control method of claim 14, outputting a control signal to each of the first current regulating device and the second current regulating device in accordance with a difference between an output voltage at the output terminal and a target voltage; A control method comprising regulating a current through the first current regulating device and the fourth switch and a current through the second current regulating device and the fifth switch.

17. 14. The control method according to claim 13, a clock path that guides a clock signal to a control terminal of the fourth switch; an inverted clock path that guides an inverted clock signal, which has a high and low inverted relationship with respect to the clock signal, to a control terminal of the fifth switch; a second clock path coupled to the clock path via a first voltage shift capacitor; a second inverting clock path connected to the inverting clock path via a second voltage shift capacitor; an offset clock signal having a DC component offset from the clock signal is guided to a control terminal of the third switch via the second clock path; a control method including guiding an offset inverted clock signal, the DC component of which is offset relative to the inverted clock signal, to a control terminal of the second switch via the second inverted clock path.

18. 18. The control method of claim 17, a control method including connecting an auxiliary circuit including the first voltage shift capacitor and the second voltage shift capacitor to the second clock path and the second inverted clock path, and causing the auxiliary circuit to charge its own first voltage shift capacitor and second voltage shift capacitor.

19. 14. The control method according to claim 13, the first switch, the second switch, the third switch, and the fifth switch are NMOS switches; The fourth switch is a PMOS switch.

20. 14. The control method according to claim 13, the first switch, the second switch, the third switch, and the fifth switch are PMOS switches; The fourth switch is an NMOS switch.

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