Control device, system, method, and program

Abstract

To provide a control device, a system, a method and a program that do not place a load on a CPU for error processing.SOLUTION: In a system having a central processing unit (CPU), a main memory, a memory mirror unit, a management controller, an active accelerator, and a standby accelerator, the management controller 40, which is a control device, includes a reception unit that receives information indicating status of an active accelerator that processes data, and an instruction unit that instructs, when the information indicates an abnormality, a standby accelerator to process data, and that is connected between the CPU and a plurality of accelerators including an active accelerator and a standby accelerator, and selects, when the information indicates an abnormality, a standby accelerator from available accelerators.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to a control device, a system, a method, and a program for managing an accelerator. [Background technology]

[0002] A related technology is known in which an accelerator is added to an information processing device, distributing part of the processing that would normally be performed by a processor to the accelerator. For example, there is a technology in which a GPU (Graphics Processing Unit) is added as an accelerator to a server with a processor, and the GPU processes part of the program processing that the processor would execute, thereby improving processing speed.

[0003] If a fault occurs in an accelerator during processing, it takes time and manpower to retry, so there has been a demand for reducing this time and labor.For example, Patent Document 1 describes a technology in which, when a fault occurs in an FPGA (Field Programmable Gate Array), the FPGA notifies a host processor, and the host processor instructs another FPGA to carry out the processing. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] International Publication No. 2016 / 135875 Summary of the Invention [Problem to be solved by the invention]

[0005] The technology described in Patent Document 1 requires the CPU itself to manage the FPGA and to have a retry mechanism, which places a load on the CPU for error processing.

[0006] An object of the present disclosure is to provide a control device, a system, a method, and a program that solve the above-mentioned problems. [Means for solving the problem]

[0007] A control device according to an embodiment of the present disclosure is configured to receive information indicating a status of a first accelerator that processes data, and, if the information indicates an abnormality, instruct a second accelerator to process the data.

[0008] A system according to one embodiment of the present disclosure includes a central processing unit, a main memory, a memory mirror unit, a plurality of accelerators including a first accelerator and a second accelerator, and the above-described control device, wherein the memory mirror unit is configured to copy data to another predetermined address when the central processing unit copies data from the main memory to the memory of the first accelerator, and the first accelerator is configured to transmit information indicating a state of the first accelerator processing data to the control device.

[0009] In one embodiment of the present disclosure, a control device that manages accelerators receives information indicating the status of a first accelerator that processes data, and if the information indicates an abnormality, instructs a second accelerator to process the data.

[0010] A program according to an embodiment of the present disclosure causes a computer to receive information indicating a status of a first accelerator that processes data, and, if the information indicates an abnormality, causes the computer to instruct a second accelerator to process the data. [Effects of the Invention]

[0011] In the present invention, an error in the active accelerator is notified to the management controller, which then automatically retries the operation using the standby accelerator, so no CPU load is required for error processing. [Brief explanation of the drawings]

[0012] [Figure 1] 1 is a schematic diagram of a system 100 according to the present disclosure. [Figure 2] FIG. 1 is a diagram of a control device according to the present disclosure. [Figure 3] FIG. 1 is a diagram illustrating a processing flow of a related technique. [Figure 4] FIG. 2 is a diagram showing the first half of the processing flow of the system 100 according to the present disclosure. [Figure 5] FIG. 10 is a diagram showing the second half of the processing flow of the system 100 according to the present disclosure. [Figure 6] 10 is a processing flow of a memory mirror unit 30 according to the present disclosure. [Figure 7] 1 is a schematic diagram of a system 200 according to the present disclosure. [Figure 8] FIG. 2 is a diagram showing the first half of a processing flow of a system 200 according to the present disclosure. [Figure 9] FIG. 10 is a diagram showing the second half of the processing flow of the system 200 according to the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0013] Each embodiment will be described below with reference to the drawings. In all drawings, the same or corresponding components are designated by the same reference numerals, and common descriptions will be omitted.

[0014] First Embodiment Hereinafter, an embodiment according to the present disclosure will be described with reference to the drawings.

[0015] In this embodiment, processing data (including commands and data) sent from the CPU to the active accelerator is sent to both the active accelerator and the management controller via the memory mirror unit. The management controller, which manages the accelerators, then holds the processing data for the active accelerator. If an abnormality occurs in the active accelerator, the management controller sends the held processing data to the standby accelerator and causes the processing to be re-executed without CPU intervention.

[0016] FIG. 1 is a schematic diagram of a system 100 according to the present disclosure. The system 100 includes a CPU (Central Processing Unit) 10, a main memory 20, a memory mirror unit 30, a management controller 40, an active accelerator 50, and a standby accelerator 60. These are some of the components of a computer. Generally, a computer may include various other components, such as a disk drive and a network interface, but these components are not shown in FIG. 1 . The active accelerator 50 is an accelerator that is active at the beginning of the processing flow described below, and the standby accelerator 60 is an accelerator that is on standby at the beginning of the processing flow described below. If an abnormality occurs during the processing flow, the standby accelerator 60 starts processing upon receiving an instruction from the CPU 10. However, even after processing has started, the standby accelerator 60 will be referred to as the standby accelerator 60.

[0017] The CPU 10 controls the components of the system 100. Depending on the processing content, the CPU 10 instructs the execution unit 52 of the active accelerator 50 to execute a program 54.

[0018] The memory mirror unit 30 has a duplication unit 31 and a setting 32. The memory mirror unit 30 is, for example, a memory controller with a mirror function. The duplication unit 31 has a function of copying data at a target address to another address designated in advance when copying data at the target address to a destination address. The other address designated in advance is set in the setting 32 as the mirror destination.

[0019] The management controller 40 includes a memory 41, an execution unit 42, and settings 43. The management controller 40 corresponds to, for example, a BMC (Baseboard Management Controller). The BMC is a control device, such as a control chip, for managing a computer, for example, by monitoring or controlling the status of computer components including a CPU. The BMC may have the functions of the management controller 40, or the management controller 40 may be a dedicated device. The execution unit 42 executes a program 44 stored in the memory 41, and instructs the execution unit 62 of the standby accelerator 60 to execute the program if an abnormality occurs in the active accelerator 50 that processes data. The settings 43 contain information related to the operation of the management controller 40, such as the procedure to be followed when an abnormality notification is received from the active accelerator 50.

[0020] In FIG. 1, the management controller 40 has a memory 41, an execution unit 42, and a setting 43. However, as shown in FIG. 2, the management controller 40 may be a control device that includes a receiving unit that receives information indicating the status of a first accelerator that processes data, and an instruction unit that instructs a second accelerator to process data when the information indicates an abnormality.

[0021] The active accelerator 50 and the standby accelerator 60 are devices for offloading processing that was previously performed by the CPU 10 in order to reduce the load on the CPU 10 or improve the performance of the system 100. Accelerators are dedicated hardware designed for specific processing, such as accelerators for AI (artificial intelligence) and accelerators for image processing (graphics processing units (GPUs)). The active accelerator 50 has a memory 51, an execution unit 52, and a setting 53, and executes processing according to instructions from the CPU 10. The standby accelerator 60 has a memory 61, an execution unit 62, and a setting 63, and executes processing according to instructions from the management controller 40. The execution units 52 and 62 execute programs 54 and 64 stored in the memories 51 and 61, respectively, and notify the CPU 10 or the management controller 40 of the completion of processing according to the setting when processing is completed, or notify the CPU 10 or the management controller 40 of the occurrence of an abnormality according to the setting when an abnormality occurs. The settings 53 and 63 contain information relating to the operation of the active accelerator 50 and the standby accelerator 60, such as the normal notification destination, normal procedure, abnormal notification destination, and abnormal procedure, respectively.

[0022] The active accelerator 50 receives data to be processed from the CPU 10, processes the data, and returns it to the CPU 10. The program 54 for performing the processing may be received as data from the CPU 10, loaded into the memory 51 in the active accelerator 50, and processed as the program 54, or the program 54 may be pre-installed in the memory 51. The same applies when the standby accelerator 60 operates in response to an instruction to perform processing.

[0023] Normally, the active accelerator 50 operates. The standby accelerator 60 stands by as a backup and operates when the active accelerator 50 fails. The standby accelerator 60 may be composed of multiple accelerators. The active and standby systems refer to a relationship when focusing on a certain process. For process A, the accelerator 50 may be the active system and the accelerator 60 may be the standby system, and for process B, the accelerator 60 may be the active system and the accelerator 50 may be the standby system. Of course, for all processes, the accelerator 50 may be the active system and the accelerator 60 may be the standby system.

[0024] Before describing the operation of the system 100 shown in Fig. 1, the processing flow of the related technology will be described with reference to Fig. 3. Fig. 3 shows the processing flow when offloading processing to an accelerator.

[0025] In addition to the CPU 310 and accelerator 320 shown in FIG. 3, the system 300 also includes a main memory, an execution unit of the accelerator 320, a memory, and the like, although a block diagram thereof is omitted.

[0026] First, in step S301, CPU 310 copies processing data (including commands and data) from main memory to the memory of accelerator 320, and instructs accelerator 320 to perform processing in step S302. In step S303, accelerator 320 processes the data upon receiving the instruction. When accelerator 320 successfully completes data processing, in step S304, accelerator 320 notifies CPU 310 of the completion of processing. In step S305, CPU 310 receives the notification and copies the calculation results from the memory of accelerator 320 to main memory. "Normal" here means that no hardware failure occurred during processing, and does not mean that an unintended operation result was caused by a software bug or that the expected calculation result was not obtained.

[0027] On the other hand, if a failure occurs during processing in accelerator 320, the processing is immediately interrupted, and in step S306, accelerator 320 notifies CPU 310 of the occurrence of the abnormality as an interrupt process. Upon receiving the abnormality notification, CPU 310 performs abnormality processing in step S307, but in order to re-execute the processing, it was necessary to manually re-specify another accelerator or modify the software (SW) and re-execute the processing on another accelerator. This is the problem with the technology shown in Figure 3.

[0028] An embodiment of the present disclosure will be described below with reference to Fig. 4 and Fig. 5. Fig. 4 and Fig. 5 show the processing flow of system 100 described with reference to Fig. 1, with Fig. 4 showing the first half of the processing flow and Fig. 5 showing the second half of the processing flow. Fig. 4 and Fig. 5 show an embodiment in which there is one standby accelerator, and standby accelerator 60 directly notifies CPU 10 of processing completion or the occurrence of an abnormality.

[0029] 4, the CPU 10 copies processing data (including commands and data) from the main memory 20 to the memory 51 of the active accelerator 50. At this time, the processing data is also copied to the memory 41 of the management controller 40 by the memory mirror unit 30; that is, the processing data is copied to both the memory 51 of the active accelerator 50 and the memory 41 of the management controller 40. In FIG. 1, this is indicated by an input from the main memory 20 to the duplex unit 31 of the memory mirror unit 30, an output 1 from the duplex unit 31 to the memory 51 of the active accelerator 50, and an output 2 from the duplex unit 31 to the memory 41 of the management controller 40. Details will be described later with reference to FIG. 6.

[0030] In step S102, the CPU 10 instructs the active accelerator 50 to perform processing.

[0031] In step S103, the active accelerator 50 that received the instruction processes the data. When the data processing is completed normally, in step S104, the active accelerator 50 notifies the CPU 10 of the completion of processing. The notification may be sent via the management controller 40. Upon receiving the notification, in step S105, the CPU 10 copies the calculation results from the memory 51 of the active accelerator 50 to the main memory 20. Here, "normal" means that no hardware failure occurred during processing, and does not mean that an unintended operation result was caused by a software bug or that the expected calculation result was not obtained.

[0032] On the other hand, if a failure occurs during processing in step S103, the processing is immediately interrupted, and in step S106, the active accelerator 50 notifies the management controller 40 of the occurrence of the abnormality as an interrupt process. Here, the same processing data that was copied from the main memory 20 to the memory 51 of the active accelerator 50 as described above in step S101 has been copied to the memory 41 of the management controller 40. Upon receiving the notification of the occurrence of the abnormality, in step S107, the management controller 40 copies the processing data from the memory 41 of the management controller 40 to the memory 61 of the standby accelerator 60, and in step S108 instructs the standby accelerator 60 to perform processing.

[0033] Next, the rest of the processing flow will be explained with reference to Figure 5. The standby accelerator 60 that received the instruction processes the data in step S109. When the data processing is completed normally, the standby accelerator 60 notifies the CPU 10 of the completion of processing in step S110. This notification may be sent via the management controller 40. Upon receiving this notification, the CPU 10 copies the calculation results from the memory 61 of the standby accelerator 60 to the main memory 20 in step S111. "Normal" here means that no hardware failure occurred during processing, and does not mean that an unintended operation result was caused by a software bug or that the expected calculation result was not obtained.

[0034] On the other hand, if a failure occurs during processing in step S109, the processing is immediately interrupted, and in step S112, the standby accelerator 60 notifies the CPU 10 of the occurrence of the abnormality as an interrupt process. This notification may be sent via the management controller 40. Upon receiving this notification, in step S113, the CPU 10 performs abnormality processing. In this case, after an abnormality occurs in the active accelerator 50, an abnormality also occurs in the standby accelerator 60. Since there is only one standby accelerator, the processing cannot be re-executed even manually.

[0035] Here, referring to FIG. 6, the processing flow of the memory mirror unit 30 related to step S101 in FIG. 4 mentioned above will be described. The memory mirror unit 30 is preset so that when the CPU 10 writes certain data to the address space AAAA-BBBB, the same data is also written to another address space aaaa-bbbb. In step S1, when the memory mirror unit 30 receives an input to write data A to address 1 within the address space AAAA-BBBB, in step S3, data A is output from output 1 to address 1, and in step S2, a signal representing data A for output 2 is generated. In step S4, the output destination is switched to address 2 corresponding to address 1, and in step S5, data A is output from output 2 to address 2. Output 1 and output 2 may share the same path or may use different paths.

[0036] Second Embodiment Next, an embodiment according to the present disclosure will be described with reference to Fig. 7 to Fig. 9. Fig. 7 is a schematic diagram of a system 200 according to the present disclosure. Fig. 8 and Fig. 9 show a processing flow of the system 200 according to the present disclosure, with Fig. 8 showing the first half of the processing flow and Fig. 9 showing the second half of the processing flow.

[0037] Fig. 7 is a schematic diagram of a system 200 according to the present disclosure. The system 100 in Fig. 4 has one standby accelerator, and the standby accelerator 60 directly notifies the CPU 10 of processing completion or the occurrence of an abnormality. However, the system 200 in Fig. 7 has multiple standby accelerators (it can be just one) (for example, three standby accelerators 60, 70, and 80), and the management controller 40 relays notifications of accelerator processing completion or the occurrence of an abnormality to the CPU 10. The memory mirror unit 30 is the same as in the first embodiment.

[0038] Steps S201, S202, and S203 in Fig. 8 are the same as steps S101, S102, and S103 in Fig. 4. That is, in step S201, the CPU 10 copies processing data from the main memory 20 to the memory 51 of the active accelerator 50. At this time, the processing data is also copied to the memory 41 of the management controller 40 by the memory mirror unit 30; that is, the processing data is copied to both the memory 51 of the active accelerator 50 and the memory 41 of the management controller 40. In step S202, the CPU 10 instructs the active accelerator 50 to perform processing. In step S203, the active accelerator 50 that has received the instruction processes the data.

[0039] When data processing is completed normally, the active accelerator 50 notifies the management controller 40 of the completion of processing in step S204. In step S205 (FIG. 9), the management controller 40 accepts the completion of processing and notifies the CPU 10 of the completion of processing in step S206. In step S207, the CPU 10 copies the calculation results from the memory 51 of the active accelerator 50 to the main memory 20. "Normal" here means that no hardware failure occurred during processing, and does not mean that an unintended operation result was caused by a software bug or that the expected calculation result was not obtained.

[0040] On the other hand, if a failure occurs during processing in step S203 of FIG. 8, the processing is immediately interrupted, and in step S208, the active accelerator 50 notifies the management controller 40 of the occurrence of the abnormality as an interrupt process. Here, the same processing data as that copied from the main memory 20 to the memory 51 of the active accelerator 50 as described above in step S201 is copied to the memory 41 of the management controller 40. Upon receiving the above notification of the occurrence of the abnormality, the management controller 40 accepts the occurrence of the abnormality in step S209 (FIG. 9). In step S210, the management controller 40 determines whether there is a spare standby accelerator, i.e., whether there is a usable standby accelerator. If there is not, in step S214, the management controller 40 notifies the CPU 10 of the occurrence of the abnormality, and in step S215, the CPU 10 performs abnormality processing.

[0041] On the other hand, if there is an available standby accelerator in step S210, then in step S211 the management controller 40 selects the standby accelerator to instruct the processing (standby accelerator 60 in FIG. 9). If there is only one available standby accelerator, the processing is instructed to that standby accelerator. In step S212, the management controller 40 copies the processing data from the memory 41 of the management controller 40 to the memory of the standby accelerator selected in step S211 (memory 61 of the standby accelerator 60 in FIG. 9). In step S213, the management controller 40 instructs the standby accelerator selected in step S211 to perform the processing. The operation of the standby accelerator that receives the instruction is the same as steps S203, S204, and S208 of the active accelerator 50 described above. That is, the standby accelerator that receives the instruction executes the operation of the active accelerator 50 shown in Figures 8 and 9, thereby executing the operations from step S203 onwards. Even if an abnormality occurs in the standby accelerator that executes the operation of the active accelerator 50, as long as there is a spare standby accelerator in step S210, it is possible to select the standby accelerator in step S211 and instruct the standby accelerator to perform processing in step S213. That is, unless an abnormality occurs in all of the multiple spare standby accelerators, the CPU 10 is not notified of the occurrence of the abnormality, thereby providing high availability.

[0042] The present disclosure is applicable to systems that require high availability of accelerators.

[0043] Although the present disclosure has been described above with reference to the embodiments, the present disclosure is not limited to the above-described embodiments. Various modifications that can be understood by those skilled in the art can be made to the configuration and details of the present disclosure within the scope of the present disclosure. Furthermore, each embodiment can be combined with other embodiments as appropriate.

[0044] Some or all of the above-described embodiments can be described as, but are not limited to, the following supplementary notes.

[0045] (Appendix 1) a control device configured to receive information indicating a state of a first accelerator that processes data, and to instruct a second accelerator to process the data when the information indicates an abnormality;

[0046] (Appendix 2) 2. The control device of claim 1, wherein the control device is connected between a central processing unit and a plurality of accelerators including the first accelerator and the second accelerator.

[0047] (Appendix 3) 3. The control device according to claim 1, wherein instructing the second accelerator to process the data includes copying the processed data used for processing by the first accelerator to a memory of the second accelerator.

[0048] (Appendix 4) The control device includes a memory; 4. The control device of claim 1, further configured to store, in a memory of the control device, processing data used for processing by the first accelerator.

[0049] (Appendix 5) 5. The control device of any one of appendixes 1 to 4, further configured to select the second accelerator from available accelerators if the information indicates an abnormality.

[0050] (Appendix 6) 6. The control device of any one of claims 1 to 5, further configured to receive information indicative of a state of the second accelerator.

[0051] (Appendix 7) A system including a central processing unit, a main memory, a memory mirror unit, a plurality of accelerators including a first accelerator and a second accelerator, and a control device according to any one of appendices 1 to 6, the memory mirror unit is configured to copy data to another preset address when the central processing unit copies data from the main memory to the memory of the first accelerator; The system is configured such that the first accelerator transmits information to the controller indicative of a state of the first accelerator processing the data.

[0052] (Appendix 8) 8. The system of claim 7, wherein the predetermined separate address is an address in a memory of the control device.

[0053] (Appendix 9) A method comprising the steps of: a control device that manages accelerators receiving information indicating the status of a first accelerator that processes data; and, if the information indicates an abnormality, instructing a second accelerator to process the data.

[0054] (Appendix 10) 10. The method of claim 9, wherein the control device is connected between a central processing unit and a plurality of accelerators, including the first accelerator and the second accelerator.

[0055] (Appendix 11) 11. The method of claim 9, wherein instructing a second accelerator to process the data includes copying processed data used for processing by the first accelerator to a memory of the second accelerator.

[0056] (Appendix 12) 12. The method of any one of claims 9 to 11, further comprising the step of the control device storing, in a memory of the control device, processed data used for processing by the first accelerator.

[0057] (Appendix 13) 13. The method of any one of claims 9 to 12, further comprising the step of the controller selecting the second accelerator from available accelerators if the information indicates an anomaly.

[0058] (Appendix 14) 14. The method of any one of claims 9 to 13, further comprising the controller receiving information indicating a state of the second accelerator.

[0059] (Appendix 15) When the central processing unit copies data from the main memory to the memory of the first accelerator, the memory mirror unit also copies the data to another address set in advance; 15. The method of any one of claims 9 to 14, further comprising: the first accelerator sending information to the control device indicating a status of the first accelerator processing the data.

[0060] (Appendix 16) 16. The method of claim 15, wherein the predetermined separate address is an address in a memory of the control device.

[0061] (Appendix 17) a program for causing an execution unit of a control device to execute a step of receiving information indicating the status of a first accelerator that processes data, and instructing a second accelerator to process the data if the information indicates an abnormality;

[0062] (Appendix 18) 18. The program of claim 17, wherein the control device is connected between a central processing unit and a plurality of accelerators including the first accelerator and the second accelerator.

[0063] (Appendix 19) 19. The program of claim 17, wherein instructing the second accelerator to process the data includes copying the processed data used for processing by the first accelerator to a memory of the second accelerator.

[0064] (Appendix 20) 20. The program of claim 17, for causing an execution unit of the control device to execute a step of storing processing data used for processing by the first accelerator in a memory of the control device.

[0065] (Appendix 21) 21. The program of claim 17, further causing an execution unit of the control device to execute a step of selecting the second accelerator from available accelerators when the information indicates an abnormality.

[0066] (Appendix 22) 22. The program according to any one of appendices 17 to 21, for causing an execution unit of the control device to further execute a step of receiving information indicating a state of the second accelerator.

[0067] (Appendix 23) 23. The program of claim 17, for causing an execution unit of the first accelerator to execute a step of transmitting information indicating a state of the first accelerator that processes the data to the control device. [Explanation of symbols]

[0068] 10 CPU 20 Main Memory 21 Data 30 Memory mirror section 31 Duplex section 32 Settings 40 Management Controller 41, 51, 61 memory 42, 52, 62 Executive Department 43, 53, 63 settings 44, 54, 64 programs 45 Receiving unit 46 Instruction section 50 Production Accelerators 60, 70, 80 Standby accelerator 100, 200, 300 systems 310 CPU 320 Accelerator

Claims

1. a control device configured to receive information indicating a state of a first accelerator that processes data, and to instruct a second accelerator to process the data when the information indicates an abnormality;

2. The control device according to claim 1 , wherein the control device is connected between a central processing unit and a plurality of accelerators including the first accelerator and the second accelerator.

3. The control device according to claim 1 , wherein instructing the second accelerator to process the data includes copying the processed data used for processing by the first accelerator to a memory of the second accelerator.

4. The control device includes a memory; The control device according to claim 1 , further configured to store, in a memory of the control device, processed data used for processing by the first accelerator.

5. The control device of claim 1 , further configured to select the second accelerator from available accelerators if the information indicates an anomaly.

6. The controller of claim 1 , further configured to receive information indicative of a state of the second accelerator.

7. A computer system comprising: a central processing unit; a main memory; a memory mirror unit; a plurality of accelerators including a first accelerator and a second accelerator; and the control device according to any one of claims 1 to 6, the memory mirror unit is configured to copy data to another preset address when the central processing unit copies data from the main memory to the memory of the first accelerator; The system is configured such that the first accelerator transmits information to the controller indicative of a state of the first accelerator processing the data.

8. 8. The system of claim 7, wherein the predetermined alternate address is an address in a memory of the control device.

9. A method in which a control device that manages accelerators receives information indicating the status of a first accelerator that processes data, and instructs a second accelerator to process the data if the information indicates an abnormality.

10. A program for causing a computer to receive information indicating the status of a first accelerator that processes data, and, if the information indicates an abnormality, to instruct a second accelerator to process the data.

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