Semiconductor device

Abstract

To provide a novel semiconductor device.SOLUTION: A semiconductor device has a function of performing a product-sum operation between a weight value set by an analog current signal and an input value, in which the analog current signal is output by a digital-to-analog conversion circuit having a circuit in which a plurality of variable resistance elements and switches electrically connected in series are electrically connected in parallel, and a ferroelectric element is used as the variable resistance element. The ferroelectric element has a ferroelectric material containing an oxide containing either hafnium or zirconium, or both.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a semiconductor device. relates to an object, a driving method, or a manufacturing method.

[0002] More specifically, the technical field of one embodiment of the present invention disclosed in this specification is a semiconductor device, Display devices, liquid crystal display devices, light-emitting devices, power storage devices, imaging devices, storage devices, signal processing devices, processors processor, electronic device, system, driving method thereof, manufacturing method thereof, or An example is an inspection method. [Background technology]

[0003] Currently, the development of integrated circuits that mimic the mechanisms of the human brain is progressing vigorously. The brain's mechanisms are incorporated as electronic circuits, and the brain's "neurons" and "systems" are connected. Therefore, such an integrated circuit is called a "neuromorph." Sometimes called "brain-morphic," "brain-inspired," or "brain-morphic" The integrated circuit has a non-von Neumann architecture, and power consumption decreases as processing speed increases. Compared to the von Neumann architecture, which has a high power consumption, parallel processing is possible with extremely low power consumption. It is expected that this will be possible.

[0004] An information processing model that mimics a neural network with "neurons" and "synapses" is called an artificial The artificial neural network (ANN) is used to This makes it possible to make inferences with accuracy comparable to or even exceeding that of humans. In this network, the main operation is the sum of weighted neuron outputs, i.e., the sum of products operation. do.

[0005] Non-Patent Document 1 proposes a product-sum operation circuit using non-volatile memory elements. In the sum-of-products operation circuit, each memory element has a transistor having silicon in the channel forming region. The multiplier stored in each memory element is calculated using the subthreshold operation of the The current corresponding to the multiplication of the data corresponding to the multiplicand and the input data corresponding to the multiplicand is output. The sum of the currents output by the memory elements in each column is used to obtain data corresponding to the sum-of-products operation. The sum-of-products operation circuit has an internal memory element, so it does not require external memory for multiplication and addition. Therefore, reading and writing data from the memory can be prevented. This reduces the number of data transfers due to writing and other processes, thereby reducing power consumption. It is expected that this will reduce [Prior art documents] [Non-patent literature]

[0006] [Non-Patent Document 1] X. Guo et al., “Fast, Energy-Efficient, Robust, and Reproducible Mixed-Signal Neuromorphic Classifier Based on Embedded NOR Flash Memory Technology” IEDM2017, pp.151-154. Summary of the Invention [Problem to be solved by the invention]

[0007] When multiplying and accumulating data using a digital circuit, the digital data that becomes the multiplier (multiplier data) and The digital data (multiplicand data) that is the multiplicand is multiplied by a digital multiplication circuit. The digital data (product data) obtained by the multiplication is added in a digital adder circuit. Digital data (sum-of-products data) is obtained as a result of the sum-of-products operation. It is preferable that the digital adder circuit has specifications that allow it to handle multi-bit operations. In this case, it is necessary to increase the circuit scale of each of the digital multiplication circuit and the digital addition circuit. This may increase the circuit area and power consumption.

[0008] An object of one embodiment of the present invention is to provide a semiconductor device capable of performing a product-sum operation. An object of one embodiment of the present invention is to provide a semiconductor device with low power consumption. An object of one embodiment of the present invention is to provide a semiconductor device with a reduced circuit area. do. [Means for solving the problem]

[0009] One aspect of the present invention is to calculate a product of a weight value set by an analog current signal and an input value. This is a semiconductor device (artificial neural network) that has the function of performing summation operations.

[0010] An analog current signal can also be used to write the input value.

[0011] One embodiment of the present invention is a semiconductor device that inputs data using an analog current signal (analog memory).

[0012] One aspect of the present invention is a current output type digital signal converter that converts a digital signal into an analog current signal. Current output type DAC (Digital to Analog Converter) Converter).

[0013] One embodiment of the present invention is a semiconductor device in which a transistor to which a bias potential is input and a switch are connected in series. The first circuits are electrically connected in a row, and the first circuits are electrically connected in parallel. A digital-to-analog conversion circuit has a second circuit. The total current flowing through the second circuit is The sum of the two switches can be output as an analog current signal. The on or off state is controlled by a signal corresponding to each bit of the digital signal. The gate of the transistor is set to the value of the current that flows through the transistor. The magnitude of the current flowing through each transistor is determined by the digital signal. The current value can be set to a weighted value corresponding to each bit of the signal.

[0014] One aspect of the present invention is a first circuit in which a variable resistance element and a switch are electrically connected in series. a digital amplifier having a first circuit and a second circuit electrically connected in parallel to each other; This is an analog conversion circuit that outputs the sum of the currents flowing through the second circuit as an analog current signal. In the first circuit, the on or off state of the switch can be determined by a digital The voltage can be controlled by a signal corresponding to each bit of the variable resistance element. The magnitude of the current is weighted to correspond to each bit of the digital signal. can be set to.

[0015] The variable resistance element may be made of a material having ferroelectricity.

[0016] For example, an element using a material having ferroelectricity (ferroelectric element) can be used. As an example, a FTJ (ferroelectric tunnel junction) element can be used. The transistor (FeFET element) contains a ferroelectric material as a gate insulating layer. It can be used.

[0017] Ferroelectric materials include hafnium and / or zirconium. The insulating layer may be made of an oxide.

[0018] One aspect of the present invention is a digital-to-analog conversion device using a ferroelectric element as a variable resistance element. It is a circuit.

[0019] The output current of the second circuit is used as the input current of the current mirror circuit. The output current of the path can be used as an analog current signal.

[0020] The output current of the second circuit is used as the input current of the current mirror circuit, and the output voltage is the amplified current value. The current in the current mirror circuit can be used as an analog current signal. The amplification factor can be set in multiple stages according to the digital signal.

[0021] The digital-to-analog conversion circuit of one aspect of the present invention is an artificial neural network. It is not limited to those used in analog memories, for example, video signal input for display devices, etc. It can be used for a variety of purposes. [Effects of the Invention]

[0022] According to one embodiment of the present invention, a semiconductor device with a reduced occupation area can be provided. It is possible to provide a semiconductor device that can handle multi-bit digital signals. According to one embodiment, a semiconductor device with reduced power consumption can be provided. According to one aspect of the present invention, a semiconductor device with improved operating speed can be provided. Also or, according to one aspect of the present invention, a novel semiconductor device can be provided.

Brief Description of the Drawings

[0023] [Figure 1] FIGS. 1(A) to 1(C) are diagrams for explaining a configuration example of a DAC. [Figure 2] FIGS. 2(A) to 2(C) are diagrams for explaining a configuration example of a DAC. [Figure 3] FIG. 3 is a diagram for explaining a configuration example of an arithmetic circuit of an artificial neural network. [Figure 4] FIG. 4 is a diagram for explaining a configuration example of an arithmetic circuit of an artificial neural network. [Figure 5] FIG. 5 is a diagram for explaining a configuration example of an arithmetic circuit of an artificial neural network. [Figure 6] FIG. 6 is a top view photograph of an actually fabricated arithmetic circuit. [Figure 7] FIG. 7 is a circuit diagram showing the configuration of a DAC included in an actually fabricated arithmetic circuit. [Figure 8] FIG. 8 is a graph showing the input / output characteristics of a DAC.

Modes for Carrying Out the Invention

[0024] (Embodiment 1) The DAC 100 according to one aspect of the present invention will be described with reference to the drawings.

[0025] <Configuration Example of DAC100> FIGS. 1(A) to 1(C) show a configuration example of a DAC 100 that converts an n-bit (n is a natural number of 2 or more) digital signal into an analog current signal.

[0026] In FIG. 1(A), the DAC 100 is a transistor to which a bias potential is input to the gate The inverter 102-k (k is a natural number between 1 and n) and the switch 101-k are electrically connected in series. The circuit 110-1 to the circuit 110-n are electrically connected in parallel. The transistor 102-k may have a circuit 120 connected to it. The switch 101-k and the circuit 110-k are not shown in FIG. The sum of the currents flowing through 0 (corresponding to the current Iin) can be output as an analog current signal. can.

[0027] The current Iin flows between the wiring to which the power supply potential V1 is applied and the wiring having a potential difference from the power supply potential V1. For example, the power supply potential V1 flows between the power supply potential V2 and the wiring to which the power supply potential V2 is applied. The potential can be lower than

[0028] In the circuit 110-k, the on or off state of the switch 101-k is determined by a digital It can be controlled by the signal wd[k] corresponding to each bit of the signal. ] can be a digital voltage signal.

[0029] The gate of the transistor 102-k is connected to the current value of the current flowing through the transistor 102-k. A bias potential BIAS is input to set the The magnitude of the current is weighted according to the corresponding bit of the digital signal. It can be set as follows.

[0030] The magnitude of the current flowing through transistor 102-k is adjusted according to the corresponding bit of the digital signal. When the current value is set to be weighted depending on the transistor 102-, for example, The channel width of transistor 102-1 is k-1 It is also possible to double the The transistor 102-k is a transistor having the same configuration as the transistor 102-1. k-1 pieces in parallel The power supply 10 may be electrically connected to the power supply 11.

[0031] The current Iin output from the circuit 120 is used as the input current to the current mirror circuit 130. The output current Iout of the current mirror circuit 130 is output as an analog current signal.

[0032] The current Iin may also be the output current of the DAC 100.

[0033] FIG. 1B shows a configuration in which the current mirror circuit 130 in FIG. 1A is configured with a plurality of transistors. The connections are as shown in the circuit diagram in Figure 1(B). In FIG. 1B, the current mirror circuit 130 is configured using p-channel transistors. However, the present invention is not limited to this, and may be configured using n-channel transistors. In addition, the magnitude of the power supply potential V1 and the power supply potential V2 changes depending on the polarity of the transistors that make up the circuit. Relationships can be changed.

[0034] FIG. 1C shows a configuration example of a current mirror circuit 130 different from that shown in FIG. 1B. In the configuration C), the current mirror circuit 130 has an output current Io relative to the current Iin. For example, the amplification factor of the digital signals d1 to dm (m is 2 or more) can be changed. By controlling the output current Iout, the current value can be varied from 0 times the current value of the current Iin to 2 m -1 times the current value can be selected and output. For example, when m is 8, It is possible to select and output a current value from 255 times to 255 times (current value in 255 steps).

[0035] In this case, when the current flowing through the switch to which the digital signal d1 is input is Iin, the current flowing through the switch to which the digital signal dm is input is 2 m-1 ×Iin, so that the transistors in the current mirror circuit 130 may be designed.

[0036] Thus, a circuit corresponding to a more multi-bit digital signal can be provided.

[0037] This embodiment can be appropriately combined with other embodiments shown in this specification and the like. .

[0038] (Embodiment 2) The DAC100 according to one aspect of the present invention will be described with reference to the drawings.

[0039] <Configuration example of DAC100> Another configuration example of the DAC100 that converts an n-bit (n is a natural number of 2 or more) digital signal into an analog current signal is shown in FIGS. 2(A) to 2(C). Note that the same parts as those in FIGS. 1(A) to 1( C) are shown with the same configuration, and the description thereof is omitted.

[0040] In FIG. 2(A), the DAC100 includes a circuit 110-k in which a variable resistance element 202-k (k is a natural number from 1 to n) and a switch 101-k are electrically connected in series. Note that the variable resistance element 202-k is not shown in FIG. 2(A).

[0041] The magnitude of the current flowing through the variable resistance element 202-k can be set to a weighted current value according to the corresponding bit of the digital signal.

[0042] FIG. 2(B) shows the current mirror circuit 130 in FIG. 2(A) with a plurality of transistors The current mirror circuit 130 in FIG. 2B is an example of a circuit that is configured using the Please refer to the explanation of FIG. 1(B) in the first embodiment.

[0043] FIG. 2C shows a configuration example of a current mirror circuit 130 different from that shown in FIG. 2B. The current mirror circuit 130 in FIG. 2C is explained in conjunction with FIG. 1C in the first embodiment. I will take your opinion into consideration.

[0044] The variable resistance element 202-k is an element using a ferroelectric material (ferroelectric element). As an example, a FTJ (ferroelectric tunnel junction) element can be used. As an example, a ferroelectric material can be used as the gate insulating layer of a transistor. An FeFET device having such a structure can be used.

[0045] Materials that can have ferroelectricity include hafnium oxide, zirconium oxide, and zirconium oxide. Hafnium (HfZrO X (X is a real number greater than 0) ), hafnium oxide with element J1 (here, element J1 is zirconium (Zr), silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y), lanthanum Materials with added elements such as lanthanum (La), strontium (Sr), etc., and zirconium oxide J2 (here, element J2 is hafnium (Hf), silicon (Si), aluminum (A l), gadolinium (Gd), yttrium (Y), lanthanum (La), strontium (Sr, etc.) are added. In addition, materials that can have ferroelectricity Lead titanate (PbTiO X (sometimes referred to as barium strontium titanate) Strontium (BST), Strontium titanate, Lead zirconate titanate (PZT), Tantalum Strontium bismuthate (SBT), bismuth ferrite (BFO), titanate burr Piezoelectric ceramics having a perovskite structure, such as ferroelectric ceramics, may also be used. The material that can have electrical conductivity is, for example, a material selected from the materials listed above. The following mixtures or compounds can be used. Zirconium, zirconium hafnium oxide, and hafnium oxide with the addition of element J1 The crystal structure (characteristics) of these materials can change not only depending on the film formation conditions but also on various processes. Therefore, in this specification, not only materials that exhibit ferroelectricity are called ferroelectrics, but also materials that exhibit ferroelectricity. These materials are called materials that can have electrical conductivity.

[0046] Among these, hafnium oxide, or hafnium oxide and Materials containing zirconium oxide can retain ferroelectricity even when processed into thin films of a few nanometers. In this specification and the like, a material that can have ferroelectricity is The layered structure is sometimes called a ferroelectric layer or a metal oxide film.

[0047] In addition, when hafnium zirconium oxide is used as a material that can have ferroelectricity, the atomic Atomic Layer Deposition (ALD), especially thermal ALD It is preferable to form a film by using a thermal ALD method. When forming a film from a material, hydrocarbon (also called Hydro Carbon, HC) is used as a precursor. It is preferable to use a material that does not contain hydrogen and carbon in a material that can have ferroelectricity. When either or both of these elements are contained, the crystallization of a material that may have ferroelectric properties is inhibited. Therefore, as mentioned above, by using a precursor that does not contain hydrocarbons, Reducing the concentration of either or both of hydrogen and carbon in a material that may have ferroelectric properties For example, a precursor that does not contain hydrocarbons is a chlorine-based material. In addition, hafnium oxide and zirconium oxide are materials that can have ferroelectricity. When using a material with hafnium oxide (hafnium zirconium oxide), the precursor is H fCl4 and / or ZrCl4 may be used.

[0048] When a film is formed using a material that can have ferroelectricity, impurities in the film, such as water in this case, By thoroughly eliminating at least one of oxygen, hydrocarbons, and carbon, high-purity, genuine, strong It is possible to form a film having dielectric properties. The high-purity intrinsic oxide semiconductor shown in the embodiment described later has a very high consistency in the manufacturing process. Therefore, a method for manufacturing a semiconductor device with high productivity can be provided.

[0049] In addition, when hafnium zirconium oxide is used as a material that can have ferroelectricity, heat A Hafnium oxide and zirconium oxide are alternately mixed to form a 1:1 ratio using the LD method. It is preferable to form a film.

[0050] In addition, when using the thermal ALD method to form a film of a material that may have ferroelectricity, the oxidizing agent is HO. Alternatively, O3 can be used. However, the oxidizing agent for the thermal ALD method is not limited to this. For example, oxidizing agents for thermal ALD include O2, O3, N2O, NO2, H2O, and H2O2.

[0051] The crystal structure of the material that can have ferroelectricity is not particularly limited. The crystalline structure of the material may be cubic, tetragonal, orthorhombic, or monoclinic. In particular, the material that can have ferroelectricity is: A cubic crystal structure is preferable because it exhibits ferroelectricity. The material may have a composite structure having an amorphous structure and a crystalline structure.

[0052] This embodiment mode can be appropriately combined with other embodiment modes shown in this specification and the like. .

[0053] (Embodiment 3) The semiconductor device according to one aspect of the present invention is, for example, an arithmetic circuit of an artificial neural network. It can be used for.

[0054] The arithmetic circuit 350 shown in FIG. 3 includes, for example, an array section ALP, a circuit ILD, and a circuit W LD, a circuit XLD, a circuit AFP, and circuits TW[1] to TW[n] (where n is an integer of 1 or greater).

[0055] The circuit ILD and the circuit AFP are connected to each other through the circuits TW[1] to TW[n] by wiring OL[ 1] to wiring OL[n] and wiring OLB[1] to wiring OLB[n]. will be done.

[0056] The circuits TW[1] to TW[n] function as switching circuits. In each circuit TW[n], wirings OL[1] to OL[n] and wirings OLB[ 1] to wiring OLB[n] output signal to the circuit AFP, and the output of the circuit ILD Signals are sent to wiring OL[1] to wiring OL[n] and wiring OLB[1] to wiring OLB[n]. You can switch between input and output.

[0057] The circuit WLD includes wirings WL[1] to WL[m] (m is an integer of 1 or more) and wirings The circuit XLD is electrically connected to the wirings WX1L[1] to WX1L[m]. The wirings X1L[1] to WX1L[m] are electrically connected to each other.

[0058] The arithmetic circuit 350 shown in FIG. 3 has array units ALP arranged in a matrix of m×n units. In FIG. 3, the circuit MP is located in the i-th row and j-th column (where i is an integer between 1 and m). where j is an integer between 1 and n.) is called circuit MP[i,j] However, in Figure 3, the circuit MP[1,1], the circuit MP[1,m], the circuit MP [i,j], circuit MP[n,1], and circuit MP[n,m] are shown. The road MP is not shown in the drawing.

[0059] The circuit MP[i,j] is composed of the wiring WL[i], the wiring WXL1[i], and the wiring OL[j]. , and is electrically connected to wiring OLB[j].

[0060] The circuit MP[i,j] has a function of holding, for example, a weighting coefficient (also referred to as first data). The weighting coefficient is sometimes called a weight value. Specifically, the circuit MP[i,j] is the information storage according to the weighting coefficients input from wiring OL[j] and wiring OLB[j]. Carry out maintenance.

[0061] The circuit ILD includes wirings OL[1] to OL[n] and wirings OLB[1] to OL B[n], and has a function of outputting information corresponding to the first data, which is a weighting coefficient.

[0062] For example, the information corresponding to the weighting coefficient may be a potential, a resistance value, or a current value. When a current value is used as information corresponding to a weighting coefficient, the first embodiment and the second embodiment can be The input current can be generated using the DAC having the configuration described in the second aspect. As the circuit ILD, the DAC having the configuration described in the first and second embodiments is used. This can be done.

[0063] In addition, the circuit MP[i,j] receives an input value (second data It has a function of outputting the product of the weighting coefficient (first data) and the weighting coefficient (first data). In this case, the circuit MP[i,j] receives the second data from WX1L[i] and performs the first A current corresponding to the product of the data and the second data is output to wiring OL[j] and wiring OLB[j]. In addition, in FIG. 3, when the wiring OL[j] and the wiring OLB[j] are placed, Although an example has been shown, one embodiment of the present invention is not limited to this. B[j] may be placed alone.

[0064] The circuit XLD outputs second data as input values ​​to the wirings WXLS[1] to WXLS[m]. It has the function of supplying

[0065] The information corresponding to the input value may be, for example, a potential, a current value, etc. When a current value is used as the corresponding information, the configurations described in the first and second embodiments are The input current can be generated using the DAC. The DAC having the configuration described in the first and second embodiments can be used.

[0066] The first data and the second data output from the circuits MP[1,j] to MP[m,j] The currents corresponding to the product of these are added together and output to wiring OL[j] and wiring OLB[j]. In this way, the arithmetic circuit can perform a product-sum operation on the weighting coefficients and input values.

[0067] Furthermore, the circuit XLD and the circuit WLD receive information according to the first data input from the circuit ILD. For example, the i-th row of the array unit ALP When writing information to the first circuit MP[i,1] to the second circuit MP[i,n], The circuit XLD is, for example, a write circuit included in the circuits MP[i,1] to MP[i,n]. Wiring WXLS[i] for signals to turn on or off switching element 1 , and the write switching elements 1 included in the circuits MP other than the i-th row are turned off. The circuit WLD supplies a potential corresponding to the voltage of the circuit MP[i,1] to the wiring WXLS. to turn on or off the write switching element 2 included in the circuit MP[i,n] A signal to set the state is supplied to the wiring WLS[i], and the writing included in the circuit MP other than the i-th row is A potential that turns off the write switching element 2 is supplied to the wiring WLS.

[0068] The circuit AFP includes circuits ACTF[1] to ACTF[n]. j] is connected to wiring OL[j] and wiring OLB[ The circuit ACTF[j] is electrically connected to the wiring OL[j]. and information corresponding to the result of the sum-of-products operation input from wiring OLB[j] (for example, potential, current value, etc.) and generates a signal according to z1 (k) ~z n (k) can be output as The circuit AFP is configured to operate on the results of the multiplication and addition operations input from the wiring OL[j] and wiring OLB[j]. The information corresponding to the voltage (for example, potential, current value, etc.) is compared, and a signal is generated according to the comparison result. , z1 (k) ~z n (k) It can be output as:

[0069] <Circuit MP> An example of a circuit configuration that can be applied to the circuit MP[i,j] is shown in FIG. and a capacitance C1. For example, the transistor M2 and the capacitance C1 A holding portion HC is formed.

[0070] In the circuit MP of FIG. 4, the circuit MCr has almost the same circuit configuration as the circuit MC. Therefore, the circuit elements of the circuit MCr are distinguished from the circuit elements of the circuit MC. To distinguish between them, the letter "r" is added to the symbols.

[0071] The transistors M1 to M3 shown in FIG. The transistor is an n-channel type with a multi-gate structure that has gates above and below the transistor. Each of the transistors M1 to M3 has a first gate and a second gate.

[0072] Furthermore, the semiconductor device of one embodiment of the present invention can be used without depending on the connection structure of the back gate of the transistor. The transistors M1 to M3 shown in FIG. The connection configuration of the back gate is not shown, but the back gate The electrical connection destination of the gate can be determined at the design stage. In a transistor that uses a gate and a buffer, in order to increase the on-current of the transistor, For example, the gate of transistor M2 may be electrically connected to the gate of In addition, for example, a transistor having a back gate may be electrically connected to the back gate. In a transistor, to vary the threshold voltage of the transistor or To reduce the off-state current of the transistor, wires electrically connected to external circuits, etc. In this case, a potential may be applied to the back gate of the transistor by the external circuit or the like. Regarding this, please refer to the transistors described not only in FIG. 4 but also in other parts of the specification. , or the transistors shown in other figures.

[0073] In addition, a semiconductor device according to one embodiment of the present invention may include a transistor having a structure It does not depend on the transistor. It may be a single gate structure transistor. Some of the transistors have a back gate, and some of the other transistors have a back gate. This can be explained not only in the circuit diagram shown in FIG. Transistors described elsewhere in this specification or illustrated in other drawings The same is true for stars.

[0074] In this specification and the like, transistors having various structures are used as transistors. Therefore, there is no limitation on the type of transistor to be used. Examples include transistors with single crystal silicon, or transistors with amorphous silicon, polycrystalline silicon, etc. Silicon, microcrystalline (also called microcrystal, nanocrystal, or semi-amorphous) A transistor having a non-single-crystal semiconductor film, such as a silicon nitride film, can be used. Alternatively, thin film transistors (TFTs) made from these semiconductors can be used. There are various advantages to using TFTs. For example, they are Since it can be manufactured at a very low temperature, it is possible to reduce manufacturing costs and increase the size of manufacturing equipment. Cut.

[0075] An example of a transistor is a compound semiconductor (e.g., SiGe, GaAs, etc.). ), or oxide semiconductors (e.g., Zn-O, In-Ga-Zn-O, In-Zn-O, I n-Sn-O(ITO), Sn-O, Ti-O, Al-Zn-Sn-O(AZTO), I A transistor having a material such as n-Sn-Zn-O can be used. These compound semiconductors or thin film transistors made by thinning these oxide semiconductors These compound semiconductors or oxide semiconductors can be used as the channel of a transistor. It can be used not only for the wiring part but also for other purposes. The compound semiconductor or oxide semiconductor is used for wiring, a resistor element, a pixel electrode, a light-transmitting electrode, etc. These can be formed as films or layers at the same time as the transistors. Therefore, costs can be reduced.

[0076] An example of a transistor is a transistor formed by an ink-jet method or a printing method. These can be used for manufacturing at room temperature, manufacturing at low vacuum, or can be manufactured on a large substrate. Therefore, it can be manufactured without using a mask (reticle). This allows the transistor layout to be easily changed. Alternatively, it can be manufactured without using resist, which reduces material costs and the number of processes. Or, since it is possible to apply the film only to the necessary parts, after forming the film on the entire surface, This method wastes less material and is less costly than the conventional etching method.

[0077] An example of a transistor is a transistor having an organic semiconductor or a carbon nanotube. This allows transistors to be mounted on a flexible substrate. Transistors can be formed using organic semiconductors or carbon nanotubes. Transistor-based devices can be made shock resistant.

[0078] In the circuit MP shown in FIG. 4, a first terminal of the transistor M1 is electrically connected to a wiring VE. The second terminal of the transistor M1 is electrically connected to the first terminal of the transistor M3. The gate of the transistor M1 is connected to the first terminal of the capacitor C1 and the The first terminal of the capacitor C1 is electrically connected to the wiring VE. The second terminal of the transistor M2 is electrically connected to the wiring OL. The gate of the transistor M2 is electrically connected to the wiring WL. The terminal is electrically connected to the wiring OL, and the gate of the transistor M3 is electrically connected to the wiring WX1L. are actively connected.

[0079] The circuit MCr has a different connection configuration from the circuit MC. The second terminal of the transistor r is electrically connected to the wiring OLB, not to the wiring OL. The first terminal of M1r and the first terminal of the capacitor C1r are electrically connected to the wiring VEr. do.

[0080] In the holding unit HC shown in FIG. 4, the gate of the transistor M1 and the first capacitor C1 The electrical connection point between the terminal and the first terminal of the transistor M2 is referred to as a node n1.

[0081] The holding unit HC has a function of holding a potential corresponding to the weighting coefficient (first data). The potential is held in the holding section HC included in the circuit MC by the transistor M2 and the transistor When transistor M3 is turned on, a current of a predetermined value is input from wiring OL to This can be done by writing to the variable C1 and then turning off transistor M2. As a result, the potential of the node n1 is maintained as a potential according to the weighting coefficient (first data). At this time, a current is input from the wiring OL, and a large current corresponding to the magnitude of the current is applied. Therefore, when the first data is input, the potential of the magnitude can be held in the capacitor C1. The influence of variations in the current characteristics (threshold voltage, etc.) of the transistor M1 can be reduced. do.

[0082] The current input to the wiring OL is input to the DAC having the configuration described in the first or second embodiment. can be generated using

[0083] In addition, since the transistor M1 holds the potential of the node n1 for a long time, the off-state current is small. It is preferable to use a transistor with a low off-state current. For example, an OS transistor can be used as the transistor M1. A transistor having a gate is applied, and a low level potential is applied to the back gate to reduce the threshold voltage. may be shifted to the positive side to reduce the off-state current.

[0084] In this way, a highly reliable arithmetic circuit is provided.

[0085] This embodiment mode can be freely combined with other embodiment modes.

[0086] (Fourth embodiment) In this embodiment, another circuit capable of product-sum operation, which is a semiconductor device of one embodiment of the present invention, will be described. An example will be described.

[0087] FIG. 5 shows a multiplication and accumulation operation of a first data item that is positive or "0" and a second data item that is positive or "0". The calculation circuit MAC1 shown in FIG. 5 is a circuit configuration example for performing the calculation. A multiplication and accumulation operation is performed on the first data corresponding to the potential thus obtained and the second data inputted, and the multiplication and accumulation operation is performed on the first data corresponding to the potential thus obtained. This is a circuit that calculates an activation function using the result of the sum operation. The data may be, for example, analog data or multi-valued data (discrete data). It is possible.

[0088] This arithmetic circuit is called a memory because it also functions as a memory for storing first data. In particular, when analog data is used as the first data, the analog memory You can call.

[0089] The arithmetic circuit MAC1 includes a circuit WCS, a circuit XCS, a circuit WSD, a circuit SWS1, The circuit SWS2, the cell array CA, and the conversion circuits ITRZ[1] to ITRZ[n ] and.

[0090] The cell array CA includes cells IM[1,1] to IM[m,n] (where m is 1 or more). where n is an integer greater than or equal to 1.) and cell IMref[1] The cells IM[1,1] to IM[m,n] are Each of them has a function of holding a potential corresponding to the amount of current according to the first data, and the cell IMr Cells ef[1] to IMref[m] are required to perform product-sum operations with the stored potential. a function of supplying potentials corresponding to the second data to the signal lines XCL[1] to XCL[m]; It has.

[0091] The cell array CA in FIG. 5 has n+1 cells in the row direction and m cells in the column direction, forming a matrix. The cell array CA has two or more cells in the row direction and one or more cells in the column direction. , may be arranged in a matrix.

[0092] Each of the cells IM[1,1] to IM[m,n] is, for example, a transistor F1, a transistor F2, and a capacitor C5, and cells IMref[1] to IM For example, each of ref[m] is a transistor F1m, a transistor F2m, and , and has a capacity C5m.

[0093] In particular, the transistors included in each of the cells IM[1,1] to IM[m,n] The size of the transistor F1 (e.g., channel length, channel width, and transistor configuration) is and each of the cells IM[1,1] to IM[m,n] is preferably equal to The sizes of the transistors F2 included in the cell I are preferably equal to each other. The transistor F1m included in each of the cells Mref[1] to IMref[m] The sizes of the cells IMref[1] to IMref[m ] are preferably equal in size to each other. Moreover, it is preferable that the sizes of the transistors F1 and F1m are equal to each other. , the sizes of the transistors F2 and F2m are preferably equal to each other.

[0094] Unless otherwise specified, the transistors F1 and F1m are in the on state. The above cases include the case where the circuit finally operates in the linear region. The gate, source, and drain voltages of each transistor operate in the linear region. However, this includes cases where the voltage is appropriately biased in the range For example, the transistors F1 and F1m are in an on state. In the case of the linear mode, it may operate in the saturation region. It is also possible to mix the two cases.

[0095] In addition, unless otherwise specified, the transistors F2 and F2m are sub-threads. When operating in the threshold region (i.e., when transistor F2 or transistor F2m In this case, if the gate-source voltage is lower than the threshold voltage, it is more preferable that the drain This includes the case where the current increases exponentially with the gate-source voltage. That is, the gate voltage, source voltage, and drain voltage of each of the above-mentioned transistors is properly biased to a voltage within the subthreshold operating range. Therefore, the transistor F2 and the transistor F2m are This includes cases where an off-state current flows between the in-state and the out-state.

[0096] In addition, the transistor F1 and / or the transistor F1m may be, for example, an OS transistor. In addition, the transistor F1 and / or the transistor F1 The channel forming region of m is formed of indium, element M (for example, aluminum , Gallium, Yttrium, Copper, Vanadium, Beryllium, Boron, Titanium, Iron, Nickel Ru, Germanium, Zirconium, Molybdenum, Lanthanum, Cerium, Neodymium, Hafnium One or more selected from the group consisting of tungsten, tantalum, magnesium, etc. It is more preferable that the oxide contains at least one of zinc and the like.

[0097] An OS transistor is used as the transistor F1 and / or the transistor F1m. This reduces the leakage current of the transistor F1 and / or the transistor F1m. This allows the power consumption of the arithmetic circuit to be reduced. When transistor F1 and / or transistor F1m are in a non-conductive state, a write is performed from the holding node. The leakage current to the word line can be made very small, so the potential of the retention node can be lifted. This reduces the number of reset operations, which reduces the power consumption of the sum-of-products operation circuit. In addition, the leakage current from the retention node to the write word line can be made very small. This allows the cell to maintain the potential of the storage node for a long time, improving the accuracy of the calculation circuit. It can be made easier.

[0098] Also, the transistor F2 and / or the transistor F2m are also OS transistors. By using a capacitor, it is possible to operate in a wide current range in the subthreshold region. Therefore, the current consumption can be reduced. By using an OS transistor for transistor F2m, Since it can be fabricated simultaneously with the register F1m, the fabrication process of the product-sum operation circuit can be shortened. In addition, the transistor F2 and / or the transistor F2m may be In addition to S transistors, transistors that contain silicon in the channel formation region (hereinafter referred to as The silicon can be, for example, amorphous Silicon (sometimes called hydrogenated amorphous silicon), microcrystalline silicon, polycrystalline silicon Silicon, single crystal silicon, etc. can be used.

[0099] Incidentally, when semiconductor devices are highly integrated into chips, the chips contain a large number of circuits. Heat may be generated by driving the device. This heat may cause the temperature of the transistor to rise. The characteristics of the transistor change, resulting in a change in field-effect mobility or a decrease in operating frequency. OS transistors have higher heat resistance than Si transistors, The field effect mobility is less likely to change due to temperature changes, and the operating frequency is less likely to decrease. Furthermore, in OS transistors, the drain current is proportional to the gate-source voltage even at high temperatures. Therefore, it is easy to maintain the exponential increase in capacitance with voltage. This makes it easier to perform the product-sum calculations described below even in high temperature environments. When constructing a semiconductor device that is resistant to heat generated by movement, an OS transistor is used as the transistor. It is preferable to apply

[0100] In each of the cells IM[1,1] to IM[m,n], the transistor F1 The first terminal is electrically connected to the gate of the transistor F2. The first terminal of the capacitor C5 is electrically connected to the wiring VE. It is electrically connected to the gate of F2.

[0101] In addition, in each of the cells IMref[1] to IMref[m], The first terminal of the transistor F1m is electrically connected to the gate of the transistor F2m. The first terminal of the capacitor C5m is electrically connected to the wiring VE. The terminal is electrically connected to the gate of transistor F2m.

[0102] In addition, in the semiconductor device of one embodiment of the present invention, the polarity of a transistor included in the semiconductor device For example, the transistors F1 and F2 shown in FIG. Although the transistors are of the p-channel type, some or all of the transistors may be p-channel. It may be replaced with a transistor.

[0103] The above-mentioned examples of the changes in the structure and polarity of the transistors are as follows: transistor F1 and transistor F2. It is not limited to the transistor F2. For example, the transistor F1m, the transistor F2m , transistors F3[1] to F3[n], and transistor F4[1 ] to transistor F4[n], as well as transistors described elsewhere in the specification. , or the transistors shown in other figures.

[0104] The wiring VE is composed of cells IM[1,1], IM[m,1], IM[1,n], and In order to pass current between the first and second terminals of each transistor F2 of the filter IM[m,n], The wiring for the cell IMref[1] and the cell IMref[m] This functions as a wiring for passing a current between the first terminal and the second terminal of the transistor F2. For example, the wiring VE functions as a wiring that supplies a constant voltage. The constant voltage is For example, it can be a low level potential, a ground potential, or the like.

[0105] In the cell IM[1,1], the second terminal of the transistor F1 is connected to the wiring WCL[1]. The gate of transistor F1 is electrically connected to wiring WSL[1]. The second terminal of the transistor F2 is electrically connected to the wiring WCL[1], and the capacitor C5 The second terminal of the cell IM is electrically connected to the wiring XCL[1]. In [1,1], the first terminal of the transistor F1, the gate of the transistor F2, and the capacitor The connection point between the first terminal of the quantity C5 and the node NN[1,1].

[0106] In the cell IM[m,1], the second terminal of the transistor F1 is connected to the wiring WCL[1]. The gate of the transistor F1 is electrically connected to the wiring WSL[m]. The second terminal of the transistor F2 is electrically connected to the wiring WCL[1], and the capacitor C5 The second terminal of the cell IM is electrically connected to the wiring XCL[m]. In [m, 1], the first terminal of the transistor F1, the gate of the transistor F2, and the capacitor The connection point between the first terminal of the quantity C5 and the node NN[m,1].

[0107] In the cell IM[1,n], the second terminal of the transistor F1 is connected to the wiring WCL[n]. The gate of transistor F1 is electrically connected to wiring WSL[1]. The second terminal of the transistor F2 is electrically connected to the wiring WCL[n] and the capacitor C5 The second terminal of the cell IM is electrically connected to the wiring XCL[1]. In [1,n], the first terminal of the transistor F1, the gate of the transistor F2, and the capacitor The connection point between the first terminal of the quantity C5 and the node NN[1,n].

[0108] In the cell IM[m,n], the second terminal of the transistor F1 is connected to the wiring WCL[n]. The gate of the transistor F1 is electrically connected to the wiring WSL[m]. The second terminal of the transistor F2 is electrically connected to the wiring WCL[n] and the capacitor C5 The second terminal of the cell IM is electrically connected to the wiring XCL[m]. In [m, n], the first terminal of the transistor F1, the gate of the transistor F2, and the capacitor The connection point between the first terminal of the quantity C5 and the node NN[m, n].

[0109] In the cell IMref[1], the second terminal of the transistor F1m is connected to the line XCL[1] The gate of the transistor F1m is electrically connected to the wiring WSL[1]. The second terminal of the transistor F2m is electrically connected to the wiring XCL[1]. The second terminal of the capacitor C5 is electrically connected to the line XCL[1]. In the cell IMref[1], the first terminal of the transistor F1m and the first terminal of the transistor F2m The connection point between the gate of and the first terminal of the capacitor C5 is the node NNref[1].

[0110] In the cell IMref[m], the second terminal of the transistor F1m is connected to the wiring XCL[m] The gate of the transistor F1m is electrically connected to the wiring WSL[m]. The second terminal of the transistor F2m is electrically connected to the wiring XCL[m]. The second terminal of the capacitor C5 is electrically connected to the line XCL[m]. In the cell IMref[m], the first terminal of the transistor F1m and the first terminal of the transistor F2m The connection point between the gate of and the first terminal of the capacitor C5 is defined as a node NNref[m].

[0111] The above-mentioned nodes NN[1,1], NN[m,1], NN[1,n], node NN[m,n], node NNref[1], and node NMref[m] are respectively It serves as a holding node for the cell.

[0112] In the cells IM[1,1] to IM[m,n], for example, the transistor F1 is turned on. When the transistor F2 is in the on state, the transistor F2 is in a diode-connected configuration. The constant voltage applied is the ground potential (GND), and the transistor F1 is in the on state and the wiring W When a current of I flows from CL to the second terminal of transistor F2, The potential of the gate (node ​​NN) is determined according to the amount of current I. Since transistor F1 is on, the potential of the two terminals is ideally The gate of transistor F1 (node ​​NN) is equal to the gate of transistor F2. As a result, the potential of the gate (node ​​NN) of the transistor F2 is maintained. , the transistor F2 is connected to the ground potential of the first terminal of the transistor F2 and the A current of a magnitude I corresponding to the potential of the gate (node ​​NN) flows between the source and drain of transistor F2. In this specification, this operation is referred to as "transistor F2 The amount of current flowing between the source and drain of transistor F2 is programmed to I. It is called "do".

[0113] The circuit SWS1 includes, for example, transistors F3[1] to F3[n]. The first terminal of the transistor F3[1] is electrically connected to the wiring WCL[1]. The second terminal of the transistor F3[1] is electrically connected to the circuit WCS, and the second terminal of the transistor F The gate of transistor F3[n] is electrically connected to wiring SWL1. The first terminal of the transistor F3[n] is electrically connected to the wiring WCL[n], and the second terminal of the transistor F3[n] is electrically connected to the wiring WCL[n]. The transistor F3[n] is electrically connected to the circuit WCS, and the gate of the transistor F3[n] is connected to the wiring SWL. 1 is electrically connected to

[0114] The transistors F3[1] to F3[n] are, for example, the transistor F1, And / or an OS transistor applicable to transistor F2 is preferable.

[0115] The circuit SWS1 is connected to the circuit WCS and each of the wirings WCL[1] to WCL[n]. , functions as a circuit that puts the gap between the two terminals into a conductive state or a non-conductive state.

[0116] The circuit SWS2 includes, for example, transistors F4[1] to F4[n]. A first terminal of the transistor F4[1] is electrically connected to the wiring WCL[1], The second terminal of the transistor F4[1] is electrically connected to the input terminal of the conversion circuit ITRZ[1]. The gate of the transistor F4[1] is electrically connected to the wiring SWL2. The first terminal of the transistor F4[n] is electrically connected to the wiring WCL[n]. The second terminal of the F4[n] is electrically connected to the input terminal of the conversion circuit ITRZ[n]. The gate of the transistor F4[n] is electrically connected to the wiring SWL2.

[0117] The transistors F4[1] to F4[n] are, for example, the transistor F1, And / or an OS transistor applicable to transistor F2 is preferable.

[0118] The circuit SWS2 is connected between the wiring WCL[1] and the conversion circuit ITRZ[1], and between the wiring WCL It functions as a circuit that puts the connection between the ITRZ[n] and the conversion circuit ITRZ[n] into a conductive or non-conductive state. It works.

[0119] The circuit WCS supplies data to be stored in each cell of the cell array CA. It has the function of

[0120] The circuit XCS is electrically connected to the wirings XCL[1] to XCL[m]. The path XCS is a path of the cells IMref[1] to IMref[m] of the cell array CA. For each, a function to pass a current according to the reference data or a current according to the second data is provided. Has.

[0121] The circuit WSD is electrically connected to the wirings WSL[1] to WSL[m]. When writing the first data to the cells IM[1,1] to IM[m,n], the path WSD By supplying predetermined signals to the wirings WSL[1] to WSL[m], the first data It has the function of selecting the row of the cell array CA to which data is to be written.

[0122] In addition, the circuit WSD is electrically connected to the wiring SWL1 and the wiring SWL2, for example. The circuit WSD supplies a predetermined signal to the wiring SWL1. A function to make the connection between CS and the cell array CA conductive or non-conductive, and a ... By supplying a certain signal, the conversion circuits ITRZ[1] to ITRZ[m] and the cell array CA.

[0123] Each of the conversion circuits ITRZ[1] to ITRZ[m] is, for example, For example, the output terminal of the conversion circuit ITRZ[1] is connected to the wiring O L[1], and the output terminal of the conversion circuit ITRZ[n] is connected to the wiring OL[n]. are electrically connected.

[0124] Each of the conversion circuits ITRZ[1] to ITRZ[m] receives an input signal at its input terminal. The voltage is converted into a voltage corresponding to the input current and output from the output terminal. can be, for example, an analog voltage, a digital voltage, etc. Also, the conversion circuit IT Each of the conversion circuits ITRZ[1] to ITRZ[m] may have a function-based arithmetic circuit. In this case, for example, the converted voltage is used to perform a function calculation by the calculation circuit. The results of the calculation may then be output to the wirings OL[1] to OL[n].

[0125] In particular, when performing calculations on a hierarchical artificial neural network, the above function is For example, sigmoid function, tanh function, softmax function, ReLU function, threshold Value functions, etc. can be used.

[0126] The DAC described in the first or second embodiment is used as the circuit WCS shown in FIG. In addition, the XCS shown in FIG. 5 can be the XCS shown in the first embodiment or the XCS shown in the first embodiment. 2 can be used.

[0127] This embodiment mode can be appropriately combined with other embodiment modes shown in this specification and the like. .

[0128] (Embodiment 5) In this embodiment, an example of an electronic device including a semiconductor device according to one embodiment of the present invention will be described. explain.

[0129] In various electronic devices, various information such as acoustic information, image information, illuminance information, and temperature information is collected. In some electronic devices, digital-to-analog conversion is performed to convert various digital information into analog information. By using a semiconductor device according to one embodiment of the present invention, it is possible to perform DA conversion with reduced increase in power consumption. That is, by using a semiconductor device according to one embodiment of the present invention in an electronic device, Furthermore, by using a semiconductor device according to one embodiment of the present invention, precision Furthermore, by using a semiconductor device according to one embodiment of the present invention, High-speed DA conversion can be achieved.

[0130] This embodiment mode can be appropriately combined with other embodiment modes shown in this specification and the like. . [Example]

[0131] An arithmetic circuit incorporating the DAC described in this specification was actually prototyped, and the operation of the DAC was verified. In this example, we will explain the DAC that was actually prototyped and the results of the operation check. Reveal.

[0132] Figure 6 is a photograph of the top view of the die (chip) that contains the actual arithmetic circuit. The die shown in Figure 6 has a silicon transistor on a silicon semiconductor substrate. A transistor is formed on the semiconductor substrate, and an OS transistor is formed above the transistor. Specifically, a circuit (to be described later) is formed on the semiconductor substrate by a Si transistor process. WD, circuit XD, circuit RD, and circuit GD are formed, and the OS transistor process This forms a circuit MCA, which will be described later.

[0133] The circuit WD corresponds to the circuit WCS described in the fourth embodiment, and the circuit XD corresponds to the circuit WCS described in the fourth embodiment. The circuit GD corresponds to the circuit WSD described in the fourth embodiment. The circuit RD includes the conversion circuits ITRZ[1] to ITRZ[2] described in the fourth embodiment. [n]. The circuit MCA corresponds to the cell array CA described in the fourth embodiment. do.

[0134] In particular, a DAC is included in each of the circuits WD and XD.

[0135] The circuit configuration of the DAC included in the prototype arithmetic circuit is shown in Figure 7. The DAC shown in FIG. 7 is based on the configuration of FIG. 1(B), and in FIG. , n is 8. Also, the transistor 102-k has a k-1 Same The transistors are electrically connected in parallel. The transistor 102-2 has a configuration in which two transistors are electrically connected in parallel. The transistor 102-8 has a configuration in which 128 transistors are electrically connected in parallel. The transistor 102-1 is configured to include one transistor. This is a configuration in which two or more transistors are electrically connected in parallel. do not have.

[0136] Here, digital signals of 0 to 255 are input to the wiring wd[1] to wiring wd[8]. In this way, the output current Iout obtained from the current mirror circuit 130 was measured.

[0137] Figure 8 shows the input / output characteristics of the DAC in the actual arithmetic circuit. The input / output characteristics in Figure 8 are plotted with the digital input value (IN (digital)) on the horizontal axis. The vertical axis shows the output current Iout [nA]. ] to wiring wd[8], the output current Iou As a result, t increased in proportion to the value of the digital signal. It was confirmed that the DAC included in the arithmetic circuit operated normally. [Explanation of symbols]

[0138] 100: DAC, 101-k: switch, 102-k: transistor, 110-k: circuit , 110-n: circuit, 110-1: circuit, 120: circuit, 130: current mirror circuit, 202-k: variable resistance element, 350: arithmetic circuit

Claims

1. A semiconductor device having a first digital-to-analog conversion circuit and a second digital-to-analog conversion circuit, the first digital-to-analog conversion circuit has a first ferroelectric element that functions as a variable resistance element; the second digital-to-analog conversion circuit has a second ferroelectric element that functions as a variable resistance element; the first digital-to-analog conversion circuit has a function of generating an analog first current signal corresponding to first data; the second digital-to-analog conversion circuit has a function of generating an analog second current signal corresponding to second data; a function of performing a product-sum operation on the first current signal and the second current signal; Semiconductor device.

2. A semiconductor device having a first digital-to-analog conversion circuit and a second digital-to-analog conversion circuit, the first digital-to-analog conversion circuit has a first ferroelectric element that functions as a variable resistance element; the second digital-to-analog conversion circuit has a second ferroelectric element that functions as a variable resistance element; the first digital-to-analog conversion circuit has a function of generating an analog first current signal corresponding to a weighting coefficient; the second digital-to-analog conversion circuit has a function of generating an analog second current signal corresponding to an input value; a function of performing a product-sum operation on the first current signal and the second current signal; Semiconductor device.

3. In claim 1 or claim 2, each of the first ferroelectric element and the second ferroelectric element comprises a ferroelectric tunnel junction; Semiconductor device.

4. In any one of claims 1 to 3, each of the first ferroelectric element and the second ferroelectric element has an oxide containing either or both of hafnium and zirconium as a material having ferroelectricity; Semiconductor device.

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