Display panel and display device having the same

Abstract

To provide a display panel that offers an improved aperture ratio of each pixel by suppressing the appearance of vertical line mura defects caused by luminance difference between pixels, and to provide a display device including the same.SOLUTION: A display panel disclosed herein may include a first pixel arranged in an n-th row in a second direction; a second pixel located next to the first pixel, arranged in an n-th row in a first direction intersecting the second direction, and a first pixel and a second pixel, different from the first and second pixels in the n-th row, arranged in an (n+1)-th row in the second direction. Both an n-th gate line and an (n+1)-th gate line may be disposed between the first and second pixels of the n-th row and the first and second pixels of the (n+1)-th row.SELECTED DRAWING: Figure 7a

Description

[Technical Field]

[0001] The present specification relates to a display panel that can prevent the occurrence of vertical line stain defects due to luminance differences between pixels and improve the aperture ratio of each pixel, and a display device including the same. [Background technology]

[0002] Organic light emitting display devices include organic light emitting diodes (hereinafter referred to as "OLEDs") that emit light themselves, and have the advantages of a fast response time, luminous efficiency, brightness, and a wide viewing angle. Organic light emitting display devices not only have excellent response time, luminous efficiency, brightness, and viewing angle, but also have excellent contrast ratio and color reproduction rate because they can display black gradations as perfect black.

[0003] In the existing DRD (Double Rate Driving) type pixel with a flip structure, odd / even pixels are arranged symmetrically along the X axis (row direction), and the deviation between the scan wiring that crosses each circuit section and the gate node of the driving element causes a brightness difference between odd / even pixels, resulting in the problem of vertical line stains that are visible to the user.

[0004] Meanwhile, various studies have been conducted to improve the aperture ratio of organic light-emitting display devices, but it is difficult to improve the aperture ratio due to the large number of wirings required to drive the pixels.Furthermore, when each pixel consists of four colors including red, green, blue, and white, it is even more difficult to ensure the aperture ratio. Summary of the Invention [Problem to be solved by the invention]

[0005] In order to solve the above-mentioned problems, the inventors of the present specification have invented a display panel that can prevent the occurrence of vertical line stain defects due to brightness differences between pixels and improve the aperture ratio of each pixel, and a display device including the same.

[0006] The problem to be solved by the embodiments of the present specification is to provide a display panel and a display device including the same, which eliminates the asymmetric structure of the existing flip structure and arranges two scan lines arranged in the column direction through each pixel in the row direction to cross each other at the pixel boundary so that odd and even pixels are under the same conditions, thereby preventing a difference in brightness between odd and even pixels and improving the aperture ratio.

[0007] The object of the present specification is not limited to the object mentioned above, and other unmentioned objects and advantages of the present specification can be understood from the following description and can be more clearly understood from the embodiments of the present specification. Furthermore, it can be easily understood that the object and advantages of the present specification can be achieved by the means and combinations thereof set forth in the claims. [Means for solving the problem]

[0008] According to an embodiment of the present disclosure, there may be provided a display panel, in which a first pixel is arranged in an n-th row in a second direction, a second pixel adjacent to the first pixel in a first direction intersecting the second direction is arranged in the n-th row, a first pixel and a second pixel different from the first pixel and the second pixel in the n-th row are arranged in the n+1-th row in the second direction, an n-th gate line and an n+1-th gate line are arranged between the first pixel and the second pixel in the n-th row and the first pixel and the second pixel in the n+1-th row, and the n-th gate line and the n+1-th gate line are arranged to cross each other at a boundary between the first pixel and the second pixel.

[0009] According to another embodiment of the present disclosure, there may be provided a display panel, in which a first pixel is arranged in an n-th row in a second direction, a second pixel adjacent to the first pixel in a first direction intersecting the second direction is arranged in the n-th row, a first pixel and a second pixel different from the first pixel and the second pixel in the n-th row are arranged in the n+1-th row in the second direction, an n-th gate line is arranged above the first pixel and the second pixel in the n-th row, and an n+1-th gate line is arranged below the first pixel and the second pixel in the n-th row, and the n-th gate line and the n+1-th gate line are arranged to cross each other at a boundary between the first pixel and the second pixel.

[0010] Meanwhile, according to an embodiment of the present disclosure, there may be provided a display device, in which a first pixel is arranged in an n-th row in a second direction, a second pixel adjacent to the first pixel in a first direction intersecting the second direction is arranged in the n-th row, a first pixel and a second pixel in the n-th row and another first pixel and a second pixel are arranged in the n+1-th row in the second direction, an n-th gate line is connected to each of the first pixel and the second pixel in the n-th row, an n+1-th gate line is connected to each of the first pixel and the second pixel in the n+1-th row, and a gate line is connected between the n-th gate line and the n+1-th gate line. The first gate lines include a display panel arranged to cross each other at a boundary between the first pixel and the second pixel, and the display panel has a plurality of data lines, a plurality of gate lines, a plurality of power lines, and a plurality of pixels arranged thereon. A data driver converts pixel data into data voltages and supplies the data voltages to the data lines. A gate driver sequentially supplies gate pulses to the gate lines. A timing controller transmits the pixel data to the data driver and controls the data driver and the gate driver.

[0011] According to the embodiments of the present specification, the odd and even pixels are not arranged in a flip structure, so that the asymmetric structure can be eliminated.

[0012] Furthermore, according to the embodiments of the present specification, two scan lines arranged in the column direction through each pixel in the row direction are arranged to cross each other at the pixel boundary, thereby preventing a difference in brightness between odd and even pixels and improving the aperture ratio.

[0013] In addition, according to the embodiment of the present specification, by arranging two scan lines to cross each other at the pixel boundary, it is possible to prevent the charge amount of the capacitor between the gate node of the driving transistor and the scan line for each pixel from changing regardless of fluctuations in overload.

[0014] Furthermore, according to the embodiments of the present specification, the areas affecting the gate nodes of the driving elements and the scan lines for odd and even pixels are the same, and are not affected by fluctuations in overload (OVL), and may be the same.

[0015] Furthermore, according to the embodiments of the present specification, since pixels do not flip, the capacitors of odd and even pixels do not change due to fluctuations in overload (OVL) between the top and bottom, and therefore, there is no need to apply a fluctuation prevention structure, and the aperture ratio can be increased by increasing the density of the circuit part.

[0016] In addition, according to the embodiments of the present specification, a structure is provided that can minimize an increase in the load of the gate node of the driving transistor of each pixel, thereby reducing the aperture ratio by about 3% compared to the existing flip-chip structure and reducing the brightness difference caused by the continuous arrangement of scan lines.

[0017] Furthermore, according to the embodiment of the present specification, a two-scan structure capable of driving the DRD direction of a normal 4-sub pixel can be formed by increasing the white sub-pixel area.

[0018] Furthermore, according to the embodiments of the present specification, it is possible to drive pixels with high efficiency and high brightness using four subpixel driving, so that the display panel can be driven with low power consumption.

[0019] Furthermore, according to the embodiments of the present specification, it is possible to provide a display panel that improves the aperture ratio and allows for easy repair design, and a display device including the same.

[0020] Furthermore, according to the embodiments of the present specification, since the light-emitting regions that generate white light are not continuous, images can be reproduced on the display panel without white horizontal or vertical stripes, thereby improving display quality.

[0021] In addition, according to the embodiments of the present specification, adjacent pixels alternately drive four sub-pixels and three sub-pixels, thereby increasing the brightness of the image reproduced on the display panel and improving the color reproduction rate.

[0022] Furthermore, according to the embodiments of the present specification, the light-emitting area of ​​the white subpixel can be enlarged without bending the wiring pattern.

[0023] Furthermore, according to the embodiments of the present specification, pixel circuits for driving subpixels of the same color are adjacent to each other in the horizontal direction without any light-emitting area, so that there is almost no reduction in aperture ratio due to repair patterns disposed between them.

[0024] Furthermore, according to the embodiments of the present specification, it is possible to improve the color reproduction rate and improve the display quality, thereby preventing a decrease in the lifespan of the display panel.

[0025] Furthermore, according to the embodiments of the present specification, there is an effect that the display quality is improved, thereby reducing power consumption and improving the life span.

[0026] Furthermore, according to the embodiments of the present specification, there is an effect that the life span can be improved by reducing power consumption, and a display device with a long life span can be provided.

[0027] The display device according to the present disclosure can reduce power consumption, thereby mitigating the reduction in panel lifespan and improving the quality of the display device.

[0028] The effects of this specification are not limited to those mentioned above, and other effects not mentioned above will be clearly understood by those skilled in the art from the following description.

[0029] The above-mentioned effects and specific effects of the present invention will be described in conjunction with the following description of the preferred embodiments of the present invention. [Brief explanation of the drawings]

[0030] The present disclosure will become more fully understood from the detailed description given below and the accompanying drawings. [Figure 1] 1 is a diagram schematically illustrating a configuration of a display device according to an embodiment of the present specification. [Figure 2] FIG. 2 is a diagram illustrating a first and a second pixel according to an embodiment of the present invention. [Figure 3] FIG. 3 is an equivalent circuit diagram showing in detail an example of the pixel circuit shown in FIG. 2. [Figure 4] FIG. 2 is a circuit diagram illustrating an example of a unit pixel circuit. [Figure 5] FIG. 1 shows a luminous region of 22 pixels. [Figure 6] FIG. 10 is a diagram illustrating an example of a hybrid driving method. [Figure 7a] 1 is a diagram showing an example of the arrangement structure of gate lines in a display panel according to an embodiment of the present specification. [Figure 7b]1 is a diagram showing an example of the arrangement structure of gate lines in a display panel according to an embodiment of the present specification. [Figure 7c] 1 is a diagram showing an example of the arrangement structure of gate lines in a display panel according to an embodiment of the present specification. [Figure 8a] 10A and 10B are diagrams illustrating examples of gate line arrangements for a display panel according to another embodiment of the present specification. [Figure 8b] 10A and 10B are diagrams illustrating examples of gate line arrangements for a display panel according to another embodiment of the present specification. [Figure 8c] 10A and 10B are diagrams illustrating examples of gate line arrangements for a display panel according to another embodiment of the present specification. [Figure 9a] 10A and 10B are diagrams illustrating an example in which first and second gate lines intersect at a pixel boundary in a display panel according to an embodiment of the present specification. [Figure 9b] 9b is a cross-sectional view of a display panel according to an embodiment herein taken along the line AA' of FIG. 9a. DETAILED DESCRIPTION OF THE INVENTION

[0031] The above-mentioned objects, features, and advantages will be described in detail below with reference to the accompanying drawings, so that those skilled in the art can easily implement the technical concept of the present invention. In describing the present invention, if a detailed description of known technologies according to the present invention is deemed to obscure the gist of the present invention, the detailed description will be omitted. Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings are used to indicate the same or similar components.

[0032] Furthermore, when a component is described as being "coupled," "coupled," or "connected" to another component, it should be understood that the components may be directly coupled or connected to each other, but that other components may be "intervening" between the components, or that each component may be "coupled," "coupled," or "connected" via other components.

[0033] Unless otherwise defined, all terms (including technical and scientific terms) used in this specification can be used in the sense that they can be commonly understood by a person having ordinary skill in the art to which the present invention belongs. Furthermore, terms defined in commonly used dictionaries should not be interpreted ideally or excessively unless they are clearly and specifically defined.

[0034] In the following, a display device that obtains energy to provide AR or VR and further increases the usage time of power consumption according to an embodiment of the present specification will be described. All components of each display device according to all embodiments of the present disclosure are operatively coupled and configured.

[0035] FIG. 1 is a diagram schematically illustrating the configuration of a display device according to an embodiment of the present specification.

[0036] Referring to FIG. 1, a display device according to the present specification may include a display panel 100, a display panel drive circuit for writing pixel data to pixels of the display panel 100, and a power supply unit 140 for generating power necessary to drive the pixels and the display panel drive circuit.

[0037] The display panel 100 may include a display area (active area; AA) and a non-active area (non-active area; NA). The non-active area (NA) may surround the entire display area (AA), or may surround only a portion of the display area (AA).

[0038] The display panel 100 may include a substrate and a number of sub-pixels arranged on the substrate, and may further include various signal lines for driving the number of sub-pixels.

[0039] The display area (AA) may include a number of data lines (DL) that transmit data signals (also called data voltages or video signals) and a number of gate lines (GL) that transmit gate signals (also called scan signals).

[0040] The plurality of data lines and the plurality of gate lines may intersect with each other. Each of the plurality of data lines may be arranged to extend in a first direction. Each of the plurality of gate lines may be arranged to extend in the first direction. Here, the first direction may be a row direction and the second direction may be a column direction. The first direction may be a column direction and the second direction may be a row direction. The first and second directions may be perpendicular to each other or may intersect with each other.

[0041] The non-display area (NA) may be the outer periphery of the display area (AA) and may include a bezel area. The non-display area (NA) may be entirely or partially visible from the front of the display device, or may be curved and not visible from the front of the display device.

[0042] The display panel 100 may be a rectangular panel having a length in the X-axis direction (or first direction), a width in the Y-axis direction (or second direction), and a thickness in the Z-axis direction (or third direction). The X-axis and Y-axis may be linear axes that are perpendicular to each other on the XY plane. The display area AA of the display panel 100 includes a pixel array that displays an input image. The pixel array includes a plurality of data lines DL, a plurality of gate lines GL intersecting the data lines DL, and pixels arranged in a matrix. The display panel 100 also includes a power supply line commonly connected to the pixels. The power supply line is connected to a constant voltage node of the pixel circuit to supply a constant voltage required to drive the pixels PXL to the pixels PXL. The power supply line PXL may be implemented as a stripe or mesh wiring and commonly connected to the pixels of the display panel 100.

[0043] Each pixel (PXL) includes a first subpixel, a second subpixel, a third subpixel, and a fourth subpixel, each having a different color to realize a color. The arrangement of the subpixel colors may be changed. The first subpixel may be a blue (B) subpixel, the second subpixel may be a green (G) subpixel, the third subpixel may be a red (R) subpixel, and the fourth subpixel may be a white (W) subpixel, but is not limited to this. Each subpixel includes a pixel circuit for driving a light-emitting element. Each pixel circuit is connected to a data line, a gate line, and a power line. Each subpixel is divided into a circuit area and a light-emitting area. The pixel circuit is arranged in the circuit area. The light-emitting area is an area where light is emitted from a light-emitting element electrically connected to the pixel circuit.

[0044] The pixel array includes a plurality of pixel lines (L1 to LN), where N is a real number such as a positive integer greater than 1. Each of the pixel lines (L1 to LN) includes one line of pixels arranged along the line direction (X-axis direction) in the pixel array of the display panel 100. The pixels arranged in one pixel line share a gate line (GL). The sub-pixels arranged in the column direction (Y) along the data line direction share the same data line (DL). One horizontal period is the time obtained by dividing one frame period by the total number of pixel lines (L1 to LN).

[0045] The power supply unit 140 uses a DC-DC converter to output a voltage required to drive the pixels of the display panel 100 and the display panel driving circuit. The DC-DC converter may include a charge pump, a regulator, a buck converter, a boost converter, etc.

[0046] The display panel driving circuit writes pixel data of an input image to pixels of the display panel 100 under the control of a timing controller 130. The display panel driving circuit includes a data driver 110 and a gate driver 120.

[0047] The display panel driver circuit can drive pixels in a DRD (Double Rate Driving) mode. In a display panel driven in the DRD mode, a data line (DL) is connected to adjacent sub-pixels on the left and right, which reduces the number of channels of the data driver 110 and the number of data lines (DL), which is advantageous in ensuring the aperture ratio of the pixel.

[0048] The display panel driving circuit may further include a touch sensor driving unit for driving the touch sensor. The touch sensor driving unit is omitted in Fig. 1. The data driving unit 110 and the touch sensor driving unit may be integrated together into one source drive integrated circuit (IC).

[0049] The data driver 110 receives pixel data of an input image as a digital signal from the timing controller 130 and outputs a data voltage. The data driver 110 converts the pixel data of the input image into a gamma compensation voltage for each frame period using a digital-to-analog converter (DAC) and outputs the data voltage. The data voltage is output through an output buffer in each channel of the data driver 110.

[0050] The gate driver 120 may be formed on the display panel 100 together with the TFT array and wiring of the pixel array. The gate driver 120 may be disposed on the non-display area (NA) of the display panel 100, or at least a portion of the gate driver 120 may be disposed within the display area (AA) where an input image is reproduced.

[0051] The gate driver 120 is disposed in non-display areas (NA) on both sides of the display panel 100 across the display area (AA) of the display panel 100 and can supply gate pulses to both sides of the gate lines (GL) in a double-feed manner. In another embodiment, the gate driver 120 is disposed on either the left or right non-display area (NA) of the display panel 100 and can supply gate signals to the gate lines (GL) in a single-feed manner. The gate driver 120 sequentially outputs gate signal pulses to the gate lines under the control of the timing controller 130. The gate driver 120 can sequentially supply gate signal pulses to the gate lines (GL) by shifting the gate signal pulses (hereinafter referred to as gate pulses) using a shift register. The gate driver 120 may include a plurality of shift registers that output gate signal pulses.

[0052] The timing controller 130 receives digital video data of an input image and timing signals synchronized with the data from the host system 200. The timing signals may include a vertical synchronization signal, a horizontal synchronization signal, a clock, and a data enable signal. The vertical synchronization signal and the horizontal synchronization signal can be omitted because the vertical period and the horizontal period can be determined by counting the data enable signal. The data enable signal has a period of one horizontal period (1H). The timing controller 130 generates a data timing control signal for controlling the operation timing of the data driver 110 and a gate timing control signal for controlling the operation timing of the gate driver 120 based on the timing signals received from the host system 200.

[0053] The timing controller 130 may add white data to three-primary-color pixel data (RGB) input from the host system to convert it into four-color sub-color data (RGBW) and transmit it to the data driver 110. A known color conversion algorithm may be used to convert the three-primary-color pixel data (RGB) into four-color sub-color data (RGBW) including white color data. For example, the timing controller 130 may generate W data of first pixel data based on the minimum grayscale value among R data, G data, and B data of first pixel data received in the input image data, and convert the first pixel data into four-color sub-color data (RGBW). The timing controller 130 may also generate W data of second pixel data based on the minimum grayscale value among R data, G data, and B data of second pixel data received in the input image data, and convert the second pixel data into four-color sub-color data (RGBW). In each of the first and second pixel data, the grayscale values ​​of the R, G, and B data may be lowered by the W data. Here, R data is data written to the red sub-pixels, G data is data written to the green sub-pixels, B data is data written to the blue sub-pixels, and W data is data written to the white sub-pixels.

[0054] The level shifter 150 receives a gate timing control signal from the timing controller 130, generates a start pulse and a shift clock, and provides the start pulse and shift clock to the gate driver 120. The start pulse and shift clock output from the level shifter 150 swing between a gate high voltage and a gate low voltage.

[0055] The host system 200 may include a main board of a TV (television) system, a set-top box, a navigation system, a personal computer (PC), a vehicle system, a mobile terminal, or a wearable terminal. The host system can scale a video signal from a video source to match the resolution of the display panel 100 and transmit the scaled video signal together with a timing signal to the timing controller 130.

[0056] The display device according to the embodiment of the present specification may be a liquid crystal display device, and the display panel 100 may be a self-emitting light-emitting display device. When the display device according to the embodiment of the present specification is a self-emitting light-emitting display device, each of the plurality of sub-pixels may include a light-emitting element.

[0057] For example, the display device according to the embodiment of the present specification may be an organic light emitting display device in which the light emitting elements are organic light emitting diodes (OLEDs). Alternatively, the display device 100 according to the embodiment of the present specification may be an inorganic light emitting display device in which the light emitting elements are inorganic light emitting diodes. Alternatively, the display device 100 according to the embodiment of the present specification may be a quantum dot display device in which the light emitting elements are quantum dots, which are semiconductor crystals that emit light themselves.

[0058] The structures of the subpixels vary depending on the type of display device. For example, if the display device 100 is a self-emitting display device in which the subpixels emit light themselves, each subpixel may include a light-emitting element that emits light itself, one or more transistors, and one or more capacitors.

[0059] The display device according to the embodiments of this specification may include a touch sensor, a touch sensor circuit that senses the touch sensor to detect whether a touch has occurred by a touch object such as a finger or a pen, or detects the touch position, in order to provide not only the function of displaying an image but also the function of a touch sensor.

[0060] The touch sensor circuit may include a touch drive circuit that drives and senses the touch sensor and generates and outputs touch sensor data, and a touch controller that can sense the occurrence of a touch or detect the touch position using the touch sensor data.

[0061] The touch sensor may include a plurality of touch electrodes, and may further include a plurality of touch lines for electrically connecting the plurality of touch electrodes to a touch driving circuit.

[0062] The touch sensor may be present outside the display panel 100 in the form of a touch panel, or may be present inside the display panel 100 .

[0063] When the touch sensor is in the form of a panel and is present outside the display panel 100, the touch sensor is called an external type. When the touch sensor is an external type, the touch panel and the display panel 100 can be manufactured separately and combined during an assembly process. The external type touch panel may include a touch panel substrate and a number of touch electrodes on the touch panel substrate.

[0064] When the touch sensor is present inside the display panel 100, the touch sensor may be formed on the substrate (SUB) together with signal lines and electrodes related to driving the display during the manufacturing process of the display panel 100.

[0065] The touch drive circuit may supply a touch drive signal to at least one of the plurality of touch electrodes, sense the at least one of the plurality of touch electrodes, and generate touch sensor data.

[0066] The touch sensor circuit can perform touch sensing using a self-capacitance sensor method or a mutual-capacitance sensor method.

[0067] When the touch sensor circuit performs touch sensing using a self-capacitance sensor method, the touch sensor circuit can perform touch sensing based on capacitance between each touch electrode and a touch object (eg, a finger, a pen, etc.).

[0068] According to the self-capacitance sensor method, each of the plurality of touch electrodes can function as both a driving touch electrode and a sensing touch electrode, and the touch driving circuit can drive all or part of the plurality of touch electrodes and sense all or part of the plurality of touch electrodes.

[0069] When the touch sensor circuit performs touch sensing using a mutual-capacitance sensor method, the touch sensor circuit can perform touch sensing based on the capacitance between the touch electrodes.

[0070] According to the mutual-capacitance sensor method, a plurality of touch electrodes are divided into driving touch electrodes and sensing touch electrodes, and a touch driving circuit can drive the driving touch electrodes and sense the sensing touch electrodes.

[0071] The touch driver circuit and the touch controller included in the touch sensor circuit may be implemented as separate devices or as a single device, and the touch driver circuit and the data driver 110 may be implemented as separate devices or as a single device.

[0072] The display device according to the embodiments of this specification may be a mobile terminal such as a smartphone or a tablet PC, or may be a monitor or television (TV) of various sizes, or may be a display device of various types and sizes capable of displaying information or images.

[0073] 2 is a diagram illustrating a first and a second pixel according to an embodiment of the present invention. The pixels of the display panel may be arranged in a form in which the first and second pixel structures are repeated.

[0074] Referring to FIG. 2, the display panel 100 may be arranged in a mirror symmetric structure with respect to the Y axis and may include first and second pixels (PXL1, PXL2) adjacent to each other in the first direction, i.e., the X axis direction.

[0075] Each of the first pixel (PXL1) and the second pixel (PXL2) may include a first sub-pixel, a second sub-pixel, and a third sub-pixel that are different in color from each other.

[0076] The first pixel (PXL1) and the second pixel (PXL2) can share multiple white sub-pixels.

[0077] The display panel 100 includes a first data line pair (DL10) arranged on wiring aligned in the Y-axis direction to the left of the first pixel (PXL1), a second data line pair (DL20) arranged on wiring aligned in the Y-axis direction at the boundary between the first pixel (PXL1) and the second pixel (PXL1), a third data line pair (DL30) arranged on wiring aligned in the Y-axis direction to the right of the second pixel (PXL2), a first power supply line (PL10) arranged on wiring aligned in the Y-axis direction between the first data line pair (DL10) and the second data line pair (DL20), and a second power supply line (PL20) arranged on wiring aligned in the Y-axis direction between the second data line pair (DL20) and the third data line pair (DL30).

[0078] The first power supply line (PL10) and the second power supply line (PL20) may each include a plurality of first power supply lines (VL) to which a pixel drive voltage (EVDD) is applied and a second power supply line (RL) to which a reference voltage (Vref) is applied. The plurality of first power supply lines (VL) may be arranged on both sides of the second power supply line (RL) and connected to each other. The width of each of the plurality of first power supply lines (VL) may be greater than the width of the second power supply line (RL).

[0079] In FIG. 2, the first vertical reference line (VL1) is a virtual line extending in the Y-axis direction between the first data line pair (DL10) and the first power supply line (VL, RL). The second vertical reference line (VL2) is a virtual line extending in the Y-axis direction between the first power supply line (VL, RL) and the second data line pair (DLW, DLR). The third vertical reference line (VL3) is a virtual line extending in the Y-axis direction between the second data line pair (DLW, DLR) and the second power supply line (VL, RL). The fourth vertical reference line (VL4) is a virtual line extending in the Y-axis direction between the second power supply line (VL, RL) and the third data line pair (DL30).

[0080] The first pixel (PXL1) includes a blue subpixel, a green subpixel, and a red subpixel arranged along the Y-axis direction so as to pass through virtual first and second vertical reference lines (VL1, VL2). The second pixel (PXL2) includes a blue subpixel, a green subpixel, and a red subpixel arranged along the Y-axis direction so as to pass through virtual third and fourth vertical reference lines (VL3, VL4). The blue subpixel, green subpixel, and red subpixel are separated from each other between the first and second pixels (PXL1, PXL2). Independent R, G, and B data are written to the first and second pixels (PXL1, PXL2).

[0081] The first and second pixels (PXL1, PXL2) share multiple white sub-pixels, whose emissive areas (EW) include the areas where the second and third vertical reference lines (VR2, VR3) intersect with the virtual fourth horizontal reference line (HR4).

[0082] Each of the first and second pixels (PXL1, PXL2) may have four subpixels or three subpixels driven. The four subpixels include a red subpixel, a green subpixel, a blue subpixel, and a shared white subpixel. The three subpixels include a red subpixel, a green subpixel, and a blue subpixel excluding the white subpixel.

[0083] When the first pixel (PXL1) is driven with four sub-pixels, the W data generated from the R, G, and B data of the first pixel (PXL1) is written to the white sub-pixel. When the second pixel (PXL2) is driven with four sub-pixels, the W data generated from the R, G, and B data of the second pixel (PXL2) is written to the white sub-pixel.

[0084] The first and second pixels (PXL1, PXL2) can be driven in a hybrid manner. For example, when the first pixel (PXL1) is driven with four subpixels, the second pixel (PXL2) can be driven with three subpixels. When the second pixel (PXL2) is driven with four subpixels, the first pixel (PXL1) can be driven with three subpixels.

[0085] The timing controller 130 analyzes whether the input image is a pure color or the saturation of the input image, and when the saturation is equal to or greater than a predetermined reference value, it can simultaneously drive three sub-pixels (PXL1, PXL2) and not drive the white sub-pixel.

[0086] The blue subpixel includes a first pixel circuit (CB) and a first light-emitting region (EB) connected to the first pixel circuit (CB) and emitting blue light. The green subpixel includes a second pixel circuit (CG) and a second light-emitting region (EG) connected to the second pixel circuit (CG) and emitting green light. The red subpixel includes a third pixel circuit (CR) and a third light-emitting region (ER) connected to the third pixel circuit (CR) and emitting red light. The white subpixel includes a fourth pixel circuit (CW1, CW2) and a fourth light-emitting region (EW) connected to the fourth pixel circuit (CW1, CW2) and emitting white light. An anode electrode of a light-emitting element (EL) may be disposed in each of the light-emitting regions (EB, EG, ER, EW). The pixel circuits (CB, CG, CR, CW1, CW2) are connected to the anode electrodes of the corresponding light-emitting areas. When a current is generated from the driving element of the pixel circuit, the light-emitting area can emit light. The 4-1st light-emitting area (EW1) is connected to the 4-1st pixel circuit (CW1), and the 4-2nd light-emitting area (EW2) is connected to the 4-2nd pixel circuit (CW2).

[0087] In the white subpixel, the fourth light-emitting region (EW) may be driven by one or two fourth pixel circuits (CW1, CW2). The 4-1 pixel circuit (CW1) and the 4-2 pixel circuit (CW2) are connected to different gate lines as shown in FIG. 3, and gate pulses are input sequentially to drive the light-emitting element of the white subpixel. Here, the fourth light-emitting region (EW) is illustrated as sharing the first pixel (CPLX1) and the second pixel (CPLX2), but is not limited thereto. For example, the fourth light-emitting region may include the 4-1 light-emitting region (EW1) and the 4-2 light-emitting region (EW2), and the first pixel (PXL1) and the second pixel (PXL2) may each share two light-emitting regions (EW1, EW2).

[0088] On the first vertical reference line (VR1), the first pixel circuit (CB) of the first pixel (PXL1), the left side of the first light-emitting area (EB), the left side of the second light-emitting area (EG), the second pixel circuit (CG), and the left side of the third light-emitting area (ER) are arranged from top to bottom.

[0089] On the second vertical reference line (VR2), the right side of the first light-emitting area (EB) of the first pixel (PXL1), the right side of the second light-emitting area (EG), the third pixel circuit (CR), the right side of the third light-emitting area (ER), the 4-1st light-emitting area (EW1), and the 4-1st pixel circuit (CW1) are arranged from top to bottom.

[0090] On the third vertical reference line (VR3), the left side of the first light-emitting area (EB) of the second pixel (PXL2), the left side of the second light-emitting area (EG), the third pixel circuit (CR), the left side of the third light-emitting area (ER), the 4-2 light-emitting area (EW2), and the 4-2 pixel circuit (CW2) are arranged from top to bottom.

[0091] On the fourth vertical reference line (VR4), the first pixel circuit (CB) of the second pixel (PXL2), the right side of the first light-emitting area (EB), the right side of the second light-emitting area (EG), the second pixel circuit (CG), and the right side of the third light-emitting area (ER) are arranged from top to bottom.

[0092] The first and second pixels (PXL1, PXL2) have light-emitting regions of the same color arranged along the X-axis direction. For example, the first light-emitting region (EB) of the first and second pixels (PXL1, PXL2) is arranged on a virtual first horizontal reference line (HR1) aligned in the X-axis direction, and the second light-emitting region (EG) of the first and second pixels (PXL1, PXL2) is arranged below the first light-emitting region (EB) on a virtual second horizontal reference line (HR2) aligned in the X-axis direction. The upper part of the third light-emitting region (ER) of the first and second pixels (PXL1, PXL2) is arranged below the second light-emitting region (EG) on a virtual third horizontal reference line (HR3) aligned in the X-axis direction, and the lower part of the third light-emitting region (ER) of the first and second pixels (PXL1, PXL2) and the fourth light-emitting region (EW) are arranged on a virtual fourth horizontal reference line (HR4) below the third horizontal reference line (HR3). In order to improve color reproduction ratio, the size of the third light-emitting region (ER) that emits red light may be larger than the first and second light-emitting regions (EB, EG).

[0093] The fourth light-emitting region (EW) that emits white light is not continuous on the display panel 100. This prevents the phenomenon of white horizontal or vertical stripes being visible when the entire display region (AA) of the display panel 100 displays a single color or a specific gray.

[0094] The third light-emitting region (ER) may be an "L"-shaped light-emitting region with one side removed from a square. The top of the third light-emitting region (ER) includes a narrow portion 20 adjacent to the top of the fourth light-emitting region (EW). The fourth light-emitting region (EW) is located in an area created by removing a portion of the bottom of the red light-emitting region (ER) of the first pixel (PXL1) and the red light-emitting region (ER) of the second pixel (PXL1), which are mirror-symmetrically adjacent to each other. The top and left and right sides of the fourth light-emitting region (EW) are surrounded by the third light-emitting regions (ER) of the first and second pixels (PXL1, PXL2), and the first light-emitting regions (EB) of the third and fourth pixels (PXL3, PXL4; see FIG. 5) are located below the fourth light-emitting region (EW2). The third and fourth pixels (PXL3, PXL4) are adjacent to each other. Therefore, the fourth light-emitting region (EW) is not adjacent to another fourth light-emitting region (EW).

[0095] The power supply lines (PL10, PL20) can supply constant voltages required to drive the pixels (PXL1, PX2) to the pixel circuits (CB, CG, CR, CW1, CW2). A pixel drive voltage may be applied to the EVDD power supply line (VL), and a reference voltage may be applied to the REF power supply line (RL). The EVDD power supply line (VL) is connected to all pixel circuits (CB, CG, CR, CW1, CW1) adjacent in the X-axis direction via the EVDD power supply line (VL) and supplies pixel drive voltages to these pixel circuits (CB, CG, CR, CW1, CW1). The REF power supply lines (RL) may be arranged on both sides via the relatively wider EVDD power supply line and connected to each other in the non-display area (NA). The REF power supply line (VR) is connected to all pixel circuits (CB, CG, CR, CW1, CW1) adjacent in the X-axis direction via the REF power supply line (VR) to supply a reference voltage to these pixel circuits (CB, CG, CR, CW1, CW1).

[0096] The power supply lines (VL, RL) cross the first light-emitting region (EB), the second light-emitting region (EG), and the third light-emitting region (ER) in each of the first and second pixels (PXL1, PXL2) and overlap the light-emitting regions (EB, EG, ER). The power supply lines (VL, RL) avoid the fourth light-emitting region (EW) and do not overlap the fourth light-emitting region (EW).

[0097] The first data line pair (DL10) includes a first data line (DLB1) to which a data voltage of B data is applied and a second data line (DLG1) to which a data voltage of G data is applied. The first data line (DLB1) is commonly connected to first pixel circuits (CB) of adjacent pixels in the X-axis direction via the first data line (DLB1) and supplies a data voltage of B data to the first pixel circuits (CB). The second data line (DLG1) is commonly connected to second pixel circuits (CG) of adjacent pixels in the X-axis direction via the second data line (DLG1) and supplies a data voltage of G data to the second pixel circuits (CG).

[0098] The first data line (DLB1) is connected to a plurality of first pixel circuits (CB) arranged along the Y-axis direction. The first data line (DLB1) transmits a data voltage of B data to be written to a blue sub-pixel from the data driver 110 to the first pixel circuit (CB). Only the data voltage of B data is applied to the first data line (DLB1). The second data line (DLG1) is connected to a plurality of second pixel circuits (CG) arranged along the Y-axis direction. The second data line (DLG1) transmits a data voltage of G data to be written to a green sub-pixel from the data driver 110 to the second pixel circuit (CG). Only the data voltage of G data is applied to the second data line (DLG1).

[0099] The second data line pair (DL20) includes a third data line (DLR) to which a data voltage of R data is applied and a fourth data line (DLW) to which a data voltage of W data is applied. The third data line (DLR) is commonly connected to the third pixel circuits (CR) of adjacent pixels (PXL1, PXL2) in the X-axis direction via the third data line (DLR) and supplies the data voltage of R data to the third pixel circuits (CR). The fourth data line (DLW) is commonly connected to the fourth pixel circuits (CW1, CW2) of adjacent pixels (PXL1, PXL2) in the X-axis direction via the fourth data line (DLW) and supplies the data voltage of W data to the fourth pixel circuits (CW1, CW2).

[0100] The third data line (DLR) is connected to a plurality of third pixel circuits (CR) arranged along the Y-axis direction. The third data line (DLR) transmits a data voltage of R data to be written to the red sub-pixel from the data driver 110 to the third pixel circuit (CR). Only the data voltage of R data is applied to the third data line (DLR). The fourth data line (DLW) is connected to a plurality of fourth pixel circuits (CW1, CW2) arranged along the Y-axis direction. The fourth data line (DLW) transmits a data voltage of W data to be written to the white sub-pixel from the data driver 110 to the fourth pixel circuits (CW1, CW2). Only the data voltage of W data is applied to the fourth data line (DLW).

[0101] The second data line pair (DL20) crosses the fourth light-emitting region (EW) and overlaps with the fourth light-emitting region (EW). The second data line pair (DL20) avoids the other light-emitting regions (EB, EG, ER) and pixel circuits (CB, CG, CR, CW1, CW2) so as not to overlap with these components (EB, EG, ER, CB, CG, CR, CW1, CW2).

[0102] The third data line pair (DL30) includes a fifth data line (DLB2) to which a data voltage of B data is applied and a sixth data line (DLG2) to which a data voltage of G data is applied. The fifth data line (DLB2) receives only the data voltage of B data, which is supplied from the data driver 110 to the blue subpixels. The sixth data line (DLG2) receives only the data voltage of G data, which is supplied from the data driver 110 to the green subpixels. The fifth data line (DLB2) is commonly connected to the first pixel circuits (CB) of adjacent pixels in the X-axis direction via the fifth data line (DLB2) and supplies the data voltage of B data to the first pixel circuits (CB). The sixth data line (DLG2) is commonly connected to the second pixel circuits (CG) of adjacent pixels in the X-axis direction via the sixth data line (DLG2) and supplies the data voltage of G data to the second pixel circuits (CG).

[0103] Although multiple gate lines are arranged along the first direction (X), the colors in the second direction (Y) may be formed by connecting two gate lines arranged between two different light-emitting regions (EB, EG or ER, EW).

[0104] Each gate line is arranged for each pixel line, and two adjacent gate lines are commonly connected to one output terminal of the gate driver 120. For example, as shown in FIGS. 2 and 3, two gate lines arranged through two different color light-emitting regions may be connected to each other and connected to a specific output terminal of the gate driver 120. Therefore, a gate pulse may be applied to two pixel lines simultaneously. The nth gate line (GLn) may simultaneously apply a gate pulse to pixel circuits (CB, CG, CR, CW1, CW2) distributed across the two pixel lines. In FIG. 2, some pixel circuits (CW2) connected to the nth gate line (GLn) are omitted. Gate pulses are sequentially applied to the gate lines (GLn-1 to GLn+2) in the order of GLn-1, GLn, GLn+1, and GLn+2, where n is a real number such as an integer.

[0105] Between two gate lines (GLn) connected to each other, and between two light-emitting areas (EB, EG or ER, EW) of different colors, scan lines (SCn, SCn+1) may be arranged to drive only the sensor transistors (T2) of the first pixel (PXL1) and the second pixel (PXL2), respectively.

[0106] For example, the scan lines (SCn, SCn+1) may be arranged such that the nth scan line (SCn) is arranged between a first light-emitting region (EB) and a second light-emitting region (EG) which are different in color, and the n+1th scan line (SCn+1) is arranged between a third light-emitting region (ER) and a fourth light-emitting region (EW1, EW2) which are different in color.

[0107] For example, the nth scan line (SCn) may be arranged between two gate lines of the nth gate line (GLn) in the first direction (X), and between a first light-emitting region (EB) and a second light-emitting region (EG) having different colors in the second direction (Y) of the first pixel (PXL1) and the second pixel (PXL2).

[0108] In addition, the n+1th scan line (SCn+1) may be arranged between two gate lines of the n+1th gate line (GLn+1) in the first direction (X) and between the third light-emitting region (ER) and the fourth light-emitting region (EW1, EW2) of the first pixel (PXL1) and the second pixel (PXL2) which have different colors in the second direction (Y).

[0109] The first to third light-emitting regions (EB, EG, ER) of the first pixel (PXL1) and the first to third light-emitting regions (EB, EG, ER) of the second pixel (PXL2) may be arranged in mirror symmetry with respect to the first direction (X).

[0110] A fourth light-emitting region (EW1, EW2) may be disposed between the third light-emitting region (ER) of the first pixel (PXL1) and the third light-emitting region (ER) of the second pixel (PXL2) in the first direction (X). The third light-emitting region (ER) may include a third sub-pixel, and the fourth light-emitting region (EW1, EW2) may include a white sub-pixel.

[0111] The distribution of the light-emitting areas of the subpixels for each color can be appropriately selected taking into consideration color gamut and brightness. For example, in an image or display model where high brightness relative to color gamut is important, the area of ​​the fourth light-emitting region (EW) can be further increased, thereby increasing the driving voltage of the three subpixels excluding the white subpixel. The structure of the third and fourth light-emitting regions (ER, EW) shown in FIG. 2 is a structure that allows the size of the fourth light-emitting region (EG) parallel to the horizontal reference line to be easily expanded or reduced, making it easy to distribute the areas of the third and fourth light-emitting regions (ER, EW) without changing the wiring shape. In a display model where pure colors are important, the fourth light-emitting region (EG) can be reduced. To increase brightness, the fourth light-emitting region (EG) may be enlarged.

[0112] Figure 3 is an equivalent circuit diagram showing in detail an example of the pixel circuit shown in Figure 2. Figure 4 is a circuit diagram showing a single pixel circuit.

[0113] Referring to Figures 3 and 4, each of the pixel circuits (CB, CG, CR, CW1, CW2) is connected to a data line (DL) to which a data voltage (Vdata) of pixel data is applied, a gate line (GL) to which a gate pulse (SCAN) is applied, a power supply line (VL) to which a pixel driving voltage (EVDD) is applied, a VDD power supply line to which a cathode voltage (EVSS) is applied, and a reference voltage (Vref) is connected to a REF power supply line (RL).

[0114] The display panel 100 has a plurality of gate lines arranged along the first direction (X), but two gate lines arranged via two light-emitting regions (EB, EG or ER, EW) having different colors in the second direction (Y) may be connected to each other.

[0115] Each of the pixel circuits (CB, CG, CR, CW1, CW2) includes a light emitting element (EL), a plurality of transistors (DT, T1, T2), and a capacitor (C).

[0116] The light emitting element (EL) may be an inorganic light emitting element such as an organic light emitting diode (OLED) or a micro LED. The light emitting element (EL) may include, but is not limited to, a red light emitting element, a green light emitting element, and a blue light emitting element. The anode electrode of the light emitting element (EL) is electrically connected to the driving element (DT) and disposed in a corresponding light emitting area in each pixel. The light emitting element (EL) is driven to emit light when a current is generated from the driving element (DT), and the light is emitted to the outside of the display panel 100 through the light emitting area.

[0117] The driving element (DT) generates a current according to a voltage between its gate and source to drive the light emitting element (EL). The driving element (DT) includes a gate electrode connected to a first node (N1), a first electrode connected to a second node (N2), and a second electrode connected to a third node (N3). The capacitor (C) is connected between the first node (N1) and the third node (N3). The second node (N2) is connected to the EVDD power supply line (VL). The third node (N3) is connected to the anode electrode of the light emitting element (EL). The cathode electrode of the light emitting element (EL) is connected to a power supply line to which a cathode voltage (EVSS) is applied.

[0118] The first switch element (T1) is connected between the data line (DL) and a first node (N1). The first switch element (T1) may be, for example, a scan transistor. The first switch element (T1) is turned on in response to a gate pulse (SCAN). When the first switch element (T1) is turned on, a data voltage (Vdata) of pixel data is applied to the first node (N1), and the pixel data is written to the subpixel. The first switch element (T1) includes a gate electrode connected to the gate line (GL), a first electrode connected to the data line (DL), and a second electrode connected to the first node (N1).

[0119] The second switch element (T2) is connected between the third node (N3) and the REF power supply line (RL). The second switch element (T2) may be, for example, a sensor transistor. The second switch element (T2) is turned on in response to a gate pulse (SCAN). When the second switch element (T2) is turned on, the third node (N3) is connected to the REF power supply line (RL). The second switch element (T2) includes a gate electrode connected to the scan line (SCn, SCn+1), a first electrode connected to the third node (N3), and a second electrode connected to the REF power supply line (RL).

[0120] Although the driving elements (DT) should have uniform electrical characteristics in all subpixels, differences can occur between subpixels due to process variations and variations in element characteristics, and these differences can become larger as the subpixels are driven over time. To compensate for these variations in the electrical characteristics of the driving elements (DT), an external compensation circuit can be applied to the display panel driving circuit.

[0121] The external compensation circuit senses and compensates for the electrical characteristics of the driver element (DT) in real time in sensing mode. Sensing mode is divided into pre-production and post-production. Before product shipment, the electrical characteristics of the driver element (DT) in each sub-pixel are sensed via the reference power line (RL) connected to the pixel, and the sensing results are used to compensate for deviations in the electrical characteristics of the driver element (DT) for each sub-pixel.

[0122] After product shipment, the sensing modes are divided into ON RF mode performed during the power-on sequence, RT mode performed during the vertical blank period (VB) during the display driving period, and OFF RS mode performed during the power-off sequence.

[0123] In the ON RF mode, the external compensation circuit senses the mobility of the driver element (DT) that drives the light-emitting element via the REF power line (RL) in each pixel when the display device is powered on, compares the mobility sensing result with the driver element mobility compensation value measured for each subpixel before product shipment, and updates the mobility compensation value based on the difference. Before product shipment, the threshold voltage and mobility of the driver element (DT) for each subpixel are sensed in sensing mode, and the driver element threshold voltage compensation value and mobility compensation value are set in a look-up table. The driver element mobility is compensated for for each subpixel using a mobility compensation value that reflects the driver element mobility sensing result.

[0124] In the RT mode, during a display driving period in which an image is displayed, the mobility of the driving element (DT) is sensed in real time via the REF power line (RL) during the vertical blank period (VB) of each frame period, and the mobility compensation value is updated for each subpixel according to the mobility sensing result. The vertical blank period is a period in which no data is input to the timing controller 130 between the active period of the (N-1)th frame period and the active period of the Nth frame period.

[0125] In the OFF RS mode, when the display device is powered off, the external compensation circuit senses the threshold voltage of the driving element (DT) in each pixel via the REF power line (RL) and updates the threshold voltage compensation value for each subpixel based on the threshold voltage sensing result. In the OFF RS mode, before the power is completely turned off, the display panel driving circuit and the external compensation circuit are driven for a predetermined delay time to sense the threshold voltage of the driving element (DT) in each subpixel and update the threshold voltage compensation value for the driving element (DT) in each subpixel.

[0126] The external compensation circuit includes an analog-to-digital converter (ADC) electrically connected to the REF power line (RL) and a compensation circuit for compensating data from the ADC. A lookup table of the compensation circuit stores compensation values ​​for compensating for the threshold voltage and mobility of a driving element that drives a light emitting element for each subpixel. The compensation circuit inputs sensing data output from the ADC to the lookup table and adds or multiplies the compensation value output from the lookup table to pixel data of an input image to modulate the pixel data, thereby compensating for changes in the electrical characteristics of the driving element. An ADC may be provided for each sensing channel set in a source drive IC integrated in the data driver 110. The compensation circuit may be implemented in a logic circuit of the timing controller 130.

[0127] Fig. 5 is a diagram showing a light-emitting area of ​​22 pixels, and Fig. 6 is a diagram showing an example of a hybrid driving method.

[0128] Referring to Figures 5 and 6, third and fourth pixels (PXL3, PXL4) having substantially the same structure as the first and second pixels (PXL1, PXL2) may be arranged below the first and second pixels (PXL1, PXL2).

[0129] The first to fourth pixels (PXL1 to PXL4) can be hybrid-driven as shown in FIG. 6. In a predetermined time unit, the first to fourth pixels (PXL1 to PXL4) can be alternately driven as four subpixels and three subpixels. For example, during an odd-numbered frame period (FRodd), the first and fourth pixels (PXL1, PXL4) can be driven as four subpixels, and the second and third pixels (PXL2, PXL3) can be driven as three subpixels, as shown in FIG. 6. During an even-numbered frame period (FReven), the first and fourth pixels (PXL1, PXL4) can be driven as three subpixels, and the second and third pixels (PXL2, PXL3) can be driven as four subpixels, as shown in FIG. 6. When the first pixel (PXL1) is driven as four subpixels, the W data written to the white subpixel is generated from the R, G, and B data of the first pixel (PXL1). When the second pixel (PXL2) is driven with four sub-pixels, the W data written to the white sub-pixel is generated from the R, G, and B data of the second pixel (PXL2). When the third pixel (PXL3) is driven with four sub-pixels, the W data written to the white sub-pixel is generated from the R, G, and B data of the third pixel (PXL3). When the fourth pixel (PXL4) is driven with four sub-pixels, the W data written to the white sub-pixel is generated from the R, G, and B data of the fourth pixel (PXL4).

[0130] 7a to 7c are diagrams showing examples of the arrangement structure of gate lines in a display panel according to an embodiment of the present specification.

[0131] Referring to Figures 7a to 7c, a display panel 100 according to an embodiment of the present specification may include a first pixel (PXL1) arranged in an nth row in a second direction (Y), and a second pixel (PXL1) arranged in the nth row and adjacent to the first pixel in a first direction (X) intersecting the second direction.

[0132] Each of the first pixel (PXL1) and the second pixel (PXL2) may include first to fourth subpixels (R, W, B, G) of different colors. The first subpixel may be a red subpixel (R). The second subpixel may be a white subpixel (W). The third subpixel may be a blue subpixel (B). The fourth subpixel may be a green subpixel (G).

[0133] The first pixel (PXL1) and the second pixel (PXL2) in the nth row in the second direction (Y) and another first pixel (PXL1) and a second pixel (PXL2) may be arranged in the n+1th row.

[0134] An nth gate line (GLn) and an n+1th gate line (GLn+1) may be arranged between the first pixel and the second pixel in the nth row and the first pixel and the second pixel in the n+1th row.

[0135] The nth gate line (GLn) and the n+1th gate line (GLn+1) may be arranged to intersect with each other at the boundary (Pixel Border Area; PBA) between the first pixel (PXL1) and the second pixel (PXL2).

[0136] The n-th gate line (GLn) and the (n+1)-th gate line (GLn+1) may be arranged in different layers.

[0137] The n-th gate line (GLn) may be electrically connected to each of the first pixel (PXL1) and the second pixel (PXL2) arranged in the n-th row.

[0138] The (n+1)th gate line (GLn+1) may be electrically connected to each of the first pixel (PXL1) and the second pixel (PXL2) arranged in the (n+1)th row.

[0139] The nth gate line (GLn) and the n+1th gate line (GLn+1) can overlap with a second power supply line (RL) to which a reference voltage (Vref) is applied, which is arranged along the second direction (Y) at the boundary (PBA) between the first pixel (PXL1) and the second pixel (PXL2).

[0140] 7a and 7b, the first pixel (PXL1) and the second pixel (PXL2) have the first to fourth sub-pixels (R, W, B, G) arranged in the same row, but are not limited thereto. For example, the first pixel (PXL1) and the second pixel (PXL2) may have a structure in which they share a white sub-pixel (W).

[0141] Each of the first sub-pixels may include a first pixel circuit and a first light-emitting region coupled to the first pixel circuit, and each of the second sub-pixels may include a second pixel circuit and a second light-emitting region coupled to the second pixel circuit.

[0142] Additionally, each of the third sub-pixels may include a third pixel circuit and a third light-emitting region coupled to the third pixel circuit, and each of the white sub-pixels may include a fourth pixel circuit and a fourth light-emitting region coupled to the fourth pixel circuit.

[0143] As shown in the above-mentioned Figures 7a to 7c, the nth gate line (GLn) and the n+1th gate line (GLn+1) may be arranged to cross each other at the boundary (PBA) between the first pixel (PXL1) and the second pixel (PXL2).

[0144] Therefore, the display panel 100 according to an embodiment of the present specification implements a compensation form based on the overload (OVL) fluctuation of the capacitor (Cst), as shown in FIG. 7c, and does not require a pattern (PTN) for this purpose, and has the effect of being resistant to overload (OVL) fluctuation and increasing the open rate (OpR).

[0145] 8a to 8c are diagrams showing examples of gate line arrangements for a display panel according to another embodiment of the present specification.

[0146] Referring to Figures 8a to 8c, a display panel 100 according to an embodiment of the present specification may include a first pixel (PXL1) arranged in an nth row in a second direction (Y), and a second pixel (PXL1) arranged in the nth row and adjacent to the first pixel in a first direction (X) intersecting the second direction.

[0147] Each of the first pixel (PXL1) and the second pixel (PXL2) may include first to fourth subpixels (R, W, B, G) of different colors. The first subpixel may be a red subpixel (R). The second subpixel may be a white subpixel (W). The third subpixel may be a blue subpixel (B). The fourth subpixel may be a green subpixel (G).

[0148] The first pixel (PXL1) and the second pixel (PXL2) in the nth row in the second direction (Y) and another first pixel (PXL1) and a second pixel (PXL2) may be arranged in the n+1th row.

[0149] The nth gate line (GLn) may be arranged above the first pixel (PXL1) and the second pixel (PXL2) in the nth row, and the n+1th gate line (GLn+1) may be arranged below the first pixel (PXL1) and the second pixel (PXL2) in the nth row.

[0150] The nth gate line (GLn) and the (n+1)th gate line (GLn+1) may be disposed to intersect with each other at a boundary (PBA2) between the first pixel (PXL1) and the second pixel (PXL2). That is, the nth gate line (GLn) extends in the first direction (X) above the first pixel (PXL1) of the nth row, turns downward vertically at the boundary (PBA2), extends downward in the second direction (Y) to overlap with the second power line (RL), and then extends in the first direction (X) below the second pixel (PXL2) of the nth row.

[0151] In addition, the (n+1)th gate line (GLn+1) extends in the first direction (X) below the first pixel (PXL1) in the nth row, then bends upward vertically at the boundary (PBA2), extends upward in the second direction (Y) to overlap with the second power line (RL), and then extends in the first direction (X) above the second pixel (PXL2) in the nth row.

[0152] The n-th gate line (GLn) and the (n+1)-th gate line (GLn+1) may be arranged in different layers.

[0153] The n-th gate line (GLn) may be electrically connected to each of the first pixel (PXL1) and the second pixel (PXL2) arranged in the n-th row.

[0154] The (n+1)th gate line (GLn+1) may be electrically connected to each of the first pixel (PXL1) and the second pixel (PXL2) arranged in the (n+1)th row.

[0155] The nth gate line (GLn) and the n+1th gate line (GLn+1) can overlap with a second power supply line (RL) to which a reference voltage (Vref) is applied, which is arranged along the second direction (Y) at the boundary (PBA2) between the first pixel (PXL1) and the second pixel (PXL2).

[0156] As shown in the above-mentioned Figures 8a to 8c, the nth gate line (GLn) and the n+1th gate line (GLn+1) may be arranged to cross each other at the boundary (PBA2) between the first pixel (PXL1) and the second pixel (PXL2).

[0157] Therefore, the display panel 100 according to an embodiment of the present specification implements a compensation form based on the overload (OVL) fluctuation of the capacitor (Cst), as shown in FIG. 8c, and does not require a pattern (PTN) for this purpose, and has the effect of being resistant to overload (OVL) fluctuation and increasing the aperture ratio (OpR).

[0158] 9a is a diagram illustrating an example in which first and second gate lines in a display panel according to an embodiment of the present disclosure intersect at a pixel boundary, and FIG. 9b is a cross-sectional view of the display panel according to an embodiment of the present disclosure taken along line A-A' in FIG.

[0159] Referring to FIG. 9a, the display panel 100 according to an embodiment of the present specification may have a structure in which the first gate line (GLn) and the second gate line (GLn+1) are arranged to cross each other in the pixel boundary area (PBA) and overlap with the second power line (RL) in this boundary area (PBA).

[0160] Referring to FIG. 9b, the display panel 100 according to an embodiment of the present specification may have a second data line (DLG1), a first light-shielding film (LS1), a second power line (RL), a second light-shielding film (LS2), and a third data line (DLR1) arranged on a substrate (GLS).

[0161] A buffer film (BUF) may be disposed on the substrate (GLS), the second data line (DLG1), the first light-shielding film (LS1), the second power supply line (RL), the second light-shielding film (LS2), and the third data line (DLR1).

[0162] The first and second light-shielding films (LS1, LS2) are formed corresponding to the channel region or semiconductor layer (ACT) of the driving transistor (DT). The first and second light-shielding films (LS1, LS2) are made of metal such as copper (Cu) and can be used as electrodes for constituting a capacitor by connecting with other electrodes or lines as well as blocking external light.

[0163] A first source line (DTs1) of the drive transistor (DT), an n+1-th gate line (GLn+1), and a second source line (DTs2) of the drive transistor (DT) may be arranged on the buffer film (BUF).

[0164] A gate insulating film (GI) may be disposed on the buffer film (BUF), the first and second source lines (DTs1, DTs2) of the drive transistor (DT), and the n+1-th gate line (GLn+1). Here, the n+1-th gate line (GLn+1) may be referred to as the second gate line (GLn+1).

[0165] The first and second source lines (DTs1, DTs2) and the n+1th gate line (GLn+1) of the drive transistor (DT) may be formed of a semiconductor layer (ACT). The semiconductor layer (ACT) is the semiconductor layer of the drive transistor (DT) and may be composed of an oxide semiconductor layer (e.g., IGZO). For example, the portions of the semiconductor layer (ACT) corresponding to the source and drain regions, excluding the portion corresponding to the channel region, are converted into metal electrodes or wiring (metalization), thereby forming the first and second source lines (DTs1, DTs2) and the n+1th gate line (GLn+1) of the drive transistor (DT). The conversion process may be, but is not limited to, an O2 plasma or etching process.

[0166] A first gate line (DTg1) of the driving transistor (DT), an n-th gate line (GLn), and a second gate line (DTg2) of the driving transistor (DT) may be arranged on the gate insulating film (GI), where the n-th gate line (GLn) can be referred to as the first gate line (GLn).

[0167] A passivation film (PAS) may be disposed on the gate insulating film (GI), the first and second gate lines (DTg1, DTg2) of the drive transistor (DT), and the n-th gate line (GLn).

[0168] A planarization film (PAC) may be disposed on the passivation film (PAS).

[0169] A first anode electrode (AE1) and a second anode electrode (AE2) may be disposed on the planarization film (PAC). The first anode electrode (AE1) may be an electrode disposed in the first pixel (PXL1), and the second anode electrode (AE2) may be an electrode disposed in the second pixel (PXL2).

[0170] An organic light-emitting layer (OLED) may be disposed on the planarization film (PAC), the first anode electrode (AE1), and the second anode electrode (AE2).

[0171] A cathode electrode (CE) may be disposed on the organic light-emitting layer (OLED).

[0172] The first and second anode electrodes (AE1, AE2) may include an ITO (Indium Tin Oxide) material, and the cathode electrode (CE) may include a metal such as aluminum (Al).

[0173] As described above, according to the embodiments of the present specification, it is possible to provide a display panel and a display device including the same, in which two scan lines arranged in the column direction through each pixel in the row direction are arranged to cross each other at the boundary between pixels, thereby preventing a difference in brightness between odd and even pixels and improving the aperture ratio.

[0174] As described above, the present specification has been described with reference to exemplary drawings, but the present specification is not limited to the embodiments and drawings disclosed in the present specification, and it is obvious that various modifications can be made by those skilled in the art within the scope of the technical concept of the present specification. Furthermore, even if the effects of the configurations of the embodiments of the present specification have not been explicitly described and explained, it is natural that the effects that can be predicted by the configurations should also be recognized. [Explanation of symbols]

[0175] 100 Display Panel 110 Data Drive Unit 120 Gate driver 130 Timing Controller 140 Power supply section 150 Level Shifter 200 host systems VL, RL power supply lines AA display area NA hidden area PXL1, PXL Pixel GL Gate Line PL10, PL20 power line CB 1st pixel circuit EB First light-emitting region CG Second pixel circuit EG Second light-emitting area CR 3rd pixel circuit ER Third emission region CW 4th pixel circuit EW Fourth Light Region T1, T2 switch elements DT drive element EVDD Pixel drive voltage Vref Reference voltage GLS board LS1, LS2 Light shielding film BUF Buffer film GI gate insulating film PAS passivation film PAC planarization film OLED organic light-emitting layer AE1, AE2 anode electrodes CE cathode electrode

Claims

1. a first pixel disposed in the n-th row in the second direction; a second pixel arranged in the n-th row and adjacent to the first pixel in a first direction intersecting the second direction; Including, where n is a real number, each of the first pixel and the second pixel includes first to fourth sub-pixels configured to emit light of different colors; a first pixel and a second pixel different from the first pixel and the second pixel of the nth row are arranged in the n+1th row in the second direction, an n-th gate line and an n+1-th gate line are disposed between the first pixel and the second pixel of the n-th row and the first pixel and the second pixel of the n+1-th row; the n-th gate line and the n+1-th gate line are arranged to cross each other at a boundary between the first pixel and the second pixel. Display panel.

2. the n-th gate line and the n+1-th gate line are disposed in different layers; The display panel according to claim 1 .

3. the n-th gate line is electrically connected to each of the first pixels and the second pixels arranged in the n-th row; The (n+1)th gate line is electrically connected to each of the first and second pixels arranged in the (n+1)th row. The display panel according to claim 1 .

4. each of the n-th gate line and the n+1-th gate line overlaps with a second power supply line extending along the second direction at a boundary between the first pixel and the second pixel, and a reference voltage is applied to the second power supply line; The display panel according to claim 1 .

5. the first pixel and the second pixel share a white subpixel; each of the first sub-pixels includes a first pixel circuit and a first light-emitting region coupled to the first pixel circuit; each of the second sub-pixels includes a second pixel circuit and a second light-emitting region coupled to the second pixel circuit; each of the third sub-pixels includes a third pixel circuit and a third light-emitting region coupled to the third pixel circuit; each of the white sub-pixels includes a fourth pixel circuit and a fourth light-emitting region coupled to the fourth pixel circuit; The display panel according to claim 1 .

6. in each of the n-th row and the n+1-th row, the first to third light-emitting regions of the first pixel and the first to third light-emitting regions of the second pixel are arranged in mirror symmetry, In each of the nth row and the n+1th row, the fourth light-emitting region is disposed between the third light-emitting region of the first pixel and the third light-emitting region of the second pixel in the first direction. The display panel according to claim 5 .

7. a power supply line configured to supply a constant voltage to the pixel circuit; the power supply line is arranged along the second direction and overlaps with the first light-emitting region, the second light-emitting region, and the third light-emitting region; The display panel according to claim 5 .

8. The power supply line is a first power supply wiring to which a pixel driving voltage is applied; second power supply wirings arranged on both sides of the first power supply wiring in the first direction and coupled to each other; Including, The width of the first power supply wiring is greater than the width of each of the second power supply wirings. The display panel according to claim 7 .

9. further comprising a plurality of data line pairs configured to supply data voltages of pixel data to the pixel circuits; the plurality of data line pairs include a first data line pair and a second data line pair; the first data line pair includes a first data line and a second data line, the first data line extending in the second direction and coupled to a plurality of first pixel circuits arranged along the second direction, and the second data line extending in the second direction and coupled to a plurality of second pixel circuits arranged along the second direction; the second data line pair includes a third data line and a fourth data line, the third data line extending in the second direction and connected to a plurality of third pixel circuits arranged along the second direction, and the fourth data line extending in the second direction and connected to a plurality of fourth pixel circuits arranged along the second direction; The display panel according to claim 8 .

10. the fourth pixel circuit further includes a 4-1 pixel circuit coupled to the fourth light-emitting area and a 4-2 pixel circuit coupled to the fourth light-emitting area; the fourth light-emitting region includes a fourth-1 light-emitting region connected to the fourth-1 pixel circuit, and a fourth-2 light-emitting region separated from the fourth-1 light-emitting region and connected to the fourth-2 pixel circuit; The display panel according to claim 9 .

11. a first pixel disposed in the n-th row in the second direction; a second pixel arranged in the n-th row and adjacent to the first pixel in a first direction intersecting the second direction; where n is a real number; each of the first pixel and the second pixel includes first to fourth sub-pixels configured to emit light of different colors; a first pixel and a second pixel different from the first pixel and the second pixel of the nth row are arranged in the n+1th row in the second direction, an n-th gate line is disposed above the first pixel and the second pixel of the n-th row; an (n+1)th gate line is disposed below the first pixel and the second pixel of the nth row; the n-th gate line and the n+1-th gate line are arranged to cross each other at a boundary between the first pixel and the second pixel; Display panel.

12. the n-th gate line and the n+1-th gate line are disposed in different layers; The display panel according to claim 11 .

13. the n-th gate line is electrically connected to each of the first pixels and the second pixels arranged in the n-th row; The (n+1)th gate line is electrically connected to each of the first and second pixels arranged in the (n+1)th row. The display panel according to claim 11 .

14. each of the n-th gate line and the n+1-th gate line overlaps with a second power supply line extending along the second direction at a boundary between the first pixel and the second pixel, and a reference voltage is applied to the second power supply line; The display panel according to claim 11 .

15. a display panel including a plurality of data lines, a plurality of gate lines, a plurality of power supply lines, and a plurality of pixels; a data driver that converts pixel data into a data voltage and supplies the data voltage to the data line; a gate driver for sequentially supplying gate pulses to the gate lines; a timing controller for transmitting the pixel data to the data driver and controlling the data driver and the gate driver; The plurality of pixels include: a first pixel disposed in the n-th row in the second direction; a second pixel arranged in the n-th row and adjacent to the first pixel in a first direction intersecting the second direction; where n is a real number; each of the first pixel and the second pixel includes first to fourth sub-pixels configured to emit light of different colors; a first pixel and a second pixel different from the first pixel and the second pixel of the nth row are arranged in the n+1th row in the second direction, an n-th gate line is connected to each of the first pixel and the second pixel in the n-th row; an n+1th gate line is connected to each of the first pixel and the second pixel in the n+1th row; the n-th gate line and the n+1-th gate line are arranged to cross each other at a boundary between the first pixel and the second pixel; Display device.

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