Semiconductor device

Abstract

To provide a storage device capable of suppressing power consumption, and to provide a semiconductor device using the same.SOLUTION: As a switching element for holding electric charges stored in a transistor that functions as a storage element, a transistor that uses an oxide semiconductor film as an active layer is provided on each memory cell of a storage device. The transistor used as the storage element comprises: a first gate electrode; a second gate electrode; a semiconductor film located between the first gate electrode and the second gate electrode; a first insulating film located between the first gate electrode and the semiconductor film; a second insulating film located between the second gate electrode and the semiconductor film; and a source electrode and a drain electrode contacted with the semiconductor film.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a nonvolatile semiconductor memory device, and to a configuration and driving method of a memory cell for storing data. do. [Background technology]

[0002] Semiconductor memory devices (hereinafter simply referred to as memory devices) include DRAM, which is classified as volatile memory. , SRAM, mask ROM, EPROM, EEPROM, which are classified as non-volatile memory, These include flash memory and ferroelectric memory, which are formed using a single-crystal semiconductor substrate. Many of these memories are already in practical use. Among the above semiconductor memories, flash The memory allows data to be written and erased repeatedly, and can be used without power. It is a non-volatile memory that can retain data, making it highly convenient and resistant to physical shocks. Because of its strength, it is mainly used for portable storage media such as USB memory and memory cards, and It is widely available in

[0003] There are two types of flash memory: NAND type, which has a structure in which multiple memory cells are connected in series, and There are two types of memory cells: one is a NOR type, and the other is a type with a structure in which multiple memory cells are connected in a matrix. Each flash memory has a transistor that functions as a memory element in each memory cell. The transistor that functions as this memory element is called a floating gate. The electrode for storing the electric charge is provided between the gate electrode and the semiconductor film which is the active layer. This allows data storage by charge accumulation on the floating gate.

[0004] The following Patent Documents 1 and 2 disclose floating gates formed on a glass substrate. A thin film transistor having [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Publication No. 6-021478 [Patent Document 2] Japanese Patent Application Laid-Open No. 2005-322899 Summary of the Invention [Problem to be solved by the invention]

[0006] By the way, in nonvolatile memory, the absolute value of the voltage applied to the memory element when writing data is However, it tends to be around 20V, which is generally larger than volatile memory. In the case of flash memory, which can be repeatedly When erasing data, it is necessary to apply a large voltage to the transistor used as the memory element. Therefore, when the flash memory is operating, such as writing or erasing data, The power consumed is high, which is why electronic devices that use flash memory as storage devices This is one of the factors that hinders the reduction of power consumption. When using flash memory in a device, the high power consumption is offset by the drawback of shortening the continuous use time. leads to benefits.

[0007] Although flash memory is non-volatile, data can be lost due to minute leakage of electric charges. Therefore, the current data retention period is said to be about 5 to 10 years. Therefore, there is a demand for a flash memory that can ensure a longer data retention period.

[0008] Furthermore, flash memory cannot be repeatedly written and erased. However, when charges are stored in the floating gate, the gate insulating film is Therefore, the number of times data is rewritten in one memory element is limited to tens of thousands to tens of thousands. The limit is about 10,000 times, and actual flash memory that can withstand more rewrites is The present is desired.

[0009] In view of the above-mentioned problems, the present invention provides a storage device capable of reducing power consumption, Another object of the present invention is to provide a semiconductor device using the same. One of the objects is to provide a memory device capable of storing data and a semiconductor device using the memory device. The present invention also relates to a storage device that can increase the number of times data can be rewritten, One of the objects is to provide a semiconductor device using the device. [Means for solving the problem]

[0010] In one embodiment of the present invention, in addition to a normal gate electrode, a second gate electrode is provided to control the threshold voltage. A nonvolatile memory device is configured by using a transistor provided with an electrode as a memory element. In the memory device, a charge is injected at a high voltage into the floating gate surrounded by an insulating film. Instead of inserting a second transistor, a second transistor is inserted to control the threshold voltage of the transistor used as a memory element. By controlling the potential of the gate electrode of the transistor with extremely low off-state current, That is, a memory device according to one embodiment of the present invention includes at least a transistor whose threshold voltage is controlled by a second gate electrode, and a transistor whose threshold voltage is controlled by the voltage of the second gate electrode a capacitance element for holding the capacitance, and a switching element for controlling the charging and discharging of the capacitance element. The present invention is characterized by being composed of a transistor used as a gate.

[0011] The amount of shift in the threshold voltage of the transistor used as the memory element is determined by the potential of the second gate electrode. The height, more specifically, is controlled by the potential difference between the source electrode and the second gate electrode. The difference in the threshold voltage or the difference in the threshold voltage between the source electrode and the drain electrode The difference in the resistance value between the electrodes corresponds to the difference in the data stored in the memory element.

[0012] The transistor used as the memory element may be an insulated gate field effect transistor. Specifically, a first gate electrode, a second gate electrode, and a first gate electrode and a second gate electrode a semiconductor film located between the first gate electrode and the semiconductor film; an insulating film, a second insulating film located between the second gate electrode and the semiconductor film, and a gate electrode in contact with the semiconductor film; and a source electrode and a drain electrode.

[0013] The transistors used as switching elements are made of silicon, which has a band gap The channel formation region contains a semiconductor material with a wide band and a lower intrinsic carrier density than silicon. The present invention is characterized in that a semiconductor material having the above-mentioned properties is used in a channel forming region. By including the SiO 2 in the region, a transistor with extremely low off-state current can be realized. Suitable semiconductor materials include, for example, silicon, which has a band gap approximately three times larger than that of silicon. , oxide semiconductors, silicon carbide, gallium nitride, and the like.

[0014] Note that oxide semiconductors have high mobility, which can be obtained by using microcrystalline silicon or polycrystalline silicon. It exhibits semiconductor properties, combining high efficiency with uniform device characteristics obtained by amorphous silicon. The metal oxides are electron donors (donors) such as water or hydrogen. The highly purified oxide semiconductor (purified OS) is an i-type (intrinsic semiconductor). The transistor using the oxide semiconductor has an off-state current of Specifically, the oxide semiconductor has a characteristic of being extremely low in moisture or hydrogen. After removing impurities, secondary ion mass spectrometry (SIMS) was performed. Measurement of hydrogen concentration in oxide semiconductors using ion-depletion spectrometry (IEDS) But 5 x 10 19 / cm 3 Less than or equal to 5 x 10 18 / cm 3 Below, more preferably 5×10 17 / cm 3 or less, more preferably 1 × 10 16 / cm 3 The following applies. Also, The carrier density of the oxide semiconductor film that can be measured by Hall effect measurement is 1×10 14 cm - 3 Less than 1 x 10 12 cm -3 Less than 1 × 1, more preferably less than the measurement limit 0 11 cm -3 That is, the carrier density of the oxide semiconductor film is close to zero. The band gap is 2 eV or more, preferably 2.5 eV or more, and more preferably 3 eV or more. eV or more. Highly purified acid with sufficiently reduced impurity concentrations such as water and hydrogen. By using a nitride semiconductor film, the off-state current of a transistor can be reduced.

[0015] Here, analysis of the hydrogen concentration in the oxide semiconductor film and the conductive film will be described. The hydrogen concentration in semiconductor and conductive films is measured using SIMS. It is difficult to obtain accurate data near the sample surface or near the interface between layers of different materials. Therefore, the distribution of hydrogen concentration in the film in the thickness direction was analyzed by SIMS. When analyzing, the values ​​should be almost constant without extreme fluctuations within the range where the target film exists. The average value in the area where the value is obtained is adopted as the hydrogen concentration. When the film thickness is small, the hydrogen concentration in the adjacent film affects the film thickness, and a nearly constant value is obtained. In this case, the hydrogen concentration in the area where the film exists may be The maximum or minimum value of the hydrogen concentration in the film is used as the hydrogen concentration in the film. In the region, there are no mountain-shaped peaks with maximum values ​​or valley-shaped peaks with minimum values. If not, the value at the inflection point is used as the hydrogen concentration.

[0016] Note that moisture or hydrogen as impurities is contained in the oxide semiconductor film formed by sputtering or the like. It has been found that water or hydrogen is contained in large amounts. Therefore, in one embodiment of the present invention, In order to reduce impurities such as moisture or hydrogen in the conductive film, the oxide semiconductor film is Oxygen, oxygen, ultra-dry air (water content is 20 ppm or less, preferably 1 ppm or less, or air with a concentration of 10 ppb or less), or in an atmosphere of rare gas (argon, helium, etc.). Heat treatment is carried out at a temperature of 500°C to 850°C (or the strain point of the glass substrate). It is desirable to carry out the treatment at a temperature of 550°C or higher and 750°C or lower. The heat treatment temperature must not exceed the heat resistance temperature of the substrate used. The effect of desorption by TDS (Thermal Desorption Spectroscopy) This has been confirmed by thermal desorption spectroscopy (thermal desorption spectroscopy).

[0017] Heat treatment is performed using a furnace or rapid thermal annealing (RTA). The TA method uses a lamp light source, and moves the substrate through a heated gas for a short time. The RTA method can reduce the time required for heat treatment to less than 0.1 hours. You can also do this.

[0018] Specifically, the oxide semiconductor film highly purified by the above-described heat treatment was used as an active layer. The transistor has a channel width W of 1×10 6 μm and the channel length L is 10 μm Even if the device is a semiconductor, the voltage between the source and drain electrodes (drain voltage) is between 1V and 10V. In the range, the off-state current (the drain current when the voltage between the gate electrode and source electrode is 0 V) current) is below the measurement limit of the semiconductor parameter analyzer, i.e., 1×10 -13 Below A Therefore, the off-state current is divided by the channel width of the transistor, The off-state current density corresponding to the numerical value is 100 zA / μm or less. A highly purified oxide semiconductor film is used as a switching element for storing the charge in the capacitor. Using a transistor with a gate insulating film thickness of 100 nm, The off-state current of the transistor was measured from the change in the amount of charge per transistor. When the voltage between the source electrode and the drain electrode is 3V, the current is 10zA / μm to 100zA / μm It was found that an even lower off-state current of 1000 m can be obtained. In the memory device according to the present invention, a transistor using a highly purified oxide semiconductor film as an active layer is The off-state current density is 100 zA / μm or less, preferably 10 zA / μm or less, and more preferably Therefore, it is possible to utilize a highly purified oxide semiconductor film. The transistor using the conductive layer is an on-state transistor when the voltage between the gate electrode and the source electrode is 0 or less. The current is significantly lower than that of a transistor using crystalline silicon.

[0019] In addition, a transistor using a highly purified oxide semiconductor has almost no temperature dependence of its off-state current. This is because impurities that act as electron donors in oxide semiconductors are removed. By purifying the oxide semiconductor, the conductivity type becomes as close as possible to the intrinsic type, and This is because the Luminescence level is located in the center of the forbidden band. This is also due to the fact that the energy gap is 3 eV or more and there are very few thermally excited carriers. In addition, the fact that the source electrode and the drain electrode are in a degenerated state is also a factor that causes no temperature dependency. The transistor operates by injecting electrons from the degenerated source electrode into the oxide semiconductor. Since most of the carrier density is independent of temperature, This can explain why the off-current does not exhibit temperature dependence.

[0020] The oxide semiconductor is an In-Sn-Ga-Zn-O-based oxide semiconductor, which is a quaternary metal oxide. Conductors, ternary metal oxides such as In-Ga-Zn-O oxide semiconductors, In-Sn-Z nO-based oxide semiconductors, In-Al-Zn-O-based oxide semiconductors, Sn-Ga-Zn-O-based Oxide semiconductors, Al-Ga-Zn-O oxide semiconductors, Sn-Al-Zn-O oxide semiconductors Conductors, binary metal oxides such as In-Zn-O oxide semiconductors and Sn-Zn-O oxides semiconductors, Al-Zn-O oxide semiconductors, Zn-Mg-O oxide semiconductors, Sn-Mg -O-based oxide semiconductors, In-Mg-O-based oxide semiconductors, In-Ga-O-based oxide semiconductors, In-O based oxide semiconductors, Sn-O based oxide semiconductors, Zn-O based oxide semiconductors, etc. In this specification, for example, an In—Sn—Ga—Zn—O system Oxide semiconductors are made of indium (In), tin (Sn), gallium (Ga), and zinc (Zn). The stoichiometric composition ratio is not particularly limited. The oxide semiconductor may contain silicon.

[0021] Alternatively, the oxide semiconductor may have the chemical formula InMO3(ZnO) m (m>0) Here, M represents one or more metal elements selected from Ga, Al, Mn, and Co. vinegar. [Effects of the Invention]

[0022] The transistor with low off-state current is used as a switch for holding charge stored in a memory element. By using it as a switching element, it is possible to prevent leakage of charges from the memory element. The present invention provides a memory device capable of storing data for a long period of time and a semiconductor device using the memory device. It can be provided.

[0023] The voltage required to write and read data to the memory element is controlled by the switching element. This is largely determined by the operating voltage of the transistor that functions as a A storage device capable of significantly lowering the operating voltage and reducing power consumption, It is possible to provide a semiconductor device using the device.

[0024] In addition, the degradation of the gate insulating film caused by tunnel current is suppressed compared to conventional flash memory. Therefore, a storage device that can increase the number of times data can be rewritten, Therefore, it is possible to provide a semiconductor device having such a structure. [Brief explanation of the drawings]

[0025] [Figure 1] FIG. 2 is a diagram showing the configuration of a memory cell. [Figure 2] FIG. 1A is a diagram illustrating the configuration of a memory element, and FIG. 1B is a diagram illustrating its operation. [Figure 3] FIG. 2 is a diagram showing the configuration of a memory cell. [Figure 4] FIG. 2 is a diagram showing the configuration of a memory cell. [Figure 5] FIG. 2 is a diagram showing the configuration of a cell array. [Figure 6] FIG. 2 is a diagram showing the configuration of a cell array. [Figure 7] 1 is a timing chart showing a method of driving a memory device. [Figure 8] FIG. 1 is a diagram showing the configuration of a storage device. [Figure 9] FIG. 2 is a diagram showing the configuration of a readout circuit. [Figure 10] 1A to 1C are cross-sectional views of a memory cell, illustrating a method for manufacturing a memory device. [Figure 11] FIG. [Figure 12] FIG. 10 is a longitudinal cross-sectional view of an inverted staggered transistor including an oxide semiconductor. [Figure 13] Energy band diagram (schematic diagram) along the line A-A' shown in FIG. [Figure 14] (A) shows the state where a positive voltage (VG>0) is applied to the gate electrode (GE), and (B) shows the state where a negative voltage (VG<0) is applied to the gate electrode (GE). [Figure 15]A diagram showing the relationship between the vacuum level, the work function of a metal (φM), and the electron affinity of an oxide semiconductor (χ). [Figure 16] FIG. 2 is a diagram showing the configuration of a storage medium. [Figure 17] FIG. 1 illustrates a configuration of an electronic device. [Figure 18] FIG. 2 is a diagram showing the configuration of a measurement circuit. [Figure 19] FIG. 10 is a diagram showing measurement results (a diagram showing the relationship between elapsed time Time and output potential Vout). [Figure 20] 1 is a graph showing measurement results (a graph showing the relationship between source-drain voltage V and off-state current I). [Figure 21] 1 is a timing chart showing a method of driving a memory device. DETAILED DESCRIPTION OF THE INVENTION

[0026] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The present invention is not limited to the following description, and the embodiments and aspects thereof may be modified without departing from the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that various modifications may be made to the details. However, the present invention should not be construed as being limited to the description of the following embodiments.

[0027] In addition, integrated circuits such as microprocessors and image processing circuits, RF tags, storage media, and semiconductors Any and all semiconductor devices that can use memory devices, such as display devices, can be used in the present invention. The semiconductor display devices include liquid crystal display devices and organic light emitting diode (OLED) devices. Light-emitting devices with light-emitting elements, such as those represented by l Micromirror Device), PDP (Plasma Display) Panel), FED (Field Emission Display), etc. The category includes semiconductor display devices that have circuit elements using a semiconductor film in the pixel section or drive circuit. Included in.

[0028] (Embodiment 1) FIG. 1A shows an example of a circuit diagram of a memory cell, which is the minimum unit of a memory device of the present invention. The memory cell 100 shown in FIG. 1A includes a transistor 101 functioning as a memory element and a , the supply of a potential to the second gate electrode of the transistor 101 can be controlled. The memory cell 100 also includes a transistor 102 that functions as an switching element. A capacitor 103 for holding the potential of the second gate electrode of the transistor 101 is provided. It may be possible to do so.

[0029] The memory cell 100 may include other elements such as diodes, resistors, and inductors as needed. The circuit may further include other circuit elements.

[0030] The transistor 101 functioning as a memory element has a first gate electrode and a second gate electrode. a semiconductor film located between the first gate electrode and the second gate electrode; a first insulating film located between the gate electrode and the semiconductor film; and a second insulating film located between the gate electrode and the semiconductor film. The transistor has a second insulating film, and a source electrode and a drain electrode in contact with the semiconductor film. The first gate electrode, the second gate electrode, the source electrode, and the drain electrode of the gate electrode 101 are provided with a Various operations of the memory device can be controlled by the potential.

[0031] The transistor 102 that functions as a switching element has a band gap larger than that of silicon. The channel formation region contains a semiconductor material with a wide band and a lower intrinsic carrier density than silicon. By using such a semiconductor material for the channel formation region of the transistor 102, This is because the off-state current can be sufficiently reduced.

[0032] A semiconductor with a wider band gap than silicon semiconductors and a lower intrinsic carrier density than silicon. Examples of conductive materials include compound semiconductors such as silicon carbide (SiC) and gallium nitride (GaN). and oxide semiconductors made of metal oxides such as zinc oxide (ZnO). Among these, oxide semiconductors can be produced by sputtering or wet methods (printing, etc.). The process temperature for silicon carbide is approximately The process temperature for gallium nitride is about 1100°C, while the process temperature for oxide semiconductor deposition is about 1500°C. The temperature is low, 300 to 500°C (below the glass transition temperature, up to about 700°C), and it is inexpensive. It is possible to form a film on a glass substrate, which is readily available, and it can be heated to temperatures of 1500 to 2000°C. An oxide semiconductor is formed on an integrated circuit using a semiconductor material that does not have resistance to high-temperature heat treatment. It is also possible to stack semiconductor elements by using this method. Therefore, among the wide-gap semiconductors mentioned above, oxide semiconductors are particularly suitable for mass production. It also has the advantage of improving transistor performance (e.g., field-effect mobility). Even when trying to obtain a crystalline oxide semiconductor, the temperature must be between 450 and 800°C. A crystalline oxide semiconductor can be easily obtained by the treatment.

[0033] In the following description, the semiconductor film of the second transistor 102 will be described. The case where an oxide semiconductor is used is given as an example.

[0034] In FIG. 1A, the memory cell 100 is a transistor that functions as a switching element. Although a configuration having only one controller 102 is shown, the present invention is not limited to this configuration. In one embodiment, each memory cell has at least one transistor that functions as a switching element. It is sufficient to provide one transistor, and the number of the transistors may be plural. When the 00 has a plurality of transistors functioning as switching elements, The transistors may be connected in parallel, in series, or in both series and Parallel connections may also be combined.

[0035] The state in which the transistors are connected in series is when the source electrode of the first transistor and drain electrodes of the second transistor. Also, when transistors are connected in parallel, The state in which the source electrode of the first transistor is connected to the source voltage of the second transistor is The drain electrode of the first transistor is connected to the drain electrode of the second transistor. This means that the device is connected to

[0036] The transistor 102 functioning as a switching element may also function as a memory element. Unlike transistor 101, if the transistor has a gate electrode on only one side of the active layer, However, the present invention is not limited to this configuration, and a transistor that functions as a switching element may be used. Like a transistor that functions as a memory element, a resistor also has an active layer sandwiched between them. A pair of gate electrodes may be provided.

[0037] In one embodiment of the present invention, at least a transistor functioning as a switching element 102 has only to have the above-mentioned wide-gap semiconductor material in the active layer. An oxide semiconductor film is used for an active layer of the transistor 101 that functions as a memory element. Alternatively, an oxide semiconductor may be used for the active layer of the transistor 101 that functions as a memory element. Other than amorphous, microcrystalline, polycrystalline, or single crystalline silicon, or germanium, etc. However, the semiconductors of all the transistors in the memory cell 100 may be used. By using an oxide semiconductor film for the active layer, the process can be simplified.

[0038] Next, the transistor 101 and the transistor The connection relationship between the capacitor 102 and the capacitor element 103 will be described.

[0039] The gate electrode of the transistor 102 is connected to the write word line WL. In the transistor 102, either one of the source electrode and the drain electrode is connected to the input data. The other end is connected to the second gate electrode of the transistor 101. The first gate electrode of the transistor 101 is connected to a read word line RL. The transistor 101 has either a source electrode or a drain electrode. One is connected to the output data line Dout, and the other is given a fixed potential such as ground. It is connected to the power line.

[0040] One of the pair of electrodes of the capacitor 103 is connected to the second gate of the transistor 101. One end is connected to an electrode, and the other end is connected to a power line that is given a fixed potential such as ground. It has been done.

[0041] In this specification, connection means electrical connection, and the current, voltage, or potential Therefore, the connected state corresponds to the state in which the signal is directly connected. It does not necessarily refer to the state of being connected, but rather to the state in which a current, voltage, or potential is available or is transmitted through circuit elements such as wires, resistors, diodes, and transistors. This also includes situations where the connection is indirectly made via a direct connection.

[0042] Also, even if components that are independent on the circuit diagram are connected, For example, when a part of the wiring also functions as an electrode, one conductive film is connected to a plurality of components. In this specification, the term "connection" refers to such a single The case where the conductive film has the functions of multiple components is also included in this category.

[0043] The source electrode and the drain electrode of the transistor are connected to each other. The name changes depending on the difference in potential applied to the electrodes. Generally, n-channel In a transistor, the electrode to which a low potential is applied is called the source electrode, and the electrode to which a high potential is applied is called the The electrode that is connected to the drain is called the drain electrode. The electrode to which a low potential is applied is called the drain electrode, and the electrode to which a high potential is applied is called the source electrode. In this specification, for convenience, it is assumed that the source electrode and the drain electrode are fixed. In some cases, the connection relationship of the transistors is explained using the above potential relationship. This means that the names of the source and drain electrodes are interchangeable.

[0044] In FIG. 1A, the transistor 102 has a gate electrode on only one side of the active layer. The transistor 102 has a pair of gates sandwiching an active layer. When the memory cell has electrodes, one of the gate electrodes is connected to a write word line WL, and the other The gate electrode may be in a floating state where it is electrically insulated, or may be in a state where the potential is In the latter case, the pair of electrodes may be provided with the same potential. Alternatively, a fixed potential such as ground may be applied to only the other gate electrode. By controlling the level of the potential applied to the other gate electrode, The threshold voltage of 102 can be controlled.

[0045] Next, FIG. 1B shows a cross section of the memory cell 100 having the circuit configuration shown in FIG. 1A. An example of the memory cell shown in FIG. 1B is a transistor functioning as a memory element. A transistor 101 and a transistor 102 functioning as a switching element have insulating surfaces. It is formed on a substrate 110 .

[0046] Specifically, the transistor 101 includes a first gate electrode 111 formed on a substrate 110 having an insulating surface. 121, the insulating film 112 on the first gate electrode 121, and the first gate electrode 121 with the insulating film 112 sandwiched therebetween. The oxide semiconductor film 123 functions as an active layer and overlaps the gate electrode 121. The source electrode 124 and the drain electrode 125 on the conductive film 123, the oxide semiconductor film 123, and the The insulating film 116 on the source electrode 124 and the drain electrode 125, and the oxide film on the insulating film 116 The second gate electrode 126 overlaps the nitride semiconductor film 123. The insulating film 117 is formed on the gate electrode 126 of the transistor 101. 117 may be included as a component.

[0047] The transistor 102 includes a gate electrode 111 and a gate insulating film 112 formed over a substrate 110 having an insulating surface. The insulating film 112 on the gate electrode 111 and the insulating film 112 overlapping the gate electrode 111 are sandwiched between the insulating film 112 and the gate electrode 111. The oxide semiconductor film 113 functions as an active layer, and the source The oxide semiconductor film 113 has a source electrode 114 and a drain electrode 115. An insulating film 116 is formed on the gate electrode 14 and the drain electrode 115, and the transistor 102 The insulating film 116 may be included as a component.

[0048] The capacitor 103 is connected to the source electrode 124 of the transistor 101 and the second gate electrode 126 are formed in an area where they overlap with the insulating film 116 sandwiched therebetween.

[0049] Next, the operation of a transistor functioning as a memory element will be described with reference to FIG. Let us take the case where the master 101 is an n-channel type and handles binary data as an example. Note that FIG. 2A shows a circuit diagram of the transistor 101, and the first gate The potential of the first gate electrode is Vcg, the potential of the second gate electrode is Vbg, the potential of the source electrode is Vs, and the potential of the drain electrode is Vs. The potential of the gate electrode is represented as Vd, and the potential of each electrode of the transistor 101 is represented.

[0050] First, the operation of the transistor 101 during data writing will be described. When the transistor 101 is turned on, a threshold voltage V The threshold voltage Vth0 is equal to or lower than the second threshold voltage Vth0. When the gate electrode potential Vbg is equal to the ground potential Vgnd, the transistor 10 This corresponds to the threshold voltage of 1. Specifically, the first gate electrode and the source electrode The relationship of the potentials is Vcg-Vs≦Vth0. When the transistor is turned on, it is off and the drain electrode is in a high impedance state.

[0051] When writing data, the potential Vbg of the second gate electrode is set to the value of When handling binary data, the second gate electrode has a height controlled by the value of the gate electrode. , either a high potential Vdd or a low potential Vss is given. The relationship between these potentials is as follows: For example, when the potential Vbg of the second gate electrode is a low potential, When Vss=Vgnd is set, the threshold voltage of transistor 101 remains at Vth0. On the other hand, when the potential Vbg of the second gate electrode is set to a high potential Vdd, The threshold voltage of the transistor 101 shifts to the negative side and becomes Vth1.

[0052] In this embodiment, the case where the low potential Vss=Vgnd during writing is taken as an example. As mentioned above, the low potential Vss does not necessarily have to be equal to the ground potential Vgnd. For example, Vdd>Vss>Vgnd may be used. However, in this case, the threshold voltage The shift amount is the value when the potential Vbg of the second gate electrode is set to the high potential Vdd. It is assumed to be smaller than the amount of shift in the threshold voltage.

[0053] Next, the operation of the transistor 101 when data is held will be described. In this state, the transistor 102 functioning as a switching element is off. Since the off-state current of the transistor 102 is extremely low, the potential Vbg of the second gate electrode is , the height set at the time of writing is maintained.

[0054] Next, the operation of the transistor 101 when reading data will be described. At the time of discharge, the transistor 101 has a threshold voltage Vth between the first gate electrode and the source electrode. A voltage higher than Vth1 and lower than Vth0 is applied.

[0055] In the immediately preceding data write, the threshold voltage of the transistor 101 is When Vth1 is set, the voltage between the first gate electrode and the source electrode is equal to or greater than the threshold voltage V When the voltage becomes higher than th1, the transistor 101 is turned on, and the source electrode and the drain electrode The resistance between the electrodes decreases. Therefore, the potential Vs of the source electrode is applied to the drain electrode. On the other hand, when the data was written immediately before, the threshold voltage of the transistor 101 was When Vth0 is set, the voltage between the first gate electrode and the source electrode is equal to or greater than the threshold voltage V Even if the voltage becomes higher than th1, if it is lower than the threshold voltage Vth0, the transistor 101 is turned off. Therefore, the resistance between the source electrode and the drain electrode is high, and the voltage of the drain electrode remains low. The terminal Vd remains in a high impedance state.

[0056] Therefore, the potential Vd of the drain electrode is the second potential Vd at the time of the immediately preceding data write. The voltage applied to the gate electrode of the The relationship between the potential Vcg of the first gate electrode and the drain current Id of the transistor 101 is expressed as follows: The line 130 shows the relationship between the potential Vcg and the drain when the threshold voltage is set to Vth1. The line 131 shows the relationship between the current Id and the threshold voltage Vth0. 2(B) shows the relationship between the potential Vcg and the drain current Id. The voltage between the gate electrode and the source electrode is higher than the threshold voltage Vth1 and lower than the threshold voltage Vth0. When the threshold voltage is set to a potential Vread lower than Vth1, the line 130 and the line 131 indicate that the threshold voltage is Vth1. The drain current Id1 obtained when the threshold voltage is Vth0 is Therefore, the drain current Id or the drain electrode potential Vd By reading the value of , you can understand the value of the written data.

[0057] In this embodiment, the voltage between the first gate electrode and the source electrode during reading is , the case where the threshold voltage is higher than the threshold voltage Vth1 and lower than the threshold voltage Vth0 has been described. The present invention is not limited to this configuration. The voltage does not necessarily have to be equal to or lower than the threshold voltage Vth0. When writing data, the threshold voltage of the transistor 101 is set to Vth1. In this case, when reading, the voltage between the first gate electrode and the source electrode is equal to or lower than the threshold voltage Vth0 When the voltage is higher, the transistor 101 is turned on and the resistance between the source and drain electrodes is At this time, the resistance between the source electrode and the drain electrode is Rds0. When data was previously written, the threshold voltage of the transistor 101 was Vth0. When set, the voltage between the first gate electrode and the source electrode is below the threshold during reading. When the voltage Vth0 is higher than the threshold voltage Vth0, the transistor 101 is turned on and the voltage between the source electrode and the drain electrode The resistance value between the electrodes decreases. At this time, the resistance value between the source electrode and the drain electrode is defined as Rds1 and. And at least when the threshold voltage is set to Vth1, by operating the transistor 101 in the saturation region, when reading, the transistor 101, regardless of whether it is on at the threshold voltage setting of either Vt h1 or Vth0, can have a difference such that the resistance value between the source electrode and the drain electrode is Rds0 < Rds1. Specifically when the voltage between the first gate electrode and the source electrode is Vgs and the voltage Vds between the source electrode and the drain electrode is considered, in the range where |Vds| > |Vgs - Vth0| is satisfied, the tra nsistor 101 may be operated. By having a difference such that the resistance value between the source electrode and the drain electrode is Rds0 < Rds1, even when the voltage between the first gate electrode and the source electrode during reading is higher than the threshold voltage Vth0, the potential Vd of the drain electrode can be made to联动 with the height of the potential applied to the second gate electrode during the writing of the immediately preceding data . For example, as shown in Fig. 2(B), when the voltage between the first gate electrode and the source electrode is set to a potential Vread' higher than the threshold voltage Vth0, from line 130 and line 131, the drain current Id1' obtained when the threshold voltage is Vth1 becomes higher than the drain current Id0' obtained when the threshold voltage is Vth0. Therefore, by reading the value of the drain current Id or the potential Vd of the drain electrode, the value of the written data can be grasped. <000057 ... (the text seems to be cut off here, but following the rules, the tags are preserved as is)

[0058] Next, the operation of the transistor of 101 at the time of data erasure will be described. At the time of erasure the transistor 101, similar to the time of data writing, has the first gate electrode and the sourceIt should be noted that there seems to be some text cut off in the original, but the translation is done according to the provided rules. Also, the term "联动" is directly translated as it is not clear what the exact intended meaning is in this context. You may need to further clarify the original text for a more accurate translation. A voltage equal to or lower than the threshold voltage Vth1 is applied between the gate electrodes. The relationship between the potentials of the first gate electrode and the source electrode during erasure is Vcg-Vs≦Vth1 Therefore, the transistor 101 is off during erasure, and the drain electrode is high. When erasing data, the potential of the second gate electrode is The potential Vbg is set to a fixed potential such as ground, and the threshold voltage of the transistor 101 is V It is set to th0.

[0059] In this embodiment, a method for driving a memory device that erases written data will be described. However, the present invention is not limited to this configuration. Unlike flash memory, one of its advantages is that it does not require an erase operation. For example, it is possible to write new data to overwrite previously written data. is.

[0060] In general, flash memory stores electric charge when writing data. The floating gate is covered with an insulating film and is in an insulating state. To store charge in the gate using the tunnel effect, a high voltage of about 20 V must be applied. However, in one embodiment of the present invention, a highly purified oxide semiconductor The transistor using the semiconductor film as the active layer of the transistor enables writing and reading of data. Therefore, the voltage required for the memory device to operate is only a few volts. This allows for significantly reduced power consumption. and a transistor used as a memory element of a memory device according to one embodiment of the present invention. The structure and driving method are different from those of the transistors currently used, so the It is difficult to accurately grasp the difference in power consumption during operation from the voltage. When comparing power consumption only when writing data, one aspect of the present invention In the memory device according to the present invention, a voltage of 5 V applied between the second gate electrode and the source electrode is sufficient. On the other hand, in normal flash memory, floating To store charge in the gate and write data, a gate electrode is placed between the gate and source electrodes. , a voltage of at least 16V is required. The power consumed by the transistor is It corresponds to the square of the transistor gate voltage divided by the transistor load resistance. Therefore, the power consumption of the storage device according to one embodiment of the present invention is approximately the same as that of a normal flash memory. Therefore, the power consumption during writing is about 10% of the power consumption during writing. This shows that the power consumption during operation can be significantly reduced.

[0061] In a semiconductor device using a general flash memory, Because the required voltage (operating voltage) is high, a voltage boost circuit is usually used to However, in the memory device according to one embodiment of the present invention, the operation of the memory device is Since the operating voltage can be kept low, power consumption can be reduced. This reduces the load on external circuits, such as boost circuits, involved in the operation of the storage device. This allows for the functionality of external circuits to be expanded, thereby enabling the semiconductor device to have higher performance. In addition, the operating voltage of the memory device can be kept low, which makes it possible to cover the large operating voltage. This eliminates the need for redundant circuit design for the purpose of reducing the integration density of integrated circuits used in semiconductor devices. This can improve the performance of the semiconductor device.

[0062] In this embodiment, a driving method for handling binary digital data has been described. However, the storage device of the present invention can also handle multi-valued data with three or more values. When handling multi-value data, when writing data, the potential V of the second gate electrode The value of the threshold voltage is determined by the voltage of the second gate electrode. The potential Vbg of the second gate electrode is controlled by the above-mentioned configuration. The threshold voltage can be set to three or more levels depending on the level of bg. The difference in drain current due to the difference in thickness, or the difference in source voltage due to the difference in threshold voltage The difference in resistance between the source and drain electrodes is used to read out multi-value data. As another method, it is possible to set the threshold voltage higher than each level in advance according to each level of the threshold voltage. A slightly higher voltage is prepared and applied to the first gate electrode to generate a threshold voltage. For example, when reading out four-level data, four levels of Four voltages slightly higher than the threshold voltages (Vth0, Vth1, Vth2, Vth3) Prepare the voltages (Vread0, Vread1, Vread2, Vread3) in advance. By reading four times using four voltages, four levels of data can be read. The above configuration makes it possible to increase the storage capacity of the storage device while keeping the area small.

[0063] In the case of multi-value data with three or more values, as the number of values ​​increases to four or five, the values ​​are Since the difference between the threshold voltages of the first and second gate electrodes becomes small, if a small amount of off-current exists, the voltage of the second gate electrode Data is becoming increasingly difficult to maintain and retention periods are becoming shorter. However, in one embodiment of the present invention, the off-state current can be reduced by using a highly purified oxide semiconductor film. Since transistors with significantly reduced current are used as switching elements, silicon is not used. Therefore, the effect of preventing off-current is higher than that of the conventional transistor. This can prevent the shortening of the time.

[0064] In addition, in FIG. 1B, the transistor 102 functioning as a switching element is 1 shows a bottom-gate type device having an oxide semiconductor film 113 over an electrode 111. However, the transistor 102 is not limited to a bottom gate type. It is sufficient to use an oxide semiconductor film as an active layer. For example, a gate electrode may be formed on an oxide semiconductor film. The transistor 102 may be a top-gate type having a source electrode 114. and a drain electrode 115 is formed on the oxide semiconductor film 113. Without being limited thereto, the oxide semiconductor film 113 is formed on the source electrode 114 and the drain electrode 115. The transistor 102 may be a bottom contact type in which the source electrode The oxide semiconductor film 113 overlaps the insulating film 116 between the gate electrode 114 and the drain electrode 115. The thickness of the channel etched type is thinner than that of other portions, but the present invention is not limited to this configuration. The planarization during etching for forming the source electrode 114 and the drain electrode 115 is not specified. In order to prevent damage due to noise and film loss due to etching, the source electrode 114 and the drain electrode A channel protective film is provided on the oxide semiconductor film 113 between the drain electrodes 115. It may be of a protection type.

[0065] FIG. 3A is a cross-sectional view of a memory cell 100 having the circuit configuration shown in FIG. The memory cell shown in FIG. 3A is a channel-protection transistor that functions as a memory element. a channel protection transistor 101 functioning as a switching element; 2 is formed on a substrate 140 having an insulating surface.

[0066] Specifically, the transistor 101 includes a first gate electrode 140 formed on a substrate 140 having an insulating surface. 151, an insulating film 142 on the first gate electrode 151, and a first gate electrode 152 with the insulating film 142 sandwiched therebetween. The oxide semiconductor film 153 functions as an active layer and overlaps the gate electrode 151. A channel protection film 157 overlapping the gate electrode 151 on the conductive film 153, and an oxide semiconductor The source electrode 154 and the drain electrode 155 on the oxide semiconductor film 153, the the insulating film 146 on the panel protective film 157, the source electrode 154 and the drain electrode 155, and the insulating film 146 on the a second gate electrode 156 that is over the oxide semiconductor film 146 and overlaps with the oxide semiconductor film 153; Moreover, an insulating film 147 is formed on the second gate electrode 156, and the transistor The resistor 101 may include an insulating film 147 as a component.

[0067] The transistor 102 includes a gate electrode 141 and a gate insulating film 142 over a substrate 140 having an insulating surface. The insulating film 142 on the gate electrode 141 and the insulating film 142 overlapping the gate electrode 141 are sandwiched between the insulating film 142 and the gate electrode 141. The oxide semiconductor film 143 functions as an active layer, and the channel on the oxide semiconductor film 143 The protective film 148 and the source electrode 144 and the drain electrode 145 on the oxide semiconductor film 143 are The oxide semiconductor film 143, the channel protective film 148, the source electrode 144, and An insulating film 146 is formed on the drain electrode 145, and the transistor 102 is 146 may be included as a component.

[0068] The capacitor 103 is connected to the source electrode 154 of the transistor 101 and the second gate electrode 156 are formed in an area where they overlap with the insulating film 146 sandwiched therebetween.

[0069] The channel protection film 157 and the channel protection film 148 are formed by a method such as plasma CVD or thermal CVD. It can be formed by chemical vapor deposition or sputtering. The film 157 and the channel protection film 148 are made of inorganic materials containing oxygen (silicon oxide, silicon oxynitride, It is desirable to use an inorganic material containing oxygen as the channel protection film 15. 7, by using it as the channel protective film 148, the oxide semiconductor film 153, the oxide semiconductor film 14 3. It is assumed that oxygen deficiency occurred due to heat treatment to reduce the moisture or hydrogen in Also, the oxide semiconductor film 153, at least the channel protective film 157 of the oxide semiconductor film 143, Oxygen is supplied to the regions in contact with the channel protective film 148, and oxygen vacancies that become donors are reduced. Therefore, it is possible to reduce the amount of the stoichiometric composition of the channel formation region. The region can be made i-type or substantially i-type, and the transistor voltage drop due to oxygen vacancies can be reduced. This reduces variations in electrical characteristics and improves electrical characteristics.

[0070] The channel formation region is a region of the semiconductor film that is adjacent to the gate electrode with the gate insulating film sandwiched therebetween. In the case of a transistor used as a memory element, the semiconductor film A first gate electrode is disposed between the source electrode and the drain electrode, with a gate insulating film sandwiched therebetween. Or it corresponds to the region overlapping with the second gate electrode.

[0071] Next, FIG. 3B shows a cross section of the memory cell 100 having the circuit configuration shown in FIG. The memory cell shown in FIG. 3B has a bottom contact that functions as a memory element. a bottom-contact type transistor 101 that functions as a switching element; The transistor 102 is formed on a substrate 160 having an insulating surface.

[0072] Specifically, the transistor 101 includes a first gate electrode 161 formed on a substrate 160 having an insulating surface. 171, an insulating film 162 on the first gate electrode 171, and a source electrode 1 on the insulating film 162. 74 and the drain electrode 175 overlap with the first gate electrode 171 with the insulating film 162 sandwiched therebetween. The active layer is in contact with the source electrode 174 and the drain electrode 175. The oxide semiconductor film 173, the source electrode 174, and the drain electrode The insulating film 166 on the electrode 175 overlaps with the oxide semiconductor film 173 on the insulating film 166. The second gate electrode 176 has an insulating layer. The insulating film 167 is formed on the transistor 101, and the insulating film 167 is included as a component of the transistor 101. is also good.

[0073] The transistor 102 includes a gate electrode 161 and a gate insulating film 162 over a substrate 160 having an insulating surface. An insulating film 162 on the gate electrode 161, a source electrode 164 on the insulating film 162, and a drain electrode The electrode 165 overlaps the gate electrode 161 with the insulating film 162 sandwiched therebetween, and the source electrode 164 and the drain electrode 165. The oxide semiconductor film 16 functions as an active layer. 3. The oxide semiconductor film 163, the source electrode 164, and the drain electrode 165 An insulating film 166 is formed on the transistor 102. The insulating film 166 is a component of the transistor 102. It may contain.

[0074] The capacitor 103 is connected to the source electrode 174 of the transistor 101 and the second gate electrode 176 are formed in an area where they overlap with the insulating film 166 sandwiched therebetween.

[0075] In addition, in FIGS. 1A, 3A, and 3B, a transistor functioning as a memory element The active layer 101 is an oxide semiconductor film. As described above, the active layer of the transistor 101 may be made of an amorphous, microcrystalline, polycrystalline, or other material other than an oxide semiconductor. Alternatively, a semiconductor such as single crystal silicon or germanium may be used.

[0076] FIG. 4A shows a structure in which an active layer of a transistor 101 functioning as a memory element contains silicon. A cross-sectional view of a memory cell 100 using a semiconductor film is shown as an example. The memory cell shown in FIG. 1 includes a transistor 101 functioning as a memory element, a switching element, and a The transistor 102 that functions as a transistor 103 is formed on a substrate 200 having an insulating surface. .

[0077] Specifically, the transistor 102 includes a gate electrode 211 formed on a substrate 200 having an insulating surface. The insulating film 230 on the gate electrode 211 and the insulating film 230 on the gate electrode 211 are sandwiched between the insulating film 230 and the gate electrode 211. The oxide semiconductor film 213 functions as an active layer and overlaps the oxide semiconductor film 213. The oxide semiconductor film 213 has a source electrode 214 and a drain electrode 215. An insulating film 231 is formed on the electrode 214 and the drain electrode 215, and the transistor The insulating film 231 may be included in the component of the film 102.

[0078] The transistor 101 includes an insulating film 231 formed on a substrate 200 having an insulating surface. On the top, a first gate electrode 221, an insulating film 212 on the first gate electrode 221, and an insulating film 212 is sandwiched between the first gate electrode 221 and the active layer 222. a semiconductor film 223, a source electrode 224, a drain electrode 225 on the semiconductor film 223, , the insulating film 216 on the semiconductor film 223, the source electrode 224 and the drain electrode 225, and the insulating and a second gate electrode 226 on the film 216 overlapping the semiconductor film 223. Moreover, an insulating film 217 is formed on the second gate electrode 226, 101 may include an insulating film 217 as a component.

[0079] The capacitor 103 is connected to the drain electrode 225 of the transistor 101 and the second gate electrode 226. The electrode 226 is formed in an overlapping region with the insulating film 216 sandwiched therebetween.

[0080] Next, as shown in FIG. 4B, a silicon layer is formed on the active layer of the transistor 101 that functions as a memory element. 4 shows a cross-sectional view of a memory cell 100 using a semiconductor film containing silicon. The memory cell shown in FIG. 1B includes a transistor 101 functioning as a memory element and a switching transistor 102. A transistor 102 functioning as a gate element is formed on a substrate 270 having an insulating surface. It is being done.

[0081] Specifically, the transistor 102 has a gate electrode 244 formed on an insulating film 247 formed on a substrate 270. The electrode 241, the insulating film 260 on the gate electrode 241, and the gate electrode 241 with the insulating film 260 sandwiched therebetween The oxide semiconductor film 243 overlaps the electrode 241 and functions as an active layer. The oxide semiconductor film 2 has a source electrode 244 or a drain electrode 245 on the oxide semiconductor film 2. 43, an insulating film 261 is formed on the source electrode 244 and the drain electrode 245; The transistor 102 may include an insulating film 261 as a component.

[0082] The transistor 101 also includes a first gate electrode 251 and a first gate The insulating film 242 is disposed on the first gate electrode 251, and the insulating film 242 is disposed between the first gate electrode 251 and the second gate electrode 251. A semiconductor film 253 that functions as an active layer using silicon is overlapped with the semiconductor film 253. The source electrode 254, the drain electrode 255, and the semiconductor film 253, the source electrode 254, and the drain electrode 255 are The insulating film 246 on the inner electrode 255 overlaps with the semiconductor film 253 on the insulating film 246. The second gate electrode 256 has an insulating layer. The insulating film 247 is formed, and the transistor 101 includes the insulating film 247 as a component. is also good.

[0083] The capacitor 103 is connected to the drain electrode 255 of the transistor 101 and the second gate electrode 256 of the transistor 101. The electrode 256 is formed in the overlapping region with the insulating film 246 sandwiched therebetween.

[0084] Note that the transistors 101 shown in FIGS. 4A and 4B are both bottom-gate transistors. Although a case is shown as an example, it may be a top gate type or a bottom contact type. The transistor 101 is a channel-etched type, but has a channel protection. The transistor 102 shown in both FIG. 4A and FIG. 4B may be a Although a bottom gate type is shown as an example, a top gate type or a bottom gate type may also be used. The transistor 102 may be a channel-etched type. However, it may be a channel protection type.

[0085] (Embodiment 2) In this embodiment, an example of a configuration of a memory device having a plurality of memory cells and a driving method thereof will be described. We will explain about this.

[0086] FIG. 5 shows a cell of a NOR type memory device in which a plurality of memory cells 300 are connected in a matrix. A circuit diagram of a memory cell array is shown as an example. This configuration is the same as that of the memory cell 100 described in the first embodiment. The contents can be taken into consideration.

[0087] Specifically, the memory cell 300 includes a transistor 301 that functions as a memory element and a transistor A switching element can control the supply of a potential to the second gate electrode of the transistor 301. The memory cell 300 also includes a transistor 302 that functions as an element. A capacitor 303 is provided to hold the potential of the second gate electrode of the transistor 301. The memory cell 300 may include a diode, a resistor, an inductor, etc., as needed. The circuit may further include other circuit elements.

[0088] In the cell array shown in FIG. 5, a plurality of input data lines Din and a plurality of output data lines Dou t, a plurality of write word lines WL, a plurality of read word lines RL, and other wiring are provided. The signals or power supply potential from the cell array driver circuit are transmitted through these wirings. The wiring is supplied to each memory cell 300. Therefore, the number of wirings is determined by the number of memory cells 300 and This can be determined by placement.

[0089] Specifically, in the case of the cell array shown in Figure 5, memory cells are connected in a matrix of 3 rows and 3 columns. At least the input data lines Din1 to Din3 and the output data line Dout 1 to Dout3, write word lines WL1 to WL3, read word lines RL1 to RL 3 is arranged in the cell array.

[0090] Then, the connection structure between the wiring and the circuit elements in the memory cell 300 is data line Din1, output data line Dout1, write word line WL1, read word line WL2 The following description will be given taking one of the memory cells 300 connected to the transistor line RL1 as an example. The gate electrode of the transistor 302 is connected to the write word line WL1. The transistor 302 has a source electrode and a drain electrode, either of which is connected to the input data line D. in1, and the other end is connected to the second gate electrode of the transistor 301. The first gate electrode of the transistor 301 is connected to a read word line RL1. The transistor 301 has either a source electrode or a drain electrode. One is connected to the output data line Dout1, and the other is given a fixed potential such as ground. The power supply line 304 is connected to the power supply line 304.

[0091] One of the pair of electrodes of the capacitor 303 is connected to the second gate of the transistor 301. The other end of the power line 304 is connected to the electrode, and the other end is given a fixed potential such as ground. is connected to.

[0092] FIG. 6 shows a cell of a NAND type memory device in which a plurality of memory cells 300 are connected in series. The circuit diagram of the memory cell array shown in FIG. 6 is an example of the configuration of each memory cell in the memory device. 5, and the configuration of the memory cell 100 has been described in the first embodiment. The contents of the above can be taken into consideration.

[0093] In the case of the cell array shown in FIG. 6, three columns of cell arrays each having three memory cells connected in series are used. Specifically, in a cell array with 3x3 memory cells, Input data lines Din1 to Din3, output data lines Dout1 to Dout3, write word lines WL1 to WL3, read word lines RL1 to RL3, selection signal lines SEL1 to SEL4, SEL2 and the power supply line 304 are arranged in the cell array. Signals or power supply potentials from the drive circuit of the array are supplied to each memory cell through these wirings. Therefore, the number of the above-mentioned wirings can be determined depending on the number of memory cells 300.

[0094] Next, the connection structure between the wiring and the circuit elements in the memory cell 300 will be described. For example, an input data line Din1, an output data line Dout1, and a write word line WL1 When attention is paid to the memory cell 300 connected to the read word line RL1, the transistor The gate electrode of the transistor 302 is connected to the write word line WL1. The transistor 302 has a source electrode and a drain electrode, either of which is connected to the input data line D. in1, and the other end is connected to the second gate electrode of the transistor 301. The first gate electrode of the transistor 301 is connected to a read word line RL1. The transistor 301 is connected to the output data line Dout1 and the ground. Adjacent memory cells are connected in series between the power supply lines 304 to which a fixed potential is applied. is connected to.

[0095] One of the pair of electrodes of the capacitor 303 is connected to the second gate of the transistor 301. The other end of the power line 304 is connected to the electrode, and the other end is given a fixed potential such as ground. is connected to.

[0096] Next, the operation of the memory device according to one embodiment of the present invention will be described using the cell array in FIG. 6 as an example. This will be explained with reference to Figure 21. Figure 21 shows the change over time in the potential of a signal input to each wiring. 3 is a timing chart showing the state where the transistor 301 and the transistor 302 are n-channel transistors. This is an example of a type that handles binary data.

[0097] First, the operation of the storage device when writing data will be described. When a signal having a pulse is input to the write word line WL1, the potential of the pulse Specifically, a high-level potential is applied to the gate electrode of the transistor 302. The transistor 302, whose gate electrode is connected to the write word line WL1, On the other hand, a low level potential is input to the read word line RL1. A low-level potential is applied to the first gate electrode of the transistor 301. The transistor 301, the first gate electrode of which is connected to the read word line RL1, , all will be turned off.

[0098] Then, signals containing data as information are input to the input data lines Din1 to Din3 in order. In FIG. 21, a high level is input to the input data line Din1 and the input data line Din3. A signal having a low level potential is input to the input data line Din2. The example shows a case where signals are input to the input data lines Din1 to Din3. The potential level of the signal that is input naturally differs depending on the content of the data.

[0099] The potentials input to the input data lines Din1 to Din3 are The second gate electrode of the transistor 301 is supplied with the second The amount of shift in the threshold voltage of the transistor 301 is determined according to the potential of the gate electrode. In this case, the input data line Din1 and the input data line Din3 have a high level potential. Since a signal is input, the memory cell 300 connected to the input data line Din1 In the memory cell 300 connected to the input data line Din3, the transistor The potential of the second gate electrode of the memory cell 301 is at a high level. In 300, a transistor 301 functioning as a memory element is connected to the line 130 in FIG. On the other hand, a signal having a low level potential is input to the input data line Din2. Since the data is input, in the memory cell 300 connected to the input data line Din2, Therefore, the potential of the second gate electrode of the transistor 301 is at a low level. In the memory cell 300, a transistor 301 functioning as a memory element is It operates according to line 131 in

[0100] When the input of the pulse signal to the write word line WL1 is completed, All of the transistors 302 whose gate electrodes are connected to the gate line WL1 are turned off. Then, a signal having a pulse is applied to the write word line WL2 and the write word line WL3. The memory cells having the write word line WL2 and the write word line WL The above-described operations are repeated in the memory cells having 3.

[0101] Next, the operation of the storage device when data is being held will be described. All the write word lines WL1 to WL3 are set to a level at which the transistor 302 is turned off. A potential, specifically a low-level potential, is applied to the transistor 302. Since the off-state current is extremely low, the potential of the second gate electrode is set at the time of writing. Also, all the read word lines RL1 to RL3 are set to a low level. is given a potential of

[0102] In the timing chart of Figure 21, a data retention period is provided to explain the data retention operation. However, in actual memory operation, it is not necessary to provide a retention period.

[0103] Next, the operation of the storage device when reading data will be described. In this case, all the write word lines WL1 to WL3 are connected to the transistors 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, A potential of a level that turns off 02, specifically a low level potential, is applied.

[0104] NAND type memory devices are given fixed potentials such as output data lines and ground. Adjacent memory cells are connected in series between the power supply lines. When you want to read data from a cell, you need to connect the same output data line as the memory cell. By controlling the memory cell connected to the memory cell, the output data line connected to the memory cell is The binary value stored in the memory is determined by whether or not the power supply line is connected to a fixed potential such as a winding. can be distinguished.

[0105] Specifically, an input data line Din1, an output data line Dout1, a write word line WL1, and the memory cell 300 connected to the read word line RL1. Consider the case where high level data stored in memory cell 300 is read. To select the output data line Dout1 to which the memory cell 300 is connected, SEL1 and SEL2 are set to a high level potential, and the transistor 320 and The transistor 321 connected to SEL1 and SEL2 is turned on. The read word line RL1 connected to the first gate electrode of the transistor 301 in Furthermore, a high level potential is applied to the read word lines RL2 and RL3. This turns on the transistors 301 connected to the read word lines RL2 and RL3. The transistor 301 of the memory cell 300 has a high-level data at the second gate electrode. In other words, the transistors shown in FIG. In accordance with the operation of the capacitor 301, the threshold voltage shifts to the negative side and becomes Vth1. Therefore, the transistor 301 is turned on. All connected transistors are turned on, and the output data line Dout1 is grounded. It conducts to the power supply line and has approximately the same potential as ground.

[0106] Next, the input data line Din2, the output data line Dout2, and the write word line WL 1. Focusing on the memory cell 300 connected to the read word line RL1, Consider the case where low level data stored in cell 300 is read. To select out2, SEL1 and SEL2 are set to high potential. and the transistor 321 connected to SEL2 are turned on. Then, a first gate electrode of the transistor 301 in the memory cell 300 is connected to The read word line RL1 is set to a low level. 2 to RL3 are applied with a high level potential, and the The transistor 301 of the memory cell 300 is turned on. 2. In other words, low level data is written to the gate electrode of , the threshold voltage does not shift according to the operation of the transistor 301 functioning as a memory element, and V Therefore, the transistor 301 is turned off. The output data line Dout2 is not connected to the power line to which ground is applied, and is a high impedance. The device enters a impedance state.

[0107] A read circuit is connected to the end of each output data line Dout. The output signal of is the actual output of the memory.

[0108] In this embodiment, when reading data, an output data line is selected. In this case, two selection signal lines SEL1 and SEL2 and gate electrodes are connected to the respective signal lines. The figure shows an example of a case where a transistor connected to The selection of the input data line is performed by turning on or off the output data line and the readout circuit connected to it. Since it is sufficient to be able to select at least one selection signal line and the A transistor would be fine.

[0109] In this embodiment, each of the write, hold, and read operations is performed in a plurality of memory cells. Although the driving method in which the signals are driven in order has been described, the present invention is not limited to this configuration. The above operation may be performed only in the memory cell of the address.

[0110] In the case of the cell array shown in FIG. 6, each memory cell is provided with an input data line Din and an output data line D The four wirings of the data line Dout, the write word line WL, and the read word line RL are connected. In the example shown, the memory cell is connected to the The number of wirings connected to the transistor 301 is not limited to this. a signal for controlling the switching of transistor 302; A signal for supplying a potential to the second gate electrode of the memory cell 300 is supplied to the memory cell 300. The drain current of the transistor 301 or the source electrode and the drain The resistance between the rain electrodes is set so that the potential contained as information can be sent to the drive circuit. The number of wires and the connection structure can then be determined appropriately.

[0111] In the timing chart shown in FIG. 21, the output data lines Dout1 and Dout2 The shaded areas of t2 and Dout3 indicate that the data is in an uncertain state. The rising edge of each signal rises vertically and the falling edge of each signal falls vertically. Those skilled in the art will understand that the waveform of each signal will be dull because the signal will be affected by the load on the signal line and noise, etc. This is easily understood.

[0112] Next, the operation of the memory device according to one embodiment of the present invention will be described using the cell array in FIG. 5 as an example. This will be explained with reference to FIG. 7. FIG. 7 is a timing chart showing the time change of the potential of a signal input to each wiring. 1 is a timing chart in which the transistor 301 and the transistor 302 are n-channel transistors. This example illustrates a case where binary data is handled.

[0113] First, the operation of the storage device when writing data will be described. When a signal having a pulse is input to the write word line WL1, the voltage of the pulse A write word is written by applying a potential, specifically a high level potential, to the gate electrode. All of the transistors 302 whose gate electrodes are connected to the line WL1 are turned on. The read word line RL1 is connected to a transistor that functions as a memory element. A signal having a potential lower than Vth1 in FIG. 2 is input, and the read word line All of the transistors 301 whose first gate electrodes are connected to RL1 remain off. .

[0114] Then, signals containing data as information are input to the input data lines Din1 to Din3 in order. In FIG. 7, a high level potential is applied to all of the input data lines Din1 to Din3. The example shows a case where a signal having the following characteristics is input to the input data lines Din1 to Din3. The potential level of the signal input to the When handling data, the potential of the signal input to the input data lines Din1 to Din3 is the power supply voltage. It is sufficient if the voltage is two values ​​(for example, Vdd and Vss) that correspond to the voltage. However, it is also possible to use multi-value devices with three or more values. When handling data, the number of potential levels must be adjusted to match the base number used for the data. Just decide.

[0115] The potentials input to the input data lines Din1 to Din3 are The second gate electrode of the transistor 301 is supplied with the second The amount of shift in the threshold voltage of the transistor 301 is determined according to the potential of the gate electrode.

[0116] When the input of the pulse signal to the write word line WL1 is completed, All of the transistors 302 whose gate electrodes are connected to the gate line WL1 are turned off. Then, a signal having a pulse is applied to the write word line WL2 and the write word line WL3. The memory cells having the write word line WL2 and the write word line WL The above-described operations are repeated in the memory cells having 3.

[0117] Next, the operation of the storage device when data is being held will be described. All the write word lines WL1 to WL3 are set to a level at which the transistor 302 is turned off. A potential, specifically a low-level potential, is applied to the transistor 302. Since the off-state current is extremely low, the potential of the second gate electrode is set at the time of writing. Also, all of the read word lines RL1 to RL3 are connected to transistors Specifically, the potential of the transistor functioning as a memory element is set to a level at which the transistor 301 is turned off. A potential lower than Vth1 in FIG. 2 showing the operation is applied.

[0118] In the timing chart of Figure 7, a data retention period is provided to explain the data retention operation. However, in actual memory operation, it is not necessary to provide a retention period.

[0119] Next, the operation of the storage device when reading data will be described. In this case, all the write word lines WL1 to WL3 are connected to the transistors 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, A potential of a level that turns off 02, specifically a low level potential, is applied.

[0120] On the other hand, during a read operation, a signal having a pulse is applied to the read word lines RL1 to RL3. Specifically, first, a signal having a pulse is input to the read word line RL1. When a signal is input, the potential of the pulse, specifically, the transistor that functions as a memory element A potential higher than Vth1 and lower than Vth0 in Figure 2, which shows the operation of the A potential higher than Vth0 is applied to the first gate electrode of the transistor 301. In the transistor 301, the first gate electrode is connected to the transistor functioning as a memory element. A potential higher than Vth1 and lower than Vth0 in FIG. 2, or Vth0 When a potential higher than , the drain current or the resistance between the source electrode and the drain electrode is determined.

[0121] The drain current of the transistor 301 or the resistance between the source electrode and the drain electrode The value is the potential included as information, that is, the potential between the source electrode and the drain electrode of the transistor 301. The voltage of the electrodes connected to the output data lines Dout1 to Dout3 is The potentials are supplied to the driving circuits via output data lines Dout1 to Dout3.

[0122] The potentials supplied to the output data lines Dout1 to Dout3 are the same as those written to the memory cells. The level is determined according to the data stored in the memory. If the same data value is stored in the memory cell, all the output The same level of potential should be supplied to the data lines. The characteristics of the transistor 301 or the transistor 302 vary among memory cells. Therefore, even if all the data to be read is the same value, The potential supplied to the output terminals may vary, and the distribution may have a certain width. Even if there is some variation in the potentials supplied to the data lines Dout1 to Dout3, The data read from the stored potential is included as information, and the amplitude is adjusted to meet the desired specifications. A readout circuit capable of forming a signal whose width and waveform have been processed is stored as a drive circuit. Installed on the device.

[0123] An example of a readout circuit is shown in the circuit diagram of FIG. 9. The readout circuit shown in FIG. A switch for controlling the input of the potentials of the lines Dout1 to Dout3 to the readout circuit. The transistors 310_1 to 310_3 function as switching elements, and the transistors 310_1 to 310_3 function as resistors. The read circuit shown in FIG. The pumps 312_1 to 312_3 are provided.

[0124] Specifically, the transistors 311_1 to 311_3 each have a gate electrode and a drain. The gate electrode is connected to the gate electrode and the drain electrode, and a high-level power supply voltage is applied to the gate electrode and the drain electrode. The transistors 311_1 to 311_3 are connected to a source electrode are connected to the non-inverting input terminals (+) of the operational amplifiers 312_1 to 312_3. The transistors 311_1 to 311_3 are connected to a node to which the power supply potential Vdd is applied. , resistors connected between the non-inverting input terminals (+) of the operational amplifiers 312_1 to 312_3 In Figure 9, the gate electrode and drain electrode of a transistor are connected. However, the present invention is not limited to this, and any element that functions as a resistor can be used instead. Replacement is possible.

[0125] The transistors 310_1 to 310_3 functioning as switching elements have gates The electrodes are connected to the bit lines BL1 to BL3, respectively. The output data lines Dout1 to Dout3 and the transistors 311, 312, 313, 314, 315, 316, 317, 318, 319, 320, 321, 322, 323, 324, 325, 326, 327, 328, 329, 330, 331, 332, 333, 334, 335, 336, 337, 338, 339, 340, 341, 342, 343, 344, 345, 346, 347, 348, 349, 350, 351, 352, 353, 354, 355, 356, 357, 358, The connection between the source electrodes of 1 to 311_3 is controlled.

[0126] For example, when transistor 310_1 is turned on, transistor 310_2 in memory cell 300 01 and the transistor 311_1 in the read circuit are connected in series. The potential Vdata at the node connected to the non-inverting input of the operational amplifiers 312_1 to 312_3 The potential Vdata is applied to the terminal (+). The resistance between the source electrode and the drain electrode of the transistor 311_1 is Since it is determined according to the ratio of the resistance values ​​between the drain electrodes, the level of the potential Vdata is The values ​​of the data are reflected.

[0127] On the other hand, the inverting input terminals (-) of the operational amplifiers 312_1 to 312_3 are connected to the reference potential Vref The potential Vdata given to the non-inverting input terminal (+) is given as the reference The level of the output terminal potential Vout can be changed depending on whether it is higher or lower than the potential Vref. This allows a signal containing data as information to be obtained indirectly.

[0128] Even if the same data value is stored in memory cells, there may be variations in the characteristics between the memory cells. The variation in the voltage Vdata causes variations in the level of the read potential Vdata, and the distribution Therefore, the level of the reference potential Vref is Therefore, it is determined taking into consideration the variations in the node potential Vdata.

[0129] In addition, in FIG. 9, one operational amplifier is used for each output data line to read out data. However, the number of operational amplifiers is not limited to this. Data for n values ​​(n is a natural number greater than or equal to 2) When dealing with the above, the number of operational amplifiers used for each output data line is set to (n-1).

[0130] Next, the operation of the storage device when erasing data will be described. As in the case of writing, a signal having a pulse is input to the write word line WL1. The potential of the pulse, specifically, a high-level potential, is applied to the gate electrode. , all the transistors 302 whose gate electrodes are connected to the write word line WL1 are On the other hand, the read word line RL1 has a transistor that functions as a memory element. A signal having a potential lower than Vth1 in FIG. 2 showing the operation of the capacitor is input. The transistor 301, whose first gate electrode is connected to the read word line RL1, Keep everything off.

[0131] A fixed potential such as ground is applied to the input data lines Din1 to Din3. In FIG. 7, a signal having a low level potential is applied to all of the input data lines Din1 to Din3. The example shows a case where a signal is input to the input data lines Din1 to Din3. The low-level fixed potential is applied to the transistor 302 through the transistor 303 which is turned on. 1 is applied to the second gate electrode. Then, according to the potential of the second gate electrode, The value of the threshold voltage of transistor 301 is reset.

[0132] When the input of the pulse signal to the write word line WL1 is completed, All of the transistors 302 whose gate electrodes are connected to the gate line WL1 are turned off. Then, a signal having a pulse is applied to the write word line WL2 and the write word line WL3. The memory cells having the write word line WL2 and the write word line WL The above-described operations are repeated in the memory cells having 3.

[0133] In the timing chart of Figure 7, an erasing period is provided to explain the data erasing operation. However, in actual memory operation, it is not necessary to provide an erase period. All you have to do is write new data to overwrite the previously written data. One advantage of the storage device according to one embodiment of the present invention is that no erasure period is required.

[0134] In this embodiment, the write, hold, read and erase operations are performed on a plurality of memory cells. Although the driving method in which the steps are performed in sequence has been described above, the present invention is not limited to this configuration. Alternatively, the above operation may be performed only on the memory cell at the specified address.

[0135] In the case of the cell array shown in FIG. 5, each memory cell has an input data line Din and an output data line D The four wirings of the data line Dout, the write word line WL, and the read word line RL are connected. In the example shown, the memory cell is connected to the The number of wirings connected to the transistor 301 is not limited to this. a signal for controlling the switching of transistor 302; A signal for supplying a potential to the second gate electrode of the memory cell 300 is supplied to the memory cell 300. The drain current of the transistor 301 or the source electrode and the drain The resistance between the rain electrodes is set so that the potential contained as information can be sent to the drive circuit. The number of wires and the connection structure can then be determined appropriately.

[0136] Next, a memory device using the cell array shown in FIG. 5 will be taken as an example. The configuration of the drive circuit of the device will be described.

[0137] FIG. 8 is a block diagram illustrating an example of a configuration of a memory device according to one embodiment of the present invention. In the block diagram shown in Figure 8, the circuits in the memory device are classified by function and are separated into independent blocks. However, in actual circuits, it is difficult to completely separate each function. A circuit may be involved in multiple functions.

[0138] The memory device shown in FIG. 8 includes a cell array 500 in which a plurality of memory cells are connected in a matrix. and a drive circuit 501 that controls the driving of the cell array 500. The circuit 501 generates a signal containing the data read from the cell array 500 as information. A read circuit 502 and a word circuit for selecting memory cells in the cell array 500 row by row. A data write / erase circuit 503 controls the data write / erase in the selected memory cell. A data line driving circuit 504 controls the read circuit 502, the word line driving circuit 503, and the data The word line driver circuit 504 has a control circuit 505 for selecting the operation of the word line driver circuit 504. The driving circuit 503 has a word line decoder 506. The data line driving circuit 504 has , a data line decoder 508 and a data line selector 509 .

[0139] Note that a memory device according to one embodiment of the present invention includes at least a cell array 500 in its configuration. A memory device according to one embodiment of the present invention includes a cell array and a driver circuit for the cell array. This category includes memory modules with some or all of the memory cards connected. The module is provided with a connection terminal that can be mounted on a printed wiring board, etc. In addition, the device may be in a so-called packaged state, protected by resin or the like.

[0140] In addition, all or part of the drive circuit 501 is mounted on one substrate together with the cell array 500. The cell array 500 may be formed on a substrate different from that of the cell array 500. In the case where all or part of the operating circuit 501 and the cell array 500 are formed on different substrates, In this case, the cell is connected via an FPC (Flexible Printed Circuit) or similar. The array 500 can be connected to all or part of the driving circuit 501. A part of the operating circuit 501 is connected to the FPC using the COF (Chip On Film) method. Alternatively, the driving circuit 50 may be formed by using a COG (Chip On Glass) method. 1 may be connected to the cell array 500.

[0141] The cell array 500 and the drive circuit 501 are formed on a single substrate, thereby forming a memory device. The number of external circuit parts connected to the device is reduced, resulting in cost reductions due to fewer assembly and inspection processes. In addition, the number of contacts at the connection between the storage device and the external circuit can be reduced. This prevents a decrease in yield due to poor connections and reduces mechanical stress at the connection points. It is possible to prevent a decrease in reliability due to low strength. Only circuits whose driving frequency is relatively lower than other circuits, such as the data line selector 509, are selected as selectors. It is also possible to form the filter array 500 on a single substrate. By forming the drive circuit 501 together with the cell array 500 on one substrate, the above-mentioned connection Avoiding defects that lead to reduced yields and poor mechanical strength at connection points, and assembly This will bring about some benefits, such as cost reductions due to fewer processes and inspection processes. Furthermore, compared to when the cell array 500 and the drive circuit 501 are all formed on one substrate, This can improve the performance of high frequency circuits.

[0142] When a signal AD containing address (Ax, Ay) information is input to the memory device, the control circuit 505 transmits the address Ax, which is information about the column direction of the address, to the data line driving circuit 504 and sends address Ay, which is information about the row direction of the address, to word line driver circuit 503. The control circuit 505 also sends a signal DA containing the data input to the storage device as information. TA is sent to the data line driving circuit 504 .

[0143] The selection of the operation, whether to write, read or erase data, is controlled by the RE (Read enable), WE (Write enable) are supplied to the control circuit 505. It is selected by signals such as BLE (Erase enable) and EE (Erase enable). When a memory device is provided with a plurality of cell arrays 500, the control circuit 505 A signal CE (Chip enable) for selecting the above may be input.

[0144] When a write operation is selected by the signal WE, the control circuit 505 instructs: The word line decoder 506 included in the word line driving circuit 503 outputs a signal corresponding to the address Ay. A signal having a pulse is input to the write word line WL. When the write operation is selected, the data line drive circuit 504 drives the data line driver 506 in accordance with the instruction from the control circuit 505. In the circuit 504, the operation of the data line selector 509 is controlled by the data line decoder 508. The signal is given to the data line selector 509. The data line selector 509 In accordance with a signal from the data line decoder 508, a signal DATA containing data as information is output. The sampled signal is input to the input data line Din corresponding to the address Ax. Enter.

[0145] When a read operation is selected by the signal RE, the control circuit 505 instructs: The word line decoder 506 included in the word line driving circuit 503 outputs a signal corresponding to the address Ay. A signal having a pulse is input to the read word line RL. When the read operation is selected, the read circuit 504 operates in accordance with an instruction from the control circuit 505. In 502, the potential of the bit line BL corresponding to the address Ax is controlled to Among the transistors 310_1 to 310_3, the transistor corresponding to the address Ax is turned on. Then, the potential of the output data line Dout corresponding to the address Ax is calculated. and generating a signal containing the data as information. do.

[0146] When the erase operation is selected by the signal EE, the erase operation is performed in accordance with the instruction from the control circuit 505. The word line decoder 506 of the word line driver circuit 503 outputs the corresponding address Ay. A signal having a pulse is input to the write word line WL. When the erase operation is selected, the data line driving circuit 50 4, a signal for controlling the operation of the data line selector 509 from the data line decoder 508 is is given to the data line selector 509. In the data line selector 509, In accordance with the signal from the address decoder 508, a signal for erasing data is sent to the corresponding address. The signal is input to the input data line Din of the sensor Ax.

[0147] In the memory device shown in FIG. 8, the word line driver circuit 503 drives the write word line W L and the read word line RL. However, the present invention is not limited to this configuration. a drive circuit for controlling the input of a signal to the read word line RL, and a drive circuit for controlling the input of a signal to the read word line RL. It may be provided in a storage device.

[0148] This embodiment mode can be implemented in appropriate combination with any of the above embodiment modes.

[0149] (Embodiment 3) A bottom-gate transistor with a channel-etched structure will be taken as an example of a transistor according to one embodiment of the present invention. A method for manufacturing a memory device will be described. The transistor functioning as a switching element and the transistor functioning as a gate electrode are both made of oxide semiconductor. An example in which a membrane is used as the active layer will be described.

[0150] As shown in FIG. 10(A), a gate electrode 401 and a gate electrode 402 are formed on a substrate 400. do.

[0151] There is no significant limitation on the substrate that can be used as the substrate 400 having an insulating surface. At the very least, it is necessary for the material to have heat resistance sufficient to withstand subsequent heat treatment. A glass substrate manufactured by a fusion method or a float method can be used. If the temperature of the subsequent heat treatment is high, use a plate with a strain point of 730°C or higher. The glass substrate may be made of, for example, aluminosilicate glass or aluminoborosilicate glass. Glass materials such as acid glass and barium borosilicate glass are used. By containing more barium oxide (BaO) than boron oxide, more practical resistance is achieved. Thermal glass is obtained. For this reason, a glass substrate containing more BaO than B2O3 is used. is preferred.

[0152] Instead of the glass substrate, an insulating substrate such as a ceramic substrate, a quartz substrate, or a sapphire substrate may be used. Alternatively, a substrate made of an insulating material may be used. Alternatively, a substrate made of a crystallized glass may be used. A substrate having an insulating film provided on the surface of a metal substrate such as a stainless alloy may also be used.

[0153] In addition, substrates made of flexible synthetic resins such as plastic generally have a low heat resistance temperature. However, if it can withstand the processing temperatures in the subsequent manufacturing steps, it is possible to use a material such as a silicon dioxide film as the substrate 400. As a plastic substrate, polyethylene terephthalate (P Polyesters such as polyethersulfone (PES), polyethylene naphtha (PEP), Polyethylene terephthalate (PEN), Polycarbonate (PC), Polyether ether ketone (PEE K), polysulfone (PSF), polyetherimide (PEI), polyarylate (PA R), polybutylene terephthalate (PBT), polyimide, acrylonitrile butadiene Polystyrene resin, polyvinyl chloride, polypropylene, polyvinyl acetate, acrylic resin, etc. Examples include:

[0154] An insulating film serving as a base film is formed between the substrate 400 and the gate electrodes 401 and 402. As the base film, for example, a silicon oxide film, a silicon oxynitride film, a silicon nitride film, film, silicon nitride oxide film, aluminum nitride film, or aluminum nitride oxide film In particular, the undercoat film may be a barrier film. High insulating film, such as silicon nitride film, silicon oxynitride film, aluminum nitride film, or oxynitride film By using an aluminum film, etc., impurities in the atmosphere such as moisture or hydrogen, or bases Impurities such as alkali metals and heavy metals contained in the plate 400 may be present in the oxide semiconductor film and the gate It is necessary to prevent the oxide semiconductor film from penetrating into the insulating film, or into the interface between the oxide semiconductor film and other insulating films and its vicinity. This can be done.

[0155] In this specification, an oxynitride is a compound having a composition in which oxygen is contained more than nitrogen. Nitrogen oxide is a substance that contains more nitrogen than oxygen. It refers to a substance.

[0156] The gate electrodes 401 and 402 are made of molybdenum, titanium, chromium, or tantalum. Metallic materials such as tungsten, neodymium, scandium, etc., and materials containing these metallic materials as the main components A conductive film using an alloy material or a nitride of these metals can be used in a single layer or a laminated layer. In addition, if it can withstand the temperature of the heat treatment to be performed in the subsequent process, Aluminum and copper can also be used as the metal material. Aluminum and copper are heat-resistant. To avoid problems with corrosion, it is recommended to use it in combination with high melting point metal materials. Metal materials include molybdenum, titanium, chromium, tantalum, tungsten, neodymium, Scandium and the like can be used.

[0157] For example, the gate electrode 401 and the gate electrode 402 each having a two-layer laminated structure are made of aluminum. Two-layer laminated structure with a molybdenum film laminated on a silicon film, and a molybdenum film laminated on a copper film. A two-layer structure, a two-layer structure in which a titanium nitride film or a tantalum nitride film is laminated on a copper film, or It is preferable to use a two-layer structure in which a titanium nitride film and a molybdenum film are laminated. The gate electrodes 401 and 402 having the structure are made of aluminum films, Aluminum and silicon alloy film, aluminum and titanium alloy film or aluminum and neodymium alloy film The alloy film is used as an intermediate layer, and a tungsten film, a tungsten nitride film, a titanium nitride film, or a titanium It is preferable to use a structure in which the films are stacked as upper and lower layers.

[0158] In addition, the gate electrode 401 and the gate electrode 402 are made of an indium oxide film, an indium oxide glass film, and zinc alloy film, indium oxide zinc oxide alloy film, zinc oxide film, zinc aluminum oxide film, oxynitride film A light-transmitting oxide conductive film such as an aluminum zinc oxide film or a zinc gallium oxide film is used. This can improve the aperture ratio of the pixel portion.

[0159] The thickness of the gate electrode 401 and the gate electrode 402 is 10 nm to 400 nm, preferably 10 In this embodiment, a sputtering process using a tungsten target is performed. After forming a conductive film for the gate electrode with a thickness of 150 nm by the photolithography method, the conductive film was removed by etching. By processing (patterning) the gate electrode 401 and the gate electrode 402 into a desired shape, If the end of the formed gate electrode is tapered, the gate electrode layered thereon may be formed in a tapered shape. This is preferable because it improves the coverage of the gate insulating film. If the resist mask is formed by the inkjet method, a photomask can be used. Therefore, the manufacturing cost can be reduced.

[0160] Next, a gate insulating film 403 is formed on the gate electrodes 401 and 402. The gate insulating film 403 is a silicon oxide film formed by using a plasma CVD method or a sputtering method. Silicon nitride film, silicon oxynitride film, silicon nitride oxide film, aluminum oxide film, aluminum nitride film, aluminum oxynitride film, aluminum nitride oxide film, hafnium oxide film or tungsten oxide film The gate insulating film 403 can be formed as a single layer or a stacked layer. It is desirable that the silicon oxide film contains as few impurities as possible, such as hydrogen. When forming a film, a silicon target or a quartz target is used as the target, Oxygen or a mixed gas of oxygen and argon is used as the sputtering gas.

[0161] By removing impurities, an oxide semiconductor that has been made i-type or substantially i-type (highly purified) Since the oxide semiconductor is extremely sensitive to the interface state and the interface charge, The interface between the oxide semiconductor and the gate insulating film 403 is important. The gate insulating film (GI) in contact with the nitride semiconductor is required to be of high quality.

[0162] For example, high density plasma CVD using microwaves (2.45 GHz) produces dense, high dielectric strength films. This is preferable because it allows the formation of a high-quality insulating film. By closely contacting the insulating film, the interface state is reduced and the interface characteristics are improved. Because it is possible.

[0163] Of course, if a good quality insulating film can be formed as a gate insulating film, sputtering is also possible. Other film formation methods such as the plasma CVD method and the like can also be applied. This improves the quality of the gate insulating film and the interface characteristics between the gate insulating film and the oxide semiconductor. In any case, it is important that the film quality as a gate insulating film is good. In other words, it is possible to reduce the interface state density between the gate insulating film and the oxide semiconductor and form a good interface. As long as it's possible, that's fine.

[0164] Insulating films made of materials with high barrier properties, silicon oxide films with low nitrogen content, and silicon oxynitride films Alternatively, a gate insulating film 403 having a structure in which an insulating film such as a silicon dioxide film is laminated may be formed. In this case, insulating films such as silicon oxide films and silicon oxynitride films are used as insulating films with high barrier properties and oxide semiconductors. As an insulating film with high barrier properties, for example, a silicon nitride film or a silicon nitride oxide film is used. , aluminum nitride film, or aluminum nitride oxide film. By using a thin insulating film, impurities in the atmosphere such as moisture or hydrogen, or impurities contained in the substrate, Impurities such as alkali metals and heavy metals are present in the oxide semiconductor film, the gate insulating film 403, Alternatively, the intrusion of the oxide semiconductor film into the interface between the oxide semiconductor film and another insulating film and its vicinity can be prevented. In addition, a silicon oxide film or a silicon oxynitride film having a low nitrogen content that is in contact with the oxide semiconductor film may be used. By forming an insulating film such as a film, the insulating film with high barrier properties is in direct contact with the oxide semiconductor film. This can prevent this.

[0165] For example, the first gate insulating film is formed by sputtering to a thickness of 50 nm to 200 nm. The following silicon nitride films (SiN y (y>0)), and a second gate insulating film is formed on the first gate insulating film. As the insulating film, a silicon oxide film (SiOx (x>0) The gate insulating film 403 may be formed by layering the gate insulating film 403 with a thickness of 100 nm. can be set appropriately depending on the characteristics required for the transistor, and is in the range of 350 nm to 400 nm. nm is also acceptable.

[0166] In this embodiment, a silicon nitride film having a thickness of 50 nm is formed by sputtering. The gate insulating film 40 has a structure in which a silicon oxide film having a thickness of 100 nm formed by Form 3.

[0167] In order to prevent hydrogen, hydroxyl groups, and moisture from being contained in the gate insulating film 403 as much as possible, As a pre-treatment for film formation, the gate electrode 401 and the gate electrode 402 are formed in the pre-heating chamber of the sputtering device. The substrate 400 on which the electrode 402 is formed is preheated to remove the moisture or water adsorbed on the substrate 400. It is preferable to desorb and exhaust impurities such as oxygen. The temperature is 0°C or higher and 400°C or lower, preferably 150°C or higher and 300°C or lower. The exhaust means provided in the vacuum chamber is preferably a cryopump. It can also be done as follows.

[0168] Next, a film having a thickness of 2 nm to 200 nm, preferably 3 nm, is deposited on the gate insulating film 403. The oxide semiconductor film 40 has a thickness of 3 nm to 20 nm, and more preferably has a thickness of 3 nm to 20 nm. The oxide semiconductor film 404 is formed by sputtering using an oxide semiconductor as a target. The oxide semiconductor film 404 is formed in a rare gas (for example, argon) atmosphere. under an oxygen atmosphere or a mixture of a rare gas (e.g., argon) and oxygen. It can be formed by the TA method.

[0169] Note that before the oxide semiconductor film 404 was formed by a sputtering method, argon gas was introduced. Reverse sputtering is performed to generate plasma, and dust adhering to the surface of the gate insulating film 403 is removed. It is preferable to remove the target. In a nitrogen atmosphere, a voltage is applied to the substrate side using an RF power supply to form plasma on the substrate surface. It is possible to use nitrogen, helium, etc. instead of the argon atmosphere. Alternatively, the treatment may be carried out in an argon atmosphere to which oxygen, hydrogen, nitrous oxide, etc. have been added. Alternatively, the treatment may be carried out in an argon atmosphere to which chlorine, carbon tetrafluoride, or the like has been added.

[0170] For the oxide semiconductor film 404, any of the above-described oxide semiconductors can be used.

[0171] In this embodiment, an acid containing In (indium), Ga (gallium), and Zn (zinc) is used. 30 nm thick In-Ga-Z obtained by sputtering using an In-Ga-Zr nitride semiconductor target An nO-based non-single-crystal film is used as the oxide semiconductor film 404. For example, the atomic ratio of each metal is In:Ga:Zn=1:1:0.5, In:Ga:Zn=1:1 :1, or an oxide semiconductor target having a composition ratio of In:Ga:Zn=1:1:2 In addition, when the sputtering method is used, SiO2 is used in an amount of 2% by weight or more. Film formation may be performed using a target containing 0% by weight or less of In, Ga, and Zn. The filling rate of the oxide semiconductor target containing By using an oxide semiconductor target with a high filling rate, The deposited oxide semiconductor film becomes a dense film.

[0172] The substrate is held in a processing chamber maintained in a reduced pressure state, and hydrogen and A sputtering gas from which the moisture and oxygen have been removed is introduced, and a metal oxide is used as a target to deposit a metal oxide on the substrate 400. During the deposition, the substrate temperature is set to 100° C. or higher and 600° C. or lower. Preferably, the temperature may be set to 200° C. or higher and 400° C. or lower. As a result, the impurity concentration in the formed oxide semiconductor film can be reduced. Damage caused by sputtering is reduced. To remove residual moisture in the processing chamber, an adsorption type It is preferable to use a vacuum pump such as a cryopump, an ion pump, or a titanium It is preferable to use a sublimation pump. Also, as an exhaust means, a turbo pump is preferable. A cryopump with a cold trap may be used. The membrane chamber contains, for example, hydrogen atoms, compounds containing hydrogen atoms such as water (H2O), and more preferably carbon. Since the exhaust gas contains oxygen (including compounds containing hydrogen atoms), the oxide semiconductor film formed in the deposition chamber is The concentration of impurities contained in the material can be reduced.

[0173] As an example of the film formation conditions, the distance between the substrate and the target is 100 mm, and the pressure is 0.6 Pa. The conditions were: DC power 0.5kW, oxygen (oxygen flow rate 100%) atmosphere. When a pulsed direct current (DC) power supply is used, particles that are generated during film formation are The oxide semiconductor film is preferable because it can reduce dust particles and make the film thickness distribution uniform. The thickness is set to 5 nm or more and 30 nm or less. The appropriate thickness depends on the oxide semiconductor material used. The thickness may be selected appropriately depending on the material.

[0174] Note that in order to prevent hydrogen, a hydroxyl group, and moisture from being contained in the oxide semiconductor film 404 as much as possible, In order to do this, as a pre-treatment for film formation, the gate insulating film 403 is formed in the pre-heating chamber of the sputtering equipment. The substrate 400 on which the impurities have been formed is preheated to remove impurities such as moisture or hydrogen adsorbed on the substrate 400. It is preferable to desorb and exhaust the substances. The temperature is 0°C or lower, preferably 150°C to 300°C. The means is preferably a cryopump, but this preheating process can be omitted. This preheating is also performed before the insulating film 411 is formed on the source electrode 407 and the drain electrode 40 8, the same process is carried out on the substrate 400 on which the source electrode 409 and the drain electrode 410 have been formed. Good too.

[0175] There are two types of sputtering methods: RF sputtering, which uses a high frequency power supply, and D There is also the pulsed DC sputtering method, which applies a bias in a pulsed manner. The RF sputtering method is mainly used to form insulating films, while the DC sputtering method The tarring method is mainly used when forming a metal film.

[0176] There are also multi-target sputtering devices that can accommodate multiple targets of different materials. The equipment can deposit layers of different materials in the same chamber, or multiple types of materials in the same chamber. It is also possible to simultaneously discharge and deposit the same materials.

[0177] In addition, a magnetron sputtering method using a magnet mechanism inside the chamber is used. The ECR device uses a plasma generated by microwaves without glow discharge. There is a sputtering device that uses the sputtering method.

[0178] In addition, as a film formation method using a sputtering method, a target material and a sputtering gas are mixed during film formation. Reactive sputtering method to form compound thin films by chemically reacting the silicon dioxide and silicon dioxide components. There is also a bias sputtering method in which a voltage is applied to the substrate during film formation.

[0179] The gate insulating film 403 and the oxide semiconductor film 404 are successively formed without being exposed to the air. By continuously forming the film without exposing it to the atmosphere, the interface is free from water and hydrochloric acid. Each layer interface is free from contamination by atmospheric components and impurities floating in the air, such as oxygen. Since it is possible to form the transistor, variations in transistor characteristics can be reduced.

[0180] Next, as shown in FIG. 10B, the oxide semiconductor film 404 is removed by etching or the like. and patterned in a position overlapping the gate electrodes 401 and 402. In this case, an island-shaped oxide semiconductor film 405 and an island-shaped oxide semiconductor film 406 are formed over a gate insulating film 403. , respectively.

[0181] A resist mask for forming the island-shaped oxide semiconductor films 405 and 406 was formed. The resist mask may be formed by an ink-jet method. Since no photomask is used, manufacturing costs can be reduced.

[0182] In addition, when forming a contact hole in the gate insulating film 403, the process is performed by forming an island-shaped oxide film. This can be performed when the semiconductor film 405 and the oxide semiconductor film 406 are formed.

[0183] Note that etching for forming the island-shaped oxide semiconductor films 405 and 406 is The etching may be dry etching or wet etching, or both. The etching gas used in etching is a gas containing chlorine (chlorine-based gas, for example, chlorine ( Cl2), boron chloride (BCl3), silicon chloride (SiCl4), carbon tetrachloride (CCl4), etc. Also, a gas containing fluorine (a fluorine-based gas, for example, carbon tetrafluoride (CF4)) is preferable. , sulfur hexafluoride (SF6), nitrogen trifluoride (NF3), trifluoromethane (CHF3), etc. ), hydrogen bromide (HBr), oxygen (O2), and these gases with helium (He) or argon ( A gas containing a rare gas such as Ar can be used.

[0184] As a dry etching method, parallel plate type RIE (Reactive Ion Etch) ing) method and ICP (Inductively Coupled Plasma) A combined plasma etching method can be used. It is possible to etch into the desired processed shape. The etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the electrode on the substrate side) were determined as follows: The amount of power used, the temperature of the electrode on the substrate, etc. are adjusted appropriately.

[0185] The etching solution used for wet etching is a mixture of phosphoric acid, acetic acid, and nitric acid. ITO-07N (manufactured by Kanto Chemical Co., Ltd.) may also be used. After wet etching, the etching solution is removed by washing along with the etched material. The waste etching solution containing the removed material is purified and the contained material is reused. The material such as indium contained in the oxide semiconductor film may be extracted from the waste liquid after the etching. By collecting and reusing these materials, resources can be used effectively and costs can be reduced.

[0186] Note that reverse sputtering is performed before forming a conductive film in the next step, and the island-shaped oxide semiconductor film 405 Resist residues and the like adhering to the surfaces of the oxide semiconductor film 406 and the gate insulating film 403 are removed. It is preferable to remove it.

[0187] Next, nitrogen, oxygen, and ultra-dry air (water content of 20 ppm or less, preferably 1 ppm or less) or an atmosphere of rare gas (argon, helium, etc.) The oxide semiconductor films 405 and 406 are subjected to heat treatment under an atmosphere. The oxide semiconductor film 405 and the oxide semiconductor film 406 are subjected to a heat treatment to form the oxide semiconductor film 40 5. Moisture or hydrogen in the oxide semiconductor film 406 can be released. 300°C or higher and 850°C or lower (or a temperature below the strain point of the glass substrate), preferably 550°C or lower For example, the heat treatment may be performed at 600°C for 3 to 6 minutes. The RTA method allows dehydration or dehydrogenation to be carried out in a short time. It can be processed at temperatures exceeding the strain point of the glass substrate. In this state, heat treatment may be carried out for about 1 hour.

[0188] In this embodiment, an electric furnace, which is one of heat treatment devices, is used to heat the oxide semiconductor film 405 and the acid The nitride semiconductor film 406 was placed in a nitrogen atmosphere and the substrate temperature reached 600°C. After the above heat treatment, to prevent re-incorporation of moisture or hydrogen, The oxide semiconductor films 405 and 406 are prevented from being exposed to the air.

[0189] The heat treatment device is not limited to an electric furnace, and may be a heat treatment device using heat conduction or heat from a heat source such as a resistance heating element. A device for heating the object to be treated by radiation may be provided. For example, a GRTA (Gas Rapid Thermal Anneal) equipment, LRTA (Lamp Rapid RTA (Rapid Thermal Anneal) equipment, etc. The LRTA device can be used with halogen lamps, metal halide lamps, etc. lamp, xenon arc lamp, carbon arc lamp, high pressure sodium lamp, high pressure A device that heats the workpiece by radiating light (electromagnetic waves) emitted from a lamp such as a mercury lamp. The GRTA device is a device that uses high-temperature gas for heat treatment. An inert gas that does not react with the material to be treated by heat treatment, such as a rare gas such as argon or nitrogen. Sexual gases are used.

[0190] For example, the substrate is transferred into an inert gas heated to a high temperature of 650°C to 700°C as a heat treatment. After heating for several minutes, the substrate is removed from the inert gas heated to a high temperature. GRTA can be used to perform high-temperature heat treatment in a short time.

[0191] In the heat treatment, nitrogen or a rare gas such as helium, neon, or argon is used. It is preferable that the nitrogen introduced into the heat treatment device does not contain oxygen or hydrogen. Or the purity of rare gases such as helium, neon, and argon must be 6N (99.9999%) or higher. Preferably, the impurity concentration is 7N (99.99999%) or more (i.e., the impurity concentration is 1 ppm or less, It is preferable to set the concentration to 0.1 ppm or less.

[0192] When impurities such as moisture or hydrogen are added to an oxide semiconductor, the 6 V / cm, 12-hour gate bias thermal stress test (BT test), impurities and acids The bonds between the main component of the compound semiconductor are broken by a strong electric field (B: bias) and high temperature (T: temperature). The resulting dangling bonds induce a drift in the threshold voltage (Vth). However, as described above, it is necessary to improve the interface characteristics between the gate insulating film and the oxide semiconductor film. In addition, impurities, particularly moisture and hydrogen, in the oxide semiconductor film are removed as much as possible. A stable transistor is obtained even in the T test.

[0193] Through the above steps, the concentration of hydrogen in the oxide semiconductor film can be reduced and the oxide semiconductor film can be highly purified. This makes it possible to stabilize the oxide semiconductor film. By heat treatment, an oxide semiconductor film with extremely low carrier density and a wide band gap is formed. Therefore, a transistor can be fabricated using a large-area substrate. Therefore, mass productivity can be improved. By using a semiconductor film, it is possible to achieve high voltage resistance, low short channel effect, and high on-off ratio. Therefore, it is possible to fabricate a high-performance transistor.

[0194] When the oxide semiconductor film is heated, the temperature may vary depending on the material of the oxide semiconductor film and heating conditions. Plate-like crystals may be formed on the surface of the oxide semiconductor film. It is preferable that the single crystal has a c-axis oriented substantially perpendicular to the crystal. In the core formation region, the ab planes of each crystal coincide, or the a axis or the b axis coincides throughout. In addition, it is preferable that the oxide semiconductor film is a polycrystalline body with its c-axis oriented substantially perpendicular to the surface of the oxide semiconductor film. Note that when the base surface of the oxide semiconductor film has unevenness, the plate-like crystals become polycrystalline.

[0195] Next, as shown in FIG. 10C, the gate insulating film 403, the oxide semiconductor film 405, and the oxide On the semiconductor film 406, a source electrode and a drain electrode (wires formed in the same layer as this) are formed. and then patterning the conductive film to form an oxide semiconductor film. A source electrode 407 and a drain electrode 408 are formed on the oxide semiconductor film 405, and a source electrode 408 is formed on the oxide semiconductor film 406. An electrode 409 and a drain electrode 410 are formed by forming a conductive film using a sputtering method or a vacuum evaporation method. The source and drain electrodes (wiring formed in the same layer as this) can be formed by deposition. The material of the conductive film (including the conductive film) is selected from Al, Cr, Cu, Ta, Ti, Mo, and W. The above elements, or alloys containing the above elements, or alloy films of a combination of the above elements In addition, Cr, Ta, Ti may be applied to the underside or the top side of a metal film such as Al or Cu. It may also be configured by laminating high melting point metal films such as Si, Ti, Ta, etc. , W, Mo, Cr, Nd, Sc, Y, etc., prevent the occurrence of hillocks and whiskers that occur in Al films. By using Al material with added insulating elements, it is possible to improve heat resistance. do.

[0196] The conductive film may have a single layer structure or a stacked structure of two or more layers. a single-layer structure of an aluminum film containing titanium; a two-layer structure of a titanium film laminated on an aluminum film; A film is then laminated on top of the Ti film, an aluminum film is then laminated on top of that, and a Ti film is then formed on top of that. Examples include a three-layer structure.

[0197] Also, the conductive layer that becomes the source electrode and the drain electrode (including the wiring formed in the same layer as these) The film may be formed of a conductive metal oxide. In2O3, tin oxide (SnO2), zinc oxide (ZnO), indic oxide Tin oxide alloy (In2O3-SnO2, abbreviated as ITO), indium oxide zinc oxide alloy (In2O3-ZnO) or the metal oxide material containing silicon or silicon oxide The mixture can be used.

[0198] When a heat treatment is performed after forming the conductive film, the conductive film must have heat resistance to withstand this heat treatment. It is preferable that:

[0199] Then, a resist mask is formed on the conductive film, and selective etching is performed to form the source electrode 4 407 and drain electrode 408, and source electrode 409 and drain electrode 410 were formed. Thereafter, the resist mask is removed.

[0200] In the photolithography process, ultraviolet light and KrF laser light are used for exposure when forming resist masks. The oxide semiconductor film 405 and the oxide semiconductor film 406 are adjacent to each other. The width of the gap between the bottom end of the source electrode and the bottom end of the drain electrode determines the width of the transistor to be formed later. The channel length L of the photoresist is determined. Note that when exposure is performed with a channel length L of less than 25 nm, In the photolithography process, when forming a resist mask, the size is extremely small, ranging from several nm to several tens of nm. Extreme ultraviolet light with a short wavelength is used for exposure. Extreme ultraviolet light exposure provides high resolution and a large depth of focus. The channel length L of the transistor can be set to 10 nm or more and 1000 nm or less. The operating speed can be increased, and the off-current value is extremely small, so power consumption can also be reduced. This can be done.

[0201] Note that when the conductive film is etched, the oxide semiconductor film 405 and the oxide semiconductor film 406 are formed. The materials and etching conditions are adjusted appropriately so that as little as possible is removed.

[0202] In this embodiment, a titanium film is used as the conductive film, and a solution containing ammonia and hydrogen peroxide (ammonia) is used. The conductive film is wet-etched using ammonia hydrogen peroxide (ammonia hydrogen peroxide) to form the source electrode 407 and A source electrode 409 and a drain electrode 410 are formed on the gate electrode 404. The solution containing hydrogen peroxide is specifically 31% by weight of hydrogen peroxide and 28% by weight of ammonium peroxide. An aqueous solution of ammonium hydroxide and water in a volume ratio of 5:2:2 is used. Alternatively, chlorine (Cl2 The conductive film may be dry-etched using a gas containing fluorine (BCl3), boron chloride (BCl3), or the like. stomach.

[0203] By the above patterning, a source electrode 407 and a drain electrode 408 are formed, and a source electrode 409 and the drain electrode 410, the island-shaped oxide semiconductor film 405, the oxide semiconductor The exposed portion of the film 406 is partially etched to form a groove (recess). In addition, a source electrode 407 and a drain electrode 408, and a source electrode 409 and a drain electrode 409 are also provided. A resist mask for forming the inner electrode 410 may be formed by an ink-jet method. When a resist mask is formed by the inkjet method, a photomask is not used, so the manufacturing process is This reduces manufacturing costs.

[0204] In addition, in order to reduce the number of photomasks and steps used in the photolithography process, A resist mask formed by a multi-tone mask that gives the applied light multiple levels of intensity is used. The resist mask formed using the multi-tone mask may be formed by etching a plurality of resist masks. The shape can be further modified by etching. Therefore, it can be used in multiple etching processes to process different patterns. A single multi-tone mask can be used to create a register that corresponds to at least two different patterns. Therefore, the number of exposure masks can be reduced, and the corresponding The photolithography process can also be eliminated, which simplifies the process.

[0205] Next, plasma treatment is performed using gases such as N2O, N2, or Ar. The annealing process removes adsorbed water and other substances adhering to the exposed surface of the oxide semiconductor film. Alternatively, the plasma treatment may be performed using a mixed gas of oxygen and argon.

[0206] After the plasma treatment, as shown in FIG. 10(D), the source electrode 407 and the drain electrode a source electrode 409, a drain electrode 410, and an oxide semiconductor film 405 An insulating film 411 is formed to cover the oxide semiconductor film 406. It is desirable that the film contains as little impurities as possible, such as moisture and hydrogen, and may be a single-layer insulating film. Alternatively, the insulating film 411 may be formed by stacking a plurality of insulating films. The hydrogen penetrates into the oxide semiconductor film or extracts oxygen from the oxide semiconductor film. The back channel of the oxide semiconductor film becomes low-resistance (n-type), and a parasitic channel is formed. Therefore, the insulating film 411 should be a film that contains as little hydrogen as possible. It is particularly important that hydrogen is not used in the film formation method. For example, silicon nitride film, nitride film, etc. are used as insulating films with high barrier properties. A silicon oxide film, an aluminum nitride film, an aluminum nitride oxide film, or the like can be used. When a plurality of laminated insulating films are used, the insulating film having a high barrier property is more likely to have a high nitrogen content than the insulating film having a high barrier property. The insulating film such as a silicon oxide film or a silicon oxynitride film with a low content is formed on the oxide semiconductor film 405, the oxide The insulating film having a low nitrogen content is formed on the side closer to the nitride semiconductor film 406. Then, the source electrode 407 and the drain electrode 408, the source electrode 409 and the drain electrode 4 10, and the oxide semiconductor film 405 and the oxide semiconductor film 406. By using an insulating film with high barrier properties, the oxide semiconductor film 405 and the In the oxide semiconductor film 406, in the gate insulating film 403, or in the oxide semiconductor film 405 and the oxide Impurities such as moisture or hydrogen enter the interface between the compound semiconductor film 406 and other insulating films and the vicinity thereof. In addition, the oxide semiconductor film 405 and the oxide semiconductor film 406 can be prevented from being absorbed. By forming an insulating film such as a silicon oxide film or a silicon oxynitride film with a low nitrogen ratio, The insulating film made of a material with high barrier properties is directly formed on the oxide semiconductor film 405 and the oxide semiconductor film 40 It can prevent contact with 6.

[0207] In this embodiment, a silicon oxide film having a thickness of 200 nm is formed by sputtering. The insulating film 411 has a structure in which a silicon nitride film having a thickness of 100 nm formed by a method is laminated. The substrate temperature during film formation may be set to a temperature between room temperature and 300° C. Set the temperature to 100°C.

[0208] Note that heat treatment may be performed after the insulating film 411 is formed. , ultra-dry air (water content is 20 ppm or less, preferably 1 ppm or less, preferably 10 It is preferable to use it under an atmosphere of air (less than ppb) or rare gas (argon, helium, etc.). The temperature is preferably 200°C or higher and 400°C or lower, for example, 250°C or higher and 350°C or lower. In this embodiment, for example, a heat treatment is performed at 250°C for 1 hour in a nitrogen atmosphere. The electrode 407 and the drain electrode 408, and the source electrode 409 and the drain electrode 410 are formed. Before the formation of the oxide semiconductor film, the oxide semiconductor film was subjected to high-temperature RTA for a short time, similar to the heat treatment performed on the oxide semiconductor film. The oxide semiconductor film may be subjected to heat treatment. Even if oxygen vacancies occur in the film 405 and the oxide semiconductor film 406, the source electrode 40 an exposed region of the oxide semiconductor film 405 provided between the gate electrode 7 and the drain electrode 408 and a region containing oxygen After the insulating film 411 containing the source electrode 409 and the drain electrode 41 is formed in contact with each other, 0, an exposed region of the oxide semiconductor film 406 is in contact with the insulating film 411 containing oxygen. After the oxide semiconductor film 405 is formed, heat treatment is performed. Oxygen is supplied to the oxide semiconductor film 406. Oxygen is provided to the region of 406 in contact with the insulating film 411, and oxygen vacancies that become donors are formed. As a result, it is possible to reduce the amount of oxide semiconductor and achieve a structure that satisfies the stoichiometric composition ratio. The oxide semiconductor film 405 and the oxide semiconductor film 406 can be made i-type or substantially i-type. The electrical characteristics of the transistor can be improved and the variations in the electrical characteristics can be reduced. The timing of the heat treatment is not particularly limited as long as it is performed after the insulating film 411 is formed. Heat treatment during the process, such as heat treatment during resin film formation, or heat treatment to reduce the resistance of transparent conductive films By making the heat treatment for the purpose of the above-mentioned heating treatment also serve as the heating treatment for the purpose of the above-mentioned heating treatment, the number of steps can be reduced without increasing. The oxide semiconductor film 405 and the oxide semiconductor film 406 are made i-type or substantially i-type. This can be done.

[0209] FIG. 11A shows a top view of the memory device after the steps shown in FIG. 10D have been completed. The cross-sectional view taken along the dashed line A1-A2 in FIG. 11(A) corresponds to FIG. 10(D).

[0210] Next, a contact hole 412 is formed in the insulating film 411 by etching or the like. 10(E), a part of the insulating film 411 is exposed. After forming a conductive film, the conductive film is patterned to overlap the oxide semiconductor film 406. After forming the back gate electrode 413 at the position where the back gate electrode 413 is to be formed, An insulating film 414 is formed. The back gate electrode 413 is formed in the contact hole 412. The back gate electrode 413 is connected to the gate electrode 401, Gate electrode 402, or source electrode 407 and drain electrode 408, source electrode 409 The gate electrode 410 can be formed using the same material and structure as the drain electrode 410 .

[0211] The thickness of the back gate electrode 413 is 10 nm to 400 nm, preferably 100 nm to 20 In this embodiment, a structure in which a titanium film, an aluminum film, and a titanium film are stacked is used. After forming a conductive film having a structure, a resist mask is formed by photolithography or the like. Then, unnecessary portions are removed by etching to process the conductive film into a desired shape (patterning). By this, the back gate electrode 413 is formed.

[0212] The insulating film 414 prevents moisture, hydrogen, and the like in the atmosphere from affecting the characteristics of the transistor. It is desirable to use a material with high barrier properties that can prevent the The insulating film may be a silicon nitride film, a silicon nitride oxide film, an aluminum nitride film, or an aluminum nitride oxide film. A single layer or laminated layer of aluminum film is formed by plasma CVD or sputtering. To obtain a barrier effect, the insulating film 414 may be formed to a thickness of, for example, 15 nm. It is preferable to form the film with a thickness of 100 to 400 nm.

[0213] In this embodiment, a 300 nm insulating film is formed by plasma CVD. The film formation conditions are as follows: The flow rate of silane gas was set to 4 sccm, and the flow rate of nitrous oxide (NO) was set to 800 sccm. The substrate temperature is set to 400°C.

[0214] Through the above steps, the transistor 420 functioning as a switching element and the memory element A transistor 421 functioning as a capacitor and a capacitor 430 are formed. 10(E) shows a top view of the memory cell shown in FIG. 11(B). This corresponds to the cross-sectional view at -A2.

[0215] The transistor 420 includes a gate electrode 401 formed on a substrate 400 having an insulating surface. 4, a gate insulating film 403 on the gate electrode 401, and a gate electrode 402 on the gate insulating film 403. The oxide semiconductor film 405 overlapping the electrode 401 and the oxide semiconductor film 405 formed thereon The transistor 4 has a pair of source electrodes 407 and drain electrodes 408. 20 may include an insulating film 411 formed over an oxide semiconductor film 405 as a component. The transistor 420 shown in FIG. 10(E) has a source electrode 407 and a drain electrode 40 8, a channel-etched structure in which part of the oxide semiconductor film 405 is etched is formed. be.

[0216] Note that although the transistor 420 has been described as a single-gate transistor, If necessary, a plurality of electrically connected gate electrodes 401 may be provided to form a channel. A transistor having a multi-gate structure having multiple regions can also be formed.

[0217] The transistor 421 has a gate electrode 4 formed on a substrate 400 having an insulating surface. 402, a gate insulating film 403 on the gate electrode 402, and a gate insulating film 404 on the gate insulating film 403. The oxide semiconductor film 406 overlapping the gate electrode 402 and the oxide semiconductor film 406 are formed on the oxide semiconductor film 406. The pair of source and drain electrodes 409 and 410 are connected to the oxide semiconductor film 406 and the An insulating film 411 is formed on the source electrode 409 and the drain electrode 410. In the back gate electrode 404, the oxide semiconductor film 406 and the gate electrode 402 overlap with each other. 13. Furthermore, the transistor 421 has a back gate electrode 413 formed thereon. The insulating film 414 may be included as a component of the transistor 4 shown in FIG. 21 is a film of the oxide semiconductor film 406 between the source electrode 409 and the drain electrode 410. This is a channel etch structure in which a portion is etched.

[0218] Note that although the transistor 421 has been described as a single-gate transistor, Optionally, a plurality of electrically connected gate electrodes 402 may be provided to facilitate channel formation. A transistor having a multi-gate structure having multiple regions can also be formed.

[0219] The capacitor 430 is connected between the source electrode 409 and the back gate electrode of the transistor 421. 413 are formed in an area where they overlap with each other with the insulating film 411 sandwiched therebetween.

[0220] The gate electrode 402 of the transistor 421 controls the potential of the gate electrode 402. The operation as a memory element, such as writing, reading, retaining, and erasing, can be selected. The back gate electrode 413 functions as a first electrode. In this way, the threshold voltage of the transistor 421 used as a memory element can be controlled. , which functions as a second gate electrode. In the transistor 421, the gate electrode 402 formed before the oxide semiconductor film 406 is The back gate electrode 413 formed after the first electrode and the oxide semiconductor film 406 is connected to the second electrode. Although memory cells used as poles are illustrated, the invention is not limited to this configuration. For example, in the transistor 421 used as a memory element, The gate electrode 402 formed after the oxide semiconductor film 406 is used as the second electrode. It is also possible to operate the back gate electrode 413 as a first electrode. In this case, the gate electrode 402 is used instead of the back gate electrode 413 of the transistor 420. It is connected to the drain electrode 408 .

[0221] In addition, in FIG. 11B, the back gate electrode 413 covers the entire oxide semiconductor film 406. However, the present invention is not limited to this configuration. The oxide semiconductor film 406 includes a channel formation region 3 at least partially overlapping the oxide semiconductor film 406. That's good.

[0222] The band gap of oxide semiconductors is 3.0 to 3.5 eV. The band gap of gallium nitride is 3.39 eV, and Both have a band gap approximately three times larger than that of silicon. Compound semiconductors such as silicon and gallium nitride are wide-gap semiconductors. The wide band gap characteristic common to oxide semiconductors is a factor in the breakdown voltage of transistors. This is advantageous for improving the efficiency and reducing power loss.

[0223] Next, as in this embodiment, impurities such as moisture or hydrogen contained in the oxide semiconductor film are removed. How removing as much as possible and purifying the oxide semiconductor film affects the characteristics of transistors The impact will be explained below.

[0224] FIG. 12 is a longitudinal cross-sectional view of an inverted staggered transistor using an oxide semiconductor. An oxide semiconductor film (OS) is provided on a gate electrode (GE) via a gate insulating film (GI), and A source electrode (S) and a drain electrode (D) are provided on the An insulating film is provided to cover the inner electrode (D).

[0225] FIG. 13 shows an energy band diagram (schematic diagram) on the line A-A' shown in FIG. In FIG. 13, black circles (●) represent electrons, white circles (○) represent holes, and each represents a charge. It has -q and +q. When a positive voltage (VD>0) is applied to the drain electrode (D), The dashed line indicates when no voltage is applied to the gate electrode (GE) (VG=0), and the solid line indicates when the gate electrode (G This shows the case where a positive voltage (VG>0) is applied to the gate electrode (GE). If there is no potential barrier, the source electrode (S) is This indicates the off state, where no carriers (electrons) are injected into the gate electrode and no current flows. When a positive voltage is applied to (GE), the potential barrier decreases, indicating an on-state in which current flows. .

[0226] FIG. 14 is an energy band diagram (schematic diagram) on line BB' in FIG. 14(A) shows the state where a positive potential (VG>0) is applied to the gate electrode (GE), and the source This shows the on-state where carriers (electrons) flow between the source electrode (S) and the drain electrode (D). Also, FIG. 14(B) shows the state where a negative potential (VG<0) is applied to the gate electrode (GE). and indicates the case where the transistor is in the off state (no minority carriers flow).

[0227] Figure 15 shows the relationship between the vacuum level and the work function (φ M ) and the electron affinity (χ) of the oxide semiconductor Shows.

[0228] At room temperature, electrons in metals are degenerate, and the Fermi level is located within the conduction band. Conventional oxide semiconductors are generally n-type, and in this case the Fermi level (Ef) is Located away from the intrinsic Fermi level (Ei) in the center of the gap and closer to the conduction band (Ec) In the oxide semiconductor, some of the hydrogen acts as a donor, and the oxide semiconductor becomes an n-type It is known that oxygen vacancies are one of the factors that cause n-type It is known that there is.

[0229] In contrast, one embodiment of the present invention is a method for forming an oxide semiconductor by removing hydrogen, which is an n-type impurity, from an oxide semiconductor. The semiconductor is highly purified to minimize the amount of impurities other than the main component of the compound semiconductor, and oxygen deficiency is eliminated. By removing the impurities, the oxide semiconductor is made as close to intrinsic as possible. Instead of adding pure substances to make the oxide semiconductor i-type, impurities such as moisture or hydrogen and oxygen deficiency are added. By removing as much loss as possible and purifying it, it can be made into an i-type (intrinsic semiconductor) or i-type (intrinsic semiconductor) The above structure allows the formation of an oxide semiconductor having a structure as close as possible to the structure shown by the arrow. As shown in Fig. 1, the Fermi level (Ef) approaches the intrinsic Fermi level (Ei) as closely as possible. It can be done.

[0230] The band gap (Eg) of the oxide semiconductor is 3.15 eV and the electron affinity (χ) is 4.3 V. It is said that the work function of titanium (Ti) that constitutes the source and drain electrodes is The electron affinity (χ) of the oxide semiconductor is approximately equal to the electron affinity (χ) of the metal-oxide semiconductor interface. In this case, no Schottky barrier is formed for electrons.

[0231] At this time, the electrons pass through the gate insulating film and the highly purified oxide semiconductor as shown in FIG. The electrons move through the lowest energetically stable part on the oxide semiconductor side at the interface with the oxide semiconductor.

[0232] In addition, in FIG. 14(B), when a negative potential is applied to the gate electrode (GE), the minority capacitance Since the rear hole is substantially zero, the current is close to zero.

[0233] Next, the intrinsic carrier density in the oxide semiconductor was calculated. The band gap of the semiconductor is 3.05 eV, and the intrinsic carrier density is calculated based on this value. The energy distribution f(E) of electrons in a solid is the Fermi-Dirac equation, which is given by the following formula: It is known to follow statistics.

[0234]

number

[0235] In ordinary semiconductors where the carrier density is not extremely high (not degenerate), the following relationship holds: do.

[0236]

number

[0237] Therefore, the Fermi-Dirac distribution in equation (1) can be expressed as the Boltzmann distribution in the following equation: is approximated.

[0238]

number

[0239] Using equation (3), we can calculate the intrinsic carrier density (n i ) gives the following formula:

[0240]

number

[0241] Then, in equation (4), the effective density of states (Nc The values ​​of the intrinsic carrier density were calculated by substituting the values ​​of the valence band (V), the band gap (Eg), and the intrinsic carrier density. The results are shown in Table 1.

[0242] [Table 1]

[0243] In-Ga-Zn-O oxide semiconductors have an extremely low intrinsic carrier density compared to Si. It can be seen that the band gap of In-Ga-Zn-O oxide semiconductor is 3.05e When V is selected, the intrinsic carrier density of Si and In-Ga-Zn-O oxide semiconductors is Assuming that the Fermi-Dirac distribution law is approximately correct, the former has a higher carrier density than the latter. The degree is about 10 17 It can be said to be twice as big.

[0244] Next, a method for measuring the off-state current of a transistor including a highly purified oxide semiconductor film and The results will be explained below.

[0245] Figure 18 shows the configuration of the measurement circuit used in the actual measurement. The measurement circuit shown in Figure 18 is Highly purified oxide semiconductors are used as switching elements to hold the charge in the storage capacitor. Using a transistor having a film, the above The off-state current of the transistor is measured.

[0246] Specifically, the measurement circuit shown in FIG. 18 includes three measurement systems 801-803 for measuring the off-state current. The measurement systems 801-1 to 801-3 are connected in parallel. The measurement system 801-3 includes a capacitance element 802 and a transistor 803 to be measured. Furthermore, the measurement systems 801-1 to 801-3 each have a transistor Each of the transistors 804 to 806 is provided.

[0247] In each measurement system, the gate electrode of the transistor 803 is connected to a node to which a potential Vgb is applied. The source electrode of the transistor 803 is connected to a node to which a potential Vb is applied. The transistor has its gate connected to node A and its drain connected to node B. The gate electrode of 804 is connected to a node to which a potential Vga is applied. The transistor 804 has a source electrode connected to the node A and a drain electrode to which a potential Va is applied. The gate electrode and drain voltage of the transistor 805 are connected to a node. The gate of the transistor 806 is connected to a node to which a potential Va is applied. The source electrode of the transistor 806 is connected to node A, and the source electrode of the transistor 806 is connected to node B. The source electrode of transistor 805 is connected to a node The drain electrode of the transistor 806 is connected to the drain electrode of the transistor 806, and the potential of these two electrodes is The potentials Vout1 to Vout3 are output from each measurement system. One of the pair of electrodes is connected to node A, and the other is connected to a node to which potential Vb is applied. It continues.

[0248] In this embodiment, the transistor 803 to be measured has a highly purified film thickness. A 30 nm thick oxide semiconductor film and a 100 nm thick gate insulating film were used. The channel forming region of the transistor 803 has a channel length L=10 μm and a channel width W=50 μm. The capacitance values ​​of the capacitance elements 802 in each measurement system were 100 fF, The capacitances were set to 1pF and 3pF.

[0249] Before measurement, initialization is performed. First, the potential Vgb is set to a value such that the transistor 803 is turned on. This turns on transistor 803, causing node A to be at the potential V b, i.e., a low level potential VSS is applied. The transistor 803 is turned off by setting the voltage to a level that turns the transistor 803 off. Next, the potential Vga is set to a level that turns on the transistor 804. Therefore, the potential Va, that is, the high-level potential VDD, is applied to the node A, and the capacitance element 8 Between the pair of electrodes of 02, there is a potential difference between the low level potential VSS and the high level potential VDD. After that, the potential Vga is increased so that the transistor 804 is turned off. By setting the voltage at such a high level, transistor 804 is turned off and node A is left floating. The device enters a pinging state.

[0250] Next, the measurement operation is started. When the measurement is performed, the potential Va and the potential Vb are applied to the node A. The height is set so that charge flows in or out from node A. In this state, the potentials Va and Vb are set to a low level potential VSS. At the timing when measuring, the potential Va is temporarily set to the high level potential VDD. However, otherwise, the potentials Va and Vb were maintained at the low level potential VSS.

[0251] Since a small amount of off-current flows through the transistor 803, the voltage held at the node A is gradually increased over time. The amount of charge held at node A fluctuates. Since the potential of A fluctuates, the potentials Vout1 to Vout3 change depending on the off-state potential of the transistor 803. Its height varies according to the value of the current.

[0252] Specifically, in this measurement, the potential VDD was set to 5 V and the potential VSS was set to 0 V. In principle, the potential Va is set to the potential VSS, and the potential is increased by 100 msec every 10 to 300 sec. The potential Va was set to the potential VDD for the period c, and the potentials Vout1 to Vout3 were measured. .

[0253] FIG. 19 shows the relationship between the elapsed time Time and the potential Vout in the current measurement. After about an hour, the change in potential can be seen.

[0254] Beforehand, the potential of node A, V A By finding the relationship between the potential Vout and the potential Vo ut to node A potential V A Generally, the potential V of node A can be calculated. A teeth , can be expressed as a function of the potential Vout as follows:

[0255]

number

[0256] Also, the charge Q at node A A is the potential V of node A A , capacitance C connected to node A A , fixed Using a constant, it is expressed as follows: C A is the capacitance value of the capacitor 802 and other capacitances (transistor 805 and transistor 80 6) and the input capacitance of the circuit.

[0257]

number

[0258] The current I at node A is the time when the charge flows into (or out of) node A. Since it is an inverse differential, the current I at node A can be expressed as follows:

[0259]

number

[0260] In this way, the capacitance C connected to node A A From the potentials Vout1 to Vout3, The current I of the diode A can be calculated.

[0261] 20 shows the off-state current calculated by the above measurement. The time Δt used to calculate the current I was set to approximately 30,000 seconds. This shows the relationship between the voltage V between the source and drain electrodes and the off-current I. When the voltage between the source and drain electrodes is 4 V, the off-state current is approximately 40 A / μm. It can be seen that...

[0262] In this way, impurities such as moisture or hydrogen other than the main components of the oxide semiconductor are contained as little as possible. Thus, by purifying the oxide semiconductor film, the operation of the transistor can be improved. It is possible.

[0263] This embodiment mode can be implemented in appropriate combination with any of the above embodiment modes.

[0264] (Fourth embodiment) In this embodiment, a semiconductor device using a memory device according to one embodiment of the present invention will be described. An example of a strip-type storage medium will be described.

[0265] FIG. 16A illustrates an example of the structure of a storage medium according to one embodiment of the present invention. The storage medium shown in A) is a storage device 701 according to one embodiment of the present invention, a drive device, and a storage medium. A connector 702 for electrical connection and a signal input / output circuit for various signals input / output via the connector 702 , an interface 703 that processes signals according to specifications, and an interface 704 that processes signals according to specifications, such as the operating state of the storage medium. Therefore, the light emitting diode 704 lights up, and the memory device 701, the interface 703, the light emitting diode 704 ... A controller that controls the operation of various circuits and semiconductor elements in the storage medium, such as a photodiode 704. A roller 705 is mounted on a printed wiring board 706. In addition, a controller A quartz crystal used to generate a clock signal to control the operation of the 705, A regulator or the like may be provided to control the level of the power supply voltage within the medium. stomach.

[0266] The printed wiring board 706 shown in FIG. 16(A) is connected to the connector 7 as shown in FIG. 16(B). The cover 707 is made of resin or the like so that the 02 and the light emitting diode 704 are partially exposed. It is also possible to protect it by doing so.

[0267] The memory device 701 according to one embodiment of the present invention can reduce power consumption during operation. This allows for lower power consumption of the storage medium using the storage device 701, and ultimately reduces the storage medium's A driving device connected to the driving circuit can be reduced in power consumption. The storage device 701 can store data for a long period of time and can also write data. This increases the number of times the storage medium can be replaced, thereby improving the reliability of the storage medium. It is possible to retain data for a long period of time and increase the number of times data can be rewritten. This loosens the constraints on the operating conditions of the storage medium, making it possible to increase the versatility of the storage medium. do.

[0268] This embodiment mode can be implemented in appropriate combination with any of the above embodiment modes. [Example]

[0269] By using a semiconductor device according to one embodiment of the present invention, highly reliable electronic devices and low power consumption devices can be realized. It is possible to provide electronic devices with low power consumption and high-speed operation. In the case of portable electronic devices that are difficult to install, the low-power semiconductor device according to one embodiment of the present invention By adding the device to the components, the benefit of continuous use time can be extended. Obtained.

[0270] In addition, in the semiconductor device of the present invention, the temperature of the heat treatment in the manufacturing process can be suppressed. Therefore, the substrate is made of flexible synthetic resin such as plastic, which has lower heat resistance than glass. It is possible to fabricate highly reliable transistors with excellent characteristics even on substrates. Therefore, by using the manufacturing method according to one embodiment of the present invention, a highly reliable, lightweight, and It is possible to provide a flexible semiconductor device. Polyesters, such as ethylene terephthalate (PET), polyethersulfone ( PES), polyethylene naphthalate (PEN), polycarbonate (PC), polyethylene Polyether ketone (PEEK), polysulfone (PSF), polyetherimide (PE I), polyarylate (PAR), polybutylene terephthalate (PBT), polyimide , acrylonitrile butadiene styrene resin, polyvinyl chloride, polypropylene, polyacetic acid vinyl acid, acrylic resin, etc.

[0271] The semiconductor device according to one embodiment of the present invention can be used in a display device, a notebook personal computer, a recording medium, Image playback device equipped with a medium (typically DVD: Digital Versatile (Devices with a display that can play back recording media such as discs and display the images) In addition, a semiconductor device according to one embodiment of the present invention can be used in an electric device. Sub-devices include mobile phones, portable game consoles, personal digital assistants, e-books, video cameras, Digital still camera, goggle-type display (head-mounted display), navigation audio systems, audio playback devices (car audio, digital audio players, etc.) , copiers, facsimiles, printers, printer-combined machines, automated teller machines (A TM), vending machines, etc. Specific examples of these electronic devices are shown in Figure 17.

[0272] FIG. 17A shows a portable game machine, which includes a housing 7031, a housing 7032, a display portion 7033, Display unit 7034, microphone 7035, speaker 7036, operation keys 7037, The semiconductor device according to one embodiment of the present invention is a driving circuit for a portable game machine. It can be used in an integrated circuit for controlling the operation of a portable game console. By using a semiconductor device according to one embodiment of the present invention for an integrated circuit, a highly reliable portable game device can be realized. game consoles, low-power portable game consoles, high-speed portable game consoles, high-performance portable game consoles The portable game machine shown in FIG. 17(A) has two tables. The portable game machine has a display unit 7033 and a display unit 7034. , but is not limited to this.

[0273] FIG. 17B shows a mobile phone, which includes a housing 7041, a display portion 7042, an audio input portion 7043, It has an audio output unit 7044, an operation key 7045, a light receiving unit 7046, etc. By converting the light received in the sensor into an electrical signal, an external image can be captured. A semiconductor device according to one embodiment of the present invention can be used in an integrated circuit for controlling the driving of a mobile phone. The semiconductor device according to one aspect of the present invention can be used in an integrated circuit for controlling the operation of a mobile phone. By using this device, it is possible to produce highly reliable mobile phones, mobile phones with low power consumption, and mobile phones with high speed operation. This allows us to provide high-performance mobile phones.

[0274] FIG. 17C shows a portable information terminal, which includes a housing 7051, a display unit 7052, and operation keys 7053. The portable information terminal shown in FIG. 17C has a modem built in a housing 7051. A semiconductor device according to one embodiment of the present invention may be a semiconductor device for controlling the driving of a portable information terminal. The present invention can be applied to an integrated circuit for controlling the operation of a portable information terminal. By using the semiconductor device according to one embodiment, a highly reliable portable information terminal and a low-power portable information terminal can be provided. It is possible to provide a portable information terminal, a high-speed portable information terminal, and a highly functional portable information terminal.

[0275] This embodiment can be implemented in appropriate combination with the above embodiment modes. [Explanation of symbols]

[0276] 100 memory cells 101 Transistor 102 transistor 103 Capacitor element 110 Substrate 111 Gate electrode 112 insulating film 113 Oxide semiconductor film 114 Source electrode 115 Drain electrode 116 Insulating film 117 Insulating film 121 gate electrode 123 Oxide semiconductor film 124 Source electrode 125 Drain electrode 126 gate electrode 130 lines 131 line 140 PCB 141 gate electrode 142 insulating film 143 Oxide semiconductor film 144 Source electrode 145 Drain electrode 146 Insulating Film 147 Insulating Film 148 Channel protection film 151 gate electrode 153 Oxide semiconductor film 154 Source electrode 155 Drain electrode 156 gate electrode 157 Channel protection film 160 boards 161 gate electrode 162 insulating film 163 Oxide semiconductor film 164 Source electrode 165 Drain electrode 166 Insulating Film 167 Insulating Film 171 gate electrode 173 Oxide semiconductor film 174 Source electrode 175 Drain electrode 176 gate electrode 200 boards 208 Oxide semiconductor film 211 Gate electrode 212 insulating film 213 Oxide semiconductor film 214 Source electrode 215 Drain electrode 216 Insulating film 217 Insulating Film 221 Gate electrode 223 Semiconductor Film 224 Source electrode 225 Drain electrode 226 Gate electrode 230 insulating film 231 Insulating Film 241 gate electrode 242 insulating film 243 Oxide semiconductor film 244 Source Electrode 245 Drain electrode 246 Insulating Film 247 Insulating Film 251 gate electrode 253 Semiconductor Film 254 Source Electrode 255 drain electrode 256 gate electrodes 260 insulating film 261 Insulating Film 270 PCB 300 memory cells 301 Transistor 302 Transistor 303 Capacitor 304 Power line 310_1 Transistor 310_2 Transistor 310_3 Transistor 311_1 Transistor 311_2 Transistor 311_3 Transistor 312_1 Operational amplifier 312_2 Op-amp 312_3 Op-amp 320 transistors 321 Transistor 400 boards 401 Gate electrode 402 gate electrode 403 Gate insulating film 404 Oxide semiconductor film 405 Oxide semiconductor film 406 Oxide semiconductor film 407 Source electrode 408 Drain electrode 409 Source Electrode 410 Drain electrode 411 Insulating film 412 Contact Hole 413 Back gate electrode 414 Insulating film 420 transistors 421 Transistor 430 Capacitor 500 cell array 501 Drive circuit 502 readout circuit 503 Word line driver circuit 504 Data line driving circuit 505 Control circuit 506 Word Line Decoder 508 Data Line Decoder 509 Data Line Selector 701 Storage device 702 Connector 703 Interface 704 Light Emitting Diode 705 Controller 706 Printed Wiring Board 707 Cover material 801-1 Measurement system 801-2 Measurement system 801-3 Measurement system 802 Capacitor element 803 Transistor 804 transistor 805 transistor 806 Transistor 7031 Housing 7032 chassis 7033 Display section 7034 Display section 7035 Microphone 7036 Speaker 7037 Operation Key 7038 Stylus 7041 Housing 7042 Display section 7043 Audio Input Unit 7044 Audio output section 7045 Operation Key 7046 Light receiving section 7051 Housing 7052 Display section 7053 Operation Key

Claims

[Claim 1] A first transistor and a second transistor are included in each of the plurality of memory cells; a channel formation region of the first transistor is located between a first gate electrode and a second gate electrode; a channel formation region of the second transistor includes an oxide semiconductor; The second transistor controls the supply of a potential to the second gate electrode.

Images