Semiconductor device

Abstract

To provide a semiconductor device in which dummy capacitors are arranged around a memory cell array so as to improve possible structural defects of the semiconductor device caused by continuously increased cell-density.SOLUTION: The semiconductor device includes a substrate and a capacitor structure. The substrate includes a periphery region. The capacitor structure is disposed on the substrate and includes a plurality of capacitors arranged in an array, where at least two capacitors physically contact with each other along a direction being horizontal to the substrate. Through these arrangements, the semiconductor device is enabled to improve the possible structural defects of the semiconductor device caused by continuously increased cell-density, by arranging the dummy capacitors around the cell array, so as to obtain a more stable and more reliable structure to achieve better functions and performances.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates generally to semiconductor devices, and more particularly to semiconductor devices that include capacitor structures. [Background technology]

[0002] Due to the trend toward miniaturization of various electronic products, the design of semiconductor devices must also meet the requirements of high integration and density. In the current mainstream development trend, dynamic random access memories (DRAMs) with recessed gate structures are gradually replacing DRAMs with only planar gate structures because they have a longer carrier path for the same semiconductor substrate, reducing the current leakage of the capacitor structure. Generally, a DRAM cell with a recessed gate structure comprises a transistor component and a charge storage device for receiving voltage signals from bit lines and word lines. However, due to the limitations of current handling technology, currently available DRAM cells with recessed gate structures still have many drawbacks and need to be further improved to effectively improve the performance and reliability of associated memory devices. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] U.S. Patent No. 7,923,343 [Patent Document 2] U.S. Patent No. 7,951,668 [Patent Document 3] U.S. Patent No. 8,816,418 [Patent Document 4] U.S. Patent No. 9,153,639 [Patent Document 5] U.S. Patent No. 9,263,536 [Patent Document 6] U.S. Patent No. 9,941,286 [Patent Document 7] U.S. Patent No. 10,249,627 [Patent Document 8] US Patent Application Publication No. 2006 / 0211178 [Patent Document 9] US Patent Application Publication No. 2020 / 0098854 [Patent Document 10] Chinese Patent Application Publication No. 1967809 [Patent Document 11] Chinese Patent No. 111029249 [Patent Document 12] Chinese Utility Model No. 218831177 [Patent Document 13] Chinese Patent Application Publication No. 101911263 Summary of the Invention [Problem to be solved by the invention]

[0004] The objective of the present disclosure is to provide a semiconductor device in which dummy capacitors are arranged around a storage cell array, so as to improve possible structural defects of the semiconductor device caused by continuously increasing cell density, thereby allowing the semiconductor device to obtain a more stable and reliable structure and thereby achieve better function and performance. [Means for solving the problem]

[0005] To achieve the above object, one embodiment of the present disclosure provides a semiconductor device comprising a substrate and a capacitor structure, wherein the capacitor structure is disposed on the substrate and comprises a plurality of capacitors arranged in an array, at least two of the capacitors being in physical contact with each other in a horizontal direction parallel to the substrate.

[0006] To achieve the above object, another embodiment of the present disclosure provides a semiconductor device including a substrate, a capacitor structure, and a support structure. The capacitor structure is disposed on the substrate and includes at least one first capacitor and at least one second capacitor. A bottom surface of a lower electrode layer of the at least one first capacitor is lower than a bottom surface of a lower electrode layer of the at least one second capacitor, and at least one of the at least one first capacitor and the at least one second capacitor has a curved end. A support structure is disposed on the substrate between the capacitors, and the support substrate includes a first support layer and a second support layer that are stacked continuously from bottom to top.

[0007] Overall, according to the semiconductor device of the present disclosure, in order to improve the possible structural defects of the semiconductor device caused by continuously increasing cell density, dummy capacitors are arranged around the storage cell array, and the top electrode layers of the dummy capacitors are in physical contact with each other, the capacitor dielectric layers are in physical contact with each other, and / or the top electrical layers are in physical contact with each other, so that the semiconductor device can achieve a more reliable structure and thereby achieve better function and performance.

[0008] These and other objects of the present invention will no doubt become obvious to those skilled in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.

[0009] The accompanying drawings are intended to provide a better understanding of the embodiments and are included as part of the specification of this disclosure. These drawings and illustrations are used to illustrate the principles of the embodiments. It should be noted that all drawings are schematic, and relative dimensions and scales are adjusted for convenience of illustration. The same or similar features in different embodiments are marked with the same reference numerals. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a schematic top view illustrating a semiconductor device according to a first embodiment of the present disclosure. [Figure 2] 1 is a schematic cross-sectional view illustrating a semiconductor device according to a first embodiment of the present disclosure. [Figure 3] FIG. 4 is a schematic top view illustrating a semiconductor device according to a second embodiment of the present disclosure. [Figure 4] FIG. 4 is a schematic cross-sectional view illustrating a semiconductor device according to a second embodiment of the present disclosure. [Figure 5] FIG. 4 is a schematic diagram illustrating a semiconductor device according to a third embodiment of the present disclosure. [Figure 6] FIG. 10 is a schematic diagram illustrating a semiconductor device according to a fourth embodiment of the present disclosure. [Figure 7] FIG. 10 is a schematic diagram illustrating a semiconductor device according to a fifth embodiment of the present disclosure. [Figure 8] FIG. 10 is a schematic diagram illustrating a semiconductor device according to a sixth embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0011] For better understanding of the present disclosure, preferred embodiments will be described in detail. The preferred embodiments of the present disclosure are shown in the accompanying drawings with numbered elements. In addition, the technical features in the different embodiments described below may be replaced, recombined, or mixed with each other to form other embodiments without departing from the spirit of the present disclosure.

[0012] 1 and 2 are schematic diagrams illustrating a semiconductor device 10 according to a first embodiment of the present disclosure, showing a top view and a cross-sectional view of the semiconductor device 10, respectively. Initially, as shown in FIG. 1 , the semiconductor device 10 includes a substrate 100 and a capacitor structure 150 disposed on the substrate 100. The substrate 100 may be, for example, a silicon substrate, a silicon-containing substrate (e.g., SiC or SiGe), or a silicon-on-insulator (SOI) substrate. The substrate 100 further includes a region with a relatively higher device density, such as a cell region 104, and another region with a relatively lower device density, such as a peripheral region 102. The cell region 104 and the peripheral region 102 may be adjacent to each other, but are not limited thereto. Preferably, but not limited to, the peripheral region 102 is disposed around the periphery of the cell region 104, as shown in FIG. 1 .

[0013] The capacitor structure 150 is disposed on the substrate 100 and includes a plurality of capacitors 140 arranged alternately in a horizontal direction D1 parallel to the substrate 100, the capacitors 140 arranged in an array along the horizontal direction D1 and a vertical direction D2. The capacitors 142 disposed in the cell region 104 are spaced apart from one another by support structures 160 disposed therebetween, so that each capacitor 142 can be electrically connected to a transistor element (not shown in the drawings) in the substrate 100 via an underlying plug (not shown in FIG. 1 ), thereby forming a memory cell array. It should be noted that at least two capacitors 144, 146 disposed in the peripheral region 102 physically contact each other in the horizontal direction D1 to function as dummy capacitors. Therefore, by disposing the dummy capacitors that physically contact each other at the periphery of the memory cell array, the difference in element density between the cell region 104 and the peripheral region 102 is balanced during fabrication of the semiconductor device 10, thereby improving potential structural defects of the semiconductor device caused by continuously increasing cell density. In this way, the semiconductor device 10 can achieve better functionality and performance due to a more reliable structure.

[0014] 1 , the capacitor structure 150 includes a lower electrode layer 152, a capacitor dielectric layer 154, and an upper electrode layer 156 arranged in a horizontal direction D1. To form each capacitor 140, the capacitor dielectric layer 154 is arranged on the side of the lower electrode layer 152, and the upper electrode layer 156 is further arranged on the side of the capacitor dielectric layer 154. In this embodiment, the lower electrode layer 152 includes, for example, a U-shaped lower electrode (shown in FIG. 2 ) having a U-shaped cross-sectional structure, and the upper electrode layer 156 fills the gap between the U-shaped cross sections of the lower electrode layer 152. In one embodiment, the upper electrode layer 156 may optionally include a single-layer structure or a multi-layer structure, and the multi-layer structure of the upper electrode layer 156 is arranged inside and outside the lower electrode layer 152, as shown in FIG. 1 . Therefore, each capacitor 140 is provided with a cylindrical cross-sectional structure, but is not limited thereto. In other embodiments, two capacitors 144 disposed in the peripheral region 102 are in physical contact with each other, such as, but not limited to, through a connecting bottom electrode layer 152, a connecting capacitor dielectric layer 154, or a connecting top electrode layer 156, to function like a dummy capacitor as shown in FIG. 1. Alternatively, at least one capacitor 146 disposed in the peripheral region 102 includes a relatively smaller width W1 in the horizontal direction D1 so as to be able to directly contact another adjacent capacitor 144. Through these arrangements, two or more capacitors 144, 146 in the peripheral region 102 contact each other, optionally through a contacting bottom electrode layer 152, a contacting top electrode layer 156, or a capacitor dielectric layer 154, to function like a dummy capacitor.

[0015] 2, the semiconductor device 10 includes the substrate 100, a capacitor structure 150, and a support structure 160 disposed on the substrate 100 between each of the capacitors 140. The support structure 160 precisely includes, but is not limited to, a first support layer 162 and a second support layer 164 stacked from bottom to top to support the middle and upper portions of each of the capacitors 140, respectively. Note that there is no plug disposed under the capacitor 144 in the peripheral region 102 so that the capacitor 144 does not electrically connect to the transistor element in the substrate 100 and thus functions as a dummy capacitor. The heights from the bottom surfaces of the lower electrode layers 152a, 152b, and 152c of the at least two capacitors 144a, 144b, and 144c to the top surface of the substrate 100 are different in the vertical direction D3. To be precise, the bottom surface of the lower electrode layer 152a of one capacitor 144a is lower than the bottom surface of the lower electrode layer 152b of the other capacitor 144b, and the lower electrode layer 152a of capacitor 144a and / or the lower electrode layer 152b of capacitor 144b have curved edges at their bottoms, but this is not limiting. In another embodiment, the bottom surface of the lower electrode layer 152c of one capacitor 144c is lower than the bottom surfaces of the lower electrode layers 152a, 152b of capacitors 144a, 144b, and the lower electrode layer 152a of capacitor 144a and / or the lower electrode layer 152b of capacitor 144b have curved edges at their bottoms. Through these arrangements, the difference in element density between the cell region 104 and the peripheral region 102 is also balanced during the fabrication of the semiconductor device 10, improving possible structural defects of the semiconductor device caused by continuously increasing cell density. Therefore, the semiconductor device 10 of the present embodiment can achieve a more reliable structure and thereby achieve better functionality and performance.

[0016] 2, the capacitor structure 150 includes a lower electrode layer 152, a capacitor dielectric layer 154, and an upper electrode layer 156, which are stacked successively in a vertical direction D3. In this embodiment, the lower electrode layer 152 includes, for example, a continuously elongated U-shaped cross section, the capacitor dielectric layer 154 is disposed on the sidewalls and the lower surface of the U-shaped cross section of the lower electrode layer 152, and the upper electrode layer 156 fills the gap of the U-shaped cross section of the lower electrode layer 152. Thus, each capacitor 144 disposed in the peripheral region 102 substantially includes, but is not limited to, a cylindrical cross-sectional structure. It should be noted that the curved ends of the lower electrode layers 152a, 152b of the capacitors 144a, 144b are disposed, for example, between the upper surface of the substrate 100 and the first support layer 162, or between the first support layer 162 and the second support layer 164, and each curved end is gradually bent toward the other adjacent capacitor 144c. In one embodiment, the curved ends of the lower electrode layers 152b, 152a, 152c are preferably not in physical contact with the lower electrode layers 152b, 152a, 152c of the adjacent capacitors 144b, 144a, 144c, and the capacitor dielectric layers 154 covering the curved ends are in physical contact with the capacitor dielectrics 154 covering the lower electrode layers 152b, 152a, 152c of the adjacent capacitors 144b, 144a, 144c, as shown in FIG. 2, but are not limited thereto.

[0017] The semiconductor device 10 further includes a plurality of buried gate structures 120 disposed in the substrate 100 and a plurality of plugs 130 disposed in the substrate 100, both of which are in the cell region 104. To be precise, the gate structures 120 extend along a direction in the substrate (not shown in the drawings) to intersect with the shallow trench isolation 112 and the plurality of active regions 114 in the substrate 100. Each of the gate structures 120 further includes a dielectric layer 122, a gate dielectric layer 124, a gate layer 126, and a capping layer 128, which are stacked in succession, and the surface of the capping layer 128 is flush with the upper surface of the substrate 100, so that the gate structures 120 can function like buried word lines (BWLs) of the semiconductor device 10. Each of the plugs 130 further includes a storage node contact 132 and a storage node pad 134 disposed in the substrate 100, with two adjacent ones of the plugs 130 separated from each other by a storage node contact isolation (SCISO) 136 directly above each gate structure 120. In one embodiment, the storage node contacts 132 include an epitaxial material such as, for example, silicon, silicon phosphate (SiP), silicon germanium (SiGe), or germanium, and the storage node pads 134 include a low-resistivity metallic material such as, for example, but not limited to, aluminum (Al), titanium (Ti), copper (Cu), or tungsten (W). In another embodiment, the storage node pads 134 include the same conductive material as the storage node contacts 132, but are not limited to this.

[0018] Through these arrangements, each capacitor 142 disposed in the cell region 104 can be electrically connected to a transistor element in the substrate 100 through an underlying plug 130, and the capacitor 142 and the plug 130 together serve as a minimum memory cell of a storage cell array in a dynamic random access memory (DRAM, not shown in the drawings) for receiving voltage signals from a bit line (BL, not shown in the drawings) and a word line (i.e., gate structure 120). On the other hand, each capacitor 144 disposed in the peripheral region 102 only contacts the underlying insulating layer 138 and cannot be electrically connected to a transistor element in the substrate 100, thereby serving as a dummy capacitor. It should be noted that although the bit lines are not shown in the drawings of this disclosure, one skilled in the art would fully understand that the bit lines are parallel to each other in a direction perpendicular to the word lines (i.e., gate structures 120) due to the bit line contacts (BLCs) disposed underneath to electrically connect to the substrate 100 and the insulating layer (e.g., an oxide-nitride-oxide structure, not shown in the drawings) disposed on the substrate 100 to electrically isolate the gate structures 120 within the substrate.

[0019] According to the first embodiment of the semiconductor device 10, the capacitors in the peripheral region 102 are in physical contact with each other through the connecting bottom electrodes 152, the connecting capacitor dielectric layers 154, and / or the connecting top electrode layers 156 to configure as dummy capacitors. Therefore, the difference in element density between the cell region 104 and the peripheral region 102 is balanced by disposing the dummy capacitors, which improves the possible structural defects of the semiconductor device 10 caused by the continuously increasing cell density. In this way, the semiconductor device 10 can achieve a more reliable structure and thereby achieve better function and performance.

[0020] Those skilled in the art will easily understand that the semiconductor device of the present disclosure is not limited to the above-described embodiments and may include other examples or modifications. The following description details different embodiments of the semiconductor device of the present disclosure. For simplicity, the following description details the differences between different embodiments, and identical features are not repeatedly described. To easily compare the differences between the embodiments, identical components in each of the following embodiments are marked with the same reference numerals.

[0021] 3 and 4 are schematic diagrams illustrating a semiconductor device 20 according to a second embodiment of the present disclosure, showing a top view and a cross-sectional view of the semiconductor device 20, respectively. The difference between the semiconductor device 20 of this embodiment and the semiconductor device 10 of the previous embodiment is mainly, but not limited to, that the capacitor structure 250 includes a bottom electrode layer 252, a capacitor dielectric layer 254, and an top electrode layer 256 that are successively stacked in a horizontal direction D1 to form a plurality of capacitors 240, each having a cylindrical cross section. The bottom electrode layer 252, for example, includes a pillar-shaped bottom electrode, and the capacitor dielectric layer 254 and the top electrode layer 256 continuously cover the outside of the bottom electrode layer 252, thereby surrounding the pillar-shaped bottom electrode.

[0022] The capacitors 240 are arranged in an array in the horizontal direction D1 and the vertical direction D2, with support structures 160 disposed between and supporting the capacitors 242 in the cell region 104. Each of the capacitors 242 may be electrically connected to a transistor device in the substrate 100 through an underlying plug 130 (as shown in FIG. 4 ) to form a storage cell array. Note that at least two capacitors 244, 246 disposed in the peripheral region 102 are in physical contact with each other in the horizontal direction D1 to function like dummy capacitors. In one embodiment, but not limited to, the two capacitors 244 in the peripheral region 102 are in physical contact with each other through a connecting bottom electrode 252, a connecting capacitor dielectric layer 254, and / or a connecting top electrode layer 256 to be configured as a dummy capacitor as shown in FIG. 3 . Alternatively, at least one capacitor 246 in the peripheral region 102 includes a relatively smaller width W1 in the horizontal direction D1, allowing it to directly contact another adjacent capacitor 244. With these arrangements, two or more capacitors 244, 246 in the peripheral region 102 contact each other through connecting upper electrode layers 256, connecting capacitor dielectric layers 254, or connecting lower electrode layers 252 to form a dummy capacitor.

[0023] 4, the heights from the bottom surfaces of the lower electrode layers of at least two capacitors 244a, 244b, and 244c to the top surface of the substrate 100 are at different heights h1, h2, and h3 in the vertical direction D3. To be precise, the bottom surface of the lower electrode layer 252a of the capacitor 244a is lower than the bottom surface of the lower electrode layer 252b of the other capacitor 244b, and the lower electrode layer 252a of the capacitor 244a and / or the lower electrode layer 252b of the capacitor 244b have, but are not limited to, curved edges at their bottoms. Alternatively, the bottom surface of the lower electrode layer 252c of the capacitor 244c is lower than the bottom surfaces of the lower electrode layers 252a and 252b of the capacitors 244a and 244b, and the lower electrode layer 252a of the capacitor 244a and / or the lower electrode layer 252b of the capacitor 244b have, but are not limited to, curved edges at their bottoms.

[0024] According to the semiconductor device 20 of this embodiment, the capacitors 242 in the peripheral region 102 are still in physical contact with each other through the connecting lower electrode layer 252, the connecting capacitor dielectric layer 254, and / or the connecting upper electrode layer 256 to serve as dummy capacitors. With these arrangements, the difference in element density between the cell region 104 and the peripheral region 102 is balanced by placing the dummy capacitors, improving the possible structural defects of the semiconductor device 20 caused by continuously increasing cell density. In this way, the semiconductor device 20 can achieve better function and performance by obtaining a more reliable structure.

[0025] Please refer to FIG. 5, which is a schematic diagram showing a semiconductor device 30 according to a third embodiment of the present disclosure. The structure of the semiconductor device 30 is substantially the same as that of the semiconductor device 10 of the first embodiment described above, and all similarities will not be redundantly described hereinafter. The main difference between the semiconductor device 30 of this embodiment and the semiconductor device 10 of the first embodiment described above is that a capacitor structure 350 includes a lower electrode layer 352, a capacitor dielectric layer 354, and an upper electrode layer 156, which are successively stacked to form a plurality of capacitors 142, 344 in the cell region 104 and the peripheral region 102. It should be noted that at least one of the lower electrode layers 352a, 352b of the capacitors 344a, 344b in the peripheral region 102 includes a discontinuous film at its base.

[0026] To be precise, the lower electrode layer 352a of the capacitor 344a and the lower electrode layer 352b of the capacitor 344b each have two portions that gradually bend toward the adjacent capacitors 344c and 344a on the same side, such that the lower portions of the two portions are not connected to each other. Therefore, the lower electrode layers 352a and 352b of the capacitors 344a and 344b, respectively, have a discontinuous structure, as shown in FIG. 5 . Furthermore, the subsequent capacitor dielectric layers 354 covering the two portions are also not connected to each other because they have a discontinuous structure as shown in FIG. 5 , but are not limited to this. However, in other embodiments, the capacitor dielectric layers 354 covering the two portions may optionally be in physical contact with the capacitor dielectric layers 354 covering the lower electrode layers 352, 352a, and 152 of the adjacent capacitors 344. According to the semiconductor device 30 of this embodiment, the capacitors 342 in the peripheral region 102 are still in physical contact with each other through the connecting lower electrode layer 352, the connecting capacitor dielectric layer 354, and / or the connecting upper electrode layer 156 to serve as dummy capacitors. With these arrangements, the difference in element density between the cell region 104 and the peripheral region 102 is balanced by disposing the dummy capacitors, improving possible structural defects of the semiconductor device 30 caused by continuously increasing cell density. In this way, the semiconductor device 30 of this embodiment can achieve better function and performance by obtaining a more reliable structure.

[0027] 6 is a schematic diagram illustrating a semiconductor device 40 according to a fourth embodiment of the present disclosure. The structure of the semiconductor device 40 is substantially the same as that of the semiconductor device 10 of the first embodiment described above, and all similarities therebetween will not be redundantly described hereinafter. The difference between the semiconductor device 40 of this embodiment and the semiconductor device 10 of the first embodiment described above is mainly that a capacitor structure 450 includes a lower electrode layer 452, a capacitor dielectric layer 454, and an upper electrode layer 156 that are successively stacked to form a plurality of capacitors 142, 444 in the cell region 104 and the peripheral region 102. It should be noted that the lower electrode layer 452a of at least one capacitor 444a in the peripheral region 102 includes a bent end at its bottom that is gradually bent toward another capacitor 144b.

[0028] More precisely, the lower electrode layer 452a of the capacitor 444a includes a curved end that gradually curves toward the adjacent capacitor 144b on one side, while the lower electrode layer 152b of the capacitor 144b also includes a curved end that gradually curves toward the capacitor 444a. That is, the curved end of the lower electrode layer 452a of the capacitor 444a and the curved end of the lower electrode layer 152b of the capacitor 144b are opposite each other and gradually approach each other. As shown in FIG. 6 , the curved end of the lower electrode layer 452a of the capacitor 444a is positioned between the surface of the substrate 100 and the first support layer 162, while the curved end of the lower electrode layer 152b of the capacitor 144b is positioned between the first support layer 162 and the second support layer 164. Additionally, because the curved ends of the lower electrode layers 152b of the capacitors 444a and 144b gradually approach each other, the capacitor dielectric layer 454 covering the lower electrode layer 452a of the capacitor 444a and the capacitor dielectric layer 454 covering the lower electrode layer 152b of the capacitor 144b do not directly contact each other, but this is not limiting. However, in other embodiments, the lower electrode layers of the capacitors 444a and 144a may optionally be in direct contact (not shown in the drawings). According to the semiconductor device 40 of this embodiment, the capacitors 442 in the peripheral region 102 still physically contact each other through the connecting lower electrode layers 452, connecting capacitor dielectric layers 454, and / or connecting upper electrode layers 156 to serve as dummy capacitors. With these arrangements, the difference in density of elements between the cell region 104 and the peripheral region 102 is balanced by placing dummy capacitors, improving the possible structural defects of the semiconductor device 40 caused by continuously increasing cell density. In this way, the semiconductor device 40 can obtain a more reliable structure and thereby achieve better function and performance.

[0029] 7 is a schematic diagram illustrating a semiconductor device 50 according to a fifth embodiment of the present disclosure. The structure of the semiconductor device 50 is substantially the same as that of the semiconductor device 10 of the first embodiment described above, and all similarities will not be redundantly described hereinafter. The difference between the semiconductor device 50 of this embodiment and the semiconductor device 10 of the first embodiment described above is mainly that a capacitor structure 550 includes a lower electrode layer 552, a capacitor dielectric layer 554, and an upper electrode layer 156 that are successively stacked to form a plurality of capacitors 142, 544 in the cell region 104 and the peripheral region 102. It should be noted that the lower electrode layer 152a of at least one capacitor 144a in the peripheral region 102 includes a bent end at its bottom that is gradually bent toward the other capacitors 544a.

[0030] More precisely, capacitor 544a extends in vertical direction D3, is disposed on substrate 100, and includes a U-shaped cross section through which lower electrode layer 552a extends continuously. Lower electrode layer 152a of capacitor 144a and lower electrode layer 552b of capacitor 544b each include a curved end that is gradually bent toward capacitor 544a such that vertically extending capacitor 544a is sandwiched between capacitor 144a and capacitor 544b at the curved end. Also, as shown in FIG. 7, because the lower electrode layer 552a of the capacitor 544a has a width W2 that is relatively smaller than the width of the other capacitors 544b, the curved end of the lower electrode layer 152a of the capacitor 144a and the curved end of the lower electrode layer 552b of the capacitor 544b gradually approach each other and come into physical contact with the lower electrode layer 552a of the capacitor 544a, with the lower electrode layer 552a of the capacitor 544a being sandwiched between the curved ends. However, in other embodiments, the curved end of the bottom electrode layer 152a of the capacitor 144a and the curved end of the bottom electrode layer 552b of the capacitor 544b may gradually approach the bottom electrode layer 552a of the capacitor 544a but not be in physical contact with the bottom electrode layer 552a, so that the capacitor dielectric layer covering the bottom electrode layer 152a of the capacitor 144a, the capacitor dielectric layer covering the bottom electrode layer 552b of the capacitor 444b, and the capacitor dielectric layer covering the bottom electrode layer 552a of the capacitor 444a are connected and in contact with each other, but are not limited to this. According to the semiconductor device 50 of this embodiment, the capacitors 542 in the peripheral region 102 are still in physical contact with each other through the connecting bottom electrode layers 552, the connecting capacitor dielectric layers 554, and / or the connecting top electrode layers 156 to serve as dummy capacitors. With these arrangements, the difference in density of elements between the cell region 104 and the peripheral region 102 is balanced by placing dummy capacitors, improving the possible structural defects of the semiconductor device 50 caused by continuously increasing cell density. In this way, the semiconductor device 50 can obtain a more reliable structure and thereby achieve better function and performance.

[0031] 8 is a schematic diagram illustrating a semiconductor device 60 according to a sixth embodiment of the present disclosure. The structure of the semiconductor device 60 is substantially the same as that of the semiconductor device 10 of the aforementioned first embodiment, and all similarities therebetween will not be redundantly described hereinafter. The difference between the semiconductor device 60 of this embodiment and the semiconductor device 10 of the aforementioned first embodiment is mainly that a capacitor structure 650 includes a lower electrode layer 652, a capacitor dielectric layer 654, and an upper electrode layer 156 that are successively stacked to form a plurality of capacitors 642, 644 in the cell region 104 and the peripheral region 102. It should be noted that the bottom electrode layer 652a of at least one capacitor 644a in the peripheral region 102 includes a curved end that gradually bends toward the other capacitor 644b, while the bottom electrode layer 652c of at least one capacitor 644c in the cell region 104 also includes a curved end that gradually bends toward the capacitor 644b, with the bottoms of the bottom electrode layers 652a, 652c still being in physical contact by the underlying insulating layer 138 or plug 130.

[0032] More precisely, the capacitors 642, 644a disposed in the cell region 104 and the peripheral region 102, respectively, extend across the substrate 100 in the vertical direction D3. The curved ends of the lower electrode layers 652a, 652c of the capacitors 642, 644a are positioned between the surface of the substrate 100 and the first support layer 162 to substantially present a continuously extending U-shaped cross section, as shown in FIG. 8 . The curved end of the lower electrode layer 652a of the capacitor 644a is preferably close to but not physically contacting the lower electrode layer 652b of the adjacent capacitor 644b so that the capacitor dielectric layers 654 covering the lower electrode layers 652a, 652b of the capacitors 644a, 644b are connected and in contact with each other, but this is not limiting. However, in other embodiments, the lower electrode layers 652a, 652b of the capacitors 644a, 644b may be in direct contact with each other. Thus, the capacitors 642 located in the cell region 104 are still aligned with the corresponding underlying plugs to form the memory cell array, while the capacitors 644a, 644b, and 144b located in the peripheral region 102 contact the insulating layer 138 to serve as dummy capacitors.

[0033] According to the semiconductor device 60 of this embodiment, the capacitors 642 in the peripheral region 102 are still in physical contact with each other through the connecting lower electrode layer 652, the connecting capacitor dielectric layer 654, and / or the connecting upper electrode layer 156 to serve as dummy capacitors. With these arrangements, the difference in element density between the cell region 104 and the peripheral region 102 is balanced by placing the dummy capacitors, improving the possible structural defects of the semiconductor device 60 caused by continuously increasing cell density. In this way, the semiconductor device 60 can achieve better function and performance by obtaining a more reliable structure. Furthermore, those skilled in the art will recognize that although the semiconductor device 60 of this embodiment includes capacitors 644a, 644b, and 144b in the peripheral region 102 serving as dummy capacitors, the practical structure of the dummy capacitors is not limited to that shown in FIG. 8 and may include capacitors 544a and 544b as shown in FIG. 7 serving as dummy capacitors, capacitor 444a as shown in FIG. 6 serving as dummy capacitors, or capacitors 344a, 344b, and 344c as shown in FIG. 5 serving as dummy capacitors, depending on the requirements of a particular product. The bottom electrode layer of the aforementioned capacitors may or may not contact the bottom electrode layer 652c of an adjacent capacitor 642, as needed, to obtain a more reliable structure.

[0034] Overall, according to the semiconductor device of the present disclosure, optionally, in order to improve possible structural defects of the semiconductor device caused by continuously increasing cell density, dummy capacitors are disposed around the storage cell array, and the top electrode layers of the dummy capacitors are in physical contact with each other, the capacitor dielectric layers are in physical contact with each other, and / or the top electrical layers are in physical contact with each other, so that the semiconductor device of the present disclosure can achieve better function and performance by obtaining a more reliable structure.

[0035] Those skilled in the art will readily appreciate that numerous modifications and alterations to the devices and methods may be made while retaining the teachings of the present invention. Accordingly, the foregoing disclosure should be construed as limited only by the metes and bounds of the appended claims. [Explanation of symbols]

[0036] 10 Semiconductor Devices 100 boards 102 Surrounding Area 104 cell area 120 Buried gate structure 130 plug 132 Storage Node Contact 134 Storage Node Pad 136 Storage Node Contact Isolation, SCISO 140, 142, 144, 144a, 144b, 144c, 146 capacitors 150 Capacitor Structure 152, 152a, 152b, 152c Lower electrode layer 154 Capacitor dielectric layer, capacitor dielectric 156 Upper electrode layer 160 Support structure 162 First Support Group 164 Second Support Group 20 Semiconductor Devices 240, 242, 244, 244a, 244b, 244c, 246 capacitors 250 Capacitor Structure 252, 252a, 252b, 252c lower electrode layer 254 Capacitor Dielectric Layer 256 Upper electrode layer 30 Semiconductor Devices 344, 344a, 344b, 344c capacitors 350 Capacitor Structure 352, 352a, 352b bottom electrode layer 354 Capacitor Dielectric Layer 40 Semiconductor Devices 444, 444a capacitor 450 Capacitor Structure 452, 452a Lower electrode layer 454 Capacitor Dielectric Layer 50 Semiconductor Devices 542, 544, 544a, 544b capacitors 552, 552a, 552b bottom electrode layer 554 Capacitor Dielectric Layer 60 Semiconductor Devices 642, 644, 644a, 644b, 644c capacitors 650 Capacitor Structure 652, 652a, 652c lower electrode layer 654 Capacitor Dielectric Layer D1 horizontal direction D2 Vertical direction D3 Vertical direction h1, h2, h3 height W1 Width of capacitor 146, width of capacitor 246 W2 Width of the lower electrode layer 552a

Claims

1. A substrate; a capacitor structure disposed on the substrate and comprising a plurality of capacitors arranged in an array, at least two of the capacitors being in physical contact with each other in a horizontal direction parallel to the substrate; A semiconductor device comprising:

2. The semiconductor device of claim 1 , wherein each of the capacitors comprises a lower electrode layer, a capacitor dielectric layer, and an upper electrode layer arranged successively along the horizontal direction.

3. The semiconductor device of claim 2 , wherein the bottom electrode layers of at least two of the capacitors are in physical contact with each other.

4. The semiconductor device of claim 2 , wherein the top electrode layers of at least two of the capacitors are in physical contact with each other.

5. The semiconductor device of claim 2 , wherein the capacitor dielectric layers of at least two of the capacitors are in physical contact with each other.

6. The semiconductor device of claim 1 , wherein at least two of the capacitors are of different widths in the horizontal direction.

7. A substrate; a capacitor structure disposed on the substrate, the capacitor structure comprising at least one first capacitor and at least one second capacitor, wherein a bottom surface of a bottom electrode layer of the at least one first capacitor is lower than a bottom surface of a bottom electrode layer of the at least one second capacitor, and at least one of the at least one first capacitor and the at least one second capacitor comprises a curved end; a support structure disposed on the substrate between the at least one first capacitor and the at least one second capacitor, the support structure comprising a first support layer and a second support layer stacked successively from bottom to top; A semiconductor device comprising:

8. The semiconductor device of claim 7 , wherein the bottom electrode layer of the at least one first capacitor bends toward one side of the at least one second capacitor.

9. The semiconductor device of claim 7 , wherein the bottom electrode layer of the at least one second capacitor is bent toward one side of the at least one first capacitor.

10. 8. The semiconductor device of claim 7, wherein a bottom surface of the curved end of the bottom electrode layer of the at least one second capacitor is disposed between the first support layer and the second support layer.

11. The semiconductor device of claim 7 , wherein a bottom surface of the curved end of the bottom electrode layer of the at least one second capacitor is disposed between the first support layer and the substrate.

12. The semiconductor device of claim 7 , wherein the bottom electrode layer of the at least one second capacitor comprises a discontinuous substructure.

13. The semiconductor device of claim 7 , wherein the at least one first capacitor and the at least one second capacitor each comprise a cylindrical cross-sectional structure.

14. The semiconductor device of claim 7 , wherein the bent end of the bottom electrode layer of the at least one second capacitor is not in physical contact with the bottom electrode layer of the at least one first capacitor.

15. 15. The semiconductor device of claim 14, wherein a capacitor dielectric layer disposed on the lower electrode layer of the at least one first capacitor is in physical contact with a capacitor dielectric layer disposed on the lower electrode layer of the at least one second capacitor.

16. 15. The semiconductor device of claim 14, wherein a capacitor dielectric layer disposed on the lower electrode layer of the at least one first capacitor is not in physical contact with a capacitor dielectric layer disposed on the lower electrode layer of the at least one second capacitor.

17. The semiconductor device of claim 7 , wherein the bottom electrode layer of the at least one first capacitor is in physical contact with the bottom electrode layer of the at least one second capacitor.

18. 8. The semiconductor device of claim 7, wherein a width of the bottom electrode layer of the at least one first capacitor is different from a width of the bottom electrode layer of the at least one second capacitor.

19. 8. The semiconductor device of claim 7, wherein the bottom electrode layer of the at least one first capacitor includes the curved end, and the bottom electrode layer of the at least one second capacitor is disposed vertically on the substrate.

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