Semiconductor device

Abstract

To provide a semiconductor device with which product-sum computation can be performed with little power consumption.SOLUTION: An arithmetic circuit 110 is a semiconductor device for processing a plurality of signals zm(k-1) inputted to a plurality of k-th layer neurons Nn(k) and generating a plurality of zn(k) outputted from each of the plurality of neurons Nn(k). A circuit ILD is electrically connected to a plurality of wirings IL[n] and a plurality of wirings ILB[n], a circuit WLD is electrically connected to a plurality of wirings WLS[m], a circuit XLD is electrically connected to a plurality of wirings XLS[m], and a circuit AFP is electrically connected to a plurality of wirings OL[n] and a plurality of wirings OLB[n]. An array unit ALP has m×n circuits MP, and is arranged in a m row by n column matrix and electrically connected to, for example, a wiring IL[j], a wiring ILB[j], a wiring WLS[i], a wiring XLS[i], a wiring OL[j], and a wiring OLB[j].SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a semiconductor device and an electronic device.

[0002] Note that one embodiment of the present invention is not limited to the above technical fields. The technical field relates to an article, a method, or a manufacturing method. Process, machine, manufacture, or composition of matter Therefore, the technology of one embodiment of the present invention disclosed in this specification more specifically relates to the above. Fields include semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, power storage devices, imaging devices, Storage device, signal processing device, processor, electronic device, system, driving method thereof, Examples of the manufacturing method and the inspection method thereof are as follows. [Background technology]

[0003] Currently, the development of integrated circuits that mimic the mechanisms of the human brain is progressing vigorously. The brain's mechanisms are incorporated as electronic circuits, and the brain's "neurons" and "systems" are connected. Therefore, such an integrated circuit is called a "neuromorph." It is also sometimes called "brain-morphic," "brain-inspired," or "brain-morphic." The integrated circuit has a non-von Neumann architecture, and power consumption decreases as processing speed increases. Compared to the larger von Neumann architecture, parallel processing can be performed with extremely low power consumption. It is expected that this will be possible.

[0004] The information processing model that mimics a neural network with "neurons" and "synapses" is called artificial neural network. These are called neural networks (ANNs). For example, see Non-Patent Document 1 and Non-Patent Document 2 uses SRAM (Static Random Access Memory) The document discloses a computing device that configures an artificial neural network. [Prior art documents] [Non-patent literature]

[0005] [Non-Patent Document 1] M. Kang et al., “IEEE Journal Of Solid-State Circuits”, 2018, Volume 53, No.2, p.642-655. [Non-patent document 2] J. Zhang et al., “IEEE Journal Of Solid-State Circuits”, 2017, Volume 52, No.4, p.915-924. Summary of the Invention [Problem to be solved by the invention]

[0006] In artificial neural networks, the strength of the synapse that connects two neurons is called the Multiply the signal transmitted between two neurons by the degree (sometimes called a weighting coefficient) In particular, in a hierarchical artificial neural network, the first layer consists of multiple first The strength of each synaptic connection between the neuron and one of the second neurons in layer 2, Each signal input from multiple first neurons in the first layer to one of the second neurons in the second layer It is necessary to multiply and add the numbers, and depending on the scale of the artificial neural network, For example, the number of connection strengths and the number of parameters that represent the signal are determined. The more layers and neurons in a neural network, the more "neurons" and The number of circuits corresponding to each "synapse" can increase, and the amount of calculations can become enormous. .

[0007] As the number of circuits that make up a chip increases, power consumption also increases, and the amount of electricity generated when the device is running also increases. The amount of heat also increases. In particular, the higher the amount of heat generated, the more the characteristics of the circuit elements included in the chip deteriorate. Therefore, the circuits that make up the chip must have circuit elements that are less susceptible to temperature changes. It is preferable that

[0008] One aspect of the present invention is a semiconductor device in which a hierarchical artificial neural network is constructed. Another object of one embodiment of the present invention is to provide a semiconductor device with low power consumption. Another object of the present invention is to provide a method for manufacturing a semiconductor device that is not affected by the temperature of the environment. Another object of the present invention is to provide a semiconductor device or the like that is less susceptible to cracking. An object of the present invention is to provide a new semiconductor device or the like.

[0009] Note that the problems of one embodiment of the present invention are not limited to the above-listed problems. This does not preclude the existence of other problems. Problems not mentioned in this section are problems that a person skilled in the art would be able to solve by understanding the specification or can be derived from the descriptions in the drawings, etc., and can be extracted appropriately from these descriptions. One aspect of the present invention is to achieve at least one of the above-listed objects and other objects. One aspect of the present invention is to solve the above-listed problems and other problems. You don't need to solve all of them. [Means for solving the problem]

[0010] (1) One aspect of the present invention is a semiconductor device including a first circuit, the first circuit including a first transistor and a second transistor. a first capacitance element, the first transistor having a first gate and a second gate; a first gate of the first transistor electrically connected to a first input wiring; a second gate of the second transistor connected to the first terminal of the second transistor and the first terminal of the first capacitance element; and the first circuit turns the second transistor to an off state, thereby a function of maintaining a first potential between the first terminal of the capacitance element and the second gate of the first transistor; The first transistor is turned on in response to the first potential and the second potential input to the first input wiring. The semiconductor device has a function of being in either an on state or an off state.

[0011] (2) Alternatively, in the configuration (1), the first potential is an analog value. When the first transistor is in an on state, an analog current flows through the first transistor. It is a body device.

[0012] (3) Alternatively, in one aspect of the present invention, in the configuration (1) or (2), a third transistor the third transistor has a first gate and a second gate, The first gate is electrically connected to the second input wiring, and the second gate of the third transistor is a first terminal of the second transistor, a first terminal of the first capacitance element, and a second gate of the first transistor; and a third potential input to the second input wiring. and a semiconductor device having a function of turning the third transistor either on or off. be.

[0013] (4) Alternatively, one embodiment of the present invention is the above-described configuration (3), further including a second circuit, The fourth transistor and the sixth transistor are connected to each other. Each of the fourth transistors has a first gate and a second gate. The gate of the sixth transistor is electrically connected to the first input wiring, and the first gate of the sixth transistor is electrically connected to the second input wiring. the second gate of the fourth transistor is electrically connected to the first gate of the fifth transistor; the terminal, the first terminal of the second capacitance element, and the second gate of the sixth transistor. a first terminal of the first transistor electrically connected to the first wiring; a first terminal of the fourth transistor electrically connected to the second wiring; a first terminal of the sixth transistor electrically connected to the first wiring; The second circuit turns off the fifth transistor, thereby turning off the first terminal of the second capacitance element. The second gate of the fourth transistor and the second gate of the sixth transistor are maintained at a fourth potential. The fourth transistor is connected to the first input wiring in accordance with the function of the fourth potential and the second potential input to the first input wiring. The fourth potential and the second input wiring have a function to turn the transistor on or off. The sixth transistor is turned on or off depending on the third potential applied. The semiconductor device has the function of

[0014] (5) Alternatively, in the configuration (4), the fourth potential is an analog value. When the fourth transistor is in the on state, an analog current flows through the fourth transistor, and the sixth transistor A semiconductor device in which an analog current flows through the sixth transistor when the transistor is in an on state. is.

[0015] (6) Alternatively, one aspect of the present invention is the above (5), further comprising a third circuit and a fourth circuit, The first potential and the fourth potential are potentials according to the first data, and the third circuit The function of inputting the first and third potentials according to the second data to the first and second input wirings, respectively. The fourth circuit compares the currents flowing from the first wiring and the second wiring, and a semiconductor device having a function of outputting a potential corresponding to the product of the first data and the second data from an output terminal of the semiconductor device; It is a body device.

[0016] (7) Another embodiment of the present invention is a semiconductor device including any one of the semiconductor devices (1) to (6). It is an electronic device that performs neural network calculations using a semiconductor device.

[0017] In this specification, a semiconductor device is a device that utilizes semiconductor characteristics. Circuits containing semiconductor elements (transistors, diodes, photodiodes, etc.) It also refers to any device that can function by utilizing the properties of semiconductors. For example, Integrated circuits, chips with integrated circuits, and electronic components that house chips in packages are semiconductors. In addition, a storage device, a display device, a light-emitting device, a lighting device, an electronic device, etc. It may itself be a semiconductor device and may contain a semiconductor device.

[0018] In addition, in this specification, when it is stated that X and Y are connected, it means that X and Y are connected. When X and Y are electrically connected, when X and Y are functionally connected, and when X and The case where Y is directly connected is also considered to be disclosed in this specification. Therefore, the present invention is not limited to predetermined connection relationships, for example, connection relationships shown in drawings or text, but may be applied to connections shown in drawings or text. Connections other than those shown in the figure or text are also considered to be disclosed. The object (e.g., device, element, circuit, wiring, electrode, terminal, conductive film, layer, etc.) .

[0019] An example of the case where X and Y are electrically connected is The elements that function as One or more diodes, display elements, light-emitting elements, loads, etc.) are connected between X and Y. The switch has a function to control on / off. A switch can be in a conducting state (ON state) or a non-conducting state (OFF state), allowing current to flow. It has a function to control whether or not water is flushed.

[0020] An example of a case where X and Y are functionally connected is when the functional connection between X and Y is possible. Circuits that perform functions (e.g., logic circuits (inverters, NAND circuits, NOR circuits, etc.)), signal Conversion circuits (digital-analog conversion circuits, analog-to-digital conversion circuits, gamma correction circuits, etc.) ), potential level conversion circuits (power supply circuits (booster circuits, step-down circuits, etc.), voltage sources, current sources, switching circuits, amplifier circuits (such as level shifter circuits that can Circuits that can increase the amount of current, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc. There are one or more circuits between X and Y (e.g., a power supply circuit, a signal generating circuit, a memory circuit, a control circuit, etc.) It is possible to connect X and Y. For example, if another circuit is inserted between X and Y, However, if the signal output from X is transmitted to Y, then X and Y are functionally connected. It shall be.

[0021] When it is explicitly stated that X and Y are electrically connected, it means that X and Y are electrically connected. When X and Y are electrically connected (i.e., when another element or circuit is inserted between X and Y) X and Y are functionally connected (i.e., there is no connection between X and Y) When X and Y are connected directly (i.e. when they are connected via another circuit) , when X and Y are connected without any other element or circuit between them) In other words, when explicitly stating that something is electrically connected, it simply means that it is connected. The same applies if it is explicitly stated that the

[0022] Also, for example, "X and Y and the source (or first terminal, etc.) and drain ( or the second terminal, etc.) are electrically connected to each other, and X is the source of the transistor (or first terminal, etc.), the drain (or second terminal, etc.) of the transistor, and Y in that order. It can be expressed as "electrically connected to the source ( or the first terminal) is electrically connected to X, and the drain (or second terminal, etc.) is electrically connected to Y, and X, the source (or first terminal, etc.) of the transistor. , the drain (or second terminal, etc.) of the transistor, Y, are electrically connected in this order. Alternatively, "X is the source (or first terminal) of the transistor." The transistor is electrically connected to Y through the drain (or second terminal, etc.) and the transistor is electrically connected to X. The source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor (e.g., Y is provided in this connection order). By using a similar expression method to specify the order of connections in a circuit configuration, The source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor are connected to each other. The technical scope can be determined by distinguishing between the two. Note that these methods of expression are merely examples. , and are not limited to these representation methods. Here, X and Y represent objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0023] Note that the circuit diagram shows independent components as if they are electrically connected to each other. Even if one component has the functions of multiple components, For example, when a part of the wiring also functions as an electrode, one conductive film functions as both the wiring and the electrode. Therefore, the present invention has the functions of both the electrode and the electrode. Electrical connection means that one conductive film has the functions of multiple components. This case will also be included in that category.

[0024] In this specification, a transistor is referred to as a gate, a source, and a drain. The gate is a control terminal that controls the conduction state of the transistor. The two terminals that function as the source and drain are the input and output terminals of the transistor. The two input / output terminals are used to select the transistor conductivity type (n-channel, p-channel) and the Depending on the potential applied to the three terminals of the transistor, one becomes the source and the other becomes the drain. Therefore, in this specification and the like, the terms source and drain can be interchanged. In addition, in this specification and the like, when describing the connection relationship of a transistor, "One of the source and drain" (or first electrode, or first terminal), "the source or drain The term "second electrode" or "second terminal" is used. In some cases, a back gate is provided in addition to the three terminals described above. In this specification, either the gate or the back gate of a transistor is referred to as a first gate. The other of the gate or back gate of the transistor is sometimes called the second gate. Furthermore, the terms "gate" and "backgate" are interchangeable for the same transistor. In addition, if a transistor has three or more gates, In this specification, each gate is referred to as a first gate, a second gate, a third gate, etc. It is sometimes called.

[0025] In this specification, a node may be a terminal, a wiring, or the like depending on the circuit configuration, device structure, etc. It can be called a line, an electrode, a conductive layer, a conductor, an impurity region, etc. Wiring and the like can be called nodes in other words.

[0026] In addition, in this specification, the terms "voltage" and "potential" can be interchanged as appropriate. "Voltage" refers to the potential difference from a reference potential. For example, If we consider the ground potential as the earth potential, we can change the word "voltage" to "potential." The potential does not necessarily mean 0V. Note that the potential is relative and the reference Depending on the potential, the potential applied to the wiring etc. may be changed.

[0027] "Current" refers to the phenomenon of the movement of electric charges (electrical conduction). For example, "the electric current of a positively charged body" The statement "electrical conduction is occurring in the opposite direction" means "electrical conduction is occurring in the negatively charged body." Therefore, in this specification and the like, unless otherwise specified, the term "current" is used. In this case, the term "electrical conduction" refers to the phenomenon of charge transfer accompanying the movement of carriers. Carriers include electrons, holes, anions, cations, complex ions, etc., and are the carriers through which current flows. The carriers differ depending on the system (e.g., semiconductor, metal, electrolyte, vacuum, etc.). The "direction of current" in a wire, etc. is the direction in which positive carriers move, and is expressed as a positive current amount. In other words, the direction in which negative carriers move is opposite to the direction of the current, and the negative Therefore, in this specification, the positive and negative currents (or the direction of the current) Unless otherwise specified, statements such as "current flows from element A to element B" should be interpreted as "current flows from element B to element This can be rephrased as "current flows through element A" or "current flows through element A." A statement such as "current is input" can be rephrased as "current is output from element A" Let's say.

[0028] In addition, in this specification, the ordinal numbers "first," "second," and "third" are used to indicate constituent elements. Therefore, it does not limit the number of components. In addition, the order of the components is not limited. The element referred to as "first" in the above may be used in other embodiments or in the claims. In addition, for example, in the present specification, A component referred to as "first" in one embodiment may be used in other embodiments or in particular It may be omitted within the scope of the claims.

[0029] In addition, in this specification, terms indicating arrangement such as "above" and "below" refer to the relationship between components. The positional relationship may be used for convenience in explaining the configuration with reference to the drawings. The positional relationship between them changes depending on the direction in which each component is depicted. The terms are not limited to those explained in the detailed instructions, but can be rephrased appropriately depending on the situation. For example, the expression "insulator on top of conductor" means that the orientation of the drawing shown is rotated 180 degrees. By turning it around, it can be rephrased as "an insulator located on the underside of a conductor."

[0030] In addition, the terms "above" and "below" refer to the positional relationship of the components directly above or below and directly connected to each other. For example, if the expression is "electrode B on insulating layer A," The electrode B does not need to be formed directly on the insulating layer A, and the insulating layer A and the electrode B This does not exclude the inclusion of other components in between.

[0031] In addition, in this specification and the like, the terms "film" and "layer" may be used interchangeably depending on the situation. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" may be changed to "insulating layer." In some cases, or depending on the circumstances, it may be possible to change the term to " For example, terms such as "film" and "layer" can be omitted and replaced with other terms. For example, the term "conductive layer" or "conductive film" may be changed to the term "conductor." Or, for example, the terms "insulating layer" and "insulating film" may be changed to "insulator." It may be possible to change the term to something like this.

[0032] In addition, the terms "electrode" and "wiring" used in this specification and the like refer to these components functionally. This is not a limitation. For example, an "electrode" may be used as part of a "wiring." , and vice versa. Furthermore, the terms "electrode" and "wiring" may be used interchangeably with "electrodes" and "wiring." This also includes cases where the wiring is formed integrally.

[0033] In addition, in this specification, terms such as "wiring," "signal line," and "power line" may be used interchangeably. Depending on the situation, they can be interchanged. For example, "wiring" It may be possible to change the term to "signal line". In some cases, it may be possible to change the term "wiring" to a term such as "power line." The reverse is also true; terms such as "signal line" and "power line" should be changed to "wiring." It may be possible to change terms such as "power line" to terms such as "signal line." In addition, the reverse is also true, and terms such as "signal line" may be used interchangeably with "power line" In some cases, it may be possible to change the term to something like "potential" applied to the wiring. In some cases or depending on the situation, the term "signal" may be changed to "signal" or similar. And vice versa, terms such as "signal" can be used to refer to "potential." It may be possible to change the term.

[0034] In this specification, impurities in a semiconductor are, for example, substances other than the main components constituting a semiconductor layer. For example, elements with a concentration of less than 0.1 atomic percent are considered impurities. This can result in the formation of DOS (Density of States) in semiconductors. In some cases, the carrier mobility may decrease, or the crystallinity may decrease. When the semiconductor is an oxide semiconductor, impurities that change the properties of the semiconductor include, for example, , Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, other than the main component Transition metals, especially hydrogen (which is also contained in water), lithium, sodium, Silicon, boron, phosphorus, carbon, nitrogen, etc. Specifically, if the semiconductor is a silicon layer, In this case, impurities that change the properties of the semiconductor include, for example, oxygen and group 1 elements excluding hydrogen. These include the elements of Group 2, Group 13, and Group 15.

[0035] In this specification, a switch is a device that can be in a conducting state (ON state) or a non-conducting state (OFF state). It is a device that has the function of controlling whether or not current flows by entering a state where it is in a switched state. A switch is a device that has the function of selecting and switching the path through which current flows. , electrical switches, mechanical switches, etc. can be used. The device is not limited to a specific one as long as it can control the current.

[0036] An example of an electrical switch is a transistor (e.g., a bipolar transistor, MOS transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diode, MIM (Metal Insulator Metal) die MIS (Metal Insulator Semiconductor) die diode-connected transistors, etc.), or logic circuits that combine these When using a transistor as a switch, the "conduction state" of the transistor This means that the source and drain electrodes of the transistor are considered to be electrically short-circuited. The "non-conducting state" of a transistor refers to the state in which the source electrode and drain electrode of the transistor are in a non-conducting state. This refers to a state in which the gate electrodes can be considered to be electrically disconnected. When operating as a switch, the polarity (conductivity type) of the transistor is not particularly limited.

[0037] An example of a mechanical switch is a MEMS (microelectromechanical system). There are switches that use stem technology. These switches are electrically operated switches that can be mechanically operated. It has poles, and the movement of these electrodes controls conduction and non-conduction. [Effects of the Invention]

[0038] According to one aspect of the present invention, a semiconductor device in which a hierarchical artificial neural network is constructed is provided. According to one embodiment of the present invention, a semiconductor device with low power consumption can be provided. Alternatively, according to one aspect of the present invention, it is possible to provide a device or the like that can reduce the influence of the temperature of the environment. According to one embodiment of the present invention, a semiconductor device or the like that is less susceptible to damage can be provided. It is possible to provide a new semiconductor device.

[0039] The effects of one embodiment of the present invention are not limited to the effects listed above. This does not preclude the existence of other effects. Other effects may be affected by this item, as described below. The effects not mentioned in this section are obvious to a person skilled in the art from the description or can be derived from the descriptions in the drawings, etc., and can be extracted appropriately from these descriptions. One aspect of the present invention is to achieve at least one of the effects listed above and other effects. Therefore, one aspect of the present invention may have the above-listed effects. In some cases, the [Brief explanation of the drawings]

[0040] [Figure 1] 1A and 1B are diagrams illustrating a hierarchical neural network. [Figure 2] FIG. 2 is a circuit diagram showing an example of the configuration of a semiconductor device. [Figure 3] 3A, 3B, 3C, 3D, 3E, and 3F are circuit diagrams showing examples of the configuration of circuits included in the semiconductor device. [Figure 4] 4A, 4B, 4C, 4D, 4E, and 4F are circuit diagrams showing examples of the configuration of circuits included in the semiconductor device. [Figure 5] 5A, 5B, 5C, 5D, and 5E are circuit diagrams showing examples of the configuration of circuits included in the semiconductor device. [Figure 6] FIG. 6 is a circuit diagram showing an example of the configuration of a semiconductor device. [Figure 7] FIG. 7 is a circuit diagram showing an example of the configuration of a semiconductor device. [Figure 8] FIG. 8 is a circuit diagram showing an example of the configuration of a semiconductor device. [Figure 9] 9A and 9B are circuit diagrams showing examples of the configuration of circuits included in a semiconductor device. [Figure 10] FIG. 10 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 11] 11A and 11B are circuit diagrams showing examples of the configuration of circuits included in a semiconductor device. [Figure 12] 12A and 12B are diagrams showing voltage-current characteristics of a transistor included in a semiconductor device. [Figure 13] 13A, 13B, and 13C are timing charts showing examples of the operation of the circuits included in the semiconductor device. [Figure 14]14A, 14B, and 14C are timing charts showing examples of the operation of the circuits included in the semiconductor device. [Figure 15] 15A, 15B, and 15C are timing charts showing examples of the operation of the circuits included in the semiconductor device. [Figure 16] 16A and 16B are circuit diagrams showing examples of the configuration of circuits included in a semiconductor device. [Figure 17] FIG. 17 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 18] FIG. 18 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 19] FIG. 19 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 20] 20A and 20B are circuit diagrams showing examples of the configuration of circuits included in a semiconductor device. [Figure 21] 21A and 21B are circuit diagrams showing examples of the configuration of circuits included in a semiconductor device. [Figure 22] 22A and 22B are circuit diagrams showing examples of the configuration of circuits included in a semiconductor device. [Figure 23] FIG. 23 is a cross-sectional view showing an example of the configuration of a semiconductor device. [Figure 24] FIG. 24 is a cross-sectional view showing an example of the configuration of a semiconductor device. [Figure 25] 25A, 25B, and 25C are cross-sectional views showing examples of the structure of a transistor. [Figure 26] 26A, 26B, and 26C are a top view and a cross-sectional view illustrating an example of the structure of a transistor. [Figure 27] 27A, 27B, and 27C are a top view and a cross-sectional view illustrating an example of the structure of a transistor. [Figure 28] 28A, 28B, and 28C are a top view and a cross-sectional view illustrating an example of the structure of a transistor. [Figure 29] 29A, 29B, and 29C are a top view and a cross-sectional view illustrating an example of the structure of a transistor. [Figure 30]30A, 30B, and 30C are a top view and a cross-sectional view illustrating an example of the structure of a transistor. [Figure 31] 31A and 31B are a top view and a perspective view illustrating an example of the structure of a transistor. [Figure 32] 32A and 32B are cross-sectional views showing examples of the structure of a transistor. [Figure 33] 33A, 33B, and 33C are a top view and a perspective view showing an example of the structure of a capacitive element. [Figure 34] 34A, 34B, and 34C are a top view and a perspective view showing an example of the structure of a capacitive element. [Figure 35] 35A, 35B, 35C, and 35D are perspective views showing examples of a semiconductor wafer and an electronic component. [Figure 36] FIG. 36 is a perspective view showing an example of an electronic device. [Figure 37] FIG. 37A is a front view showing an example of an electronic device, and FIGS. 37B and 37C are perspective views showing examples of the electronic device. DETAILED DESCRIPTION OF THE INVENTION

[0041] In artificial neural networks (hereafter referred to as neural networks), ,The connection strength of the synapses is determined by providing existing information to the neural ,network. In this way, we can give the neural network existing information and The process of determining connection strength is sometimes called "learning."

[0042] In addition, no action is taken against the neural network that has undergone "learning" (the connection weights have been determined). By providing some information, new information can be output based on the connection strength. In this way, in a neural network, the The process of generating new information is sometimes called "inference" or "cognition."

[0043] Neural network models include, for example, Hopfield and hierarchical types. In particular, neural networks with multi-layer structures are called "deep neural networks." They call machine learning using deep neural networks "DNNs" and call machine learning using deep neural networks " It is sometimes called "deep learning."

[0044] In this specification, the term "metal oxide" refers to a metal in a broad sense. Metal oxides are oxides of the following: oxide insulators, oxide conductors (including transparent oxide conductors), ), oxide semiconductors (also called oxide semiconductors or simply OS), For example, when a metal oxide is used in the active layer of a transistor, the metal oxide In other words, metal oxides have amplifying, rectifying, and and forming a channel forming region of a transistor having at least one of a switching function and a If possible, the metal oxide is referred to as a metal oxide semiconductor. It can also be called an OS FET or OS transistor. In the above description, the transistor is referred to as a transistor including a metal oxide or an oxide semiconductor. It is possible.

[0045] In this specification and the like, metal oxides containing nitrogen are also referred to as metal oxides (metal ox). Metal oxides containing nitrogen are sometimes collectively called metal oxynitrides (metal oxynitrides). It may also be called tal oxynitride.

[0046] In addition, in this specification and the like, the configurations shown in each embodiment may be interchangeable with the configurations shown in other embodiments. The above-described embodiments can be combined appropriately to form one aspect of the present invention. When multiple configuration examples are shown, the configuration examples can be combined with each other as appropriate.

[0047] It should be noted that the contents (or even a part of the contents) described in one embodiment may be used in the implementation of the embodiment. Another content (or part of the content) described in the embodiment and one or more other embodiments The content described (or a part of the content) is applied to, combined with, or at least one of the contents. or replacement, etc.

[0048] The contents described in the embodiments are explained using various drawings in each embodiment. This refers to the content stated in the specification or the content stated using the text in the specification.

[0049] In addition, a drawing (or a part thereof) described in one embodiment may be replaced with another part of the drawing. In the embodiment, another figure (or a part thereof) and one or more other embodiments may be used. At least one of the drawings (or a part thereof) described in the embodiment is combined with By adding more, more figures can be constructed.

[0050] The embodiments described in this specification are explained with reference to the drawings. The present invention may be embodied in many different forms without departing from the spirit and scope thereof. It will be readily understood by those skilled in the art that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiment. In the configuration of the invention of the embodiment, the same parts or parts having similar functions are designated by the same reference numerals. The same elements are used in different drawings, and repeated explanations may be omitted. In some cases, in order to ensure clarity of the drawings, some components may be omitted. be.

[0051] In this specification and the like, when the same reference numeral is used for a plurality of elements, it is not necessary to distinguish them. When necessary, a distinguishing code such as "_1", "[n]", or "[m,n]" is added to the code. It may be stated in writing.

[0052] Also, in the drawings of this specification, the size, layer thickness, or area may be exaggerated for clarity. Therefore, the drawings are not necessarily limited to the scale. The drawings are merely conceptual examples, and are not limited to the shapes or values ​​shown in the drawings. For example, variations in signal, voltage, or current due to noise, or timing errors This can include variations in signal, voltage, or current.

[0053] (Embodiment 1) In this embodiment, a semiconductor device according to one embodiment of the present invention is a neural network processor. The arithmetic circuit that performs the calculation will be described.

[0054] <Hierarchical neural network> First, we will explain about hierarchical neural networks. For example, the network has one input layer, one or more intermediate layers (hidden layers), and one output layer. The hierarchical neural network shown in Figure 1A has three or more layers. Neural network 100 is an example of such a network. The layer has R layers (where R can be an integer of 4 or greater). The first layer corresponds to the input layer, the Rth layer corresponds to the output layer, and the other layers correspond to the intermediate layers. In addition, in FIG. 1A, the (k-1)th layer and the kth layer (where k is 3 or more and R-1) are shown as intermediate layers. The following integers are used.) are shown in the figure, and other intermediate layers are omitted from the illustration. .

[0055] Each layer of the neural network 100 has one or more neurons. In this case, the first layer is made up of neurons N1 (1) Neuron N p (1) (where p is 1 or more ) and the (k-1)th layer has neurons N1 (k-1) Neuron N m (k-1) (where m is an integer greater than or equal to 1), and the kth layer has neurons N1 ( k) Neuron N n (k) (where n is an integer equal to or greater than 1), and the Rth layer is Neuron N1 (R) Neuron N q (R) (where q is an integer greater than or equal to 1.) It has.

[0056] In addition, in Figure 1A, neuron N1 (1) , neuron N p (1) , neuron N1 ( k-1) , neuron N m (k-1) , neuron N1 (k) , neuron N n (k) , Neuron N1 (R) , neuron N q (R) In addition, the (k-1)th layer neuron N i (k-1) (where i is an integer between 1 and m), and the kth layer neuron N j ( k) (where j is an integer between 1 and n) are also shown. The illustration of the .

[0057] Next, the transmission of signals from the neurons in the previous layer to the neurons in the next layer, and the In this explanation, we will explain the signals input and output in the k-th layer of the neural network. N j (k) We are focusing on the following.

[0058] Figure 1B shows the kth layer neuron N j (k) and neuron N j (k) The signal input to and neuron N j (k) 10 shows the signal output from the

[0059] Specifically, the (k-1)th layer neuron N1 (k-1) Neuron N m (k-1 ) The output signal z1 (k-1) ~z m (k-1) But neuron N j ( k) The output is directed to neuron N j (k) is z1 (k-1) ~z m (k-1) Depending on z j (k) Generate z j (k) is used as the output signal The output is directed to each neuron in the layer (not shown).

[0060] The signals input from the neurons in the previous layer to the neurons in the next layer are transmitted between those neurons. The strength of the synapse (hereafter referred to as the weighting coefficient) that connects the In the neural network 100, the output from the previous layer neuron is The signal is multiplied by the corresponding weighting coefficient and input to the neuron in the next layer. The (k-1)th layer neuron N i (k-1) and the k-th layer neuron N j (k) The weight coefficient of the synapse between i (k-1) j (k) Then, the k-th layer Newron N j (k) The signal input to can be expressed by equation (1.1).

[0061]

number

[0062] That is, the neuron N1 in the (k-1)th layer (k-1) Neuron N m (k-1) of From each, the k-th layer neuron N j (k) When a signal is transmitted to the (k-1) ~z m (k-1) The weighting coefficients w1 corresponding to each signal are (k-1) j (k) Or even w m (k-1) j (k) Then, the k-th layer neuron Nj ( k) has w1 (k-1) j (k) z1 (k-1) Or even w m (k-1) j (k) z m (k-1) is input. At this time, the k-th layer neuron N j (k) of the signal input to Sumwau j (k) is expressed as equation (1.2).

[0063]

number

[0064] Neuron N j (k) u j (k) Depending on j (k) Generate In. Neuron N j (k) Output signal z from j (k) is defined as follows:

[0065]

number

[0066] The function f(u j (k) ) is the activation function in a hierarchical neural network , step function, linear ramp function, sigmoid function, etc. The activation function may be the same for all neurons or may be different. Therefore, the activation functions of neurons in each layer may be the same or different.

[0067] Incidentally, the signals output by the neurons in each layer may be analog values ​​or digital values. The digital value may be, for example, a binary value or a ternary value. For analog values, activation functions such as linear ramp functions, sigmoid functions, etc. In the case of binary digital values, for example, the output can be set to -1 or 1, or 0 or A step function with a value of 1 or 2 can be used. can be three or more values, in which case the activation function has three values, e.g., the output is -1, 0, or If we use a step function with 1, or a step function with 0, 1, or 2, good.

[0068] The neural network 100 receives an input signal at the first layer (input layer). Therefore, in each layer from the first layer (input layer) to the last layer (output layer), the input from the previous layer is sequentially Based on the input signal, an output signal is generated using equations (1.1) to (1.3), and the output signal is The signal output from the last layer (output layer) is sent to the next layer. This corresponds to the result calculated by the neural network 100.

[0069] <Configuration example of an arithmetic circuit> Here, in the above-mentioned neural network 100, the equations (1.2) and (1 An example of an arithmetic circuit that can perform the operation of .3) will be explained. In this case, as an example, the weight coefficients of the synapse circuits of the neural network 100 are expressed as binary (e.g., a combination of "-1" and "+1" or a combination of "0" and "+1"), or 3 The activation function of a neuron is a binary function (e.g., a combination of "-1", "0", and "1"). (e.g., a combination of "-1" and "+1" or a combination of "0" and "+1"), or 3 It is a function that outputs a value (such as a combination of "-1", "0", and "1"). In the literature, the weight coefficients and the signals input from the previous layer neurons to the next layer neurons are One of the two values ​​(sometimes called the calculated value) is called the first data. The other data may be referred to as second data.

[0070] The arithmetic circuit 110 shown in FIG. 2 includes, for example, an array section ALP, a circuit ILD, and a circuit W The semiconductor device includes an LD, a circuit XLD, and a circuit AFP. Neuron N1 in the kth layer in Figure 1A and Figure 1B (k) Neuron N n (k) to Input signal z1 (k-1) ~z m (k-1) and neuron N1 (k) No To Neuron N n (k) The signal z1 output from each (k) ~z n (k) Generate This is a circuit that:

[0071] The entire arithmetic circuit 110 or a part of it may be implemented as a neural network or It may be used for purposes other than AI. For example, it may be used for graphics calculations or scientific calculations. In the case of performing a sum-of-products operation or a matrix operation, the entire operation circuit 110 or a part thereof You can use a part of it to perform processing. In other words, it can be used not only for AI calculations but also for general calculations. For this purpose, the entire arithmetic circuit 110 or a part thereof may be used.

[0072] The circuit ILD includes, for example, wirings IL[1] to IL[n] and wirings ILB[1]. The circuit WLD is electrically connected to the wirings WL[n] to ILB[n]. The circuit XLD is electrically connected to wirings S[1] to WLS[m]. The circuit AFP is electrically connected to the wiring XLS[1] to the wiring XLS[m]. The wiring OL[1] to wiring OL[n], the wiring OLB[1] to wiring OLB[n], is electrically connected to

[0073] <<Array section ALP>> The array unit ALP has, for example, m×n circuits MP. are arranged in a matrix of m rows and n columns in the array section ALP. In Figure 2, the i-th row and j-th column (where i is an integer between 1 and m, and j is an integer between 1 and n) The circuit MP located at i,j is expressed as circuit MP[i,j]. is the circuit MP[1,1], the circuit MP[m,1], the circuit MP[i,j], the circuit MP[1,n ], and only the circuit MP[m,n] is shown, and the illustration of other circuits MP is omitted. are.

[0074] For example, the circuit MP[i,j] includes a wiring IL[j], a wiring ILB[j], and a wiring W LS[i], wiring XLS[i], wiring OL[j], and wiring OLB[j] are electrically is connected to.

[0075] The circuit MP[i,j] is, for example, a neuron N i (k-1) and neuron N j (k ) The weighting coefficient between the first data and the second data (sometimes referred to as either the first data or the second data) Specifically, the circuit MP[i,j] has the function of storing the first data. The first data (weighting coefficient) input from the wiring IL[j] and the wiring ILB[j] is It stores information (such as potential, resistance, and current). Also, the circuit MP[i,j] is , neuron N i (k-1) The signal z output from i (k-1) (First data or second data The product of the first data and the second data (sometimes referred to as the other data). As a specific example, the circuit MP[i,j] has a function of outputting the wiring XLS[i ] to the second data z i (k-1) By inputting, the product of the first data and the second data is The current (for example, current, voltage, etc.) according to the Information (e.g., current, voltage, etc.) or related to the product of the first data and the second data Information (e.g., current, voltage, etc.) is output to the wiring OL[j] and wiring OLB[j]. Although an example in which the wiring IL[j] and the wiring ILB[j] are arranged has been shown, One aspect of the present invention is not limited to this. In addition, when the wiring OL[j] and the wiring OLB[j] are arranged, only the wiring OL[j] and the wiring OLB[j] may be arranged. However, one embodiment of the present invention is not limited to this. Only one of the wirings OLB[j] may be arranged.

[0076] <<Circuit ILD>> The circuit ILD includes, for example, wirings IL[1] to IL[n] and wirings ILB[1]. through wiring ILB[n] and the circuits MP[1,1] to MP[m,n]. For each of these, the first data w1 (k-1) 1 (k) Or even w m (k-1) n (k) The device has a function of inputting information (for example, potential, resistance value, current value, etc.) corresponding to the above. As a specific example, the circuit ILD is a first weighting coefficient for the circuit MP[i,j]. Data W i (k-1) j (k) Information corresponding to the potential, resistance, or current ) are supplied by wiring IL[j] and wiring ILB[j].

[0077] <<Circuit WLD>> For example, the circuit WLD receives information (for example, It has the function of selecting the circuit MP to which data (for example, potential, resistance value, current value, etc.) is written. For example, the circuits MP[i,1] to MP[i,n] located in the i-th row of the array unit ALP When writing information (for example, potential, resistance value, current value, etc.) to the circuit WLD, For example, the write switching elements included in the circuits MP[i,1] to MP[i,n] A signal to turn on or off the child is supplied to the wiring WLS[i], and the child is turned on or off in the other rows. A potential that turns off the write switching element included in the circuit MP is supplied to the wiring WLS. Although an example in which the wiring WLS[i] is arranged has been shown, One embodiment is not limited to this. For example, the wiring WLS[i] is arranged as a plurality of wirings. That's fine.

[0078] <<Circuit XLD>> For example, the circuit XLD is connected to the circuit M via wirings XLS[1] to XLS[n]. For each of P[1,1] to MP[m,n], neuron N1 (k-1) No To Neuron N m (k-1) The second data z1 corresponds to the calculated value output from (k-1) ~z m (k-1) Specifically, the circuit XLD has a function of supplying the circuit MP[i , 1] to circuit MP[i, n], neuron N i (k-1) The second output from Data z i (k-1) The information corresponding to the wiring XLS[i ]. Note that an example where wiring XLS[i] is placed is shown, but in this One aspect of the invention is not limited to this. For example, the wiring XLS[i] may be a plurality of wirings, such as It may be placed.

[0079] <<Circuit AFP>> The circuit AFP includes, for example, circuits ACTF[1] to ACTF[n]. The circuit ACTF[j] is, for example, a combination of wiring OL[j] and wiring OLB[j]. The circuit ACTF[j] is electrically connected to the wiring OL[j], for example. and the wiring OLB[j] according to the information (e.g., potential, current value, etc.) input. For example, the signal input from the wiring OL[j] and wiring OLB[j] is generated. The respective pieces of information (for example, potential or current value) are compared, and a signal is generated according to the comparison result. This signal is sent to neuron N j (k) The signal z output from j (k) Equivalent to That is, the circuits ACTF[1] to ACTF[n] are, for example, It functions as a circuit that calculates the activation function of the neural network. For example, the circuits ACTF[1] to ACTF[n] are not limited to this example. may have a function of converting an analog signal into a digital signal. The circuits ACTF[1] to ACTF[n] have the function of amplifying and outputting analog signals. It may have a function of converting the output impedance. However, one embodiment of the present invention is not limited to this. F does not have to be placed.

[0080] The circuits ACTF[1] to ACTF[n] have the circuit configuration shown in FIG. 3A, for example. FIG. 3A shows an example of input from wiring OL[j] and wiring OLB[j]. Depending on the applied current, the signal z j (k) Specifically, FIG. 3A shows a circuit that generates Output signal z represented by a binary value j (k) An example of an activation function calculation circuit that outputs are.

[0081] In FIG. 3A, the circuit ACTF[j] includes a resistor RE, a resistor REB, a comparator CM P. Resistance elements RE and REB have the function of converting current into voltage. Therefore, any element or circuit that has the function of converting current into voltage is not limited to a resistive element. The wiring OL[j] is connected to the first terminal of the resistor RE and the first input terminal of the comparator CMP. and the wiring OLB[j] is electrically connected to the first terminal of the resistor REB and the comparator CM The second terminal of the resistor element RE is electrically connected to the second input terminal of the resistor element P. The second terminal of the resistor REB is electrically connected to the wiring VAL. The second terminal of the resistor element RE and the second terminal of the resistor element REB are connected to the same wiring. Alternatively, it may be connected to another wiring having the same potential.

[0082] It is preferable that the resistance values ​​of the resistor elements RE and REB are equal to each other. For example, the difference in resistance value between the resistor element RE and the resistor element REB is preferably within 10%. Preferably, it is within 5%. However, one aspect of the present invention is to In some cases or depending on the situation, the resistance elements RE and REB The resistance values ​​may be different from each other.

[0083] The wiring VAL functions as a wiring that applies a constant voltage, for example. For example, VDD is a high-level potential, VSS is a low-level potential, and GND is a ground potential. ) etc. The constant voltage can be set appropriately depending on the configuration of the circuit MP. It is preferable that a pulse signal, not a constant voltage, is supplied to the wiring VAL. It may also be used.

[0084] The voltage between the first and second terminals of the resistor element RE is the voltage flowing from the wiring OL[j]. Therefore, the resistance value of the resistor RE is input to the first input terminal of the comparator CMP. Similarly, the first and second terminals of the resistor element REB are connected to each other. The voltage between the comparator CM is determined by the current flowing from the wiring OLB[j]. A voltage according to the resistance value of the resistor REB and the current is input to the second input terminal of P.

[0085] As an example, the comparator CMP receives the signals input to the first input terminal and the second input terminal. A function that compares voltages and outputs a signal from the output terminal of the comparator CMP according to the comparison result. For example, the comparator CMP has a function of detecting a voltage at the second input terminal that is higher than the voltage input at the first input terminal. When the voltage input to the terminal is high, a high level potential is output from the output terminal of the comparator CMP. When the voltage input to the first input terminal is higher than the voltage input to the second input terminal, the low level The bell potential can be output from the output terminal of the comparator CMP. The potential output from the output terminal can be either high level or low level. Output signal z output by ACTF[j] j (k) can be binary. For example, the comparison The high-level potential and low-level potential output from the output terminal of the CMP are output signals z j (k) It can correspond to "+1" and "-1". The high-level potential and the low-level potential output from the output terminal of the comparator CMP are signal z j (k) may correspond to "+1" and "0".

[0086] In addition, in the circuit ACTF[j] of FIG. 3A, the resistor element RE and the resistor element REB are used. The element or circuit is not limited to a resistive element, as long as it has the function of converting current into voltage. Therefore, the resistors RE and REB of the circuit ACTF[j] in FIG. 3A are different circuit elements. For example, the circuit ACTF[j] shown in Figure 3B can be replaced by the circuit in Figure 3A. The resistors RE and REB included in the circuit ACTF[j] are replaced with the capacitors CE and This is a circuit in which CEB is replaced by ACTF[j], and it operates in a manner similar to that of the ACTF[j] circuit in Figure 3A. The capacitance values ​​of the capacitance elements CE and CEB are For example, the capacitance values ​​of the capacitance elements CE and CEB are preferably equal to each other. The difference should be within 10%, and more preferably within 5%. However, one embodiment of the present invention is not limited to this. For example, a circuit for initializing the accumulated charge may be provided in parallel with the capacitance element CE. A switch may be provided. That is, a second terminal of the switch is connected to the wiring VAL. The first terminal of the switch is connected to the first terminal of the capacitance element CE, the wiring OL[j], and the comparator Alternatively, the second terminal of the switch may be connected to the first input terminal of the CMP. AL is connected to a wiring different from the first terminal of the switch, and the first terminal of the capacitance element CE is connected to the wiring OL[j] and the first input terminal of the comparator CMP. The circuit ACTF[j] shown in C is a resistor element RE included in the circuit ACTF[j] of FIG. This is a circuit in which the resistor element REB is replaced with the diode element DE and the diode element DEB. , it can perform almost the same operation as the circuit ACTF[j] in FIG. 3A. E, the direction of the diode element DEB (the connection point between the anode and cathode) is It is desirable to change it appropriately depending on the magnitude of the order.

[0087] In addition, the comparator CMP included in the circuit ACTF[j] of FIGS. 3A to 3C is, for example, , can be replaced by an operational amplifier OP. The circuit ACTF[j] shown in Figure 3D can be The circuit diagram shows the circuit ACTF[j] in A, where the comparator CMP is replaced with an operational amplifier OP. do.

[0088] In addition, even if the switch S01a and the switch S01b are provided in the circuit ACTF[j] of FIG. 3B, As a result, the circuit ACTF[j] has the following capacitances for the capacitance elements CE and CEB: It is possible to maintain the potential according to the current input from wiring OL[j] and wiring OLB[j]. As a specific example of the circuit, as shown in FIG. 3E, The wiring OL[j] is electrically connected to the terminal of the switch S01a, and the capacitance element CE The first terminal of the switch S01b is electrically connected to the first input terminal of the comparator CMP, and the The wiring OLB[j] is electrically connected to the first terminal of the switch S01b, and the capacitance element The first terminal of CEB may be electrically connected to the second input terminal of the comparator CMP. In the circuit ACTF[j] of FIG. 3E, the first and second input terminals of the comparator CMP are When the potential of the wiring OL[j] and wiring OLB[j] is input to the switch S01a, This can be done by turning on each of the switches S01b and S01b. , the switch S01a and the switch S01b are turned off, The potentials input to the first and second input terminals of the capacitor CMP are applied to the capacitance elements CE and The switch S01a and the switch S01b are used as switches S01a and S01b. For example, an electrical switch such as an analog switch or a transistor may be used. In addition, the switches S01a and S01b may be, for example, mechanical switches. It is also possible to apply a transistor to the switches S01a and S01b. When using a silicon-doped silicon nitride semiconductor (SiN) transistor, the transistor is an OS transistor or a silicon-doped silicon nitride semiconductor (SiN) transistor. The transistor may be a transistor having a silicon nitride film (hereinafter referred to as a silicon transistor). Alternatively, the period during which each of the switches S01a and S01b is kept in the ON state may be limited. By controlling the capacitance of the capacitor CE, the voltage values ​​of the capacitor CEB can be controlled. For example, when the current flowing through the capacitance elements CE and CEB is large, the switch S01 a) and by shortening the period during which the switch S01b is kept in the on state, This can prevent the voltage values ​​of the capacitance elements CE and CEB from becoming too large.

[0089] The comparator CMP included in the circuit ACTF[j] of FIGS. 3A to 3C and 3E is, for example, For example, a chopper type comparator can be used. The comparator CMP shown in FIG. 3F is a chopper type comparator. The comparator CMP is a comparator of the type shown in FIG. The inverter circuit INV3 includes a switch S03, a capacitance element CC, and an inverter circuit INV3. Switch S02a, switch S02b, and switch S03 are the same as the switches S01a and S02b. As with 01b, mechanical switches, OS transistors, Si transistors, and other transistors are used. It can be a digital signal.

[0090] The first terminal of the switch S02a is electrically connected to the terminal VinT, and the second terminal of the switch S02b is electrically connected to the terminal VinT. A first terminal of the switch S02a is electrically connected to the terminal VrefT, and a second terminal of the switch S02b is electrically connected to the terminal VrefT. The second terminal of the switch S02b is electrically connected to the first terminal of the capacitance element CC. The second terminal of the capacitor CC is connected to the input terminal of the inverter circuit INV3 and the first terminal of the switch S03. The terminal VoutT is electrically connected to the output terminal of the inverter circuit INV3. The output terminal of the switch S01 is electrically connected to the output terminal of the switch S02 and the second terminal of the switch S03.

[0091] The terminal VinT functions as a terminal for inputting the input potential to the comparator CMP, and the terminal V refT functions as a terminal for inputting a reference potential to the comparator CMP, and the terminal Vout T functions as a terminal for outputting the output potential from the comparator CMP. nT corresponds to either the first terminal or the second terminal of the comparator CMP in FIGS. 3A to 3C and 3E. The terminal VrefT corresponds to the first or second terminal of the comparator CMP shown in FIGS. 3A to 3C and 3E. It can correspond to the other child.

[0092] The circuit ACTF[j] of FIGS. 3A to 3E outputs an output signal z j (k) The activation function circuit ACTF[j] outputs the output signal z j (k) of The output may be three or more values ​​or an analog value.

[0093] 4A to 4F show the currents input from the wiring OL[j] and wiring OLB[j]. , signal z j (k) is a circuit that generates an output signal z represented by a ternary value. j (k) Exit 1 shows an example of a calculation circuit for the activation function to be input.

[0094] The circuit ACTF[j] shown in FIG. 4A includes a resistor RE, a resistor REB, a comparator CMPa , and comparator CMPb. The wiring OL[j] connects the first terminal of the resistor element RE and the comparator CM The wiring OLB[j] is electrically connected to the first input terminal of the resistor REB. The terminal is electrically connected to the first input terminal of the comparator CMPb. The second input terminal of the comparator Pa and the second input terminal of the comparator CMPb are electrically connected to the wiring VrefL. Furthermore, the second terminal of the resistor element RE is electrically connected to the wiring VAL, A second terminal of the resistor REB is electrically connected to the wiring VAL.

[0095] The wiring VrefL is a constant voltage V ref acts as a voltage line that gives V ref For example, , it is preferable that it is above GND and below VDD. ref is G It may be a potential lower than ND or higher than VDD. ref is the comparator CMPa, It is used as a reference potential (potential for comparison) in the comparator CMPb.

[0096] The voltage between the first and second terminals of the resistor element RE is the voltage flowing from the wiring OL[j]. Therefore, the first input terminal of the comparator CMPa is connected to the resistor element RE. Similarly, the first and second terminals of the resistor element REB are connected to the resistor R1 and R2. The voltage between is determined by the current flowing from the wiring OLB[j]. The first input terminal of the resistor CMPb receives a voltage according to the resistance value of the resistor REB and the current. will be done.

[0097] The comparator CMPa compares the voltages input to the first input terminal and the second input terminal. Then, a signal is output from the output terminal of the comparator CMPa according to the comparison result. The comparator CMPa detects that the voltage input to the second input terminal ( V ref ) is high, a high-level potential is output from the output terminal of the comparator CMPa, and a high-level potential is output from the second input terminal The voltage (V ref ) when the voltage input to the first input terminal is higher than , a low level potential can be output from the output terminal of the comparator CMPa.

[0098] Similar to the comparator CMPa, the comparator CMPb has a first input terminal and a second input terminal. The voltage input to the comparator CMPb is compared with the voltage input to the comparator CMPb, and a signal is output from the output terminal of the comparator CMPb according to the comparison result. For example, the comparator CMPb outputs a signal when the voltage input to the second input terminal is lower than the voltage input to the first input terminal. The voltage (V ref ) is high, the high level potential is output from the comparator CMPb. The voltage input to the second input terminal (V ref ) to the first input terminal. When the input voltage is high, a low level potential is output from the output terminal of the comparator CMPb. can be done.

[0099] At this time, the potentials output from the output terminals of the comparators CMPa and CMPb are Depending on j (k) For example, the output of the comparator CMPa can be expressed as A high-level potential is output from the output terminal of the comparator CMPb, and a low-level potential is output from the output terminal of the comparator CMPb. If the output signal z j (k) is set to "+1", and a low level is output from the output terminal of the comparator CMPa. When a high-level potential is output from the output terminal of comparator CMPb, signal z j (k)is set to "-1", and a low level potential is output from the output terminal of the comparator CMPa. When a low-level potential is output from the output terminal of the comparator CMPb, the output signal z j (k) teeth It can be set to "+0".

[0100] The circuit ACTF[j] is not limited to the circuit configuration shown in FIG. 4A. Depending on the situation, For example, in the circuit ACTF[j] of FIG. 4A, the comparator CMPa If you want to combine the two output results of the comparator CMPb into one signal, use the circuit ACTF The circuit ACTF[j] in FIG. 4B is the same as the circuit ACTF[j] in FIG. 4A. This is a configuration example in which a conversion circuit TRF is provided in ACTF[j], and the comparators CMPa and CMPb The output terminals of the converters T and T are electrically connected to the input terminals of the converter circuit T. A specific example of RF is a digital-to-analog converter (in this case, a signal z j (k) Haa (The value is analog.)

[0101] Also, for example, in FIG. 4A, the second inputs of the comparators CMPa and CMPb are The wire VrefL electrically connected to the output terminal is connected to the wires Vref1L and Vref2L. The ACTF[j] circuit in FIG. 4C is the ACTF[j] circuit in FIG. 4A. The second terminal of the comparator CMPa included in [j] is connected to the wiring Vref1 instead of the wiring VrefL. L, and the second terminal of the comparator CMPb is connected to the line Vref instead of the line VrefL. 2L. The input to the wiring Vref1L and Vref2L By setting the potentials output from the comparators CMPa and CMPb to different values, The reference potentials can be set separately.

[0102] Also, for example, as a configuration different from the circuit ACTF[j] of FIGS. 4A to 4C, an amplifier circuit Alternatively, an impedance conversion circuit or the like may be used. For example, the circuit AC TF[j] can be applied to the circuit AFP of the arithmetic circuit 110 in Figure 2. ACTF[j] is the resistor RE, resistor REB, operational amplifier OPa, and operational amplifier OP b, which functions as an amplifier circuit.

[0103] The wiring OL[j] is connected to the first terminal of the resistor RE and the non-inverting input terminal of the operational amplifier OPa. , and the wiring OLB[j] is electrically connected to the first terminal of the resistor REB and the operational amplifier O It is electrically connected to the non-inverting input terminal of Pb. It is also electrically connected to the inverting input terminal of the operational amplifier OPa. The terminal is electrically connected to the output terminal of the operational amplifier OPa and the inverting input terminal of the operational amplifier OPb. The terminal is electrically connected to the output terminal of the operational amplifier OPb. The second terminal of the resistor REB is electrically connected to the wiring VAL. is electrically connected to

[0104] That is, the operational amplifiers OPa and O Pb is configured as a voltage follower. This allows the operational amplifier OPa to The potential output from the output terminal is the same as the potential input to the non-inverting input terminal of the operational amplifier OPa. The voltage output from the output terminal of the operational amplifier OPb is approximately equal to the voltage In this case, the output signal z j (k) teeth , are output from the circuit ACTF[j] as two analog values. The output terminal of the operational amplifier OPb is connected to the input terminal of the comparator CMP. The output from the comparator CMP may be connected to the output signal z j (k) It may also be possible to use the following.

[0105] Also, for example, as a configuration different from the circuit ACTF[j] of FIGS. 4A to 4D, an integrating circuit Alternatively, a current-voltage conversion circuit or the like may be used. As an example, a circuit ACT shown in FIG. F[j] can be applied to the circuit AFP of the arithmetic circuit 110 in FIG. CTF[j] is the operational amplifier OPa, the operational amplifier OPb, the load element LEa, and the load element LE It has b.

[0106] The wiring OL[j] is connected to the first input terminal (for example, the inverting input terminal) of the operational amplifier OPa and the negative The first terminal of the load element LEa is electrically connected to the line OLB[j]. b and the first terminal of the load element LEb. Also, the second input terminal (for example, the non-inverting input terminal) of the operational amplifier OPa is connected to , electrically connected to the wiring Vref1L, and the second input terminal (for example, non The inverting input terminal of the load element LEa is electrically connected to the wiring Vref2L. The terminal is electrically connected to the output terminal of the operational amplifier OPa, and the second terminal of the load element LEa is , and is electrically connected to the output terminal of the operational amplifier OPb.

[0107] The wiring Vref1L and the wiring Vref2L may have the same voltage or different voltages. Therefore, the wiring Vref1L and wiring Vref2 L can sometimes be combined into a single wire.

[0108] In the circuit ACTF[j] of FIG. 4E, the load elements LEa and LEb are, for example, For example, it can be a resistance element or a capacitance element. By using a capacitance element as the operational amplifier OPa, the load element LEa, and the operational amplifier OPb and the load element LEb each function as an integrator. Or, depending on the amount of current flowing through the wiring OLB[j], each capacitance element (load element LEa , LEb) charges are stored. That is, charges flow from wiring OL[j] and wiring OLB[j]. The current is integrated by an integrator circuit and converted into a voltage, which is then output as a signal z j (k) year The output terminal of the operational amplifier OPa and the output terminal of the operational amplifier OPb are connected to each other. , may be connected to the input terminals of the comparator CMP. The output signal z j (k) The capacitive elements of the load elements LEa and LEb may be For example, a circuit for initializing the charge stored in the load element LEa( A switch may be provided in parallel with the capacitor element. That is, the second terminal of the switch , the output terminal of the operational amplifier OPa is connected, and the first terminal of the switch is connected to the wiring OL[j], It may also be connected to the first input terminal (for example, the inverting input terminal) of the operational amplifier OPa. stomach.

[0109] In addition, in the circuit ACTF[j] of FIG. 4E, from the wiring OL[j] and wiring OLB[j] When converting the flowing current into a voltage and outputting it, the load elements LEa and LEb are as follows: A resistive element can be used instead of the capacitive element.

[0110] 4F as a configuration different from the circuit ACTF[j] of FIG. 4A to FIG. 4E. The circuit ACTF[j] shown can be applied to the circuit AFP of the arithmetic circuit 110 in FIG. The circuit ACTF[j] in FIG. 4F includes a resistor RE, a resistor REB, and an analog-to-digital converter. It has a circuit ADCa and an analog-to-digital conversion circuit ADCb.

[0111] The wiring OL[j] is connected to the input terminal of the analog-to-digital conversion circuit ADCa and the resistor element RE. The first terminal is electrically connected to the wiring OLB[j], and the wiring OLB[j] is electrically connected to the analog-to-digital conversion circuit AD The resistor element REB is electrically connected to the input terminal of the resistor element Cb and the first terminal of the resistor element REB. The second terminal of the resistor RE is electrically connected to the wiring VAL, and the second terminal of the resistor REB is electrically connected to the wiring VAL. It is electrically connected to VAL.

[0112] In the circuit ACTF[j] of FIG. 4F, the current flows from the wiring OL[j] and wiring OLB[j]. The potentials of the first terminals of the resistors RE and REB are determined according to the current. Then, the circuit ACTF[j] converts the analog value of the potential into an analog-to-digital conversion circuit. By ADCa and ADCb, two-value or three-value or more (for example, 256-value) digital Convert the signal z j (k) It has the function to output as

[0113] The resistor elements RE and REB shown in FIGS. 4A to 4F are the same as those shown in FIGS. 3B and 3C. Similarly, the capacitance element CE, the capacitance element CEB, or the diode element DE, the diode element DE In particular, the resistor element RE and the resistor element B shown in FIGS. When REB is replaced with the capacitance element CE and the capacitance element CEB, the switching By providing switches S01a and S01b, the wiring OL[j] and wiring OLB[j] can be The input potential can be maintained.

[0114] The arithmetic circuit 110 in FIG. 2 performs the following operations depending on the circuit configuration of the circuit MP[i,j]. i,j] can be changed. For example, in Figure 2, In the arithmetic circuit 110, the wiring WLS[i ] can be one or more wires. For example, in the circuit MP[i,j], The electrically connected wire XLS[i] can be one or more wires. .

[0115] <<Circuit MP>> Next, a configuration example of the circuit MP[i,j] included in the arithmetic circuit 110 will be described.

[0116] FIG. 5A shows an example of the configuration of a circuit MP[i,j] that can be applied to the arithmetic circuit 110. The path MP[i,j] includes, for example, a circuit MC and a circuit MCr. The circuit MCr is a circuit MP that stores weight coefficients, input signals (calculated values) of neurons, and The circuit MC is a circuit that calculates the product of the two. The circuit MC may have the same configuration as the circuit MCr or a different configuration from the circuit MCr. Therefore, the circuit MCr is designated by the symbol MC in order to distinguish it from the circuit MC. The symbols of the circuit elements included in the circuit MCr, which will be described later, are marked with "r". It also has an "r" attached to it.

[0117] For example, the circuit MC has a holding unit HC, and the circuit MCr has a holding unit HCr. The holding unit HC and the holding unit HCr each store information (for example, a potential, a resistance value, or a voltage The first data set in the circuit MP[i,j] is w i (k-1) j (k) is the information stored in the storage unit HC and the storage unit HCr (e.g. For example, the potential, resistance, or current value is determined according to the holding section HC and the holding unit HCr store the first data w i (k-1) j (k) Each piece of information (e.g. For example, the potential, resistance, or current value of the wiring IL[j] and the wiring ILB[ j] is electrically connected to

[0118] The wiring WL[i] shown in FIG. 5A corresponds to the wiring WLS[i] in FIG. 2. L[i] is electrically connected to each of the holding unit HC and the holding unit HCr. The first data w is stored in each of the holding unit HC and the holding unit HCr included in P[i,j]. i (k -1) j (k) Write information (such as potential, resistance, or current) according to the When the potential is applied to the wiring WL[i], the wiring IL[j] and the holding unit H C is brought into a conductive state, and the wiring ILB[j] and the holding unit HCr are brought into a conductive state. , wiring IL[j], wiring ILB[j], and the first data w i (k-1) j (k) to By supplying a potential etc. according to the holding part HC and the holding part HCr, The potential can then be input. After that, a predetermined potential is supplied to the wiring WL[i], The wiring IL[j] and the holding unit HC are brought into a non-conductive state, and the wiring ILB[j] and the holding unit HCr Then, the first data is stored in each of the holding unit HC and the holding unit HCr. w i (k-1) j (k) Each potential according to the above is maintained.

[0119] For example, the first data i (k-1) j (k) is one of the three values ​​"-1", "0" or "1". Consider the case where either of the first data w i (k-1) j (k) If is "1", for example As a result, a high level potential is held in the holding unit HC, and a low level potential is held in the holding unit HCr. Also, the first data i (k-1) j (k) is "-1", for example, the holding part H C holds a low level potential, and the holding section HCr holds a high level potential. Ta w i (k-1) j (k) is "0", for example, a low level potential is applied to the holding unit HC. As another example, the first data w i (k-1) j (k) is an analog value, specifically a "negative analog value", "0", or , consider the case where the first data w takes a "positive analog value." i(k-1) j (k) is "positive In the case of the "analog value", for example, a high level analog potential is held in the holding unit HC, The holding unit HCr holds a low level potential. i (k-1) j (k) but" In the case of a "negative analog value", for example, a low level potential is held in the holding unit HC, and A high level analog potential is held in HCr. i (k-1) j (k ) is "0", for example, a low level potential is held in the holding unit HC, and the holding unit HCr The analog value is a multi-bit (multi-value) digital value. That is, as an example, the first data w i (k-1) j (k) But, "1", In the case where the numbers are "2" and "3", for example, the holder HC has a number corresponding to "1", "2", and "3". The high level potential having the potential set by the voltage applied to the capacitor is held in the holding section HCr, and the low level potential is held in the holding section HCr. , the first data w i (k-1) j (k) If is "-1", "-2", "-3", for example The holding section HC holds a low level potential, and the holding section HCr holds "-1", "-2" ", "-3" respectively. And the first data i (k-1) j (k) is "0", as an example, A low level potential is held in HC, and a low level potential is held in the holding section HCr.

[0120] Also, as an example, the circuit MC stores information (for example, potential, resistance value) stored in the storage unit HC. , current value, etc.) of wiring OL[j] or wiring OLB[j] The circuit MCr has a function of outputting information (for example, current or voltage according to the value of the wiring OL[j] or wiring OL For example, if a high-level potential is held in the holding unit HC, the holding unit HC has the function of outputting the high-level potential to the other of B[j]. When the voltage Vcc is high, the circuit MC outputs a current having a first current value, and the holding unit HC holds a low level potential. When the circuit MC is held, the circuit MC outputs a current having a second current value. When the holding portion HCr is held at a high level potential, the circuit MCr flows a current having a first current value. When the low level potential is held in the holding section HCr, the circuit MCr outputs a second current value The first current value and the second current value are output as follows: The configuration of the circuit MC, the circuit MCr, the holding unit HC, the holding unit HCr, etc., and the first data w i (k- 1) j (k) For example, the first current value is greater than the second current value. Furthermore, one of the first current value or the second current value may be zero. Current, i.e., the current value may be 0. Or, current with a first current value and current with a second current value may be In particular, for example, the first data w i (k -1) j (k) When takes one of the three values ​​"-1", "0" or "1", the first current value or It is preferable to configure the circuit MC and the circuit MCr so that one of the first and second current values ​​is zero. In addition, the first data i (k-1) j (k) is an analog value, e.g., "negative analog If the value is "0", "1", or "positive analog value", the first current value or the second current value For example, the value of can also be an analog value.

[0121] In this specification and the like, the information held in the holding unit HC and the holding unit HCr (for example, For example, a current or voltage according to a potential, resistance, or current value is a positive current or voltage. Alternatively, a negative current or voltage may be used, or both positive and negative currents or voltages may be mixed. That is, for example, the information stored in the storage unit HC (for example, potential, resistance value, current current or voltage according to the value) to either wiring OL[j] or wiring OLB[j]. The circuit MCr has a function of outputting information (for example, potential, resistance) stored in the storage unit HCr. The current, voltage, etc. according to the resistance, current value, etc. of the wiring OL[j] or wiring OLB[j] The phrase "has the function of outputting to the other party" means "information stored in the storage unit HC (for example, The current or voltage according to the potential, resistance, current value, etc. is applied to the wiring OL[j] or wiring O LB[j] from one side, and the circuit MCr discharges the current held in the holding section HCr. The current corresponding to the potential is discharged from the other of the wiring OL[j] and the wiring OLB[j]. This can be rephrased as "the

[0122] The wiring X1L[i] and the wiring X2L[i] shown in FIG. 5A correspond to the wiring XLS in FIG. [i]. The second data z input to the circuit MP[i,j] corresponds toi (k-1) teeth For example, the potentials and currents of the wiring X1L[i] and the wiring X2L[i] Therefore, the circuit MC and the circuit MCr are provided with, for example, wiring X1L[ i] and the second data z i (k-1) Each potential is input according to can be.

[0123] The circuit MC is electrically connected to the wiring OL[j] and the wiring OLB[j]. r is electrically connected to the wiring OL[j] and the wiring OLB[j]. For example, the circuit MCr receives the voltages input to the wiring X1L[i] and the wiring X2L[i]. The first data w is applied to the wiring OL[j] and the wiring OLB[j] according to the potential, current, etc. i (k- 1) j (k) and the second data z i (k-1) It outputs a current, potential, etc. according to the product of As a specific example, the current output destination from the circuit MC and the circuit MCr is the wiring X1L[i] and the potential of the wiring X2L[i]. For example, Each of them is a current output from the circuit MC to either the wiring OL[j] or the wiring OLB[j]. The current output from the circuit MCr flows to the other of the wiring OL[j] or wiring OLB[j]. It is a flowing circuit configuration. In other words, the output from the circuit MC and the circuit MCr The respective currents do not flow through the same wiring, but through different wirings. , the circuit MC and the circuit MCr are connected to either the wiring OL[j] or the wiring OLB[j]. Sometimes there is no current.

[0124] For example, the second data z i (k-1) can take one of three values: "-1", "0", or "1". For example, the second data z i (k-1) If is "1", the circuit MP The circuit MC and the wiring OL[j] are in a conductive state, and the circuit MCr and the wiring OLB[j] are in a conductive state. For example, the second data z i (k-1) If is "-1", the circuit MP is connected between the circuit MC and the wiring OLB[j], and the circuit MCr and the wiring OL[j] For example, the second data z i (k-1) If is "0", the circuit M The currents output by the wiring OL[j] and the circuit MCr are respectively ], the circuit MP is connected between the circuit MC and the wiring OL[j]. , and the circuit MC and the wiring OLB[j] are in a non-conductive state, and the circuit MCr and the wiring OL[ The circuit MCr and the wiring OLB[j] are brought into a non-conductive state, as well as the circuit MCr and the wiring OLB[j].

[0125] An example of the above operations is shown below. i (k-1) j (k) is "1" In this case, a current is output from the circuit MC, and the first data w i (k-1) j (k) is "-1" In this case, a current is output from the circuit MCr. i (k-1) is "1" In this case, the connection between the circuit MC and the wiring OL[j] and between the circuit MCr and the wiring OLB[j] The second data z i(k-1) If is "-1", then the circuit MC and Conduction occurs between the wiring OLB[j] and the circuit MCr and the wiring OL[j]. From the above, the first data i (k-1) j (k) and the second data z i (k-1) product of When the first data w is a positive value, a current is output to the wiring OL[j]. i (k-1) j (k) and the second data z i (k-1) If the product is negative, the current flows through the wiring OLB[j]. The first data w is output. i (k-1) j (k) and the second data z i (k-1) The product of is zero When the value is , no current is output to either wire.

[0126] To take the above example as a specific example, the first data w i (k-1) j (k) is "1" And the second data z i (k-1) is "1", for example, from the circuit MC to the wiring OL A current I1[i, j] with a first current value flows through the wiring OLB[j] from the circuit MCr. A current I2[i, j] having a second current value flows through the first current I2[i, j]. At this time, the magnitude of the second current value is For example, it is zero. In other words, strictly speaking, the current from the circuit MCr to the wiring OLB[j] is It doesn't flow. First data i (k-1) j (k) is "-1", and the second data z i (k -1) If is "1", for example, a current having a second current value is sent from the circuit MC to the wiring OL[j]. A current I1[i, j] flows, and a current I2 with a first current value flows from the circuit MCr to the wiring OLB[j]. [i, j] flows. At this time, the magnitude of the second current value is, for example, zero. In other words, strictly speaking, no current flows from the circuit MC to the wiring OL[j]. i (k- 1) j (k) is "0", and the second data z i (k-1) If is "1", the circuit M A current I1[i, j] having a second current value flows from C to the wiring OL[j], and a current I2[i, j] flows from the circuit MCr to the wiring OL[j]. A current I2[i, j] having a second current value flows through the line OLB[j]. At this time, the second current value For example, the magnitude of is zero. In other words, strictly speaking, from the circuit MC to the wiring OL[j ], and no current flows from circuit MCr to wiring OLB[j].

[0127] Also, the first data i (k-1) j (k) is "1", and the second data z i (k-1 ) When is "-1", a current I1[ i, j] flows from the circuit MCr to the wiring OL[j], and a current I2[i, j] with a second current value flows At this time, the magnitude of the second current value is, for example, zero. In this case, no current flows from the circuit MCr to the wiring OL[j]. i (k-1) j ( k) is "-1", and the second data zi (k-1) If is "-1", the circuit MC A current I1[i, j] with a second current value flows from the circuit MCr to the wiring OLB[j]. A current I2[i, j] with a first current value flows through OL[j]. At this time, a current I2[i, j] with a second current value flows through OL[j]. For example, the magnitude is zero. In other words, strictly speaking, the wiring OLB[j] from the circuit MC No current flows through the first data i (k-1) j (k) is "0", and the second data z i (k-1) If is "-1", the second current value flows from the circuit MC to the wiring OLB[j]. Current I1[i, j] flows, and current I2 with a second current value flows from circuit MCr to wiring OL[j]. [i, j] flows. At this time, the magnitude of the second current value is, for example, zero. Strictly speaking, no current flows from the circuit MC to the wiring OLB[j], and no current flows from the circuit MCr to the wiring O No current flows through L[j].

[0128] Also, the second data z i (k-1) When is "0", for example, the circuit MC and the wiring OL[j] and between the circuit MC and the wiring OLB[j]. , between the circuit MCr and the wiring OL[j], and between the circuit MCr and the wiring OLB[j] Therefore, the first data w i (k-1) j (k) Whatever the value of No current is output from the circuit MC and the circuit MCr to the wiring OL[j] and the wiring OLB[j]. stomach.

[0129] In this way, as an example, the first data w i (k-1)j (k) and the second data z i (k -1) If the product of is positive, the wiring is A current flows through OL[j]. At this time, the first data w i (k-1) j (k) If is a positive value In this case, a current flows from the circuit MC to the wiring OL[j], and the first data w i (k-1) j (k) When the value of is negative, a current flows from the circuit MCr to the wiring OL[j]. w i (k-1) j (k) and the second data z i (k-1) If the product of is negative, A current flows through the wiring OLB[j] from either the circuit MC or the circuit MCr. First data w i (k-1) j (k) If is a positive value, the wiring OLB[j] from the circuit MC A current flows through the first data w i (k-1) j (k) If is negative, then from the circuit MCr Current flows through the wiring OLB[j]. Therefore, multiple circuits M connected to the wiring OL[j] The sum of the currents output from C or the circuit MCr flows through the wiring OL[j]. In other words, a current that is the sum of positive values ​​flows through the wiring OL[j]. On the other hand, the current output from multiple circuits MC or MCr connected to wiring OLB[j] The sum of the negative current flows to the wiring OLB[j]. As a result of the above operation, a current equal to the sum of the values ​​flows through the wiring OL[ The total current value flowing through wiring OLB[j], that is, the sum of the positive values, and the total current value flowing through wiring OLB[j], In other words, by using the sum of negative values, it is possible to perform product-sum calculations. For example, the total current value flowing through wiring OL[j] is greater than the total current value flowing through wiring OLB[j]. If it is larger, it can be determined that the result of the multiplication and accumulation operation will be a positive value. If the total current value flowing through OL[j] is smaller than the total current value flowing through wiring OLB[j], In this case, it can be determined that the result of the sum-of-products operation is a negative value. ] and the total current value flowing through wiring OLB[j] are approximately the same value. It can be determined that the result of the multiplication and addition operation is zero.

[0130] In addition, the second data z i (k-1) is one of two values: "-1", "0", or "1" For example, the binary values ​​"-1" and "1" or the binary values ​​"0" and "1" are also the same. Similarly, the first data w i (k-1) j (k) is "-1", Either two values ​​of "0" or "1", for example, "-1" or "1", Alternatively, it can operate in the same way when the binary values ​​are "0" and "1".

[0131] In addition, the first data i (k-1) j (k) is an analog value or multi-bit (multi-valued) A specific example is to use "negative analog" instead of "-1". value” and “1” can be replaced by “positive analog value”. In this case, the circuit M The magnitude of the current flowing from C or the circuit MCr is also, for example, the first data w i (k-1 ) j (k) The analog value corresponds to the absolute value of the value.

[0132] Next, an example of modifying the circuit MP[i,j] in FIG. 5A will be described. Regarding the modified example of [i,j], the difference from the circuit MP[i,j] of FIG. 5A will be mainly explained. , the description of the parts common to the circuit MP[i,j] in FIG. 5A may be omitted.

[0133] The circuit MP[i,j] shown in FIG. 5B is a modified example of the circuit MP[i,j] in FIG. 5A. The circuit MP[i,j] of FIG. 5B is the same as the circuit MP[i,j] of FIG. 5A, but is composed of a circuit MC and a circuit However, the circuit MP[i,j] in FIG. 5B includes a holding unit HCr in the circuit MCr. 5A in that it does not include

[0134] Also, since the circuit MCr does not have a holding unit HCr, the circuit MP[i,j] in FIG. The applied arithmetic circuit uses the wiring ILB[j] to supply the potential to be held in the holding unit HCr. In addition, the circuit MCr may not be electrically connected to the wiring WL[i]. Good too.

[0135] In the circuit MP[i,j] of FIG. 5B, the holding unit HC included in the circuit MC is That is, the circuit MP[i,j] in FIG. 5B is electrically connected to the circuit MCr and the circuit MC and the holding unit HC are configured to share each other. The inverted signal of the signal held in C is supplied from the holding unit HC to the circuit MCr. This allows the circuits MC and MCr to operate differently. Alternatively, the internal circuit configurations of the circuits MC and MCr may be different. The voltages output by the circuits MC and MCr for the same signal held by the holding unit HC are It is also possible to make the magnitude of the flow different. i (k-1) j (k) and holds the potential according to the second data z i (k-1) Apply a potential according to By supplying the line X1L[i] and the wiring X2L[i], the circuit MP[i,j] is The first data w i (k-1) j (k) and Day 2 Taz i (k-1) It is possible to output a current according to the product of

[0136] The arithmetic circuit 110 to which the circuit MP of FIG. 5B is applied is the same as the circuit of the arithmetic circuit 120 shown in FIG. The arithmetic circuit 120 can be changed to a wiring configuration from the arithmetic circuit 110 in FIG. The configuration excludes wiring B[1] to wiring ILB[m].

[0137] The circuit MP[i,j] shown in FIG. 5C is a modified example of the circuit MP[i,j] in FIG. 5A. Specifically, this is an example of the configuration of the circuit MP[i,j] that can be applied to the arithmetic circuit 120 in FIG. The circuit MP[i,j] of C is the same as the circuit MP[i,j] of FIG. 5A, and is composed of the circuit MC and the circuit M Cr. However, the circuit MP[i,j] in FIG. 5C and the circuit MP[i,j] in FIG. 5A have , the configuration of the electrically connected wiring is different.

[0138] The wiring W1L[i] and the wiring W2L[i] shown in FIG. 5C are the wiring WLS The wiring W1L[i] is electrically connected to the holding unit HC, and the wiring W2L[i ] is electrically connected to the holding part HCr.

[0139] The wiring IL[j] is electrically connected to the holding portion HC and the holding portion HCr. .

[0140] In the circuit MP[i,j] of FIG. 5C, different When holding the potential, the holding operation of the potential to the holding part HC and the holding part HCr is not simultaneous, For example, the first data w of the circuit MP[i,j] i (k-1) j (k ) can be expressed by holding the first potential in the holding part HC and the second potential in the holding part HCr. First, a predetermined voltage is applied to each of the wiring W1L[i] and the wiring W2L[i]. By applying a potential, the holding unit HC and the wiring IL[j] are brought into a conductive state, and the holding unit HCr and the wiring IL[j] are brought into a conductive state. Next, a first potential is supplied to the wiring IL[j]. Then, the first potential can be applied to the holding unit HC. A predetermined potential is applied to each of the lines W2L[i], and a potential is applied between the holding unit HC and the wiring IL[j]. The holding unit HCr and the wiring IL[j] are brought into a non-conductive state, and the holding unit HCr and the wiring IL[j] are brought into a conductive state. By supplying the second potential to the wiring IL[j], the second potential can be applied to the holding unit HCr. As a result, the circuit MP[i,j] receives w as the first data. i(k-1) j (k) of It can be set.

[0141] In addition, when the holding section HC and the holding section HCr are held at approximately the same potential (circuit M The first data w of P[i,j] i (k-1) j (k) However, the holding part HC and the holding part HCr (When the voltage is set by holding the voltage at the holding section HC and the wiring IL and the holding unit HCr and the wiring IL[j] are in a conductive state. In this way, a predetermined potential is applied to each of the wiring W1L[i] and the wiring W2L[i]. After that, the potential is supplied to the wiring IL[j].

[0142] The circuit MP[i,j] in FIG. 5C stores first data w in the holding unit HC and the holding unit HCr. i (k -1) j (k) and holds the potential according to the second data z i (k-1) Wire X with a potential according to 1L[i] and wiring X2L[i], the circuit MP[i,j] in FIG. 5A Similarly, the first data w i (k-1) j (k) and the second data z i (k-1) It is possible to output a current according to the product of

[0143] The circuit MP[i,j] shown in FIG. 5D is a modified version of the circuit MP[i,j] in FIG. 5A. The circuit MP[i,j] of FIG. 5D is composed of a circuit MC and a circuit MCr, where the circuit MP[i,j] in FIG. 5D and the circuit MP[i,j] in FIG. 5A The configuration of the electrically connected wiring is different.

[0144] The wiring IOL[j] in FIG. 5D is a combination of the wiring IL[j] and the wiring OL[j] in FIG. 5A. The wire IOLB[j] in Figure 5D functions as a bundled wire. LB[j] and wiring OLB[j] function as a single wiring. The IOL[j] is electrically connected to the holding portion HC, the circuit MC, and the circuit MCr, and is connected to the wiring The IOLB[j] is electrically connected to the holding unit HCr, the circuit MC, and the circuit MCr. There are.

[0145] The circuit MP[i,j] in FIG. 5D is i (k-1) j (k) When holding Therefore, between the circuit MC and the wiring IOL[j], and between the circuit MC and the wiring IOLB[j] becomes non-conductive, and the circuit MCr and the wiring IOL[j] and the circuit MCr and the wiring IOL[j] become non-conductive. The wiring X1L[i] and the wiring X2L[ A predetermined potential is input to the wiring WL[i]. Then, a predetermined potential is input to the wiring WL[i] and maintained. The holding unit HC and the wiring IOL[j] are electrically connected, and the holding unit HCr and the wiring IOLB[j ] and the wiring IOL[j] and the wiring IOLB[j] are connected to each other. 1 data w i (k-1) j (k) By supplying each potential according to Each potential can be input to the holding unit HC and the holding unit HCr. The connection between the holding part HCr and the wiring IOL[j] is non-conductive, and the connection between the holding part HCr and the wiring IOLB[j] is non-conductive. By inputting a predetermined potential to the wiring WL[i], the connection between the wirings is made non-conductive. The first data w is stored in each of the holding unit HC and the holding unit HCr. i (k-1) j (k) According to each The potential can be maintained.

[0146] The first data w is stored in each of the holding unit HC and the holding unit HCr. i (k-1) j (k) Depending on After the potential is maintained, the second data z i (k-1) The potential according to the wiring X1L[i] and By supplying the signal to the wiring X2L[i], the wiring is connected in the same manner as the circuit MP[i,j] in FIG. 5A. OL[j] and wiring OLB[j], the first data w i (k-1) j (k) and the second data z i (k-1) It is possible to output a current according to the product of

[0147] The arithmetic circuit 110 to which the circuit MP of FIG. 5D is applied is the same as the circuit of the arithmetic circuit 130 shown in FIG. The arithmetic circuit 130 can be changed to the circuit configuration in the arithmetic circuit 110 of FIG. The lines IL[1] to IL[n] and the lines OL[1] to OL[n] are connected to the wiring IO L[1] to IOL[n] are grouped together, and wiring ILB[1] to ILB[n] are grouped together. , wiring OLB[1] to wiring OLB[n], and wiring IOLB[1] to wiring IOLB[n] n]. In the arithmetic circuit 130, the wiring IOL[1 ] to IOL[n], and wirings IOLB[1] to IOLB[n] are connected to the circuit ILD. The wiring I is electrically connected to the circuits ACTF[1] to ACTF[n]. The wirings OL[1] to IOL[n] and the wirings IOLB[1] to IOLB[n] are circuits For MP[1,j] to MP[m,j], the first data w i (k-1) j (k) Send and a current line for supplying current to the circuit ACTF[j]. In this case, when the first data wi(k-1)j(k) is sent to the circuit MP[i,j], , the circuit ILD is the connection between the circuit ILD and the wiring IOL[j], and between the circuit ILD and the wiring IOLB[j] and the circuit ACTF[j] is in a conductive state, and the circuit ACTF[j] is in a conductive state between the circuit ACTF[j] and the wiring IOL[j] and between the circuits ACTF[j] and IOLB[j]. And when supplying current to the circuit ACTF[j], the circuit ILD is The wiring IOL[j] and the circuit ILD and IOLB[j] are in a non-conductive state. ACTF[j] is the circuit ACTF[j] and the wiring IOL[j], and the circuit ACTF[j ] and IOLB[j] are preferably in a conductive state.

[0148] The circuit MP[i,j] shown in FIG. 5E is a modified example of the circuit MP[i,j] in FIG. 5A. Specifically, this is an example of the configuration of the circuit MP[i,j] that can be applied to the arithmetic circuit 110 in FIG. The circuit MP[i,j] of E is the same as the circuit MP[i,j] of FIG. 5A, and is composed of the circuit MC and the circuit M However, the circuit MP[i,j] in FIG. 5E has a circuit MC connected to the wiring OLB[j]. The circuit MCr is electrically connected to the wiring OL[j]. 5A and the circuit MP[i,j] in FIG.

[0149] The wiring WL[i] shown in FIG. 5E corresponds to the wiring WLS[i] in FIG. 2. L[i] is electrically connected to the holding unit HC and the holding unit HCr.

[0150] 2. The wiring XL[i] shown in FIG. 5E corresponds to the wiring XLS[i] in FIG. The wiring XL[i] is electrically connected to the circuit MC and the circuit MCr.

[0151] As will be described later, the circuit MP[i,j] in FIG. 5E is a circuit in which the circuit MC is electrically connected to the wiring OLB[j]. , and the circuit MCr is not electrically connected to the wiring OL[j]. 5A to 5E, the circuit MP[i,j] in FIG. 5E is different from the circuit MP[i,j] in FIG. The current output from the circuit MC does not flow through the wiring OLB[j], and the current output from the circuit MCr is configured so that it does not flow into wiring OL[j].

[0152] Therefore, the circuit MP[i,j] of FIG. 5E receives the second data z i (k-1) is "0", or For example, when the second data z i (k-1) When the value is "1", the circuit MP establishes a conductive state between the circuit MC and the wiring OL[j]. In this state, the circuit MCr and the wiring OLB[j] are electrically connected. Data z i (k-1) When is "0", the voltages output by the circuits MC and MCr are In order to prevent current from flowing to either wiring OL[j] or OLB[j], the circuit MP Between MC and wiring OL[j], and between circuit MC and wiring OLB[j], a non-conductive state is established. Between the circuit MCr and the wiring OL[j], and between the circuit MCr and the wiring OLB[j], Put into a non-conducting state.

[0153] The circuit MP[i,j] in FIG. 5E can be applied to the arithmetic circuit 110 to obtain, for example: is the first data w i (k-1) j (k) can take one of three values: "-1", "0", or "1". Take the second data z i (k-1) When the value is "0" or "1", the calculation is performed. The circuit MP[i,j] in FIG. 5E stores the first data w i (k-1) j ( k) is "-1", "0", "1", or any two values, for example, "-1", "1 It can also operate in the case of two values ​​of "0" and "1". Oh, the first data i (k-1) j (k) is an analog value or a multi-bit (multi-value) data A specific example would be a "negative analog value" instead of "-1". , and "positive analog value" may be used instead of "1". In this case, the circuit MC Alternatively, the magnitude of the current flowing from the circuit MCr may be, for example, the first data w i (k-1) j (k) The analog value corresponds to the absolute value of the value.

[0154] <Example of operation of an arithmetic circuit> Next, an example of the operation of the arithmetic circuit 110 in Fig. 2 will be described. As an example, the arithmetic circuit 110 shown in FIG. 8 is used.

[0155] The arithmetic circuit 110 in FIG. 8 is illustrated by focusing on the circuit located in the j-th column of the arithmetic circuit 110 in FIG. That is, the arithmetic circuit 110 of FIG. 8 is the same as the neural network shown in FIG. 1A. Neuron N in Network 100 j (k) neuron N1 (k-1 ) Neuron N m (k-1) Signal z1 from (k-1) ~z m (k-1) and weight Coefficient w1 (k-1) j (k) Or even w m (k-1) j (k) and the sum of products operation The calculation circuit 1 in FIG. The circuit MP included in the array unit ALP of 10 is the circuit MP of FIG. 5A. Let's say.

[0156] First, in the arithmetic circuit 110, the first Data w1 (k-1) j (k) Or even w m (k-1) j (k) The first data w is set. i (k-1) j (k) As a method of setting, the wiring WLS[1] A predetermined potential is input to the wiring WLS[m] in order, and the circuits MP[1,j] to MP[m , j] in order, and the holding part HC of the circuit MC included in the selected circuit MP, For the holding part HCr of the circuit MCr, from the circuit ILD, the wiring IL[j], the wiring ILB After the supply of the potential, the circuit W Deselecting each of the circuits MP[1,j] to MP[m,j] by LD By this, the holding of the circuit MC that each of the circuits MP[1,j] to MP[m,j] has The first data w1 is stored in the storage unit HC and the storage unit HCr of the circuit MCr. (k-1) j (k) Or even w m ( k-1) j (k) As an example, the potential corresponding to the first data w1 (k-1) j (k) Or even w m (k-1) j (k) When each of the values ​​is positive, In the hold part HC, enter a value corresponding to the positive value, and in the hold part HCr, enter a value corresponding to zero. On the other hand, the first data w1 (k-1) j (k) Or even w m (k-1) j (k ) If each of these takes a negative value, the value equivalent to zero is entered in the holding section HC. The holding unit HCr receives a value corresponding to the absolute value of the negative value.

[0157] Next, the wirings X1L[1] to X1L[m] and X2L[1 ] to wiring X2L[m], (k-1) ~z m (k-1) of As a specific example, the second data is supplied to the wiring X1L[i] and the wiring X2L[i]. z i (k-1) The wiring X1L[i] and wiring X2L[i] are shown in FIG. This corresponds to the wiring XLS[i] of the arithmetic circuit 110.

[0158] Second data z1 input to each of the circuits MP[1,j] to MP[m,j] ( k-1) ~z m (k-1) According to the circuit MP[1,j] to the circuit MP[m,j], The conduction state between the circuit MC and the circuit MCr and the wiring OL[j] and the circuit OLB[j] As a specific example, the circuit MP[i,j] is determined by the second data z i (k-1) In response As a result, "continuity occurs between the circuit MC and the wiring OL[j], and the circuit MCr and the wiring OLB[j] and "conduction occurs between the circuit MC and wiring OLB[j], and the circuit MCr and wiring OL[j] are electrically connected, and the circuit MC and the circuit MCr are electrically connected. Each of them takes one of two states: "non-conductive" with wiring OL[j] and wiring OLB[j], or "non-conductive" with wiring OL[j]. For example, the second data z1 (k-1) If the value is positive, wire X1 In L[1], the circuit MC and the wiring OL[j] are in a conductive state, and the circuit MCr and Enter a value that will bring the line between OLB[j] and the line into a conductive state. , the circuit MC and the wiring OLB[j] are in a non-conductive state, and the circuit MCr and the wiring OL Then, input the value that makes the connection between [j] and [j] non-conductive. (k-1) Two If the value is negative, the wiring X2L[1] has a connection between the circuit MC and the wiring OLB[j]. Enter a value that will bring the circuit MCr and wiring OL[j] into a conductive state. Then, the wiring X1L[1] is in a non-conductive state between the circuit MC and the wiring OL[j]. and a value that brings the circuit MCr and the wiring OLB[j] into a non-conductive state is input. And the second data z1 (k-1) If the value of 1 is zero, ], the circuit MC and the wiring OLB[j] are in a non-conductive state, and the circuit MCr and the wiring OLB[j] are in a non-conductive state. Input a value that will cause a non-conductive state between the wire OL[j] and the wire X1L[1]. When the circuit MC and the wiring OL[j] are in a non-conductive state, and the circuit MCr and the wiring OLB[ j].

[0159] The second data z input to the circuit MP[i,j] i (k-1) Depending on the circuit MP[i, [j] and the wiring OL[j] and the circuit OLB[j]. The conduction state or non-conduction state between the circuit MC and the circuit MCr and the wiring is determined by the determination. Current is input / output between OL[j] and wiring OLB[j]. The amount is the first data w set in the circuit MP[i,j]. i (k-1) j (k) and / or 2 Dataz i (k-1) It depends on:

[0160] For example, in the circuit MP[i,j], the wiring OL[j] is connected to the circuit MC or the circuit MCr. Let I[i,j] be the current flowing through the wiring OLB[j] to the circuit MC or the circuit MCr. The current flowing through the B [i,j]. Then, the current flows from the circuit ACTF[j] to the wiring OL[j]. The current flowing through the out [j], and the current flowing from wiring OLB[j] to circuit ACTF[j] I Bout If [j], then I out [j] and I Bout [j] can be expressed by the following formula: This can be done.

[0161]

number

[0162] In the circuit MP[i,j], as an example, the first data w i (k-1) j (k) "+ 1", the circuit MC outputs I(+1) and the circuit MCr outputs I(-1). The first data w i (k-1) j (k) When is "-1", the circuit MC is I(-1 ) and the circuit MCr outputs I(+1), and the first data w i (k-1) j (k) When is "0", the circuit MC emits I(-1) and the circuit MCr emits I(-1). shall be discharged.

[0163] Furthermore, the circuit MP[i,j] receives the second data z i (k-1) When is "+1", Conduction occurs between the circuit MC and the wiring OL[j], and conduction occurs between the circuit MCr and the wiring OLB[j]. Conduction occurs, and there is no conduction between the circuit MC and the wiring OLB[j], and there is no conduction between the circuit MCr and the wiring OL [j] is in a non-conductive state, and the second data z i (k-1) is "-1" When this happens, "there is conduction between the circuit MC and the wiring OLB[j], and the circuit MCr and the wiring OL[j ] becomes conductive, and the circuit MC and the wiring OL[j] become non-conductive, and the circuit MCr and The second data z i (k-1) is "0 "When "circuit MC and wiring OL[j], and circuit MC and OLB[j] There is no conduction between the circuit MCr and the wiring OL[j], and between the circuit MCr and the wiring OL[j]. There is no conduction between the circuit MCr and the line OLB[j], and there is no conduction between the circuit MCr and the line OL[j], and The state between the circuits MCr and OLB[j] is assumed to be "non-conductive."

[0164] At this time, in the circuit MP[i,j], the wiring OL[j] is connected to the circuit MC or the circuit MC The current I[i,j] flowing through r and the current I[i,j] flowing from wiring OLB[j] to circuit MC or circuit MCr The current I B [i,j] is as shown in the table below. In some cases, I(- The circuit MP[i,j] may be configured so that the current amount of 1) is 0. i,j] may be a current flowing from the circuit MC or the circuit MCr to the wiring OL[j]. Similarly, the current I B [i,j] flows from the circuit MC or the circuit MCr to the wiring OLB[j]. It may also be an electric current.

[0165] [Table 1]

[0166] Then, I flowing from each of the wiring OL[j] and wiring OLB[j] out [ j] and I Bout [j] is input to the circuit ACTF[j]. , Circuit ACTF[j] is, for example, I out [j] and I Bout [j] comparison The circuit ACTF[j] performs, for example, the following operations depending on the result of the comparison: N j (k) is the signal z sent to the (k+1)th layer neuron. j (k) Output.

[0167] As an example, the arithmetic circuit 110 of FIG. j (k) is entered into Neuron N1 (k-1) Neuron N m (k-1) Signal z1 from (k-1) ~ z m (k-1) and weighting factor w1 (k-1) j (k) Or even w m (k-1) j (k) And, It is possible to perform a product-sum operation and a calculation of an activation function using the result of the product-sum operation. In addition, in the array part ALP of the arithmetic circuit of FIG. 8, by providing n columns of circuits MP, the arithmetic circuit of FIG. In other words, the arithmetic circuit 110 of FIG. Ron N1 (k) Neuron N n (k) and the sum of products in each of the The activation function can be calculated using the result of the calculation at the same time.

[0168] <<Example of changing circuits included in the arithmetic circuit>> The above-mentioned array part ALP, circuit ILD, circuit WLD, circuit XLD, circuit AFP, circuit Some or all of the transistors included in each of the MPs are, for example, For example, it is desirable to have a low off-state current. Such a transistor, for example, a transistor having a function of retaining charge accumulated in a capacitor element, The transistor is preferably an OS transistor. When an OS transistor is used as the OS transistor, the OS transistor may be the OS transistor described in Embodiment 3. However, one embodiment of the present invention is not limited to this. Not determined.

[0169] Also, the array part ALP, the circuit ILD, the circuit WLD, the circuit XLD, the circuit AFP, the circuit MP The transistors included in the above are, in addition to OS transistors, for example, channel-type It can also be used as a transistor containing silicon in the compound region (hereinafter referred to as a Si transistor). As the silicon, for example, single crystal silicon or hydrogenated amorphous silicon can be used. The OS transistor may be made of silicon, microcrystalline silicon, polycrystalline silicon, or the like. As for transistors other than Si transistors, for example, semiconductors such as Ge are used. Layered transistors, ZnSe, CdS, GaAs, InP, GaN, SiGe, etc. Transistors with compound semiconductor active layers, transistors with carbon nanotubes active layers A transistor having an organic semiconductor as an active layer, or the like can be used.

[0170] In the metal oxide semiconductor layer of the OS transistor, a metal oxide containing indium In oxides containing zinc (e.g., In oxide), Although n-type semiconductors have been successfully fabricated, p-type semiconductors are difficult to fabricate due to mobility and reliability issues. Therefore, the arithmetic circuit 110, the arithmetic circuit 120, and the arithmetic circuit 130 are n circuits included in LP, circuit ILD, circuit WLD, circuit XLD, circuit AFP, circuit MP, etc. An OS transistor is used as a p-channel transistor. A configuration using Si transistors may also be used.

[0171] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. do.

[0172] (Embodiment 2) In this embodiment, a specific configuration example of the circuit MP described in the first embodiment will be described. do.

[0173] In the first embodiment, the reference numerals of the circuits MP are denoted by [1,1 ], [i,j], [m,n], etc. are added, but in this embodiment, unless otherwise specified, The notation [1,1], [i,j], [m,n], etc. is omitted for the symbols of the MP.

[0174] <Configuration example 1> First, an example of a circuit configuration that can be applied to the circuit MP of FIG. 5A will be described. The circuit MP is an example of the configuration of the circuit MP of FIG. 5A, and is a circuit included in the circuit MP of FIG. 9A. The circuit MC includes, for example, a transistor M3, a transistor M4, and a transistor M8. For example, the transistor M8 and the capacitance element C3 The holding portion HC is formed by these.

[0175] The transistors M3, M4, and M8 shown in FIG. For example, an n-channel transistor with a multi-gate structure that has gates above and below the channel The transistors M3, M4, and M8 are In particular, as an example, the first gate and the second gate of the transistors M3 and M4 are However, for the sake of convenience, the size of each is set as an example in this specification. The first gate is called the gate (sometimes called the front gate), and the second gate is called the back gate. Although the gates are listed separately, the first and second gates are interchangeable. Therefore, in this specification, the term "gate" is used to mean "backgate." Similarly, the term "back gate" can be used interchangeably with the term "gate." The phrase can be written interchangeably with the word "gate." The gate is electrically connected to the first wiring, and the back gate is electrically connected to the second wiring. The connection configuration is such that the back gate is electrically connected to the first wiring and the gate is electrically connected to the second wiring. This can be replaced with a connection configuration in which the wiring is electrically connected to the wiring.

[0176] Furthermore, the connection structure of the back gate of the transistor included in the semiconductor device of one embodiment of the present invention The transistor M8 shown in FIG. 9A has a back gate. The connection configuration of the back gate is not shown in the figure, but the back gate The electrical connection destination of the gate can be determined at the design stage. In a transistor with a gate and back gate, in order to increase the on-current of the transistor, For example, the gate of transistor M8 may be electrically connected to the backplane. The gate of the transistor may be electrically connected to the back gate. In a transistor, in order to vary the threshold voltage of the transistor or In order to reduce the off-state current of the transistor, wiring is provided that is electrically connected to an external circuit, etc. In this case, a potential may be applied to the back gate of the transistor by the external circuit or the like. 9A as well as other transistors described elsewhere in this specification. , or the transistors shown in other figures.

[0177] The structure of a transistor included in a semiconductor device of one embodiment of the present invention is not particularly limited. For example, transistor M8 shown in FIG. 9A is connected to the buffer as shown in FIG. 9B. It may be a transistor having a single gate structure, i.e., a structure without a gate. In addition, some transistors have a back gate, while other transistors The transistor may have a structure without a back gate. A. Circuit diagrams shown in A, as well as transistors or other The same applies to the transistors shown in the drawings.

[0178] In this specification and the like, transistors having various structures are used as transistors. Therefore, there is no limitation on the type of transistor to be used. Examples include transistors with single crystal silicon, or transistors with amorphous silicon, polycrystalline silicon, etc. Silicon, microcrystalline (also called microcrystal, nanocrystal, or semi-amorphous) A transistor having a non-single-crystal semiconductor film, such as a silicon nitride film, can be used. Alternatively, thin film transistors (TFTs) made from these semiconductors can be used. There are various advantages to using TFTs. For example, it is Since it can be manufactured at a very low temperature, it is possible to reduce manufacturing costs and increase the size of manufacturing equipment. Since the manufacturing equipment can be made larger, it is possible to manufacture on large substrates. Since a large number of display devices can be manufactured, they can be manufactured at low cost. Therefore, a substrate having low heat resistance can be used. Alternatively, a transistor on a light-transmitting substrate can be used to manufacture a display element. It is possible to control the light transmission. Also, because the film thickness of the transistor is thin, A part of the film that forms the capacitor can transmit light, which improves the aperture ratio. It is possible.

[0179] An example of a transistor is a compound semiconductor (e.g., SiGe, GaAs, etc.). ), or oxide semiconductors (e.g., Zn-O, In-Ga-Zn-O, In-Zn-O, I n-Sn-O(ITO), Sn-O, Ti-O, Al-Zn-Sn-O(AZTO), I A transistor having a material such as n-Sn-Zn-O can be used. These compound semiconductors or thin film transistors made by thinning these oxide semiconductors These can be used to lower the manufacturing temperature, for example, As a result, it is possible to manufacture a resistor on a substrate with low heat resistance, such as a plastic The transistor can be formed directly on a substrate or a film substrate. Compound semiconductors or oxide semiconductors are used not only for the channel portion of transistors but also for For example, these compound semiconductors or oxide semiconductors can be used for other purposes. It can be used as a wiring, a resistor element, a pixel electrode, or a light-transmitting electrode. These can be deposited or formed simultaneously with the transistor, thereby reducing costs.

[0180] Note that an example of a transistor is a transistor formed by an ink-jet method or a printing method. These can be used for manufacturing at room temperature, manufacturing at low vacuum, or can be manufactured on a large substrate. Therefore, it can be manufactured without using a mask (reticle). This allows the transistor layout to be easily changed. Alternatively, it can be manufactured without using resist, which reduces material costs and the number of processes. Or, since it is possible to apply the film only to the necessary parts, it is possible to apply the film only to the necessary parts after forming the film on the entire surface. This method wastes less material and is less costly than etching.

[0181] An example of a transistor is a transistor having an organic semiconductor or a carbon nanotube. This allows transistors to be mounted on a flexible substrate. Transistors using organic semiconductors and carbon nanotubes can be formed. The device using this can be made shock resistant.

[0182] Note that transistors with various other structures can also be used. For example, transistors include MOS transistors, junction transistors, and bipolar transistors. A MOS transistor can be used as the transistor. By using this, the size of the transistor can be reduced. It is possible to mount a bipolar transistor as a transistor. This allows a large current to flow, making it possible to operate the circuit at high speed. It is also possible to combine MOS transistors and bipolar transistors on the same substrate. This makes it possible to achieve low power consumption, miniaturization, high-speed operation, etc. can.

[0183] An example of a transistor is a structure in which gate electrodes are arranged above and below an active layer. The transistor can be applied to a structure in which gate electrodes are arranged above and below the active layer. This results in a circuit configuration in which multiple transistors are connected in parallel. Since the channel forming region increases, the current value can be increased. The structure in which gate electrodes are arranged above and below makes it easier for a depletion layer to form. , the S value can be improved.

[0184] An example of a transistor is a structure in which a gate electrode is disposed on an active layer. A structure in which a gate electrode is placed under an active layer, a normal staggered structure, an inverted staggered structure, a channel A structure in which the region is divided into multiple regions, a structure in which the active layers are connected in parallel, or a structure in which the active layers are connected in series Alternatively, a transistor having a structure such as a pre-transistor may be used. NA type, FIN type, TRI-GATE type, top gate type, bottom gate type, double gate type (gates are placed above and below the channel), etc. A variety of configurations can be used.

[0185] An example of a transistor is a transistor in which a source electrode or a drain electrode is formed in the active layer (or a part thereof). A transistor with an overlapping active layer (or its equivalent) can be used. By using a structure in which the source electrode and drain electrode overlap with part of the active layer, This can prevent the operation from becoming unstable due to accumulation of electric charges.

[0186] As an example of a transistor, a structure provided with an LDD region can be applied. By providing a region, the off-state current can be reduced or the withstand voltage of the transistor can be improved (reliability can be improved). Alternatively, by providing an LDD region, it is possible to , even if the voltage between the drain and source changes, the drain current does not change much, and the slope is A flat voltage-current characteristic can be obtained.

[0187] For example, in this specification and the like, it is possible to form transistors using various substrates. The type of substrate is not limited to a specific one. Conductor substrates (e.g., single crystal substrates or silicon substrates), SOI substrates, glass substrates, quartz substrates, Plastic substrate, sapphire glass substrate, metal substrate, stainless steel substrate, stainless Substrate with less steel foil, tungsten substrate, tungsten foil Substrates, flexible substrates, laminated films, paper containing fibrous materials, base film, etc. Examples of glass substrates include barium borosilicate glass and aluminoborosilicate glass. Glass or soda lime glass. Flexible substrates, laminating films, base film Examples of films include polyethylene terephthalate. Polyethylene naphthalate (PET), Polyethersulfone (PES) ), and polytetrafluoroethylene (PTFE) are typical plastics. For example, synthetic resin such as acrylic resin is used. Examples include polyethylene, polyester, polyvinyl fluoride, and polyvinyl chloride. Examples of the material include polyamide, polyimide, aramid, epoxy resin, inorganic vapor deposition film, and the like. In particular, transistors are manufactured using semiconductor substrates, single crystal substrates, or SOI substrates. By manufacturing the capacitors, there is little variation in characteristics, size, or shape, and current capacity is This allows for the production of high-power, small-sized transistors. By configuring a circuit using a capacitor, it is possible to reduce the power consumption of the circuit or to increase the integration density of the circuit. Cut.

[0188] In addition, a flexible substrate is used as the substrate, and a transistor is formed directly on the flexible substrate. Alternatively, a separation layer may be provided between the substrate and the transistor. After a semiconductor device is partially or completely completed, it is separated from the substrate and transferred to another substrate. In this case, the transistor can be transferred to a substrate with poor heat resistance or a flexible substrate. The above-mentioned peeling layer may be formed of an inorganic film such as a tungsten film and a silicon oxide film. It uses a laminated film structure or a structure in which an organic resin film such as polyimide is formed on a substrate. It is possible.

[0189] That is, a transistor is formed using one substrate, and then a transistor is formed on another substrate. The transistor may be transposed and placed on another substrate. For example, in addition to the substrate on which the above-mentioned transistors can be formed, a paper substrate, a cellophane substrate, etc. Fan board, aramid film board, polyimide film board, stone board, wood board, cloth Substrate (natural fibers (silk, cotton, linen), synthetic fibers (nylon, polyurethane, polyester) or recycled fibers (including acetate, cupra, rayon, recycled polyester, etc.), There are leather substrates, rubber substrates, etc. By using these substrates, Formation of transistors, formation of low power consumption transistors, manufacturing of durable devices, heat resistance It is possible to provide a lighter, thinner, or more flexible device.

[0190] All circuits required to realize a given function are mounted on the same substrate (e.g., glass It can be formed on a substrate such as a silicon substrate, a plastic substrate, a single crystal substrate, or an SOI substrate. This reduces the cost by reducing the number of components, or reduces the number of connections to circuit components. This can improve reliability.

[0191] It is possible that not all of the circuits required to realize a given function are formed on the same substrate. In other words, part of the circuitry required to achieve a given function can be formed on a certain substrate. Another part of the circuitry required to realize a given function is formed on a different substrate. For example, some of the circuits required to realize a given function can be Another part of the circuitry required to realize a specific function is formed on the single crystal substrate. It can be formed on a substrate (or SOI substrate) and realizes a predetermined function. The single crystal substrate (also called an IC chip) on which another part of the circuitry required for (Chip On Glass) connects to the glass substrate and Alternatively, the IC chip can be mounted on a TAB (Tape Au tomated Bonding), COF(Chip On Film), SMT(S Surface Mount Technology) or a printed circuit board. In this way, part of the circuit is formed on the same substrate as the pixel section. This reduces the number of components and reduces costs, and the number of connection points with the circuit components This reduces the number of circuits, which improves reliability. Also, circuits with high drive frequencies often consume a lot of power. Therefore, such a circuit is formed on a substrate (for example, a single crystal substrate) separate from the pixel section, and By using this IC chip, it is possible to prevent an increase in power consumption. Cut.

[0192] In the circuit MP of FIG. 9A, the first terminal of the transistor M8 is electrically connected to the line IL. The second terminal of the transistor M8 is connected to the first terminal of the capacitance element C3 and the first terminal of the transistor M3. The back gate of the transistor M1 is electrically connected to the back gate of the transistor M2. The gate of the transistor M8 is electrically connected to the wiring WL. The second terminal of the capacitor C3 is , electrically connected to the wiring VLs. The first terminal of M4 is electrically connected to the wiring VL. The second terminal of M3 The gate of the transistor M3 is electrically connected to the wiring X1L. A second terminal of the transistor M4 is electrically connected to the wiring OLB. The gate of the transistor M4 is electrically connected to the wiring X2L. As shown in the figure, the first terminal of the transistor M4 is electrically connected to another wiring VLm, not to the wiring VL. Similarly, the first terminal of the transistor M4r may be connected to the line VLr. 9A, the wiring VLmr may be electrically connected to another wiring VLmr. In the circuit diagrams of other drawings, the first terminal of the transistor M4 is connected to another terminal, not the wiring VL. and / or the first wiring VLm of the transistor M4r. The terminal is configured so that it is electrically connected to another wiring VLmr instead of wiring VLr. In addition, in FIG. 10, for example, the wiring VL and the wiring VLr may be treated as one and the same wiring. The wiring VLm and the wiring VLmr may be one and the same wiring (not shown).

[0193] In the holding unit HC shown in FIG. 9A, the second terminal of the transistor M8 and the capacitance element C the first terminal of transistor M3, the back gate of transistor M4, The electrical connection point between and is designated as node nd3.

[0194] As described in the first embodiment, the holding unit HC holds, for example, The circuit MC shown in FIG. 9A has a function of holding the potential. When the transistor M8 is turned on, the potential is input from the wiring IL. , by writing to the capacitive element C3 and then turning off the transistor M8. This allows the potential of the node nd3 to be maintained as a potential corresponding to the first data. can.

[0195] In addition, the transistor M8 holds the potential of the node nd3 for a long time, and therefore the off-state current is small. It is preferable to use a transistor that does not have a low off-state current. For example, an OS transistor can be used. A transistor having a gate is applied, and a low level potential is applied to the back gate to obtain a threshold voltage. Alternatively, the voltage may be shifted to the positive side to reduce the off-state current.

[0196] The circuit MCr has almost the same circuit configuration as the circuit MC. The circuit elements that have the same characteristics are marked with "r" to distinguish them from the circuit elements that have the same characteristics as the circuit MC. are.

[0197] The circuit MCr has a different connection configuration from the circuit MC. The second terminal of the transistor M4r is electrically connected to the wiring OLB instead of the wiring OL. The second terminal of the transistor M is electrically connected to the wiring OL, not to the wiring OLB. The first terminal of the transistor M3r and the first terminal of the transistor M4r are electrically connected to the wiring VLr. It is being done.

[0198] In the operation example described later, in order to simply explain the current flowing in and out of the circuit MP, The ends of the wiring OL shown in 9A are the nodes ina and outa, and the ends of the wiring OLB are the nodes Let node inb and node outb.

[0199] The wiring VL functions as a wiring for supplying a constant voltage, for example. is the transistor M3, the transistor M3r, the transistor M4, or the transistor When M4r is an n-channel transistor, for example, VSS , ground potential, or other low-level potential. Like the line VL, the lines VLs, VLr, and VLsr are each a power supply that supplies a constant voltage. The constant voltage functions as a voltage line, and the low level potential VSS, low level potential other than VSS, The constant voltage may be a high level potential, a ground potential, or the like. In this case, the arithmetic circuit 110, the arithmetic circuit 120, and the arithmetic circuit 13 may be set to VDD. 3A to 3E, 4A to 4E, and 4F. 4D, when applying FIG. 4F, the circuits ACTF[1] to ACTF[n] are electrically The constant voltage given by VAL connected to It is preferable to set the potential to the highest level possible, for example, VDD.

[0200] In addition, the constants supplied by the wiring VL, the wiring VLs, the wiring VLr, and the wiring VLsr are The voltages may be different from each other, or some or all of them may be the same. If the voltages supplied by the wires are the same, select those wires and treat them as the same wire. For example, each of the wiring VL, the wiring VLs, the wiring VLr, and the wiring VLsr may be When the constant voltages applied are approximately equal, as shown in the circuit MP of FIG. 11A, the wiring VLs and the wiring VLr , the wiring VLsr can be the same wiring as the wiring VL. When the constant voltages applied to the wirings VL and VLr are approximately equal, the wirings VL and VLr are connected together. Alternatively, for example, the wiring VLs and the wiring VLsr may be When the constant voltages applied by these are approximately equal, the wiring VLs and the wiring VLsr are treated as one and the same wiring. Similarly, in FIG. 10, for example, the wiring VL and the wiring VLr can be connected to one wiring. As the same wiring, the wiring VLm and the wiring VLmr may be one and the same wiring. Alternatively, for example, the wiring VL and the wiring VLmr are regarded as one and the same wiring, and the wiring VLm and the wiring V Lr may be one and the same wiring.

[0201] The configuration of the circuit MP in FIG. 9A can be changed depending on the situation. For example, 11B, the transistor M3, the transistor M3r, and the transistor M4 of the circuit MP of FIG. 9A are The transistor M4 and the transistor M4r are p-channel transistors. The transistors M3p, M3pr, M4p, and M4pr are The transistors M3p, M3pr, M4p, and M5p may be replaced. As an example of the transistor M4pr, SOI (Silicon On Insulator) In this case, a p-channel transistor with a gate electrode structure can be applied. The constant voltage applied by the wiring VL and the wiring VLr is preferably set to VDD, which is a high level potential. In addition to this case, the circuit of the arithmetic circuit 110, the arithmetic circuit 120, or the arithmetic circuit 130 may be 3A to 3E, 4A to 4D, and When FIG. 4F is applied, the circuits ACTF[1] to ACTF[n] are electrically connected. The constant voltage provided by the VAL is preferably the ground potential or VSS. Thus, when the potential of the wiring is changed, the direction of the current flow is also changed.

[0202] Similarly, transistor M8 can be replaced with a p-channel transistor. Good too.

[0203] 9A, 9B, 10, 11A, and 11B. The sizes of the transistors M3r, M4, and M4r, for example, It is preferable that the channel length L or the channel width is equal. By doing so, it is possible to achieve an efficient layout. The currents flowing through the transistors M3r, M4, and M4r are aligned. There is a possibility that this can be achieved.

[0204] <<Example of operation>> First, the operating characteristics of the transistor M3 or M4 included in the circuit MP will be described. FIG. 12A shows the transistor M3 and the transistor The gate of one of the transistors M3r, M4, and M4r 1 is a graph showing the characteristics of the drain-source voltage and the drain current in a simplified manner. The vertical axis represents the gate-source voltage Vgs of the transistor. 12A shows the current Id. The vertical axis shown in FIG. 12A is a linear scale.

[0205] In FIG. 12A, the potential applied to the gate of the transistor is Vg. The potential applied to the back gate of the transistor is Vbg. The constant potential applied to the source of the capacitor is set to 0 V, for example.

[0206] FIG. 12A shows two curves. One curve indicates the transistor Vbg is high. The gate-source voltage when the gate-source voltage is at a high level potential (shown as High in FIG. 12A). The other curve shows the characteristics of the Vgs and drain current Id of the transistor. When bg is at a low level potential (shown as Low in FIG. 12A), 12A shows the characteristics of the gate-to-gate voltage Vgs and the drain current Id. The threshold voltage Vth2 of the transistor when Vbg is at the low level potential is It can be seen that the threshold voltage Vth1 of the transistor is lower than the threshold voltage Vth1 of the transistor when the voltage is at the Vth position. That is, by varying the Vbg of the transistor, the transistor is turned on. The Vgs required to bring the device into this state (the source potential is set to 0V, so this can be translated as Vg) It is possible to change .

[0207] Here, when the Vbg of the transistor is at a high level potential, the transistor is turned on. When the transistor is in an on state and the Vbg of the transistor is at a low level potential, The Vg of the transistor is determined so that the transistor is in the off state. The Vg of the transistor is shown as Vg1. In other words, Vg1 is the voltage when Vbg is the high level potential. When Vbg is higher than the threshold voltage Vth2 of the transistor, and Vbg is a low-level potential, The potential may be set to be lower than the threshold voltage Vth1 of the transistor.

[0208] Also, when the Vbg of the transistor is at a high level potential, the transistor is turned off. When the Vbg of the transistor is at a low level potential, the transistor The Vg of the transistor is determined so that the transistor is in the off state. The Vg of the transistor is shown as Vg2. That is, Vg2 is the potential when Vbg is the high level potential. If the potential is lower than the threshold voltage Vth2 of the transistor M3 (transistor M4), good.

[0209] 9A, for example, the potential V of the gates of the transistors M3 and M3r g is given from the wiring X1L. Therefore, Vg1 and Vg2 are given from the wiring X1L. Similarly, the potential of the transistors M4 and M4r can be set to The gate potential Vg is given from the wiring X2L. Therefore, Vg1 and Vg2 are 2L. In this specification, Vg1 and Vg2 are the potentials given by These can be rephrased as high-level potential and low-level potential, respectively.

[0210] In this specification and the like, the terms "low-level potential" and "high-level potential" refer to specific potentials. This does not mean the potential, and if the wiring is different, the actual potential may be different. Therefore, transistors M3, M3r, M4, and M4r The high-level potential applied to the back gate is the same as the high-level potential applied to the wiring X1L and wiring X2L. Similarly, the transistor M3, the transistor A low level is applied to the back gates of transistors M3r, M4, and M4r. The potential is different from the low-level potential (Vg2) applied to the wiring X1L and the wiring X2L. For example, the transistor M3, the transistor M3r, the transistor M4, and The high-level potential applied to the back gate of the transistor M4r is applied to the transistors M3, M4r, The source potentials of the transistors M3r, M4, and M4r are the same. For example, the transistor M3, the transistor M3r, the transistor M4, and The low-level potential applied to the back gates of the transistors M3 and M4r is Lower than the source potential of the transistor M3r, the transistor M4, and the transistor M4r Therefore, for example, the transistor M3, the transistor M3r, the transistor M4, When the source potential of the transistor M4 and the transistor M4r is 0V, the transistor M3 , applied to the back gates of the transistors M3r, M4, and M4r. The low level potential applied is a negative potential, for example, -11V or more and -2V or less, More preferably, it may be about −3V.

[0211] In the operation example described below, the potential (Vg1 or Vg2), transistor M3, transistor M3r, transistor M4, and transistor The back gate potential of transistor M4r is explained as a binary (digital) value. One embodiment of the present invention is not limited to this. For example, as shown in FIG. 12B, When the gate is Vga1, the potential of the back gate of the transistor is Vbg1, Vbg By varying Vbg3 to either Vbg2 or Vbg3, the drain current Id Here, let us consider the case of the circuit MP shown in Fig. 9A and Fig. 11. The gates of transistors M3, M3r, M4, and M4r The potential is kept constant, and the transistors M3, M3r, M4, and The potential of the back gate of the transistor M4r is changed to 3r, transistor M4, and transistor M4r by changing the drain current Id. This allows the amount of current flowing through the wiring OL and wiring OLB to be increased or decreased. The back gates of transistors M3, M3r, M4, and M4r By varying the potential of the gate as an analog value, the circuit MP uses an analog value. Calculations can be performed.

[0212] Also, for example, as shown in FIG. 12B, the potential of the back gate of the transistor is Vbg1 , Vbg2, or Vbg3, the potential of the gate of the transistor is By varying Vga1, Vga2, or Vga3, the transistor The drain current Id of the capacitor can be increased or decreased. Consider the case of the circuit MP shown in FIGS. 9A and 11. When the transistor M3, the transistor M3r, the transistor M4, and the transistor The potential of the back gate of M4r is kept constant, and the transistors M3, M3r, and The potentials of the gates of the transistors M4 and M4r are changed to , the drain current Id of the transistor M3r, the transistor M4, and the transistor M4r By changing this, the amount of current flowing through the wiring OL and wiring OLB can be increased or decreased. That is, transistor M3, transistor M3r, transistor M4, and transistor M By varying the potential of the gate of 4r as an analog value, the circuit MP In addition, the transistor M3, the transistor M3r, and the transistor M4 can be used to perform calculations. The potentials of the gate and back gate of the transistor M4 and the transistor M4r are kept constant, The potential of the source electrode is changed as an analog value to turn on the transistors M3 and M3r. The drain current Id of the transistor M4 and the transistor M4r is changed. This may be done (not shown).

[0213] Next, an example of the operation of the circuit MP shown in FIG. 9A will be described. 14A to 14C and 15A to 15C are timing charts showing examples of the operation of the circuit MP. These are the wiring IL, wiring ILB, wiring WL, wiring X1L, wiring X2L, 13A to 13C show the fluctuations in the potentials of the nodes nd3 and nd3r. 14A to 14C and 15A to 15C, "high" indicates a high level potential. In this example, the line OL is connected to the node The amount of current output to node outa (or from node outa to wiring OL) is I OL and Also, from wiring OLB to node outb (or from node outb to wiring O The amount of current output to LB is I OLB 13A to 13C and 14A to 14C. In the timing charts shown in FIGS. 14C and 15A to 15C, the amount of current I OL , I OL B The change in the

[0214] In this operation example, the constant voltages applied by the wiring VL, wiring VLs, wiring VLr, and wiring VLsr In this case, the voltage is VSS (low level potential). Similarly, current flows from the wiring VAL through the wiring OLB. A current flows through VLr.

[0215] Before explaining the operation example, the weighting coefficients held by the circuit MP are defined as follows: A high level potential is held at the node nd3 of C, and a low level potential is held at the node nd3r of the holding unit HCr. When this is done, the circuit MP holds a weighting factor of "+1". A low level potential is held at the node nd3 of the HC, and a high level potential is held at the node nd3r of the holding unit HCr. When the weighting coefficient is held, the circuit MP is assumed to hold "-1". A low level potential is applied to the node nd3 of the holding unit HC, and a low level potential is applied to the node nd3r of the holding unit HCr. When this is held, the circuit MP holds "0" as the weighting coefficient. , the node nd3, and the node nd3r are held at high level potentials, for example, VD D, or a potential slightly lower than VDD, and nodes nd3 and nd4 The low level potential held in the node nd3r can be, for example, VSS. Alternatively, for example, the high level potential held at the node nd3 and the node nd3r may be V SS, and the low level potential held at the node nd3 and the node nd3r. For example, it can be set to a potential lower than VSS, for example, a negative potential. It is also possible to use analog values ​​for the weighting coefficients. In that case, for example, In the case of "analog value", a high level analog potential is applied to the node nd3 of the holding unit HC, and A low level potential is maintained at the node nd3r of HCr. In the case of the "log value", for example, a low level potential is applied to the node nd3 of the holding unit HC, and a low level potential is applied to the node nd4 of the holding unit HCr. A high level analog potential is held at node nd3r. When the weighting coefficient is "0", In this case, for example, the node nd3 of the holding unit HC is at a low level potential, and the node nd A low level potential is maintained at 3r.

[0216] In addition, the neuron signal (operation value) input to the circuit MP is defined as follows as an example: A high-level potential (Vg1) is applied to the wiring X1L, and a low-level potential (Vg2) is applied to the wiring X2L. When this signal is added, a neuron signal of "+1" is input to the circuit MP. A low-level potential (Vg2) is applied to the wiring X1L, and a high-level potential (Vg1) is applied to the wiring X2L. When this happens, the circuit MP receives a neuron signal of "-1." A low-level potential (Vg2) is applied to 1L, and a low-level potential (Vg2) is applied to wiring X2L. When this happens, the circuit MP receives a signal of "0" as the neuron signal. For example, the high level potential (Vg1) is VDD or 10% or more higher than VDD. or take a potential 20% or higher.

[0217] In this operation example, as an example, the transistor M3 included in the circuit MP The transistors M3r, M4, and M4r are the same as those in FIG. 12A. As shown in the figure, a high-level potential is applied to the back gate, shifting the threshold voltage to the negative side. When the transistor is turned on, a high-level potential (Vg1) is applied to the gate. In addition, the transistor M3, the transistor M3r, the transistor M4, and As explained in FIG. 12A, each of the transistors M4r and M4r has a low-level voltage applied to its back gate. When a potential is applied to the gate, the threshold voltage is shifted to the positive side. (Vg1) is applied to the transistor, which is turned off. M3, transistor M3r, transistor M4, and transistor M4r are As explained in Figure 12A, a high level potential is applied to the back gate, and the threshold voltage is Even if the gate is shifted to the negative side, a low-level potential (Vg2) is applied to the gate. In this case, the transistor M3 and the transistor M3r, transistor M4, and transistor M4r are as described in FIG. 12A. A low level potential is applied to the back gate, and the threshold voltage is shifted to the positive side. Even if the transistor is in the off state, a low-level potential (Vg2) is applied to the gate. It shall be as follows.

[0218] That is, in this operation example, as an example, unless otherwise specified, transistors M3, M4, and M5 are used. Each of the transistors M3r, M4, and M4r is a back gate. A high level potential is applied to the gate and a high level potential is applied to the on A low level potential is applied to at least one of the gate and back gate. The transistor M3 and the transistor The operations of M3r, transistor M4, and transistor M4r are merely examples and are not intended to be limiting of the present invention. The type is not limited to this. For example, the transistor M3, the transistor M3r, the transistor The transistors M4 and M4r are connected to the gate and back gate of the transistors M4 and M4r. A voltage regulator that generates an analog current according to a voltage (analog voltage or multi-value digital voltage). It may also function as a flow source.

[0219] In this specification and the like, the transistor M3, the transistor M3r, the transistor Unless otherwise specified, M4 and transistor M4r will eventually saturate when in the on state. This includes the case where the transistors operate in the sum region. The gate voltage, source voltage, and drain voltage are appropriate for the voltage range in which the device operates in the saturation region. However, one aspect of the present invention is not limited to this. In order to reduce the amplitude of the supplied voltage, transistor M3 and transistor M3r, transistor M4, and transistor M4r may operate in the linear region. In addition, when the weighting coefficient is an analog value, the value of the transceiver is changed depending on the magnitude of the weighting coefficient. Transistor M3, transistor M3r, transistor M4, and transistor M4r are linear The operation may be in the low-pass region and the saturation region at the same time.

[0220] In this specification and the like, the transistor M8 and the transistor M8r are not particularly limited. When there is no change, the on-state includes the case where the device ultimately operates in the linear region. That is, the gate voltage, source voltage, and drain voltage of each of the above-mentioned transistors This includes when the voltage is properly biased to a voltage within the range in which the device operates in the linear region. do.

[0221] Below, for each combination of the weighting coefficients and the neuron's signals, An example of the operation of the circuit MP will now be described.

[0222] [Condition 1] First, as an example, the weight coefficient w is "0" and the neuron input to the circuit MP is Consider the case where the signal (calculated value) of the circuit M is "+1". 1 is a timing chart of P.

[0223] Between time T1 and time T2, the wiring IL and the wiring ILB each have a holding The potential of the node nd3 of the holding unit HC and the potential of the node nd3r of the holding unit HCr are used to initialize the Initialization potential V ini In FIG. 13A, V ini is a low level potential Although the potential is shown as higher than the high-level potential and lower than the high-level potential, V ini is a low level potential Alternatively, the potential may be set to a potential lower than the high-level potential or a potential higher than the high-level potential. i ni may be set to the same potential as the low level potential or the same potential as the high level potential. In addition, the initialization potential V given to each of the wiring IL and the wiring ILB ini are different from each other Note that the wirings IL and ILB may be supplied with an initialization potential V ini of In other words, there is no need to set a period between time T1 and time T2. .

[0224] In addition, a low level potential is input to the wiring WL between time T1 and time T2. Therefore, the transistor M8 and the transistor M8r are both in an off state. It is.

[0225] In addition, between time T1 and time T2, The potentials of the nodes nd3 and nd The potential of each of the 3r is higher than the low-level potential, V ini The potential is lower than .

[0226] A low-level potential (Vg2) is input to the wiring X1L and the wiring X2L. The transistors M3, M4, M3r, and The threshold voltage of M4r is determined according to the potential of each back gate. , transistor M3, transistor M4, transistor M3r, and transistor M4r may assume an ON state rather than an OFF state.

[0227] Next, between time T2 and time T3, a high-level potential is input to the wiring WL. As a result, the transistors M8 and M8r are turned on. , the line IL and the node nd3 are in a conductive state, and the line ILB and the node nd3r are in a conductive state. Therefore, the potentials of the nodes nd3 and nd3r are V ini This becomes:

[0228] At this time, the transistors M3, M4, M3r, and Each back gate of StaM4r has a V ini is input to the transistor M3, Each of the transistors M4, M3r, and M4r is a back V at the gate ini When this signal is input, the device will be in a normally-off state. Therefore, the transistor M3, the transistor M4, the transistor M3r, and the transistor M4r are turned off. The potentials of the nodes nd3 and nd3r are , initialization potential V ini In other words, the period from time T2 to time T3 may be It does not have to be provided.

[0229] Between time T3 and time T4, the wiring IL and the wiring ILB are at a low level. A potential is applied to the wiring WL, and "0" is input as the weighting coefficient w. Since a high-level potential continues to be input from transistor M8 and transistor M8r is in the ON state. Therefore, "0" is input as the weighting coefficient w, and the node The potentials of the node nd3 and the node nd3r are both at low level potential.

[0230] Between time T4 and time T5, a low level potential is input to the wiring WL. As a result, the transistors M8 and M8r are turned off, and the capacitance element The potentials of the nodes nd3 and nd3r are maintained by the capacitor C3 and the capacitor C3r. It will be held.

[0231] The operation from time T1 to time T5 sets the weighting coefficient of the circuit MP to "0". can be.

[0232] Through the operations up to this point, transistors M3, M4, and M3r , and the back gates of the transistors M4r and M4r are at low level potentials. The transistors M3, M4, M3r, and M4r Each threshold voltage is higher on the positive side than the threshold voltage from time T2 to time T3. Also, the transistors M3, M4, M3r, and The potential of the first terminal of each of the transistors M4r is 0V, and the potential of each of the gates is at a low level potential (Vg2), so transistors M3, M4, and The transistors M3r and M4r are both turned off.

[0233] Between time T5 and time T6, for example, the wiring IL and the wiring ILB are initialized. Potential V ini is input. Note that this operation is not particularly necessary, so wiring I L and wiring ILB are initialized to a potential V ini In other words, from time T5 The period up to time T6 does not need to be set. may input different potentials.

[0234] After time T6, the neuron signal (operation value) “+1” is input to the circuit MP. A high-level potential (Vg1) is input to the wire X1L, and a low-level potential (Vg2) is input to the wire X2L. At this time, a high level potential is applied to the gates of the transistors M3 and M3r. (Vg1) is input, and a low level is applied to the gates of the transistors M4 and M4r. A potential (Vg2) is input to the transistor M3, the transistor M3r, and the transistor M A low-level potential is input to the back gates of transistors M4 and M4r. Therefore, the transistor M3, the transistor M3r, the transistor M4, and the transistor In other words, this operation turns off the circuit MC and the wiring OL. and between the circuit MC and the wiring OLB, and and between the circuit MCr and the wiring OLB.

[0235] Therefore, in the circuit MC, a current flows between the wiring OL and the wiring OLB and the wiring VL. does not flow. In other words, the current I output from the node outa of the wiring OL OL , and wiring O The current I output from node outb of LB OLB does not change before and after time T6. Similarly, in the circuit MCr, the current flows from the wiring OL and wiring OLB to the wiring VLr. In other words, the current I output from node outa of wiring OL OL , and wiring OL The current I output from node outb of B OLB does not change before and after time T6.

[0236] By the way, this condition is that the weight coefficient is "0" and the neuron signal input to the circuit MP is Since it is set to "+1", when using equation (1.1), the product of the weight coefficient and the neuron signal is , "0". The result of the product of the weight coefficient and the neuron signal being "0" is that the behavior of the circuit MP In this operation, the current I OL and current I OLB If each of these does not change Corresponds to.

[0237] Once the weighting coefficient w is input, it is possible to change only the calculated value without updating the value. In this case, it is not necessary to update the weight coefficient w. Therefore, power consumption can be reduced. In this case, for example, the OS transistor is By using this, it is possible to maintain the weighting factor w for a long period of time by taking advantage of the low off-state current. do.

[0238] [Condition 2] Next, as an example, the weight coefficient w is "+1" and the neuron input to the circuit MP is Consider the case where the signal (calculated value) of the circuit M is "+1". 1 is a timing chart of P.

[0239] Regarding the behavior from time T1 to time T3, the behavior from time T1 to time T3 under condition 1 Since the operation is the same as that in Condition 1, the explanation of the operation from time T1 to time T3 will be taken into consideration.

[0240] Between time T3 and time T4, a high level potential is applied to the wiring IL and a low level potential is applied to the wiring ILB. A bell potential is applied, and a weighting coefficient w is set to "1." Since a high level potential continues to be input from before, transistor M8 and transistor Therefore, "1" is input as the weighting coefficient w, and the The potential of the node nd3 becomes a high level potential, and the potential of the node nd3r becomes a low level potential.

[0241] Between time T4 and time T5, a low level potential is input to the wiring WL. As a result, the transistors M8 and M8r are turned off, and The capacitance elements C3 and C3r respectively connect the nodes nd3 and nd3r. The respective potentials are maintained.

[0242] The operation from time T1 to time T5 sets the weighting coefficient of circuit MP to "+1". will be done.

[0243] By the operations up to this point, the buffers of the transistors M3 and M4 are The potential of the gate of transistor M3r is at a high level, and the potential of transistor M4r is at a high level. The back gates of the transistors M3 and M4 are at a low level. The threshold voltage of each of the transistors M4 is lower than the threshold voltage from time T2 to time T3. , shifts to the negative side, and the threshold voltages of the transistors M3r and M4r The threshold voltage is shifted to the positive side from time T2 to time T3. Also, transistor M3, transistor M4, transistor M3r, and transistor M4 The potential of each first terminal of r is 0V, and the potential of each gate is low level potential. (Vg2), the transistors M3, M4, M3r, and and transistor M4r are both in the off state.

[0244] Regarding the operation from time T5 to time T6, the operation from time T5 to time T6 under condition 1 is Since the operation is the same as that in Condition 1, the explanation of the operation from time T5 to time T6 will be taken into consideration.

[0245] After time T6, the neuron signal (operation value) “+1” is input to the circuit MP. A high-level potential (Vg1) is input to the wire X1L, and a low-level potential (Vg2) is input to the wire X2L. At this time, a high-level potential (Vg1) is input to the gates of the transistors M3 and M3r. A low level potential (Vg2) is applied to the gates of the transistors M4 and M4r. The back gates of the transistors M3 and M4 are supplied with high A level potential is input, and the buffers of the transistors M3r and M4r are Since a low-level potential is input to the input gate, transistor M3 is in the on state, and transistor The transistor M3r, the transistor M4, and the transistor M4r are turned off. This operation brings the circuit MC and the wiring OL into a conductive state, and the circuit MC and the wiring OLB and the circuit MCr and the wiring OL are in a non-conductive state, and the circuit MC There is no conduction between r and the wiring OLB.

[0246] At this time, in the circuit MC, the transistor M3 is in the on state, so that the wiring O A current flows from L to the wiring VL. In other words, the current is output from the node outa of the wiring OL. The current I OL increases after time T6 (in FIG. 13B, the current I OL The increase in On the other hand, in the circuit MC, the transistor M4 is in the off state. Therefore, no current flows between the wiring OLB and the wiring VL. Since the transistor M3r is in the off state, In the circuit MCr, the transistor M4r is in the off state. Therefore, no current flows between the wiring OL and the wiring VLr. The current I output from node outb of B OLB does not change before and after time T6.

[0247] By the way, this condition is that the weight coefficient w is "+1" and the neuron input to the circuit MP is Since the signal (calculated value) is "+1", when using equation (1.1), the weighting coefficient and the neuro The product of the weight coefficient and the neuron signal is "+1". In the operation of the circuit MP, the current I OL changes, and the current I OLB is strange This corresponds to the case where the conversion is not performed.

[0248] [Condition 3] Next, as an example, the weight coefficient w is "-1" and the neuron input to the circuit MP is Consider the case where the signal (calculated value) of the circuit M is "+1". 1 is a timing chart of P.

[0249] Regarding the behavior from time T1 to time T3, the behavior from time T1 to time T3 under condition 1 Since the operation is the same as that in Condition 1, the explanation of the operation from time T1 to time T3 will be taken into consideration.

[0250] Between time T3 and time T4, the wiring IL is at a low level potential and the wiring ILB is at a high level potential. A bell potential is applied, and "-1" is input as the weighting coefficient w. Since a high level potential has been input from before, the transistor M8 and the The register M8r is in the ON state. Therefore, "-1" is input as the weighting coefficient w. The potential of the node nd3 becomes low level potential, and the potential of the node nd3r becomes high level potential. do.

[0251] Between time T4 and time T5, a low level potential is input to the wiring WL. As a result, the transistors M8 and M8r are turned off, and The capacitance element C3 and the capacitance element C3r are connected to the nodes nd3 and nd3r, respectively. The potential of each of the electrodes r is maintained.

[0252] The operation from time T1 to time T5 sets the weighting coefficient of circuit MP to "-1". will be done.

[0253] By the operations up to this point, the buffers of the transistors M3 and M4 are The potential of the gate of transistor M3r is at a low level, and the potential of transistor M4r is at a low level. The back gates of the transistors M3 and M4 are at a high level. The threshold voltage of each of the transistors M4 is higher than the threshold voltage from time T2 to time T3. The voltages of the transistors M3r and M4r are shifted to the positive side. The threshold voltage shifts to the positive side compared to the threshold voltage from time T2 to time T3. In addition, the transistor M3, the transistor M4, the transistor M3r, and the transistor The potential of the first terminal of each of the transistors M4r is 0V, and the potential of each gate is low. Since the transistor M3, transistor M4, and transistor M3 r and transistor M4r are each assumed to be in an off state.

[0254] Regarding the operation from time T5 to time T6, the operation from time T5 to time T6 under condition 1 is Since the operation is the same as that in Condition 1, the explanation of the operation from time T5 to time T6 will be taken into consideration.

[0255] After time T6, the neuron signal (operation value) “+1” is input to the circuit MP. A high-level potential (Vg1) is input to the wire X1L, and a low-level potential (Vg2) is input to the wire X2L. When this is done, a high-level potential (Vg 1) is input, and a low-level potential ( Vg2) is input to the back gates of the transistors M3 and M4. A low level potential is input to the output of the transistor M3r and that of the transistor M4r. Since a high-level potential is input to each back gate, the transistor M3r is turned on. In this state, the transistors M3, M4, and M4r are turned off. In other words, this operation causes a non-conductive state between the circuit MC and the wiring OL, and the circuit MC There is no conduction between the circuit MCr and the wiring OLB, and there is no conduction between the circuit MCr and the wiring OL. As a result, the circuit MCr and the wiring OLB are brought into a conductive state.

[0256] At this time, in the circuit MCr, the transistor M3r is in the on state, so the A current flows from the line OLB to the wiring VLr. That is, the node outb of the wiring OLB The current I output from OLB increases after time T6 (in FIG. 13C, the current I O LB The increase in current is denoted as ΔI.) On the other hand, in the circuit MC, the transistor M3 Since it is in the off state, no current flows between the wiring OL and the wiring VL. In the circuit MC, the transistor M4 is in the off state, so the line V No current flows between L and L. In addition, in the circuit MCr, the transistor M4r is in the off state. Therefore, no current flows between the wiring OL and the wiring VLr. The current I output from node outa of line OL OL does not change before and after time T6.

[0257] By the way, this condition is that the weight coefficient w is "-1" and the neuron input to the circuit MP is Since the signal (calculated value) is "+1", when using equation (1.1), the weighting coefficient and the neuro The product of the weight coefficient and the neuron signal is "-1". As a result, in the operation of the circuit MP, the current I OL does not change, and the current I OLB This corresponds to the case where changes.

[0258] [Condition 4] In this condition, for example, the weight coefficient w is set to "0", and the neuron input to the circuit MP is Consider the operation of the circuit MP when the signal (calculated value) is set to "-1." 10 is a timing chart of the circuit MP in this case.

[0259] Regarding the operation from time T1 to time T6, the operation from time T1 to time T6 under condition 1 is Since the operation is the same as that of the first condition, the explanation of the operation from time T1 to time T6 in the first condition will be taken into consideration.

[0260] After time T6, the neuron signal (calculated value) “-1” is input to the circuit MP. A low-level potential (Vg2) is input to the wire X1L, and a high-level potential (Vg1) is input to the wire X2L. At this time, a low level potential is applied to the gates of the transistors M3 and M3r. (Vg2) is input, and a high level is applied to the gates of the transistors M4 and M4r. A potential (Vg1) is input to the transistor M3, the transistor M3r, and the transistor M A low-level potential is input to the back gates of transistors M4 and M4r. Therefore, the transistor M3, the transistor M3r, the transistor M4, and the transistor In other words, this operation turns off the circuit MC and the wiring OL. and between the circuit MC and the wiring OLB, and and between the circuit MCr and the wiring OLB.

[0261] Therefore, in the circuit MC, a current flows between the wiring OL and the wiring OLB and the wiring VL. does not flow. In other words, the current I output from the node outa of the wiring OL OL , and wiring O The current I output from node outb of LB OLB does not change before and after time T6. Similarly, in the circuit MCr, the current flows from the wiring OL and wiring OLB to the wiring VLr. In other words, the current I output from node outa of wiring OL OL , and wiring OL The current I output from node outb of B OLB does not change before and after time T6.

[0262] By the way, this condition is that the weight coefficient w is "0" and the signal of the neuron input to the circuit MP is Since the calculation value is "-1", when using equation (1.1), the weight coefficient and neuron The product of the signals is "0". When the product of the weight coefficient and the neuron signal is "0", the result is In the operation of the circuit MP, from time T6 onwards, the current I OL and current I OLB Each of them is strange This corresponds to the case where no conversion is performed, and is consistent with the circuit operation results for condition 1.

[0263] [Condition 5] In this condition, for example, the weight coefficient w is set to "+1", and the neuron input to the circuit MP is Consider the operation of the circuit MP when the signal (operation value) of the input is set to "-1". 10 is a timing chart of the circuit MP in the case where

[0264] Regarding the behavior from time T1 to time T6, the behavior from time T1 to time T6 under condition 2 Since the operation is the same as that in Condition 2, the explanation of the operation from time T1 to time T6 will be taken into consideration.

[0265] After time T6, the neuron signal (calculated value) “-1” is input to the circuit MP. A low-level potential (Vg2) is input to the wire X1L, and a high-level potential (Vg1) is input to the wire X2L. At this time, a low level potential is applied to the gates of the transistors M3 and M3r. (Vg2) is input, and a high level is applied to the gates of the transistors M4 and M4r. A potential (Vg1) is input to the transistors M3 and M4. A high-level potential is input to the clock gate of the transistor M3r and the transistor M4r. Since a low level potential is input to the back gates of the transistors M4 and M5, On state, transistor M3, transistor M3r, and transistor M4r are off state In other words, this operation causes a non-conductive state between the circuit MC and the wiring OL, The circuit MC and the wiring OLB are in a conductive state, and the circuit MCr and the wiring OL are in a non-conductive state. This results in a non-conductive state between the circuit MCr and the wiring OLB.

[0266] At this time, in the circuit MC, the transistor M4 is in the on state, so that the wiring O Current flows from LB to the wiring VL. In other words, the current flows from the node outb of the wiring OLB. Input current I OLB increases after time T6 (in FIG. 14B, the current I OLB of The increase is denoted as ΔI.) Meanwhile, in the circuit MC, when the transistor M3 is in the off state, Since the circuit is in the ON state, no current flows between the wiring OL and the wiring VL. At r, the transistor M3r is in the off state, so the line OLB to the line VL In the circuit MCr, the transistor M4r is in the off state. Therefore, no current flows between the wiring OL and the wiring VLr. The current I output from node outa of line OL OL does not change before and after time T6.

[0267] By the way, this condition is that the weight coefficient w is "+1" and the neuron input to the circuit MP is Since the signal (calculated value) is "-1", when using equation (1.1), the weighting coefficient and the neuro The product of the weight coefficient and the neuron signal is "-1". As a result, in the operation of the circuit MP, the current I OL does not change, and the current I OLB This corresponds to the case where changes, which is consistent with the circuit operation result for condition 3.

[0268] [Condition 6] In this condition, for example, the weighting coefficient w is set to "-1", and the neuron input to the circuit MP is Consider the operation of the circuit MP when the signal (operation value) of the input is set to "-1". 10 is a timing chart of the circuit MP in the case where

[0269] Regarding the behavior from time T1 to time T6, the behavior from time T1 to time T6 under condition 3 Since the operation is the same as that of the condition 3, the explanation of the operation from time T1 to time T6 will be taken into consideration.

[0270] After time T6, the neuron signal (calculated value) “-1” is input to the circuit MP. A low-level potential (Vg2) is input to the wire X1L, and a high-level potential (Vg1) is input to the wire X2L. At this time, a low level potential is applied to the gates of the transistors M3 and M3r. (Vg2) is input, and a high level is applied to the gates of the transistors M4 and M4r. A potential (Vg1) is input to the transistors M3 and M4. A low level potential is input to the clock gate of the transistor M3r and the transistor M4r. Since a high-level potential is input to the back gate of each of the transistors M4r is in an on state, and the transistor M3, the transistor M3r, and the transistor M4 are in an off state. In other words, this operation causes a non-conductive state between the circuit MC and the wiring OL, The circuit MC and the wiring OLB are in a non-conductive state, and the circuit MCr and the wiring OL are in a conductive state. This results in a non-conductive state between the circuit MCr and the wiring OLB.

[0271] At this time, in the circuit MCr, the transistor M4r is in the on state, so that the Current flows from the line OL to the wiring VLr. That is, from the node outa of the wiring OL Output current I OL increases after time T6 (in FIG. 14C, the current I OLB of The increase is denoted as ΔI.) Meanwhile, in the circuit MC, when the transistor M3 is in the off state, Since the circuit is in the ON state, no current flows between the wiring OL and the wiring VL. At r, the transistor M3r is in the off state, so the line OLB to the line VL In the circuit MCr, the transistor M4r is in the off state. Therefore, no current flows between the wiring OL and the wiring VLr. The current I output from node outb of line OLB OLB does not change before and after time T6 .

[0272] By the way, this condition is that the weight coefficient w is "-1" and the neuron input to the circuit MP is Since the signal (calculated value) is "-1", when using equation (1.1), the weighting coefficient and the neuro The product of the weight coefficient and the neuron signal is "+1". As a result, in the operation of the circuit MP, the current I OL changes, and the current I OLB but This corresponds to the case where there is no change, which is consistent with the result of the circuit operation under condition 2.

[0273] [Condition 7] In this condition, for example, the weighting coefficient w is "0" and the new Let us consider the operation of the circuit MP under condition 7, where the signal (calculated value) of the RON is "0". 15A is a timing chart of the circuit MP in this case.

[0274] Regarding the operation from time T1 to time T6, the operation from time T1 to time T6 under condition 1 is Since the operation is the same as that of the first condition, the explanation of the operation from time T1 to time T6 in the first condition will be taken into consideration.

[0275] After time T6, as the input of the neuron signal (operation value) “0” to the circuit MP, A low-level potential (Vg2) is input to the wiring X1L, and a low-level potential (Vg2) is input to the wiring X2L. At this time, a low level potential ( Vg2) is input, and a low level voltage is applied to the gates of the transistors M4 and M4r. That is, the transistor M3, the transistor M3r, the transistor Regardless of the potential of the back gates of the transistors M4 and M4r, the transistor M3 , the transistor M3r, the transistor M4, and the transistor M4r are in the off state. In other words, this operation causes a B, between the circuit MCr and wiring OL, and between the circuit MCr and wiring OLB. This is the state.

[0276] Therefore, in the circuit MC, between the wiring OL and either the wiring VL or the wiring VLr, No current flows. In other words, the current I output from node outb of wiring OLB OLB teeth, There is no change before and after time T6. Similarly, in the circuit MCr, In other words, no current flows from node outa of wiring OL to the other end of wiring VLr. The current I OL does not change before and after time T6.

[0277] By the way, this condition is that the weight coefficient w is "0" and the signal of the neuron input to the circuit MP is Since the signal (calculated value) is "0", when using equation (1.1), the weight coefficient and the neuron The product of the signal is "0". The result of the product of the weight coefficient and the neuron signal being "0" is In the operation of the MP, the current I OL and current I OLB Each of these changes This corresponds to the case where no such condition is applied, and is consistent with the results of the circuit operation under conditions 1 and 4.

[0278] [Condition 8] In this condition, for example, the weighting coefficient w is "+1" and the input to the circuit MP is The operation of the circuit MP is considered under the condition 8 where the signal (calculated value) of the LO is "0". FIG. 15B is a timing chart of the circuit MP in this case.

[0279] Regarding the behavior from time T1 to time T6, the behavior from time T1 to time T6 under condition 2 Since the operation is the same as that in Condition 2, the explanation of the operation from time T1 to time T6 will be taken into consideration.

[0280] After time T6, as the input of the neuron signal (operation value) “0” to the circuit MP, A low-level potential (Vg2) is input to the wiring X1L, and a low-level potential (Vg2) is input to the wiring X2L. That is, the transistor M3, the transistor M3r, the transistor M4, and the transistor Regardless of the potential of the back gate of transistor M4r, transistor M3 and transistor M3r , transistor M4, and transistor M4r are turned off. Therefore, there is no conduction between the circuit MC and the wiring OL, and between the circuit MC and the wiring OLB. As a result, there is no conduction between the circuit MCr and the wiring OL, and between the circuit MCr and the wiring OLB. Therefore, when the line OL or the line OLB is connected to either the line VL or the line VLr, Since no current flows between these two points, the current I output from node outa of wiring OL OL , and the current I output from node outb of wiring OLB OLB Each of the There is no change before and after.

[0281] By the way, this condition is that the weight coefficient w is "+1" and the neuron input to the circuit MP is Since the signal (calculated value) is set to "0", when using equation (1.1), the weight coefficient and neuron The product of the signals is "0". When the product of the weight coefficient and the neuron signal is "0", the result is In the operation of the circuit MP, from time T6 onwards, the current I OL and current I OLB Each of them is strange This corresponds to the case where the circuit is not initialized, which is consistent with the results of the circuit operation under conditions 1, 4, and 7. .

[0282] [Condition 9] In this condition, for example, the weighting coefficient w is "-1", and the number of inputs to the circuit MP is Consider the operation of the circuit MP under the condition 9 where the signal (calculated value) of the RON is "0". 15C is a timing chart of the circuit MP in this case.

[0283] Regarding the behavior from time T1 to time T6, the behavior from time T1 to time T6 under condition 3 Since the operation is the same as that of the condition 3, the explanation of the operation from time T1 to time T6 will be taken into consideration.

[0284] After time T6, as the input of the neuron signal (operation value) “0” to the circuit MP, A low-level potential (Vg2) is input to the wiring X1L, and a low-level potential (Vg2) is input to the wiring X2L. That is, the transistor M3, the transistor M3r, the transistor M4, and the transistor Regardless of the potential of the back gate of transistor M4r, transistor M3 and transistor M3r , transistor M4, and transistor M4r are each turned off. Therefore, the circuit MC is in a non-conductive state between the wiring OL and the wiring OLB. Therefore, the circuit MCr is in a non-conductive state between both the wiring OL and the wiring OLB. Therefore, from the wiring OL or wiring OLB to either the wiring VL or wiring VLr Since current flows between these two points, the current I output from node outa of wiring OL OL , and The current I output from node outb of wiring OLB OLB Each of these is before and after time T6. does not change.

[0285] By the way, this condition is that the weight coefficient w is "-1" and the neuron input to the circuit MP is Since the signal (calculated value) is set to "0", when using equation (1.1), the weight coefficient and neuron The product of the signals is "0". When the product of the weight coefficient and the neuron signal is "0", the result is In the operation of the circuit MP, from time T6 onwards, the current I OL and current I OLB Each of them is strange This corresponds to the case where no optimization is performed, and is the result of the circuit operation under conditions 1, 4, 7, and 8. Matches.

[0286] The results of the operation example under the above conditions 1 to 9 are summarized in the table below. The high level potential is described as high, and the low level potential is described as low.

[0287] [Table 2]

[0288] Here, one circuit MC and one circuit MCr are connected to the wiring OL and the wiring OLB, respectively. This is an example of a case where the As shown in the figure, multiple circuits MC and multiple circuits MCr are connected to the wiring OL and wiring OLB. In this case, the current output from each circuit MC and circuit MCr is also in accordance with Kirchhoff's current law. As a result, the sum is calculated. In the circuits MC and MCr, multiplication is performed, and multiple circuits MC and MCr are used. The sum of these currents is calculated. As a result, the sum of products calculation is performed. This will be the case.

[0289] By the way, in the operation of the circuit MP, the weighting coefficients are limited to two values, "+1" and "-1", By calculating neuron signals with only two values, "+1" and "-1", the circuit MP It can perform the same operation as an exclusive OR negation circuit (match circuit).

[0290] In addition, in the operation of the circuit MP, the weighting coefficient is limited to two values, "+1" and "0", and the By performing calculations with only two values ​​for the Ron signal, "+1" and "0", the circuit MP can It can perform the same operation as the circuit.

[0291] In this operation example, the circuit MC of the circuit MP, the holding unit HC of the circuit MCr, and The potential held in the holding part HCr was set to a high level potential or a low level potential. The HC and the holding unit HCr may hold a potential indicating an analog value. For example, the weighting coefficient In the case of a "positive analog value", a high-level analog signal is output to node nd3 of the holding unit HC. A low level potential is held at the node nd3r of the potential holding unit HCr. In the case of a "negative analog value," for example, a low level potential is applied to the node nd3 of the holding unit HC, A high level analog potential is held at the node nd3r of the holding unit HCr. I OL and current I OLB The magnitude of the current is determined by the analog potential. The holding units HC and HCr hold potentials that indicate analog values, as shown in the circuit of FIG. 9A. This is not limited to the example of the operation of the MP, and may also be performed on other circuits MP shown in this specification and the like.

[0292] <Configuration example 2> Next, an example of a circuit configuration that can be applied to the circuit MP shown in FIGS. 5C and 5D will be described. .

[0293] The circuit MP shown in FIG. 16A shows a configuration example of the circuit MP of FIG. 5C, and is the same as the circuit M of FIG. 9A. The difference from P is that the wiring IL and wiring ILB are combined into one, and the wiring WL in Figure 9A is The point is that it has wiring W1L and wiring W2L.

[0294] In the circuit MP of FIG. 16A, the first terminal of the transistor M8 and the transistor M8r , and the wiring IL. In addition, the gate of the transistor M8 is electrically connected to the wiring W1L. The gate of the transistor M8r is electrically connected to the wiring W2L. Note that the circuit MP in FIG. 16A and the circuit MP in FIG. 9A have the same connection configuration. The explanation of this will be omitted.

[0295] When setting weighting coefficients for the circuit MP of FIG. 16A, first, By changing the potential supplied to the transistor M8, the transistor M8r is turned on and the transistor M8r is turned off. Then, a potential for holding is supplied from the wiring IL to the holding section HC, and the transistor Then, the potentials supplied to the wirings W1L and W2L are changed. This turns off the transistor M8 and turns on the transistor M8r. A potential for holding is supplied from the line IL to the holding unit HCr, and the transistor M8r is turned off. In this way, in the case of the circuit MP of FIG. 16A, the wiring IL is connected to the holding unit HC, the holding unit HC By sequentially supplying potentials to the holding units HC and HCr, the weighting coefficients corresponding to the weighting coefficients are applied to the holding units HC and HCr. The potential can be maintained.

[0296] The circuit MP shown in FIG. 16B is a configuration example of the circuit MP of FIG. 5D, and is the same as the circuit MP of FIG. 9A. The difference with P is that the wiring IL and wiring OL are combined into wiring IOL, and the wiring ILB and wiring OLB are combined into wiring IOL. The key point is that these are all integrated into the wiring IOLB.

[0297] In the circuit MP of FIG. 16B, the first terminal of the transistor M8 is electrically connected to the line IOL. The transistor M8r is electrically connected to the wiring IOLB. The second terminal of the transistor M3 is electrically connected to the wiring IOL, and the second terminal of the transistor M4 is The terminal of the transistor M3r is electrically connected to the wiring IOLB, and the second terminal of the transistor M3r is electrically connected to the wiring IO LB, and the second terminal of the transistor M4r is electrically connected to the wiring IOL. The circuit MP in FIG. 16B has the same connection configuration as the circuit MP in FIG. 9A. The explanation of the parts where

[0298] In the circuit MP of FIG. 16B, the wiring IOL is electrically connected to the holding part HC, and the holding part HCr is The wiring IOLB is electrically connected to the wiring WL. Since the gates are electrically connected, the holding unit H C, a potential corresponding to a weighting coefficient can be simultaneously written to the holding unit HCr.

[0299] <Configuration example 3> The circuit MP shown in FIG. 17 differs from the circuit MP shown in FIG. 9A in that only the holding unit HC and the holding unit HCr HCs and HCsr.

[0300] The circuit MC included in the circuit MP of FIG. 17 is added to the circuit elements included in the circuit MP of FIG. 9A. E, transistor M8s, transistor M5a, transistor M5b, transistor M5 sa, a transistor M5sb, and a capacitance element C3s. The circuit MCr has the same circuit elements as the circuit MC, so the transistors of the circuit MC Transistor M8s, transistor M5a, transistor M5b, transistor M5sa, The transistors M8sr and M5sb correspond to the capacitors C3s and C4s, respectively. Transistor M5ar, transistor M5br, transistor M5sar, transistor M5sb r, and has a capacitance element C3sr.

[0301] In this specification and the like, the transistors M5a, M5b, and Transistor M5sa, transistor M5sb, transistor M5ar, transistor M5br, Unless otherwise specified, the transistors M5sar and M5sbr are in the on state. This case includes the case where the operation is ultimately in the linear region. The gate, source, and drain voltages of the transistor are set to a range where the transistor operates in the linear region. This includes when the device is properly biased to a voltage within the specified range.

[0302] Next, the configuration of the circuit MP in Fig. 17 will be described. In the circuit MP in Fig. 17, Explanation of parts having the same configuration as the circuit MP in FIG. 9A will be omitted.

[0303] The first terminal of the transistor M5a is electrically connected to the second terminal of the transistor M3; The second terminal of the transistor M5a is electrically connected to the wiring OL. The gate of the transistor M5b is electrically connected to the wiring S1L. The second terminal of the transistor M5b is electrically connected to the wiring O LB, and the gate of the transistor M5b is electrically connected to the wiring S1L. The first terminal of transistor M5sa is electrically connected to the second terminal of transistor M3s. The second terminal of the transistor M5sa is electrically connected to the wiring OL. The gate of the transistor M5sa is electrically connected to the wiring S2L. The first terminal is electrically connected to the second terminal of the transistor M4s, and the second terminal of the transistor M5sb The second terminal of the transistor M5sb is electrically connected to the wiring OLB, and the gate of the transistor M5sb is electrically connected to the wiring S 2L. The first terminal of the transistor M3s and the second terminal of the transistor M4s The first terminal of the transistor M3s is electrically connected to the wiring VLc, and the gate of the transistor M3s is electrically connected to the wiring VLc. The gate of the transistor M4s is electrically connected to the wiring X2L. It is being done.

[0304] A first terminal of the transistor M8 is electrically connected to the wiring I1L. The gate of the transistor M8s is electrically connected to the wiring WL, and the first terminal of the transistor M8s is electrically connected to the wiring WL. The second terminal of the transistor M8s is electrically connected to the line I2L. a terminal, a back gate of the transistor M3s, a back gate of the transistor M4s, The second terminal of the capacitance element C3s is electrically connected to the wiring VLcs. It has been done.

[0305] In the circuit MP of FIG. 17, the circuit MCr has almost the same circuit configuration as the circuit MC. Therefore, the circuit elements of the circuit MCr are distinguished from the circuit elements of the circuit MC. Therefore, the symbol is prefixed with "r."

[0306] The wiring VLc, wiring VLcs, wiring VLcr, and wiring VLcsr are Like Ls, wiring VLr, and wiring VLsr, it functions as a voltage line that supplies a constant voltage, The constant voltages include VSS, which is a low-level potential, a low-level potential other than VSS, and a ground potential. The constant voltage can be set to VDD, which is a high level potential. Also, the wiring VL, the wiring VLs, the wiring VLr, the wiring VLsr, the wiring VLc, and the wiring V The constant voltages supplied by the lines Lcs, VLcr, and VLcsr are different from each other. Alternatively, some or all of them may be the same.

[0307] The wiring S1L is connected to the transistors M5a, M5b, M5ar, and and a voltage line that supplies a potential to turn on or off the transistor M5br. The wiring S2L functions as a M5sar and M5sbr to provide a potential for turning on or off the transistors. It functions as a voltage line that supplies

[0308] The circuit MP shown in FIGS. 5C and 5D can be realized by applying the configuration shown in the circuit MP of FIG. Specifically, the circuit MP in FIG. The potential corresponding to the weighting coefficient is stored in the holding section HC of the circuit MC and the holding section HCr of the circuit MCr. , and the potential according to the second weighting coefficient is stored in the storage unit HCs of the circuit MC and the storage unit HCs of the circuit MC. The circuit MP in FIG. The weighting coefficients used in the calculation can be switched by the potential applied from the wiring S2L. For example, the circuits MP[1,j] to MP[m,j] included in the arithmetic circuit 110 The weighting coefficient w1 is assigned to each of the holding parts HC and HCr. (k-1) j (k) Or even w m (k-1 ) j (k) and the circuits MP[1,j] to MP Each holding part HCs, HCsr included in [m,j] is weighted by a weighting coefficient w1 (k-1) h ( k) Or even w m (k-1) h (k) (Here, h is an integer greater than or equal to 1 and not equal to j.) The wirings XLS[1] to XLS[m] (in the circuit MP in FIG. 17) are held at a potential corresponding to the Signal z1 is connected to wires X1L and X2L. (k-1) ~z m (k-1) The potential according to At this time, a high-level potential is applied to the wiring S1L, and the transistors M5a and M5b are turned on. The transistors M5b, M5ar, and M5br are turned on. A low level potential is applied to the line S2L to turn on the transistors M5sa, M5sb, and By turning off the transistor M5sar and the transistor M5sbr, the arithmetic circuit The circuits MP[1,j] to MP[m,j] of 110 are weighted by weight coefficients w1 (k-1) j (k ) Or even w m (k-1) j (k) and signal z1 (k-1) ~z m (k-1) and activation In addition, a low level potential is applied to the wiring S1L, transistor M5a, transistor M5b, transistor M5ar, and transistor M5br is turned off, a high-level potential is applied to the wiring S2L, and the transistors M5sa and M5b are turned on. The transistor M5sb, the transistor M5sar, and the transistor M5sbr are turned on. By doing so, the circuits MP[1,j] to MP[m,j] of the arithmetic circuit 110 calculate the weight coefficient w 1 (k-1) h (k) Or even w m (k-1) h (k) and signal z1 (k-1) ~z m (k- 1)It is possible to perform product sum and activation function calculations.

[0309] As described above, by applying the circuit MP of FIG. 17 to the arithmetic circuit 110, the weight coefficients are It is possible to hold two weight coefficients and switch between them to perform product sum and activation function calculations. The arithmetic circuit 110 constituting the circuit MP of FIG. 17 can, for example, When the number of nodes is greater than n, when performing calculations in a hidden layer other than the kth layer, etc. In the circuit MP of FIG. 17, the holding unit of the circuit MC and the circuit MCr However, depending on the situation, the number of circuits MC and MCr may be increased to three. The above holding portions may be provided.

[0310] The circuit MP included in the semiconductor device of one embodiment of the present invention is not limited to the circuit MP in FIG. The circuit configuration of the circuit MP of the semiconductor device of one embodiment of the present invention is different from that of the circuit MP in FIG. This can be changed depending on the situation.

[0311] For example, the circuit MP shown in FIG. 18 is a circuit in which the individual transistors included in the circuit MP of FIG. Specifically, the circuit MP in FIG. 18 is the same as the circuit M in FIG. P's transistor M5a, transistor M5b, transistor M5ar, transistor M 5br, transistor M5sa, transistor M5sb, transistor M5sar, and Instead of transistor M5sbr, transistor M5, transistor M5r, transistor The first terminal of the transistor M5 is connected to the transistor M5s. a first terminal of the transistor M3 and a first terminal of the transistor M4; The second terminal of the transistor M5 is electrically connected to the line VL. The first terminal of the transistor M5s is electrically connected to the wiring S1L. The first terminal of the transistor M3 and the first terminal of the transistor M4 are electrically connected to the first terminal of the transistor M5. The second terminal of the transistor M5s is electrically connected to the wiring VLc. is electrically connected to the wiring S2L.

[0312] The second terminal of the transistor M3 and the second terminal of the transistor M3s are electrically connected to the wiring OL. The second terminal of the transistor M4 and the second terminal of the transistor M4s are connected to the wiring O It is electrically connected to LB.

[0313] The circuit MCr of the circuit MP in FIG. 18 has almost the same circuit configuration as the circuit MC. Therefore, the circuit elements of the circuit MCr are distinguished from the circuit elements of the circuit MC. Therefore, the symbol "r" is added. The second terminal of the transistor M3sr is electrically connected to the wiring OL. The second terminal of the transistor M4r and the second terminal of the transistor M4sr are electrically connected to the wiring OLB. It continues.

[0314] The circuit MP of FIG. 18 can reduce the number of circuit elements compared to the circuit MP of FIG. Therefore, by using the circuit MP of FIG. 18 in the arithmetic circuit 110, the circuit area of ​​the arithmetic circuit 110 can be reduced. It can be reduced.

[0315] For example, the circuit MP shown in FIG. 19 is obtained by changing the configuration of the peripheral wiring of the circuit MP shown in FIG. Specifically, the circuit MP in FIG. 19 is a circuit configuration similar to that of the circuit MP in FIG. The wiring I1L and wiring I2L are grouped into wiring IL, and the wiring I1LB and wiring I2L of the circuit MP in Figure 18 are B is grouped into wiring ILB, and wiring W1L and wiring W2L are grouped into wiring WL of the circuit MP in Fig. 18. The wiring W1L is connected to the gate of the transistor M8 and the The wiring W2L is electrically connected to the gate of the transistor M8s. It is electrically connected to the gate of the transistor M8sr.

[0316] When setting the weighting coefficients for the circuit MP in FIG. 19, first, those for the wiring W1L and the wiring W2L are By changing the potential supplied to each, the transistor M8 and the transistor M8r are turned on. state, and the transistor M8s and the transistor M8sr are turned off. The potential for holding is supplied to the holding unit HC and the holding unit HCr from the wiring IL and the wiring ILB, respectively. Then, the transistor M8 and the transistor M8r are turned off. By changing the potentials supplied to the wiring W1L and the wiring W2L, the transistors M8 and The transistor M8r is turned off, and the transistor M8s and the transistor M8sr are turned on. Then, the wiring IL and wiring ILB are connected to the holding parts HCs and HCsr. A potential for holding the transistor M8s and the transistor M8sr in the off state is supplied. In this way, in the case of the circuit MP of FIG. 19, the wiring IL and the wiring ILB are connected to the holding unit HC , HCr, the holding unit HCs, and the holding unit HCsr are sequentially supplied with potentials. The potentials corresponding to the weighting coefficients are held in the HC and HCr sections, the HCs section, and the HCsr section. It is possible.

[0317] <Configuration Example 4> The circuit MP shown in FIG. 20A is applicable to the circuit MP of FIG. 5A, and includes a holding unit HC, Each of HCr is a circuit of an inverter loop instead of the capacitance element C3 and the capacitance element C3r. 9A in that it has the following configuration.

[0318] In the circuit MC of the circuit MP of FIG. 20A, the holding unit HC includes an inverter circuit INV5 and The input terminal of the inverter circuit INV5 is connected to an inverter circuit INV6. the output terminal of the inverter circuit INV6, the second terminal of the transistor M8, and the buffer of the transistor M3 The gate of the transistor M1 is electrically connected to the back gate of the transistor M2 and the back gate of the transistor M3. As in the description of 9A, the second terminal of transistor M8 and the back gate of transistor M3 the back gate of the transistor M4, the input terminal of the inverter circuit INV5, The electrical connection point between the output terminal of the data circuit INV6 and the node nd3 is called the node nd4. The terminal nd3 is not the input terminal of the inverter circuit INV5, but the output terminal of the inverter circuit INV5. The power terminal may be connected to the power terminal.

[0319] The circuit MCr of the circuit MP in FIG. 20A has almost the same circuit configuration as the circuit MC. Therefore, the circuit elements of the circuit MCr are distinguished from the circuit elements of the circuit MC. Therefore, the symbol is prefixed with "r."

[0320] The holding unit HC included in the circuit MC is an inverter circuit INV5 and an inverter circuit I NV6 and NV7 form an inverter loop, and the holding unit H included in the circuit MCr Cr is an inverter circuit INV5r, an inverter circuit INV6r, and That is, the circuit MP in FIG. 20A includes a holding unit HC and a holding unit H Each inverter loop of Cr can hold a potential corresponding to the weighting coefficient. can.

[0321] In the circuit MP of FIG. 20A, the inverter circuit INV5 and the inverter circuit INV5r , inverter circuit INV6 and inverter circuit INV6r are shown, circuit INV5, inverter circuit INV5r, inverter circuit INV6, inverter circuit IN At least one of V6r is a logic circuit that receives an input signal and outputs an inverted signal of the input signal. The logic circuit may be replaced with a circuit, such as a NAND circuit, a NOR circuit, XOR circuits, and circuits combining these. Specifically, inverters When replacing the circuit with a NAND circuit, a fixed potential is applied to one of the two input terminals of the NAND circuit. By inputting a high-level potential, the NAND circuit can function as an inverter circuit. Also, when replacing the inverter circuit with a NOR circuit, the two input terminals of the NOR circuit By inputting a low-level potential as a fixed potential to one of the Also, if the inverter circuit is replaced with an XOR circuit, the XOR By inputting a high-level voltage as a fixed voltage to one of the two input terminals of the R circuit, an XOR circuit can function as an inverter circuit.

[0322] As described above, the inverter circuits described in this specification and the like are not limited to NAND circuits, NOR circuits, or the like. It can be replaced with a logic circuit such as a logic circuit, an XOR circuit, or a circuit that combines these. Therefore, in this specification and elsewhere, the term "inverter circuit" is used interchangeably with "logic circuit." It can be called as:

[0323] The circuit MP in Figure 20A can be reconfigured depending on the situation. An example of a modified circuit MP is shown in FIG. 20B. The circuit MP of FIG. 20B is the same as the circuit MP of FIG. 20A. The MP circuit MCr is configured by removing the holding unit HCr, and the holding unit HC of the circuit MC is configured by removing the holding unit HCr from the circuit MCr. The back gates of the transistors M3r and M4r of the MCr are electrically connected to the It is structured as follows.

[0324] In FIG. 20B, the output terminal of the inverter circuit INV5 and the input terminal of the inverter circuit INV6 The electrical connection point between the terminal and the node nd3r is the The potential of the node nd3r is input to the back gate of the transistor M4r and the back gate of the transistor M4r. Be encouraged.

[0325] In the circuit MP shown in FIG. 20B, the holding unit HCr is not included in the circuit MCr, and the transistor The potentials applied to the back gates of M3r and M4r are The voltage is held by the holding unit HC of the MC. The holding unit HC is connected to the inverter circuit INV5. Since the inverter circuit INV6 has an inverter loop configuration, the node nd3 At node nd3r, either a high level potential or a low level potential is held, and at node nd4r, a high level potential is held. Alternatively, the other is maintained at a low level potential.

[0326] In addition, in the configuration of the inverter loop, the holding unit HC is connected to the node nd3 and the node nd3r. Therefore, in the circuit MP of FIG. This is expressed by maintaining the same potential at the nodes nd3 and nd3r. Specifically, in the above example of operation, it is not possible to set a weighting coefficient for the transistor. The transistors M3, M4, M3r, and M4r are Since the back gate cannot be held at a low level potential, the weighting factor "0" is set to the circuit MP of FIG. 20B. cannot be set.

[0327] <Configuration example 5> In the configuration examples 1 to 4, the weighting coefficients held by the circuit MP are "+1", "-1", and "0". " and the neuron signal according to the potential input from the wires X1L and X2L is "+1 This section explains the circuit MP, which can calculate the product of three values: "," "-1," and "0" However, in this configuration example, as an example, the weighting coefficients are three values ​​of "+1", "-1" and "0", and Regarding the circuit MP, which can calculate the product of the neuron signal with two values ​​of "+1" and "0", and explain.

[0328] The circuit MP shown in FIG. 21A is a circuit MP of FIG. 9A, which is obtained by removing transistor M4 and transistor The circuit excluding the transistor M4 and the transistor M4r is also shown. Therefore, in FIG. 21A, the gates of the transistors M4 and M4r are The wiring X2L for inputting the potential to the GND is also excluded. In addition, the wiring equivalent to the wiring X1L is In FIG. 21A, this is indicated as wiring XL.

[0329] The weighting coefficient set in the circuit MP in FIG. 21A is a weighting coefficient set in the node nd3 of the holding unit HC when a high-level voltage is applied to the node nd3. When a low level potential is held at the node nd3r of the holding unit HCr, it is set to "+1". , a low level potential is applied to the node nd3 of the holding unit HC, and a high level potential is applied to the node nd3r of the holding unit HCr. When the potential is held, it is set to "-1" and a low level potential is applied to the node nd3 of the holding unit HC. When a low level potential is held at the node nd3r of the holding unit HCr, it is set to "0".

[0330] In addition, the neuron signal input to the circuit MP in FIG. 21A is a high-level potential on the wire XL. When a low level potential is applied to the wiring XL, it is set to "+1". Let it be “0”.

[0331] For the operation of the circuit MP in FIG. 21, please refer to the explanation of the operation example of the first configuration example.

[0332] In the circuit MP of FIG. 21, as mentioned above, the weight coefficients and the input neuron signals are When the weight coefficients are defined, the neuron signal is input to the circuit MP. As a result, the current I output from node outa of wiring OL OL Changes in , and the current I output from node outb of wiring OLB OLB The presence or absence of change is as follows In the table below, high level potential is indicated as high, and low level potential is indicated as It is described as low.

[0333] [Table 3]

[0334] As shown in the table above, the circuit MP in FIG. 21A has three weighting coefficients: "+1", "-1", and "0". The product of this and the binary value of the neuron signal, "+1" or "0", can be calculated. The weighting coefficient may be two values ​​or more than three values ​​instead of three values. For example, It may be a binary value of "1" or "0", or a binary value of "+1" or "-1". Alternatively, a weighting coefficient may be an analog value or a multi-bit (multi-valued) digital value.

[0335] In this operation example, the holding units HC and H included in the circuit MC and circuit MCr of the circuit MP The potential held in Cr is set to a high level potential or a low level potential, but the holding part HC and The holding unit HCr may hold a potential indicating an analog value. For example, In the case of a "positive analog value", a high level analog potential is applied to the node nd3 of the holding unit HC, A low level potential is held at the node nd3r of the holding part HCr. In the case of "analog value", for example, a low level potential is applied to the node nd3 of the holding unit HC, and A high-level analog potential is held at node nd3r of r. Then, the current I OL Reach and current I OLB The magnitude of the current is in accordance with the analog potential.

[0336] Furthermore, the configuration of the circuit MP in Figure 21A can be changed depending on the situation. A modified example of the circuit MP is shown in FIG. 21B. The circuit MP of FIG. 21B is a modified version of the circuit MP of FIG. 21A. The electrical connections between the gate and back gate of transistor M3 and transistor M3r are swapped. The gate potentials of the transistors M3 and M3r are The circuit MP is configured to hold the wiring by the holding portion HC and the holding portion HCr. A potential is applied to the back gates of the transistors M3 and M3r from the line XL. The potential applied from the wiring XL turns on the transistors M3 and M3 The threshold voltage of r is changed to switch between the on and off states. do.

[0337] In the circuit MP of FIG. 21B, the change in the current flowing through the wiring OL and wiring OLB is Therefore, in the circuit MP of FIG. The combination of the potentials held at the nodes nd3 and nd3r and the potential given by the wiring XL The current I output from the node outa of the wiring OL is determined by the OL Changes in and the current I output from node outb of wiring OLB OLB The presence or absence of changes in The result is as shown in the above table, which was explained for the circuit MP in FIG. 21A.

[0338] 21A, similar to the circuit MP of FIG. 16A, the wiring IL and Even if the wiring ILB is combined into one and the wiring WL is divided into wiring W1L and wiring W2L, Such a circuit configuration is shown in FIG. 22A. The circuit MP in FIG. 22A may be implemented as an example using the circuit shown in FIG. The operation method of the circuit MP in FIG. For details, please refer to the description of the operation method of the circuit MP in FIG. 16A.

[0339] As a modification of the circuit MP of FIG. 22A, the wiring XL is divided into wiring X1L and wiring X2L. Such a circuit configuration is shown in FIG. 22B. Each of them is given a high level potential (Vg1) or a low level potential (Vg2). The potentials given by the wiring X1L and the wiring X2L are combined in four ways. The nodes nd3 and nd3r of the holding unit HCr and C are connected to a high level potential or a low level potential. If the level potential is maintained, the potential maintained at the node nd3 and the node nd3r is There are four possible combinations.

[0340] Specifically, a high-level potential is held at the node nd3, and a high-level potential (V When voltage g1) is applied, the line OL and the line VL are in a conductive state. Amount of current flowing through OL I OL Also, a high level potential is held at node nd3r. When a high-level potential (Vg1) is applied to the wiring X2L, the wiring OLB and the wiring VL Since the connection between r and OLB is established, the current I OLB Figure 22 In the circuit MP of B, the combination of the potentials held at the node nd3 and the node nd3r and the combination of potentials applied by the wiring X1L and the wiring X2L. The current I output from node outa of wiring OL OL Changes in wiring OLB The current I output from the board outb OLB The changes in the following are as shown in the table below. In the table below, high level potential is written as "high" and low level potential is written as "low". .

[0341] [Table 4]

[0342] In this example of operation, the holding units HC The potential held in the holding unit HCr is set to a high level potential or a low level potential. The weighting coefficient HC and the holding coefficient HCr may hold a potential indicating an analog value. In the case of a "positive analog value" as a number, a high-level analog signal is output to node nd3 of the holding unit HC. A low level potential is held at the node nd3r of the holding unit HCr. In the case of a "negative analog value", for example, a low level potential is applied to the node nd3 of the holding unit HC, A high level analog potential is held at the node nd3r of the holding unit HCr. Flow I OL and current I OLB The magnitude of the current is in accordance with the analog potential.

[0343] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. do.

[0344] (Embodiment 3) In this embodiment mode, an OS transistor applicable to the semiconductor device described in the above embodiment mode will be described. An example of the configuration of the data will be described below.

[0345] <Configuration example of semiconductor device> The semiconductor device shown in FIG. 23 includes a transistor 300, a transistor 500, and a capacitor element 25A is a cross-sectional view of the transistor 500 in the channel length direction. 25B is a cross-sectional view of the transistor 500 in the channel width direction, and FIG. 25C is a cross-sectional view of the transistor 500 in the channel width direction. 1 is a cross-sectional view of a transistor 300 in the channel width direction.

[0346] The transistor 500 is a transistor having a metal oxide in a channel formation region (OS transistor). Since the off-state current of the transistor 500 is small, it is , in particular, the transistors M3 and M4 of the circuit MP included in the arithmetic circuit 110, By using it in transistor M8, etc., it is possible to retain written data for a long period of time. In other words, it is possible to perform refresh operations less frequently or Since no operation is required, the power consumption of the semiconductor device can be reduced.

[0347] The transistor 500 is provided above the transistor 300, and the capacitance element 600 is provided above the transistor 300. The capacitor 600 is provided above the transistor 300 and the transistor 500. can be the capacitive element C3, the capacitive element C3r, etc. in the circuit MP.

[0348] The transistor 300 is disposed on a substrate 311, and includes a conductor 316, an insulator 315, and a substrate a semiconductor region 313 formed of a part of the semiconductor region 311; The transistor 300 has a resistive region 314a and a low resistive region 314b. For example, the present invention can be applied to the transistors in the above embodiments.

[0349] The transistor 300 is formed by forming a semiconductor region 313 on the upper surface thereof and a channel region thereof as shown in FIG. 25C. The side surfaces in the width direction are covered with the conductor 316 via the insulator 315. By making the resistor 300 a fin type, the effective channel width is increased, and This can improve the on-characteristics of the transistor 300. In addition, the contribution of the electric field of the gate electrode can be increased, thereby improving the off-state characteristics of the transistor 300. .

[0350] The transistor 300 may be either a p-channel type or an n-channel type. .

[0351] The region where the channel of the semiconductor region 313 is formed, the region nearby, the source region, or the drain region In the low resistance region 314a and the low resistance region 314b, which are to be the drain region, silicon It is preferable that the material contains a semiconductor such as a silicon-based semiconductor, and it is preferable that the material contains single crystal silicon. are Ge (germanium), SiGe (silicon germanium), and GaAs (gallium arsenide). Alternatively, the insulating layer 12 may be formed of a material containing gallium aluminum arsenide (GaAlAs), GaAlAs (gallium aluminum arsenide), or the like. It uses silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing. Alternatively, the transistor 30 may be formed by using GaAs and GaAlAs. 0 stands for HEMT (High Electron Mobility Transistor) ) can also be used.

[0352] The low resistance region 314a and the low resistance region 314b are semiconductor regions applied to the semiconductor region 313. In addition to the material, elements that give n-type conductivity, such as arsenic or phosphorus, or p-type conductivity, such as boron, are added. It contains an element that provides electrical conductivity.

[0353] The conductor 316, which functions as a gate electrode, is made of arsenic, phosphorus, or the like, which provides n-type conductivity. Semiconductor materials such as silicon that contain elements or elements that give them p-type conductivity, such as boron Conductive materials such as aluminum, metal, alloy, or metal oxide materials can be used.

[0354] Since the work function is determined by the material of the conductor, it is necessary to select the material of the conductor. Specifically, the conductor is made of nitride silicon, and the threshold voltage of the transistor can be adjusted. It is preferable to use materials such as tantalum or tantalum nitride. To achieve this, metal materials such as tungsten and aluminum are used as layers for the conductor. It is preferable to use tungsten, in particular, in terms of heat resistance.

[0355] The transistor 300 shown in FIG. 23 is an example, and the present invention is not limited to this structure. An appropriate transistor may be used depending on the structure and driving method. In the case of a unipolar circuit using only transistors, the structure of transistor 300 is as shown in FIG. The structure of the transistor 500 may be similar to that of the transistor 500 including an oxide semiconductor. The transistor 500 will be described in detail below.

[0356] Over the transistor 300 are insulators 320, 322, 324, and The bodies 326 are stacked one on top of the other.

[0357] The insulators 320, 322, 324, and 326 may be, for example, oxide. Silicon, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, oxide Aluminum oxynitride, aluminum nitride oxide, aluminum nitride, etc. may be used.

[0358] In this specification, silicon oxynitride refers to a material having a higher content of oxygen than nitrogen in its composition. Silicon nitride oxide refers to a material that contains more nitrogen than oxygen. In this specification, aluminum oxynitride refers to a material with a high content. Aluminum oxide nitride is a material that has a higher oxygen content than nitrogen. It refers to a material that contains more nitrogen than oxygen as a constituent.

[0359] The insulator 322 serves to eliminate a step caused by the transistor 300 and other components disposed below it. For example, the top surface of the insulator 322 may have a function as a planarizing film. To improve flatness, the surface is flattened by a planarization process using chemical mechanical polishing (CMP) or other methods. It may be possible.

[0360] The insulator 324 is also provided with a substrate 311 or a transistor 300, etc. A film having a barrier property that prevents hydrogen and impurities from diffusing is used in the area where the capacitor 500 is provided. It is preferable that

[0361] An example of a film having a barrier property against hydrogen is silicon nitride formed by CVD. Here, a semiconductor having an oxide semiconductor such as the transistor 500 can be used. The diffusion of hydrogen into semiconductor elements can cause a deterioration in the characteristics of the semiconductor elements. Therefore, a film that suppresses hydrogen diffusion is provided between the transistor 500 and the transistor 300. Specifically, the film that suppresses the diffusion of hydrogen is a film that reduces the amount of hydrogen desorption. The membrane is thin.

[0362] The amount of hydrogen desorption can be analyzed using, for example, thermal desorption spectroscopy (TDS). For example, the amount of hydrogen desorbed from the insulator 324 can be determined by TDS analysis as follows: In the range of 50°C to 500°C, the amount of desorption converted to hydrogen atoms is Converted to a hit, it's 10 x 10 15 atoms / cm 2 Less than or equal to 5 x 10 15 a toms / cm 2 The following is fine.

[0363] It is preferable that the insulator 326 has a lower dielectric constant than the insulator 324. For example, The dielectric constant of the insulator 326 is preferably less than 4, more preferably less than 3. The relative dielectric constant of the insulator 326 is preferably 0.7 times or less than the relative dielectric constant of the insulator 324, and more preferably 0.6 times or less. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance generated between wirings can be reduced. It can be reduced.

[0364] The insulators 320, 322, 324, and 326 are connected to the capacitance element 6. 00, or the conductor 328 and the conductor 330 connected to the transistor 500 are embedded. The conductor 328 and the conductor 330 function as plugs or wiring. In addition, the conductors that function as plugs or wiring are grouped together to form the same structure. In addition, in this specification and the like, a wiring and a plug connected to the wiring may be In other words, when a part of the conductor functions as a wiring, In some cases, a portion of the conductor functions as a plug.

[0365] The materials for each plug and wiring (conductor 328, conductor 330, etc.) include metal materials, alloys, and the like. Conductive materials such as gold, metal nitride, or metal oxide materials are used in a single layer or laminated layers. High-melting-point materials such as tungsten and molybdenum, which are both heat-resistant and conductive, can be used. It is preferable to use a material such as tungsten, or aluminum. It is preferable to form the wiring layer from a low-resistance conductive material such as copper. This can reduce the wiring resistance.

[0366] A wiring layer may be provided on the insulator 326 and the conductor 330. For example, in FIG. An insulator 350, an insulator 352, and an insulator 354 are stacked in this order. In addition, a conductor 356 is formed on the insulators 350, 352, and 354. The conductor 356 functions as a plug or wiring that connects to the transistor 300. The conductor 356 is made of the same material as the conductors 328 and 330. It is possible.

[0367] For example, the insulator 350 has a barrier property against hydrogen, similar to the insulator 324. It is preferable to use an insulator having a barrier property against hydrogen. It is preferable that the insulating material 350 has a barrier property against hydrogen. A conductor having a barrier property against hydrogen is formed in the opening. The transistor 300 and the transistor 500 can be separated by a barrier layer. The diffusion of hydrogen from the transistor 300 to the transistor 500 can be suppressed.

[0368] As a conductor having a barrier property against hydrogen, for example, tantalum nitride or the like is used. In addition, by laminating tantalum nitride and highly conductive tungsten, The diffusion of hydrogen from the transistor 300 can be suppressed while maintaining the overall conductivity. In this case, the tantalum nitride layer having a barrier property against hydrogen is It is preferable that the insulating body 350 has a structure in which the insulating body 350 is in contact with the insulating body 350.

[0369] A wiring layer may be provided on the insulator 354 and the conductor 356. For example, in FIG. An insulator 360, an insulator 362, and an insulator 364 are stacked in this order. In addition, a conductor 366 is formed on the insulators 360, 362, and 364. The conductor 366 functions as a plug or wiring. The conductive body 328 and the conductive body 330 may be formed using the same materials.

[0370] For example, the insulator 360 has a barrier property against hydrogen, similar to the insulator 324. It is preferable to use an insulator having a barrier property against hydrogen. It is preferable that the insulating material 360 has a barrier property against hydrogen. A conductor having a barrier property against hydrogen is formed in the opening. The transistor 300 and the transistor 500 can be separated by a barrier layer. The diffusion of hydrogen from the transistor 300 to the transistor 500 can be suppressed.

[0371] A wiring layer may be provided on the insulator 364 and the conductor 366. For example, in FIG. An insulator 370, an insulator 372, and an insulator 374 are stacked in this order. In addition, a conductor 376 is formed on the insulators 370, 372, and 374. The conductor 376 functions as a plug or wiring. The conductive body 328 and the conductive body 330 may be formed using the same materials.

[0372] For example, the insulator 370 has a barrier property against hydrogen, similar to the insulator 324. It is preferable to use an insulator having a barrier property against hydrogen. In particular, an insulator 370 having a barrier property against hydrogen is useful. A conductor having a barrier property against hydrogen is formed in the opening. The transistor 300 and the transistor 500 can be separated by a barrier layer. The diffusion of hydrogen from the transistor 300 to the transistor 500 can be suppressed.

[0373] A wiring layer may be provided on the insulator 374 and the conductor 376. For example, in FIG. An insulator 380, an insulator 382, ​​and an insulator 384 are stacked in this order. In addition, a conductor 386 is formed on the insulators 380, 382, ​​and 384. The conductor 386 functions as a plug or wiring. The conductive body 328 and the conductive body 330 may be formed using the same materials.

[0374] For example, the insulator 380 has a barrier property against hydrogen, similar to the insulator 324. It is preferable to use an insulator having a barrier property against hydrogen. It is preferable that the insulator 380 has a barrier property against hydrogen. A conductor having a barrier property against hydrogen is formed in the opening. The transistor 300 and the transistor 500 can be separated by a barrier layer. The diffusion of hydrogen from the transistor 300 to the transistor 500 can be suppressed.

[0375] In the above, the wiring layer including the conductor 356, the wiring layer including the conductor 366, the conductor 376 The wiring layer including the conductor 386 has been described above. The semiconductor device is not limited to this. Alternatively, the number of wiring layers may be three or less, or five or more wiring layers similar to the wiring layer including the conductor 356 may be provided. Good too.

[0376] On the insulator 384, an insulator 510, an insulator 512, an insulator 514, and an insulator 516 are formed. , are stacked in this order. It is preferable that any of the bodies 516 is made of a material that has a barrier property against oxygen and hydrogen. .

[0377] For example, the insulator 510 and the insulator 514 may include, for example, the substrate 311 or the transistor. Hydrogen and impurities diffuse from the region where the capacitor 300 is provided to the region where the transistor 500 is provided. It is preferable to use a film having a barrier property that prevents the diffusion of the insulator 324. The same materials as those mentioned above can be used.

[0378] As an example of a film with barrier properties against hydrogen, silicon nitride formed by CVD is used. Here, a semiconductor element including an oxide semiconductor, such as the transistor 500, However, the diffusion of hydrogen may deteriorate the characteristics of the semiconductor element. A film that suppresses hydrogen diffusion is used between the transistor 500 and the transistor 300. Specifically, the film that suppresses hydrogen diffusion is a film that releases a small amount of hydrogen. do.

[0379] In addition, as a film having a barrier property against hydrogen, for example, an insulator 510 and an insulator 5 14 uses metal oxides such as aluminum oxide, hafnium oxide, and tantalum oxide. It is preferable.

[0380] In particular, aluminum oxide is a material that can absorb oxygen and hydrogen, which can cause fluctuations in the electrical characteristics of transistors. Therefore, it has a high blocking effect that prevents impurities such as acid and moisture from passing through the membrane. Aluminum oxide is a material that can absorb impurities such as hydrogen and moisture during and after the transistor manufacturing process. This can prevent impurities from being mixed into the transistor 500. Therefore, the release of oxygen from the oxide constituting the transistor 5 can be suppressed. Suitable for use as a protective film against 00.

[0381] For example, the insulators 512 and 516 may be made of the same material as the insulator 320. In addition, by using materials with a relatively low dielectric constant for these insulators, , the parasitic capacitance occurring between the wirings can be reduced. A silicon oxide film, a silicon oxynitride film, or the like can be used as the film 516 .

[0382] In addition, the insulators 510, 512, 514, and 516 are provided with conductors 5 18, and conductors (for example, conductor 503) that constitute the transistor 500 are embedded. Note that the conductor 518 is connected to the capacitor 600 or the transistor 300. The conductor 518 functions as a plug or a wiring. It can be provided using the same material as 30.

[0383] In particular, the insulator 510 and the conductor 518 in the area in contact with the insulator 514 are free of oxygen, hydrogen, It is preferable that the conductive material has a barrier property against water. The transistor 300 and the transistor 500 have barrier properties against oxygen, hydrogen, and water. The layer can be separated, and hydrogen diffusion from transistor 300 to transistor 500 can be suppressed.

[0384] Above the insulator 516 is the transistor 500 .

[0385] As shown in FIGS. 25A and 25B, the transistor 500 includes an insulator 514 and an insulator 516. The conductor 503 is disposed so as to be embedded in the insulator 516, and the insulator 516 and the conductor 50 3, an insulator 520 disposed on the insulator 520, and an insulator 522 disposed on the insulator 520. An insulator 524 is disposed on the insulator 522, and an oxide 53 is disposed on the insulator 524. 530a, oxide 530b disposed on oxide 530a, and oxide 530b disposed on oxide 530b. Conductor 542a and conductor 542b are spaced apart, and conductor 542a and conductor 54 2b, and an opening is formed between the conductors 542a and 542b. The edge 580, the oxide 530c disposed on the bottom and side surfaces of the opening, and the shape of the oxide 530c an insulator 550 disposed on the forming surface; and a conductor 560 disposed on the forming surface of the insulator 550; It has.

[0386] As shown in FIGS. 25A and 25B, the oxide 530a, the oxide 530b, and the conductive The insulator 544 is disposed between the conductor 542a and the insulator 580, and the conductor 542b. As shown in FIGS. 25A and 25B, the conductor 560 is preferably made of an insulator 560. 50, and a conductor 560a provided inside the conductor 560a. It is preferable to have a conductor 560b provided thereon. As shown, an insulator 574 is disposed over an insulator 580, a conductor 560, and an insulator 550. It is preferable that the

[0387] In the following, the oxide 530a, the oxide 530b, and the oxide 530c will be collectively referred to as oxides 530a, 530b, and 530c. It is sometimes called oxide 530.

[0388] In the transistor 500, an oxide is formed in the region where the channel is formed and in the vicinity thereof. 5 shows a structure in which three layers of oxide 530a, oxide 530b, and oxide 530c are stacked. However, the present invention is not limited to this. For example, a single layer of oxide 530b, an oxide a two-layer structure of oxide 530b and oxide 530a; a two-layer structure of oxide 530b and oxide 530c; Alternatively, a stacked structure of four or more layers may be provided. Although the conductive body 560 is shown as a two-layer laminate structure, the present invention is not limited to this. For example, the conductor 560 may have a single layer structure or a laminated structure of three or more layers. 23 and 25A is an example, and the structure of the transistor 500 is not limited to this example. It is only necessary to use an appropriate transistor depending on the circuit configuration and driving method.

[0389] Here, the conductor 560 functions as the gate electrode of the transistor, and the conductors 542a and The conductor 542b functions as a source electrode and a drain electrode, respectively. The conductor 560 is sandwiched between the opening of the insulator 580 and the conductors 542a and 542b. The conductor 560, the conductor 542a, and the conductor 542b are formed so as to be embedded in the region. The placement of 42b is selected to be self-aligned with the opening of the insulator 580. In the transistor 500, the gate electrode is self-aligned between the source electrode and the drain electrode. Therefore, the conductor 560 can be positioned with a margin for alignment. Since the transistor 500 can be formed without any additional wiring, the area occupied by the transistor 500 can be reduced. This allows for miniaturization and high integration of semiconductor devices.

[0390] Furthermore, the conductor 560 is self-aligned in the region between the conductors 542a and 542b. Since the conductor 560 is formed, the conductor 560 has an overlapping region with the conductor 542a or the conductor 542b. As a result, the gap formed between the conductor 560 and the conductors 542a and 542b is Therefore, the switching speed of the transistor 500 can be improved. This improves the sound quality and provides high frequency characteristics.

[0391] Conductor 560 may function as a first gate (also called a top gate) electrode. The conductor 503 also functions as a second gate (also called a bottom gate) electrode. In this case, the potential applied to the conductor 503 may be different from the potential applied to the conductor 560. The threshold voltage of the transistor 500 is controlled by changing them independently without linking them together. In particular, applying a negative potential to the conductor 503 can turn on the transistor 5 It is possible to increase the threshold voltage of 00 to be higher than 0V and reduce the off-current. Therefore, when a negative potential is applied to the conductor 503, the conductor 560 This can reduce the drain current when the potential applied to is 0V.

[0392] The conductor 503 is arranged to overlap the oxide 530 and the conductor 560. Therefore, when a potential is applied to the conductor 560 and the conductor 503, The electric field and the electric field generated by the conductor 503 are connected, and a channel is formed in the oxide 530. In this specification and the like, the first gate electrode and the second gate electrode can cover the region where the first gate electrode and the second gate electrode are formed. The structure of a transistor in which the electric field of the gate electrode electrically surrounds the channel formation region is called This is called a surrounded channel (S-channel) structure.

[0393] The conductor 503 has the same structure as the conductor 518, and the insulators 514 and 5 Conductor 503a is formed in contact with the inner wall of opening 16, and conductor 503b is formed further inside. In the transistor 500, the conductor 503a and the conductor 503b are stacked. However, the present invention is not limited to this. The body 503 may have a single layer structure or a laminated structure of three or more layers.

[0394] Here, the conductor 503a is a diffusion layer for impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms. It is preferable to use a conductive material that has the function of suppressing the impurities (i.e., the impurities are less likely to permeate). Alternatively, the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) is suppressed. It is preferable to use a conductive material that has the function of being difficult to permeate by the above oxygen. In this specification, the function of suppressing the diffusion of impurities or oxygen means the function of suppressing the diffusion of the above impurities or the above The function is to suppress the diffusion of any one or all of the oxygen.

[0395] For example, the conductor 503a has a function of suppressing the diffusion of oxygen, so that the conductor 503 This can prevent b from being oxidized and the electrical conductivity from decreasing.

[0396] When the conductor 503 also functions as a wiring, the conductor 503b is made of tungsten, copper, or the like. It is preferable to use a conductive material having high conductivity, such as aluminum or aluminum-based material. In this case, the conductor 505 is not necessarily provided. Although shown in the figure, it may have a laminated structure, for example, titanium or titanium nitride and the above conductive material. The above may be laminated.

[0397] The insulators 520, 522, and 524 function as a second gate insulating film. It has.

[0398] Here, the insulator 524 in contact with the oxide 530 has more oxygen than the stoichiometric composition. It is preferable to use an insulator that contains a large amount of oxygen. That is, the insulator 524 has an excess oxygen region. It is preferable that the insulator containing such excess oxygen is formed in the oxide 530. By providing the oxide 530 in contact with the oxide 530, oxygen vacancies in the oxide 530 are reduced, and the signal quality of the transistor 500 is improved. Reliability can be improved.

[0399] As an insulator having an excess oxygen region, specifically, an oxide in which a part of oxygen is released by heating is used. It is preferable to use oxide materials. Oxides that release oxygen when heated are called TDS (Th Thermal Desorption Spectroscopy (DSS) analysis revealed that the oxygen atoms The converted amount of oxygen desorption is 1.0 x 10 18 atoms / cm 3 Above 1.0, preferably 1.0 x10 19 atoms / cm 3 More preferably, 2.0 × 10 19 atoms / c m 3 or more, or 3.0 x 10 20 atoms / cm 3 The oxide film is as described above. The surface temperature of the film during the TDS analysis is 100°C or higher and 700°C or lower. The temperature range is preferably from 0°C to 400°C.

[0400] In addition, the insulator having the excess oxygen region and the oxide 530 are in contact with each other and then subjected to heat treatment. Alternatively, one or more of the following may be performed: microwave treatment, RF treatment, or the like. By performing the treatment, water or hydrogen in the oxide 530 can be removed. For example, In oxide 530, the reaction in which the VoH bond is broken, in other words, "V O H→V O +H This reaction occurs, and some of the hydrogen generated is dehydrogenated. The oxide 530 or the insulator adjacent to the oxide 530 is removed by combining with the element to form H2O. In addition, some of the hydrogen may diffuse or be absorbed into the conductor 542a and the conductor 542b. may be captured (also known as gettering).

[0401] The microwave treatment may be carried out using, for example, an apparatus having a power source that generates high-density plasma. Alternatively, it is preferable to use a device having a power source that applies RF to the substrate side. By using a gas containing oxygen and high density plasma, high density oxygen radicals are generated. By applying RF to the substrate side, the high density plasma generated Oxygen radicals are efficiently introduced into the oxide 530 or into the insulator near the oxide 530. The microwave treatment can be carried out at a pressure of 133 Pa or more, preferably 200 The pressure may be 400 Pa or more, more preferably 400 Pa or more. The gases introduced into the device are, for example, oxygen and argon, with an oxygen flow rate ratio (O / (O2+Ar)) is set to 50% or less, preferably 10% or more and 30% or less.

[0402] In addition, during the manufacturing process of the transistor 500, the surface of the oxide 530 is exposed. The heat treatment is preferably carried out at a temperature of, for example, 100° C. or higher and 450° C. or lower. Preferably, the heat treatment is carried out at a temperature of 350° C. or higher and 400° C. or lower. or an inert gas atmosphere, or an oxidizing gas of 10 ppm or more, 1% or more, or 10 For example, the heat treatment is preferably carried out in an oxygen atmosphere. This provides oxygen to the oxide 530, eliminating oxygen vacancies (V O ) can be reduced. The heat treatment may be carried out under reduced pressure or under nitrogen gas or an inert gas. After heat treatment in a gas atmosphere, oxidizing gas is added at 10 ppm to compensate for the oxygen that has been removed. The oxidation may be carried out in an atmosphere containing 1% or more, 1% or more, or 10% or more of an oxidizing gas. After heat treatment in an atmosphere containing 0 ppm or more, 1% or more, or 10% or more, nitrogen is continuously The heat treatment may be carried out in an atmosphere of nitrogen gas or inert gas.

[0403] In addition, by performing an oxygen addition treatment on the oxide 530, oxygen vacancies in the oxide 530 are filled with oxygen. The reaction of repairing the damaged area with oxygen, in other words, "V O +O→null reaction Furthermore, the supplied oxygen reacts with the hydrogen remaining in the oxide 530. By doing so, the hydrogen can be removed as H2O (dehydration). The hydrogen remaining in the oxide 530 recombines with the oxygen vacancy to form V O Inhibits the formation of H It is possible.

[0404] Also, if the insulator 524 has an excess oxygen region, the insulator 522 may be oxygen-rich (e.g., It has the function of suppressing the diffusion of oxygen atoms, oxygen molecules, etc. (the oxygen is less likely to permeate) It is preferable that:

[0405] The insulator 522 has a function of suppressing the diffusion of oxygen and impurities, and the oxide 530 The oxygen contained in the conductor 503 is preferably not diffused to the insulator 520 side. This can prevent the insulator 524 and the oxide 530 from reacting with oxygen.

[0406] The insulator 522 may be, for example, aluminum oxide, hafnium oxide, aluminum and hafnium oxide. oxides containing ammonium (hafnium aluminate), tantalum oxide, zirconium oxide, titanium Lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba Insulators containing so-called high-k materials such as (Sr, Sr)TiO3 (BST) are used as single layers or laminated layers. As transistors become smaller and more highly integrated, the gate insulating layer Thinning the film can cause problems such as leakage current. Functions as a gate insulating film By using a high-k material as the insulator, the transistor behavior can be improved while maintaining the physical thickness. This makes it possible to reduce the gate potential during operation.

[0407] In particular, it has the function of suppressing the diffusion of impurities and oxygen (the oxygen is difficult to penetrate) ) Use an insulator containing oxide of one or both of aluminum and hafnium, which are insulating materials. It is recommended to use an oxide of aluminum or hafnium as an insulator. Aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium It is preferable to use a material such as aluminum aluminate. When formed, the insulator 522 prevents oxygen from being released from the oxide 530 and prevents the transistor 500 from being damaged. The layer functions as a layer that suppresses the intrusion of impurities such as hydrogen from the surrounding area into the oxide 530.

[0408] Alternatively, for example, aluminum oxide, bismuth oxide, or germanium oxide may be added to these insulators. Niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, Alternatively, zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be laminated on the edge.

[0409] The insulator 520 is preferably thermally stable. For example, silicon oxide and Silicon oxide nitride and silicon oxynitride are suitable because they are thermally stable. By combining an insulator with silicon oxide or silicon oxynitride, it is possible to obtain a thermally stable Furthermore, it is possible to obtain the insulator 520 having a laminated structure with a high relative dielectric constant.

[0410] 25A and 25B, the transistor 500 has a three-layer stack structure. As the second gate insulating film, an insulator 520, an insulator 522, and an insulator 524 are illustrated. However, the second gate insulating film may have a single layer, two layers, or a laminated structure of four or more layers. In this case, it is not limited to a laminated structure made of the same material, but may be a laminated structure made of different materials. Good too.

[0411] The transistor 500 includes an oxide 530 including a channel formation region, and an oxide semiconductor It is preferable to use a functional metal oxide. For example, the oxide 530 is In-M- Zn oxide (element M is aluminum, gallium, yttrium, copper, vanadium, beryl Sodium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, la tantalum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium It is preferable to use a metal oxide such as one or more selected from the following. Examples of the In-M-Zn oxide that can be used as the In-Zn oxide include CAAC-OS, The oxide 530 is preferably an In—Ga oxide, an I n-Zn oxide may also be used.

[0412] Furthermore, it is preferable to use a metal oxide with a low carrier concentration for the transistor 500. When the carrier concentration of the metal oxide is reduced, the impurity concentration in the metal oxide is reduced. In this specification and the like, the impurity concentration is low and the defect level density is low. A low level density is called high purity intrinsic or substantially high purity intrinsic. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, Examples include silicon and silicon dioxide.

[0413] In particular, hydrogen contained in metal oxides reacts with oxygen that bonds with metal atoms to form water. In this case, oxygen vacancies may be formed in the metal oxide. When an oxygen atom is introduced, the oxygen vacancy and hydrogen bond to form V O May form H. V O H is for Donna It functions as a carrier and electrons are generated. It may combine with oxygen to produce electrons, which are carriers. Transistors using metal oxides containing a large amount of silicon tend to be normally on. In addition, hydrogen in metal oxides is easily moved by stresses such as heat and electric fields. If the metal oxide contains a large amount of hydrogen, the reliability of the transistor may be reduced. In one aspect of the invention, V in oxide 530 O Reduce H as much as possible and use high purity intrinsic or It is preferable that V is substantially intrinsic with high purity. O Metal with sufficiently reduced H To obtain oxides, impurities such as water and hydrogen must be removed from the metal oxides (dehydration, This is sometimes referred to as oxidation treatment.) and oxygen deficiency is compensated for by supplying oxygen to the metal oxide. It is important to note that this is sometimes referred to as oxygenation treatment. O Impurities such as H are not enough By using a metal oxide that has been reduced to a low level in the channel formation region of a transistor, stable current can be obtained. It can be given a special characteristic.

[0414] The defect where hydrogen has entered the oxygen vacancy can function as a donor for the metal oxide. However, it is difficult to quantitatively evaluate the defects. Therefore, in this specification, metal As a parameter of the oxide, instead of donor concentration, we use the capacitance assuming a state where no electric field is applied. In other words, the "carrier concentration" described in this specification and the like is This can sometimes be rephrased as "energy concentration."

[0415] Therefore, when a metal oxide is used for the oxide 530, the hydrogen in the metal oxide should be as low as possible. Specifically, in the case of metal oxides, secondary ion mass spectrometry (SIMS: Secondary Ion Mass Spectrometry) The resulting hydrogen concentration is 1×10 20 atoms / cm 3 Less than 1 x 10 19 atoms / cm 3 less than 5 × 10 18 atoms / cm 3 Less than, more Preferably 1 x 10 18 atoms / cm 3 Less than 100%. Impurities such as hydrogen are sufficiently reduced. By using this metal oxide in the channel formation region of a transistor, stable electrical characteristics can be achieved. can be granted.

[0416] In addition, when a metal oxide is used for the oxide 530, the capacitance of the metal oxide in the channel formation region is Rear density is 1 x 10 18 cm -3 Preferably, it is 1×10 or less. 17 cm -3 Not yet It is more preferable that the 16 cm -3 more preferably less than 1×10 13 cm -3 More preferably, it is less than 1×10 12 cm -3 Less than It is more preferable that the lower limit of the carrier concentration of the metal oxide in the channel formation region is There is no particular limitation on the -9 cm -3 It can be said that:

[0417] When a metal oxide is used for the oxide 530, the conductors 542a and 542b When the oxide 530 comes into contact with the conductor 542a, the oxygen in the oxide 530 is transferred to the conductor 542a and the conductor 542b. 2b, and the conductor 542a and the conductor 542b may be oxidized. The oxidization of the conductors 542a and 542b reduces the conductivity of the conductors 542a and 542b. It is highly likely that the oxygen in the oxide 530 will decrease. The conductors 542a and 542b absorb oxygen in the oxide 530 and diffuse to the oxide 530. This can be rephrased as ``to do.''

[0418] Furthermore, oxygen in the oxide 530 diffuses into the conductors 542a and 542b, Between the conductor 542a and the oxide 530b, and between the conductor 542b and the oxide 530b A different layer may be formed between the conductor 542a and the conductor 542b. Since the conductor 54 also contains a large amount of oxygen, it is presumed that the different layer has insulating properties. The three-layer structure of the conductor 542b, the hetero layer, and the oxide 530b is a metal-insulator structure. -It can be considered as a three-layer structure consisting of semiconductors, and is MIS (Metal-Insulator diodes that are mainly of the MIS structure This is sometimes called a joint structure.

[0419] The different layer is formed between the conductor 542a and the oxide 530b and between the conductor 542b and the oxide 530b. For example, the different layers may be a conductor 542a and a conductor 542b and an oxide 542b. 30c, or between the conductor 542a and the conductor 542b and the oxide 530b. and between the conductor 542a and the oxide 530c. be.

[0420] The metal oxide that functions as the channel forming region in the oxide 530 has a band gap It is preferable to use one having a value of 2 eV or more, preferably 2.5 eV or more. The off-state current of a transistor is reduced by using a metal oxide with a wide band gap. It is possible.

[0421] The oxide 530 has an oxide 530a under the oxide 530b, so that the oxide 530a The diffusion of impurities from structures formed below the oxide 530b can be suppressed. In addition, by having the oxide 530c on the oxide 530b, the oxide 530c can be formed. Therefore, the diffusion of impurities from the structure formed above into the oxide 530b can be suppressed. do.

[0422] The oxide 530 has a layered structure made of oxides with different atomic ratios of metal atoms. Specifically, in the metal oxide used for the oxide 530a, the constituent elements are preferably The atomic ratio of element M in the oxide 530b is It is preferable that the atomic ratio of the metal oxide used for the oxide 530a is larger than that of the element M. In the oxide 530b, the atomic ratio of the element M to In is It is preferable that the atomic ratio of element M to In is larger than that of element M. In the metal oxide used, the atomic ratio of In to the element M is It is preferable that the atomic ratio of In to the element M in the metal oxide is larger than that of In. The oxide 530c is a metal oxide that can be used for the oxide 530a or the oxide 530b. can be used.

[0423] The energy of the conduction band minimum of the oxide 530a and the oxide 530c is It is preferable that the energy of the oxide is higher than the energy of the bottom of the conduction band of oxide b. The electron affinity of oxide 530a and oxide 530c is smaller than that of oxide 530b. It is preferable that:

[0424] Here, at the junctions of the oxide 530a, the oxide 530b, and the oxide 530c, The energy level of the lower conduction band edge changes gradually. The energy levels of the conduction band minimum at the junction of 530b and oxide 530c are continuous. In order to achieve this, the oxide 530 The interface between oxide 530a and oxide 530b, and the interface between oxide 530b and oxide 530c are It is preferable to lower the defect level density of the resulting mixed layer.

[0425] Specifically, oxide 530a and oxide 530b, and oxide 530b and oxide 530c are By having a common element other than oxygen (as the main component), a mixed layer with low defect level density is formed. For example, when the oxide 530b is an In-Ga-Zn oxide, the oxide 530a and oxide 530c are In-Ga-Zn oxide, Ga-Zn oxide, oxide Gallium or the like may be used.

[0426] At this time, the main path of the carriers is the oxide 530b. By configuring the oxide 530c as described above, the interface between the oxide 530a and the oxide 530b and the oxide The defect state density at the interface between the substrate 530b and the oxide 530c can be reduced. Therefore, the influence of interface scattering on carrier conduction is reduced, and the transistor 500 has a high On-current can be obtained.

[0427] On the oxide 530b, a conductor 542a is formed, which functions as a source electrode and a drain electrode. The conductors 542a and 542b are provided. Aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, ungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium , beryllium, indium, ruthenium, iridium, strontium, and lanthanum The metal elements mentioned above, or alloys containing the above metal elements, or combinations of the above metal elements It is preferable to use an alloy of tantalum nitride, titanium nitride, tungsten nitride, etc. titanium and aluminum nitrides, tantalum and aluminum nitrides, and titanium oxides Ruthenium, ruthenium nitride, oxides containing strontium and ruthenium, lanthanum and nickel It is preferable to use oxides containing titanium. Nitrides containing tantalum and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide , ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel Oxides are conductive materials that are resistant to oxidation or that maintain conductivity even after absorbing oxygen. Furthermore, metal nitride films such as tantalum nitride have low resistance to hydrogen or oxygen. It is preferable because it has barrier properties.

[0428] In addition, in FIGS. 25A and 25B, the conductor 542a and the conductor 542b are formed as a single layer. However, a laminated structure of two or more layers may be used. For example, a tantalum nitride film and a tungsten film may be used. It is preferable to laminate a titanium film and an aluminum film. Two-layer structure with aluminum film laminated on stainless steel film, copper-magnesium-aluminum alloy Two-layer structure with copper film laminated on gold film, two-layer structure with copper film laminated on titanium film, tungsten A two-layer structure in which a copper film is laminated on the film may also be used.

[0429] Also, a titanium film or titanium nitride film and an aluminum film overlaid on the titanium film or titanium nitride film are used. A three-layer structure in which a titanium film or a copper film is laminated and a titanium film or a titanium nitride film is further formed on top of that. Molybdenum film or molybdenum nitride film and a An aluminum film or a copper film is laminated on top of it, and a molybdenum film or a molybdenum nitride film is further laminated on top of it. There are three-layer structures that form a transparent film. Transparent conductive materials may also be used.

[0430] As shown in FIG. 25A, the conductor 542a (conductor 542b) of the oxide 530 At the interface and its vicinity, a region 543a and a region 543b are formed as low resistance regions. In this case, the region 543a functions as either a source region or a drain region. The region 543b functions as the other of the source region and the drain region. A channel forming region is formed in the region sandwiched between 3a and region 543b.

[0431] By providing the conductor 542a (conductor 542b) so as to be in contact with the oxide 530, The oxygen concentration in the region 543a (region 543b) may decrease. The metal contained in the conductor 542a (conductor 542b) and the oxide 530 are In such a case, a metal compound layer containing the component may be formed in the region 543a (region The carrier density in the region 543a (region 543b) increases, and the region 543a (region 543b) becomes a low resistance region. become.

[0432] The insulator 544 is provided to cover the conductor 542a and the conductor 542b. The insulator 544 prevents oxidation of the oxide 542a and the conductor 542b. 30 and may be provided so as to be in contact with the insulator 524.

[0433] Insulator 544 includes hafnium, aluminum, gallium, yttrium, and zirconium. Smoke, tungsten, titanium, tantalum, nickel, germanium, neodymium, lanthanum Alternatively, a metal oxide containing one or more metals selected from magnesium, etc. may be used. Alternatively, silicon nitride oxide or silicon nitride may be used as the insulator 544. You can be there.

[0434] In particular, the insulator 544 may be an oxide of aluminum or hafnium, or both. Insulators including aluminum oxide, hafnium oxide, aluminum, and hafnium It is preferable to use an oxide containing hafnium (hafnium aluminate). Hafnium aluminate has higher heat resistance than hafnium oxide film. This is preferable because it is difficult to crystallize during the treatment. If b is a material that is resistant to oxidation or does not significantly decrease in conductivity even when it absorbs oxygen, it is an insulating material. The insulator 544 is not an essential component and may be appropriately designed depending on the desired transistor characteristics. stomach.

[0435] By including the insulator 544, impurities such as water and hydrogen contained in the insulator 580 are converted into acids. The oxide 530c is prevented from diffusing into the oxide 530b through the insulator 550. In addition, the excess oxygen contained in the insulator 580 can prevent the conductor 560 from being oxidized. It is possible.

[0436] The insulator 550 functions as a first gate insulating film. It is preferable that the insulator 550 is disposed in contact with the inside (top and side surfaces) of the insulating member 550. Similar to the insulator 524, an insulator containing excess oxygen and releasing oxygen when heated is used. It is preferable to form it using a

[0437] Specifically, silicon oxide having excess oxygen, silicon oxynitride, silicon nitride oxide, Silicon nitride, fluorine-doped silicon oxide, carbon-doped silicon oxide, carbon, and Silicon oxide doped with nitrogen and silicon oxide having vacancies can be used. Silicon oxide and silicon oxynitride are preferred because they are stable to heat.

[0438] An insulator that releases oxygen when heated is used as the insulator 550, and is placed on the top surface of the oxide 530c. By providing the oxide 530b in contact with the insulator 550, the oxide 530c passes through the oxide 530b. In addition, oxygen can be effectively supplied to the channel forming region of the insulator 524. In addition, it is preferable that the concentration of impurities such as water or hydrogen in the insulator 550 is reduced. The thickness of the insulator 550 is preferably 1 nm or more and 20 nm or less.

[0439] In addition, in order to efficiently supply excess oxygen contained in the insulator 550 to the oxide 530, A metal oxide may be provided between the insulating material 550 and the conductor 560. It is preferable to suppress the diffusion of oxygen from the body 550 to the conductor 560. By providing a metal oxide, the diffusion of excess oxygen from the insulator 550 to the conductor 560 is suppressed. In other words, it is possible to suppress the decrease in the amount of excess oxygen supplied to the oxide 530. In addition, oxidation of the conductor 560 due to excess oxygen can be suppressed. Any material that can be used for the insulator 544 may be used.

[0440] Note that the insulator 550 may have a stacked structure similar to the second gate insulating film. As transistors become smaller and more highly integrated, the gate insulating film becomes thinner, which reduces leakage current and other problems. Therefore, the insulator that functions as the gate insulating film is made of high-k material. By using a laminated structure of a thermally stable material and a thin film of a thin film, It is possible to reduce the gate potential during transistor operation. It may have a laminated structure.

[0441] The conductor 560 functioning as the first gate electrode has a two-layer structure in FIGS. 25A and 25B. Although the structure is shown as a single layer structure, it may also be a laminated structure of three or more layers.

[0442] The conductor 560a is a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, or a nitrogen oxide molecule. (N2O, NO, NO2, etc.), conductive material with the function of suppressing the diffusion of impurities such as copper atoms It is preferable to use a material containing oxygen (for example, oxygen atoms, oxygen molecules, etc.). It is preferable to use a conductive material that has the function of suppressing the diffusion of the conductor 56. Oa has the function of suppressing oxygen diffusion, so the oxygen contained in the insulator 550 This can prevent the conductor 560b from being oxidized and the conductivity from decreasing. Examples of conductive materials that have the function of suppressing this include tantalum, tantalum nitride, and ruthenium. It is preferable to use ruthenium, ruthenium oxide, or the like as the conductor 560a. An oxide semiconductor that can be used for the oxide 530 can be used. In that case, the conductor 560 By forming the conductive layer 560b by sputtering, the electrical resistance of the conductive layer 560a is reduced, and the conductive layer 560b is This is called an OC (Oxide Conductor) electrode. can be done.

[0443] The conductor 560b is a conductive material mainly composed of tungsten, copper, or aluminum. In addition, since the conductor 560b also functions as a wiring, It is preferable to use a highly conductive material, such as tungsten, copper, or aluminum. A conductive material containing rubber as a main component can be used. For example, a laminated structure of titanium or titanium nitride and the above conductive material may be used. .

[0444] The insulator 580 is provided on the conductor 542a and the conductor 542b via the insulator 544. Preferably, the insulator 580 has an excess oxygen region. For example, the insulator 58 0, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, fluorine silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen It is preferable that the material contains silicon, silicon oxide having pores, or resin. Silicon nitride and silicon oxynitride are preferred because they are thermally stable. However, silicon oxide with vacancies can easily form excess oxygen regions in later processes. This is preferable because it can

[0445] The insulator 580 preferably has an excess oxygen region. Oxygen is released upon heating. By providing the insulator 580 in contact with the oxide 530c, the oxygen in the insulator 580 is oxidized. The oxide 530 can be efficiently supplied through the insulator 530c. It is preferable that the concentration of impurities such as water or hydrogen in 80 is reduced.

[0446] The opening in the insulator 580 is formed to overlap the region between the conductor 542a and the conductor 542b. As a result, the conductor 560 is inserted through the opening in the insulator 580 and the conductor 542a and the conductor 542b. It is formed so as to be embedded in the region sandwiched between 542b.

[0447] In miniaturizing semiconductor devices, it is required to shorten the gate length. It is necessary to prevent the conductivity of the conductor 60 from decreasing. In this embodiment, the conductive material 560 has a high aspect ratio. The conductor 560 is provided so as to be embedded in the opening of the insulator 580. Even a shape with a high ratio can be formed without causing the conductor 560 to collapse during the process. Cut.

[0448] The insulator 574 is connected to the upper surface of the insulator 580, the upper surface of the conductor 560, and the upper surface of the insulator 550. The insulator 574 is preferably provided in contact with the , insulator 550, and insulator 580 can be provided with excess oxygen regions. Oxygen can be supplied into the oxide 530 from the excess oxygen region.

[0449] For example, the insulator 574 may be hafnium, aluminum, gallium, yttrium, Zirconium, tungsten, titanium, tantalum, nickel, germanium, or magnesium Metal oxides containing one or more metals selected from the group consisting of sodium, .

[0450] In particular, aluminum oxide has a high barrier property and is a thin film of 0.5 nm to 3.0 nm. Therefore, the diffusion of hydrogen and nitrogen can be suppressed even if the sputtering method is used. The aluminum oxide film formed by this method is both an oxygen source and a barrier to impurities such as hydrogen. It can also function as a membrane.

[0451] In addition, it is preferable to provide an insulator 581 that functions as an interlayer film over the insulator 574. The insulator 581, like the insulator 524, has a low impurity concentration such as water or hydrogen. It is preferably reduced.

[0452] In addition, the openings formed in the insulators 581, 574, 580, and 544 Conductor 540a and conductor 540b are placed in the opening. The conductors 540a and 540b are provided facing each other with the conductor 560 in between. It has the same structure as the conductor 546 and the conductor 548 described later.

[0453] An insulator 582 is provided on the insulator 581. The insulator 582 is resistant to oxygen and hydrogen. Therefore, the insulator 582 is preferably made of an insulating material. The insulator 582 may be made of the same material as the insulator 514. For example, aluminum oxide may be used. It is preferable to use metal oxides such as tungsten oxide, hafnium oxide, and tantalum oxide.

[0454] In particular, aluminum oxide is a material that can absorb oxygen and hydrogen, which can cause fluctuations in the electrical characteristics of transistors. Therefore, it has a high blocking effect that prevents impurities such as acid and moisture from passing through the membrane. Aluminum oxide is a material that can absorb impurities such as hydrogen and moisture during and after the transistor manufacturing process. This can prevent impurities from being mixed into the transistor 500. Therefore, the release of oxygen from the oxide constituting the transistor 5 can be suppressed. Suitable for use as a protective film against 00.

[0455] An insulator 586 is provided on the insulator 582. The insulator 586 is The same materials as those of 320 can be used. In addition, these insulators have a relatively low dielectric constant. By using a material with high insulating properties, the parasitic capacitance between wiring can be reduced. The edge 586 can be a silicon oxide film, a silicon oxynitride film, or the like.

[0456] Also, the insulator 520, the insulator 522, the insulator 524, the insulator 544, the insulator 580, the insulator The edge 574, the insulator 581, the insulator 582, and the insulator 586 are provided with the conductor 546 and Conductors 548 and the like are embedded.

[0457] The conductor 546 and the conductor 548 are connected to the capacitor 600, the transistor 500, or the transistor The conductor 546 functions as a plug or wiring that connects to the transistor 300. The conductor 548 can be formed using the same material as the conductor 328 and the conductor 330. Cut.

[0458] After the transistor 500 is formed, an opening is formed to surround the transistor 500. An insulator having high barrier properties against hydrogen or water may be formed so as to cover the opening. By encasing the transistor 500 in the insulator with high barrier properties, moisture, In addition, it is possible to prevent hydrogen from penetrating the transistors 500. The whole may be wrapped in an insulator that has high barrier properties against hydrogen or water. When forming an opening to surround the transistor 500, for example, the insulator 514 or the insulator An opening is formed that reaches the insulator 522, and the above-mentioned barrier is formed so as to contact the insulator 514 or the insulator 522. If a highly flexible insulator is formed, the manufacturing process of the transistor 500 can be performed simultaneously. In addition, examples of insulators with high barrier properties against hydrogen or water include The same material as the insulator 522 may be used.

[0459] Next, a capacitor 600 is provided above the transistor 500. 600 includes a conductor 610, a conductor 620, and an insulator 630.

[0460] Moreover, a conductor 612 may be provided over the conductor 546 and the conductor 548. The conductor 12 functions as a plug or wiring that connects to the transistor 500. The conductor 610 functions as an electrode of the capacitor 600. The body 610 can be formed simultaneously.

[0461] The conductor 612 and the conductor 610 may be made of molybdenum, titanium, tantalum, or tungsten. a metal film containing an element selected from aluminum, copper, chromium, neodymium, and scandium; Or a metal nitride film containing the above elements (tantalum nitride film, titanium nitride film, molybdenum nitride film) Indium tin oxide, tungsten nitride film, etc. can be used. Indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide Indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium Conductive materials such as indium zinc oxide and indium tin oxide doped with silicon oxide are used. It is also possible.

[0462] In FIG. 23, the conductor 612 and the conductor 610 are shown as single-layer structures, but the present invention is not limited to this configuration. For example, a conductive material having a barrier property and a conductive material having a high conductivity may be used. Conductors with barrier properties and high adhesion to highly conductive conductors A thin conductor may be formed.

[0463] The conductor 620 is provided so as to overlap with the conductor 610 with the insulator 630 interposed therebetween. The conductor 620 is made of a conductive material such as a metal material, an alloy material, or a metal oxide material. High-melting-point materials such as tungsten and molybdenum, which have both heat resistance and electrical conductivity, are used. It is preferable to use tungsten, and it is particularly preferable to use tungsten. When forming the structure at the same time as other structures, low-resistance metal materials such as Cu (copper) and Al (aluminum) are used. It is best to use a

[0464] An insulator 650 is provided on the conductor 620 and the insulator 630. The insulator 650 can be formed using the same material as the insulator 320. It may also function as a planarizing film that covers the underlying unevenness.

[0465] By using this structure, a semiconductor device using a transistor having an oxide semiconductor This can suppress fluctuations in electrical characteristics and improve reliability. In semiconductor devices using transistors having compound semiconductors, miniaturization or high integration is being attempted. It is possible.

[0466] <Example of transistor structure> Note that the transistor 500 of the semiconductor device described in this embodiment is not limited to the above structure. The following describes examples of structures that can be used for the transistor 500. The transistors described below are modifications of the transistors described above. Therefore, in the following description, differences will be mainly explained, and the same points may be omitted.

[0467] <<Transistor structure example 1>> A structural example of the transistor 500A will be described with reference to FIGS. 26A to 26C. 26B is a top view of a transistor 500A. 26C is a cross-sectional view of the area indicated by the dashed line W1-W2 in FIG. In the top view of FIG. 26A, some elements are omitted for clarity. There are.

[0468] The transistor 500A shown in FIGS. 26A-26C is the same as the transistor 500A shown in FIG. 500, an insulator 511 functioning as an interlayer film, and a conductor 505 functioning as wiring, It is composed of the following:

[0469] 26A to 26C, the transistor 500A includes an oxide 530c, an insulating The body 550 and the conductor 560 are inserted through the insulator 544 into the opening in the insulator 580. The oxide 530c, the insulator 550, and the conductor 560 are arranged in a conductor. 542a and the conductor 542b.

[0470] The insulator 511 may be silicon oxide, silicon oxynitride, silicon nitride oxide, or aluminum oxide. Aluminum, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3) or (Ba,Sr)TiO3(B Insulators such as PTFE (Teflon) can be used in a single layer or multilayer. For example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, Titanium oxide, tungsten oxide, yttrium oxide, and zirconium oxide may be added. Alternatively, these insulators may be nitrided. Silicon or silicon nitride may also be used in a laminated state.

[0471] For example, the insulator 511 prevents impurities such as water or hydrogen from entering the transistor 500 from the substrate side. It is preferable that the insulating film functions as a barrier film to prevent the inclusion of A. 511 has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms. It is preferable to use an insulating material that is resistant to the penetration of the above impurities. For example, it has a function of suppressing the diffusion of at least one of oxygen atoms, oxygen molecules, etc. (see above). It is preferable to use an insulating material that is difficult for oxygen to permeate. Aluminum oxide or silicon nitride may be used as the material of the electrode 1. Impurities such as water are prevented from diffusing from the substrate side to the transistor 500A side by the insulator 511. It can be suppressed.

[0472] For example, the insulator 512 preferably has a lower dielectric constant than the insulator 511. By using a low-cost material for the interlayer film, the parasitic capacitance occurring between wirings can be reduced.

[0473] The conductor 505 is formed so as to be embedded in the insulator 512. The height of the upper surface of the conductor 505 can be made to be approximately the same as the height of the upper surface of the insulator 512. Although a single layer structure is shown, the present invention is not limited to this. For example, The conductor 505 may have a multilayer structure of two or more layers. It is preferable to use a conductive material having high conductivity, which is mainly composed of silicon, copper, or aluminum. stomach.

[0474] The insulators 514 and 516 are interlayer films, similar to the insulators 511 and 512. For example, the insulator 514 functions as a barrier to prevent impurities such as water or hydrogen from traversing the substrate side. It is preferable that the film functions as a barrier film that prevents the metal from being mixed into the transistor 500A. Due to the structure, impurities such as hydrogen and water can enter the transistor 500 from the substrate side rather than the insulator 514. In addition, for example, the insulator 516 can prevent the insulator 51 from diffusing to the side A. It is preferable that the dielectric constant is lower than that of 4. By using a material with a low dielectric constant as the interlayer film, This can reduce the parasitic capacitance that occurs in the

[0475] Furthermore, the insulator 522 preferably has a barrier property. By having such a structure, impurities such as hydrogen can be prevented from being transferred from the periphery of the transistor 500A to the transistor 500A. It functions as a layer that suppresses the inclusion of impurities.

[0476] The oxide 530c is formed in the opening of the insulator 580 through the insulator 544. When the insulator 544 has a barrier property, the insulating material 544 is preferably provided as a barrier material. This can prevent impurities from diffusing into the oxide 530.

[0477] A barrier layer may be provided over the conductor 542a and the conductor 542b. It is preferable to use a material that has a barrier property against oxygen or hydrogen. Therefore, when the insulator 544 is formed, the conductors 542a and 542b are oxidized. This can suppress the above.

[0478] The barrier layer may be made of, for example, a metal oxide, particularly aluminum oxide, Using insulating films such as hafnium oxide and gallium oxide that have barrier properties against oxygen and hydrogen It is also preferable to use silicon nitride formed by the CVD method.

[0479] The barrier layer widens the range of material choices for the conductor 542a and the conductor 542b. For example, the conductor 542a and the conductor 542b may be made of tungsten or aluminum. Materials with low oxidation resistance but high conductivity, such as aluminum, can be used. For example, a conductor that is easy to form or process can be used.

[0480] The insulator 550 functions as a first gate insulating film. The oxide 530c and the insulator 544 are provided in the opening formed in the preferable.

[0481] As for the material of the conductor 540a and the conductor 540b, similarly to the conductor 503, Conductive materials such as metal materials, alloy materials, metal nitride materials, or metal oxide materials are deposited in a single layer or For example, tungsten and molybdenum, which have both heat resistance and electrical conductivity, can be used. It is preferable to use a high melting point material such as butanol, or a low resistance material such as aluminum or copper. It is preferable to form the wiring from a conductive material. By using a low-resistance conductive material, the wiring resistance can be reduced. It is possible.

[0482] For example, the conductor 540a and the conductor 540b may be, for example, hydrogen and oxygen. The compound of tantalum nitride, which is a conductor with barrier properties, and tungsten, which has high conductivity, By using a layered structure, the conductivity of the wiring is maintained while preventing the diffusion of impurities from the outside. It can be suppressed.

[0483] By having the above structure, a transistor including an oxide semiconductor and having a large on-state current can be provided. Alternatively, a semiconductor device including an oxide semiconductor having a low off-state current can be provided. It is possible to provide a semiconductor device having a transistor, or to suppress fluctuations in electrical characteristics. As a result, it is possible to provide a semiconductor device having stable electrical characteristics and improved reliability. Cut.

[0484] <<Transistor structure example 2>> A structural example of the transistor 500B will be described with reference to FIGS. 27A to 27C. 27B is a top view of a transistor 500B. 27C is a cross-sectional view of the area indicated by the dashed line W1-W2 in FIG. In the top view of FIG. 27A, some elements are omitted for clarity. There are.

[0485] The transistor 500B is a modified example of the transistor 500A. To avoid confusion, differences from transistor 500A will be mainly described.

[0486] The transistor 500B includes a conductor 542a (conductor 542b), an oxide 530c, and The insulator 550 and the conductor 560 overlap each other. It is possible to provide a transistor with a high on-state current. can be provided.

[0487] The conductor 560 functioning as the first gate electrode includes the conductor 560a and the conductor 560b. The conductor 560a has a conductor 560b on the conductor 503a. The conductor 560a is a hydrogen atom, similar to the conductor 503a. Conductive materials that have the function of suppressing the diffusion of impurities such as hydrogen molecules, water molecules, and copper atoms are used. It is preferable that the oxygen (for example, at least one of an oxygen atom, an oxygen molecule, etc.) It is preferable to use a conductive material that has the function of suppressing diffusion.

[0488] The conductor 560a has a function of suppressing the diffusion of oxygen, and therefore the material of the conductor 560b In other words, by having the conductor 560a, the conductor 560 The oxidation of b is suppressed, and the decrease in electrical conductivity can be prevented.

[0489] In addition, the top and side surfaces of the conductor 560, the side surface of the insulator 550, and the side surface of the oxide 530c It is preferable to provide an insulator 544 so as to cover the above.

[0490] By providing the insulator 544, oxidation of the conductor 560 can be suppressed. By providing the insulator 544, impurities such as water and hydrogen contained in the insulator 580 can be prevented from being transferred to the transistor. This can prevent the light from diffusing to the star 500B.

[0491] The contact plug of the transistor 500B is connected to the contact plug of the transistor 500A. The transistor 500B has a different structure from the contact plug. Between the conductor 546a (conductor 546b) and the insulator 580, there is provided a barrier An insulator 576a (insulator 576b) is disposed. ) is provided, the oxygen in the insulator 580 reacts with the conductor 546, and the conductor 546 is oxidized. This can prevent this from happening.

[0492] In addition, by providing an insulator 576a (insulator 576b) having a barrier property, plugs and The range of materials that can be selected for the conductors used for wiring can be expanded. For example, the conductor 546a (Conductor 546b) is made of a metal material that has the property of absorbing oxygen and is highly conductive. By using tungsten, a semiconductor device with low power consumption can be provided. Alternatively, a material having low oxidation resistance but high conductivity, such as aluminum, can be used. Furthermore, for example, a conductor that is easy to form a film or process can be used.

[0493] <<Transistor structure example 3>> A structural example of the transistor 500C will be described with reference to FIGS. 28A to 28C. 28B is a top view of a transistor 500C. 28C is a cross-sectional view of the area indicated by the dashed line W1-W2 in FIG. In the top view of FIG. 28A, some elements are omitted for clarity. There are.

[0494] Transistor 500C is a modified version of transistor 500A. To avoid confusion, differences from transistor 500A will be mainly described.

[0495] Transistor 500C shown in FIGS. 28A to 28C includes conductor 542a and oxide 530. conductor 547a is disposed between conductor 542b and oxide 530b, and conductor 547b is disposed between conductor 542b and oxide 530b. 7b is arranged. Here, the conductor 542a (conductor 542b) is arranged between the conductor 547a (conductor 547b) and the side surface of the conductor 560 side, and the oxide 530b The conductor 547a and the conductor 547b have a region that contacts the upper surface. The conductors that can be used for the conductors 42a and 542b may be used. The thickness of the conductive material 547a and the conductive material 547b is at least the same as that of the conductive material 542a and the conductive material 544a. Preferably it is thicker than 2b.

[0496] The transistor 500C shown in FIGS. 28A to 28C has the above-described configuration. Therefore, the conductor 542a and the conductor 542b are connected to the conductor 542a by the transistor 500A. 60. Alternatively, the end of the conductor 542a and the end of the conductor 542b may be , conductor 560 can be overlapped. This allows the transistor 500C to be essentially The channel length can be shortened, and the on-current and frequency characteristics can be improved.

[0497] In addition, the conductor 547a (conductor 547b) overlaps with the conductor 542a (conductor 542b). By adopting such a configuration, the conductor 540a (the conductor In the etching to form the opening in which the conductor 547a (conductor 540b) is embedded, 47b) acts as a stopper to prevent over-etching of oxide 530b. It is possible.

[0498] 28, the transistor 500C has an insulator 545 in contact with the insulator 544. The insulator 544 is configured to be a material that can absorb impurities such as water or hydrogen, and excess A barrier insulating film that prevents oxygen from entering the transistor 500C from the insulator 580 side. The insulator 545 preferably functions as the insulator 544. As the insulator 544, for example, aluminum nitride can be used. titanium nitride, titanium nitride, silicon nitride, silicon oxide nitride, etc. Alternatively, nitride insulators may be used.

[0499] 28 differs from the transistor 500A shown in FIG. The conductor 503 has a single layer structure. In this case, the patterned conductor 50...

Claims

[Claim 1] a first circuit; the first circuit includes a first transistor, a second transistor, and a first capacitance element; the first transistor has a first gate and a second gate; a first gate of the first transistor electrically connected to a first input wiring; a second gate of the first transistor is electrically connected to a first terminal of the second transistor and a first terminal of the first capacitive element; The first circuit is a function of holding a first potential of a first terminal of the first capacitance element and a second gate of the first transistor by turning off the second transistor; a function of turning the first transistor into one of an on state and an off state in response to the first potential and a second potential input to the first input wiring; the first potential is an analog value; When the first transistor is in an on state, an analog current flows through the first transistor.

Images