Information processing device and information processing method

Abstract

To provide an information processing device or the like capable of operating a program correctly.SOLUTION: An information processing device has: a control unit that writes a program read from an external storage unit into an internal storage unit and executes the program read from the internal storage unit; a write control unit that calculates a parity value for an instruction or data of the program read from the external storage unit, and writes the instruction or the data and the parity value into the internal storage unit; a read control unit that determines whether there is an error in the instruction or the data of the program on the basis of the parity value of the instruction or the data read from the internal storage unit; and a transfer unit that transfers the instruction or the data of the program re-read from the external storage unit when there is the error.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to an information processing device and an information processing method. [Background technology]

[0002] Conventional information processing devices have an integrated circuit (IC) and an external read-only memory (ROM) that stores information such as programs to be executed by the IC. Typically, the RAM inside the IC can access programs faster than the external ROM, enabling high-speed program processing.

[0003] In general, if a single bit in a program stored in RAM is inverted for some reason, such as a bit inversion, the program may not run properly. In particular, in systems that require stable operation, such as plant control systems, operational abnormalities caused by bit inversion can have a major impact.

[0004] Possible causes of bit flips include, for example, hard errors that result in permanent failures and transient soft errors. Hard errors are caused by physical factors such as aging or failures due to overvoltage, and because they are physical failures, they cannot be repaired by resetting the power supply, etc. In contrast, soft errors are phenomena caused by external factors such as neutron rays contained in radiation or electromagnetic noise. Therefore, in the case of soft errors, since the hardware itself is sound, soft errors can be repaired by resetting the power supply, etc., to rewrite the correct value.

[0005] Furthermore, in recent years, there has been a demand for miniaturization and power saving of semiconductors in order to improve device performance and save energy. However, as a result of this miniaturization and power saving, the resistance of semiconductors to external influences such as radiation and electromagnetic noise decreases, resulting in an increased incidence of soft errors. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-18414 Summary of the Invention [Problem to be solved by the invention]

[0007] Therefore, in the case of conventional information processing devices, there is a demand for an information processing device that can resolve a soft error and continue normal program operation even when a soft error occurs in the program.

[0008] In one aspect, an object is to provide an information processing device or the like that can continue normal program operation. [Means for solving the problem]

[0009] In one aspect, the information processing device disclosed herein includes a control unit that writes a program read from an external storage unit to an internal storage unit and executes the program read from the internal storage unit. The information processing device includes a write control unit that calculates a parity value of instructions or data of the program read from the external storage unit and writes the instructions or data and the parity value to the internal storage unit. The information processing device includes a read control unit that determines whether or not there is an error in the instructions or data of the program based on the parity value of the instructions or data of the program read from the internal storage unit. Furthermore, the information processing device includes a transfer unit that, if there is an error, transfers instructions or data of the program read again from the external storage unit to the control unit and the write control unit. [Effects of the Invention]

[0010] According to one aspect, normal program operation can be continued. [Brief explanation of the drawings]

[0011] [Figure 1] FIG. 1 is a block diagram showing an example of an information processing apparatus according to this embodiment. [Figure 2] FIG. 2 is a block diagram illustrating an example of a storage control unit. [Figure 3] FIG. 3 is a flowchart showing an example of the processing operation of the information processing device related to the write processing. [Figure 4] FIG. 4 is a flowchart showing an example of the processing operation of the information processing device related to the execution process. [Figure 5] FIG. 5 is a block diagram showing an example of an information processing apparatus of the comparative example. DETAILED DESCRIPTION OF THE INVENTION

[0012] <Comparative Example> Fig. 5 is a block diagram showing an example of an information processing device 100 of a comparative example. The information processing device 100 shown in Fig. 5 has an IC (Integrated Circuit) 101 and an external ROM (Read Only Memory) 102. The external ROM 102 is an external storage unit that stores information such as programs to be executed by the IC 101. The IC 101 is a control unit that controls the entire information processing device 100. The IC 101 reads out programs stored in the external ROM 102 and executes the read out programs as functions.

[0013] The IC 101 has an external bus I / F (Interface) 111, a RAM (Random Access Memory) 112, a CPU (Central Processing Unit) 113, and an internal bus 114. The external bus I / F 111 is an input / output interface that connects to the external ROM 102. The RAM 112 is an internal storage unit that temporarily stores programs read from the external ROM 102. The CPU 113 controls the entire IC 101. The CPU 113 writes programs read from the external ROM 102 via the external bus I / F 111 to the RAM 112. The CPU 113 reads program instructions (data) from the RAM 112 and executes the read instructions (data). For ease of explanation, the program instructions (data) will be taken to mean the program instructions or data. The internal bus 114 is a bus line that connects the external bus I / F 111, the RAM 112, and the CPU 113, and transmits and receives information such as data and programs between the external bus I / F 111, the RAM 112, and the CPU 113.

[0014] For example, when the information processing device 100 is powered on, the CPU 113 reads the program stored in the external ROM 102, transfers the read program to the RAM 112, and writes the program to the RAM 112. Then, for example, when the program is started, the CPU 113 reads instructions (data) of the program written in the RAM 112 and executes the read instructions (data).

[0015] In the conventional information processing device 100, the internal RAM 112 can normally access a program faster than the external ROM 102, thereby realizing high-speed program processing.

[0016] As a countermeasure against soft errors in the information processing device 100, for example, a method of providing the information processing device with an error detection and correction function using ECC (Error Correction Code) can be considered.

[0017] However, while ECC increases the number of errors that can be detected and corrected by lengthening the error-correcting code, it also increases the amount of calculation required to calculate and verify the code, and the extra capacity and bandwidth (overhead) required for the error-correcting code during recording and transmission. As a result, information processing devices equipped with ECC require memory to store the error-correcting code and control circuits for error detection and correction. In particular, increasing the memory capacity for storing the error-correcting code requires an increase in the memory capacity of the RAM, which increases the implementation area and the circuit scale of the information processing device.

[0018] Furthermore, ECC correction does not correct memory contents, but only output data. Therefore, in plant control systems that cannot be restarted for long periods of time, errors may accumulate and corrections may not be possible if multiple errors (bit flips) occur in the read program.

[0019] Therefore, there is a demand for an information processing device that can resolve soft errors and continue normal program operation even when soft errors occur in a program, without incorporating an ECC.

[0020] Hereinafter, embodiments of the information processing device and the like disclosed in the present application will be described in detail with reference to the drawings. Note that the disclosed technology is not limited to these embodiments. Furthermore, each embodiment described below may be modified as appropriate within the scope of not causing any contradiction.

[0021] <Example> FIG. 1 is a block diagram showing an example of an information processing device 1 according to this embodiment. The information processing device 1 shown in FIG. 1 includes an integrated circuit (IC) 2 and an external read-only memory (ROM) 3. The information processing device 1 is, for example, a distributed control system (DCS) or safety instrumented system (SIS) of a plant, other factory automation (FA) devices, or field devices such as a pressure transmitter, a temperature transmitter, a multivariable transmitter, or a flow meter. The IC 2 is, for example, an integrated circuit mounted inside the DCS, the SIS, the FA device, or the field device. The IC 2 controls the entire information processing device 1. The external ROM 3 is an external storage unit in which programs executed by the IC 2 are stored.

[0022] The IC2 has an external bus I / F 4, a memory control unit 5, a CPU (Central Processing Unit) 6, a first bus 7, and a second bus 8. The external bus I / F 4 is an input / output interface that connects to an external ROM 3. The memory control unit 5 incorporates a RAM (Random Access Memory) 12, which is an internal memory unit, and controls the RAM 12. The CPU 6 is a control unit that controls the entire IC2.

[0023] The first bus 7 is an internal bus that connects, for example, the CPU 6 and the external bus I / F 4 or the CPU 6 and the storage control unit 5, and transmits and receives various information such as programs and data. The second bus 8 is an internal bus that connects, for example, the external bus I / F 4 and the storage control unit 5, and transmits and receives various information such as programs and data.

[0024] <Configuration of the memory control unit> FIG. 2 is a block diagram showing an example of the storage control unit 5. The storage control unit 5 shown in FIG. 2 includes a write control unit 11, a RAM 12, a read control unit 13, and a transfer unit 14. The write control unit 11 controls writing to the RAM 12. The write control unit 11 sequentially writes program instructions or data read from the external ROM 3 to the RAM 12. When sequentially writing the program instructions or data read from the external ROM 3 to the RAM 12, the write control unit 11 calculates a first parity value of the program instructions (data), and associates the calculated first parity value with the instructions (data) and writes them sequentially to the RAM 12. The first parity value is, for example, an even parity value or an odd parity value.

[0025] The read control unit 13 controls reading from the RAM 12. When reading an instruction (data) and a first parity value from the RAM 12, the read control unit 13 calculates a second parity value for the read instruction (data). The second parity value is, for example, an even parity value or an odd parity value. The read control unit 13 compares the calculated second parity value with the first parity value read from the RAM 12 and determines whether the first parity value and the second parity value match. The read control unit 13 determines whether a parity error exists in the instruction (data) based on the determination result of whether the first parity value and the second parity value match. A parity error is, for example, a bit inversion due to a soft error or the like. If the first parity value and the second parity value match, the read control unit 13 determines that the instruction (data) read from the RAM 12 does not have a parity error. If the first parity value and the second parity value do not match, the read control unit 13 determines that the instruction (data) read from the RAM 12 has a parity error.

[0026] The transfer unit 14 transfers the instruction (data) reread from the external ROM 3 via the second bus 8 to the CPU 6 if a parity error in the instruction (data) exists, and transfers the instruction (data) read from the RAM 12 to the CPU 6 if no parity error in the instruction (data) exists. The transfer unit 14 has an output unit 15 and a reload unit 16. The output unit 15 is a multiplexer that switches between transferring the instruction (data) from the external ROM 3 transferred from the reload unit 16 and the instruction (data) from the RAM 12 transferred from the read control unit 13 to the first bus 7. If a parity error in the instruction (data) exists, the output unit 15 transfers the instruction (data) from the external ROM 3 transferred from the reload unit 16 to the first bus 7. If no parity error in the instruction (data) exists, the output unit 15 transfers the instruction (data) from the RAM 12 transferred from the read control unit 13 to the first bus 7.

[0027] If there is a parity error in the command (data), the reload unit 16 rereads the command (data) from the external ROM 3 via the second bus 8. The reload unit 16 transfers the command (data) reread from the external ROM 3 to the output unit 15, and also transfers the reread command (data) to the write control unit 11.

[0028] In addition, if there is no parity error in the command (data), the read control unit 13 transfers the command (data) to the output unit 15 in the transfer unit 14 and controls the output unit 15 to switch so as to connect between the read control unit 13 and the first bus 7.

[0029] If there is a parity error in the command (data), the read control unit 13 outputs a control signal to the reload unit 16 to read the command (data) again from the external ROM 3, and also controls the output unit 15 to switch so as to connect between the reload unit 16 and the first bus 7. Then, the reload unit 16 transfers the command (data) read again from the external ROM 3 to the output unit 15 and the write control unit 11 via the second bus 8.

[0030] As described above, if there is a parity error in the instruction (data), the output unit 15 transfers the instruction (data) reread from the reload unit 16 to the CPU 6 via the first bus 7. The CPU 6 then receives the instruction (data) transferred from the output unit 15 via the first bus 7, and if it receives an instruction, it executes the instruction, and if it receives data, it uses the data.

[0031] Furthermore, the write control unit 11 calculates a first parity value of the command (data) transferred from the reload unit 16, and writes the command (data) and the first parity value into the RAM 12.

[0032] <Write process> 3 is a flow chart showing an example of the processing operation of the information processing device 1 related to the write process. The information processing device 1 determines whether or not the timing for transfer from the external ROM 3 of the information processing device 1 to the RAM 12 has been detected (step S11). If the timing for transfer from the external ROM 3 to the RAM 12 has been detected (step S11: Yes), the information processing device 1 reads program instructions (data) from the external ROM 3 (step S12). The external bus I / F 4 in the information processing device 1 transfers the instructions (data) read from the external ROM 3 to the write control unit 11 in the storage control unit 5 via the first bus 7 (step S13).

[0033] The write control unit 11 calculates a first parity value of the instruction (data) transferred via the first bus 7 (step S14). The write control unit 11 writes the transferred instruction (data) and the calculated parity value to the RAM 12 in the storage control unit 5 (step S15). Furthermore, after writing the transferred instruction (data) to the RAM 12, the write control unit 11 determines whether the written instruction (data) is the final instruction (final data) of the program (step S16). Note that the final instruction is, for example, the last instruction of multiple instructions in the program written to the RAM 12. The final data is, for example, the last data of multiple data in the program written to the RAM 12.

[0034] If the written command (data) is the final command (final data) of the program (step S16: Yes), the write control unit 11 determines that there are no remaining commands (data) in the program, and ends the processing operation shown in Fig. 3. If the written command (data) is not the final command (final data) of the program (step S16: No), the write control unit 11 determines that there are remaining commands (data) in the program, and proceeds to processing in step S12, where the command (data) is read from the external ROM 3.

[0035] When the information processing device 1 does not detect the timing of transfer from the external ROM 3 of the information processing device 1 to the RAM 12 (step S11: No), the information processing device 1 ends the processing operation shown in FIG.

[0036] When the storage control unit 5 in the information processing device 1 detects the timing of transfer from the external ROM 3 to the RAM 12, it calculates a first parity value of the instruction (data) read from the external ROM 3 via the first bus 7, and writes the calculated first parity value and the instruction (data) to the RAM 12. As a result, the information processing device 1 can prepare to achieve high-speed access to the program when the program is started.

[0037] <Execution process> 4 is a flow diagram showing an example of the processing operation of the information processing device 1 related to execution processing. In FIG. 4, the information processing device 1 determines whether or not program startup has been detected (step S21). If program startup has been detected (step S21: Yes), the read control unit 13 in the information processing device 1 reads program instructions (data) and a first parity value from the RAM 12 (step S22).

[0038] The read control unit 13 calculates a second parity value of the instruction (data) read from the RAM 12 (step S23). The read control unit 13 compares the first parity value read in step S22 with the second parity value calculated in step S23 (step S24). The read control unit 13 determines whether the first parity value and the second parity value match (step S25).

[0039] If the first parity value and the second parity value match (step S25: Yes), the read control unit 13 determines that there is no parity error in the read instruction (data) (step S26).Then, the read control unit 13 controls the output unit 15 to switch and transfer the instruction (data) read from the RAM 12 to the first bus 7 (step S27).

[0040] The output unit 15 transfers the instruction (data) read from the read control unit 13 to the CPU 6 via the first bus 7 (step S28). Furthermore, if an instruction was transferred in step S28, the CPU 6 executes the instruction read from the RAM 12, or if data was transferred in step S28, the CPU 6 uses the data read from the RAM 12 (step S29). Then, the CPU 6 determines whether the program has ended (step S40). If the program has not ended (step S40: No), the CPU 6 returns to the processing of step S22 to read further program instructions (data) and the first parity value within the program.

[0041] Furthermore, when the CPU 6 has finished the program (step S40: Yes), it ends the processing operation shown in Fig. 4. As a result, the CPU 6 executes all the instructions or uses all the data in the program read from the RAM 12, thereby realizing high-speed access to the program.

[0042] If the first parity value and the second parity value do not match (step S25: No), the read control unit 13 determines that there is a parity error in the instruction (data) read from the RAM 12 (step S30). If the reload unit 16 determines that there is a parity error, it reads the instruction (data) again from the external ROM 3 via the second bus 8 (step S31).

[0043] Furthermore, if the read control unit 13 determines in step S30 that a parity error exists, it controls the output unit 15 to switch over to the first bus 7 and transfer the instructions (data) reread from the reload unit 16 (step S32). Furthermore, the output unit 15 transfers the instructions (data) reread from the external ROM 3 to the CPU 6 via the first bus 7 (step S33). If the instructions reread from the reload unit 16 are transferred in step S33, the CPU 6 executes the instructions read from the external ROM 3. Alternatively, if data are transferred in step S33, the CPU 6 uses the data read from the external ROM 3 (step S34). Then, the CPU 6 proceeds to step S40, where it determines whether the program has ended. As a result, even if an error exists in the instructions or data in the program stored in the RAM 12, the CPU 6 can execute the program normally by using the correct instructions or data read from the external ROM 3.

[0044] Furthermore, if the reload unit 16 determines in step S30 that a parity error has occurred, it transfers the reread instructions (data) to the write control unit 11 while transferring the reread instructions (data) to the CPU 6 via the first bus 7 (step S35). Furthermore, the write control unit 11 calculates a first parity value for the instructions (data) transferred in step S35 (step S36), writes the transferred instructions (data) and the calculated first parity value to the RAM 12 (step S37), and proceeds to the process of step S40 in which it is determined whether the program has ended. As a result, the information processing device 1 can prepare to achieve high-speed access the next time instructions (data) are read.

[0045] If the read control unit 13 does not detect the program start (step S21: No), the read control unit 13 ends the processing operation shown in FIG.

[0046] <Effects of the Example> When a parity error is found in the program instructions (data) stored in RAM 12, which has been transferred from external ROM 3, the information processing device 1 rereads normal instructions (data) from external ROM 3. The information processing device 1 then causes the CPU 6 to execute the reread normal instructions (data). As a result, normal program operation can be continued even when a parity error is found in the instructions (data) stored in RAM 12. Moreover, bit inversions caused by soft errors can be repaired and normal program operation can be continued, while suppressing the circuit implementation area by not incorporating ECC and reducing the scale of circuits required for soft error detection and correction.

[0047] The information processing device 1 determines whether or not there is a parity error in the instruction (data) based on the parity value of the instruction (data) read from the RAM 12, and if there is a parity error, transfers the instruction (data) read again from the external ROM 3 to the CPU 6. As a result, even if a soft error occurs, normal program operation can be continued.

[0048] Furthermore, if there is no parity error, the information processing device 1 transfers the instruction (data) read from the RAM 12 to the CPU 6. As a result, high-speed access to the program can be achieved.

[0049] If a parity error occurs, the reload unit 16 reads the instructions (data) again from the external ROM 3 and transfers the reread instructions (data) to the output unit 15 and the write control unit 11. Furthermore, if a parity error occurs, the output unit 15 transfers the instructions (data) reread by the reload unit 16 to the CPU 6, and if no parity error occurs, it transfers the instructions (data) read from the RAM 12 to the CPU 6. As a result, even if a soft error occurs, normal program operation can be continued.

[0050] The information processing device 1 has a first bus 7 connecting the transfer unit 14 and the CPU 6, and a second bus 8 connecting the external ROM 3 and the transfer unit 14. If a parity error occurs, the reload unit 16 rereads instructions (data) from the external ROM 3 via the second bus 8. If a parity error occurs, the output unit 15 transfers the instructions (data) reread by the reload unit 16 to the CPU 6 via the first bus 7, and if no parity error occurs, the output unit 15 transfers the instructions (data) read from the RAM 12 to the CPU 6 via the first bus 7. As a result, even if the CPU 6 occupies the first bus 7, it can read instructions (data) from the external ROM 3 using the second bus 8.

[0051] The output unit 15 transfers the instructions (data) of the program reread by the reload unit 16 to the CPU 6 via the first bus 7. The reload unit 16 also transfers the instructions (data) of the program reread to the write control unit 11. Furthermore, the first write control unit 11 calculates a first parity value of the program reread by the reload unit 16. Furthermore, the write control unit 11 writes the reread instructions (data) and the calculated first parity value to the RAM 12. As a result, the information processing device 1 can prepare to achieve high-speed access for the next read of instructions (data).

[0052] In the illustrated example, when a parity error occurs, the reload unit 16 rereads the instruction (data) from the external ROM 3 via the second bus 8 and transfers the instruction (data) to the CPU 6 and the write control unit 11 via the first bus 7. However, this is not limiting. When a parity error occurs, the reload unit 16 rereads the instruction (data) from the external ROM 3 via the second bus 8 and transfers the reread instruction (data) to the write control unit 11. The write control unit 11 then executes a write process to write the first parity value of the instruction (data) and the instruction (data) to the RAM 12. The read control unit 13 then executes the process of step S22 shown in FIG. 4. As a result, normal program operation can be continued even when a soft error occurs.

[0053] In the information processing device 1 of this embodiment, in addition to the first bus 7, a second bus 8 connected to the reload unit 16 for error correction is used, so that even if the CPU 6 occupies the first bus 7, instructions (data) can be read from the external ROM 3 via the second bus 8. However, the number of buses is not limited to two, and for example, the first bus 7 may be connected to the reload unit 16 even if the second bus 8 is not provided.

[0054] In this case, if the information processing device 1 detects an error in the program instructions (data) based on the parity value while the CPU 6 is reading the instructions (data) using the first bus 7, the information processing device 1 releases the first bus 7. After releasing the first bus 7, the write control unit 11 uses the first bus 7 to write the instructions (data) reread from the external ROM 3 by the reload unit 16 to the RAM 12. After completing the writing of the instructions (data), the read control unit 13 releases the first bus 7 and reads the instructions (data) from the RAM 12. The output unit 15 then transfers the read instructions (data) to the CPU 6 using the first bus 7. The CPU 6 then executes the transferred instructions or uses the transferred data. As a result, the information processing device 1 can continue to operate normally even if the second bus 8 is not provided and only the first bus 7 is used.

[0055] For ease of explanation, IC2 may be replaced by, for example, an ASIC / FPGA (Application Specific Integrated Circuit / Field Programmable Gate Array), and modifications can be made as appropriate.

[0056] Furthermore, all or any part of the processing functions performed by each device may be realized by a CPU and a program analyzed and executed by the CPU, or may be realized as hardware using wired logic. [Explanation of symbols]

[0057] 1. Information processing equipment 3 External ROM 5 Memory control unit 6 CPU 7. First Bus 8. Second Bus 11 Write control section 12 RAM 13 Readout control section 14 Transfer Unit 15 Output section 16 Reloading Department

Claims

1. An information processing device having a control unit that writes a program read from an external storage unit into an internal storage unit and executes the program read from the internal storage unit, a write control unit that calculates a parity value of an instruction or data of a program read from the external storage unit, and writes the instruction or data and the parity value into the internal storage unit; a read control unit that determines whether or not there is an error in the instruction or data of the program based on a parity value of the instruction or data of the program read from the internal storage unit; a transfer unit that transfers, when the error occurs, the instructions or data of the program that have been reread from the external storage unit to the control unit and the write control unit; An information processing device comprising:

2. The transfer unit a reload unit that re-reads instructions or data of the program from the external storage unit when the error occurs; an output unit that transfers the instructions or data of the program reloaded by the reload unit to the control unit when the error is detected, and transfers the instructions or data of the program read from the internal storage unit to the control unit when the error is not detected; 2. The information processing apparatus according to claim 1, further comprising:

3. a first bus connecting the transfer unit and the control unit; a second bus connecting the external storage unit and the transfer unit; The reloading unit When the error occurs, the instructions or data of the program are read again from the external storage unit via the second bus, and the reread instructions or data of the program are transferred to the output unit and the write control unit, The output unit An information processing device as described in claim 2, characterized in that if there is an error, the instructions or data of the program re-read by the reload unit are transferred to the control unit via the first bus, and if there is no error, the instructions or data of the program read from the internal memory unit are transferred to the control unit via the first bus.

4. The write control unit 4. An information processing device according to claim 2 or 3, characterized in that the reload unit calculates a parity value of the instructions or data of the program that have been reread, and writes the instructions or data of the program that have been reread and the calculated parity value to the internal memory unit.

5. An information processing device having a control unit that writes a program read from an external storage unit into an internal storage unit and executes the program read from the internal storage unit, calculating a parity value of an instruction or data of the program read from the external storage unit, and writing the instruction or data and the parity value into the internal storage unit; determining whether or not there is an error in the instruction or data of the program based on the parity value of the instruction or data of the program read from the internal storage unit; If the error occurs, the instructions or data of the program read again from the external storage unit are transferred to the control unit. An information processing method characterized by executing processing.

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