Display device

Abstract

To provide a display device capable of improving color viewing angle characteristics.SOLUTION: One embodiment of the disclosure may provide a display device comprising: a subpixel including a first area overlapping a light emitting layer and a second area not overlapping the light emitting layer; a main emission area disposed in the first area; and a reflected light area disposed to surround an outer periphery of the main emission area in the second area and having a protruding portion protruding outward on one side.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] An embodiment of the present disclosure relates to a display device capable of improving color viewing angle characteristics. [Background technology]

[0002] As we enter the information age, the field of displays that visually represent electrical information signals has rapidly developed, and accordingly, various display devices with excellent performance such as thinness, light weight, and low power consumption have been developed.

[0003] Specific examples of display devices include a liquid crystal display (LCD), a field emission display (FED), and an organic light emitting display (OLED).

[0004] Meanwhile, display devices can display images by arranging red, green, and blue sub-pixels in a matrix. These sub-pixels output different wavelengths depending on the color, so there is a difference in the amount of brightness reduction depending on the viewing angle. This can cause problems such as a decrease in color viewing angle (VACS) characteristics as one moves from the front to the side. Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the present disclosure is to provide a display device with an improved color viewing angle by controlling the distance between the opening of the bank layer and the reflective electrode according to the wavelength of each subpixel.

[0006] Another object of the present disclosure is to provide a display device that can improve the color viewing angle without reducing the aperture ratio.

[0007] Furthermore, an object of the present disclosure is to provide a display device in which light traveling from the light-emitting layer to the side is reflected again by the reflective electrode and emitted to the outside, thereby improving brightness.

[0008] Another object of the present disclosure is to provide a display device that can be used with low power consumption by improving light extraction efficiency using a reflective electrode. [Means for solving the problem]

[0009] An embodiment of the present disclosure may relate to a display device including a sub-pixel including a first region overlapping an emission layer and a second region not overlapping the emission layer, a main emission region disposed in the first region, and a protruding region disposed in the second region to surround an outer peripheral surface of the main emission region, one side of which protrudes outward. [Effects of the Invention]

[0010] According to an embodiment of the present disclosure, a display device with improved color viewing angle can be provided by controlling the distance between the opening of the bank layer and the reflective electrode according to the wavelength of each subpixel.

[0011] According to another embodiment of the present disclosure, a display device capable of improving the color viewing angle without reducing the aperture ratio can be provided.

[0012] According to another embodiment of the present disclosure, a display device with improved brightness can be provided by having light traveling laterally from the light emitting layer reflected again by the reflective electrode and emitted to the outside.

[0013] According to another embodiment of the present disclosure, a display device that can be used with low power consumption can be provided by improving light extraction efficiency using a reflective electrode. [Brief explanation of the drawings]

[0014] [Figure 1] FIG. 1 is a system configuration diagram of a display device according to an embodiment of the present disclosure. [Figure 2] 2 is a plan view of the display device shown in FIG. 1 taken along line AA'. FIG. [Figure 3] 3 is a diagram showing the path of light generated in region (A) of the display device shown in FIG. 2; [Figure 4] FIG. 10 is a cross-sectional view of a display device according to another embodiment of the present disclosure. [Figure 5] FIG. 5 is a plan view schematically showing the space between adjacent sub-pixels in FIGS. 2 and 4. FIG. [Figure 6] 6 is a diagram illustrating a state in which light is emitted from the subpixel shown in FIG. 5. [Figure 7] FIG. 2 is a plan view showing an arrangement of subpixels according to an embodiment of the present disclosure. [Figure 8] FIG. 2 is a plan view illustrating data lines overlapping sub-pixels according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0015] An embodiment will now be described in detail with reference to the accompanying drawings. When adding reference numerals to components in each drawing, identical components may be designated by the same numerals whenever possible, even if they are displayed in different drawings. Furthermore, when describing this embodiment, if it is determined that a detailed description of related known structures or functions may deviate from the gist of this embodiment, such detailed description may be omitted. When terms such as "include," "have," and "be made" are used in this specification, other terms may be added unless "only" is used. When a component is expressed in the singular, it may also include a plural unless otherwise expressly stated.

[0016] In addition, in describing the components of this embodiment, terms such as first, second, A, B, (a), (b), etc. are used only to distinguish the component from other components, and do not limit the nature, order, sequence, or number of the corresponding component.

[0017] In describing the positional relationship of components, when two or more components are described as being "coupled," "coupled," or "connected," it should be understood that the two or more components may be directly "coupled," "coupled," or "connected," but that the two or more components may be "coupled," "coupled," or "connected" through an additional "intervening" component, where the additional component may be included in one or more of the two or more components that are "coupled," "coupled," or "connected" to each other.

[0018] In describing the temporal flow relationship related to components, operating methods, manufacturing methods, etc., when a temporal or flow precedence relationship such as "after," "following," "next," or "before" is described, it may also include cases where the relationship is not consecutive, since "immediately" or "directly" is not used.

[0019] On the other hand, when a numerical value or its corresponding information (e.g., level, etc.) for a component is mentioned, the numerical value or its corresponding information may be interpreted as including an error range that may occur due to various factors (e.g., process factors, internal or external impact, noise, etc.) even if not otherwise explicitly stated.

[0020] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0021] FIG. 1 is a system configuration diagram of a display device according to an embodiment of the present disclosure.

[0022] Referring to FIG. 1, a display driving system of a display device 100 according to an embodiment of the present disclosure may include a display panel 1 and a display driving circuit for driving the display panel 1.

[0023] The display panel 1 may include a display area (AA) where an image is displayed and a non-display area (NA) where an image is not displayed. The display panel 1 may include a plurality of sub-pixels (SP) arranged on a base substrate 110 for image display.

[0024] The display panel 1 may include a plurality of signal lines disposed on a base substrate 110. For example, the signal lines may include data lines (DL), gate lines (GL), and driving voltage lines (DVL).

[0025] Each of the plurality of data lines (DL) may be arranged to extend in a first direction (e.g., a column direction or a row direction), and each of the plurality of gate lines (GL) may be arranged to extend in a direction intersecting the first direction.

[0026] The display driving circuit may include a data driving circuit 11 and a gate driving circuit 12 , and may further include a controller 13 for controlling the data driving circuit 11 and the gate driving circuit 12 .

[0027] The data driving circuit 11 may output data signals (also referred to as data voltages) corresponding to video signals to a plurality of data lines (DL). The gate driving circuit 12 may generate gate signals and output the gate signals to a plurality of gate lines (GL). The controller 13 may convert input video data received from an external host 14 to a data signal format used by the data driving circuit 11 and supply the converted video data to the data driving circuit 11.

[0028] The data driving circuit 11 may include one or more source driver integrated circuits. For example, each source driver integrated circuit may be connected to the display panel 1 by a tape automated bonding (TAB) method, or may be connected to a bonding pad of the display panel 1 by a COG (Chip On Glass) or COP (Chip On Panel) method, or may be configured and connected to the display panel 1 by a COF (Chip On Film) method.

[0029] The gate driving circuit 12 may be connected to the display panel 1 using a tape automated bonding (TAB) method, or may be connected to a bonding pad of the display panel 1 using a COG or COP method, or may be connected to the display panel 1 using a COF method, or may be formed in the non-display area (NA) of the display panel 1 as a GIP (Gate In Panel) type.

[0030] Referring to FIG. 1, in a display device 100 according to an embodiment of the present disclosure, each sub-pixel (SP) includes a light-emitting element (ED) and a pixel driving circuit (SPC) for driving the light-emitting element, and the pixel driving circuit (SPC) may include a driving transistor (DRT), a scan transistor (SCT), and a storage capacitor (Cst).

[0031] The drive transistor (DRT) may control the current flowing through the light emitting element (ED) to drive the light emitting element (ED). The scan transistor (SCT) may transmit a data voltage (Vdata) to a second node (N2) that is a gate node of the drive transistor (DRT). The storage capacitor (Cst) may be configured to maintain a voltage for a certain period of time.

[0032] The light emitting element (ED) may include a first electrode 150, a second electrode 180, and an emitting layer 170 located between the first electrode 150 and the second electrode 180. The first electrode 150 may be a pixel electrode involved in forming the light emitting element (ED) of each subpixel (SP) and may be electrically connected to the first node (N1) of the driving transistor (DRT). The second electrode 180 may be a common electrode involved in forming the light emitting elements (ED) of all subpixels (SP) and may have a base voltage (EVSS) applied to it.

[0033] For example, the light emitting device (ED) may be an organic light emitting diode (OLED), an inorganic light emitting diode (LED), or a quantum dot light emitting device that is a semiconductor crystal that emits light by itself.

[0034] The driving transistor (DRT) is a transistor for driving the light emitting element (ED) and may include a first node (N1), a second node (N2), and a third node (N3). The first node (N1) may be a source or drain node and may be electrically connected to the first electrode 150 of the light emitting element (ED). The second node (N2) may be a gate node and may be electrically connected to the source or drain node of the scan transistor (SCT). The third node (N3) may be a drain or source node and may be electrically connected to the driving voltage line (DVL) that supplies the driving voltage (EVDD). For convenience of explanation, the following description will be given assuming that the first node (N1) is a source node and the third node (N3) is a drain node.

[0035] The scan transistor (SCT) may switch the connection between the data line (DL) and the second node (N2) of the drive transistor (DRT). The scan transistor (SCT) may control the connection between the second node (N2) of the drive transistor (DRT) and a corresponding data line (DL) among the plurality of data lines (DL) in response to a scan signal (SCAN) supplied from a scan line (SCL), which is a type of gate line (GL).

[0036] The storage capacitor Cst may be configured between the first node N1 and the second node N2 of the driving transistor DRT.

[0037] 1 is merely an example for the purpose of explanation, and the subpixel (SP) may further include one or more transistors or one or more capacitors. Alternatively, each of the multiple subpixels may have the same structure, or some of the multiple subpixels may have a different structure. Each of the drive transistor (DRT) and the scan transistor (SCT) may be an n-type transistor or a p-type transistor.

[0038] FIG. 2 is a cross-sectional view of the display device shown in FIG. 1 taken along line AA'.

[0039] Referring to FIG. 2, the display device 100 may include a base substrate 110, a first planarization layer 120, a second planarization layer 130, a third planarization layer 140, a first electrode 150, a bank layer 160, an emission layer 170, and a second electrode 180.

[0040] The base substrate 110 supports various components of the display device 100 and may include a display area (AA) that displays images and a non-display area (NA) that does not display images. The display area (AA) may include a first area (A1) and a second area (A2). The first area (A1) is a main emission area (MEA) in which an organic light emitting diode (OLED) formed by a first electrode, an emitting layer 170, and a second electrode is disposed, and the second area (A2) may be an area that does not overlap the organic light emitting diode (OLED). In some embodiments, the emitting layer 170 may extend beyond the first area (A1). In this case, the operating organic light emitting diode may be limited to the first area (A1) where the first electrode 150, the emitting layer 170, and the second electrode 180 overlap and contact each other. Specifically, the second region (A2) may be a region where a reflective area (REA) where waveguide mode light traveling to the side of the light emitting layer 170 is totally reflected by the first electrode 150 and emitted to the outside and a non-emitting area (NEA) coexist. The second region (A2) may include a boundary between adjacent sub-pixels (SP) and / or a non-display area (NA).

[0041] The base substrate 110 may be composed of multiple layers. For example, the base substrate 110 may include a first base substrate 111, a second base substrate 112, and an insulating layer 113 disposed between the first base substrate 111 and the second base substrate 112.

[0042] The first base substrate 111 and the second base substrate 112 may be made of polyimide (PI). Polyimide is a polymer with a relatively low degree of crystallinity or a mostly amorphous structure, and is easy to synthesize and can be used to make a thin film. It also has advantages such as transparency, heat resistance, and mechanical properties. However, polyimide has poor moisture resistance, so silicon nitride (SiN) is used between the first base substrate 111 and the second base substrate 112. x ), silicon oxide (SiO x By disposing the insulating layer 113 made of an inorganic insulating material such as SiO 2 , the moisture permeability of the base substrate 110 can be ensured.

[0043] A plurality of buffer layers for blocking moisture and oxygen from entering the second base substrate 112 may be disposed on the second base substrate 112. For example, the buffer layers may include a multi-buffer layer 114 and an active buffer layer 115.

[0044] The multi-buffer layer 114 is for blocking moisture and oxygen from entering the inside, and is made of silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), or other inorganic materials.

[0045] A first light-shielding layer 10 for preventing external light from entering the driving transistor (DRT) may be disposed between the base substrate 110 and the multi-buffer layer 114. That is, the multi-buffer layer 114 may be formed on the base substrate 110 to cover the first light-shielding layer 10.

[0046] An active buffer layer 115 may be disposed on the multi-buffer layer 114. The active buffer layer 115 may be silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), or other inorganic materials.

[0047] A driving transistor (DRT) may be disposed between the base substrate 110 and the first planarization layer 120. The driving transistor (DRT) controls a current flowing through the light emitting element (ED) to drive the light emitting element (ED), and may be electrically connected to the first electrode 150.

[0048] The drive transistor (DRT) is disposed on the active buffer layer 115 and may include a first active layer (ACT1), a first gate electrode (GE1), a first source electrode (SE1), and a first drain electrode (DE1). A first light-shielding layer 10 for protecting the first active layer (ACT1) may be disposed below the first active layer (ACT1).

[0049] A plurality of inorganic layers for forming components of the drive transistor (DRT) may be formed on the active buffer layer 115. For example, the inorganic layers may include a gate insulating layer 116 and a plurality of interlayer insulating layers 117.

[0050] A gate insulating layer 116 may be disposed on the active buffer layer 115 to cover the first active layer (ACT1). A first gate electrode (GE1) may be disposed on the gate insulating layer 116.

[0051] The interlayer insulating layer 117 may be configured in plurality and may be disposed on the gate insulating layer 116 to cover the first gate electrode GE1. A first source electrode SE1 and a first drain electrode DE1 may be disposed on the interlayer insulating layer 117. At this time, contact holes through which the first source electrode SE1 and the first drain electrode DE1 pass may be formed in the gate insulating layer 116 and the interlayer insulating layer 117, and the first source electrode SE1 and the first drain electrode DE1 may be connected to a first active layer ACT1 in which a channel is formed when the driving transistor DRT is driven.

[0052] The interlayer insulating layer 117 may include a first interlayer insulating layer 117a, a second interlayer insulating layer 117b, a third interlayer insulating layer 117c, and a fourth interlayer insulating layer 117d. A scan transistor (SCT) including a second active layer (ACT2), a second gate electrode (GE2), a second source electrode (SE2), and a second drain electrode (DE2) may be disposed on the interlayer insulating layer 117.

[0053] For example, a second active layer (ACT2) may be disposed on the second interlayer insulating layer 117b, and a third interlayer insulating layer 117c may be disposed on the second active layer (ACT2) to cover the second active layer (ACT2). A second gate electrode (GE2) may be disposed on the third interlayer insulating layer 117c, and a fourth interlayer insulating layer 117d may be disposed on the third interlayer insulating layer 117c to cover the second gate electrode (GE2). A first source electrode (SE1) and a first drain electrode (DE1) may be disposed on the fourth interlayer insulating layer 117d. In this case, contact holes through which the second source electrode (SE2) and the second drain electrode (DE2) pass may be formed in the third interlayer insulating layer 117c and the fourth interlayer insulating layer 117d, and the second source electrode (SE2) and the second drain electrode (DE2) may be connected to the second active layer (ACT2).

[0054] A second light-shielding layer 20 may be disposed below the scan transistor (SCT) to prevent light from being incident on the scan transistor (SCT). For example, the second light-shielding layer 20 may be disposed between the first interlayer insulating layer 117a and the second interlayer insulating layer 117b.

[0055] The first planarization layer 120 may be disposed on the base substrate 110. For example, the first planarization layer 120 may be formed of an organic material such as photo-acrylic (PAC), and may be disposed on the interlayer insulating layer 117 to cover the first source electrode (SE1) and the first drain electrode (DE1). Thus, the first planarization layer 120 can reduce lower steps caused by the components of the first source electrode (SE1) and the first drain electrode (DE1).

[0056] The first planarization layer 120 may include a first contact hole 120a overlapping the driving transistor (DRT) and the hole 140a of the third planarization layer 140. As such, the first contact hole 120a is formed in the first planarization layer 120, so that the driving transistor (DRT) and the first electrode 150 may be electrically connected through a connecting electrode (CE) disposed on the first planarization layer 120. For example, a lower portion of the connecting electrode (CE) may be inserted into the first contact hole 120a, so that the connecting electrode (CE) may contact the driving transistor (DRT).

[0057] The second planarization layer 130 may be disposed on the first planarization layer 120 to cover the connecting electrode (CE). The second planarization layer 130 may include a second contact hole 130a overlapping the first contact hole 120a.

[0058] As such, the second contact hole 130a is formed in the second planarization layer 130, so that a portion of the first electrode 150 is inserted into the second contact hole 130a, and the first electrode 150 can contact the connecting electrode (CE).

[0059] The third planarization layer 140 may be disposed on the second planarization layer 130, and may have a plurality of holes 140a formed therein exposing portions of the second planarization layer 130. For example, the plurality of holes 140a formed in the third planarization layer 140 may be formed in the first region (A1) and a portion of the second region (A2) disposed to surround the outer periphery of the first region (A1). The holes 140a may be formed to overlap the first contact hole 120a and the second contact hole 130a. That is, the holes 140a, the first contact hole 120a, and the second contact hole 130a may be disposed to overlap in the Z-axis direction in the drawing.

[0060] The first electrode 150 may be disposed to overlap the hole 140a of the third planarization layer 140. For example, a plurality of first electrodes 150 may be disposed independently in each hole 140a. In this embodiment, the first electrode 150 may be an anode and a reflective electrode. To this end, the first electrode 150 may be formed of an opaque electrode made of a metal material with good reflectivity, such as aluminum (Al), copper (Cu), or nickel (Ni). Alternatively, the second electrode 180 may be formed of a stacked structure of a transparent electrode and an opaque electrode, such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0061] The bank layer 160 is for dividing the first region (A1), and may have a plurality of openings 160a formed therein to expose portions of the first electrode 150. For example, the bank layer 160 may be disposed in the second region (A2), and may be disposed to cover portions of the outer periphery of the first electrode 150 and the third planarization layer 140.

[0062] The bank layer 160 may have an opening 160a formed in a portion corresponding to the first region (A1). For example, the opening 160a of the bank layer 160 may overlap the hole 140a but may not overlap the first contact hole 120a and the second contact hole 130a. With this structure, a portion of the first electrode 150 may be exposed to the outside through the opening 160a of the bank layer 160.

[0063] The light-emitting layer 170 may be composed of a plurality of layers, each disposed in the opening 160a of the bank layer 160. That is, the light-emitting layer 170 may be disposed independently in the first region (A1). In some embodiments, the light-emitting layer 170 may extend beyond the first region (A1) to the side of the bank layer 160. In this embodiment, the light-emitting layer 170 may be an organic light-emitting layer including an organic compound layer such as a hole injection layer (HIL), a hole transport layer (HTL), an emission material layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL).

[0064] The second electrode 180 may be disposed on the bank layer 160 and the light-emitting layer 170. For example, the second electrode 180 may be a cathode and may be disposed in the first region (A1) and the second region (A2). As a result, an organic light-emitting diode may be formed in the first region (A1) by the first electrode 150, the light-emitting layer 170, and the second electrode 180.

[0065] The second electrode 180 may be an opaque electrode such as aluminum (Al), copper (Cu), nickel (Ni), etc., or a transparent electrode such as indium tin oxide (ITO), indium zinc oxide (IZO), etc. Alternatively, the second electrode 180 may be formed as a stacked structure of an opaque electrode and a transparent electrode.

[0066] FIG. 3 is a diagram showing the light paths generated in the "A" region of the display device shown in FIG.

[0067] 3, light generated in the light emitting layer 170 may be totally reflected at the interface with the underlying member and travel laterally. This is called a waveguide mode and causes a decrease in light extraction efficiency. To solve this problem, the waveguide mode light traveling laterally may be reflected by the first electrode 150 and emitted to the outside. That is, the first electrode 150 may be used as a reflective electrode.

[0068] The first electrode 150 may include a first body portion 151 , a second body portion 152 , and a third body portion 153 .

[0069] The first body part 151 may be disposed in the first region A1. For example, the first body part 151 may be disposed on the second planarization layer 130 exposed to the outside of the hole 140a of the third planarization layer 140.

[0070] The second body portion 152 may extend from an end of the first body portion 151, with a portion disposed on the top of the second planarization layer 130 and the remainder disposed on a side of the third planarization layer 140. As the second body portion 152 is formed perpendicularly to the side of the third planarization layer 140, light traveling laterally at the interface between the light emitting layer 170 and the first body portion 151 may be reflected again by the second body portion 152 and emitted to the outside.

[0071] A portion of the second body portion 152 is inserted into the second contact hole 130a formed in the second planarization layer 130 and contacts the connection electrode (CE), thereby electrically connecting to the driving transistor (DRT). At this time, a portion of the second body portion 152 inserted into the second contact hole 130a may be recessed, so that a step may be formed on the upper portion of the second body portion 152.

[0072] The second body portion 152 may be disposed in the second region (A2) to surround the outer periphery of the first body portion 151, and may have a protrusion 150a that protrudes from one side of the first body portion 151 and overlaps the second contact hole 130a. For example, the protrusion 150a may be formed through the second body portion 152 that overlaps the second contact hole 130a in the second region (A2).

[0073] The third body portion 153 may be disposed in the second region (A2) to surround the outer circumferential surface of the second body portion 152. For example, the third body portion 153 may extend from an end of the second body portion 152 and be disposed on an upper portion of the third planarization layer 140.

[0074] As described above, light traveling from the light-emitting layer 170 to the side can be totally reflected by the second body portion 152 of the first electrode 150, which is used as a reflective electrode, and extracted to the outside, thereby improving the light extraction efficiency of the display device 100 and providing a display device 100 that can be used with low power.

[0075] Meanwhile, since the first electrode 150 is formed to include a first body portion 151, a second body portion 152, and a third body portion 153, steps may be formed in the first electrode 150. Due to this step structure, the bank layer 160 disposed on the first electrode 150 and the third planarization layer 140 may be formed to have different heights depending on the position. For example, the height (h1) of the bank layer 160 disposed between the second contact hole 130a and the first region (A1) may be greater than the height (h3) of the bank layer 160 overlapping the third planarization layer 140 and less than the height (h2) of the bank layer 160 overlapping the second contact hole 130a.

[0076] The display device 100 according to this embodiment can output white light through red, green, and blue sub-pixels (SP). Because the red, green, and blue sub-pixels (SP) have different wavelengths, the amount of luminance reduction varies from the front to the side, which can degrade the color viewing angle (VACS). For example, the luminance of blue decreases more from the front to the side, which can degrade the color viewing angle.

[0077] In order to prevent or reduce such a decrease in the color viewing angle, it is preferable to set the distance between the second body portion 152 of the first electrode 150 formed on the side of the third planarization layer 140 and the opening 160a of the bank layer 160 to vary in the horizontal direction parallel to the base substrate 110. That is, by setting the horizontal distance between the opening 160a, in which the light emitting layer 170 is disposed, and the second body portion 152 to vary depending on the wavelength for each subpixel (SP), the reflection angle of light reflected from the second body portion 152 can be controlled, thereby improving the color viewing angle.

[0078] FIG. 4 is a cross-sectional view of a display device according to another embodiment of the present disclosure.

[0079] 4, the display device 200 can control the horizontal separation distance between a portion of the second body portion 152 disposed on the side of the third planarization layer 140 and the opening 160a of the bank layer 160 by disposing a control member 141 formed of the same material as the third planarization layer 140 under the first body portion 151 of the first electrode 150. For example, the separation distance between the second body portion 152, which is a reflective electrode, can be controlled by shifting the position of the control member 141 outward or inward depending on the wavelength for each subpixel (SP).

[0080] FIG. 5 is a plan view schematically showing the space between adjacent sub-pixels in FIGS.

[0081] Referring to FIG. 5, adjacent first electrodes 150 must have a minimized process margin (M). In this case, moving the control member 141 to the location where the second contact hole 130a is located can make it difficult to minimize the process margin (M). Therefore, the display device 200 of FIG. 4 can reduce the process margin (M) by reducing the width of the second contact hole 130a formed on the side of the second body portion 152 adjacent to the first electrode 150. The display device 200 of FIG. 4 reduces the width of the opening 160a in the bank layer 160 while maintaining a horizontal separation distance between a portion of the second body portion 152 formed on the side of the third planarization layer 140 and the opening 160a, which may reduce the aperture ratio of the display device 200 and result in reduced light extraction efficiency.

[0082] To prevent such a decrease in aperture ratio, in the display device 100 according to this embodiment, the second body portion 152 disposed on the second planarization layer 130 may be disposed so as not to overlap the third planarization layer 140. That is, in order to control the horizontal separation distance between the opposing second body portions 152 without changing the width of the opening 160a formed in the bank layer 160, the control member 141, which is a part of the third planarization layer 140, is configured not to be disposed between the second contact hole 130a and the first body portion 151. Therefore, the horizontal separation distance between the second body portion 152 formed on the side of the third planarization layer 140 and the opening 160a of the bank layer 160 can be further increased or decreased by the possible width of the control member 141, thereby controlling the horizontal separation distance between the second body portions 152 without a decrease in aperture ratio.

[0083] For example, the size of the hole 140a formed in the third planarization layer 140 can be varied to control the horizontal distance between the opening 160a and the first electrode 150. That is, when the size of the hole 140a in the third planarization layer 140 is increased, the distance between the opening 160a formed on the side of the third planarization layer and the second body portion 152 also increases, and when the size of the hole 140a is decreased, the distance between the opening 160a and the second body portion 152 also decreases.

[0084] 5, the first electrode 150 of the display device 100 may include a first electrode region S1 overlapping the second contact hole 130a and a second electrode region S2 extending from the first electrode region S1 to one side and overlapping the opening 160a. The hole 140a formed in the third planarization layer 140 may include a first hole region H1 extending from an end of the second body portion 152 overlapping the second contact hole 130a within the second electrode region S2 to one side closest to the outer periphery of the second body portion 152, and a second hole region H2 extending from one side of the first hole region H1 to the other side of the outer periphery of the second body portion 152, and overlapping the opening 160a.

[0085] With this structure, the distance L1 from the center of the opening 160a to the end of the second body portion 152 disposed in the first hole region H1 may be greater than the distance L2 from the center of the opening 160a to the end of the second body portion 152 disposed in the second hole region H2. The first hole region H1 and the second hole region H2 are areas where the second body portion 152, which is a reflective electrode, is disposed on the first electrode. By varying the width of the second hole region H2 formed in the third planarization layer 140, the distance between the outer periphery of the second body portion 152 and the opening 160a can be controlled in the plan view shown in FIG. 5. That is, the horizontal distance between the portion of the second body portion 152 formed on the side of the third planarization layer 140 and the opening 160a in the cross-sectional view shown in FIG. 3 may increase or decrease in proportion to the change in the width of the second hole region H2. Here, the change in width of the second hole region H2 means the change in length in the X-axis direction and the Y-axis direction on the drawing.

[0086] Therefore, when the width of the second hole region H2 is increased or decreased according to the wavelength for each subpixel SP, the separation distance between the outer periphery of the second body portion 152 and the opening 160a can be set differently, thereby improving the color viewing angle. Also, since the position of the second body portion 152 is expanded and moved by the width of the first hole region H1, the separation distance can be made wider by the width of the first hole region H1, thereby improving the color viewing angle without reducing the aperture ratio.

[0087] The second hole region (H2) may be formed to extend up to the second contact hole 130a because, if the second hole region (H2) overlaps the second contact hole 130a, the size of the first electrode 150 covering the hole 140a also increases, making it difficult to ensure the minimum process margin (M) required between adjacent first electrodes 150.

[0088] Meanwhile, in the display device 100 according to this embodiment, the control member 141 is not disposed between the second contact hole 130a and the first body part 151, so the width of the opening 160a can be increased by approximately the width of the control member 141. Therefore, the aperture ratio can be increased, thereby improving the light extraction efficiency.

[0089] FIG. 6 is a diagram illustrating the state in which light is emitted from the subpixel shown in FIG.

[0090] Referring to FIG. 6, the sub-pixels (SP) arranged in the display area (AA) may include an emissive area (EA) including a main emissive area (MEA) and a reflective area (REA), and a non-emissive area (NEA) which is the remaining area excluding the emissive area (EA).

[0091] The main emission area (MEA) may be disposed in a first area (A1) overlapping the organic light emitting diode formed by the first electrode 150, the emission layer 170, and the second electrode 180. That is, the main emission area (MEA) is an area where light generated in the light emitting element (ED) is emitted through the opening 160a, and may be the area with the highest brightness in the sub-pixel (SP).

[0092] The reflective area (REA) is disposed in the second area (A2) to surround the outer periphery of the main light emitting area (MEA), and one side of the reflective area (REA) may protrude outward to form a protruding area (PA). For example, the protruding area (PA) may protrude in the direction in which the second contact hole 130a is disposed, and the first contact hole 120a and the second contact hole 130a may be located within the protruding area (PA).

[0093] In this embodiment, the reflective area (REA) may be a region where waveguide-mode light traveling to the side of the light-emitting layer 170 is totally reflected by the second body portion 152 of the first electrode 150 and emitted to the outside. Since the amount of waveguide-mode light is less than the amount of light emitted through the opening 160a, the reflective area (REA) may have lower brightness than the main light-emitting area (MEA). The region of the second body portion 152 of the first electrode 150 that overlaps the bank layer 160 and is disposed on the second planarization layer 130 without extending to the side of the third planarization layer 140 may be relatively less prone to total reflection. Therefore, a side ring (R) may be formed between the main light-emitting area (MEA) and the reflective area (REA). That is, the side ring (R) may be the region of the light-emitting area (EA) with the lowest brightness. Although not shown, when viewed from a plan view, the side ring (R) may have a protruding shape due to the protruding area (PA). Due to such a protruding shape, the width of the side ring (R) can be greatest in the protruding area (PA).

[0094] FIG. 7 is a plan view showing an arrangement of subpixels according to one embodiment of the present disclosure.

[0095] 7, the subpixels (SP) may include a first subpixel (SP1), a second subpixel (SP2), a third subpixel (SP3), and a fourth subpixel (SP4) adjacent to each other. For example, the first subpixel (SP1) may be formed to emit red light, the second subpixels (SP2) and (SP3) may be formed to emit green light, and the fourth subpixel (SP4) may be formed to emit blue light. Because the subpixels (SP) are formed to have different structures and arrangements for each color, the spacing between the first subpixel (SP1), the second subpixel (SP2), the third subpixel (SP3), and the fourth subpixel (SP4) may vary. Therefore, the distance between the outer periphery of the second body portion 152 and the opening 160a may be asymmetrically extended according to the spacing between each subpixel (SP).

[0096] According to this embodiment, the first sub-pixel (SP1) and the fourth sub-pixel (SP4) may be rectangular, and the second sub-pixel (SP2) and the third sub-pixel (SP3) may be oval or rectangular. The protruding regions (PA) of the first sub-pixel (SP1) and the third sub-pixel (SP3) may protrude outward, and the protruding regions (PA) of the fourth sub-pixel (SP4) and the second sub-pixel (SP2) may protrude inward. This structure allows a maximum number of sub-pixels to be arranged on a plane, improving light-emitting efficiency. The protruding regions (PA) of the second sub-pixel (SP2) and the third sub-pixel (SP3) may extend in a first direction, and the protruding regions (PA) of the first sub-pixel (SP1) and the fourth sub-pixel (SP4) may extend in a second direction different from the first direction. The protruding regions (PA) of the fourth sub-pixel (SP4) and the second sub-pixel (SP2) may be closer to and face each other than the protruding regions (PA) of the first sub-pixel (SP1) and the third sub-pixel (SP3).

[0097] FIG. 8 is a plan view showing data lines overlapping sub-pixels according to one embodiment of the present disclosure.

[0098] 8, the display device 100 further includes data lines DL electrically connected to the subpixels SP arranged in the first region A1, and the data lines DL may be arranged in a single line. Arranging the data lines DL in a single line like this can secure more installation space than data lines with bends. This makes it easier to design the positions of the first contact holes 120a and the second contact holes 130a.

[0099] According to this embodiment, a plurality of sub-pixels (SP) are configured, and a data line (DL) may overlap at least two sub-pixels (SP). In addition, the data line (DL) may overlap the reflective area (REA) of at least one sub-pixel (SP). This structure allows for the maximum arrangement of a plurality of sub-pixels (SP) on a plane, thereby improving luminous efficiency.

[0100] 8, the display device 100 may further include a driving voltage line (DVL) for applying a driving voltage to the sub-pixel (SP), and the protruding region (PA) may be disposed between the driving voltage line (DVL) and the data line (DL), which facilitates the formation of the first contact hole 120a and the second contact hole 130a formed in the protruding region (PA).

[0101] The above-described embodiments of the present disclosure will be briefly described below.

[0102] According to an embodiment of the present disclosure, a display device may be provided that includes a sub-pixel including a first region overlapping an organic light emitting diode and a second region not overlapping the organic light emitting diode, a main light emitting region disposed in the first region, and a reflective light region including a protruding region disposed in the second region to surround an outer periphery of the main light emitting region, one side of which protrudes outward.

[0103] According to an embodiment of the present disclosure, the light emitting device may include a side ring formed between the main light emitting region and the reflective light region.

[0104] According to embodiments of the present disclosure, the side ring may have a protruding shape with a protruding region.

[0105] According to an embodiment of the present disclosure, the width of the side ring may be formed to be thickest in the protruding region. According to an embodiment of the present disclosure, the subpixel may include a base substrate including a first region and a second region, a first planarization layer disposed on the base substrate and having a first contact hole formed therein, a second planarization layer disposed on the first planarization layer and having a second contact hole formed therein overlapping with the first contact hole, a third planarization layer disposed on the second planarization layer and having holes formed therein overlapping with the first contact hole and the second contact hole, a first electrode overlapping the holes in the third planarization layer, a bank layer having an opening formed therein to expose a portion of the first electrode, a light-emitting layer disposed in the opening of the bank layer, and a second electrode disposed on the bank layer and the light-emitting layer.

[0106] According to an embodiment of the present disclosure, the protruding region may protrude in a direction in which the second contact hole is disposed.

[0107] According to an embodiment of the present disclosure, the first contact hole and the second contact hole may be located within the protruding region.

[0108] According to an embodiment of the present disclosure, the first electrode may include a first body portion disposed in the first region, a second body portion disposed in the second region to surround the outer periphery of the first body portion, protruding from one side of the first body portion and having a protrusion formed thereon that overlaps the second contact hole, and a third body portion disposed to surround the outer periphery of the second body portion.

[0109] According to an embodiment of the present disclosure, the horizontal distance between the opening formed on the side of the third planarization layer and the second body portion can be controlled by varying the size of the hole formed in the third planarization layer.

[0110] According to an embodiment of the present disclosure, the height of the bank layer disposed between the second contact hole and the first region may be greater than the height of the bank layer overlapping the third planarization layer and less than the height of the bank layer overlapping the second contact hole.

[0111] According to an embodiment of the present disclosure, the opening may not overlap the first contact hole and the second contact hole, but may overlap the hole in the third planarization layer.

[0112] According to an embodiment of the present disclosure, the first electrode may include a first electrode region overlapping the second contact hole, and a second electrode region extending to one side from the first electrode region and overlapping the opening.

[0113] According to an embodiment of the present disclosure, the hole formed in the third planarization layer may include a first hole region extending to one side closest to the outer surface of the second body portion disposed within the second electrode region at an end of the second body portion overlapping the second contact hole, and a second hole region extending from one side of the first hole region to the other side of the outer surface of the second body portion and overlapping the opening.

[0114] According to an embodiment of the present disclosure, the distance between the opening and the outer periphery of the second body portion can be controlled by varying the width of the second hole region.

[0115] According to an embodiment of the present disclosure, the distance between the center of the opening and the end of the second body portion disposed in the first hole region may be greater than the linear distance between the center of the opening and the end of the second body portion disposed in the second hole region.

[0116] According to an embodiment of the present disclosure, a subpixel may include a first subpixel, a second subpixel, a third subpixel, and a fourth subpixel adjacent to each other, and the first subpixel and the fourth subpixel may be formed in a rectangular shape, and the second subpixel and the third subpixel may be formed in an elliptical shape.

[0117] According to an embodiment of the present disclosure, the first subpixel and the fourth subpixel may be arranged symmetrically with respect to the horizontal axis, and the second subpixel and the third subpixel may be arranged symmetrically with respect to the vertical axis.

[0118] According to an embodiment of the present disclosure, the protruding regions of the first and third sub-pixels may protrude outward, and the protruding regions of the fourth and second sub-pixels may protrude inward.

[0119] According to an embodiment of the present disclosure, the pixel may further include data lines electrically connected to the sub-pixels, and the data lines may be arranged in a row.

[0120] According to an embodiment of the present disclosure, a plurality of sub-pixels may be configured, and a data line may be arranged to overlap at least two sub-pixels.

[0121] According to an embodiment of the present disclosure, a plurality of sub-pixels may be configured, and a data line may be disposed so as to overlap a reflective light area of ​​at least one of the sub-pixels.

[0122] The above description is merely an illustrative example of the technical idea of ​​the present disclosure, and various modifications and variations may be made by a person skilled in the art without departing from the essential characteristics of the present disclosure. Furthermore, the examples disclosed in the present disclosure are for the purpose of explanation, not for the purpose of limiting the technical idea of ​​the present disclosure, and therefore the scope of the technical idea of ​​the present disclosure is not limited by these examples. [Explanation of symbols]

[0123] 100 display device 110 Base board 120 1st planarization layer 130 Second planarization layer 140 Third planarization layer 150 1st electrode 151 First Body Section 152 Second Body Section 153 Third Body Section 160 bank layers 170 Light-emitting layer 180 2nd electrode

Claims

1. a subpixel including a first region overlapping an organic light emitting diode and a second region not overlapping the organic light emitting diode; a main light-emitting region disposed in the first region; a reflective region including a protruding region in the second region, the protruding region having one side protruding outward, the reflective region being disposed to surround an outer periphery of the main light-emitting region; A display device comprising:

2. The display device of claim 1 , further comprising a side ring formed between the main light-emitting region and the reflective light region.

3. The display device according to claim 2 , wherein the side ring has a shape that protrudes due to the protruding region.

4. The display device according to claim 3 , wherein the width of the side ring is formed to be thickest in the protruding region.

5. The subpixels are a base substrate including the first region and the second region; a first planarization layer disposed on the base substrate and having a first contact hole formed therein; a second planarization layer disposed on the first planarization layer and having a second contact hole formed therein, the second contact hole overlapping the first contact hole; a third planarization layer disposed on the second planarization layer, the third planarization layer having holes formed therein that overlap the first contact hole and the second contact hole; a first electrode overlapping the hole in the third planarization layer; a bank layer having an opening formed therein so as to expose a portion of the first electrode; a light-emitting layer disposed in the opening of the bank layer; a second electrode disposed on the bank layer and the light-emitting layer; The display device according to claim 1 , comprising:

6. The display device according to claim 5 , wherein the protruding region protrudes in a direction in which the second contact hole is disposed.

7. The display device according to claim 5 , wherein the first contact hole and the second contact hole are disposed within the protruding region.

8. The first electrode is a first body portion disposed in the first region; a second body portion disposed in the second region to surround an outer circumferential surface of the first body portion, the second body portion having a protrusion protruding from one side of the first body portion and overlapping the second contact hole; The display device according to claim 5 , further comprising: a third body portion disposed so as to surround an outer peripheral surface of the second body portion.

9. The display device of claim 8 , wherein a horizontal distance between the opening formed on the side of the third planarization layer and the second body portion is controlled by changing a size of a hole formed in the third planarization layer.

10. 10. The display device of claim 9, wherein the height of the bank layer disposed between the first regions of the second contact hole is greater than the height of the bank layer overlapping the third planarization layer and less than the height of the bank layer overlapping the second contact hole.

11. The display device of claim 8 , wherein the opening does not overlap the first contact hole and the second contact hole, but overlaps the hole in the third planarization layer.

12. The first electrode is a first electrode region overlapping the second contact hole; The display device of claim 8 , further comprising a second electrode region extending from the first electrode region to one side and overlapping the opening.

13. The hole formed in the third planarization layer is a first hole region extending from an end of the second body portion overlapping the second contact hole to one side closest to an outer circumferential surface of the second body portion disposed within the second electrode region; The display device of claim 12 , further comprising a second hole region extending from one side of the first hole region to the other side of the outer periphery of the second body portion and overlapping the opening.

14. The display device of claim 13 , wherein a distance between the opening and the outer periphery of the second body portion is controlled by varying a width of the second hole region.

15. 14. The display device of claim 13, wherein a distance from the center of the opening to an end of the second body portion disposed in the first hole region is greater than a linear distance from the center of the opening to an end of the second body portion disposed in the second hole region.

16. The subpixels include a first subpixel, a second subpixel, a third subpixel, and a fourth subpixel adjacent to each other, The display device of claim 1 , wherein the first sub-pixel and the fourth sub-pixel are rectangular, and the second sub-pixel and the third sub-pixel are elliptical.

17. The display device of claim 16 , wherein the first sub-pixel and the fourth sub-pixel are arranged symmetrically with respect to a horizontal axis, and the second sub-pixel and the third sub-pixel are arranged symmetrically with respect to a vertical axis.

18. The display device of claim 16 , wherein the protruding regions of the first and third sub-pixels protrude outward, and the protruding regions of the fourth and second sub-pixels protrude inward.

19. The display device of claim 1 , further comprising data lines electrically connected to the sub-pixels, the data lines being arranged in a row.

20. 20. The display device of claim 19, wherein the sub-pixels are configured in a plurality of types, and the data line overlaps at least two of the sub-pixels.

21. The display device of claim 19, wherein the sub-pixel is a plurality of sub-pixels, and the data line overlaps the reflective light region of at least one of the sub-pixels.

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