Communication device

Abstract

To appropriately cancel self-interference signals even when antenna impedance fluctuates.SOLUTION: A communication device is a communication device that receives a response wave radiated from a wireless tag on the basis of a received carrier wave, and comprises an antenna, a first generation part, a common part, a second generation part, a suppression part, a first detection part, and an adjustment part. The common part inputs a carrier wave generated by the first generation part from an input end and outputs it from an input / output end to the antenna, and outputs a signal input from the antenna to the input / output end from an output end. The second generation part generates a cancellation signal by changing the amplitude and phase of the carrier wave. The suppression part suppresses a self-interference signal contained in an output signal from the output end by using the cancellation signal. The first detection part detects a mismatch state of impedance matching related to the antenna. The adjustment part adjusts the impedance of the antenna so as to eliminate the mismatch state according to the detection of the mismatch state.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] FIELD OF THE INVENTION An embodiment of the present invention relates to a communication device. [Background technology]

[0002] In communication devices that share an antenna for both transmission and reception, a portion of the transmission signal may be superimposed on the reception signal and enter the reception system. This superimposed transmission signal component may become a self-interference signal, which may cause saturation of the reception system and increase noise, resulting in a deterioration of communication quality. Therefore, a technique is known in which a cancellation signal having an opposite phase to the self-interference signal is generated from a transmission signal, and this cancellation signal is used to cancel out the self-interference signal.

[0003] The self-interference signal varies depending on the surrounding environment, so a carrier wave is transmitted prior to receiving a response signal from a wireless tag to generate a self-interference signal, and a cancellation signal is adjusted to effectively cancel out the self-interference signal. However, when the impedance of the antenna fluctuates due to changes in the surrounding environment, the self-interference signal fluctuates, and the adjusted cancellation signal may not be able to cancel the self-interference signal properly. Under these circumstances, it has been desired to be able to properly cancel self-interference signals even when the antenna impedance fluctuates. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2006-14072 Summary of the Invention [Problem to be solved by the invention]

[0005] The problem to be solved by the present invention is to provide a communication device that can properly cancel a self-interference signal even if the impedance of the antenna fluctuates. [Means for solving the problem]

[0006] A communication device according to an embodiment receives a response wave emitted from a wireless tag based on a received carrier wave, and includes an antenna, a first generating unit, a duplexing unit, a second generating unit, a suppression unit, a first detecting unit, and an adjusting unit. The first generating unit generates a carrier wave. The duplexing unit receives the carrier wave generated by the first generating unit from an input terminal and outputs it to the antenna from an input / output terminal, and outputs a signal input from the antenna to the input / output terminal from an output terminal. The second generating unit generates a cancellation signal by changing the amplitude and phase of the carrier wave generated by the first generating unit. The suppression unit suppresses a self-interference signal included in the output signal from the output terminal using the cancellation signal generated by the second generating unit. The first detecting unit detects that the impedance matching related to the antenna is in a predetermined mismatch state. The adjusting unit adjusts the impedance of the antenna to eliminate the mismatch state in response to the first detecting unit detecting that the mismatch state exists. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 2 is a block diagram showing the main circuit configuration of a reading device according to an embodiment. [Figure 2] FIG. 2 is a block diagram showing the main circuit configuration of a matching adjustment unit. [Figure 3] 1 is an immittance chart showing the adjustment amounts of each of a plurality of matching circuits. [Figure 4] 10 is a flowchart of a control process. [Figure 5] 10 is a flowchart of a control process. [Figure 6] FIG. 10 is a diagram showing an example of actual measurements of time fluctuations in the phase of a reflected signal. [Figure 7] FIG. 10 is a graph showing an example of actual measurements of changes in the amount of cancellation due to a phase error. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, embodiments will be described with reference to the drawings. The following description will be made taking as an example a reading device that reads data stored in an RFID (radio frequency identification) tag. This reading device wirelessly communicates with the RFID tag when reading the data, and is an example of a communication device. The RFID tag is also an example of a wireless tag.

[0009] FIG. 1 is a block diagram showing the main circuit configuration of a reading device 100 according to an embodiment. The reader 100 includes an oscillator 11, a phase shifter 12, a digital-to-analog (DA) converter 13, a quadrature modulator 14, a band-pass filter (BPF) 15, a power amplifier 16, a low-pass filter (LPF) 17, an antenna duplexer 18, a matching adjuster 19, a feeder 20, an antenna 21, a variable attenuator 22, a variable phase shifter 23, a DA converter 24, a power combiner 25, a quadrature detector 26, an LPF 27, an alternating current (AC) coupled amplifier 28, an analog-to-digital (AD) converter 29, an LPF 30, an AD converter 31, a control unit 32, and a memory 33. The control unit 32 includes a central processing unit (CPU) 321 and a field programmable gate array (FPGA) 322. The antenna 21, or the feeder 20 and the antenna 21, may not be included in the reader 100, and any separate device may be connectable.

[0010] The oscillator 11 generates a sine wave of a predetermined frequency as a carrier wave. Phase shifter 12 shifts the phase of the carrier wave generated by oscillator 11 by 90 degrees, and outputs a cosine wave as another carrier wave. The oscillator 11 and the phase shifter 12 are an example of a first generating unit.

[0011] The DA converter 13 converts into analog form the two systems of transmit baseband signals that are output in digital form from the CPU 321. In the following, the two systems of transmit baseband signals are referred to as I signals and Q signals, respectively. The quadrature modulator 14 receives as modulated waves the I and Q signals converted to analog form by the DA converter 13. The quadrature modulator 14 receives as input the carrier wave generated by the oscillator 11 and the carrier wave output from the phase shifter 12 as I and Q system carrier waves, respectively. The quadrature modulator 14 then obtains a transmission signal by quadrature modulation.

[0012] The BPF 15 removes low-frequency components and high-frequency components from the transmission signal obtained by the quadrature modulator 14 in order to limit the band. The power amplifier 16 amplifies the power of the transmission signal that has passed through the BPF 15 to a level suitable for wireless transmission. The LPF 17 removes harmonic components from the transmission signal amplified by the power amplifier 16 . The transmission signal becomes a signal for radio transmission through the processes of the BPF 15, power amplifier 16, and LPF 17. That is, the BPF 15, power amplifier 16, and LPF 17 generate a transmission signal for radio transmission.

[0013] The antenna duplexer 18 has an input terminal TI, an input / output terminal TIO, an output terminal TOA, and an output terminal TOB. The transmission signal that has passed through the LPF 17 is input to the input terminal TI. The antenna duplexer 18 outputs the transmission signal input to the input terminal TI from the input / output terminal TIO and the output terminal TOB. The antenna duplexer 18 outputs the signal input to the input / output terminal TIO from the output terminal TOA. The signal output from the output terminal TOA of the antenna duplexer 18 is a signal obtained by combining the received signal generated at the antenna 21 and a self-interference signal, which will be described later, and this signal will be simply referred to as the received signal below. The antenna duplexer 18 is an example of a duplexer.

[0014] The matching adjustment unit 19 matches the impedance of the antenna 21 to within a predetermined control target range. The feeder line 20 supplies the transmission signal output from the input / output terminal TIO of the antenna duplexer 18 to the antenna 21. The feeder line 20 transmits the reception signal generated at the antenna 21 to the input / output terminal TIO of the antenna duplexer 18. The antenna 21 emits radio waves corresponding to the transmission signal supplied by the power supply line 20. The antenna 21 generates an electric signal corresponding to the incoming radio waves as a reception signal.

[0015] The variable attenuator 22 attenuates the transmission signal output from the output terminal TOB of the antenna duplexer 18 with a gain according to the gain setting signal supplied from the DA converter 24 . The variable phase shifter 23 changes the phase of the transmission signal after attenuation by the variable attenuator 22 by an amount of phase shift corresponding to a phase-shift amount setting signal supplied from the DA converter 24. The transmission signal after being phase-shifted by the variable phase shifter 23 is hereinafter referred to as a cancellation signal. Thus, the variable attenuator 22 and the variable phase shifter 23 realize the function of a second generating section that generates a cancellation signal.

[0016] The DA converter 24 converts the gain setting data output from the control unit 32 into an analog gain setting signal and supplies it to the variable attenuator 22. The DA converter converts the phase shift amount setting data output from the control unit 32 into an analog phase shift amount setting signal and supplies it to the variable phase shifter 23.

[0017] The power combiner 25 combines the power of the received signal output from the output terminal TOA of the antenna duplexer 18 with the cancellation signal output from the variable phase shifter 23. In this way, the power combiner 25 reduces the self-interference signal included in the received signal. The power combiner 25 is an example of a suppression unit.

[0018] The quadrature detector 26 performs quadrature detection on the received signal output from the power combiner 25 using the two carrier waves output from the oscillator 11 and the phase shifter 12. The quadrature detector 26 outputs, in parallel, two systems of analog received baseband signals obtained by quadrature detection.

[0019] The LPF 27 removes unnecessary frequency components other than the baseband components from each of the two systems of received baseband signals output from the quadrature detector 26 . The AC coupling amplifier 28 cuts out the DC components of each of the two systems of received baseband signals that have passed through the LPF 27, while amplifying the AC components that correspond to the response waves. AD converter 29 digitizes each of the two systems of received baseband signals output from AC coupled amplifier 28 .

[0020] The LPF 30 removes harmonic components contained in each of the two systems of received baseband signals output from the quadrature detector . The AD converter 31 digitizes each of the two systems of received baseband signals output from the LPF 30 .

[0021] The memory 33 stores an information processing program that describes information processing to be executed by the CPU 321. One of the information processing programs stored in the memory 33 is a control program PRA related to control processing, which will be described later. The memory 33 stores various data required for the CPU 321 to execute various types of information processing. The memory 33 stores various types of data generated or acquired when the CPU 321 executes various types of information processing.

[0022] When communicating with the RFID tag 200, the CPU 321 outputs an I signal and a Q signal according to a predetermined sequence. The CPU 321 reconstructs the data sent from the RFID tag 200 based on the two systems of received signals digitized by the AD converter 29. The CPU 321 executes information processing, which will be described later, for controlling the matching adjustment unit 19 or for adjusting the gain of the variable attenuator 22 and the phase shift amount of the variable phase shifter 23.

[0023] The FPGA 322 performs pre-programmed signal processing to quickly execute various calculations associated with the information processing by the CPU 321. One of the functions of the FPGA 322 is to calculate the amount of suppression of the self-interference signal by the cancellation signal based on the levels of the two systems of received baseband signals digitized by the AD converter 31. Another function of the FPGA 322 is to determine the magnitude of return loss of the antenna 21 based on the levels of the two systems of received baseband signals digitized by the AD converter 31. The return loss of the antenna 21 is the ratio between the magnitude of the power supplied to the antenna 21 and the magnitude of the reflected power generated at the feed point of the antenna 21.

[0024] FIG. 2 is a block diagram showing the main circuit configuration of the matching adjustment unit 19. The matching adjustment unit 19 includes a plurality of matching circuits 191 and switches 192 and 193 . Under the control of the CPU 321, the switches 192 and 193 insert one of the plurality of matching circuits 191 between the antenna duplexer 18 and the antenna 21. Each of the plurality of matching circuits 191 changes the antenna impedance when inserted between the antenna duplexer 18 and the antenna 21. Each of the plurality of matching circuits 191 includes an inductor 1911 connected in series between the antenna duplexer 18 and the antenna 21, and a capacitor 1912 connected in parallel between the antenna duplexer 18 and the antenna 21. The plurality of matching circuits 191 each have a different combination of the inductance value of the inductor 1911 and the capacitance value of the capacitor 1912.

[0025] FIG. 3 is an immittance chart showing the adjustment amount of each of the plurality of matching circuits 191. As an example, the number of matching circuits 191 is set to 16, and each matching circuit 191 is associated with one of the 16 antenna impedances VA, VB, ..., VP shown in Fig. 3. The antenna impedances VA to VH are each defined on a circle corresponding to a return loss of 6 dB. The antenna impedances VI to VP are each defined on a circle corresponding to a return loss of 9 dB. However, the number of matching circuits 191 and the characteristics of each matching circuit 191 may be determined as appropriate by, for example, the designer of the reader 100.

[0026] The matching adjustment unit 19 of this embodiment aims to achieve impedance matching so that the return loss is 14 dB or more. In other words, the inside of the circle corresponding to a return loss of 14 dB in FIG. 3 is the target control range. When the return loss is 14 dB, the voltage standing wave ratio (VSWR) is approximately 1.5. Since the Radio Law stipulates that the voltage standing wave ratio should be 1.5 or more, it is reasonable to set 14 dB or more as the target control range for return loss. Each matching circuit 191 is configured to match the associated antenna impedance to 50 Ω (the origin in FIG. 3). The arrows in FIG. 3 indicate how the antenna impedance VL is matched to 50 Ω. In the matching circuit 191 for matching the antenna impedance VL to 50 Ω in this manner, the inductance value of the inductor 1911 is LL in FIG. 3, and the capacitance value of the capacitor 1912 is CL in FIG. 3.

[0027] Next, the operation of the reading device 100 configured as above will be described. Before describing the operation, the self-interference signal and its cancellation process will be described. The antenna duplexer 18 is designed so that a transmission signal input to the input terminal TI is not output from the output terminal TOA. However, in an actual circuit configuration, it is difficult to completely prevent the transmission signal input to the input terminal TI from leaking out from the output terminal TOA. For this reason, a portion of the transmission signal input to the input terminal TI (hereinafter referred to as a leak signal) is output directly from the output terminal TOA. Furthermore, a portion of the transmission signal output from the input / output terminal TIO of the antenna duplexer 18 is reflected at the feed point of the antenna 21 and transmitted to the antenna duplexer 18 via the feed line 20. The power of such a reflected signal increases as the antenna impedance mismatch increases. Therefore, this power is hereinafter referred to as mismatch reflected power. Such a reflected signal is output from the output terminal TOA by the function of the antenna duplexer 18. Thus, the signal output from the output terminal TOA of the antenna duplexer 18 includes a composite signal of a leak signal component and a mismatch reflected power component. This composite signal is a self-interference signal. Since the leak signal and the reflected signal each have an amplitude and phase, the amplitude and phase of the self-interference signal are determined as the magnitude and direction of the resultant vector of the leak signal vector and the reflected signal vector. The impedance of the antenna 21 changes depending on the environment around the antenna 21, such as the proximity of the RFID tag 200 and other objects to the antenna 21. Therefore, the impedance matching condition for the antenna 21 also changes depending on the environment around the antenna 21, and the amplitude and phase of the self-interference signal also change depending on the environment around the antenna 21.

[0028] The self-interference signal is a signal derived from the transmission signal. Therefore, the self-interference signal contained in the received signal can be canceled by combining a cancellation signal generated by changing the amplitude and phase of a signal branched from the transmission signal with the received signal output from the output terminal TOA of the antenna duplexer 18. In the reader 100, the cancellation signal obtained by changing the amplitude and phase using the variable attenuator 22 and variable phase shifter 23 is combined with the received signal output from the output terminal TOA of the antenna duplexer 18 using the power combiner 25, thereby reducing the self-interference signal contained in the received signal. This is the cancellation process, which will be referred to below as SJC (self-jammer cancellation) process.

[0029] Next, the process of measuring the self-interference signal and return loss will be described. For example, in a state in which the cancellation of the self-interference signal is stopped by stopping the output of the cancellation signal from the variable phase shifter 23, if the carrier waves output from the oscillator 11 and the phase shifter 12 are supplied as is to the input terminal TI of the antenna duplexer 18, the level of the output signal of the quadrature detector 26 will change in accordance with the self-interference signal. Therefore, the FPGA 322 performs predetermined arithmetic processing on the two systems of digital received baseband signals output from the AD converter 31, thereby determining the amplitude and phase of the self-interference signal.

[0030] Furthermore, the ratio between the power of the carrier wave supplied to the input terminal TI of the antenna duplexer 18 and the power of the leak signal is determined by the characteristics of the antenna duplexer 18 and is constant. Therefore, if the power of the carrier wave supplied to the input terminal TI of the antenna duplexer 18 is constant, the power of the leak signal will also be constant. Thus, the amplitude and phase of the output signal of the quadrature detector 26 change depending on the reflected signal. In other words, there is a positive correlation between the changes in the amplitude and phase of the output signal of the quadrature detector 26 and the return loss. Therefore, the FPGA 322 determines the return loss based on the changes in the amplitude and phase of the output signal of the quadrature detector 26.

[0031] 4 and 5 are flowcharts of the control process. When it becomes necessary to read the RFID tag 200, the CPU 321 executes the control processing shown in FIGS. 4 and 5 based on the control program PRA. 4, the CPU 321 starts transmitting the carrier wave. That is, the CPU 321, for example, puts the quadrature modulator 14 into a state in which the carrier wave output from the oscillator 11 and the phase shifter 12 is output as is.

[0032] In ACT2, the CPU 321 acquires the latest return loss determination result from the FPGA 322. In ACT 3, the CPU 321 checks whether the impedance matching performed by the matching adjuster 19 is good. For example, the CPU 321 checks whether the return loss acquired in ACT 2 is within the target control range. If the return loss is outside the target control range, the CPU 321 determines that the matching is not good and determines NO, and proceeds to ACT 4. At this time, the CPU 321 detects that the impedance matching related to the antenna 21 is in a mismatched state defined as a state in which the return loss is not within a target range, and the CPU 321 functions as a first detection unit.

[0033] In ACT4, the CPU 321 checks whether the impedance matching performed by the matching adjustment unit 19 is abnormal. For example, the CPU 321 checks whether the return loss acquired in ACT2 is within a predetermined abnormal range. The abnormal range may be appropriately determined by the designer of the reading device 100, for example, as "less than 6 dB." If the return loss is outside the abnormal range, the CPU 321 determines that the matching is not abnormal and determines NO, and proceeds to ACT5.

[0034] In ACT5, the CPU 321 checks whether there is any unselected matching circuit 191 while looping through ACT2 to ACT7, as will be described later. If the CPU 321 has proceeded from ACT1 to ACT6 via ACT2 to ACT4, no matching circuits 191 other than the matching circuit 191 currently selected by the switches 192 and 193 have been selected. If there is any unselected matching circuit 191, the CPU 321 determines YES and proceeds to ACT6. In ACT6, the CPU 321 switches the switches 192 and 193 so as to select the matching circuit 191 that has not been selected.

[0035] In ACT 7, the CPU 321 updates the switching history. For example, the CPU 321 manages the switching history by storing, for example, in the memory 33, history data representing a list of matching circuits 191 included in the matching adjustment unit 19 that have been selected, and updates the history data to add the matching circuit 191 selected immediately before in ACT 16 to the list. Alternatively, for example, the CPU 321 manages the switching history by storing, for example, in the memory 33, history data representing a list of matching circuits 191 included in the matching adjustment unit 19 that have not been selected, and updates the history data to remove the matching circuit 191 selected immediately before in ACT 16 from the list.

[0036] The CPU 321 then returns to ACT2 and repeats the process from there onward as described above. Thus, the CPU 321 repeats the process of checking the return loss while switching the matching circuit 191 until it determines that the matching circuit 191 is good in ACT3, that the matching circuit 191 is abnormal in ACT4, or that there is no matching circuit 191 that has not been selected in ACT5. Even if the CPU 321 has selected all matching circuits 191 by repeating this loop process, if it does not determine that the matching circuit 191 is good in ACT3 or that the matching circuit 191 is abnormal in ACT4, it determines NO in ACT5 and proceeds to ACT8. If the return loss acquired in ACT2 falls within the abnormal range, the CPU 321 determines that the impedance matching is abnormal, determines YES in ACT4, and proceeds to ACT8. When the CPU 321 proceeds to ACT8 in this way, it has detected that the impedance matching for the antenna 21 is in a difficult-to-match state, which is defined as a state in which it is difficult for the matching adjustment unit 19 to achieve a good matching state, and thus functions as a second detection unit.

[0037] In ACT8, the CPU 321 stops transmitting the carrier wave. In ACT 9, the CPU 321 executes error processing. For example, the CPU 321 may execute error processing to inform the operator that the environment is not appropriate for reading. The CPU 321 may execute other error processing, such as outputting an alarm or playing a voice message. The CPU 321 may also execute multiple types of error processing. Operations such as displaying guidance associated with error processing may be performed by, for example, another information terminal. However, the reading device 100 may be provided with an appropriate user interface device (not shown), and the user interface device may execute operations such as displaying guidance associated with error processing. The content of the guidance provided by the error processing may be different depending on whether ACT 4 is determined to be YES or ACT 5 is determined to be NO. Thus, the CPU 321 functions as a processing unit for performing error processing. After completing error processing, the CPU 321 terminates the current control process.

[0038] For example, if the return loss is within the target range due to impedance matching via the matching circuit 191 selected by the switches 192 and 193 at the start of this control process or via a matching circuit 191 selected sequentially thereafter, the CPU 321 determines that the matching is good and determines YES in ACT 3, and proceeds to ACT 10. By controlling the switches 192 and 193 in this way, the CPU 321 matches the impedance of the antenna 21 so as to eliminate the mismatch state. In other words, the CPU 321 functions as a control unit. The function of the CPU 321 as a control unit and the function of the matching adjustment unit 19 are realized in cooperation with each other.

[0039] In ACT10, the CPU 321 starts cancellation. That is, the CPU 321 starts outputting a cancellation signal from the variable phase shifter 23. The CPU 321 sets the attenuation amount of the variable attenuator 22 and the phase amount of the variable phase shifter 23 so that the amplitude and phase of the cancellation signal are set to predetermined initial values. The initial values ​​of the amplitude and phase of the cancellation signal are set within a predetermined sweep range. The sweep range is a range that includes the amplitude and phase of a self-interference signal that may occur under standard conditions. The sweep range may be determined as appropriate by, for example, the designer of the reader 100.

[0040] In ACT11, the CPU 321 sweeps the amplitude and phase of the cancellation signal within a sweep range. That is, the CPU 321 sequentially changes, for example, the attenuation amount of the variable attenuator 22 and the phase shift amount of the variable phase shifter 23 within a predetermined range according to the sweep range. The CPU 321 then determines the attenuation amount and the phase shift amount when the level of the output signal from the quadrature detector 26 is minimum. In ACT12, the CPU 321 sets the operating states of the variable attenuator 22 and the variable phase shifter 23 to the minimum points. That is, the CPU 321 sets, for example, the amplitude and phase of the cancellation signal to the attenuation amount and phase shift amount determined in ACT11.

[0041] In ACT13, the CPU 321 checks whether the specified suppression state is reached. The specified suppression state is a state in which the influence of the self-interference signal is sufficiently suppressed. More specifically, as an example, the specified suppression state is a state in which the level of the self-interference signal component (hereinafter referred to as the residual signal) remaining in the output signal of the quadrature detector 26 has decreased to -20 dB or less compared to the non-suppressed state. That is, the CPU 321 checks the suppression amount measured by the FPGA 322, and if it is confirmed that this has decreased to -20 dB or less compared to the non-suppressed state, it determines that the specified suppression state is reached. Note that the specified suppression state is preferably defined as a state in which the minimum amount of suppression is obtained so that the quadrature detector 26 does not saturate due to the influence of the residual signal. The specified suppression state is appropriately defined, for example, by the designer of the reader 100. For example, the CPU 321 obtains the latest determination result of the level of the output signal of the quadrature detector 26 by the FPGA 322 when the return loss was last obtained in ACT2, and uses this as the level of the self-interference signal when not suppressed.

[0042] If the CPU 321 cannot confirm that the specified suppression state is being established, it determines NO in ACT 13 and repeats ACT 2 and subsequent steps. In other words, since there is a possibility that the matching of the antenna impedance may no longer be satisfactory due to a change in the surrounding environment, the CPU 321 starts over from the above-described impedance matching adjustment.

[0043] If the CPU 321 can confirm that the specified suppression state is established, it determines YES in ACT 13 and proceeds to ACT 21 in FIG. Now, when the carrier wave transmitted up to this point reaches the RFID tag 200, the RFID tag 200 starts to generate operating power as rectified power based on this carrier wave.

[0044] In ACT21, the CPU 321 starts reading the RFID tag 200. That is, the CPU 321 calls one of the RFID tags 200 that has been started as described above, causes it to transmit a response signal, and starts a series of sequences (hereinafter referred to as a read sequence) for receiving this response signal. This read sequence may be similar to that performed by another existing reader, and a detailed description thereof will be omitted. Then, while executing the read sequence, the CPU 321 transitions to a standby state in ACT22 and ACT23.

[0045] In ACT 22, the CPU 321 checks whether reading of one RFID tag has been completed. If the CPU 321 cannot confirm the event, it determines NO and proceeds to ACT 23. In ACT23, the CPU 321 checks whether the specified suppression state is in effect, for example, in the same manner as in ACT13 in Fig. 4. If the specified suppression state remains, the CPU 321 determines YES and returns to ACT22. Thus, in the standby state of ACT22 and ACT23, the CPU 321 waits until the reading is completed or until the prescribed suppression state is no longer in effect.

[0046] If reading of one RFID tag 200 is completed, the CPU 321 determines YES in ACT22 and proceeds to ACT24. In ACT24, the CPU 321 checks whether there is another RFID tag 200 to be read. If there is such an RFID tag 200, the CPU 321 determines YES and proceeds to ACT25.

[0047] In ACT25, the CPU 321 acquires the latest return loss determination result from the FPGA 322. In ACT 26, the CPU 321 checks whether the impedance matching performed by the matching adjustment unit 19 is satisfactory, in the same manner as in ACT 3 in Fig. 4. If the CPU 321 checks that the impedance matching is satisfactory, it determines YES and repeats ACT 21 and subsequent steps in the same manner as described above. In other words, the CPU 321 attempts to read another RFID tag 200 that is to be read.

[0048] While the read sequence is being executed, the self-interference signal may change due to changes in the surrounding environment, making it impossible to maintain the specified suppression state. In particular, when the communication speed is relatively low and the time required to execute the read sequence (hereinafter referred to as the read time) is long, the self-interference signal may change significantly during the execution of the read sequence.

[0049] FIG. 6 shows an example of measured time fluctuations in the phase of a reflected signal. Fig. 6 shows an example of reading from RFID tags 200 attached to multiple items placed on a shelf while moving the reading device 100. In Fig. 6, the solid line indicates the case where the reading device 100 is moved horizontally on the shelf, and the dashed line indicates the case where the reading device 100 is moved vertically on the shelf.

[0050] FIG. 7 is a diagram showing an example of actual measurements of changes in the amount of cancellation due to phase errors. It is desirable to ensure a cancellation amount of at least 20 dB, and to achieve this, it is clear from FIG. 7 that it is desirable to keep the phase error within 5 degrees. 6, when focusing on the portion where the time fluctuation is steep, a 5 degree fluctuation in the reflection phase is observed in 31 msec from 524 msec to 555 msec. Therefore, if reading of one RFID tag 200 is not completed within 31 msec, it is conceivable that the amount of cancellation will be insufficient during reading, causing a reading error.

[0051] The reading time of the RFID tag 200 depends on the performance of the RFID tag 200. For example, if the RFID tag 200 is a UHF (ultra high frequency) tag conforming to ISO / IEC18000-63 / EPC GEN2, which is currently the standard, the reading time is approximately 6 msec (40 kbps, 240 bit length), which falls within the above-mentioned 31 msec range. However, if the RFID tag 200 is constructed inexpensively using printed electronics technology or the like and requires a reading time of 100 msec or more, reading cannot be completed within the above-mentioned 31 msec.

[0052] In particular, if the RFID tag 200 to be read is of such a slow type, there is a risk that the specified suppression state cannot be maintained while the read sequence is being executed. Note that even if the read time is short, if a sudden environmental change occurs during that read time, there is still a risk that the specified suppression state cannot be maintained.

[0053] If the CPU 321 is unable to confirm that the RFID tag 200 is in the specified suppression state before reading of one RFID tag 200 is completed, the CPU 321 determines NO in ACT23 in FIG. 5 and proceeds to ACT27. In ACT 27, the CPU 321 stops the reading sequence that is currently being executed, and then repeats the processing from ACT 5 onward in FIG. 4 in the same manner as described above.

[0054] On the other hand, if the CPU 321 cannot confirm that the impedance matching by the matching adjustment unit 19 is good after reading one RFID tag 200 is completed, it determines NO in ACT26 and proceeds to ACT28. In ACT28, the CPU 321 checks whether the impedance matching performed by the matching adjustment unit 19 is abnormal, in the same manner as in ACT4 in Fig. 4. If the CPU 321 cannot confirm that there is an abnormality, it determines NO and proceeds to ACT29. In ACT 29, the CPU 321 resets the switching history. For example, the CPU 321 updates the history data so that it can determine that only the matching circuit 191 selected by the switches 192 and 193 at this point has been selected. Alternatively, the CPU 321 may update the history data so that it can determine that no matching circuit 191 has been selected. Thereafter, the CPU 321 executes the processes from ACT 2 onward in FIG. 4 in the same manner as described above. As a result, the CPU 321 restarts the above-described impedance matching adjustment from the beginning.

[0055] 5 that the impedance matching by the matching adjustment unit 19 is abnormal, the CPU 321 determines YES and proceeds to ACT 30. When proceeding to ACT 30 in this way, the CPU 321 has detected that the impedance matching related to the antenna 21 is in a difficult-to-match state, which is defined as a state in which it is difficult for the matching adjustment unit 19 to form a good matching state, and thus has a function as a second detection unit.

[0056] In ACT30, the CPU 321 stops transmitting the carrier wave. In ACT31, the CPU 321 executes error processing in the same manner as in ACT9 in Fig. 4. Thus, at this time, the CPU 321 functions as a processing unit that executes error processing. Once the error processing is completed, the CPU 321 ends this control processing.

[0057] Now, when the CPU 321 has completed reading all of the RFID tags 200 that are the target of reading, it determines NO in ACT24 in FIG. 5 and proceeds to ACT32. In ACT 32, the CPU 321 stops transmitting the carrier wave, and then ends this control process.

[0058] As described above, when a mismatch in impedance matching occurs in the antenna 21 due to a change in the surrounding environment, the reader 100 determines this from a change in the reflected signal and performs impedance matching to achieve a matched state using the matching adjustment unit 19. As a result, even if the impedance of the antenna 21 changes, impedance matching is performed to reduce the self-interference signal, and the self-interference signal can be properly canceled by SJC processing.

[0059] Furthermore, the reader 100 switches between the multiple matching circuits 191 using the switches 192 and 193, so that the antenna impedance can be adjusted at high speed.

[0060] Furthermore, if the matching adjustment unit 19 does not achieve good impedance matching even after selecting all of the matching circuits 191 included in the matching adjustment unit 19, that is, if the matching adjustment unit 19 cannot adjust the impedance to achieve good impedance matching, the reader 100 will notify the operator or the like of this through error processing, since there is a risk that normal reading will not be possible. This enables the operator or the like to take appropriate measures, such as quickly taking measures to improve the surrounding environment that is causing the impedance fluctuation.

[0061] Furthermore, if the impedance matching by the matching adjustment unit 19 is abnormal, the reading device 100 may not be able to perform normal reading, and therefore notifies the operator or the like of this through error processing, allowing the operator or the like to take appropriate measures, such as quickly taking measures to improve the surrounding environment that is causing the impedance fluctuation.

[0062] In this embodiment, the CPU 321 determines that the impedance matching performed by the matching adjuster 19 is abnormal when the return loss is within an abnormal range, for example, "less than 6 dB." When the return loss is 6 dB, 50% of the power supplied to the antenna 21 is reflected at the antenna feed point. Therefore, when the return loss is less than 6 dB, the mismatched reflected power is large, and this power may exceed the maximum input (maximum rating) of the semiconductor element used in the receiving circuit, potentially damaging the element. In some cases, a protection circuit is provided to prevent damage to the semiconductor element. In such cases, the function of the protection circuit may prevent the reader 100 from functioning. For this reason, it is appropriate to perform error processing when the return loss is less than 6 dB.

[0063] This embodiment can be modified in various ways as follows. It may also be realized as a communication device that communicates with a wireless tag such as the RFID tag 200 for a purpose other than reading data stored in the RFID tag 200 from the RFID tag 200 .

[0064] Some or all of the functions realized by the CPU 321 through information processing can be realized by hardware that executes information processing not based on a program, such as a logic circuit, etc. Each of the above functions can also be realized by combining hardware such as the above logic circuit with software control.

[0065] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0066] 100...reader, 200...RFID tag, 11...oscillator, 12...phase shifter, 13...DA converter, 14...quadrature modulator, 15...BPF, 16...power amplifier, 17...LPF, 18...antenna duplexer, 19...matching adjustment unit, 20...feed line, 21...antenna, 22...variable attenuator, 23...variable phase shifter, 24...DA converter, 25...power combiner, 26...quadrature detector, 28...AC coupled amplifier, 29...AD converter, 31...AD converter, 32...control unit, 321...CPU, 322...FPGA, 33...memory, 191...matching circuit, 1911...inductor, 1912...capacitor, 192, 193...switcher.

Claims

1. A communication device that receives a response wave emitted from a wireless tag based on a received carrier wave, The antenna and a first generator that generates a carrier wave; a common unit that receives the carrier wave generated by the first generating unit from an input terminal, outputs the carrier wave to the antenna from an input / output terminal, and outputs the signal input from the antenna to the input / output terminal from an output terminal; a second generator that generates a cancellation signal by changing the amplitude and phase of the carrier wave generated by the first generator; a suppression unit that suppresses a self-interference signal included in the output signal from the output terminal using the cancellation signal generated by the second generation unit; a first detection unit that detects whether impedance matching related to the antenna is in a predetermined mismatch state; an adjustment unit that adjusts the impedance of the antenna so as to eliminate the mismatch state in response to the first detection unit detecting the mismatch state; A communication device equipped with:

2. The adjustment unit a plurality of matching circuits connected to the antenna, each matching a different antenna impedance to a predetermined impedance; a switch that selectively inserts one of the plurality of matching circuits between the input / output terminal and the antenna; a control unit that controls the switch to select the matching circuit whose mismatch state is no longer detected by the first detection unit; 2. The communication device according to claim 1, further comprising:

3. the adjusting unit matches the impedance of the antenna during a period when the response wave radiated from the wireless tag is not received. The communication device according to claim 1 .

4. The second generation unit determines an amount of change in amplitude and phase for generating a cancellation signal after the adjustment unit adjusts the impedance of the antenna. The communication device according to claim 1 .

5. a second detection unit that detects that the antenna is in a predetermined matching difficulty state in which impedance matching becomes difficult; a processing unit that performs a predetermined error process in response to the second detection unit detecting that the matching is difficult; and The communication device of claim 1 further comprising:

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