Method and apparatus for chroma sampling

Abstract

To provide methods and apparatuses for processing chroma sampled pictures.SOLUTION: An exemplary video processing method includes: determining whether a chroma component is included in a sequence of frames; and, in response to a determination that the chroma component is included in the sequence, activating a sub-process for processing the sequence, where the sub-process comprises one or more of joint coding for chroma residues (JCCR), block differential pulse coded modulation (BDPCM), palette mode, or adaptive color transform (ACT).SELECTED DRAWING: Figure 18

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This disclosure claims priority to U.S. Provisional Patent Application No. 62 / 944,345, filed December 5, 2019, the entirety of which is incorporated by reference herein.

[0002] Technical Field

[0002] This disclosure relates generally to video processing, and more particularly to methods and apparatus for processing chroma-sampled pictures. [Background technology]

[0003] background

[0003] A video is a set of static pictures (or "frames") that capture visual information. To reduce storage memory and transmission bandwidth, a video can be compressed before storage or transmission and decompressed before display. The compression process is typically referred to as encoding, and the decompression process is typically referred to as decoding. There are various video coding formats that use standardized video coding techniques, most commonly based on prediction, transform, quantization, entropy coding, and in-loop filtering. Standardization organizations have developed video coding standards that specify specific video coding formats, such as the High Efficiency Video Coding (HEVC / H.265) standard, the Versatile Video Coding (VVC / H.266) standard, and the AVS standard. As more and more advanced video coding techniques are adopted into video standards, the coding efficiency of new video coding standards becomes increasingly higher. Summary of the Invention [Means for solving the problem]

[0004] Disclosure Overview

[0004] In some embodiments, an exemplary video processing method includes determining whether chroma components are included in a sequence of frames, and in response to determining that chroma components are included in the sequence, initiating a sub-process for processing the sequence, the sub-process including one or more of joint coding for chroma residues (JCCR), block differential pulse coded modulation (BDPCM), palette mode, or adaptive color transform (ACT).

[0005] In some embodiments, an exemplary video processing device includes at least one memory for storing instructions and at least one processor configured to execute the instructions to cause the device to determine whether a chroma component is included in a sequence of frames and, in response to determining that the chroma component is included in the sequence, invoke a sub-process for processing the sequence, the sub-process including one or more of Joint Coding of Chroma Residual (JCCR), Block Differential Pulse Code Modulation (BDPCM), Palette Mode, or Adaptive Color Transform (ACT).

[0006] In some embodiments, an exemplary non-transitory computer-readable storage medium stores a set of instructions executable by one or more processing devices to cause a video processing apparatus to determine whether a chroma component is included in a sequence of frames, and in response to determining that the chroma component is included in the sequence, invoke a sub-process for processing the sequence, the sub-process including one or more of Joint Coding of Chroma Residual (JCCR), Block Differential Pulse Code Modulation (BDPCM), Palette Mode, or Adaptive Color Transform (ACT).

[0007] BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Embodiments and various aspects of the present disclosure are illustrated in the following detailed description and the accompanying drawings, in which the various features shown are not drawn to scale. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a schematic diagram illustrating the structure of an exemplary video sequence, according to some embodiments of the present disclosure. [Figure 2]

[0009] 1 shows a schematic diagram of an exemplary encoder of a hybrid video encoding system, according to some embodiments of the present disclosure. [Figure 3]

[0010] 1 shows a schematic diagram of an exemplary decoder of a hybrid video coding system, according to some embodiments of the present disclosure. [Figure 4]

[0011] 1 shows a block diagram of an exemplary apparatus for encoding or decoding video, according to some embodiments of the present disclosure. [Figure 5]

[0012] 1 shows exemplary Table 1 illustrating exemplary chroma formats in Versatile Video Coding (VVC), according to some embodiments of the present disclosure. [Figure 6]

[0013] 1 illustrates exemplary Table 2 showing exemplary chroma format related syntax according to some embodiments of the present disclosure. [Figure 7]

[0014] 10 shows exemplary Table 3 illustrating an exemplary reconstruction of chroma residuals according to some embodiments of the present disclosure. [Figure 8A]

[0015] 10 shows exemplary Table 4 illustrating exemplary Joint Coding of Chroma Residual (JCCR) mode-related syntax according to some embodiments of the present disclosure. [Figure 8B]

[0015] Figure 4 shows an example Table 4 illustrating an example Joint Coding of Chroma Residual (JCCR) mode-related syntax according to some embodiments of the present disclosure. [Figure 9]

[0016] 1 illustrates an example Table 5 illustrating an example block differential pulse code modulation (BDPCM) related syntax, according to some embodiments of the present disclosure. [Figure 10]

[0017] 1 illustrates a schematic diagram of an exemplary block coded in palette mode, according to some embodiments of the present disclosure. [Figure 11]

[0018] 10 shows exemplary Table 6 illustrating exemplary palette mode related syntax according to some embodiments of the present disclosure. [Figure 12]

[0019] 1 shows a schematic diagram of an exemplary decoding process for adaptive color transformation (ACT), according to some embodiments of the present disclosure. [Figure 13]

[0020] 10 shows exemplary Table 7 illustrating exemplary palette mode related syntax according to some embodiments of the present disclosure. [Figure 14]

[0021] 10 shows exemplary Table 8 illustrating an exemplary syntax for signaling whether an encoding tool is enabled, according to some embodiments of the present disclosure. [Figure 15]

[0022] 10 shows exemplary Table 9 illustrating an exemplary syntax for signaling whether an encoding tool is enabled, according to some embodiments of the present disclosure. [Figure 16]

[0023] 10 shows exemplary Table 10 illustrating an exemplary syntax for signaling whether an encoding tool is enabled, according to some embodiments of the present disclosure. [Figure 17]

[0024] 10 shows exemplary Table 11 illustrating an exemplary syntax for signaling whether an encoding tool is enabled, according to some embodiments of the present disclosure. [Figure 18]

[0025] 1 shows a flowchart of an exemplary video processing method according to some embodiments of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0009] Detailed Description

[0026] Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. The following description refers to the accompanying drawings in which like reference numerals in different drawings represent the same or similar elements unless otherwise indicated. The implementations set forth in the following description of exemplary embodiments do not represent all implementations in accordance with the present disclosure. Rather, they are merely examples of apparatus and methods in accordance with aspects related to the present disclosure as recited in the appended claims. Particular aspects of the present disclosure are described in more detail below. In the event of a conflict with terms and / or definitions incorporated by reference, the terms and definitions provided herein shall control.

[0010]

[0027] The ITU-T Video Coding Expert Group (ITU-T VCEG) and the ISO / IEC Moving Picture Expert Group (ISO / IEC MPEG) Joint Video Experts Team (JVET) are currently developing the Versatile Video Coding (VVC / H.266) standard. The VVC standard aims to double the compression efficiency of its predecessor, the High Efficiency Video Coding (HEVC / H.265) standard. In other words, the goal of VVC is to achieve the same subjective quality as HEVC / H.265 while using half the bandwidth.

[0011]

[0028] To achieve the same subjective quality as HEVC / H.265 using half the bandwidth, JVET is developing a technology that goes beyond HEVC using the joint exploration model (JEM) reference software. Because the coding technology has been incorporated into JEM, JEM has achieved substantially higher coding performance than HEVC. VCEG and MPEG have officially begun development of a next-generation video compression standard that will surpass HEVC.

[0012]

[0029] The VVC standard is a recent development and continues to incorporate more coding techniques that result in better compression performance. VVC is based on the same hybrid video coding system that has been used in modern video compression standards such as HEVC, H.264 / AVC, MPEG2, H.263, etc.

[0013]

[0030] A video is a set of static pictures (or "frames") arranged in time sequence to store visual information. A video capture device (e.g., a camera) can be used to capture and store these pictures in time sequence, and a video playback device (e.g., a television, a computer, a smartphone, a tablet computer, a video player, or any end-user terminal with display capabilities) can be used to display such pictures in time sequence. In some applications, a video capture device can also transmit the captured video in real time to a video playback device (e.g., a computer with a monitor) for purposes such as supervision, conferencing, or live broadcasting.

[0014]

[0031] To reduce the storage space and transmission bandwidth required by such applications, video can be compressed before storage and transmission and decompressed before display. Compression and decompression can be implemented by software executed by a processor (e.g., a processor in a general-purpose computer) or by specialized hardware. A module for compression is commonly referred to as an “encoder,” and a module for decompression is commonly referred to as a “decoder.” Encoders and decoders can be collectively referred to as a “codec.” Encoders and decoders can be implemented as any of a variety of suitable hardware, software, or combinations thereof. For example, hardware implementations of encoders and decoders can include circuitry such as one or more microprocessors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), discrete logic, or any combination thereof. Software implementations of encoders and decoders can include program code, computer-executable instructions, firmware, or any suitable computer-implemented algorithms or processes fixed in a computer-readable medium. Video compression and decompression may be performed by various algorithms or standards, such as MPEG-1, MPEG-2, MPEG-4, the H.26x series, or the like. In some applications, a codec may decompress video from a first encoding standard and recompress the decompressed video using a second encoding standard. In this case, the codec may be referred to as a "transcoder."

[0015]

[0032] A video coding process can identify and retain useful information that can be used to reconstruct a picture and ignore information that is not important for reconstruction. If the ignored, unimportant information cannot be perfectly reconstructed, such a coding process may be called "lossy." Otherwise, it may be called "lossless." Most coding processes are lossy; this is a tradeoff to reduce the required storage space and transmission bandwidth.

[0016]

[0033] Useful information about the picture being coded (called the "current picture") includes changes relative to a reference picture (e.g., a previously coded and reconstructed picture). Such changes may include changes in pixel position, brightness, or color, of which position changes are of most interest. Changes in the position of a group of pixels representing an object may reflect the movement of the object between the reference picture and the current picture.

[0017]

[0034] A picture that is coded without reference to another picture (i.e., it is its own reference picture) is called an "I-picture." A picture that is coded using a previous picture as a reference picture is called a "P-picture." A picture that is coded using both a previous picture and a future picture as a reference picture (i.e., the referencing is "bidirectional") is called a "B-picture."

[0018]

[0035] 1 illustrates the structure of an exemplary video sequence 100 according to some embodiments of the present disclosure. The video sequence 100 can be live video or captured and archived video. The video 100 can be real video, computer-generated video (e.g., computer game video), or a combination thereof (e.g., real video with augmented reality effects). The video sequence 100 can be input from a video capture device (e.g., a camera), a video archive containing previously captured video (e.g., video files stored in a storage device), or a video supply interface (e.g., a video broadcast transceiver) for receiving video from a video content provider.

[0019]

[0036] As shown in FIG. 1, video sequence 100 may include a series of pictures arranged temporally along a timeline, including pictures 102, 104, 106, and 108. Pictures 102-106 are consecutive, with additional pictures between pictures 106 and 108. In FIG. 1, picture 102 is an I-picture, and its reference picture is picture 102 itself. Picture 104 is a P-picture, and its reference picture is picture 102, as indicated by the arrow. Picture 106 is a B-picture, and its reference pictures are pictures 104 and 108, as indicated by the arrows. In some embodiments, the reference picture of a picture (e.g., picture 104) need not immediately precede or follow that picture. For example, the reference picture of picture 104 can be a picture before picture 102. It should be noted that the reference pictures of pictures 102-106 are merely examples, and this disclosure does not limit the reference picture embodiments to the examples shown in FIG.

[0020]

[0037] Typically, video codecs do not encode or decode an entire picture at once due to the computational complexity of such a task. Rather, they may divide a picture into elementary segments and encode or decode the picture segment by segment. Such elementary segments are referred to as basic processing units ("BPUs") in this disclosure. For example, structure 110 in FIG. 1 shows an example structure of a picture (e.g., any of pictures 102-108) of video sequence 100. In structure 110, a picture is divided into 4x4 basic processing units, the boundaries of which are shown as dashed lines. In some embodiments, a basic processing unit may be referred to as a "macroblock" in some video coding standards (e.g., MPEG family, H.261, H.263, or H.264 / AVC) or as a "coding tree unit" ("CTU") in some other video coding standards (e.g., H.265 / HEVC or H.266 / VVC). The basic processing units can have variable sizes in pictures or any arbitrary shape and size of pixels, such as 128x128, 64x64, 32x32, 16x16, 4x8, 16x32, etc. The size and shape of the basic processing unit can be selected based on a balance between coding efficiency and the level of detail to be maintained in the basic processing unit for the picture.

[0021]

[0038] A basic processing unit may be a logical unit that can include groups of different types of video data stored in computer memory (e.g., in a video frame buffer). For example, a basic processing unit for a color picture may include a luma component (Y) that represents colorless luminance information, one or more chroma components (e.g., Cb and Cr) that represent color information, and related syntax elements, where the luma and chroma components may have the same size of a basic processing unit. The luma and chroma components may be referred to as "coding tree blocks" (CTBs) in some video coding standards (e.g., H.265 / HEVC or H.266 / VVC). Any operation performed on a basic processing unit may be performed repeatedly on each of its luma and chroma components.

[0022]

[0039] Video coding has multiple computational stages, examples of which are shown in FIGS. 2 and 3. At each stage, the size of the basic processing unit may still become too large for processing and therefore may be further divided into segments referred to as "basic processing subunits" in this disclosure. In some embodiments, the basic processing subunits may be referred to as "blocks" in some video coding standards (e.g., MPEG family, H.261, H.263, or H.264 / AVC) or as "coding units" ("CUs") in some other video coding standards (e.g., H.265 / HEVC or H.266 / VVC). The basic processing subunits may have the same or smaller size as the basic processing units. Similar to the basic processing units, the basic processing subunits are also logical units that can contain groups of different types of video data (e.g., Y, Cb, Cr, and related syntax elements) stored in computer memory (e.g., in a video frame buffer). Any operation performed on a basic processing subunit may be repeatedly performed on each of its luma and chroma components. It should be noted that such division may be carried to further levels as required for processing. It should also be noted that different stages may use different schemes to divide the basic processing units.

[0023]

[0040] For example, in a mode decision stage (an example of which is shown in FIG. 2), an encoder can decide what prediction mode (e.g., intra-picture prediction or inter-picture prediction) to use for a basic processing unit, but the basic processing unit may be too large to make such a decision. The encoder can divide the basic processing unit into multiple basic processing sub-units (e.g., CUs, as in the case of H.265 / HEVC or H.266 / VVC) and decide the type of prediction for each individual basic processing sub-unit.

[0024]

[0041] As another example, in the prediction stage (an example of which is shown in FIG. 2), the encoder may perform prediction operations at the level of basic processing subunits (e.g., CUs). However, in some cases, the basic processing subunits may still be too large to process. The encoder may further divide the basic processing subunits into smaller segments (e.g., referred to as "prediction blocks" or "PBs" in H.265 / HEVC or H.266 / VVC), at which level the prediction operations may be performed.

[0025]

[0042] As another example, in the transform stage (an example of which is shown in FIG. 2), the encoder may perform transform operations for residual basic processing sub-units (e.g., CUs). However, in some cases, the basic processing sub-units may still be too large to process. The encoder may further divide the basic processing sub-units into smaller segments (e.g., referred to as "transform blocks" or "TBs" in H.265 / HEVC or H.266 / VVC), at which levels the transform operations may be performed. Note that the division scheme of the same basic processing sub-unit may be different in the prediction stage and the transform stage. For example, in H.265 / HEVC or H.266 / VVC, the prediction blocks and transform blocks of the same CU may have different sizes and numbers.

[0026]

[0043] 1, the fundamental processing unit 112 is further divided into 3x3 fundamental processing sub-units, the boundaries of which are shown as dotted lines. Different fundamental processing units of the same picture may be divided into fundamental processing sub-units in different ways.

[0027]

[0044] In some implementations, to provide parallel processing and error resilience capabilities to video encoding and decoding, a picture can be divided into regions for processing, so that the encoding or decoding process does not rely on information about a picture region from any other region of the picture. In other words, each region of a picture can be processed independently. By doing so, a codec can process different regions of a picture in parallel, thus increasing coding efficiency. Also, when data for a region is corrupted during processing or lost during network transmission, the codec can correctly encode or decode other regions of the same picture without relying on the corrupted or lost data, thus providing error resilience. Some video coding standards allow a picture to be divided into different types of regions. For example, H.265 / HEVC and H.266 / VVC provide two types of regions: "slices" and "tiles." It should also be noted that different pictures in video sequence 100 can have different partitioning schemes for dividing the picture into regions.

[0028]

[0045] For example, in Figure 1, structure 110 is divided into three regions 114, 116, and 118, the boundaries of which are shown as solid lines within structure 110. Region 114 includes four basic processing units. Regions 116 and 118 each include six basic processing units. It should be noted that the basic processing units, basic processing subunits, and regions of structure 110 in Figure 1 are merely examples, and the present disclosure does not limit the embodiments thereof.

[0029]

[0046] 2 shows a schematic diagram of an example encoder 200 of a hybrid video coding system according to some embodiments of this disclosure. The video encoder 200 may perform intra- or inter-coding of blocks within video frames, including video blocks or partitions or sub-partitions of video blocks. Intra-coding may rely on spatial prediction to reduce or remove spatial redundancy in video within a given video frame. Inter-coding may rely on temporal prediction to reduce or remove temporal redundancy in video within adjacent frames of a video sequence. Intra-mode may refer to a number of spatial-based compression modes. Inter-mode (e.g., uni-predictive or bi-predictive) may refer to a number of temporal-based compression modes.

[0030]

[0047] Referring to FIG. 2, the input video signal 202 may be processed block by block. For example, a video block unit may be a 16x16 pixel block (e.g., a macroblock (MB)). The size of the video block unit may vary depending on the encoding technique used and the required accuracy and efficiency. In HEVC, extended block sizes (e.g., coding tree units (CTUs)) may be used to compress video signals with resolutions of, for example, 1080p or higher. In HEVC, a CTU may contain up to 64x64 luma samples, corresponding chroma samples, and associated syntax elements. In VVC, the size of the CTU may be further increased to contain 128x128 luma samples, corresponding chroma samples, and associated syntax elements. The CTU may be further divided into coding units (CUs), for example, using a quad tree, a binary tree, or a ternary tree. The CUs may be further partitioned into prediction units (PUs), and separate prediction methods may be applied to the PUs. Each input video block may be processed using a spatial prediction unit 260 or a temporal prediction unit 262.

[0031]

[0048] Spatial prediction unit 260 performs spatial prediction (e.g., intra-prediction) on the current block / CU using information about the same picture / slice that contains the current block. Spatial prediction can use pixels from already-encoded neighboring blocks of the same video picture frame / slice to predict the current video block. Spatial prediction can reduce spatial redundancy inherent in video signals.

[0032]

[0049] Temporal prediction unit 262 performs temporal prediction (e.g., inter-prediction) on the current block using information from a picture / slice different from the picture / slice containing the current block. Temporal prediction for a video block may be signaled by one or more motion vectors. Unidirectional temporal prediction uses only one motion vector, pointing to one reference picture, to generate a prediction for the current block. Bidirectional temporal prediction, on the other hand, may use two motion vectors, each pointing to a respective reference picture, to generate a prediction for the current block. A motion vector may indicate the amount and direction of motion between the current block and one or more associated blocks in a reference frame. If multiple reference pictures are supported, one or more reference picture indexes may be transmitted for the video block. The one or more reference indexes may be used to identify which reference picture in a reference picture store or decoded picture buffer (DPB) 264 the temporal prediction comes from.

[0033]

[0050] The encoder mode decision and encoder control unit 280 may select a prediction mode based on, for example, rate-distortion optimization. Based on the determined prediction mode, a prediction block may be obtained. The prediction block may be subtracted from the current video block in summer 216. The prediction residual may be transformed by transform unit 204 and quantized by quantization unit 206. The quantized residual coefficients may be inverse quantized in inverse quantization unit 210 and inverse transformed in inverse transform unit 212 to form a reconstructed residual. The reconstructed residual may be added to the prediction block in summer 226 to form a reconstructed video block. The reconstructed video block before loop filtering may be used to provide reference samples for intra prediction.

[0034]

[0051] The reconstructed video block may undergo a loop filtering process in loop filter 266. For example, loop filtering such as a deblocking filter, sample adaptive offset (SAO), and adaptive loop filter (ALF) may be applied. The reconstructed block after loop filtering may be stored in reference picture store 264 and used to provide inter-prediction reference samples for encoding other video blocks. To form output video bitstream 220, the coding mode (e.g., inter or intra), prediction mode information, motion information, and quantized residual coefficients may be sent to entropy coding unit 208 to further reduce the bitrate before data is compressed and packed to form bitstream 220.

[0035]

[0052] 3 shows a schematic diagram of an example decoder 300 of a hybrid video coding system according to some embodiments of this disclosure. Referring to FIG. 3, a video bitstream 302 can be unpacked or entropy decoded in an entropy decoding unit 308. Coding mode information can be used to determine whether to select a spatial prediction unit 360 or a temporal prediction unit 362. The prediction mode information can be sent to a corresponding prediction unit to generate a prediction block. For example, motion compensation prediction can be applied by the temporal prediction unit 362 to form a temporal prediction block.

[0036]

[0053] The residual coefficients may be sent to an inverse quantization unit 310 and an inverse transform unit 312 to obtain a reconstructed residual. The prediction block and the reconstructed residual may be summed at 326 to form a reconstructed block before loop filtering. The reconstructed block may then undergo a loop filtering process at a loop filter 366. For example, loop filtering such as a deblocking filter, SAO, and ALF may be applied. The reconstructed block after loop filtering may then be stored in a reference picture store 364. The reconstructed data in the reference picture store 364 may be used to obtain a decoded video 320 or to predict future video blocks. The decoded video 320 may be displayed on a display device, such as a TV, PC, smartphone, or tablet, for viewing by an end user.

[0037]

[0054] 4 is a block diagram of an exemplary device 400 for encoding or decoding video, according to an embodiment of the present disclosure. As shown in FIG. 4, the device 400 may include a processor 402. When the processor 402 executes instructions described herein, the device 400 can become a specialized machine for video encoding or decoding. The processor 402 can be any type of circuitry capable of manipulating or processing information. For example, processor 402 may include any number and combination of a central processing unit (or "CPU"), a graphics processing unit (or "GPU"), a neural processing unit ("NPU"), a microcontroller unit ("MCU"), an optical processor, a programmable logic controller, a microcontroller, a microprocessor, a digital signal processor, an intellectual property (IP) core, a programmable logic array (PLA), a programmable array logic (PAL), a generic array logic (GAL), a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a system on chip (SoC), an application-specific integrated circuit (ASIC), or the like. In some embodiments, processor 402 may also be a set of processors grouped as a single logical entity. For example, as shown in FIG. 4, processor 402 may include multiple processors, including processor 402a, processor 402b, and processor 402n.

[0038]

[0055] The device 400 may also include a memory 404 configured to store data (e.g., a set of instructions, computer code, intermediate data, or the like). For example, as shown in FIG. 4, the stored data may include program instructions (e.g., program instructions for implementing steps in FIG. 2 or FIG. 3) as well as data for processing. The processor 402 may access the program instructions and data for processing (e.g., via a bus 410), execute the program instructions, and perform operations or manipulations on the data for processing. The memory 404 may include a high-speed random-access storage device or a non-volatile storage device. In some embodiments, the memory 404 may include any number or combination of random-access memory (RAM), read-only memory (ROM), optical disk, magnetic disk, hard drive, solid-state drive, flash drive, security digital (SD) card, memory stick, compact flash (CF) card, or the like. The memory 404 can also be a group of memories (not shown in FIG. 4) grouped as a single logical entity.

[0039]

[0056] Bus 410 can be a communication device that transfers data between components internal to apparatus 400, such as an internal bus (e.g., a CPU-memory bus), an external bus (e.g., a Universal Serial Bus port, a Peripheral Component Interconnect Express port), or the like.

[0040]

[0057] For ease of explanation and without ambiguity, the processor 402 and other data processing circuitry will be collectively referred to in this disclosure as "data processing circuitry." The data processing circuitry may be implemented entirely as hardware or as a combination of software, hardware, or firmware. Additionally, the data processing circuitry may be a single, independent module or may be fully or partially combined with any other component of the device 400.

[0041]

[0058] The device 400 may further include a network interface 406 for providing wired or wireless communication with a network (e.g., the Internet, an intranet, a local area network, a mobile communication network, or the like). In some embodiments, the network interface 406 may include any number or combination of a network interface controller (NIC), a radio frequency (RF) module, a transponder, a transceiver, a modem, a router, a gateway, a wired network adapter, a wireless network adapter, a Bluetooth® adapter, an infrared adapter, a near-field communication ("NFC") adapter, a cellular network chip, or the like.

[0042]

[0059] In some embodiments, apparatus 400 may optionally further include a peripheral interface 408 for providing connection to one or more peripheral devices. As shown in Figure 4, the peripheral devices may include, but are not limited to, a cursor control device (e.g., a mouse, a touchpad, or a touchscreen), a keyboard, a display (e.g., a cathode ray tube display, a liquid crystal display, or a light emitting diode display), a video input device (e.g., a camera, or an input interface coupled to a video archive), or the like.

[0043]

[0060] It should be noted that the video codec may be implemented as any combination of software or hardware modules within the device 400. For example, some or all of the stages of the encoder 200 of Figure 2 or the decoder 300 of Figure 3 may be implemented as one or more software modules of the device 400, such as program instructions that may be loaded into the memory 404. As another example, some or all of the stages of the encoder 200 of Figure 2 or the decoder 300 of Figure 3 may be implemented as one or more hardware modules of the device 400, such as specialized data processing circuits (e.g., FPGAs, ASICs, NPUs, or the like).

[0044]

[0061] In the quantization and inverse quantization functional blocks (e.g., quantization unit 206 and inverse quantization unit 210 in FIG. 2, inverse quantization unit 310 in FIG. 3), a quantization parameter (QP) is used to determine the amount of quantization (and inverse quantization) applied to the prediction residual. The initial QP value used for coding a picture or slice can be signaled at a high level, for example, using the init_qp_minus26 syntax element in the picture parameter set (PPS) and the slice_qp_delta syntax element in the slice header. Furthermore, the QP value can be adapted at a local level for each CU using a delta QP value sent at the granularity of the quantization group.

[0045]

[0062] In some embodiments of the present disclosure, four chroma sampling formats (i.e., monochrome, 4:2:0, 4:2:2, and 4:4:4) are supported. In monochrome sampling, there is only one sample array, which is nominally considered the luma array. In 4:2:0 sampling, each of the two chroma arrays has half the height and half the width of the luma array. In 4:2:2 sampling, each of the two chroma arrays has the same height and half the width of the luma array. In 4:4:4 sampling, depending on the high-level flag setting (e.g., the syntax element separate_color_plane_flag in Table 1 of FIG. 5), it is possible to process the three color planes separately as a monochrome sampled picture, or each of the two chroma arrays can have the same height and width as the luma array. Figure 5 shows exemplary Table 1 illustrating exemplary chroma formats in VVC, according to some embodiments of the present disclosure. As shown in Table 1 of FIG. 5, SubWidthC and SubHeightC represent the width and height of the chroma array, respectively.

[0046]

[0063] 6 shows an example Table 2 illustrating an example chroma format related syntax according to some embodiments of the present disclosure. As shown in Table 2 of FIG. 6 (highlighted portions are shown in italics), the chroma format for a sequence is signaled in the Sequence Parameter Set (SPS). The variables of ChromaArrayType can be derived using the signaled chroma format using the following rules: Depending on the value of the syntax element separate_colour_plane_flag, the values ​​of the variables of ChromaArrayType are assigned as follows: - If the separate_colour_plane_flag syntax element is equal to 0, ChromaArrayType is set equal to chroma_format_idc. - Otherwise, ChromaArrayType is set equal to 0.

[0047]

[0064] Note that ChromaArrayType equal to 0 indicates a monochrome format with no chroma components present.

[0048]

[0065] According to an embodiment of the present disclosure, various coding tools can be supported to improve chroma coding performance, including joint coding of chroma residual (JCCR), block differential pulse code modulation (BDPCM), adaptive color transformation (ACT), and palette mode. In this disclosure, these tools are referred to as sub-processes.

[0049]

[0066] Embodiments of the present disclosure may support a mode in which chroma residuals are jointly coded. When a transform unit (TU) is coded using this mode, only a single joint chroma residual block is signaled, instead of separately signaling Cb and Cr chroma residuals. Figure 7 shows an example Table 3 illustrating an example reconstruction of chroma residuals according to some embodiments of the present disclosure. As shown in Table 3 of Figure 7, two chroma residual (resCb and resCr) blocks are derived using the transmitted joint chroma residual block (resJointC), tu_cbf_cb, tu_cbf_cr, and CSign. The syntax elements tu_cbf_cb and tu_cbf_cr are two flags signaled at the TU level that indicate whether residuals are present. CSign is a sign value specified in the slice header.

[0050]

[0067] A flag in the SPS (e.g., the syntax element sps_joint_cbcr_enabled_flag in Table 4 of FIG. 8) is signaled first to indicate whether JCCR mode is supported for the current sequence. FIG. 8 shows exemplary Table 4 illustrating exemplary JCCR mode-related syntax according to some embodiments of the present disclosure. As shown in Table 4 (highlighted portions are in italics), when the syntax element sps_joint_cbcr_enabled_flag is true, flags in the picture header, slice header, and transform unit are further signaled.

[0051]

[0068] Embodiments of the present disclosure can support block differential pulse code modulation for screen content coding. For a block size of M (height) × N (width), r i,j Let (0≦i≦M-1, 0≦j≦N-1) be the prediction residual. Q(r i,j )(0≦i≦M-1, 0≦j≦N-1) is the residual r i,j Let denote the quantized version of . BDPCM is applied to the quantized residual values, and the element

number

number

number

number

number

[0052]

[0069] In the case of horizontal BDPCM prediction mode (0≦i≦(M-1)), the following equation (2) is used:

number

number

[0053]

[0070] At the decoder side, the above process is reversed to obtain Q(r i,j ) (0≦i≦M-1, 0≦j≦N-1).

number

number

[0054]

[0071] FIG. 9 shows exemplary Table 5 illustrating exemplary BDPCM-related syntax according to some embodiments of the present disclosure. At the sequence level, a BDPCM enable flag (e.g., syntax element sps_bdpcm_enabled_flag) is signaled in SPS. This flag is signaled in SPS only if transform skip mode is enabled, as shown in Table 5 of FIG. 9 (highlighted portions are italicized). When BDPCM is enabled, a flag (e.g., syntax element intra_bdpcm_luma_flag or intra_bdpcm_chroma_flag) is transmitted at the CU level. This flag indicates whether regular intra coding or BDPCM is used. When BDPCM is used, a BDPCM prediction direction flag (e.g., syntax element intra_bdpcm_luma_dir_flag or intra_bdpcm_chroma_dir_flag) is transmitted to indicate whether the prediction is horizontal or vertical.

[0055]

[0072] Embodiments of the present disclosure support a palette mode for use with screen content encoded in 4:4:4 chroma format. FIG. 10 shows a schematic diagram of an exemplary block encoded in palette mode, according to some embodiments of the present disclosure. As shown in FIG. 10, when palette mode is utilized, sample values ​​(e.g., positions 1001-1004) of a CU (e.g., block 1000) are represented by a small set of representative color values. The set is referred to as a palette (e.g., palette 1010). For pixels with values ​​close to palette colors, a palette index is signaled. It is also possible to specify samples outside the palette by signaling an escape symbol followed by a quantized component value.

[0056]

[0073] 11 shows an example Table 6 illustrating an example palette mode-related syntax for signaling whether palette mode is enabled according to some embodiments of the present disclosure. As shown in Table 6 of FIG. 11 (highlighted portions are italicized), if the chroma format of a sequence is 4:4:4, a flag in the SPS (e.g., a syntax element called sps_palette_enabled_flag) is signaled to indicate whether palette mode is enabled for this sequence. When palette mode is enabled, a flag indicating whether palette mode is used is sent at the CU level if the CU size is 64x64 or smaller.

[0057]

[0074] Embodiments of the present disclosure support adaptive color transformation in 4:4:4 chroma format. Color space transformation is performed in the residual domain. FIG. 12 shows a schematic diagram of an example decoding process 1200 for adaptive color transformation (ACT) according to some embodiments of the present disclosure. As shown in FIG. 12, an inverse ACT module 1204 is used to transform the residual from the YCgCo domain back to the original domain. Specifically, the forward and inverse YCgCo color transformation matrices are applied in the following equations (5) and (6), respectively. C0, C1, and C2 represent pixel values ​​in the original domain, and C'0, C'1, and C'2 represent pixel values ​​in the YCgCo domain.

number

[0058]

[0075] 13 shows an example Table 7 illustrating an example palette mode-related syntax according to some embodiments of the present disclosure. As shown in Table 7 of FIG. 13, when the chroma format of a sequence is 4:4:4, a flag of the SPS (e.g., a syntax element called sps_act_enabled_flag) is signaled to indicate whether ACT is enabled for this sequence. When ACT is enabled, a flag indicating whether ACT is applied is sent at the CU level.

[0059]

[0076] In some embodiments of the present disclosure, some of the above-mentioned chroma encoding tools are supported and applied to chroma components to improve encoding efficiency. However, due to the above-mentioned settings of the chroma format, there may be no available chroma components to apply these tools to. In particular, when a sequence is in 4:4:4 chroma format and the syntax element separate_colour_plane_flag is equal to "true," all three chroma components are considered monochrome, and there are effectively no chroma components to encode this sequence. In this case, the JCCR, BDPCM, and ACT flags are still signaled in the SPS, which is redundant. Furthermore, there is an inconsistency in palette mode design. Palette mode cannot be enabled for monochrome cases (e.g., 4:0:0 color format), but it can be enabled for 4:4:4 chroma formats with the syntax element separate_colour_plane_flag equal to "true."

[0060]

[0077] The present disclosure provides an apparatus and method for improving coding efficiency for applying JCCR, BDPCM, palette mode, and ACT to chroma components. According to the disclosed embodiments, a video codec determines whether to enable JCCR, BDPCM, palette mode, and / or ACT based on whether a chroma component is present.

[0061]

[0078] In some embodiments, the JCCR, BDPCM, and ACT flags in the SPS are signaled only when a chroma component is present. Figure 14 shows exemplary Table 8 illustrating proposed changes to the existing syntax according to some embodiments of the present disclosure, and Figure 15 shows exemplary Table 9 illustrating proposed changes to the existing syntax according to some embodiments of the present disclosure. As shown in Table 8 of Figure 14 and Table 9 of Figure 15, the proposed changes to the existing syntax are italicized in boxes 1401-1405 and boxes 1505-1505, respectively.

[0062]

[0079] In Table 8 of FIG. 14 and Table 9 of FIG. 15, the condition "ChromaArrayType!=0" can be replaced with "separate_colour_plane_flag!=1&&chroma_format_idc!=0".

[0063]

[0080] FIG. 16 shows an example Table 10 illustrating proposed changes to the existing syntax according to some embodiments of the present disclosure. As shown in Table 10 of FIG. 16, the proposed changes to the existing syntax are italicized in boxes 1601-1604. The SPS palette flag (e.g., the syntax element sps_palette_enabled_flag) is signaled when the chroma format is 4:4:4 and when chroma components are present (e.g., the syntax element separate_colour_plane_flag is equal to 0). In Table 10 of FIG. 16, the condition "ChromaArrayType != 0" can be replaced with "separate_colour_plane_flag != 1 && chroma_format_idc != 0".

[0064]

[0081] FIG. 17 shows an example Table 11 illustrating proposed changes to the existing syntax according to some embodiments of the present disclosure. As shown in Table 11 of FIG. 17, the proposed changes to the existing syntax are italicized in boxes 1701-1705. As shown in Table 11 of FIG. 17, palette mode is enabled for both 4:4:4 and 4:0:0 chroma formats. The condition "ChromaArrayType != 0" can be replaced with "separate_colour_plane_flag != 1 && chroma_format_idc != 0".

[0065]

[0082] In some embodiments, rather than not signaling the JCCR, BDPCM and ACT flags in the SPS when no chroma components are present, bitstream adaptation is added to these flags.

[0066]

[0083] The syntax element sps_joint_cbcr_enabled_flag equal to "0" specifies that joint coding of chroma residual is disabled. The syntax element sps_joint_cbcr_enabled_flag equal to "1" specifies that joint coding of chroma residual is enabled. It is a bitstream conformance requirement that the value of sps_joint_cbcr_enabled_flag be equal to 0 when ChromaArrayType is equal to 0.

[0067]

[0084] A syntax element sps_bdpcm_chroma_enabled_flag equal to "1" specifies that intra_bdpcm_chroma_flag is present in the coding unit syntax for an intra coding unit. A syntax element sps_bdpcm_chroma_enabled_flag equal to "0" specifies that intra_bdpcm_chroma_flag is not present in the coding unit syntax for an intra coding unit. If not present, a value of sps_bdpcm_chroma_enabled_flag equal to 0 is inferred. A value of sps_bdpcm_chroma_enabled_flag equal to 0 when ChromaArrayType is equal to 0 is a bitstream conformance requirement.

[0068]

[0085] The sps_act_enabled_flag syntax element equal to 1 specifies that adaptive color transforms can be used and cu_act_enabled_flag may be present in the coding unit syntax. The sps_act_enabled_flag syntax element equal to 0 specifies that adaptive color transforms are not used and cu_act_enabled_flag is not present in the coding unit syntax. When sps_act_enabled_flag is not present, it is inferred to be equal to 0. It is a bitstream conformance requirement that the value of sps_act_enabled_flag be equal to 0 when ChromaArrayType is equal to 0.

[0069]

[0086] In the above bitstream compatibility conditions, the condition "ChromaArrayType!=0" can be replaced with "separate_colour_plane_flag!=1&&chroma_format_idc!=0".

[0070]

[0087] 18 shows a flowchart of an exemplary video processing method 1800 according to some embodiments of the present disclosure. Method 1800 may be performed by one or more software or hardware components of an encoder (e.g., encoder 200 of FIG. 2), a decoder (e.g., decoder 300 of FIG. 3), or an apparatus (e.g., apparatus 400 of FIG. 4). For example, a processor (e.g., processor 402 of FIG. 4) may perform method 1800. In some embodiments, method 1800 may be implemented by a computer program product embodied in a computer-readable medium that includes computer-executable instructions, such as program code, for execution by a computer (e.g., apparatus 400 of FIG. 4).

[0071]

[0088] In step 1801, a determination may be made as to whether chroma components are included in a sequence of frames. For example, the sequence of frames may be an input video (e.g., input video 202 in FIG. 2) or a bitstream (e.g., bitstream 220 in FIG. 2 or bitstream 302 in FIG. 3). In some embodiments, method 1800 may include determining that chroma components are included in the sequence based on a chroma format and a separate color plane flag. The chroma format may include a monochrome type, a 4:2:0 sampling type, a 4:2:2 sampling type, or a 4:4:4 sampling type. For example, a variable of ChromaArrayType may be determined as follows: - If the separate_colour_plane_flag syntax element is equal to 0, ChromaArrayType is set equal to chroma_format_idc. - Otherwise, ChromaArrayType is set equal to 0.

[0072]

[0089] The syntax elements separate_colour_plane_flag and chroma_format_idc can be determined according to Table 1 in Figure 5. ChromaArrayType equal to 0 indicates that no chroma components are present in the sequence, and ChromaArrayType not equal to 0 indicates that chroma components are present in the sequence.

[0073]

[0090] In some embodiments, method 1800 may include determining whether a separate color plane flag (e.g., a syntax element called separate_colour_plane_flag in Table 1 of FIG. 5 or Table 2 of FIG. 6) is true or false, and determining that a chroma component is included in the sequence in response to determining that the separate color plane flag is false.

[0074]

[0091] In step 1803, in response to determining that a chroma component is included in the sequence, a sub-process may be launched to process the chroma component. The sub-process may include one or more of JCCR, BDPCM, palette mode, or ACT. In some embodiments, method 1800 may include signaling a sub-process enable flag in the SPS indicating whether the sub-process is enabled. For example, a syntax element named sps_joint_cbcr_enabled_flag (e.g., as shown in Table 8 of FIG. 14, Table 9 of FIG. 15, Table 10 of FIG. 16, or Table 11 of FIG. 17) may be signaled to indicate whether JCCR is enabled. A syntax element named sps_bdpcm_chroma_enabled_flag (e.g., as shown in Table 8 of FIG. 14, Table 9 of FIG. 15, Table 10 of FIG. 16, or Table 11 of FIG. 17) may be signaled to indicate whether BDPCM is enabled. A syntax element sps_palette_enabled_flag (e.g., as shown in Table 10 of FIG. 16 ) may be signaled to indicate whether palette mode is enabled. A syntax element sps_act_enabled_flag (e.g., as shown in Table 8 of FIG. 14 , Table 9 of FIG. 15 , Table 10 of FIG. 16 , or Table 11 of FIG. 17 ) may be signaled to indicate whether ACT is enabled. In some embodiments, method 1800 may also include invoking a sub-process for processing the chroma component in response to the sub-process enable flag indicating that the sub-process is enabled. In some embodiments, in response to determining that the chroma component is not included in the sequence, the sub-process enable flag indicates that the sub-process is not enabled. For example, if ChromaArrayType is equal to 0, then the following syntax elements may be equal to 0: sps_joint_cbcr_enabled_flag, sps_bdpcm_chroma_enabled_flag, sps_palette_enabled_flag, or sps_act_enabled_flag.

[0075]

[0092] In some embodiments, the sequence can be processed using the invoked sub-process. For example, the sequence can be processed based on Table 4 of Figure 8, Table 5 of Figure 9, Table 6 of Figure 11, Table 4 of Figure 8, Table 7 of Figure 13, Table 8 of Figure 14, Table 9 of Figure 15, Table 10 of Figure 16, or Table 11 of Figure 17.

[0076]

[0093] It will be understood that embodiments of the present disclosure can be combined with one another or with several other embodiments.

[0077]

[0094] The embodiments may be further described using the following clauses: 1. A video processing method comprising: determining whether a chroma component is included in a sequence of frames; initiating a sub-process for processing the sequence in response to determining that the chroma component is included in the sequence; A method, wherein the sub-processes include one or more of joint coding of chroma residual (JCCR), block differential pulse code modulation (BDPCM), palette mode, or adaptive color transformation (ACT). 2. Determining whether a chroma component is included in a sequence is Determining that a chroma component is included in a sequence based on the chroma format and a separate color plane flag. 2. The method according to clause 1, comprising: 3. The method according to clause 2, wherein the chroma format includes a monochrome type, a 4:2:0 sampling type, a 4:2:2 sampling type, or a 4:4:4 sampling type. 4. Determining whether a chroma component is included in a sequence is determining values ​​of separate color plane flags; determining that a chroma component is included in the sequence in response to determining that the separate color plane flag has a first value; 4. The method of any one of clauses 1 to 3, comprising: 5. Launching a subprocess to process the chroma components Signaling a flag in the Sequence Parameter Set (SPS) that indicates whether a subprocess is enabled 5. The method of any one of clauses 1 to 4, comprising: 6. Launching a subprocess to process the chroma components Initiating a sub-process for processing a chroma component in response to a flag having a value indicating that the sub-process is enabled. 6. The method according to clause 5, comprising: 7. and setting a flag to a value indicating that the subprocess is disabled in response to determining that the chroma component is not included in the sequence. 7. The method of clause 5 or 6, further comprising: 8. Processing a sequence using launched subprocesses 8. The method of any one of clauses 1 to 7, further comprising: 9. A video processing device, at least one memory for storing instructions; At least one processor and and wherein at least one processor: determining whether a chroma component is included in a sequence of frames; In response to determining that the chroma component is included in the sequence, initiating a sub-process for processing the chroma component; configured to execute instructions to cause the device to perform An apparatus, wherein the sub-processes include one or more of joint coding of chroma residual (JCCR), block differential pulse code modulation (BDPCM), palette mode, or adaptive color transformation (ACT). 10. At least one processor: Determining that a chroma component is included in a sequence based on the chroma format and a separate color plane flag. 10. An apparatus as described in clause 9, configured to execute instructions to cause the apparatus to perform the 11. The device according to clause 10, wherein the chroma format comprises a monochrome type, a 4:2:0 sampling type, a 4:2:2 sampling type or a 4:4:4 sampling type. 12. At least one processor: determining values ​​of separate color plane flags; determining that a chroma component is included in the sequence in response to determining that the separate color plane flag has a first value; 12. An apparatus according to any one of clauses 9 to 11, configured to execute instructions to cause the apparatus to perform the 13. At least one processor: Signaling a flag in the Sequence Parameter Set (SPS) that indicates whether a subprocess is enabled 13. An apparatus according to any one of clauses 9 to 12, configured to execute instructions to cause the apparatus to perform the 14. At least one processor: Initiating a sub-process for processing a chroma component in response to a flag having a value indicating that the sub-process is enabled. 14. The apparatus of clause 13, configured to execute instructions to cause the apparatus to perform the 15. At least one processor: and setting a flag to a value indicating that the subprocess is disabled in response to determining that the chroma component is not included in the sequence. 15. An apparatus according to clause 13 or 14, configured to execute instructions to cause the apparatus to perform 16. At least one processor: Processing a sequence using launched subprocesses 16. An apparatus according to any one of clauses 9 to 15, configured to execute instructions to cause the apparatus to perform the 17. A non-transitory computer-readable storage medium storing a set of instructions, the set of instructions comprising: determining whether a chroma component is included in a sequence of frames; In response to determining that the chroma component is included in the sequence, initiating a subprocess for processing the sequence; executable by one or more processing devices to cause a video processing device to perform A non-transitory computer-readable storage medium, wherein the sub-processes include one or more of joint coding of chroma residual (JCCR), block differential pulse code modulation (BDPCM), palette mode, or adaptive color transformation (ACT). 18. A set of instructions is Determining that a chroma component is included in a sequence based on the chroma format and a separate color plane flag. 18. A non-transitory computer-readable storage medium as recited in clause 17, executable by one or more processing devices to cause a video processing device to perform the 19. The non-transitory computer-readable storage medium of clause 18, wherein the chroma format includes a monochrome type, a 4:2:0 sampling type, a 4:2:2 sampling type, or a 4:4:4 sampling type. 20. A set of instructions is determining values ​​of separate color plane flags; determining that a chroma component is included in the sequence in response to determining that the separate color plane flag has a first value; 20. A non-transitory computer-readable storage medium according to any one of clauses 17 to 19, executable by one or more processing devices to cause a video processing device to execute the above. 21. A set of instructions is Signaling a flag in the Sequence Parameter Set (SPS) that indicates whether a subprocess is enabled 21. A non-transitory computer-readable storage medium according to any one of clauses 17 to 20, executable by one or more processing devices to cause a video processing device to execute the above. 22. A set of instructions is Initiating a sub-process for processing a chroma component in response to a flag having a value indicating that the sub-process is enabled. 22. A non-transitory computer-readable storage medium as recited in clause 21, executable by one or more processing devices to cause a video processing device to perform the steps of: 23. A set of instructions is and setting a flag to a value indicating that the subprocess is disabled in response to determining that the chroma component is not included in the sequence. 23. A non-transitory computer-readable storage medium according to clause 21 or 22, executable by one or more processing devices to cause a video processing device to perform the 24. A set of instructions is Processing a sequence using launched subprocesses 24. A non-transitory computer-readable storage medium according to any one of clauses 17 to 23, executable by one or more processing devices to cause a video processing device to execute the above.

[0078]

[0095] In some embodiments, a non-transitory computer-readable storage medium containing instructions is also provided, which may be executed by a device (such as the encoders and decoders of the present disclosure) to perform the methods described above. Common forms of non-transitory media include, for example, a floppy disk, a flexible disk, a hard disk, a solid-state drive, a magnetic tape, or any other magnetic data storage medium, a CD-ROM, any other optical data storage medium, any physical medium with a pattern of holes, RAM, PROM, and EPROM, FLASH-EPROM or any other flash memory, NVRAM, cache, registers, any other memory chip or cartridge, and networked versions thereof. A device may include one or more processors (CPUs), input / output interfaces, a network interface, and / or memory.

[0079]

[0096] It should be noted that relational terms herein, such as "first" and "second," are used merely to distinguish one entity or operation from another, and do not require or imply any actual relationship or order among those entities or operations. Furthermore, the words "comprising," "having," "containing," and "including," and other similar forms, are intended to be equivalent in meaning and to be open-ended in that the element or elements following any of these words are not meant to be an exclusive list of such elements or elements, or to be limited to only the listed element or elements.

[0080]

[0097] As used herein, unless specifically stated otherwise, the term "or" includes all possible combinations unless impracticable. For example, if it is stated that a database may include A or B, then, unless specifically stated otherwise or impracticable, the database may include A, or B, or A and B. As a second example, if it is stated that a database may include A, B, or C, then, unless specifically stated otherwise or impracticable, the database may include A, B, or C, or A and B, A and C, or B and C, or A, B, and C.

[0081]

[0098] It is understood that the above-described embodiments can be implemented by hardware, or software (program code), or a combination of hardware and software. If implemented by software, it can be stored in the above-described computer-readable medium. The software, when executed by a processor, can perform the methods of the present disclosure. The computational units and other functional units described in the present disclosure can be implemented by hardware, or software, or a combination of hardware and software. Those skilled in the art will also understand that multiple of the above-described modules / units can be combined into one module / unit, and that each of the above-described modules / units can be further divided into multiple sub-modules / sub-units.

[0082]

[0099] In the foregoing specification, embodiments have been described with reference to numerous specific details that may vary from implementation to implementation. Certain adaptations and modifications of the above-described embodiments may be made. Other embodiments may be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. It is intended that the specification and examples be considered as examples only, with the true scope and spirit of the invention being indicated by the appended claims. It is also intended that the sequences of steps depicted in the figures are for illustrative purposes only and are not intended to be limited to any particular sequence of steps. Thus, one skilled in the art will recognize that these steps may be performed in different orders while implementing the same method.

[0083]

[0100] In the drawings and specification, illustrative embodiments have been disclosed. However, many variations and modifications to these embodiments may be made. Accordingly, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation.

Claims

1. A video processing method, comprising: determining whether a chroma component is included in a sequence of frames; initiating a sub-process for processing the sequence in response to determining that the chroma component is included in the sequence; The method, wherein the sub-processes include one or more of Joint Coding of Chroma Residual (JCCR), Block Differential Pulse Code Modulation (BDPCM), Palette Mode, or Adaptive Color Transform (ACT).

2. Determining whether the chroma component is included in the sequence includes: determining that the chroma component is included in the sequence based on a chroma format and a separate color plane flag; The method of claim 1 , comprising:

3. The method of claim 2 , wherein the chroma format comprises a monochrome type, a 4:2:0 sampling type, a 4:2:2 sampling type, or a 4:4:4 sampling type.

4. Determining whether the chroma component is included in the sequence includes: determining values ​​of separate color plane flags; determining that the chroma component is included in the sequence in response to determining that the separate color plane flag has a first value; The method of claim 1 , comprising:

5. Invoking the sub-process for processing the chroma components signaling a flag in a sequence parameter set (SPS) indicating whether the sub-process is enabled; The method of claim 1 , comprising:

6. Invoking the sub-process for processing the chroma components initiating the sub-process for processing the chroma components in response to the flag having a value indicating that the sub-process is enabled; The method of claim 5 , comprising:

7. and in response to determining that the chroma component is not included in the sequence, setting the flag to a value indicating that the sub-process is disabled. The method of claim 5 further comprising:

8. processing the sequence using the invoked sub-process; The method of claim 1 further comprising:

9. A video processing device, at least one memory for storing instructions; at least one processor; wherein the at least one processor: determining whether a chroma component is included in a sequence of frames; initiating a sub-process for processing the sequence in response to determining that the chroma component is included in the sequence; configured to execute the instructions to cause a device to perform The apparatus, wherein the sub-processes include one or more of Joint Coding of Chroma Residual (JCCR), Block Differential Pulse Code Modulation (BDPCM), Palette Mode, or Adaptive Color Transform (ACT).

10. the at least one processor: determining that the chroma component is included in the sequence based on a chroma format and a separate color plane flag; 10. The apparatus of claim 9, configured to execute the instructions to cause the apparatus to perform:

11. the at least one processor: determining values ​​of separate color plane flags; determining that the chroma component is included in the sequence in response to determining that the separate color plane flag has a first value; 10. The apparatus of claim 9, configured to execute the instructions to cause the apparatus to perform:

12. the at least one processor: signaling a flag in a sequence parameter set (SPS) indicating whether said sub-process is enabled; initiating the sub-process for processing the chroma components in response to the flag having a value indicating that the sub-process is enabled; 10. The apparatus of claim 9, configured to execute the instructions to cause the apparatus to perform:

13. the at least one processor: and in response to determining that the chroma component is not included in the sequence, setting the flag to a value indicating that the sub-process is disabled.

13. The apparatus of claim 12, configured to execute the instructions to cause the apparatus to perform:

14. the at least one processor: processing the sequence using the invoked sub-process; 10. The apparatus of claim 9, configured to execute the instructions to cause the apparatus to perform:

15. 1. A non-transitory computer-readable storage medium storing a set of instructions, the set of instructions comprising: determining whether a chroma component is included in a sequence of frames; initiating a sub-process for processing the sequence in response to determining that the chroma component is included in the sequence; executable by one or more processing devices to cause a video processing device to perform 10. A non-transitory computer-readable storage medium, wherein the sub-processes include one or more of: joint coding of chroma residual (JCCR), block differential pulse code modulation (BDPCM), palette mode, or adaptive color transformation (ACT).

16. The set of instructions determining that the chroma component is included in the sequence based on a chroma format and a separate color plane flag; 20. The non-transitory computer-readable storage medium of claim 15, executable by the one or more processing devices to cause the video processing device to perform:

17. The set of instructions determining values ​​of separate color plane flags; determining that the chroma component is included in the sequence in response to determining that the separate color plane flag has a first value; 20. The non-transitory computer-readable storage medium of claim 15, executable by the one or more processing devices to cause the video processing device to perform:

18. The set of instructions signaling a flag in a sequence parameter set (SPS) indicating whether said sub-process is enabled; initiating the sub-process for processing the chroma components in response to the flag having a value indicating that the sub-process is enabled; 20. The non-transitory computer-readable storage medium of claim 15, executable by the one or more processing devices to cause the video processing device to perform:

19. The set of instructions and in response to determining that the chroma component is not included in the sequence, setting the flag to a value indicating that the sub-process is disabled.

20. The non-transitory computer-readable storage medium of claim 18, executable by the one or more processing devices to cause the video processing device to perform:

20. The set of instructions processing the sequence using the invoked sub-process; 20. The non-transitory computer-readable storage medium of claim 15, executable by the one or more processing devices to cause the video processing device to perform:

Images