Display device

Abstract

To provide a novel display device.SOLUTION: The display device includes: a pixel unit; a drive circuit unit located outside the pixel unit; and a protection circuit that is electrically connected to either or both of the pixel unit and drive circuit unit, and contains a pair of electrodes. The pixel unit has: pixel electrodes arranged in a matrix; and a transistor electrically connected to the pixel electrodes. The transistor has: a first insulating layer containing nitrogen and silicon; and a second insulating layer containing oxygen, nitrogen and silicon. The protection circuit has a first insulating layer between the pair of electrodes.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] The present invention relates to an object, a method, a manufacturing method, a process, a machine, a manufacture, or The present invention relates to a composition of matter. In particular, the present invention relates to a composition of matter for, for example, a semiconductor device. Devices, display devices, light-emitting devices, electronic devices, driving methods thereof, or manufacturing methods thereof In particular, the present invention relates to, for example, a semiconductor device, a display device, and an electronic device having an oxide semiconductor. , or a light-emitting device.

[0002] The display device refers to a device having a display element. The display device includes a control circuit disposed on a separate substrate. This includes circuits, power supply circuits, signal generation circuits, etc. [Background technology]

[0003] Display devices, such as liquid crystal display devices, have been miniaturized due to recent technological innovations. The technology has progressed and mass production technology has also progressed significantly. Therefore, there is a need to reduce costs.

[0004] When a surge voltage caused by static electricity is applied to a display device, the elements are destroyed and normal operation is lost. This can lead to a decrease in manufacturing yield. The display device is provided with a protection circuit to release the surge voltage to another wiring (for example, See, for example, Patent Documents 1 to 7. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2010-92036 [Patent Document 2] Japanese Patent Application Laid-Open No. 2010-92037 [Patent Document 3] Japanese Patent Application Laid-Open No. 2010-97203 [Patent Document 4] Japanese Patent Application Laid-Open No. 2010-97204 [Patent Document 5] Japanese Patent Application Laid-Open No. 2010-107976 [Patent Document 6] Japanese Patent Application Laid-Open No. 2010-107977 [Patent Document 7] Japanese Patent Application Laid-Open No. 2010-113346 Summary of the Invention [Problem to be solved by the invention]

[0006] In display devices, configurations aimed at improving reliability, such as protection circuits, are important. be.

[0007] Therefore, one embodiment of the present invention provides a display device having a novel structure that can improve reliability. Another object of the present invention is to reduce electrostatic damage. Another object of the present invention is to provide a display device having a novel structure. The object of the present invention is to provide a display device having a novel configuration that can reduce the influence of static electricity. Alternatively, one embodiment of the present invention provides a display device that is hard to break and has a novel structure. Alternatively, in one embodiment of the present invention, a transistor is The object of the present invention is to provide a display device having a novel configuration that can reduce the influence on the monitor. Alternatively, in one embodiment of the present invention, an influence on a transistor in an inspection process may be It is an object of the present invention to provide a display device with a novel structure that can reduce noise. In addition, in one embodiment of the present invention, it is possible to reduce the influence of defects when using a touch sensor. It is an object of the present invention to provide a display device having a novel structure that can achieve the above. In one embodiment, a novel configuration can reduce the fluctuation or degradation of transistor characteristics. Another object of the present invention is to provide a display device. and a display device having a novel configuration capable of reducing fluctuation or deterioration of the threshold voltage of the display device. Another object of one embodiment of the present invention is to provide a normally-on transistor. It is an object of the present invention to provide a display device with a novel structure that can reduce the noise level. Alternatively, in one embodiment of the present invention, a novel method for improving the manufacturing yield of transistors is provided. Another object of the present invention is to provide a display device with a novel structure. The object of the present invention is to provide a display device having a novel configuration in which transistors can be shielded. Alternatively, in one embodiment of the present invention, charges accumulated in a pixel electrode can be discharged. Another object of the present invention is to provide a display device having a novel structure. To provide a display device having a novel configuration capable of discharging electric charges accumulated in wiring. Another object of one embodiment of the present invention is to provide a semiconductor device having an oxide semiconductor layer with improved conductivity. Another object of the present invention is to provide a display device having a novel structure. In the present invention, a display device having a novel structure capable of controlling the conductivity of an oxide semiconductor layer is provided. Another object of one embodiment of the present invention is to control the conductivity of a gate insulating film. It is an object of the present invention to provide a display device having a novel structure that can In one embodiment of the present invention, a display device having a novel configuration is provided that can easily achieve normal display. One of our goals is to provide

[0008] The description of these problems does not preclude the existence of other problems. It is not necessary for one embodiment to solve all of these problems. The above will be made clear from the description, drawings, claims, etc. It is possible to extract issues other than those mentioned above from the descriptions in the patent, claims, etc. [Means for solving the problem]

[0009] One embodiment of the present invention is a pixel region, a driver circuit region disposed outside the pixel region, and a pixel region or a driver circuit region disposed outside the pixel region. a protection circuit electrically connected to one or both of the drive circuit units and including a pair of electrodes; The pixel section has pixel electrodes arranged in a matrix and a a transistor including a first insulating layer including nitrogen and silicon; a second insulating layer containing oxygen, nitrogen, and silicon, and a protection circuit is disposed between the pair of electrodes; The display device has an insulating layer. [Effects of the Invention]

[0010] According to one embodiment of the present invention, the reliability of a display device can be improved. [Brief explanation of the drawings]

[0011] [Figure 1] 1A and 1B are a plan view schematic diagram of a display device and a circuit diagram illustrating a protection circuit. [Figure 2] FIG. 10 is a cross-sectional view illustrating a resistor element of the display device. [Figure 3] 1A and 1B are a plan view schematic diagram of a display device and a circuit diagram illustrating a protection circuit. [Figure 4] 3A and 3B are a plan view and a cross-sectional view illustrating a protection circuit and a resistor element. [Figure 5] FIG. 2 is a circuit diagram illustrating a protection circuit. [Figure 6] FIG. [Figure 7] 1A to 1C are cross-sectional views illustrating a method for manufacturing a display device. [Figure 8] 1A to 1C are cross-sectional views illustrating a method for manufacturing a display device. [Figure 9] 1A to 1C are cross-sectional views illustrating a method for manufacturing a display device. [Figure 10] 1A to 1C are cross-sectional views illustrating a method for manufacturing a display device. [Figure 11] 1A to 1C are cross-sectional views illustrating a method for manufacturing a display device. [Figure 12] 1A to 1C are cross-sectional views illustrating a method for manufacturing a display device. [Figure 13] FIG. 1 is a circuit diagram illustrating a pixel circuit that can be used in a display device. [Figure 14] 1A and 1B illustrate a plan view and a cross section of a transistor. [Figure 15] 3A and 3B are diagrams illustrating a plan view and a cross section of a resistor element. [Figure 16] FIG. 2 is a diagram illustrating a circuit diagram of a resistor element. [Figure 17] FIG. 2 is a diagram illustrating a cross section of a resistor element. [Figure 18] 1A to 1C are cross-sectional views of a transistor and a diagram illustrating an oxide stack. [Figure 19] FIG. 2 is a cross-sectional view illustrating a connection terminal portion of the display device. [Figure 20] FIG. 2 is a diagram illustrating a touch sensor. [Figure 21] FIG. 2 is a circuit diagram illustrating a touch sensor. [Figure 22] FIG. 2 is a cross-sectional view illustrating a touch sensor. [Figure 23] 1A and 1B illustrate a display module using a display device which is one embodiment of the present invention. [Figure 24] 1A to 1C illustrate electronic devices using a display device which is one embodiment of the present invention. [Figure 25] 1A to 1C illustrate electronic devices using a display device which is one embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0012] Hereinafter, embodiments will be described with reference to the drawings. It is possible to implement the present invention in various ways without departing from the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that various modifications may be made to the details of the present invention. However, the present invention should not be construed as being limited to the description of the following embodiments.

[0013] Also, in the drawings, the size, thickness of layers, or areas are exaggerated for clarity. Therefore, the scale is not necessarily limited to that shown. The figures are merely schematic representations and are not limited to the shapes or values ​​shown in the drawings. Variations in signals, voltages, or currents due to the above, or variations in signals, voltages, or currents due to timing differences , or current variations, etc.

[0014] In this specification, a transistor includes a gate, a drain, and a source. It is an element having at least three terminals including a drain (drain terminal, drain Between the drain electrode and the source terminal The semiconductor device has a channel region therein, and a current flows through the drain, the channel region, and the source. This is what is possible.

[0015] Here, the source and drain may vary depending on the structure or operating conditions of the transistor. Therefore, it is difficult to determine which is the source and which is the drain. The part that functions as a source and the part that functions as a drain are called the source and the drain, respectively. First, one of the source and the drain is referred to as a first electrode, and the other of the source and the drain is referred to as a second electrode. It may be written as "pole."

[0016] In addition, the ordinal numbers "first," "second," and "third" used in this specification refer to the number of components. It should be noted that this is added to avoid confusion and is not intended to limit the number.

[0017] In this specification, "A and B are connected" does not mean that A and B are directly connected. In addition to those that are connected electrically, those that are connected electrically are also included. Electrically connected means that there is an object between A and B that has some kind of electrical effect. When this occurs, it means something that enables the transmission and reception of electrical signals between A and B.

[0018] In addition, in this specification, the terms "above" and "below" that indicate the position of components are used to indicate the position of components. The positional relationship is used for convenience in describing the structure with reference to the drawings. The relationship between the two components changes depending on the direction in which each component is depicted. The terms are not limited to those used above, but can be rephrased appropriately depending on the situation.

[0019] In addition, the positional relationship of each circuit block in the block diagram is specified for the purpose of explanation. Although different circuit blocks are shown to realize different functions, In circuits or regions, different functions can be realized within the same circuit or region. In addition, the function of each circuit block in the block diagram may be changed for the purpose of explanation. Although it is shown as a circuit block, it may not be applicable to actual circuits or areas. In this case, the processing that would normally be done by one circuit block is performed by multiple circuit blocks. In some cases, this may be the case.

[0020] A pixel is a pixel that contains one color element (for example, one of R (red), G (green), or B (blue)). This corresponds to a display unit that can control brightness. Therefore, in the case of a color display device, The minimum display unit of a color image is composed of three pixels: an R pixel, a G pixel, and a B pixel. However, the color elements for displaying a color image are not limited to three colors. The above may be used, or colors other than RGB may be used.

[0021] In this specification, embodiments of the present invention will be described with reference to the drawings. The description of each embodiment will be given in the following order. 1. Embodiment 1 (Basic Configuration of One Aspect of the Present Invention) 2. Second Embodiment (Regarding the Components of the Display Device) 3. Embodiment 3 (Manufacturing Method of Display Device) 4. Fourth Embodiment (Regarding the Configuration of the Pixel Circuit) 5. Fifth Embodiment (Regarding the Configuration of the Pixel Section) 6. Sixth Embodiment (Modification of Protection Circuit) 7. Seventh Embodiment (Regarding the Structure of Transistors) 8. Eighth Embodiment (Configuration of Connection Terminal Portion) 9. Embodiment 9 (Regarding Touch Sensor and Display Module) 10. Embodiment 10 (Regarding Electronic Devices)

[0022] (Embodiment 1) In this embodiment, a display device of one embodiment of the present invention will be described with reference to FIGS. conduct.

[0023] The display device shown in FIG. 1A includes a region having a pixel display element (hereinafter referred to as a pixel portion 102). a circuit section (hereinafter referred to as a driving circuit section 104) having a circuit for driving the pixels; A circuit having a function of protecting the element (hereinafter referred to as a protection circuit 106) and a terminal section 107 are provided. Has.

[0024] The pixel units 102 are arranged in X rows (X is a natural number of 2 or more) and Y columns (Y is a natural number of 2 or more). The display device further includes a circuit for driving a plurality of display elements (hereinafter referred to as pixel circuits 108), The path section 104 includes a circuit (hereinafter referred to as a gate driver) that outputs a signal (scanning signal) for selecting a pixel. 104a), for supplying signals (data signals) for driving the display elements of the pixels. The source driver 104b includes a driving circuit such as a circuit for driving the source.

[0025] The gate driver 104a includes a shift register and the like. A signal for driving the shift register is inputted through the terminal section 107, and a signal for outputting the shift register is outputted. For example, the gate driver 104a receives a start pulse signal, a clock signal, etc. The gate driver 104a receives a scanning signal and outputs a pulse signal. The gate has a function of controlling the potential of the scanning lines GL_1 to GL_X. A plurality of drivers 104a are provided, and the plurality of gate drivers 104a drive the scanning lines GL_1 to Alternatively, the gate driver 104a may control the GL_X by dividing it into two parts. However, the gate driver 10 has a function of supplying 4a may also provide other signals.

[0026] The source driver 104b includes a shift register and the like. Through the terminal section 107, signals for driving the shift register as well as the source of data signals are transmitted. The source driver 104b receives a signal (image signal) that is to be output from the pixel circuit The source driver 104b has a function of generating a data signal to be written to the source driver 108. The data is generated in accordance with the pulse signals obtained by inputting the start pulse signal, clock signal, etc. The source driver 104b has a function of controlling the output of the data signal. The function of controlling the potential of the wiring (hereinafter referred to as data lines DL_1 to DL_Y) to be applied is Alternatively, the source driver 104b may have a function of supplying an initialization signal. However, the present invention is not limited to this, and the source driver 104b may supply other signals. It is also possible.

[0027] The source driver 104b is configured using, for example, a plurality of analog switches. The source driver 104b sequentially turns on a plurality of analog switches, The image signal can be time-divided and output as a data signal. The source driver 104b may be configured using the same.

[0028] Each of the plurality of pixel circuits 108 is connected to a plurality of wirings (hereinafter referred to as scanning lines) to which scanning signals are applied. A pulse signal is input through one of the wirings (called GL) and a data signal is given through the wirings. A data signal is input via one of the data lines DL. Each of the pixel circuits 108 is driven by the gate driver 104a to write data of the data signal. For example, the pixel circuit 108 in the mth row and nth column is connected to the scanning line GL_m(m is a natural number equal to or less than X), a pulse signal is input from the gate driver 104a to the scanning line The source driver is connected to the data line DL_n (n is a natural number less than or equal to Y) according to the potential of GL_m. A data signal is input from the input terminal 104b.

[0029] The protection circuit 106 is a scanning line that is a wiring between the gate driver 104a and the pixel circuit 108. GL. Alternatively, the protection circuit 106 may be connected to the source driver 104b and the pixel circuit 10 8. Alternatively, the protection circuit 106 is connected to the data line DL, which is the wiring between the gate driver The protection circuit 1 can be connected to the wiring between the driver 104a and the terminal portion 107. 06 can be connected to the wiring between the source driver 104b and the terminal section 107. The terminal unit 107 is used to input power, control signals, and image signals from an external circuit to the display device. This refers to the part where a terminal for inputting power is provided.

[0030] When a potential outside a certain range is applied to the wiring to which the protection circuit 106 is connected, the protection circuit 106 A protection circuit is a circuit that connects a wiring to another wiring. However, it is not limited to this, and may be any other circuit. 06 can also provide other signals.

[0031] As shown in FIG. 1A, a pixel section 102 and a driver circuit section 104 are provided with a protection circuit 106. By providing a This can improve the resistance of the display device to overcurrents caused by electrical discharges, etc. However, the configuration of the protection circuit 106 is not limited to this. For example, the protection circuit 106 may be provided in the gate driver 104a. A configuration in which a protection circuit 106 is connected, or a configuration in which a protection circuit 106 is connected to the source driver 104b Alternatively, a protection circuit 106 may be connected to the terminal section 107. You can also do this.

[0032] In FIG. 1A, the gate driver 104a and the source driver 104b However, the present invention is not limited to this configuration. For example, only the gate driver 104a is formed, and a source driver circuit is separately formed. A substrate (for example, a drive circuit board formed of a single crystal semiconductor film or a polycrystalline semiconductor film) is mounted. It may also be configured as follows.

[0033] That is, the protection circuit 106 is connected to either the pixel section 102 or the driver circuit section 104. are electrically connected to each other.

[0034] The protection circuit 106 can be configured using, for example, a resistor element. An example of a specific protection circuit is shown below.

[0035] The protection circuit 106 shown in FIG. 1B includes a resistor 11 between a wiring 110 and a wiring 112. 4 is connected to the wiring 110. For example, the scanning line GL and the data line GL shown in FIG. The wiring is a data line DL or a wiring routed from the terminal unit 107 to the drive circuit unit 104.

[0036] The wiring 112 is connected to, for example, the gate driver 104a or the source driver 104b shown in FIG. The potential of the power supply line (VDD, VSS or GND) for supplying power to the driver 104b is Or, a wiring (common line) to which a common potential is applied. For example, the wiring 112 is a wiring for supplying power to the gate driver 104a. It is preferable to connect it to a power supply line, especially a line that supplies a low potential. The line GL is at a low potential for most of the time. If the potential is too low, the current leaks from the scanning line GL to the wiring 112 during normal operation. This is because the current that flows can be reduced.

[0037] Here, an example of a configuration that can be used as the resistance element 114 will be described with reference to FIG. Give an explanation.

[0038] The resistor element 114 shown in FIG. 2(A) is a conductive layer (hereinafter referred to as a and a conductive layer 142 (hereinafter referred to as a conductive layer 142) and an insulating layer formed on the substrate 140 and the conductive layer 142. a conductive layer (hereinafter referred to as insulating layer 144) formed on insulating layer 144; Hereinafter referred to as conductive layer 148).

[0039] The resistor element 114 shown in FIG. 2B includes a conductive layer 142 formed on a substrate 140 and a 140 and an insulating layer 144 formed on the conductive layer 142, and an insulating layer 144 formed on the insulating layer 144. an edge layer 146, an insulating layer 144, and a conductive layer 148 formed on the insulating layer 146. .

[0040] Note that the wiring 112 shown in FIG. 1B corresponds to the wiring formed using the conductive layer 142. 1B corresponds to the wiring formed using the conductive layer 148. The wiring 110 shown in FIG.

[0041] In other words, the resistance element 114 shown in FIGS. 2A and 2B has an insulating layer 14 between a pair of electrodes. 4 is sandwiched between the insulating layer 144, and the resistivity (electrical resistivity, specific resistance) of the insulating layer 144 is controlled. By doing so, when an overcurrent flows through one of the pair of electrodes, the other electrode is Part or all of the material can be released.

[0042] However, if the resistance of the insulating layer sandwiched between the pair of electrodes is high, e.g., 10 18 Ωcm When the above insulating layer is used, when an overcurrent flows through one of the pair of electrodes, the other The current cannot be properly discharged.

[0043] Therefore, in one aspect of the present invention, the resistivity and For example, 10 10 Ωcm or more 10 18 Less than Ωcm, preferably 10 11 Ωcm or more 10 15 An insulating film having a resistivity of less than Ωcm is used. For example, an insulating film containing nitrogen and silicon can be used.

[0044] Also, the resistance element 114 covers the end of one of the pair of electrodes as shown in FIG. 2(B). The insulating layer 146 may be provided on the insulating layer 144. The insulating layer 146 can be formed using a material having a higher resistivity than the insulating layer 44. For example, 10 18 It is advisable to use an insulating film with a resistivity of Ωcm or more. An example of such an insulating film is an insulating film containing oxygen, nitrogen, and silicon.

[0045] The conductive layers 142 and 148 functioning as a pair of electrodes of the resistor 114 and the resistor The insulating layers 144 and 146 functioning as insulating layers of the element 114 are The transistors constituting the pixel portion 102 and the driver circuit portion 104 are formed at the same time as the transistors. It is possible.

[0046] Specifically, for example, the conductive layer 142 is formed in the same process as the gate electrode of the transistor. The conductive layer 148 can be formed as a source or drain electrode of the transistor. The insulating layers 144 and 146 can be formed in the same process as the gate of the transistor. It can be manufactured in the same process as the insulating layer.

[0047] In this way, by providing the protection circuit 106 in the display device shown in FIG. 102 and the drive circuit unit 104 have enhanced resistance to overcurrent caused by ESD and the like. Therefore, it is possible to provide a novel display device that can improve reliability. do.

[0048] In addition, the pixel section 102 is formed on the same substrate as the protection circuit 106, for example. This makes it possible to reduce the number of parts and terminals. As an example, a part or the whole of the section 104 is formed on the same substrate as the pixel section 102. This makes it possible to reduce the number of parts and terminals. If a part or all of the pixel section 102 is not formed on the same substrate as the driving section 104, A part or all of the operating circuit unit 104 may be mounted by COG or TAB. many.

[0049] Next, a specific structure of the display device shown in FIG. 1A will be described with reference to FIG.

[0050] The display device shown in FIG. 3 includes a pixel section 102 and a gate driver 103 functioning as a driver circuit section. 04a, a source driver 104b, a protection circuit 106_1, a protection circuit 106_2, The protection circuit 106_3 and the protection circuit 106_4 are included.

[0051] The pixel section 102, the gate driver 104a, and the source driver 104b are the same as those shown in FIG. The configuration is the same as that shown in (A).

[0052] The protection circuit 106_1 includes transistors 151, 152, 153, and 154, and a resistance element 1 71, 172, and 173. The protection circuit 106_1 also includes the gate driver 104 a and the wirings 181, 182, and 183 connected to the transistor 15. 1 is a first terminal having a function as a source electrode and a second terminal having a function as a gate electrode. The second terminal is connected to the third terminal, which functions as a drain electrode, and the wiring 183 is connected to the third terminal. The transistor 152 has a first terminal that functions as a source electrode and a gate electrode. A second terminal having a function as a source electrode is connected to the first terminal having a function as a drain electrode. The third terminal of the transistor 153 is connected to the first terminal of the transistor 151. The first terminal functions as a source electrode, and the second terminal functions as a gate electrode. a third terminal connected to the first terminal and functioning as a drain electrode of the transistor 152; The first terminal of the transistor 154 is connected to the first terminal of the transistor 154. The first terminal is connected to a second terminal that functions as a gate electrode, and the second terminal is connected to a drain electrode. The third terminal of the transistor 153 is connected to the first terminal of the transistor 153. In addition, a first terminal of the transistor 154 is connected to the wiring 183 and the wiring 181. The resistor elements 171 and 173 are provided on the wiring 183. The resistor element 172 is Between the wiring 182 and the first terminal of the transistor 152 and the third terminal of the transistor 153 It is set up in.

[0053] The wiring 181 is used as a power supply line to which a low power supply potential VSS is applied, for example. The wiring 182 can be used as a common line, for example. The line 183 can be used as, for example, a power supply line to which a high power supply potential VDD is applied.

[0054] The protection circuit 106_2 includes transistors 155, 156, 157, and 158, and a resistance element 1 74, 175. The protection circuit 106_2 also includes a gate driver 104a and a pixel The transistor 155 is provided between the first and second electrodes 102 and 103. The transistor 155 also functions as a source electrode. A first terminal having a function as a gate electrode is connected to a second terminal having a function as a drain electrode. The third terminal, which functions as a pole, is connected to the wiring 185. 6 is a first terminal having a function as a source electrode and a second terminal having a function as a gate electrode. a third terminal connected to the second terminal and functioning as a drain electrode; and a transistor 15 The first terminal of the transistor 157 is connected to the first terminal of the transistor 157. A first terminal that functions as a gate electrode is connected to a second terminal that functions as a drain electrode. A third terminal of the transistor 156 is connected to the third terminal of the transistor 156 . The transistor 158 has a first terminal that functions as a source electrode and a second terminal that functions as a gate electrode. The second terminal having the function of a drain electrode is connected to the third terminal having the function of a drain electrode. The first terminal of the transistor 157 is connected to the first terminal of the transistor 158 and the wiring 184. The resistor element 174 is connected to the wiring 185 and the first terminal of the transistor 156. The resistor element 175 is provided between the resistor 175 and the third terminal of the transistor 157. , the wiring 184, the first terminal of the transistor 156, and the third terminal of the transistor 157. It is placed in between.

[0055] The wiring 184 is used as a power supply line to which a low power supply potential VSS is applied, for example. The wiring 185 can be used as a power supply line to which a high power supply potential VDD is applied, for example. The wiring 186 can also be used as, for example, a gate line.

[0056] The protection circuit 106_3 includes transistors 159, 160, 161, and 162, and a resistance element 1 76, 177. The protection circuit 106_3 is connected to the source driver 104b and the pixel The transistor 159 is provided between the first and second electrodes 102 and 103. The transistor 159 also functions as a source electrode. A first terminal having a function as a gate electrode is connected to a second terminal having a function as a drain electrode. The third terminal, which functions as an electrode, is connected to the wiring 190. 0 is a first terminal that functions as a source electrode and a second terminal that functions as a gate electrode. a third terminal connected to the second terminal and functioning as a drain electrode; and a transistor 15 The first terminal of the transistor 161 is connected to the first terminal of the transistor 162. The transistor 161 functions as a source electrode. A first terminal that functions as a gate electrode is connected to a second terminal that functions as a drain electrode. The third terminal of the transistor 160 is connected to the first terminal of the transistor 160. The transistor 162 has a first terminal functioning as a source electrode and a second terminal functioning as a gate electrode. a third terminal connected to the second terminal and functioning as a drain electrode; The first terminal of the transistor 161 is connected to the first terminal of the transistor 162. The resistor element 176 is connected to the wiring 190 and the transistor. The resistor 162 is provided between the first terminal of the transistor 160 and the third terminal of the transistor 161. The resistor 177 is connected to the wiring 191, the first terminal of the transistor 160, and the second terminal of the transistor 16 It is provided between the third terminal of 1.

[0057] The wiring 188 can be used as, for example, a common line or a source line. The wirings 189 and 190 are used as power supply lines to which a high power supply potential VDD is applied, for example. The wiring 191 can be, for example, a power supply line to which a low power supply potential VSS is applied. It can be used as such.

[0058] The protection circuit 106_4 includes transistors 163, 164, 165, and 166, and a resistance element 1 78, 179, and 180. The protection circuit 106_4 also includes the source driver 104 b and the wirings 187, 188, 189, 190, and 191 connected thereto. The transistor 163 has a first terminal functioning as a source electrode and a second terminal functioning as a gate electrode. a third terminal connected to the second terminal and functioning as a drain electrode; The transistor 164 has a function as a source electrode. The first terminal is connected to a second terminal that functions as a gate electrode, and the second terminal is connected to a drain electrode. The third terminal of the transistor 162 is connected to the first terminal of the transistor 163. The transistor 165 has a first terminal that functions as a source electrode and a second terminal that functions as a gate electrode. a second terminal having a function as a drain electrode, and a third terminal having a function as a transistor electrode; The first terminal of the transistor 166 is connected to a source electrode of the transistor 164. A first terminal having a function as a gate electrode is connected to a second terminal having a function as a gate electrode. a third terminal that functions as a drain electrode, and a first terminal of the transistor 165. A first terminal of the transistor 166 is connected to the wiring 189. The resistor element 178 is provided between the wiring 187 and the wiring 188. The resistor 179 is connected to the wiring 188 and is connected to the first terminal of the transistor 164 and the The resistor element 180 is connected to the third terminal of the resistor 165. The resistor element 180 is connected to the wiring 188 and the wiring 1 It is located between 89.

[0059] The wirings 187 and 191 are used as power supply lines to which a low power supply potential VSS is applied, for example. The wiring 188 can be used as, for example, a common line or a source line. The wirings 189 and 190 may be connected to a power supply to which a high power supply potential VDD is applied. It can be used as a source beam.

[0060] The wirings 181 to 191 are connected to the high power supply potential VDD and the low power supply potential VS shown in FIG. The functions are not limited to those shown in S and CL, but can also be used independently as scanning lines, signal lines, and power supply lines. The line may have the function of a line, a ground line, a capacitance line, a common line, or the like.

[0061] In addition, the semiconductor devices of the transistors 151 to 166 included in the protection circuits 106_1 to 106_4 are The conductor layer is preferably made of an oxide semiconductor. Compared with transistors that use silicon or other materials for the semiconductor layer, Since there is no gate, the resistance to electric fields is high. The transistor structure may be, for example, a planar type or an inverted staggered type.

[0062] In this way, the protection circuits 106_1 to 106_4 are configured as a plurality of diode-connected transistors. The protection circuit 106_1 is configured by a transistor and a plurality of resistance elements. 106_4 is a diode-connected transistor and a resistor element connected in parallel. You can be there.

[0063] 3, the protection circuits 106_1 to 106_4 are connected to the pixel portion 102. between the gate driver 104a and the wiring connected to the gate driver 104a, Between the element unit 102 and the source driver 104b, or connected to the source driver 104b It can be provided between the wiring.

[0064] 3. Also, as an example, a plan view corresponding to the protection circuit 106_2 described in FIG. The cross-sectional views of the area functioning as a substrate are shown in Figures 4(A) and (B). The reference numerals in FIG. 4(B) correspond to the reference numerals in FIG. 3. 4(A) and 4(B) are cross-sectional views taken along the cutting line MN. The resistor element of the protection circuit is formed by removing a part of the insulating layer that overlaps the wiring. By controlling the resistivity, it can be used as a resistance element that effectively releases excess current. .

[0065] FIG. 5 is a circuit diagram showing a different configuration from the protection circuit described in FIG. 3. In the circuit diagram, transistors 155A, 156A, 157A, 158A, and transistor 1 55B, 156B, 157B, 158B, resistor elements 174A, 175A, resistor element 174 B, 175B, a resistor element 199, a wiring 184, a wiring 185 and a wiring 186 are shown. 5. The reference numerals in the circuit diagram shown in FIG. 5 are the same as those in the protection circuit 106_2 described in FIG. The same components are designated by the same reference numerals. The difference from the protection circuit 106_2 is that a circuit equivalent to the protection circuit 106_2 in FIG. Another feature is that a resistive element 199 is provided between the wirings.

[0066] The resistivity of the resistor element 199 included in the protection circuit 106_2 shown in FIG. The resistivity of 174A, 175A, and resistor elements 174B and 175B is 10 10 Ωcm or more 10 1 8 less than 10 Ωcm 3 Ωcm or more 10 6 Less than Ωcm and smaller values By using the circuit configuration shown in FIG. 5, the sudden change of the signal applied to the wiring can be prevented. It is possible to suppress abrupt changes.

[0067] By providing a plurality of protection circuits in the display device in this way, the pixel portion 102 and the driving The circuit section 104 (gate driver 104a, source driver 104b) is resistant to ESD and other damage. This further increases the resistance to overcurrents that occur due to the It is possible to provide a novel display device that can improve image quality.

[0068] In this embodiment, when a protection circuit, a resistor, a transistor, or the like is provided, Although examples have been described, one aspect of the embodiment of the present invention is not limited thereto. In some cases, it may be possible not to provide a protection circuit or the like.

[0069] The structure described in this embodiment mode may be used in appropriate combination with structures described in other embodiments. can be done.

[0070] (Embodiment 2) In this embodiment, a vertical electric field type liquid crystal element having the protection circuit described in Embodiment 1 is used. The structure of a display device (also called a liquid crystal display device) using the LCD panel will be described with reference to FIG.

[0071] The display device shown in FIG. 6 is a display device including the pixel portion 102 and the driver circuit portion 10 of the display device shown in FIG. 4 and a protection circuit 106. In addition, the conductive layers are connected to each other at a connection point. The connecting portion 109 is an example of a connecting portion between the first conductive layer and the second conductive layer. Such a connection structure is connected to the driving circuit section 104 or the wiring. etc.

[0072] In the display device shown in FIG. 6, a protection circuit 106 is connected to the drive circuit unit 104. However, the present invention is not limited to this example. For example, the driving circuit unit 104 and the pixel unit 102 A protection circuit 106 can be connected between the two.

[0073] The display device shown in this embodiment has a liquid crystal element between a pair of substrates (a substrate 202 and a substrate 252). 268 is clamped.

[0074] The liquid crystal element 268 is formed by a conductive layer 220c formed above the substrate 202 and a conductive layer 220c. a liquid crystal layer 260 formed thereon, and a conductive layer 258 formed on the liquid crystal layer 260. The conductive layer 220c serves as one electrode of the liquid crystal element 268, and the conductive layer 258 serves as one electrode of the liquid crystal element 268. It serves as the other electrode of element 268 .

[0075] In this embodiment, when the liquid crystal element 268 is a vertical electric field type liquid crystal element, As a liquid crystal element of the vertical electric field type, for example, a TN (Twisted Ne matic) mode, STN (Super Twisted Nematic) mode, The typical example is the VA (Vertical Alignment) mode. The element is not limited to this, and may be, for example, an IPS (In-Plane-Switch) type. switching mode and FFS (Fringe Field Switching) A mode or the like may also be used.

[0076] Thus, a liquid crystal display device is a device that has a liquid crystal element. The device includes a driving circuit for driving a plurality of pixels. a control circuit, a power supply circuit, a signal generating circuit, a backlight module, etc., arranged in It is also called a liquid crystal module.

[0077] In the liquid crystal display device, a driver circuit portion 104 and a pixel portion 102 are provided in the liquid crystal display device. The transistor is provided with a protection circuit 106 as shown in this embodiment. , the resistance to external overcurrent can be improved.

[0078] For example, static electricity can be generated by the rubbing process that is performed when manufacturing a liquid crystal element. However, by providing the protection circuit 106, the pixel section 102 and the driver circuit section 104 The formed transistor does not flow or is suppressed from flowing overcurrent that may be caused by the static electricity. Therefore, electrostatic breakdown of the transistor is suppressed, and a highly reliable display device is obtained. It is possible.

[0079] Here, other components of the display device shown in FIG. 6 will be described below.

[0080] On the substrate 202, conductive layers (hereinafter referred to as conductive layers 204a, 204b, 204c, 204d) are formed. The conductive layer 204a is formed in the protection circuit 106 and is a resistor. The conductive layer 204b functions as one of a pair of electrodes of the element. The conductive layer 04 functions as a gate of a transistor in a driver circuit. 204c is formed in the pixel section 102 and functions as the gate of a transistor in the pixel circuit. The conductive layer 204d is formed in the connection portion 109 and is connected to the conductive layer 212f. .

[0081] In addition, insulating layers are formed on the substrate 202 and the conductive layers 204a, 204b, 204c, and 204d. Insulating layers 206 and 208 are formed on the insulating layer 206. 208 is a gate insulating layer of the transistor in the driver circuit section 104 and a gate insulating layer of the transistor in the pixel section 102. The insulating layer 206 also functions as a gate insulating layer for the protection circuit 106. It functions as a resistive element (resistive layer).

[0082] Furthermore, on the insulating layer 208, layers having semiconductor properties (hereinafter referred to as semiconductor layers 210a and 210b) The semiconductor layer 210a is formed in a position overlapping with the conductive layer 204b. The semiconductor layer 210 functions as a channel of a transistor in the driver circuit. b is formed in a position overlapping with the conductive layer 204c and serves as a channel of a transistor of a pixel circuit. It has the function of

[0083] In addition, conductive layers are formed on the insulating layers 206 and 208 and the semiconductor layers 210a and 210b. (hereinafter referred to as conductive layers 212a, 212b, 212c, 212d, 212e, and 212f) The conductive layer 212a is formed on the pair of electrodes of the resistance element of the protection circuit 106. The conductive layer 212b is electrically connected to the semiconductor layer 210a. The gate electrode functions as one of the source and the drain of a transistor in the driver circuit. The conductive layer 212c is electrically connected to the semiconductor layer 210a and functions as a transistor of the driving circuit. The conductive layer 212d has a function as the other of the source and drain of the transistor. The source and drain of the transistor of the pixel circuit are electrically connected to the semiconductor layer 210b. The conductive layer 212e functions as one of the electrodes. and serves as the other of the source and drain of the transistor of the pixel circuit. The conductive layer 212f is formed in the connection portion 109 and is provided on the insulating layers 206 and 208. The conductive layer 204d is electrically connected to the conductive layer 204d through the opening.

[0084] In addition, the insulating layer 208, the semiconductor layers 210a and 210b, and the conductive layers 212a and 212b, On 212c, 212d, 212e, and 212f, a layer having insulating properties (hereinafter, insulating layer 21) is provided. Insulating layers 214 and 216 are formed on the transistors to protect them. In particular, the insulating layer 214 has the function of protecting the semiconductor layers 210a and 210b. It has.

[0085] Furthermore, a layer having insulating properties (hereinafter referred to as insulating layer 218) is formed on insulating layer 216. The insulating layer 218 functions as a planarization layer. By this, the conductive layer formed below the insulating layer 218 and the conductive layer formed above the insulating layer 218 This can suppress the occurrence of parasitic capacitance that may occur between the conductive layer formed on the insulating film and the conductive layer.

[0086] Furthermore, on the insulating layer 218, conductive layers (hereinafter referred to as conductive layers 220a, 220b, 220c) are formed. The conductive layer 220a penetrates the insulating layers 214, 216, and 218. The conductive layer 212b is electrically connected to the conductive layer 212b through an opening formed therethrough, and the driving circuit section 104 The conductive layer 212b functions as a connection electrode that electrically connects the conductive layer 212b to other wirings. 220b is formed by openings formed through insulating layers 214, 216, and 218. 12d, and electrically connects the conductive layer 212d of the pixel section 102 to other wirings. The conductive layer 220c functions as a connecting electrode for connecting the insulating layers 214, 216, The pixel portion 1 is electrically connected to the conductive layer 212e through an opening formed through the conductive layer 218. The conductive layer 220c functions as a pixel electrode of the liquid crystal element of the pixel circuit. The electrode can function as one of a pair of electrodes.

[0087] Furthermore, a layer having color (hereinafter referred to as a color layer 254) is formed on the substrate 252. The colored layer 254 functions as a color filter. Although not shown, a light-shielding film having a function as a black matrix is ​​disposed adjacent to the colored layer 254. The colored layer 254 does not necessarily have to be provided. In some cases, such as when the display device is monochrome, the color layer 254 may not be provided.

[0088] Moreover, a layer having insulating properties (hereinafter referred to as insulating layer 256) is formed on the colored layer 254. The insulating layer 256 functions as a planarizing layer or to remove impurities that may be contained in the colored layer 254. It has the function of suppressing the diffusion of impurities into the liquid crystal element side.

[0089] Moreover, a layer having conductivity (hereinafter referred to as a conductive layer 258) is formed on the insulating layer 256. The conductive layer 258 functions as the other of the pair of electrodes of the liquid crystal element in the pixel circuit. On the conductive layers 220a, 220b, 220c and the conductive layer 258, an orientation film An insulating film having a function as a film may be formed separately.

[0090] In addition, a liquid crystal layer 260 is provided between the conductive layers 220a, 220b, and 220c and the conductive layer 258. The liquid crystal layer 260 is formed on the substrate 202 using a sealing material (not shown). The seal material is used to prevent moisture and the like from entering from the outside. To suppress this, a configuration in which the inorganic material is in contact with the inorganic material is preferred.

[0091] In addition, the thickness of the liquid crystal layer 260 is between the conductive layers 220a, 220b, 220c and the conductive layer 258. A spacer may be provided to maintain the thickness (also called the cell gap).

[0092] Note that the display device described in this embodiment has the pixel portion 102 and the driver circuit portion 104. The transistor and the protection circuit 106 can be formed simultaneously. The protection circuit 106 can be formed without increasing costs.

[0093] The structure described in this embodiment mode may be used in appropriate combination with structures described in other embodiments. can be done.

[0094] (Embodiment 3) In this embodiment mode, a manufacturing method of the display device described in Embodiment Mode 2 will be described with reference to FIGS. 12 will be used to explain.

[0095] First, a substrate 202 is prepared. The substrate 202 is made of aluminosilicate glass, aluminum, or the like. Glass materials such as minoborosilicate glass and barium borosilicate glass are used. Above, the substrate 202 is 8th generation (2160mm x 2460mm), 9th generation (2400 mm x 2800 mm, or 2450 mm x 3050 mm, 10th generation (2950 mm It is preferable to use mother glass such as a glass with a diameter of 3400 mm. When using mother glass for mass production, the temperature is high and the processing time is long, so the glass shrinks significantly. The heat treatment in the manufacturing process is preferably performed at 600° C. or less, more preferably at 450° C. or less, More preferably, the temperature is set to 350° C. or lower.

[0096] Next, a conductive film is formed on the substrate 202 and processed into a desired region. The conductive layers 204a, 204b, 204c, and 204d are formed. The formation of 204b, 204c, and 204d is performed by forming a mask by first patterning in a desired area. and then etching the area not covered by the mask. (See Figure 7(A)).

[0097] The conductive layers 204a, 204b, 204c, and 204d may be made of aluminum, chromium, or copper. , tantalum, titanium, molybdenum, tungsten, or a metal element selected from the group consisting of It is formed using an alloy containing metal elements or an alloy combining the above-mentioned metal elements. The conductive layers 204a, 204b, 204c, and 204d may also have a single-layer structure. For example, a titanium film may be stacked on an aluminum film. Layer structure, two-layer structure with titanium film stacked on titanium nitride film, tungsten on titanium nitride film Two-layer structure with laminated films, tungsten film on tantalum nitride film or tungsten nitride film A two-layer structure, a titanium film and an aluminum film laminated on top of the titanium film, There are also three-layer structures, such as aluminum with titanium, tantalum, A film of an element selected from tungsten, molybdenum, chromium, neodymium, and scandium, or Alternatively, an alloy film or a nitride film may be used. The layers 204b, 204c, and 204d can be formed by using, for example, a sputtering method. This can be done.

[0098] Furthermore, the conductive layer 204a of the protective circuit 106 and the pixel portion 102 are formed by the above process. The conductive layer 204c of the driving circuit section 104 and the conductive layer 204b of the driving circuit section 104 are formed on the same plane. It can be achieved.

[0099] Next, an insulating layer 2 is formed on the substrate 202 and the conductive layers 204a, 204b, 204c, and 204d. 06, 208 are formed (see FIG. 7(B)).

[0100] The insulating layer 206 may be, for example, a silicon nitride oxide film, a silicon nitride film, or an aluminum oxide film. A film such as a silicon film can be used, and it can be formed as a laminate or a single layer using a PE-CVD device. When the insulating layer 206 has a laminated structure, a silicon nitride film with few defects is used as the first silicon nitride film. A silicon nitride film was used as the first silicon nitride film, and a second silicon nitride film was used as the second silicon nitride film. It is preferable to provide a silicon nitride film that emits less ammonia. The hydrogen and nitrogen contained in the SiO 2 layer can suppress migration to the semiconductor layers 210a and 210b. It is possible.

[0101] The insulating layer 208 may be a silicon oxide film, a silicon oxynitride film, or the like. The insulating layer 206 and the insulating layer 208 are formed as a laminate or a single layer using an E-CVD apparatus. When they are formed successively in a vacuum, impurities are less likely to be mixed into the interface between the insulating layer 206 and the insulating layer 208. In addition, the insulating layer 206 in the region overlapping with the conductive layers 204b and 204c is preferably 208 can function as a gate insulating layer, for example, a 3 mm thick insulating layer as the insulating layer 206. A 50 nm thick silicon nitride film is applied as the insulating layer 208. A polyimide film can be applied.

[0102] Silicon nitride oxide is an insulating material with a higher nitrogen content than oxygen. Silicon oxynitride refers to an insulating material that contains more oxygen than nitrogen.

[0103] By configuring the gate insulating layer as described above, the following effects can be obtained, for example: Silicon nitride film has a higher dielectric constant than silicon oxide film, and it can be used at the same static Because the film thickness required to obtain capacitance is large, it is not possible to physically thicken the gate insulating film. Therefore, it is possible to suppress the decrease in the dielectric strength voltage of the transistor and further improve the dielectric strength voltage, Electrostatic breakdown of the transistor can be suppressed.

[0104] Next, a semiconductor film is formed on the insulating layer 208, and the semiconductor film is processed into a desired region. The semiconductor layers 210a and 210b are formed by Then, a mask is formed in a desired region by a second patterning, and the region not covered by the mask is removed. The etching can be performed by dry etching. Chilling, wet etching, or a combination of both can be used. (See FIG. 8(A)).

[0105] The semiconductor layers 210a and 210b may be made of, for example, an oxide semiconductor. The oxide semiconductor that can be applied to the semiconductor layers 210a and 210b is at least indium (In ), zinc (Zn) and M (Al, Ga, Ge, Y, Zr, Sn, La, Ce or Hf, etc. Preferably, the layer contains a layer represented by In-M-Zn oxide containing the metals. It is preferable that the oxide semiconductor contains both n and Zn. It is preferable to include a stabilizer therewith to reduce variations in air properties.

[0106] The stabilizers include gallium (Ga), tin (Sn), hafnium (Hf), and aluminum. Aluminum (Al) or zirconium (Zr), etc. Also, other stabilizers The lanthanides include lanthanum (La), cerium (Ce), and praseodymium ( Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium Er, Thulium, Ytterbium, Lutetium, etc. do.

[0107] For example, oxide semiconductors include indium oxide, tin oxide, zinc oxide, and In-Zn oxide. Sn-Zn oxide, Al-Zn oxide, Zn-Mg oxide, Sn-Mg oxide, In -Mg oxide, In-Ga oxide, In-Ga-Zn oxide, In-Al-Zn oxide, In-Sn-Zn oxide, Sn-Ga-Zn oxide, Al-Ga-Zn oxide, Sn-A l-Zn oxide, In-Hf-Zn oxide, In-La-Zn oxide, In-Ce-Zn Oxide, In-Pr-Zn oxide, In-Nd-Zn oxide, In-Sm-Zn oxide, In-Eu-Zn oxide, In-Gd-Zn oxide, In-Tb-Zn oxide, In-D In-Zn oxide, In-Ho-Zn oxide, In-Er-Zn oxide, In-Tm-Zn Oxide, In-Yb-Zn oxide, In-Lu-Zn ​​oxide, In-Sn-Ga-Zn oxide oxide, In-Hf-Ga-Zn oxide, In-Al-Ga-Zn oxide, In-Sn-A In-Zn oxide, In-Sn-Hf-Zn oxide, In-Hf-Al-Zn oxide It is possible.

[0108] Here, for example, In-Ga-Zn oxide is a material containing In, Ga, and Zn as its main components. The ratio of In, Ga, and Zn is not important. In addition, in this specification, the term "In-Ga" refers to a metal element other than In and Zn. A film made of -Zn oxide is also called an IGZO film.

[0109] In addition, InMO3(ZnO) m (m>0 and m is not an integer) M may be one metal element selected from Ga, Fe, Mn and Co, or indicates multiple metal elements. Also, In2SnO5(ZnO)n (n>0 and n is an integer ) may also be used.

[0110] Note that the oxide semiconductor film is preferably formed by sputtering. The sputtering methods include RF sputtering, DC sputtering, and AC sputtering. In particular, it is possible to reduce dust generated during film formation and to achieve a uniform film thickness distribution. It is preferable to use the DC sputtering method in order to obtain a uniform result.

[0111] Here, the structure of the oxide semiconductor film will be described.

[0112] Oxide semiconductor films are roughly classified into non-single-crystal oxide semiconductor films and single-crystal oxide semiconductor films. The non-single-crystal oxide semiconductor film is a CAAC-OS (C Axis Aligned Crystal Polycrystalline oxide semiconductor film The oxide semiconductor film includes a film, a microcrystalline oxide semiconductor film, an amorphous oxide semiconductor film, and the like.

[0113] First, the CAAC-OS film will be described.

[0114] The CAAC-OS film is one of the oxide semiconductor films that has multiple crystal parts aligned along the c-axis. .

[0115] The CAAC-OS film was observed under a transmission electron microscope (TEM). When observed under a tron ​​microscope, clear boundaries between the crystals are observed. It is not possible to confirm the grain boundary. It can be said that the AAC-OS film is less susceptible to the decrease in electron mobility caused by grain boundaries.

[0116] The CAAC-OS film was observed by TEM from a direction roughly parallel to the sample surface (cross-sectional TEM observation). When observed, it can be confirmed that metal atoms are arranged in layers in the crystalline part. Each layer of the CAAC-OS film is formed on a surface (also called a surface to be formed) or on a concave surface of the upper surface. The shape reflects the convexity and is aligned parallel to the surface on which the CAAC-OS film is formed or the upper surface.

[0117] On the other hand, the CAAC-OS film was observed by TEM from a direction approximately perpendicular to the sample surface (plane T EM observation reveals that metal atoms are arranged in triangular or hexagonal shapes in the crystalline region. However, no regularity was observed in the arrangement of metal atoms between different crystal regions. do not have.

[0118] Cross-sectional and planar TEM observations revealed that the crystals in the CAAC-OS film had an orientation. It can be seen that this is the case.

[0119] In this specification, "parallel" means that two straight lines are at an angle of -10° or more and 10° or less. Therefore, it also includes the case where the angle is between -5° and 5°. "Perpendicular" refers to two straight lines that form an angle of 80° or more and 100° or less. Therefore, the angle may be between 85° and 95°.

[0120] In addition, most of the crystals in the CAAC-OS film are cubic crystals with sides of less than 100 nm. Therefore, the crystal part in the CAAC-OS film has a side length of 10 This also includes cases where the size fits within a cube of less than 5 nm, or less than 3 nm. However, multiple crystals in the CAAC-OS film are connected to form a single large crystal domain. For example, in a planar TEM image,2 Over 5μm 2 or more than 1000μm 2 Crystal regions with more than this size may be observed.

[0121] X-ray diffraction (XRD) of the CAAC-OS film When structural analysis is performed using this device, for example, CAAC-OS with InGaZnO4 crystals can be seen. In the out-of-plane analysis of the film, the diffraction angle (2θ) peaks around 31°. This peak is attributed to the (009) plane of the InGaZnO4 crystal. Therefore, the crystals of the CAAC-OS film have a c-axis orientation, and the c-axis faces the surface on which the film is formed or the upper surface. It can be seen that the direction is roughly vertical.

[0122] On the other hand, the in-p X-rays incident on the CAAC-OS film are perpendicular to the c-axis. In the Lane analysis, a peak may appear around 2θ of 56°. The crystal structure of InGaZnO4 is composed of a single crystal of InGaZnO4. In the case of a nitride semiconductor film, 2θ is fixed at around 56°, and the normal vector of the sample surface is the axis (φ axis). When the sample is rotated and analyzed (φ scan), a crystal plane equivalent to the (110) plane is detected. In contrast, in the case of the CAAC-OS film, six peaks are observed, which are assigned to 2θ. Even when the φ is fixed at around 56° and scanned, no clear peak appears.

[0123] From the above, it can be concluded that the orientation of the a-axis and b-axis is uniform between different crystal regions in the CAAC-OS film. Although it is irregular, it has a c-axis orientation, and the c-axis is parallel to the normal vector of the surface on which it is formed or the upper surface. Therefore, the layered structure confirmed by the cross-sectional TEM observation mentioned above is consistent with the Each layer of arranged metal atoms is a plane parallel to the ab plane of the crystal.

[0124] The crystalline part is formed when the CAAC-OS film is formed or after a crystallization treatment such as a heat treatment. As described above, the c-axis of the crystal is aligned with the surface on which the CAAC-OS film is to be formed. Therefore, for example, in the CAAC-OS film, When the shape is changed by etching, the c-axis of the crystal is aligned with the CAAC-OS film. It may not be parallel to the normal vector of the face or top surface.

[0125] Furthermore, the distribution of c-axis oriented crystals in the CAAC-OS film does not need to be uniform. For example, the crystalline part of the CAAC-OS film is grown from the top surface of the CAAC-OS film. Therefore, when the crystal is formed, the region near the top surface has a crystal orientation that is more c-axis oriented than the region near the surface on which the crystal is formed. In addition, when impurities are added to the CAAC-OS film, the proportion of the impurity The region where the material was added is transformed, and regions with different proportions of c-axis oriented crystals are formed. It may also be possible.

[0126] In addition, the out-of-plane structure of the CAAC-OS film with InGaZnO4 crystals In the analysis by the NMR method, in addition to the peak at 2θ near 31°, a peak also appeared at 2θ near 36°. The peak at 2θ around 36° is due to the presence of c-axis orientation in part of the CAAC-OS film. The CAAC-OS film contains crystals that do not have crystalline structure. It is preferable that the peak is exhibited at 2θ of about 36° and that the peak is not exhibited at 2θ of about 36°.

[0127] The CAAC-OS film is an oxide semiconductor film with a low concentration of impurities. The oxide semiconductor film is made of an element other than the main component, such as silicon or a transition metal element. The elements such as ZnO, which have stronger bonding strength with oxygen than the metal elements constituting the oxide semiconductor film, By removing oxygen from the oxide semiconductor film, the atomic arrangement of the oxide semiconductor film is disrupted, and the crystallinity is reduced. In addition, heavy metals such as iron and nickel, argon, and carbon dioxide are Because the diameter (or molecular radius) is large, when the molecule is contained inside the oxide semiconductor film, The impurities contained in the oxide semiconductor film are likely to disturb the atomic arrangement of the oxide semiconductor film, which may result in a decrease in crystallinity. The pure material may act as a carrier trap or a carrier generation source.

[0128] The CAAC-OS film is an oxide semiconductor film with a low density of defect states. Oxygen vacancies in semiconductor films can act as carrier traps and trap hydrogen. This can become a carrier generation source.

[0129] The low impurity concentration and low defect level density (low oxygen vacancies) are called high-purity intrinsic or The term "high-purity intrinsic" refers to a substantially high-purity intrinsic oxide semiconductor. Since the film has a small number of carrier generation sources, the carrier density can be reduced. The transistor using the oxide semiconductor film has electrical characteristics (noise) such that the threshold voltage is negative. It is also called "marine.") It is rare for it to become pure or substantially pure. An intrinsic oxide semiconductor film has few carrier traps. Transistors using this film have little fluctuation in electrical characteristics and are highly reliable. Note that it takes time for the charges trapped in the carrier traps in the oxide semiconductor film to be released. The time is long and the charge may behave as if it is fixed. Therefore, a transistor using an oxide semiconductor film with a high density of defect states has unstable electrical characteristics. This may be the case.

[0130] In addition, the electrical characteristics of transistors using CAAC-OS films are improved by irradiation with visible light or ultraviolet light. There is little gender variation.

[0131] Next, a microcrystalline oxide semiconductor film will be described.

[0132] In the microcrystalline oxide semiconductor film, crystal parts can be clearly seen in the TEM image. The crystal parts contained in the microcrystalline oxide semiconductor film may have a size of 1 nm or more and 100 nm or more. In particular, the size of the particles is between 1 nm and 10 nm. Nanocrystals (nc) are microcrystals with a diameter of 1 nm or less, or 1 nm to 3 nm. The oxide semiconductor film having nc-OS (nanocrystalline O The nc-OS film is called an oxide semiconductor film. In EM observation images, the grain boundaries may not be clearly visible.

[0133] The nc-OS film is a microscopic region (e.g., a region of 1 nm to 10 nm, especially a region of 1 nm or less). The nc-OS film has a periodic atomic arrangement in the region of 3 nm or less. There is no regularity in the crystal orientation between the crystal parts, and therefore no orientation is observed throughout the film. Therefore, the nc-OS film cannot be distinguished from an amorphous oxide semiconductor film depending on the analytical method. For example, XRD, which uses X-rays with a diameter larger than that of the crystal part, is used for nc-OS films. When structural analysis is performed using the device, the crystal plane is analyzed using the out-of-plane method. In addition, the peaks shown in the figure are not detected in the nc-OS film because the probe diameter is larger than that of the crystalline part. Electron beam diffraction (also called selected area electron beam diffraction) using an electron beam (for example, 50 nm or larger) When the diffraction pattern is changed to nc-OS film, a halo-like diffraction pattern is observed. The probe diameter is close to or smaller than the size of the crystal part (for example, 1 nm or more and 30 nm or less). When electron beam diffraction (also called nanobeam electron diffraction) is performed using the electron beam (bottom), Furthermore, when nanobeam electron diffraction is performed on the nc-OS film, a circular pattern is observed. In addition, a bright area (ring-shaped) may be observed for the nc-OS film. When performing nanobeam electron diffraction, multiple spots may be observed within a ring-shaped region. be.

[0134] The nc-OS film is an oxide semiconductor film with higher order than an amorphous oxide semiconductor film. Therefore, the nc-OS film has a lower density of defect states than the amorphous oxide semiconductor film. In the nc-OS film, there is no regularity in the crystal orientation between different crystal parts. The OS film has a higher density of defect states than the CAAC-OS film.

[0135] The oxide semiconductor film may be, for example, an amorphous oxide semiconductor film, a microcrystalline oxide semiconductor film, or a C The AAC-OS film may be a laminate film having two or more kinds of films.

[0136] In addition, the following conditions are preferably applied to form the CAAC-OS film.

[0137] By reducing the amount of impurities mixed in during film formation, it is possible to prevent the crystal state from being destroyed by impurities. For example, it is possible to reduce impurities (hydrogen, water, carbon dioxide, nitrogen, etc.) present in the film formation chamber. Also, impurities in the deposition gas should be reduced. Specifically, the dew point should be -80°C. Hereinafter, a deposition gas at a temperature of -100°C or less is preferably used.

[0138] In addition, by increasing the substrate heating temperature during film formation, migration of sputtered particles after reaching the substrate is prevented. Specifically, the substrate heating temperature is set to 100°C or higher and 740°C or lower, preferably 2 The film is formed at a temperature between 00°C and 500°C. By increasing the substrate heating temperature during film formation, a flat plate-like When the sputtered particles reach the substrate, migration occurs on the substrate, and the sputtered particles The flat surface of the element is attached to the substrate.

[0139] In addition, by increasing the oxygen ratio in the deposition gas and optimizing the power, plasma damage during deposition can be reduced. The oxygen ratio in the film forming gas is 30% by volume or more, preferably 100% by volume or more. Expressed as volume %.

[0140] As an example of a sputtering target, an In-Ga-Zn-O compound target is used. The details are shown below.

[0141] InO X powder, GaO Y Powder and ZnO Z The powders are mixed in a predetermined number of moles, and after pressure treatment, By heat treatment at temperatures between 1000℃ and 1500℃, polycrystalline In-Ga- The target is a Zn-O compound. X, Y, and Z are arbitrary positive numbers. The type of powder and the molar ratio of the powder to be mixed depend on the sputtering target to be produced. It can be changed as appropriate.

[0142] Next, it is preferable to perform a first heat treatment. ℃ or less, preferably 300℃ to 500℃, in an inert gas atmosphere, an oxidizing gas atmosphere The first heat treatment may be carried out in an atmosphere containing 10 ppm or more of fluorine or under reduced pressure. The atmosphere is an inert gas atmosphere, and then an oxidizing gas is introduced to replace the oxygen that has been removed. The first heat treatment may be performed in an atmosphere containing 10 ppm or more of fluorine. , 210b, and the insulating layers 206, 208, and the semiconductor Impurities such as hydrogen and water can be removed from the conductor layers 210a and 210b. A first heating step may be performed before etching to form the nitride semiconductor layer.

[0143] In order to provide stable electrical characteristics to a transistor having an oxide semiconductor layer as a channel, To achieve this, the impurity concentration in the oxide semiconductor layer is reduced to make the oxide semiconductor layer intrinsic or substantially Here, the term "substantially intrinsic" means that the carrier density of the oxide semiconductor layer is Degrees is 1 x 10 17 / cm 3 preferably less than 1 x 10 15 / cm 3 Less than More preferably, 1×10 13 / cm 3 It means that it is less than.

[0144] In addition, in the oxide semiconductor layer, hydrogen, nitrogen, carbon, silicon, and a metal other than the main component Elements become impurities. For example, hydrogen and nitrogen form donor levels and increase the carrier density. Moreover, silicon forms impurity levels in the oxide semiconductor layer. The pure level may become a trap and degrade the electrical characteristics of the transistor.

[0145] In order for the oxide semiconductor layer to be intrinsic or substantially intrinsic, it is necessary to determine whether the oxide semiconductor layer is intrinsic or substantially intrinsic in the SIMS analysis. The silicon concentration is 1×10 19 atoms / cm 3 Less than 5 x 10 18 a toms / cm 3 less than 1×10 18 atoms / cm 3 Less than. The hydrogen concentration is 2×10 20 atoms / cm 3 Less than or equal to 5 x 10 19 at oms / cm 3 Less than or equal to 1×10 19 atoms / cm 3 Below are some more preferred Or 5 x 10 18 atoms / cm 3 The nitrogen concentration is 5 x 10 19 a toms / cm 3 Less than 5 x 10 18 atoms / cm 3 The following is more preferable: is 1 x 10 18 atoms / cm 3 Less than 5 × 10, more preferably 17 atoms / c m 3 The following applies.

[0146] In addition, when the oxide semiconductor layer contains crystals, if silicon or carbon is contained at a high concentration, the oxide semiconductor layer may be oxidized. In order to prevent the crystallinity of the oxide semiconductor layer from being reduced, To do this, the silicon concentration is set to 1×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 less than 1×10 18 atoms / cm3 Less than In addition, the carbon concentration is 1×10 19 atoms / cm 3 Less than 5 x 10 1 8 atoms / cm 3 less than 1×10 18 atoms / cm 3 Less than That's fine.

[0147] In addition, a transistor using the purified oxide semiconductor layer as described above for a channel formation region can be fabricated. The off-state current of a transistor is extremely small, and the off-state current normalized by the channel width of the transistor is It is possible to reduce the current to several yA / μm to several zA / μm.

[0148] In addition, the oxide semiconductor layer can be used to reduce the localized levels in the layer. It is possible to provide stable electrical characteristics to the transistor. In order to provide good electrical properties, CPM (Constant Phase Magnetization) measurement in the oxide semiconductor layer is required. The absorption coefficient due to the localized level obtained by the nt Photocurrent Method is , 1×10 -3 / cm, preferably less than 3 × 10 -4 / cm or less.

[0149] Next, a mask is formed on the insulating layer 208 by a third patterning. By etching the unetched area, a part of the insulating layer 208 on the protection circuit 106 and The insulating layers 206 and 208 on the connecting portion 109 are partially removed. The formation of the 07b may be performed before the formation of the semiconductor layers 210a and 210b (see FIG. 8(B)). ).

[0150] In addition, a multi-tone mask can be used to form the mask by the third patterning. A multi-tone mask has three exposure levels: exposed, intermediately exposed, and unexposed. It is an exposure mask that can be used to expose a variety of areas, and the light that passes through it has multiple intensities. The exposure and development process produces a resist mask with multiple (typically two) thickness regions. Therefore, by using a multi-tone mask, it is possible to form an exposure mask. It is possible to reduce the number of masks. Examples of multi-tone masks include half-tone masks, Alternatively, a gray tone mask may be used.

[0151] The third patterning is performed by using a multi-tone mask to form openings 207a and 207b. The openings 207a and 207b can be formed to have different depths. The insulating layer 206 is exposed in the opening 207b, and the conductive layer 204d is exposed in the opening 207c. The method for forming the openings 207a and 207b is not limited to this, and can be, for example, Alternatively, patterning may be performed using different masks.

[0152] As a result, the insulating layers 206 and 208 formed in the pixel section 102 and the driving circuit section 104 can function as a gate insulating layer of the stack. The insulating layer 206 can function as a resistive element.

[0153] Next, on the insulating layers 206 and 208, the semiconductor layers 210a and 210b, and the conductive layer 204d Conductive layers 212a, 212b, and 212c, 212d, 212e, and 212f are formed. , 212c, 212d, 212e, 212f are formed in the desired area, and the fourth patterning The mask is formed by etching the area not covered by the mask. This can be achieved (see FIG. 9(A)).

[0154] Furthermore, the conductive layer 212a of the protective circuit 106 and the pixel portion 102 are formed by the above process. and conductive layers 212b and 212c of the driving circuit section 104. and can be formed on the same plane.

[0155] The conductive layers 212a, 212b, 212c, 212d, 212e, and 212f are made of conductive Materials include aluminum, titanium, chromium, nickel, copper, yttrium, and zirconium. Elemental metals consisting of aluminum, molybdenum, silver, tantalum, or tungsten, or metals consisting mainly of these The alloy containing the element is used as a single layer structure or a laminated structure. For example, Two-layer structure with titanium film laminated on top of tungsten film, two-layer structure with titanium film laminated on top of tungsten film, copper-magnesium Two-layer structure consisting of copper film laminated on a neodymium-aluminum alloy film, titanium film or titanium nitride film a titanium film or titanium nitride film, and an aluminum film or copper film is laminated on the titanium film or titanium nitride film; A three-layer structure in which a titanium film or titanium nitride film is formed on top of the molybdenum film or nitride film Molybdenum nitride film and aluminum film overlaid on the molybdenum film or molybdenum nitride film Alternatively, a copper film is laminated, and a molybdenum film or molybdenum nitride film is formed on top of the copper film. It should be noted that transparent conductive materials containing indium oxide, tin oxide, or zinc oxide are used. In addition, the conductive layers 212a, 212b, 212c, 212d, 212e, and 212 For example, f can be formed by using a sputtering method.

[0156] In this embodiment, the conductive layers 212b, 212c, 212d, and 212e are semiconductor layers. 210a and 210b, but was provided between the insulating layer 208 and the semiconductor layers 210a and 210b. It's okay to do that.

[0157] Next, the insulating layer 208, the semiconductor layers 210a and 210b, and the conductive layers 212a and 212b, Insulating layers 214 and 216 are formed to cover 212c, 212d, 212e, and 212f. (See FIG. 9(B)).

[0158] The insulating layer 214 is formed at the interface with the oxide semiconductor used as the semiconductor layers 210a and 210b. In order to improve the surface characteristics, an inorganic insulating material containing oxygen can be used. 216 is a layer formed by adding an external impurity to an oxide semiconductor used as the semiconductor layers 210a and 210b. It is preferable to use a material that is less susceptible to impurities such as moisture. The insulating layers 214 and 216 may be made of, for example, an inorganic insulating material containing The film can be formed by using a PE-CVD method.

[0159] As an example, the insulating layer 214 is a silicon oxide film having a thickness of 150 nm to 400 nm. The insulating layer 216 can be formed using a silicon oxide nitride film, a silicon oxynitride film, an aluminum oxide film, or the like. Examples include silicon nitride films and silicon nitride oxide films with a thickness of 150 nm to 400 nm. In this embodiment, the insulating layer 214 can be made of a 300 nm thick film. A silicon oxynitride film having a thickness of 150 nm was used as the insulating layer 216. At this time, the silicon nitride film prevents moisture from entering the semiconductor layers 210a and 210b. The silicon nitride film functions as a blocking layer to prevent the Therefore, it is preferable to form the film at a high temperature, for example, a substrate temperature of 100° C. or higher but lower than the distortion point of the substrate. It is more preferable to form the film by heating at a temperature of 300° C. or more and 400° C. or less. In addition, when the film is formed at a high temperature, the oxide semiconductor used as the semiconductor layers 210a and 210b Oxygen may be released and the carrier concentration may increase. The temperature at which no

[0160] Next, the insulating layer 218 is formed over the insulating layer 216 (see FIG. 10A).

[0161] The insulating layer 218 may be made of an acrylic resin, a polyimide resin, or a benzocyclobutene resin. Heat-resistant organic materials such as grease, polyamide resin, and epoxy resin can be used. In addition, the insulating layer 218 can be formed by stacking a plurality of insulating films made of these materials. By using the insulating layer 218, unevenness of the transistor and the like can be flattened. The insulating layer 218 can be formed by using, for example, a spin coating method. It is possible.

[0162] In addition, examples of acrylic resins that can be used for the insulating layer 218 include water-absorbent The material has low thermal conductivity and releases little outgassing components (e.g., H2O, C, F, etc.) from the film. It is preferable to use it.

[0163] Next, a mask is formed on the insulating layer 218 by a fifth patterning. The unetched areas are etched to form openings 219a, 219b, and 219c. (See FIG. 10(B)).

[0164] The openings 219a, 219b, and 219c are formed by the conductive layers 212b, 212d, and Formed to reach 212e.

[0165] Next, a conductive film is formed to fill the openings 219a, 219b, and 219c. The film is processed into desired regions to form conductive layers 220a, 220b, and 220c. The formation of the conductive layers 220a, 220b, and 220c is performed by the sixth patterning in desired areas. The mask is formed by etching the area not covered by the mask. This can be done (see Figure 11).

[0166] The conductive layers 220a, 220b, and 220c are made of indium oxide containing tungsten oxide. oxide, indium zinc oxide with tungsten oxide, indium oxide with titanium oxide Indium tin oxide (hereinafter referred to as ITO) ), indium zinc oxide, indium tin oxide with silicon oxide added, etc. The conductive layers 220a, 220b, and 220c can be made of a conductive material. For example, the film can be formed by sputtering.

[0167] Through the above steps, a pixel portion having a transistor and a driver circuit portion are formed on the substrate 202. The protection circuit and the protection circuit can be formed over the same substrate. In the process, the first to sixth patterning steps, i.e., the transistors and The protection circuit can be formed simultaneously.

[0168] Next, the structure formed on the substrate 252 provided opposite the substrate 202 will be described below. Give an explanation.

[0169] First, a substrate 252 is prepared. The substrate 252 is made of the same material as the substrate 202. Next, a colored layer 254 and an insulating layer 256 are formed on the substrate 252 (FIG. 12( See A).

[0170] The colored layer 254 may be a colored layer that transmits light in a specific wavelength band. For example, A red (R) color filter that transmits light in the red wavelength band, and a green color filter that transmits light in the green wavelength band A green (G) color filter transmits light in the blue wavelength band, and a blue (B) color filter transmits light in the blue wavelength band. Each color filter can be made of a known material by a printing method, Inkjet method, etching method using photolithography technology, etc. The insulating layer 256 is formed at the position indicated by the arrows. It can be used.

[0171] Next, the conductive layer 258 is formed over the insulating layer 256 (see FIG. 12B). As the conductive layers, the materials shown in the conductive layers 220a, 220b, and 220c can be used.

[0172] Next, a liquid crystal layer 260 is formed between the substrate 202 and the substrate 252. The deposition method may be a dispenser method (dropping method) or a method in which the substrate 202 and the substrate 252 are bonded together. Then, a liquid crystal is injected by using capillary action.

[0173] Through the above steps, the display device shown in FIG. 6 can be manufactured.

[0174] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. do.

[0175] (Fourth embodiment) In this embodiment, the semiconductor device can be used in the pixel circuit 108 of the display device shown in FIG. A possible configuration will be explained with reference to FIG.

[0176] In the display device shown in FIG. 1A, the pixel circuit 108 has a structure as shown in FIG. It can be concluded that

[0177] The pixel circuit 108 shown in FIG. 13A includes a liquid crystal element 130, a transistor 131_1, and a , and a capacitor 133_1.

[0178] The potential of one of the pair of electrodes of the liquid crystal element 130 is set appropriately according to the specifications of the pixel circuit 108. The orientation state of the liquid crystal element 130 is set by the written data. A common potential is applied to one of the pair of electrodes of the liquid crystal element 130 of each of the pixel circuits 108. A common potential may be applied to each pair of liquid crystal elements 130 in each row of pixel circuits 108. A different potential may be applied to one of the electrodes.

[0179] For example, the display device including the liquid crystal element 130 can be driven in a TN mode, an STN mode, or the like. Mode, VA mode, ASM (Axially Symmetric Aligned Mode) Micro-cell mode, OCB (Optically Compensated Birefringence mode, FLC (Ferroelectric Liquid Crystal id Crystal) mode, AFLC (AntiFerroelectric Li quid Crystal) mode, MVA (Multi-Domain Vertic) mode al Alignment) mode, PVA(Patterned Vertical) mode Alignment mode, IPS mode, FFS mode, or TBA (Transv A display device such as a (Under-Bend Alignment) mode may also be used. In addition to the above-mentioned driving method, ECB (Electrically Controlled Bias Current) Controlled Birefringence mode, PDLC (Polymer Dispersed Liquid Crystal mode, PNLC (Polymer Network Liquid Crystal mode, guest host mode, etc. However, the present invention is not limited to this, and various liquid crystal elements and their driving methods can be used. It is possible.

[0180] Also, a liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent The liquid crystal element may be configured by the following. The liquid crystal that exhibits the blue phase has a response speed of 1 msec or less. Since it is short and optically isotropic, alignment treatment is not required and viewing angle dependency is small.

[0181] In the pixel circuit 108 in the mth row and the nth column, the source and drain of the transistor 131_1 One of them is electrically connected to the data line DL_n, and the other is a pair of electrodes of the liquid crystal element 130. The gate of the transistor 131_1 is electrically connected to the other of the scan lines GL_m. The transistor 131_1 is electrically connected to the This provides a function of controlling the writing of data signals.

[0182] One of the pair of electrodes of the capacitor 133_1 is connected to a wiring to which a potential is supplied (hereinafter, a potential supply line VL), and the other is electrically connected to the other of the pair of electrodes of the liquid crystal element 130. The value of the potential of the potential supply line VL is set appropriately according to the specifications of the pixel circuit 108. The capacitor 133_1 has a function as a storage capacitor for storing written data. do.

[0183] For example, in a display device having the pixel circuit 108 shown in FIG. 13A, the gate driver 104 The pixel circuits 108 in each row are selected in sequence by a, and the transistors 131_1 are turned on. Write the data of the data signal.

[0184] In the pixel circuit 108 to which the data is written, the transistor 131_1 is turned off. By repeating this process for each row, an image can be displayed.

[0185] The pixel circuit 108 shown in FIG. 13B includes a transistor 131_2 and a capacitor 1 33_2, a transistor 134, and a light-emitting element 135.

[0186] One of the source and drain of the transistor 131_2 is connected to a wiring to which a data signal is applied. (hereinafter referred to as data line DL_n). The gate of _2 is electrically connected to the wiring to which the gate signal is given (hereinafter referred to as the scanning line GL_m). is connected to.

[0187] The transistor 131_2 is turned on or off to control the data signal. It has the function of controlling the writing of data.

[0188] One of the pair of electrodes of the capacitor 133_2 is connected to a wiring to which power is supplied (hereinafter, referred to as a power supply line VL _a), and the other is electrically connected to the source and drain of the transistor 131_2. The other terminal is electrically connected to the other terminal.

[0189] The capacitor 133_2 has a function as a storage capacitor for storing written data. .

[0190] One of the source and drain of the transistor 134 is electrically connected to the power supply line VL_a. Furthermore, the gate of the transistor 134 is connected to the source and drain of the transistor 131_2. The other of the drains is electrically connected to the other of the drains.

[0191] One of the anode and the cathode of the light emitting element 135 is electrically connected to the power supply line VL_b. The other is electrically connected to the other of the source and drain of the transistor 134 .

[0192] The light emitting element 135 may be, for example, an organic electroluminescence element (also known as an organic EL element). However, the light emitting element 135 is not limited to this. Alternatively, an inorganic EL element made of an inorganic material may be used.

[0193] A high power supply potential VDD is applied to one of the power supply lines VL_a and VL_b. The other is supplied with the low power supply potential VSS.

[0194] In the display device having the pixel circuit 108 of FIG. 13B, the gate driver 104a The pixel circuits 108 in each row are selected in sequence, and the transistors 131_2 are turned on to output data signals. Write the data of the number.

[0195] In the pixel circuit 108 to which the data is written, the transistor 131_2 is turned off. Furthermore, the transistor 13 is turned on in response to the potential of the written data signal. The amount of current flowing between the source and drain of the light emitting element 135 is controlled. By performing this process row by row, an image can be displayed.

[0196] In this specification and the like, the term "display element," "display device having a display element," "light emitting element," "light emitting device," "light emitting element ... A light-emitting device, which is a device having a light-emitting element and a light-emitting element, can be formed in various forms or in various forms. Examples of a display element, a display device, a light-emitting element, or a light-emitting device include , EL (electroluminescence) elements (EL elements containing organic and inorganic materials, organic EL elements, inorganic EL elements), LEDs (white LEDs, red LEDs, green LEDs, blue LEDs, etc. ), transistors (transistors that emit light according to the current), electron-emitting devices, liquid crystal devices, Dye ink, electrophoretic element, grating light valve (GLV), plasma display PDP, Digital Micromirror Device (DMD), Piezoelectric Ceramic Display Spray, carbon nanotubes, etc., electromagnetic effects, contrast, brightness, Some display devices use EL elements, which have display media with variable reflectance and transmittance. An example of such a display device is an EL display. For example, a field emission display (FED) or an SED type flat panel display Ray (SED: Surface-conduction Electron-emitting An example of a display device using a liquid crystal element is a liquid crystal display. Display (transmissive LCD display, semi-transmissive LCD display, reflective LCD display) LCDs include OLEDs (e.g., LCDs with a 1000 x 1000 pixel resolution ... An example of a display device using an electrophoretic element is electronic paper.

[0197] An example of an EL element is a device that includes an anode, a cathode, and an EL layer sandwiched between the anode and the cathode. An example of an EL layer is a device that uses light emission (fluorescence) from singlet excitons. those that utilize emission from triplet excitons (phosphorescence), and those that utilize emission from singlet excitons ( those that utilize fluorescence and those that utilize light emission from triplet excitons (phosphorescence), Those formed by organic matter, those formed by inorganic matter, those formed by organic matter Those containing polymeric materials and those formed by inorganic materials, those containing low molecular weight materials, Some contain polymeric materials, while others contain polymeric and low molecular weight materials. However, the present invention is not limited to this, and various EL elements can be used.

[0198] An example of a liquid crystal element is a device that controls the transmission or non-transmission of light by the optical modulation action of liquid crystal. The element can be constructed by a pair of electrodes and a liquid crystal layer. The optical modulation effect of the liquid crystal is achieved by applying an electric field (horizontal electric field, vertical electric field or oblique electric field) to the liquid crystal. Specifically, an example of a liquid crystal element is a matic liquid crystal, cholesteric liquid crystal, smectic liquid crystal, discotic liquid crystal, thermo Lyotropic liquid crystal, lyotropic liquid crystal, low molecular weight liquid crystal, polymer liquid crystal, polymer dispersed liquid crystal (PD LC), ferroelectric liquid crystal, antiferroelectric liquid crystal, main chain liquid crystal, side chain polymer liquid crystal, plasma address Examples include liquid crystal (PALC) and banana-shaped liquid crystal.

[0199] One example of the display method for electronic paper is a method using molecules (optical anisotropy, dye molecular orientation, etc.), those displayed by particles (electrophoresis, particle migration, particle rotation, phase change ), those that are displayed by moving one edge of the film, and those that are displayed by coloring / phase change of molecules. Some are displayed by the light absorption of molecules, others by the self-assembled electron and hole combination. It is possible to use a display that emits light. Specifically, an electronic paper display Examples of methods include microcapsule electrophoresis, horizontal migration electrophoresis, and vertical migration electrophoresis. Electrophoresis, spherical twist ball, magnetic twist ball, cylindrical twist ball method, charged toner -, electronic powder, magnetic migration type, magnetic heat sensitive type, electrowetting, light scattering (transparent / opacity change), cholesteric liquid crystal / photoconductive layer, cholesteric liquid crystal, bistable nematic Liquid crystal, ferroelectric liquid crystal, dichroic dye / liquid crystal dispersion type, movable film, color development / decolorization by leuco dye , photochromic, electrochromic, electrodeposition, flexible However, there are various electronic paper and display methods, including but not limited to these. Here, by using microcapsule electrophoresis, This can solve the aggregation and precipitation of electrophoretic particles. It has advantages such as high reflectance, wide viewing angle, low power consumption, and memory properties.

[0200] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. do.

[0201] (Embodiment 5) In this embodiment, a structure that can be used in the pixel portion 102 of the display device shown in FIG. The structure will be described with reference to FIG.

[0202] FIG. 14A shows part of the structure of a transistor that can be used in the pixel portion 102. 14(B) is a top view, and FIG. 14(B) corresponds to a cross section taken along the dashed line A1-A2 shown in FIG. 14(A). FIG. 14C shows a transistor that can be used in the pixel portion 102. 14(D) is a top view showing a part of the configuration, and FIG. 14(D) is a diagram showing the structure of the device along the dashed line B1-B shown in FIG. 14(C). 2. Also, the parts having the same functions as those described in the previous embodiment are The same reference numerals and hatchings are used for the corresponding parts, and detailed explanations thereof will be omitted. do.

[0203] In the top views shown in FIGS. 14A and 14C, the insulating layers 206, 208, and 214 , 216, 218, etc. are omitted in order to avoid cluttering the drawing.

[0204] The transistors that can be used in the pixel portion 102 shown in FIGS. A conductive layer 204a formed on the substrate 202, and a conductive layer 204a formed on the substrate 202 and the conductive layer 204a. The insulating layers 206 and 208 are formed on the insulating layer 208, and the semiconductor layer 210a is formed on the insulating layer 208. The structure includes conductive layers 212d and 212e electrically connected to 210a.

[0205] Moreover, insulating layers 214, 216, and 218 are formed above the transistors. Conductive layer 212e and conductive layer 220 are formed through openings in layers 214, 216, and 218. c is electrically connected.

[0206] The structure shown in FIGS. 14A and 14B differs from the structure shown in FIG. 6 in the position of the conductive layer 220c. Specifically, the structure shown in FIGS. 14(A) and 14(B) has a structure in which a portion of the semiconductor layer 210a overlaps the A conductive layer 220c is disposed in the region.

[0207] By using the structure shown in FIGS. 14A and 14B, the transistors used in the pixel portion 102 For overcurrent from above, the conductive layer 220c can be used to allow the overcurrent to escape.

[0208] The transistors that can be used in the pixel portion 102 shown in FIGS. A conductive layer 204a formed on the substrate 202, and a conductive layer 204a formed on the substrate 202 and the conductive layer 204a. The insulating layers 206 and 208 are formed on the insulating layer 208, and the semiconductor layer 210a is formed on the insulating layer 208. The structure includes conductive layers 212d and 212e electrically connected to 210a.

[0209] In addition, insulating layers 214, 216, and 218 are formed on the transistors. The conductive layer 212e and the conductive layer 220c are formed through the openings formed in the layers 14, 216, and 218. are electrically connected.

[0210] The structure shown in FIGS. 14(C) and 14(D) differs from the structure shown in FIG. 6 in the position of the insulating layer 208. Specifically, the structure shown in FIGS. 14(C) and 14(D) has a side edge of the semiconductor layer 210a and an insulating layer The semiconductor layer 210a is formed at a position substantially the same as the side end of the semiconductor layer 208. For example, the formation of the semiconductor layer 210a By using the mask at the time, a part of the insulating layer 208 is etched, and the insulating layer 208 is formed as shown in FIG. D).

[0211] By using the configuration shown in FIGS. 14(C) and 14(D), for example, the charged electrode on the conductive layer 220c can be The charge can be released through the conductive layer 212e and the insulating layer 206 to the conductive layer 204a.

[0212] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. do.

[0213] (Embodiment 6) In this embodiment, a configuration that can be used as the protection circuit 106 shown in FIG. This will be explained with reference to FIGS. 15 to 17.

[0214] 15A and 15B are top views of elements that can be used as the protection circuit 106. 15(C) is a cross section taken along dashed lines C1-C2 and C3-C4 shown in FIG. 15(A). 15(D) is a diagram corresponding to the dashed lines D1-D2 and D3- This is a view equivalent to the cross section of D4.

[0215] 15(A) and 15(C) show a resistive element that can be used as the protection circuit 106. 15(A) and 15(C) are made of an insulating layer formed on a substrate 202. 206, 208, and a semiconductor layer 210c formed on the insulating layer 208, and and conductive layers 212g and 212h electrically connected to each other.

[0216] 15(B) and (D) show resistive elements that can be used as the protection circuit 106. 15(B) and (D) are made of an insulating layer formed on the substrate 202. 206, 208, a semiconductor layer 210c formed on the insulating layer 208, and a conductive layer 212g , 212h, and the insulating layer 208, the semiconductor layer 210c, and the conductive layers 212g, 212h. The insulating layers 214, 216, and 218 are formed on the insulating layer 218, and the conductive layer 212g and the semiconductor layer A conductive layer 220d electrically connecting the conductor layer 210c and a conductive layer 220b formed on the insulating layer 218 The layer 212h and the conductive layer 220e electrically connect the semiconductor layer 210c.

[0217] The semiconductor layer 210c can be used as the resistor element. The resistivity can be controlled by configuring the dielectric layer 210c as shown in FIGS. 15(A) and 15(B). It is possible.

[0218] 16(A), (B), and (C) show circuits that can be used as the protection circuit 106. 1 shows an example of a road configuration.

[0219] The circuit configuration shown in FIG. 16A includes wirings 451, 452, and 481, a transistor 402, 404.

[0220] The transistor 402 has a first terminal that functions as a source electrode and a second terminal that functions as a gate electrode. The third terminal is electrically connected to the second terminal, which functions as a drain electrode, and is connected to the wiring 45. The first terminal of the transistor 402 is electrically connected to the wiring 481. The transistor 404 has a first terminal that functions as a source electrode and a second terminal that is electrically connected to the gate. The second terminal functions as a source electrode and the second terminal functions as a drain electrode. The third terminal of the transistor 404 is electrically connected to the wiring 452. The terminal is electrically connected to the wiring 481.

[0221] The circuit configuration shown in FIG. 16B includes wirings 453, 454, 482, 483, and 484, The configuration includes transistors 406, 408, 410, and 412.

[0222] The transistor 406 has a first terminal that functions as a source electrode and a second terminal that functions as a gate electrode. The third terminal is electrically connected to the second terminal, which functions as a drain electrode, and is connected to the wiring 48. 3. The first terminal of the transistor 406 is electrically connected to the wiring 482. are electrically connected.

[0223] The transistor 408 has a first terminal that functions as a source electrode and a second terminal that functions as a gate electrode. The third terminal is electrically connected to the second terminal, which functions as a drain electrode, and is connected to the wiring 48. The first terminal of the transistor 408 is electrically connected to the wiring 483. are electrically connected.

[0224] The transistor 410 has a first terminal that functions as a source electrode and a second terminal that functions as a gate electrode. The third terminal is electrically connected to the second terminal, which functions as a drain electrode, and is connected to the wiring 48. 2. The first terminal of the transistor 410 is electrically connected to the wiring 483. are electrically connected.

[0225] The transistor 412 has a first terminal that functions as a source electrode and a second terminal that functions as a gate electrode. The third terminal is electrically connected to the second terminal, which functions as a drain electrode, and is connected to the wiring 48. 3. The first terminal of the transistor 412 is electrically connected to the wiring 484. are electrically connected.

[0226] The circuit configuration shown in FIG. 16C includes wirings 455, 456, 485, and 486 and transistors. The configuration includes the sensors 414 and 416.

[0227] The transistor 414 has a first terminal that functions as a source electrode and a second terminal that functions as a gate electrode. The third terminal is electrically connected to the second terminal, which functions as a drain electrode, and is connected to the wiring 48. 5. The first terminal of the transistor 414 is electrically connected to the wiring 486. are electrically connected.

[0228] The transistor 416 has a first terminal that functions as a source electrode and a second terminal that functions as a gate electrode. The third terminal is electrically connected to the second terminal, which functions as a drain electrode, and is connected to the wiring 48. The first terminal of the transistor 416 is electrically connected to the wiring 485. are electrically connected.

[0229] The protection circuit 106 that can be used in one embodiment of the present invention is shown in FIGS. It is also possible to use diode-connected transistors as in the circuit configuration shown in

[0230] In addition, in the circuit configurations shown in Figures 16(A), (B), and (C), The first terminal serving as a gate electrode and the second terminal serving as a gate electrode are connected in the configuration shown in FIG. By doing so, it becomes possible to arbitrarily control the resistivity.

[0231] FIG. 17A shows a resistive element that can be used as the protection circuit 106. 17A includes a conductive layer 204e formed on a substrate 202 and a 202 and the conductive layer 204e, insulating layers 206 and 208 are formed on the insulating layer 208. and a conductive layer 212i electrically connected to the semiconductor layer 210d. , the insulating layer 208, the semiconductor layer 210d, and the insulating layer 214, 21 formed on the conductive layer 212i. 6, 218, and formed on the insulating layer 218, electrically connecting the semiconductor layer 210d and the conductive layer 204e. and a conductive layer 220f for connecting to the

[0232] FIG. 17(B) shows a resistor element that can be used as the protection circuit 106. 17B includes a conductive layer 204e formed on the substrate 202 and a 202 and the conductive layer 204e, insulating layers 206 and 208 are formed on the insulating layer 208. The insulating layer 208, the semiconductor layer 210d, and the conductive layer 212j are formed. and insulating layers 214, 216, and 218 formed on the conductive layer 212j, and A conductive layer 220g is formed to electrically connect the conductive layer 212j and the semiconductor layer 210d. and a conductive layer 204e formed on the insulating layer 218, electrically connecting the conductive layer 204e and the semiconductor layer 210d. and a conductive layer 220h.

[0233] FIG. 17C shows a resistor element that can be used as the protection circuit 106. 17C includes a conductive layer 204e formed on the substrate 202 and a 202 and the conductive layer 204e, insulating layers 206 and 208 are formed on the insulating layer 208. The semiconductor layer 210d is formed on the conductive layer 212j, and the conductive layer 212j is electrically connected to the semiconductor layer 210d. The conductive layer 212k, the insulating layer 208, the semiconductor layer 210d, the conductive layer 212j, and the conductive layer 21 Insulating layers 214, 216, and 218 formed on the 2k layer, and a conductive layer formed on the insulating layer 218. a conductive layer 220i that electrically connects the insulating layer 212j and the semiconductor layer 210d; 8, and electrically connects the conductive layer 212k and the conductive layer 204e. 0j and

[0234] The semiconductor layers 210c and 210d used in the resistance element described with reference to FIGS. 15 to 17 are the same as those used in the previous embodiment. The materials described for the semiconductor layers 210a and 210b in the embodiments can be used. The semiconductor layers 210c and 210d are formed in the same process as the semiconductor layers 210a and 210b. It can be formed by

[0235] 15 to 17. The conductive layers 212g, 212h, and 21 212i, 212j, and 212k are the conductive layers 212a, 212b, and 212k shown in the previous embodiment. Materials described in 212c, 212d, 212e, and 212f can be used. The conductive layers 212g and 212h are the conductive layers 212a, 212b, 212c, 212d, and 212 They can be formed in the same process as the formation of 212e and 212f.

[0236] 15 to 17. The conductive layers 220d, 220e, and 22 0f, 220g, 220h, 220i, and 220j are the conductive layers 220 shown in the previous embodiment. The materials described in 220a, 220b, and 220c can be used. 220d and 220e are formed in the same process as the formation of the conductive layers 220a, 220b, and 220c. It is possible.

[0237] In this way, the conductive layer used in the protection circuit functions as the gate electrode of the transistor. and a conductive layer functioning as a source electrode and a drain electrode of a transistor. For example, the configuration of the protection circuit 106 shown in FIG. 17B can be expressed as follows: It can be expressed as follows:

[0238] The protection circuit 106 shown in FIG. 17(B) is a first conductive layer formed on the same surface as the gate electrode. a first insulating layer (insulating layer 204e) on the first conductive layer (conductive layer 204e); 206, 208) and a first conductive layer formed on the first insulating layer (insulating layer 206, 208). an oxide semiconductor layer (semiconductor layer 210d) at a position overlapping with the conductive layer (conductive layer 204e); a second insulating layer (insulating layers 214, 216, 218) on the semiconductor layer (semiconductor layer 210d); A second conductive layer (conductive layer 220g, 220g) on ​​the second insulating layer (insulating layers 214, 216, 218) 20h), and the second conductive layer (conductive layers 220g, 220h) is a second insulating layer (insulating layer In the openings provided in the edge layers 214, 216, and 218, the oxide semiconductor layer (semiconductor layer 210d).

[0239] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. do.

[0240] (Embodiment 7) In this embodiment, the pixel portion 102 of the display device shown in FIG. 1A of Embodiment 1 The structure of a transistor that can be used in the driver circuit portion 104 will be described with reference to FIG. The following explanation will be given.

[0241] The transistor shown in FIG. 18A includes a conductive layer 204c formed over a substrate 202 and a Insulating layers 206 and 208 are formed on the plate 202 and the conductive layer 204c, and on the insulating layer 208 The oxide stack 211 formed, the insulating layer 208 and the conductive layer formed on the oxide stack 211 The transistor shown in FIG. On the transistor, more specifically, the insulating layer 208, the oxide stack 211, and the conductive layer 212d, 2 The structure may include insulating layers 214, 216, and 218 formed on 12e.

[0242] Depending on the type of conductive film used for the conductive layers 212d and 212e, the oxide stack 211 The oxide layer 211 is then doped with oxygen or a mixed layer is formed, forming an n-type region 209 in the oxide stack 211. In FIG. 18A, the n-type region 209 is formed in the oxide stack 211. The n-type region 20 may be formed in the region near the interface where the n-type region 20 is in contact with the conductive layers 212d and 212e. 9 can function as a source region and a drain region.

[0243] In addition, in the transistor illustrated in FIG. 18A, the conductive layer 204c functions as a gate electrode. The conductive layer 212d functions as a source electrode or a drain electrode, and the conductive layer 212e functions as a source electrode or a drain electrode. It functions as a source electrode or a drain electrode.

[0244] In addition, in the transistor illustrated in FIG. 18A, the oxide film in the region overlapping with the conductive layer 204c is The distance between the conductive layer 212d and the conductive layer 212e of the layer 211 is called the channel length. The oxide stack 211 includes a conductive layer 204c and a conductive layer 218b. The channel is a region sandwiched between the conductive layer 212d and the conductive layer 212e. In this case, the region through which current mainly flows.

[0245] Here, the oxide stack 211 will be described in detail with reference to FIG.

[0246] FIG. 18B is an enlarged view of the region surrounded by the dashed line in the oxide stack 211 shown in FIG. 18A. The oxide stack 211 includes an oxide semiconductor layer 211a and an oxide layer 211b. do.

[0247] The oxide semiconductor layer 211a contains at least indium (In), zinc (Zn), and magnesium (Mg). In-MZ containing metals such as I, Ga, Ge, Y, Zr, Sn, La, Ce or Hf It is preferable that the oxide semiconductor layer 211a includes a layer represented by n-oxide. An oxide semiconductor material that can be used for the semiconductor layers 210a and 210b described in the embodiment, Alternatively, the formation method and the like can be appropriately adopted.

[0248] The oxide layer 211b is composed of one or more elements that constitute the oxide semiconductor layer 211a. The energy of the conduction band minimum is 0.05 eV or more and 0.07 eV or more lower than that of the oxide semiconductor layer 211a. eV or more, 0.1 eV or more, 0.15 eV or more and 2 eV or less, 1 eV or less, 0.5 The gate electrode is an oxide film with a potential of 0.4 eV or less, or close to the vacuum level. When an electric field is applied to the conductive layer 204c, which functions as a gate electrode, the gate of the oxide stack 211 at the bottom of the conduction band A channel is formed in the oxide semiconductor layer 211a, which has low energy. By providing the oxide layer 211b between the semiconductor layer 211a and the insulating layer 214, The channel of the transistor can be formed in the oxide semiconductor layer 211a that is not in contact with the insulating layer 214. In addition, one or more elements constituting the oxide semiconductor layer 211a can be used to form the oxide layer 211b. Therefore, the interface diffusion between the oxide semiconductor layer 211a and the oxide layer 211b is Therefore, the oxide semiconductor layer 211a and the oxide layer 211b are not easily disturbed. In this case, the movement of carriers is not hindered, and the field-effect mobility of the transistor is increased. In addition, an interface state is unlikely to be formed between the oxide semiconductor layer 211a and the oxide layer 211b. If there is an interface state between the oxide semiconductor layer 211a and the oxide layer 211b, the interface A second transistor having a different threshold voltage is formed, and the apparent appearance of the transistor is Therefore, by providing the oxide layer 211b, the threshold voltage may be changed. This can reduce variations in electrical characteristics such as the threshold voltage of the transistor.

[0249] The oxide layer 211b is made of In-M-Zn oxide (Al, Ti, Ga, Ge, Y, Zr , Sn, La, Ce, Hf, or other metal), and Specifically, the oxide layer 211b includes an oxide layer having a high atomic ratio of an oxide semiconductor. The above elements are contained in the layer 211a at a concentration 1.5 times or more, preferably 2 times or more, and more preferably 3 times or more, of the above elements. The oxide layer contains indium at an atomic ratio more than 2 times higher than that of the aforementioned elements. Therefore, it has the function of suppressing the occurrence of oxygen deficiency in the oxide layer. The layer 211b is an oxide layer in which oxygen vacancies are less likely to occur than in the oxide semiconductor layer 211a.

[0250] That is, the oxide semiconductor layer 211a and the oxide layer 211b contain at least indium and zinc. and M (metals such as Al, Ti, Ga, Ge, Y, Zr, Sn, La, Ce, or Hf) When the oxide layer 211b is an In-M-Zn oxide containing In:M:Zn=x1:y1: z1 [atomic ratio], and the oxide semiconductor layer 211a is In:M:Zn=x2:y2:z2 [atomic ratio]. If the ratio is y1 / x1, it is preferable that y1 / x1 is greater than y2 / x2. 1 is 1.5 times or more, preferably 2 times or more, and more preferably 3 times or more than y2 / x2. In this case, in the oxide semiconductor layer 211a, if y2 is equal to or larger than x2, the transistor However, if y2 is three times or more than x2, the electrical characteristics of the transistor will be stabilized. Since the field effect mobility of the transistor decreases, y2 is preferably less than three times x2. Desirable.

[0251] When the oxide semiconductor layer 211a is an In-M-Zn oxide, the number of atoms of In and M is The ratio is preferably 25 atomic % or more of In and less than 75 atomic % of M, Preferably, In is 34 atomic % or more and M is less than 66 atomic %. When the oxide layer 211b is an In-M-Zn oxide, the atomic ratio of In to M is preferably is less than 50 atomic % In, M is 50 atomic % or more, and more preferably In is less than 25 atomic % and M is 75 atomic % or more.

[0252] The oxide semiconductor layer 211a and the oxide layer 211b may contain, for example, indium, zinc, and An oxide semiconductor containing gallium can be used. Specifically, the oxide semiconductor layer 21 1a is an In-Ga-Zn oxide with an atomic ratio of In:Ga:Zn=1:1:1; In-Ga-Zn oxide with an atomic ratio of In:Ga:Zn=3:1:2, or a similar material The oxide layer 211b may be an oxide having a composition of In:Ga:Zn =1:3:2 [atomic ratio] In-Ga-Zn oxide, In:Ga:Zn=1:6:4 [ In-Ga-Zn oxide with In:Ga:Zn=1:9:6 [atomic ratio], An n-Ga-Zn oxide or an oxide having a composition close to that can be used.

[0253] The thickness of the oxide semiconductor layer 211a is 3 nm or more and 200 nm or less, preferably 3 nm or less. The oxide is preferably from 100 nm to 100 nm, more preferably from 3 nm to 50 nm. The thickness of the layer 211b is 3 nm or more and 100 nm or less, preferably 3 nm or more and 50 nm or less. do.

[0254] Next, the band structure of the oxide stack 211 will be described with reference to FIGS. 18(C) and 18(D). do.

[0255] For example, the oxide semiconductor layer 211a is an oxide semiconductor layer having an energy gap of 3.15 eV. n-Ga-Zn oxide is used as the oxide layer 211b, and the energy gap is 3.5 eV. The energy gap is measured by a spectroscopic ellipsometer (H Measurements were taken using an ORIBA JOBIN (YVON UT-300).

[0256] Vacuum level and valence band top energy of the oxide semiconductor layer 211a and the oxide layer 211b The difference (also called ionization potential) was 8 eV and 8.2 eV, respectively. The energy difference between the vacuum level and the top of the valence band is measured by ultraviolet photoelectron spectroscopy (UPS). raviolet Photoelectron Spectroscopy (P Measurements were performed using a VersaProbe (HI).

[0257] Therefore, the vacuum level and the conduction band minimum of the oxide semiconductor layer 211a and the oxide layer 211b are The energy difference (also called electron affinity) was 4.85 eV and 4.7 eV, respectively. Ta.

[0258] FIG. 18C shows a schematic diagram of a part of the band structure of the oxide stack 211. In this example, a silicon oxide film is provided in contact with the oxide stack 211. EcI1 shown in 18(C) indicates the energy of the bottom of the conduction band of the silicon oxide film, and EcS1 indicates the energy of the bottom of the conduction band of the oxide semiconductor layer 211a, and EcS2 indicates the energy of the bottom of the conduction band of the oxide semiconductor layer 211a. b, and EcI2 is the energy of the bottom of the conduction band of the silicon oxide film. In addition, EcI1 corresponds to the insulating layer 208 in FIG. 18(A), and EcI2 corresponds to the insulating layer 214 in FIG.

[0259] As shown in FIG. 18C, in the oxide semiconductor layer 211a and the oxide layer 211b, The energy at the bottom of the conduction band changes smoothly without any barrier. In other words, it changes continuously. This is because the oxide layer 211b has a common structure with the oxide semiconductor layer 211a. oxygen is transferred between the oxide semiconductor layer 211a and the oxide layer 211b. This can be said to be because a mixed layer is formed by the above process.

[0260] As shown in FIG. 18C, the oxide semiconductor layer 211a of the oxide stack 211 serves as a well. In the transistor using the oxide stack 211, the channel region is formed in the oxide semiconductor layer 2. It can be seen that the oxide stack 211 is formed at the bottom of the conduction band of Since the temperature changes continuously, the oxide semiconductor layer 211a and the oxide layer 211b are continuously bonded. It can also be said that this is the case.

[0261] As shown in FIG. 18(C), the oxide layer 211b and the insulating layer 214 are adjacent to each other. Although trap levels due to impurities or defects may be formed in the oxide layer 211b, By this, the oxide semiconductor layer 211a can be separated from the trap levels. However, if the energy difference between EcS1 and EcS2 is small, When electrons are captured in the trap level, the insulating layer boundary A negative charge is generated on the surface, and the threshold voltage of the transistor shifts in the positive direction. Therefore, the energy difference between EcS1 and EcS2 is set to 0.1 eV or more, preferably If the potential is 0.15 eV or more, the fluctuation of the threshold voltage of the transistor is reduced, and a stable voltage is obtained. This is preferable because it has a high thermal conductivity.

[0262] FIG. 18(D) shows a schematic diagram of a part of the band structure of the oxide stack 211, and FIG. 18(C) In this example, a silicon oxide film is in contact with the oxide stack 211. The case where the silicon oxide film is provided will be described. EcS1 represents the energy of the bottom of the conduction band of the oxide semiconductor layer 211a. EcI2 indicates the energy at the bottom of the conduction band of the silicon oxide film. I1 corresponds to the insulating layer 208 in FIG. 18(A), and EcI2 corresponds to the insulating layer 208 in FIG. In this case, it corresponds to the insulating layer 214 .

[0263] In the transistor shown in FIG. 18A, the conductive layers 212d and 212e are oxidized during the formation of the conductive layers 212d and 212e. The upper part of the laminated layer 211, i.e., the oxide layer 211b, may be etched. The upper surface of the oxide semiconductor layer 211a is the oxide semiconductor layer 211b. In some cases, a mixed layer of oxide layer 211a and oxide layer 211b may be formed.

[0264] For example, the oxide semiconductor layer 211a is made of In:Ga:Zn=1:1:1 [atomic ratio]. n-Ga-Zn oxide, or In-Ga with an atomic ratio of In:Ga:Zn=3:1:2 -Zn oxide, and the oxide layer 211b has an atomic ratio of In:Ga:Zn=1:3:2 In-Ga-Zn oxide, or In- with In:Ga:Zn=1:6:4 [atomic ratio] In the case of Ga-Zn oxide, the amount of Ga in the oxide layer 211b is greater than that in the oxide semiconductor layer 211a. Because of the high content, a GaOx layer or an oxide semiconductor layer is formed on the upper surface of the oxide semiconductor layer 211a. A mixed layer containing more Ga than the layer 211a can be formed.

[0265] Therefore, even when the oxide layer 211b is etched, the EcI of EcS1 The energy at the bottom of the conduction band on the 2 side becomes higher, resulting in the band structure shown in Figure 18(D). There are cases where this happens.

[0266] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. do.

[0267] (Embodiment 8) In this embodiment mode, the display device shown in FIG. 1A of Embodiment Mode 1 can be used. The structure of the connection terminal portion will be described below with reference to FIG. The parts having the same functions as those described above are designated by the same reference numerals and hatchings. The detailed description will be omitted.

[0268] The connection terminal portion 103 that can be used in the display device shown in FIG. The insulating layers 206 and 208 are formed on the insulating layer 208, and the conductive layer 212m is formed on the insulating layer 208. and insulating layers 214 and 216 formed on the insulating layer 208. The conductive layer 212m has an opening formed therein, and the opening is connected to the terminal of the FPC 264 through an anisotropic conductive The electrodes are electrically connected via the electrode 262.

[0269] In addition, in the connection terminal portion 103, a seal material 266 is formed on the insulating layer 216. The liquid crystal layer 260 is sealed between the substrate 202 and the substrate 252 by a sealant 266. do.

[0270] The insulating layers 206 and 208 can be made of the materials shown in the previous embodiments.

[0271] The conductive layer 212m is formed on the protection circuit 106 and the drive circuit section 104. They can be formed from the same conductive film as 212a, 212b, and 212c.

[0272] The anisotropic conductive agent 262 is a mixture of thermosetting or thermosetting and photosetting resin with conductive particles. It is a paste or sheet-like material that has been mixed together and hardened. Anisotropic conductive agent 262 The anisotropic conductive agent 262 is a material that exhibits anisotropic conductivity when irradiated with light or subjected to thermocompression bonding. The conductive particles that can be used include, for example, spherical organic resin coated with thin film of gold such as Au, Ni, Co, etc. Metal coated particles can be used.

[0273] As shown in this embodiment, one of the present invention is provided between the connection terminal portion 103 and the drive circuit portion 104. By providing the protection circuit 106, for example, electrostatic discharge when attaching the FPC 264 can be prevented. It is possible to protect the drive circuit unit 104 from overcurrent caused by a fire or the like. As a result, a highly reliable display device can be provided.

[0274] In this specification, the term "display device" refers to an image display device or a light source (including a lighting device). It also refers to modules with connectors, such as FPC or TCP. module with a printed wiring board at the end of the TCP, or a display element with a COG method According to the formula, all modules on which ICs (integrated circuits) are directly mounted are also included in the display device. .

[0275] Note that the structure described in this embodiment mode may be appropriately combined with structures described in other embodiments. It can be used.

[0276] (Embodiment 9) In this embodiment, a touch panel that can be combined with the display device of one embodiment of the present invention is The sensor and the display module will be described with reference to FIGS.

[0277] FIG. 20(A) is an exploded perspective view showing a configuration example of the touch sensor 4500, and FIG. 20(B) is an exploded perspective view showing a configuration example of the touch sensor 4500. 21 is a plan view showing an example of the configuration of the electrodes of the touch sensor 4500. FIG. 4 is a cross-sectional view showing an example of the configuration of a sensor 4500.

[0278] The touch sensor 4500 shown in FIGS. 20A and 20B is provided on a substrate 4910 in the X-axis direction. A plurality of conductive layers 4510 arranged in the Y-axis direction intersecting the X-axis direction. The touch sensor 4500 shown in FIGS. 45, a plan view in which a plurality of conductive layers 4510 are formed and a plan view in which a plurality of conductive layers 4520 are formed are separated. are displayed at a distance.

[0279] 21 shows the conductive layer 4510 and the conductive layer 452 of the touch sensor 4500 shown in FIG. 21 is an equivalent circuit diagram of the crossing portion of the conductive layer 4510 and the conductive layer 45 At the intersection of 20, a capacitance 4540 is formed.

[0280] The conductive layers 4510 and 4520 have a structure in which a plurality of quadrilateral conductive films are connected. The plurality of conductive layers 4510 and the plurality of conductive layers 4520 are formed in a quadrilateral portion of the conductive film. The conductive layer 4510 and the conductive layer 4520 are arranged so as not to overlap each other. In this portion, an insulating film is provided between the conductive layer 4510 and the conductive layer 4520 so that they do not come into contact with each other. There are.

[0281] 22 shows the conductive layer 4510 and the conductive layer 452 of the touch sensor 4500 shown in FIG. 4 is a cross-sectional view illustrating an example of a connection structure with a conductive layer 4510 (conductive layers 4510a, 4 A cross-sectional view of the intersection of 510b, 4510c) and 4520 is shown as an example.

[0282] As shown in FIG. 22, the conductive layer 4510 includes a first conductive layer 4510a and a conductive layer 45 10b, and a second conductive layer 4510c on the insulating layer 4810. The conductive layer 4510a and the conductive layer 4510b are connected by the conductive layer 4510c. The conductive layers 4510 and 4520 and the electrode 47 are formed of the first conductive film. An insulating layer 4820 is formed covering the insulating layer 10. For example, a silicon oxynitride film may be formed. An insulating base film may be formed between the electrodes 4710. The base film may be, for example, an oxide film. A silicon nitride film can be formed.

[0283] The conductive layer 4510 and the conductive layer 4520 are formed using a conductive material that transmits visible light. For example, examples of the conductive material having light-transmitting properties include indium tin oxide containing silicon oxide, Indium tin oxide, zinc oxide, indium zinc oxide, zinc oxide doped with gallium, etc. do.

[0284] The conductive layer 4510a is connected to an electrode 4710. The electrode 4710 is connected to an FPC. The conductive layer 4520 also constitutes a connection terminal. The electrode 4710 can be formed, for example, from a tungsten film.

[0285] An insulating layer 4820 is formed covering the conductive layers 4510, 4520 and the electrode 4710. In order to electrically connect the electrode 4710 to the FPC, an insulating layer 4810 is formed on the electrode 4710. An opening is formed in the insulating layer 4820. A substrate 4920 is provided on the insulating layer 4820. It is attached with adhesive or adhesive film. The touch panel is constructed by attaching the plate 4910 to the color filter substrate of the display panel. It is done.

[0286] Next, a display module in which the display device of one embodiment of the present invention can be used is shown in FIG. 3 will be used for explanation.

[0287] The display module 8000 shown in FIG. 23 includes an upper cover 8001 and a lower cover 8002. Between them, touch panel 8004 connected to FPC8003 and A display panel 8006, a backlight unit 8007, a frame 8009, a printed circuit board It has a board 8010 and a battery 8011.

[0288] The upper cover 8001 and the lower cover 8002 are connected to the touch panel 8004 and the display panel The shape and dimensions can be changed as needed to fit the size of the 8006.

[0289] The touch panel 8004 is a resistive or capacitive touch panel. The display panel 8006 can be used by overlapping it with the opposing substrate (sealing substrate). It is also possible to provide the display panel 8 with a touch panel function. It is also possible to provide an optical sensor in each pixel of 006 to make it an optical touch panel.

[0290] The backlight unit 8007 includes a light source 8008. The light source 8008 is It may be provided at the end of the light unit 8007 and configured to use a light diffusion plate.

[0291] The frame 8009 has a function of protecting the display panel 8006 and also a function of preventing the movement of the printed circuit board 8010. It also functions as an electromagnetic shield to block electromagnetic waves generated by frame operations. The frame 8009 may also function as a heat sink.

[0292] The printed circuit board 8010 includes a power supply circuit, a signal circuit for outputting a video signal and a clock signal. The power supply circuit is provided with a signal processing circuit. Alternatively, the power source may be a battery 8011 provided separately. 1 can be omitted if commercial power is used.

[0293] In addition, the display module 8000 includes components such as a polarizing plate, a retardation plate, and a prism sheet. It may also be provided in addition.

[0294] Note that the structure described in this embodiment mode may be appropriately combined with structures described in other embodiments. It can be used.

[0295] (Embodiment 10) In this embodiment, an example of an electronic device will be described.

[0296] 24(A) to 24(H) and 25(A) to 25(D) are diagrams showing electronic devices. These electronic devices are composed of a housing 5000, a display unit 5001, a speaker 5003, an LE D lamp 5004, operation key 5005 (including power switch or operation switch), connection Terminal 5006, sensor 5007 (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance , light, liquid, magnetism, temperature, chemicals, sound, time, hardness, electric field, current, voltage, power, radiation (including functions to measure flow rate, humidity, gradient, vibration, odor or infrared rays), It can have a 5008, etc.

[0297] FIG. 24(A) shows a mobile computer, which includes, in addition to the above, a switch 5009 , an infrared port 5010, etc. FIG. 24(B) shows a portable terminal equipped with a recording medium. A portable image reproducing device (for example, a DVD reproducing device) is also included. The display unit 5002, the recording medium reading unit 5011, etc. It is a group-type display, and in addition to the above, it has a second display unit 5002, a support unit 5012 , earphones 5013, etc. FIG. 24(D) shows a portable gaming machine. In addition to the above, it may have a recording medium reading unit 5011, etc. It is a digital camera with a TV receiving function, and in addition to the above, it also has an antenna 5014, The mobile phone may have a shutter button 5015, an image receiving unit 5016, etc. It is a belt-type gaming machine, and in addition to the above, it has a second display unit 5002, a recording medium reading unit 5011, , etc. FIG. 24(G) shows a television receiver, which, in addition to the above, has It can have a tuner, an image processor, etc. FIG. 24(H) shows a portable television receiver. In addition to the above, it has a charger 5017 capable of transmitting and receiving signals, etc. FIG. 25(A) shows a display, which includes, in addition to the above, a support base 5018, FIG. 25(B) shows a camera, which has external connections in addition to the above. It may have a port 5019, a shutter button 5015, an image receiving unit 5016, etc. FIG. 25(C) shows a computer that, in addition to the above, has a pointing device 5 020, an external connection port 5019, a reader / writer 5021, etc. FIG. 25(D) shows a mobile phone, which in addition to the above-mentioned components includes a transmitting unit, a receiving unit, a mobile phone / transmitter It may have a tuner for one segment partial reception services for mobile terminals, etc.

[0298] The electronic devices shown in FIGS. 24(A) to 24(H) and 25(A) to 25(D) are For example, various information (still images, videos, text images, etc.) can be stored. ) on the display, touch panel function, calendar, date or time display, etc. Functions for controlling processing using various software (programs), wireless communication functions , the ability to connect to various computer networks using wireless communication functions, wireless communication functions A function to send or receive various data using the program recorded on the recording medium. Or, it can have a function of reading out data and displaying it on a display unit. In electronic devices having such a display unit, one display unit is used to mainly display image information, and another display unit is used to A function that mainly displays text information on one display unit, or a function that takes parallax into account on multiple displays By displaying the image, it is possible to have a function of displaying a three-dimensional image. In electronic devices having an image receiving unit, there are functions for taking still images, taking moving images, and Function to automatically or manually correct captured images, and to save captured images to a recording medium (external or camera) It can have functions such as saving the captured image to a camera (built-in), displaying the captured image on the display, etc. In addition, the electronic devices shown in Figures 24(A) to 24(H) and Figures 25(A) to 25(D) The functions that the container can have are not limited to these, and the container can have a variety of functions.

[0299] The electronic device described in this embodiment has a display unit for displaying some information. It is characterized by the following.

[0300] Next, application examples of the display device will be described.

[0301] FIG. 25(E) shows an example in which a display device is integrated with a building. ) includes a housing 5022, a display unit 5023, a remote control device 5024 as an operation unit, and a speaker 5025. 025, etc. The display device is a wall-mounted type that is integrated with the building, and the space to install it is It can be installed without requiring a large space.

[0302] FIG. 25(F) shows another example in which a display device is provided inside a building as an integral part of the building. The display module 5026 is attached to the unit bath 5027. The bather can then view the display module 5026.

[0303] In this embodiment, a wall and a unit bath are used as examples of buildings. The form is not limited to this, and the display device can be installed in various buildings.

[0304] Next, an example in which the display device is provided integrally with a moving object will be described.

[0305] FIG. 25(G) is a diagram showing an example in which the display device is provided in an automobile. The control unit 5028 is attached to the body 5029 of the automobile and controls the operation of the body or the inside and outside of the automobile. It is possible to display information entered from the navigation function on demand. may have

[0306] FIG. 25(H) is a diagram showing an example in which a display device is integrated into a passenger airplane. FIG. 25(H) shows a display module 503 mounted on a ceiling 5030 above the seats of a passenger airplane. 1 is provided. The display module 5031 is a diagram showing the shape of the display module when in use. The ceiling 5030 is attached to the ceiling 5030 via a hinge portion 5032. The expansion and contraction of the display module 503 allows passengers to view the display module 5031. 1 has the function of displaying information when operated by passengers.

[0307] In this embodiment, an automobile body and an airplane body are exemplified as moving bodies. However, this is not limited to motorcycles, four-wheeled vehicles (including cars, buses, etc.), trains (mono It can be installed on a variety of things, including rails, railways, ships, etc.

[0308] In this specification, etc., in a drawing or text described in a certain embodiment, Therefore, it is possible to extract a part of it and use it to constitute an aspect of the invention. If a drawing or text describing a certain part is included, the drawing or text of that part may be omitted. The content of the invention is also disclosed as one aspect of the invention and constitutes one aspect of the invention. Therefore, for example, active elements (transistors, diodes) wires, passive elements (capacitance elements, resistance elements, etc.), conductive layers, insulating layers, semiconductor layers, Drawings in which one or more organic materials, inorganic materials, components, devices, operating methods, manufacturing methods, etc. are described In the drawings or the text, it is possible to extract a part thereof to constitute one aspect of the invention For example, from a circuit diagram composed of N (N is an integer) circuit elements (transistors, capacitor elements, etc.), it is possible to extract M (M is an integer and M < N) circuit elements (transistors, capacitor elements, etc.) to constitute one aspect of the invention. As another example, from a cross-sectional view composed of N (N is an integer) layers, it is possible to extract M (M is an integer and M < N) layers to constitute one aspect of the invention. As yet another example, from a flowchart composed of N (N is an integer) elements, it is possible to extract M (M is an integer and M < N) elements to constitute one aspect of the invention.

[0309] In the present specification, etc., in the drawings or the text described in a certain embodiment, when at least one specific example is described, those skilled in the art can easily derive the upper concept of the specific example. Therefore, when at least one specific example is described in the drawings or the text described in a certain embodiment, the upper concept of the specific example is also disclosed as one aspect of the invention and can constitute one aspect of the invention

[0310] In the present specification, etc., at least the content described in the drawings (even a part in the drawings) is disclosed as one aspect of the invention and can constitute one aspect of the invention. Therefore, for a certain content, if it is described in the drawings, even if it is not described in the text, that content is disclosed as one aspect of the invention and can constitute one aspect of the invention ​​​​​ Similarly, even if a part of the drawings is taken out, it is possible to construct the invention. and can constitute one embodiment of the invention.

[0311] (Embodiment 11) The conductive films and semiconductor films disclosed in the above embodiments can be formed by sputtering or plasma CVD. However, other methods, such as thermal CVD (Chemical Vapor Deposition), can also be used. The MOC method is an example of a thermal CVD method. VD(Metal Organic Chemical Vapor Depositi) The on-coat method or ALD (Atomic Layer Deposition) method may also be used. stomach.

[0312] The thermal CVD method is a film formation method that does not use plasma, so defects are generated by plasma damage. This has the advantage that it will not be

[0313] In the thermal CVD method, the source gas and oxidant are simultaneously fed into the chamber, and the pressure inside the chamber is increased to atmospheric pressure. The film is formed by reacting the material near or on the substrate under reduced pressure and depositing it on the substrate. It is also possible.

[0314] In the ALD method, the chamber is kept at atmospheric pressure or reduced pressure, and the source gases for the reaction are sequentially introduced. Next, the gas is introduced into the chamber, and the film may be formed by repeating this gas introduction sequence. For example, by switching between two or more types of switching valves (also called high-speed valves), The source gases are supplied to the chamber in order, and the first source gas is supplied to the chamber in order to prevent the mixture of the source gases. Inert gas (argon, nitrogen, etc.) is introduced simultaneously with or after the fuel gas. In case of simultaneously introducing an inert gas, the inert gas is The second source gas may be introduced as a carrier gas, and an inert gas may be introduced at the same time as the second source gas is introduced. Also, instead of introducing an inert gas, the first raw material gas is discharged by vacuum evacuation. The first source gas may be adsorbed on the surface of the substrate to form a first layer. The second layer is deposited on the first layer by reacting with the second source gas introduced later. This process is repeated several times while controlling the gas introduction order until a desired thickness is achieved. By doing so, a thin film with excellent step coverage can be formed. The thickness of the thin film is determined by the order of gas introduction. The thickness can be precisely adjusted by changing the number of times the process is repeated. This is suitable for producing thin FETs.

[0315] The thermal CVD method such as the MOCVD method or the ALD method can be used in the above-described embodiments. Conductive films and semiconductor films can be formed. For example, when forming an In-Ga-Zn-O film, In this case, trimethylindium, trimethylgallium, and dimethylzinc are used. The chemical formula for trimethylindium is In(CH3)3. The chemical formula of zinc is Ga(CH3)3, and the chemical formula of dimethylzinc is Zn(CH3 ) 2. The combination is not limited to these, and trimethylgallium may be replaced with trimethylgallium. Ethylgallium (chemical formula Ga(C2H5)3) can also be used, replacing dimethylzinc. Diethylzinc (chemical formula Zn(C2H5)2) can also be used.

[0316] For example, when forming a tungsten film using a film forming device that uses ALD, WF6 gas is used. The initial tungsten film is formed by repeatedly introducing WF6 and B2H6 gases. The tungsten film is formed by simultaneously introducing B2H6 gas and H2 gas. Alternatively, SiH4 gas may be used.

[0317] For example, an oxide semiconductor film, such as In-Ga-Zn-O, can be formed using a film formation device that uses ALD. When forming a film, In(CH3)3 gas and O3 gas are introduced in sequence and repeatedly to form an In- Then, Ga(CH3)3 gas and O3 gas are introduced simultaneously to form a GaO layer. Then, Zn(CH3)2 and O3 gases are introduced simultaneously to form a ZnO layer. The order of these layers is not limited to this example. Also, by mixing these gases, In-Ga-O Alternatively, a mixed compound layer such as an In-Zn-O layer or a Ga-Zn-O layer may be formed. Instead of O3 gas, H2O gas obtained by bubbling with an inert gas such as Ar may be used. However, it is preferable to use O3 gas, which does not contain H. Also, instead of In(CH3)3 gas, In addition, instead of Ga(CH3)3 gas, In(C2H5)3 gas may be used. In(C2H5)3 gas may be used instead of In(CH3)3 gas. 2H5)3 gas may be used, or Zn(CH3)2 gas may be used. [Explanation of symbols]

[0318] 102 Pixel section 103 Connection terminal 104 Drive circuit section 104a Gate Driver 104b Source Driver 106 Protection circuit 106_1 Protection circuit 106_2 Protection circuit 106_3 Protection circuit 106_4 Protection circuit 108 pixel circuit 109 Connection 110 Wiring 112 Wiring 114 Resistor element 130 Liquid crystal element 131_1 Transistor 131_2 Transistor 133_1 Capacitor element 133_2 Capacitor element 134 transistors 135 Light-emitting element 140 PCB 142 Conductive layer 144 Insulating Layer 146 Insulating Layer 148 Conductive Layer 151 transistors 152 transistors 153 Transistor 154 transistors 155 transistors 155A transistor 155B transistor 156 transistors 156A transistor 156B transistor 157 transistors 157A transistor 157B transistor 158 transistors 158A transistor 158B transistor 159 Transistors 160 transistors 161 transistors 162 transistors 163 Transistor 164 transistors 165 transistors 166 transistors 171 Resistor element 172 Resistor element 173 Resistor element 174 Resistor element 174A Resistive Element 174B Resistive element 175 Resistor element 175A resistor element 175B Resistor Element 176 Resistor element 177 Resistor element 178 Resistor element 179 Resistor element 180 Resistor element 181 Wiring 182 Wiring 183 Wiring 184 Wiring 185 Wiring 186 Wiring 187 Wiring 188 Wiring 189 Wiring 190 Wiring 191 Wiring 199 Resistor element 202 Substrate 204a Conductive layer 204b Conductive layer 204c conductive layer 204d conductive layer 204e conductive layer 206 Insulating layer 207a opening 207b opening 208 Insulating layer 209 n-type region 210a Semiconductor layer 210b semiconductor layer 210c Semiconductor layer 210d semiconductor layer 211 Oxide stack 211a Oxide semiconductor layer 211b Oxide layer 212a conductive layer 212b Conductive layer 212c conductive layer 212d conductive layer 212e conductive layer 212f conductive layer 212g conductive layer 212h conductive layer 212i conductive layer 212j conductive layer 212k conductive layer 212m conductive layer 214 Insulating layer 216 Insulating Layer 218 Insulating Layer 219a opening 219b opening 219c opening 220a Conductive layer 220b conductive layer 220c conductive layer 220d conductive layer 220e conductive layer 220f conductive layer 220g conductive layer 220h conductive layer 220i conductive layer 220j conductive layer 252 boards 254 colored layer 256 insulating layer 258 Conductive Layer 260 liquid crystal layer 262 Anisotropic conductive agent 264 FPC 266 Sealing material 268 Liquid Crystal Devices 402 transistor 404 Transistor 406 Transistor 408 Transistor 410 Transistor 412 transistors 414 Transistor 416 Transistor 451 Wiring 452 Wiring 453 Wiring 454 Wiring 455 Wiring 456 Wiring 481 Wiring 482 Wiring 483 Wiring 484 Wiring 485 Wiring 486 Wiring 4500 Touch Sensor 4510 Conductive layer 4510a conductive layer 4510b Conductive layer 4510c conductive layer 4520 Conductive layer 4540 capacity 4710 Electrode 4810 Insulation layer 4820 Insulation layer 4910 board 4920 board 5000 cabinets 5001 Display section 5002 Display section 5003 Speaker 5004 LED lamp 5005 Operation key 5006 Connection terminal 5007 Sensor 5008 Microphone 5009 Switch 5010 Infrared port 5011 Recording medium reading unit 5012 Support part 5013 Earphones 5014 Antenna 5015 Shutter button 5016 Image receiving unit 5017 charger 5018 Support stand 5019 External connection port 5020 pointing device 5021 Reader / Writer 5022 Housing 5023 Display section 5024 Remote control device 5025 Speaker 5026 Display Module 5027 Unit bath 5028 Display Module 5029 Car Body 5030 Ceiling 5031 Display Module 5032 Hinge part 8000 Display Module 8001 Top cover 8002 Lower cover 8003 FPC 8004 Touch Panel 8005 FPC 8006 Display Panel 8007 Backlight Unit 8008 light source 8009 Frame 8010 Printed Circuit Board 8011 Battery

Claims

1. A display device having a pixel portion and a protection circuit, the protection circuit is disposed outside the pixel unit in a plan view; the pixel portion includes a first transistor, a second transistor, and a light-emitting element; a gate of the first transistor electrically connected to a scanning line; one of a source and a drain of the first transistor is electrically connected to a data line; the other of the source and the drain of the first transistor is electrically connected to the gate of the second transistor; one of the source and the drain of the second transistor is electrically connected to a power supply line; the other of the source and the drain of the second transistor is electrically connected to the light-emitting element; the protection circuit includes an oxide semiconductor layer; the oxide semiconductor layer has a first region in contact with a first conductive layer and a second region in contact with a second conductive layer; the first conductive layer is electrically connected to the data line; the second conductive layer is electrically connected to the power supply line; The display device, wherein the oxide semiconductor layer has a meandering shape in plan view.

2. A display device having a pixel portion, a protection circuit, and a driver circuit, the protection circuit is disposed in a region between the pixel unit and the drive circuit in a plan view; the pixel portion includes a first transistor, a second transistor, and a light-emitting element; a gate of the first transistor electrically connected to a scanning line; one of a source and a drain of the first transistor is electrically connected to a data line; the other of the source and the drain of the first transistor is electrically connected to the gate of the second transistor; one of the source and the drain of the second transistor is electrically connected to a power supply line; the other of the source and the drain of the second transistor is electrically connected to the light-emitting element; the drive circuit has a function of outputting a signal to the data line; the protection circuit includes an oxide semiconductor layer; the oxide semiconductor layer has a first region in contact with a first conductive layer and a second region in contact with a second conductive layer; the first conductive layer is electrically connected to the data line; the second conductive layer is electrically connected to the power supply line; The display device, wherein the oxide semiconductor layer has a meandering shape in plan view.

3. In claim 1 or claim 2, The display device, wherein the oxide semiconductor layer contains indium oxide.

Images