Memory system

Abstract

To provide a memory system in which an increase in capacity of a necessary volatile memory is suppressed.SOLUTION: A non-volatile memory comprises a plurality of storage areas. A memory controller counts a first number being the number of requests for a read operation in which the read operation is not completed, out of requests for a read operation on a first storage area that occurred in a first time section. In a second time section following the first time section, the memory controller waits for the first number to become 0 without executing an erase operation on the first storage area while the first number is not 0, and executes the erase operation on the first storage area when the first number becomes 0.SELECTED DRAWING: Figure 10

Description

[Technical Field]

[0001] The present embodiment relates to a memory system. [Background technology]

[0002] In a conventional memory system having a flash memory and a memory controller, the memory controller performs a garbage collection operation. The garbage collection operation copies valid data from one of at least two blocks to another, and places the copy source block in a state where no valid data is stored. The memory controller performs an erase operation on the block that no longer stores valid data, thereby placing the block in a state where new data can be written. The memory controller stores management information for managing the state of each block as described above in a volatile memory, and updates and references the management information in the volatile memory. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2012 / 0284587 [Patent Document 2] US Patent Application Publication No. 2023 / 0273881 [Patent Document 3] US Patent Application Publication No. 2010 / 0235715 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of one embodiment is to provide a memory system in which an increase in the required capacity of volatile memory is suppressed. [Means for solving the problem]

[0005] According to one embodiment, the nonvolatile memory includes a plurality of storage areas, each of which is a unit of a data erase operation. The memory controller is configured to count a first number, which is the number of incomplete read requests among read operation requests generated during a first time interval for one or more first storage areas among the plurality of storage areas, count a second number, which is the number of incomplete read requests among read operation requests generated during a second time interval following the first time interval for one or more second storage areas among the plurality of storage areas, and, while the first number is not zero during the second time interval, wait for the first number to become zero without executing an erase operation on the first storage area, and execute the erase operation on the first storage area in response to the first number becoming zero. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a schematic diagram showing an example of the configuration of a memory system according to a first embodiment. [Figure 2] FIG. 1 is a schematic diagram showing an example of the configuration of a memory chip according to a first embodiment. [Figure 3] FIG. 2 is a schematic diagram showing the circuit configuration of a block according to the first embodiment. [Figure 4] FIG. 2 is a schematic diagram for explaining the state transition of a block according to the first embodiment. [Figure 5] 5A to 5C are schematic diagrams for explaining a garbage collection operation, a third state, and a fourth state according to the first embodiment; [Figure 6] FIG. 2 is a diagram showing an example of the functional configuration of a memory system according to the first embodiment. [Figure 7] 10 is a flowchart showing an example of an operation of the memory system according to the first embodiment when a read command is received. [Figure 8] 6 is a flowchart showing an example of a series of operations related to a read operation to a NAND memory in the memory system according to the first embodiment. [Figure 9]6 is a flowchart showing an example of a garbage collection operation executed by the memory system according to the first embodiment. [Figure 10] FIG. 4 is a diagram for explaining an example of the operation of a block management unit according to the first embodiment. [Figure 11] FIG. 4 is a diagram for explaining a specific example of the operation of a block management unit according to the first embodiment. [Figure 12] 6 is a flowchart showing an example of an erase operation executed by the memory system according to the first embodiment. [Figure 13] FIG. 10 is a diagram for explaining a specific example of the operation of a block management unit according to the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, a memory system according to an embodiment will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to these embodiments.

[0008] (First embodiment) FIG. 1 is a schematic diagram illustrating an example of the configuration of a memory system according to the first embodiment.

[0009] 1, a memory system 1 can be connected to a host 2 via a predetermined communication interface. The host 2 is, for example, a processor, a personal computer, a personal digital assistant, or a server. Various access commands are input to the memory system 1 from the host 2. The various access commands include a write command, a read command, and the like.

[0010] The access command includes a logical address. The memory system 1 provides a logical address space to the host 2. The logical address is address information indicating a location in the logical address space. The host 2 uses the logical address to specify a location to write user data or a location to read user data. In other words, the logical address is location information indicating the access destination.

[0011] The memory system 1 includes a memory controller 11, a NAND type flash memory 12, and a RAM (Random Access Memory) 13. Hereinafter, the flash memory 12 will be referred to as a NAND memory 12.

[0012] The NAND memory 12 is a non-volatile memory that functions as storage. The NAND memory 12 includes one or more memory chips CP. Here, eight memory chips CP0 to CP7 are illustrated as an example of one or more memory chips CP. Multiple memory chips CP may be sealed with resin or the like to form a single package. Here, as an example, memory package 20-0 including memory chips CP0 and CP1, memory package 20-1 including memory chips CP2 and CP3, memory package 20-2 including memory chips CP4 and CP5, and memory package 20-3 including memory chips CP6 and CP7 are illustrated.

[0013] The memory controller 11 and the NAND memory 12 are connected via one or more channels. Here, as an example, the memory system 1 includes two channels CH0 and CH1. The two channels CH0 and CH1 are connected to the memory controller 11. Memory packages 20-0 and 20-1 are connected to channel CH0, and memory packages 20-2 and 20-3 are connected to channel CH1.

[0014] It should be noted that the number of channels, the number of memory chips CP, the number of memory packages 20 included in the memory system 1, and the wiring between the memory controller 11 and each memory chip CP are not limited to this example.

[0015] The memory controller 11 may be configured as a system-on-a-chip (SoC). Alternatively, the memory controller 11 may be configured with multiple chips. Part or all of the memory controller 11 may also be configured as a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC).

[0016] The memory controller 11 executes various processes including data transfer between the host 2 and the NAND memory 12. To achieve this, the memory controller 11 includes a host I / F (Interface) 31, one or more NANDCs (NAND Controllers) 32, and a CPU (Central Processing Unit) 33.

[0017] The host I / F 31 controls the transfer of information such as commands and data to and from the host 2 .

[0018] The CPU 33 realizes the overall control of the memory controller 11 based on a firmware program.

[0019] Based on a request from the CPU 33, the NANDC 32 transfers a command to access the NAND memory 12 via a channel to the target memory chip CP, and transfers data corresponding to the command between the NAND memory 12. Access to the NAND memory 12 includes writing data, reading data, and erasing data.

[0020] 1, the memory controller 11 includes two NANDCs 32-0 and 32-1 as an example of one or more NANDCs 32. NANDC 32-0 controls the transfer of commands and data via channel CH0. NANDC 32-1 controls the transfer of commands and data via channel CH1. The number of NANDCs 32 included in the memory controller 11 is not limited to two.

[0021] The RAM 13 is a volatile memory that provides an area as a buffer or cache to the memory controller 11. For example, the memory controller 11 can use the RAM 13 as a buffer for data transferred between the host 2 and the NAND memory 12, or as an area for temporarily storing various types of management information.

[0022] 1, the RAM 13 is disposed outside the memory controller 11. The RAM 13 may be built into the memory controller 11. The type, number, and location of the RAM 13 provided in the memory system 1 are arbitrary. For example, the RAM 13 may be a dynamic random access memory (DRAM), a static random access memory (SRAM), or a combination thereof. When the RAM 13 is a combination of a DRAM and an SRAM, the SRAM may be built into the memory controller 11, and the DRAM may be disposed outside the memory controller 11.

[0023] 2 is a schematic diagram showing an example of the configuration of a memory chip CP according to Embodiment 1. The memory chip CP includes a peripheral circuit 210 and a memory cell array 211.

[0024] The memory cell array 211 includes a plurality of blocks BLK (BLK0, BLK1, BLK2, ...). Each block BLK includes a plurality of string units SU (SU0, SU1, SU2, ...). Each string unit SU includes a plurality of NAND strings 212. Each NAND string 212 includes a plurality of nonvolatile memory cell transistors connected in series. Note that the number of NAND strings 212 in a string unit SU is arbitrary. The number of memory cell transistors in a NAND string 212 is arbitrary.

[0025] The peripheral circuit 210 includes, for example, a row decoder, a column decoder, a sense amplifier, a latch circuit, and a voltage generating circuit. Upon receiving a command from the memory controller 11, the peripheral circuit 210 executes an operation according to the received command.

[0026] The peripheral circuit 210 can execute a data-in operation, a program operation, a sense operation, a data-out operation, an erase operation, and the like in response to a received command. The data-in operation is an operation of fetching write data input from the memory controller 11 to the memory chip CP into a latch circuit included in the peripheral circuit 210. The program operation is an operation of writing data fetched into the latch circuit by the data-in operation to the memory cell array 211. The sense operation is an operation of transferring data stored in the memory cell array 211 to the latch circuit included in the peripheral circuit 210. The data-out operation is an operation of outputting data stored in the latch circuit to the memory controller 11. The erase operation is an operation of erasing data stored in the memory cell array 211.

[0027] In a write operation, the memory controller 11 causes the peripheral circuit 210 to retrieve the write data into the latch circuit by a data-in operation. After that, the memory controller 11 causes the peripheral circuit 210 to store the write data in the memory cell array 211 by a program operation.

[0028] In a read operation, the memory controller 11 causes the peripheral circuit 210 to transfer the data stored in the memory cell array 211 to the latch circuit by a sense operation. After that, the memory controller 11 causes the peripheral circuit 210 to output the data stored in the latch circuit to the memory controller 11 by a data out operation. Note that if the data to be read is already stored in the latch circuit, the sense operation may be omitted.

[0029] 3 is a schematic diagram showing the circuit configuration of a block BLK according to the first embodiment. Each block BLK has the same configuration. The block BLK has, for example, four string units SU0 to SU3. Each string unit SU includes a plurality of NAND strings 212.

[0030] Each of the NAND strings 212 includes, for example, 64 memory cell transistors MT (MT0 to MT63) and select transistors ST1 and ST2. The memory cell transistors MT have a control gate and a charge storage layer and store data in a non-volatile manner. The 64 memory cell transistors MT (MT0 to MT63) are connected in series between the source of the select transistor ST1 and the drain of the select transistor ST2. The memory cell transistors MT may be of a MONOS (Metal-Oxide-Nitride-Oxide-Silicon) type that uses an insulating film for the charge storage layer, or may be of an FG (Floating Gate) type that uses a conductive film for the charge storage layer. The number of memory cell transistors MT in the NAND string 212 is not limited to 64.

[0031] The gates of the select transistors ST1 included in each of the string units SU0 to SU3 are connected to select gate lines SGD0 to SGD3, respectively. On the other hand, the gates of the select transistors ST2 included in each of the string units SU0 to SU3 are commonly connected to, for example, a select gate line SGS. The gates of the select transistors ST2 included in each of the string units SU0 to SU3 may be connected to select gate lines SGS0 to SGS3 (not shown) that differ for each string unit SU. The control gates of the memory cell transistors MT0 to MT63 included in the same block BLK are commonly connected to word lines WL0 to WL63, respectively.

[0032] The drains of the select transistors ST1 of the NAND strings 212 included in the string units SU are connected to different bit lines BL (BL0 to BL(L-1), where L is a natural number equal to or greater than 2). The bit lines BL commonly connect one NAND string 212 included in each string unit SU across multiple blocks BLK. The sources of the select transistors ST2 are commonly connected to a source line SL.

[0033] That is, a string unit SU is a set of multiple NAND strings 212, each connected to a different bit line BL and connected to the same select gate line SGD. A block BLK is a set of multiple string units SU that share a word line WL. The memory cell array 211 is a set of multiple blocks BLK that share at least one bit line BL.

[0034] The program operation and the sense operation by the peripheral circuit 210 can be performed collectively on the memory cell transistors MT connected to one word line WL in one string unit SU.

[0035] The erase operation by the peripheral circuit 210 is performed in units of blocks BLK, that is, all data stored in one block BLK is erased together.

[0036] Each block BLK is an example of a storage area.

[0037] The configuration of the memory cell array 211 is not limited to the configuration shown in Figures 2 and 3. For example, the memory cell array 211 may have a configuration in which the NAND strings 212 are arranged two-dimensionally or three-dimensionally.

[0038] Next, the state transition of the block BLK will be described.

[0039] FIG. 4 is a schematic diagram for explaining the state transition of the block BLK according to the first embodiment.

[0040] Regarding the notation of each block BLK in Figure 4, the black hatched areas indicate areas where valid data is stored, the dotted hatched areas indicate areas where invalid data is stored, and the white areas indicate areas where no data is stored, i.e., areas where data has been erased by an erase operation.

[0041] The block BLK can be in a first state, a second state, a third state, and a fourth state.

[0042] The first state is a state in which a block BLK (e.g., block BLKa) is set as a storage destination for new data. A block BLK in the first state (e.g., block BLKa) includes an area where no data is stored, and new data received from the memory controller 11 is stored in this area where no data is stored. The data stored in the block BLK in the first state is managed as valid data.

[0043] The second state is a state in which data storage is completed and no new data is stored. The second state is also the state of a block BLK that cannot yet be reused. Reuse refers to transitioning the state of a certain block BLK to the first state.

[0044] For example, when one block BLK's worth of data is stored in a block BLK in the first state, the block BLK transitions from the first state to the second state. Here, the state of the data stored in the block BLK in the second state is either a valid state or an invalid state. Hereinafter, data in a valid state will be referred to as valid data, and data in an invalid state will be referred to as invalid data.

[0045] In a state where certain data (referred to as "first data") is stored in a block BLK (referred to as "first block BLK") in the second state, there may be a case where second data, which is assigned the same logical address value as the first data, is sent from the host 2 to the memory system 1. More specifically, the logical address value assigned to the second data is the same as the logical address value assigned when the first data was sent to the memory system 1. In such a case, the memory controller 11 writes the second data to an area other than the first block BLK where no data of the block BLK in the first state is stored, and invalidates the first data stored in the first block BLK. Therefore, for example, as shown in blocks BLKb to BLKe in FIG. 4, the data stored in each block BLK in the second state may include valid data and invalid data.

[0046] When the memory controller 11 performs a garbage collection operation (also referred to as a GC operation) on a block BLK in the second state, all data stored in that block BLK is invalidated, and the block BLK transitions from the second state to the third state.

[0047] In the third and fourth states, no valid data is stored, as shown in blocks BLKf to BLKi, except that an erase operation cannot be performed on a block BLK in the third state, but an erase operation can be performed on a block BLK in the fourth state.

[0048] The memory controller 11 executes a read operation on the NAND memory 12 in response to a read command from the host 2. More specifically, upon receiving a read command from the host 2, the memory controller 11 identifies a physical address indicating a read position in the NAND memory 12 based on the logical address included in the read command. The physical address is location information assigned to a combination of a memory chip CP, a block BLK, a word line WL, and a location within the word line WL. The memory controller 11 stores a read operation request including the identified physical address in a NAND access queue 42, which will be described later. The memory controller 11 executes a read operation on the NAND memory 12 in accordance with the request stored in the NAND access queue 42.

[0049] Because the read operation is performed according to the data stored in the NAND access queue 42, there is a time lag between the timing when a read operation request is generated in response to a read command from the host 2 and the timing when the requested read operation is actually performed. Therefore, there may be cases where a garbage collection operation for a certain block BLK in the second state (referred to as the second block BLK) is completed even though a read operation for the second block BLK is scheduled. In such cases, an erase operation for the second block BLK is not possible (in other words, prohibited) until the scheduled read operation for the second block BLK is completed.

[0050] That is, the third state is the state of a block BLK for which it has not been confirmed that there is no outstanding read operation, and the fourth state is the state of a block BLK for which it has been confirmed that there is no outstanding read operation.

[0051] When it is confirmed that all planned read operations for a block BLK in the third state have been completed, the block BLK transitions from the third state to the fourth state.

[0052] When an erase operation is performed on a block BLK in the fourth state, the block BLK transitions from the fourth state to the first state.

[0053] 5 is a schematic diagram for explaining the garbage collection operation according to the first embodiment, and the third and fourth states. FIG. 6 is a diagram illustrating an example of the functional configuration of the memory system 1 according to the first embodiment.

[0054] The memory controller 11 functions as a host access control unit 101, a GC control unit 102, and a block management unit 103 through cooperation of some or all of the host I / F 31, the two NANDCs 32, and the CPU 33.

[0055] The RAM 13 is provided with a data buffer 41 and a NAND access queue 42. The RAM 13 also stores an LUT (Lookup table) 43, a first access counter Cn1, and a second access counter Cn2.

[0056] The LUT 43 is information that records the correspondence between logical addresses and physical addresses.

[0057] The NAND access queue 42 is a queue that stores requests for access operations to the NAND memory 12. Of the requests stored in the NAND access queue 42, a request for a read operation is referred to as a read request.

[0058] The host access control unit 101 generates a request to the NAND memory 12 in response to an access command from the host 2, and stores the generated request in the NAND access queue 42. Then, the host access control unit 101 executes an access operation to the NAND memory 12 in accordance with the request stored in the NAND access queue 42.

[0059] When two or more requests are stored in the NAND access queue 42, the order in which the two or more requests are processed may be the same as the order in which the requests were stored in the NAND access queue 42, or may be different.

[0060] In Figure 5, dotted arrows indicate the presence of a read operation scheduled for the block BLK pointed to by the dotted arrow. Solid hatched areas indicate areas where valid data is stored. Dotted hatched areas indicate areas where invalid data is stored. White areas indicate areas where no data is stored, i.e., areas where data has been erased by an erase operation. Diagonally hatched areas indicate areas where a scheduled read operation has not yet been completed.

[0061] In the garbage collection operation, the memory controller 11 copies valid data stored in one or more blocks BLK in the second state (for example, blocks BLKp to BLKr in FIG. 5) to a block BLK in the first state (for example, block BLKt in FIG. 5). The copy source block BLK is referred to as a GC source block BLK or simply as a GC source. The copy destination block BLK is referred to as a GC destination block BLK or simply as a GC destination block BLK.

[0062] When copying of valid data is completed, the memory controller 11 manages the data in the GC destination block BLK copied from the GC source block BLK as valid data, and invalidates the valid data that has been copied in the GC source block BLK. As a result, the GC source block BLK becomes a state in which it does not contain valid data.

[0063] Before the garbage collection operation is completed, a read operation request may be generated by the host access control unit 101, resulting in a read operation request for the GC source block BLK. Of the blocks BLK after the garbage collection operation is completed, blocks BLK for which it has not been confirmed that there are no pending read operations among the requested read requests (for example, blocks BLKq and BLKr in FIG. 5) are managed as the third state. Of the blocks BLK after the garbage collection operation is completed, blocks BLK for which it has been confirmed that there are no pending read operations among the requested read requests (for example, block BLKp in FIG. 5) are managed as the fourth state.

[0064] In this way, even if the garbage collection operation is completed, if there is an uncompleted read operation remaining for the GC source block BLK, the memory controller 11 cannot execute the erase operation for that GC source block BLK. Therefore, the memory controller 11 needs to check whether there is an uncompleted read operation remaining for the GC source block BLK.

[0065] Here, a technique to be compared with the first embodiment will be described. The technique to be compared with the first embodiment will be referred to as a comparative example.

[0066] According to the comparative example, the memory controller includes a counter (referred to as an access counter) for each block, which counts the number of incomplete read operations for the block. That is, the memory controller includes access counters in a number corresponding to the number of blocks included in the NAND memory. A group of these access counters is allocated to a volatile memory, and is updated and referenced on the volatile memory.

[0067] Recent memory systems have a very large number of blocks. Therefore, in the comparative example, the total size of the access counter group is very large. For example, if the access counter group is placed in a volatile memory capable of high-speed operation, such as an SRAM, a large-capacity SRAM is required, increasing the cost of the memory system. Furthermore, if the access counter group is placed in a relatively inexpensive volatile memory, such as a DRAM, the performance of the memory system will deteriorate because access to the DRAM is slower than that of an SRAM.

[0068] In the first embodiment, the memory controller 11 manages two access counters (a first access counter Cn1 and a second access counter Cn2). The memory controller 11 sets a plurality of non-overlapping, consecutive time intervals and counts the number of incomplete read operations among the read operations to the NAND memory 12 that occurred in each of two consecutive time intervals, using a different access counter, either the access counter Cn1 or the access counter Cn2. That is, the memory controller 11 switches between the access counters Cn1 and Cn2 as the access counter that counts the number of incomplete read operations among the read operations corresponding to the read requests generated by the host access control unit 101 in each time interval. The memory controller 11 checks whether any incomplete read operations remain for the GC source block BLK by using these two access counters Cn1 and Cn2. Because only two access counters are required, it is possible to significantly reduce the increase in the capacity of the volatile memory required to store the access counters compared to the comparative example. Details of a method for checking whether any incomplete read operations remain using the two access counters Cn1 and Cn2 will be described later.

[0069] Returning to the explanation of Figure 6, the GC control unit 102 controls the garbage collection operation. Specifically, the GC control unit 102 selects a GC source block BLK and a GC destination block BLK, copies valid data from the GC source block BLK to the GC destination block BLK, invalidates the original data in the GC source block BLK, and validates the copied data in the GC destination block BLK.

[0070] The block management unit 103 manages the state of each block BLK included in the NAND memory 12.

[0071] In particular, the block management unit 103 transitions the block BLK, which is the source of garbage collection and for which the garbage collection operation has been completed, from the third state to the fourth state based on the first access count Cn1 and the second access count Cn2.

[0072] Furthermore, the block management unit 103 transmits an erase command to the memory chip CP having the block BLK in the fourth state, causing the peripheral circuit 210 of the memory chip CP to execute an erase operation on the block BLK in the fourth state. As a result, the block management unit 103 transitions the block BLK from the fourth state to the first state.

[0073] Next, the operation of the memory system 1 will be described.

[0074] FIG. 7 is a flowchart showing an example of the operation of the memory system 1 according to the first embodiment when a read command is received.

[0075] When the memory system 1 receives a read command from the host 2 (S101), the host access control unit 101 refers to the LUT 43 to identify a physical address corresponding to the logical address included in the read command (S102).

[0076] The host access control unit 101 generates a read request including the identified physical address (S103), and stores the generated read request in the NAND access queue 42 (S104). Then, the operation upon receiving the read request is completed.

[0077] The host access control unit 101 executes the operations of steps S102 to S104 every time a read command is received from the host 2.

[0078] FIG. 8 is a flowchart showing an example of a series of operations related to a read operation to the NAND memory 12 in the memory system 1 according to the first embodiment.

[0079] The host access control unit 101 monitors the NAND access queue 42. If an unprocessed read request is stored in the NAND access queue 42, the host access control unit 101 acquires the read request from the NAND access queue 42 (S201).

[0080] The host access control unit 101 executes a read operation in accordance with the acquired read request (S202). In step S202, the host access control unit 101 acquires the physical address included in the read request and sends a command instructing a data-out operation, or a sense operation and a data-out operation, to the memory chip CP that includes the location indicated by the acquired physical address. When the host access control unit 101 acquires read data from the memory chip CP through the data-out operation, it stores the read data in the data buffer 41 of the RAM 13.

[0081] When the host access control unit 101 completes the read operation, it deletes the read request that caused the execution of the read operation, that is, the read request acquired in step S201, from the NAND access queue 42 (S203).

[0082] The host access control unit 101 transmits the read data acquired by the read operation and stored in the data buffer 41 to the host 2 at the appropriate time (S204), and the series of operations related to the read operation is then completed.

[0083] The host access control unit 101 repeatedly executes steps S201 to S204 until there are no pending read operations scheduled in the NAND access queue 42.

[0084] FIG. 9 is a flowchart showing an example of a garbage collection operation executed by the memory system 1 according to the first embodiment.

[0085] The GC control unit 102 selects one or more blocks BLK from the blocks BLK in the second state as blocks BLK to be GC-sourced (S301). For example, the GC control unit 102 selects blocks BLK that store a relatively small amount of valid data as blocks BLK to be GC-sourced. Note that the method for selecting blocks BLK to be GC-sourced is not limited to this.

[0086] The GC control unit 102 selects the block BLK in the first state as the block BLK to be GC-targeted (S302).

[0087] The GC control unit 102 copies valid data from one or more GC source blocks BLK to the GC destination blocks BLK (S303). The GC control unit 102 copies all valid data stored in one or more GC source blocks BLK to the GC destination blocks BLK.

[0088] In response to the copy, the GC control unit 102 updates the LUT 43 (S304). The GC control unit 102 changes the physical address corresponding to the logical address value indicating the location of the copied data from the physical address value indicating the storage location of the original data in the GC source block BLK to the physical address value indicating the storage location of the copied data in the GC destination block BLK. As a result, all data stored in one or more GC source blocks BLK is invalidated, and the copied data in the GC destination block BLK is validated.

[0089] Upon completion of the process in step S304, the garbage collection operation is completed.

[0090] As can be seen from Figure 9, valid data refers to data stored in a location associated with a logical address by the LUT 43. Invalid data refers to data stored in an area not associated with a logical address by the LUT 43. Valid data is data that may be read by the host 2 later. Invalid data is data that may no longer be read by the host 2.

[0091] After the process of step S304 is completed, the GC source block BLK is no longer associated with a logical address, so no new read requests are generated for the GC source block BLK. However, the generated read requests may include a request for a read operation for the GC source block BLK. Even if the LUT 43 is updated by the process of step S304, the physical address included in the generated read request is not changed. Therefore, even if the data scheduled for the read operation is copied to the GC destination block BLK by a garbage collection operation and the original data in the GC source block BLK is invalidated, the host access control unit 101 can read the invalidated original data stored in the GC source block BLK in accordance with the generated read request, rather than the data copied to the GC destination block BLK.

[0092] For a block BLK in which all stored data has been invalidated by a garbage collection operation, the block management unit 103 uses two access counters Cn1 and Cn2 to control the transition from the third state to the fourth state and to control the erase operation.

[0093] 10 is a diagram illustrating an example of the operation of the block management unit 103 according to the first embodiment. In the description of this diagram, it is assumed that the initial count values ​​of the access counters Cn1 and Cn2 are 0.

[0094] When the startup of the memory system 1 is completed (S401), the block management unit 103 regards time period #1 as starting from the timing (time t0) at which the startup is completed. Then, the block management unit 103 starts counting the number of incomplete read operations in time period #1 using one of the access counters Cn1 and Cn2 (here, the first access counter Cn1).

[0095] The block management unit 103 sets multiple non-overlapping, consecutive time intervals, starting with time interval #1. The block management unit 103 can increment only one of the access counters Cn1 and Cn2 in each of the multiple time intervals, and can decrement both access counters Cn1 and Cn2 regardless of the time interval. The block management unit 103 alternately selects the access counter to be incremented from the access counters Cn1 and Cn2 as each time interval elapses. Here, the block management unit 103 increments the first access counter Cn1 in time interval #1. Note that hereinafter, the access counter incremented in time interval #X may be referred to as the access counter corresponding to time interval #X.

[0096] In time interval #1, the block management unit 103 increments the first access counter Cn1 in response to the generation of a read request by the host access control unit 101 (S402). Note that the host access control unit 101 may store information for identifying the access counter corresponding to each read request (also referred to as first identification information) in, for example, the NAND access queue 42.

[0097] In response to completion of processing of the read request generated in time interval #1, the block management unit 103 decrements the first access counter Cn1 (S403). For example, in response to completion of a data-out operation requested by a read request generated in time interval #1, the block management unit 103 decrements the first access counter Cn1. The block management unit 103 may determine the access counter to be decremented by referring to the first identification information.

[0098] The first access counter Cn1 can be decremented even after time interval #1. When a read request generated in time interval #1 is processed in time interval #2 following time interval #1, the block management unit 103 decrements the first access counter Cn1 in response to the completion of processing of the read request in time interval #2.

[0099] After time t0, the GC control unit 102 repeatedly executes garbage collection operations. The block management unit 103 selects a certain block BLK (referred to as block BLKx) that has entered the third state by a certain garbage collection operation as a target for the erase operation (S404). Note that the block management unit 103 may store information (also referred to as second identification information) for identifying the access counter corresponding to each block BLK in, for example, the RAM 13.

[0100] The trigger condition for selecting the target of the erase operation is not limited to a specific condition. For example, the block management unit 103 may execute the process of step S404 when a certain block BLK transitions from the first state to the second state. Alternatively, the block management unit 103 may execute the process of step S404 when the number of blocks BLK in the fourth state becomes smaller than a predetermined number.

[0101] At the timing (time t1) when the process of step S404 is executed, the block management unit 103 switches the time interval (S405). The block management unit 103 switches the time interval setting from time interval #1 to time interval #2. In other words, the block management unit 103 switches the access counter that is incremented in response to the occurrence of a read request from the first access counter Cn1 to the second access counter Cn2.

[0102] In time interval #2, the block management unit 103 increments the second access counter Cn2 in response to the generation of a read request by the host access control unit 101 (S406). In response to the completion of processing of the read request generated in time interval #2, the block management unit 103 decrements the second access counter Cn2 (S407).

[0103] The second access counter Cn2 can be decremented even after time interval #2. When a read request generated in time interval #2 is processed in time interval #3 following time interval #2, the block management unit 103 decrements the second access counter Cn2 in response to the completion of processing of the read request in time interval #3.

[0104] At a certain timing (time t2) after time t1, the count value of the first access counter Cn1 becomes 0. Then, the block management unit 103 transitions the block BLKx from the third state to the fourth state (S408). The block management unit 103 may determine the access counter to be checked to transition the block BLKx from the third state to the fourth state by referring to the second identification information.

[0105] The count value of the first access counter Cn1 reaching 0 means that all read requests generated up to time t1 have been processed. All data stored in block BLKx has been invalidated by the garbage collection operation. Therefore, no new read operation requests for block BLKx will be generated after the garbage collection operation is complete. In other words, the count value of the first access counter Cn1 reaching 0 ensures that there are no pending read operations for block BLKx. Therefore, when the count value of the first access counter Cn1 reaches 0, the block management unit 103 considers block BLKx to have entered the fourth state, which is an erasable state.

[0106] The block management unit 103 can perform an erase operation on the block BLKx that has entered the fourth state at any time. As an example, the block management unit 103 performs an erase operation on the block BLKx at time t2 (S409). The erase operation causes the block BLKx to transition from the fourth state to the first state.

[0107] At time t2, the block management unit 103 finishes using the first access counter Cn1, and the first access counter Cn1 becomes available for use.

[0108] Similar to the processing in step S404, the block management unit 103 selects a certain block BLK (referred to as block BLKy) that has entered the third state due to a garbage collection operation performed in time interval #2 or before time interval #2 as the target for the erase operation (S410).

[0109] At the timing (time t3) when the process of step S410 is executed, the block management unit 103 switches the time interval (S411). The block management unit 103 switches the time interval setting from time interval #2 to time interval #3. In other words, the block management unit 103 switches the access counter that is incremented in response to the occurrence of a read request from the second access counter Cn2 to the first access counter Cn1.

[0110] In time interval #3, the block management unit 103 increments the first access counter Cn1 in response to the generation of a read request by the host access control unit 101 (S412). In response to the completion of processing of the read request generated in time interval #3, the block management unit 103 decrements the first access counter Cn1 (S413).

[0111] The first access counter Cn1 can be decremented even after time interval #3. If a read request generated in time interval #3 is processed in time interval #4 following time interval #3, the block management unit 103 decrements the first access counter Cn1 in response to the completion of processing of the read request in time interval #4.

[0112] At some point (time t4) after time t3, the count value of the second access counter Cn2 becomes 0. Then, similar to the process in step S408, the block management unit 103 transitions the block BLKy from the third state to the fourth state (S414). That is, the block BLKy becomes erasable.

[0113] The block management unit 103 can perform an erase operation on the block BLKy that has entered the fourth state at any time. As an example, the block management unit 103 performs an erase operation on the block BLKy at time t4 (S415). The erase operation causes the block BLKy to transition from the fourth state to the first state.

[0114] At time t4, the block management unit 103 finishes using the second access counter Cn2.

[0115] Similar to the processing in steps S404 and S410, the block management unit 103 selects a certain block BLK (referred to as block BLKz) that has entered the third state due to a garbage collection operation performed in time interval #3 or before time interval #3 as the target for the erase operation (S416).

[0116] At the timing when the process of step S416 is executed (time t5), the block management unit 103 switches the time interval (S417). The block management unit 103 switches the time interval setting from time interval #3 to time interval #4. In other words, the block management unit 103 switches the access counter that is incremented in response to the occurrence of a read request from the first access counter Cn1 to the second access counter Cn2.

[0117] At some point (time t6) after time t5, the count value of the first access counter Cn1 becomes 0. Then, similar to the processes in steps S408 and S414, the block management unit 103 transitions the block BLKz from the third state to the fourth state (S418). That is, the block BLKz becomes erasable.

[0118] The block management unit 103 can perform an erase operation on the block BLKz that has entered the fourth state at any time. As an example, the block management unit 103 performs an erase operation on the block BLKz at time t6 (S419). The erase operation causes the block BLKz to transition from the fourth state to the first state.

[0119] In this way, the block management unit 103 performs the following operation in each time interval. That is, the block management unit 103 counts the number of incomplete read requests (referred to as the target number) among requests for read operations to the NAND memory 12 that occurred in one time interval (referred to as the target time interval). The block management unit 103 performs an erase operation on a block BLK that has entered the third state due to a garbage collection operation that was performed in the target time interval or before the target time interval, after the target number becomes 0 after the garbage collection operation is completed.

[0120] The block management unit 103 then counts the number of targets using one of the two access counters Cn1 and Cn2. The block management unit 103 alternately uses the two access counters Cn1 and Cn2 as the time period elapses.

[0121] FIG. 11 is a diagram for explaining a specific example of the operation of the block management unit 103 according to the first embodiment.

[0122] 11, time interval #1 starts at time t10. At time t10, the count values ​​of access counters Cn1 and Cn2 are both 0. The access counter corresponding to time interval #1 is the first access counter Cn1.

[0123] At time t11, read request #1 is generated, at time t12, read request #2 is generated, at time t13, read request #3 is generated, and at time t14, read request #4 is generated. In response to the generation of these read requests, the first access counter Cn1 is incremented, and at time t14, the count value of the first access counter Cn1 becomes 4.

[0124] At time t14, the block management unit 103 selects a block BLK in a third state (referred to as block BLKv) as a target for the erase operation, and switches the time interval (S501). Note that this process corresponds to the processes in steps S404 and S405 shown in FIG. 10.

[0125] Subsequently, read request #5 is generated at time t15, read request #6 is generated at time t16, read request #7 is generated at time t17, and read request #8 is generated at time t18. After time t15, the second access counter Cn2 is incremented in response to the generation of each read request, and at time t18 the count value of the second access counter Cn2 becomes 4.

[0126] Processing of read request #1 is completed at time t17, processing of read request #3 is completed at time t18, and processing of read request #2 is completed at time t19. Read request #1, read request #3, and read request #2 are read requests generated in time interval #1, and when these read requests are generated, the first access counter Cn1, which is the access counter corresponding to time interval #1, is incremented. Therefore, the first access counter Cn1 is decremented in response to the completion of processing of read request #1, read request #3, and read request #2, and the count value of the first access counter Cn1 becomes 1 at time t19.

[0127] Processing of read request #5 is completed at time t20, processing of read request #6 is completed at time t21, and processing of read request #7 is completed at time t22. Read request #5, read request #6, and read request #7 are read requests generated in time interval #2, and when these read requests are generated, the second access counter Cn2, which is the access counter corresponding to time interval #2, is incremented. Therefore, the second access counter Cn2 is decremented in response to the completion of processing of read request #5, read request #6, and read request #7, and the count value of the second access counter Cn2 becomes 1 at time t22.

[0128] At time t23, a read request #9 is generated, and in response to this, the second access counter Cn2 is incremented, and the count value of the second access counter Cn2 becomes two.

[0129] At time t24, the processing of read request #8 is completed, and in response, the second access counter Cn2 is decremented, and the count value of the second access counter Cn2 becomes one.

[0130] At time t25, processing of read request #4 is completed, and accordingly the first access counter Cn1 is decremented, and the count value of the first access counter Cn1 becomes zero.

[0131] When the count value of the first access counter Cn1 reaches 0, the block management unit 103 considers that the block BLKv has transitioned from the third state to the fourth state (S502), and it becomes possible to perform an erase operation on the block BLKv.

[0132] FIG. 12 is a flowchart showing an example of the erase operation of the memory system 1 according to the first embodiment.

[0133] When a trigger condition for selecting a block BLK (also referred to as a target block) to be erased occurs, the block management unit 103 selects a target block from the blocks BLK in the third state and switches the time interval (S701).

[0134] The block management unit 103 checks whether the access count value corresponding to the target block is 0 (S702). In this case, the block management unit 103 may refer to the second identification information.

[0135] If the count value is not 0 (S702: No), the block management unit 103 waits for the count value to become 0.

[0136] If the count value is 0 (S702: Yes), the block management unit 103 manages the target block as a block BLK in the fourth state (S703).

[0137] Thereafter, when a trigger condition for an erase operation occurs, the block management unit 103 executes an erase operation on the block BLK managed as being in the fourth state (S704).

[0138] As described above, according to the first embodiment, in the memory controller 11, the block management unit 103 counts the number of incomplete read requests (referred to as the first number) among requests for read operations to the NAND memory 12 that have occurred in a certain time interval (referred to as the first time interval). The block management unit 103 executes an erase operation on a block BLK that has entered the third state due to a garbage collection operation executed in the first time interval or before the first time interval, after the first number becomes 0 following the completion of the garbage collection operation.

[0139] Since the memory controller 11 is configured to count the number of incomplete read operations for each time interval, the number of access counters can be significantly reduced compared to the comparative example. Therefore, it is possible to significantly suppress an increase in the capacity of the volatile memory (RAM 13 in the first embodiment) required for managing the access counters.

[0140] According to the first embodiment, the number of required access counters is small, so it is possible to arrange the access counters (access counters Cn1, Cn2) in a volatile memory capable of high-speed operation, such as an SRAM, while suppressing increases in costs. By arranging the access counters (access counters Cn1, Cn2) in a volatile memory capable of high-speed operation, the performance of the memory system 1 is improved. Note that the access counters (access counters Cn1, Cn2) may also be arranged in an inexpensive volatile memory, such as a DRAM. Even in such a case, the required capacity of the volatile memory is small, so it is possible to reduce the cost of the memory system 1.

[0141] According to the first embodiment, the memory controller 11 switches the time intervals. In the memory controller 11, the block management unit 103 counts the number of incomplete read requests (referred to as the second number) among requests for read operations to the NAND memory 12 that occurred in a time interval (referred to as the second time interval) subsequent to the first time interval. The block management unit 103 performs an erase operation on a block BLK that has entered the third state due to a garbage collection operation performed in the second time interval or before the second time interval, after the second number becomes 0 after the garbage collection operation is completed.

[0142] Furthermore, according to the first embodiment, in the memory controller 11, the block management unit 103 counts the number of requests for incomplete read operations using two access counters Cn1 and Cn2. Specifically, the two access counters Cn1 and Cn2 are stored in the RAM 13. In the memory controller 11, the block management unit 103 counts the number of requests for incomplete read operations (referred to as the third number) among read operation requests to the NAND memory 12 generated in a time interval (referred to as the third time interval) subsequent to the second time interval. The block management unit 103 performs an erase operation on a block BLK that has entered the third state due to a garbage collection operation performed in the third time interval or before the third time interval after the garbage collection operation is completed and the third number becomes 0. The block management unit 103 counts the first number and the third number using one of the two access counters Cn1 and Cn2. The block management unit 103 counts the second number using the other one of the two access counters Cn1 and Cn2.

[0143] Therefore, simply by providing two access counters Cn1 and Cn2 in the volatile memory (RAM 13 in the first embodiment), it becomes possible to control the transition from the third state to the fourth state for all blocks BLK that the NAND memory 12 has.

[0144] In the first embodiment, two access counters Cn1 and Cn2 are used alternately. The number of access counters provided in the RAM 13 is not limited to two. Three or more access counters may be provided in the RAM 13, and each of the three or more access counters may be used in turn.

[0145] (Second embodiment) In the first embodiment, the block management unit 103 switched the time interval at the timing when the block BLK in the third state was selected as the target of the erase operation. The trigger condition for switching the time interval is not limited to this. In the second embodiment, as another example of the trigger condition for switching the time interval, a technology in which the time interval is switched in response to the completion of a garbage collection operation will be described. The following describes matters that are different from the first embodiment. Explanations of matters that are the same as those in the second embodiment will be omitted or will be explained briefly.

[0146] FIG. 13 is a diagram for explaining a specific example of the operation of the block management unit 103 according to the second embodiment.

[0147] When the startup of the memory system 1 is completed (S601), the block management unit 103 regards time period #1 as starting from the timing (time t30) at which the startup is completed. Then, the block management unit 103 starts counting the number of incomplete read operations in time period #1 using one of the access counters Cn1 and Cn2 (here, the first access counter Cn1).

[0148] In time interval #1, the block management unit 103 increments the first access counter Cn1 in response to the generation of a read request by the host access control unit 101 (S602). In response to the completion of processing of the read request generated in time interval #1, the block management unit 103 decrements the first access counter Cn1 (S603).

[0149] In time interval #1, the GC control unit 102 selects one or more blocks BLK (here, blocks BLK1a, BLK2a, and BLK3a) as blocks BLK to be GC sources, and executes a garbage collection operation (S604). Note that the GC control unit 102 may store information (also referred to as third identification information) for identifying the access counters corresponding to the blocks BLK to be GC sources in, for example, the RAM 13.

[0150] When the garbage collection operation of step S604 is completed (time t31), blocks BLK1a, BLK2a, and BLK3a enter the third state. The block management unit 103 switches the time interval in response to the completion of the garbage collection operation of step S604 (S605). The block management unit 103 switches the time interval setting from time interval #1 to time interval #2, and switches the incremented access counter from the first access counter Cn1 to the second access counter Cn2.

[0151] In time interval #2, the block management unit 103 increments the second access counter Cn2 in response to the generation of a read request by the host access control unit 101 (S606). In response to the completion of processing of the read request generated in time interval #2, the block management unit 103 decrements the second access counter Cn2 (S607).

[0152] In time interval #2, the GC control unit 102 selects one or more blocks BLK (here, blocks BLK1b, BLK2b, and BLK3b) as blocks BLK to be GC-sourced, and executes a garbage collection operation (S608).

[0153] At a certain timing (time t32) after time t31, the count value of the first access counter Cn1 becomes 0. Then, the block management unit 103 transitions the blocks BLK1a, BLK2a, and BLK3a from the third state to the fourth state (S609). The block management unit 103 may determine the access counter to be checked to transition each block BLK from the third state to the fourth state by referring to the third identification information.

[0154] The block management unit 103 can always perform an erase operation on blocks BLK1a, BLK2a, and BLK3a that have entered the fourth state. For example, the block management unit 103 performs an erase operation on some or all of blocks BLK1a, BLK2a, and BLK3a when a block BLK in the first state transitions to the second state. Note that the trigger conditions for the erase operation are not limited to this.

[0155] When the garbage collection operation of step S608 is completed (time t33), blocks BLK1b, BLK2b, and BLK3b enter the third state. The block management unit 103 switches the time interval in response to the completion of the garbage collection operation of step S608 (S610). The block management unit 103 switches the time interval setting from time interval #2 to time interval #3, and switches the incremented access counter from the second access counter Cn2 to the first access counter Cn1.

[0156] In time interval #3, the block management unit 103 increments the first access counter Cn1 in response to the generation of a read request by the host access control unit 101 (S611). In response to the completion of processing of the read request generated in time interval #3, the block management unit 103 decrements the first access counter Cn1 (S612).

[0157] In time interval #3, the GC control unit 102 selects one or more blocks BLK (here, blocks BLK1c, BLK2c, and BLK3c) as blocks BLK to be GC-sourced, and executes a garbage collection operation (S613).

[0158] At some point after time t33 (time t34), the count value of the second access counter Cn2 becomes 0. Then, the block management unit 103 transitions the blocks BLK1b, BLK2b, and BLK3b from the third state to the fourth state (S614). As with the blocks BLK1a, BLK2a, and BLK3a that are in the fourth state, the block management unit 103 can perform an erase operation on the blocks BLK1b, BLK2b, and BLK3b that are in the fourth state at any time.

[0159] When the garbage collection operation of step S613 is completed (time t35), blocks BLK1c, BLK2c, and BLK3c enter the third state. The block management unit 103 switches the time interval in response to the completion of the garbage collection operation of step S613 (S615). The block management unit 103 switches the time interval setting from time interval #3 to time interval #4, and switches the incremented access counter from the first access counter Cn1 to the second access counter Cn2.

[0160] In time interval #4, the block management unit 103 increments the second access counter Cn2 in response to the generation of a read request by the host access control unit 101. In response to the completion of processing of the read request generated in time interval #4, the block management unit 103 decrements the second access counter Cn2.

[0161] At some point after time t35 (time t36), the count value of the first access counter Cn1 becomes 0. Then, the block management unit 103 transitions the blocks BLK1c, BLK2c, and BLK3c from the third state to the fourth state (S616). As with the blocks BLK1a, BLK2a, and BLK3a that are in the fourth state, the block management unit 103 can perform an erase operation on the blocks BLK1c, BLK2c, and BLK3c that are in the fourth state at any time.

[0162] In this way, the block management unit 103 may switch the time interval in response to the completion of the garbage collection operation.

[0163] In the first and second embodiments, the access counters Cn1 and Cn2 count the number of uncompleted read requests for the entire NAND memory 12. In each time interval, the number of uncompleted read requests may be counted in units smaller than the NAND memory 12 and larger than a single block BLK.

[0164] For example, the access counters Cn1 and Cn2 may be provided for each memory chip CP. Alternatively, the access counters Cn1 and Cn2 may be provided for each memory package 20. Alternatively, the access counters Cn1 and Cn2 may be provided for each channel CH.

[0165] In this way, the access counters Cn1 and Cn2 may be provided for each of the plurality of blocks BLK.

[0166] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0167] 1 memory system, 2 host, 11 memory controller, 12 NAND memory, 13 RAM, 20-0, 20-1, 20-2, 20-3 memory package, 31 host I / F, 32, 32-0, 32-1 NANDC, 33 CPU, 41 data buffer, 42 NAND access queue, 43 LUT, 101 host access control unit, 102 GC control unit, 103 block management unit, 210 peripheral circuit, 211 memory cell array, 212 NAND string.

Claims

1. a nonvolatile memory having a plurality of storage areas each of which is a unit of data erase operation; counting a first number, which is the number of requests for incomplete read operations among requests for read operations generated in a first time interval for one or more first storage areas of the plurality of storage areas; counting a second number, which is the number of requests for incomplete read operations, among requests for read operations that have occurred in a second time period subsequent to the first time period for one or more second storage areas among the plurality of storage areas; during the second time period, while the first number is not 0, wait for the first number to become 0 without executing the erase operation on the first storage area, and execute the erase operation on the first storage area in response to the first number becoming 0; a memory controller configured to A memory system comprising:

2. Further comprising a volatile memory; The memory controller further storing a first counter and a second counter in the volatile memory; counting a third number, which is the number of requests for incomplete read operations, among requests for read operations that have occurred in a third time period subsequent to the second time period for one or more third storage areas among the plurality of storage areas; Counting the first number and the third number using the first counter; Counting the second number is performed using the second counter. It was configured as follows:

10. The memory system of claim 1.

3. The memory controller further switching the time period from the first time period to the second time period in response to determining that the first storage area is to be the target for the erase operation during the first time period; It was configured as follows:

10. The memory system of claim 1.

4. The memory controller further performing a garbage collection operation with the first storage area as a copy source during the first time interval; switching the time interval from the first time interval to the second time interval in response to completion of the garbage collection operation; It was configured as follows:

10. The memory system of claim 1.

5. The memory controller In response to receiving a read command from the host, the read command including first address information indicating a location in an address space provided by the memory controller to the host, the memory controller obtains second address information indicating a location in the non-volatile memory corresponding to the first address information, and stores a request for a read operation including the second address information in a queue; reading the data from the location indicated by the second address information in accordance with the request stored in the queue, regardless of whether the data stored at the location indicated by the second address information is valid or invalid; It was configured as follows:

5. The memory system according to claim 1.

Images