Adaptive resolution management using sub-frames

Abstract

To provide adaptive resolution management using sub-frames.SOLUTION: A method includes receiving a bitstream, determining, for a first frame including a first sub-frame and a second sub-frame, a first scaling constant associated with the first sub-frame, determining a second scaling constant associated with the second sub-frame, and reconstructing pixel data of the first frame using the first scaling constant and the second scaling constant, where the first scaling constant and the second scaling constant characterize different values. Related apparatus, systems, techniques and articles are also described.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] (CROSS-REFERENCE TO RELATED APPLICATIONS) This application claims the benefit of priority to U.S. Provisional Patent Application No. 62 / 883,480, filed August 6, 2019, and entitled "ADAPTIVE RESOLUTION MANAGEMENT USING SUB-FRAMES," which is incorporated herein by reference in its entirety.

[0002] The present invention relates generally to the field of video compression, and more particularly to adaptive resolution management using sub-frames. [Background technology]

[0003] A video codec may include electronic circuitry or software that compresses or decompresses digital video. It may convert uncompressed video into a compressed format, or vice versa. In the context of video compression, a device that compresses video (and / or performs some function thereof) may typically be called an encoder, and a device that decompresses video (and / or performs some function thereof) may be called a decoder.

[0004] The format of the compressed data may conform to standard video compression specifications. The compression may be lossy, in that the compressed video may lack some information present in the original video. Consequences of this may include that the decompressed video may have lower quality than the original uncompressed video, because there may be insufficient information to accurately reconstruct the original video.

[0005] There can be a complex relationship between video quality, the amount of data used to represent the video (e.g., determined by bit rate), the complexity of the encoding and decoding algorithms, sensitivity to data loss and errors, ease of editing, random access, end-to-end delay (e.g., latency), and the like.

[0006] Motion compensation may include an approach for predicting a video frame or a portion thereof given a reference frame, such as a previous and / or future frame, by considering the motion of a camera and / or objects in the video. This may be employed in encoding and decoding video data for video compression, for example, in encoding and decoding using the Motion Picture Experts Group (MPEG) Advanced Video Coding (AVC) standard (also referred to as H.264). Motion compensation may describe a picture in terms of the transformation of a reference picture into a current picture. The reference picture may be temporally earlier than the current picture and / or from the future than the current picture. Summary of the Invention [Means for solving the problem]

[0007] In one aspect, a decoder includes circuitry configured to receive a bitstream, and for a first frame including a first subframe and a second subframe, determine a first scaling constant associated with the first subframe, determine a second scaling constant associated with the second subframe, and reconstruct pixel data of the first frame using the first scaling constant and the second scaling constant, wherein the first scaling constant and the second scaling constant characterize different values.

[0008] In another aspect, a method includes receiving a bitstream; for a first frame including a first subframe and a second subframe, determining a first scaling constant associated with the first subframe and a second scaling constant associated with the second subframe; and reconstructing pixel data of the first frame using the first scaling constant and the second scaling constant, wherein the first scaling constant and the second scaling constant characterize different values.

[0009] The details of one or more variations of the subject matter described herein are set forth in the accompanying drawings and the description below. Other features and advantages of the subject matter described herein will be apparent from the description and drawings, and from the claims. The present invention provides, for example, the following. (Item 1) 1. A decoder, the decoder comprising circuitry, the circuitry comprising: receiving a bitstream; For a first frame including a first subframe and a second subframe, determining a first scaling constant associated with the first subframe; determining a second scaling constant associated with the second subframe; reconstructing pixel data of the first frame using the first scaling constant and the second scaling constant, wherein the first scaling constant and the second scaling constant characterize different values; a decoder configured to: (Item 2) Item 1. The decoder of item 1, wherein the first scaling constant includes a vertical scaling component and a horizontal scaling component. (Item 3) 2. The decoder of claim 1, wherein reconstructing pixel data of the first frame includes reconstructing pixel data of the first sub-frame and reconstructing pixel data of a second frame. (Item 4) Item 1 . The decoder of item 1 , wherein the first scaling constant is signaled within the bitstream and the second scaling constant is signaled within the bitstream. (Item 5) Item 5. The decoder of item 4, wherein the first scaling constant is signaled in the bitstream as an index to a predetermined value. (Item 6) 6. The decoder of claim 5, wherein the second scaling constant is signaled in the bitstream using at least a picture parameter. (Item 7) Item 5. The decoder of item 4, wherein the first scaling constant is signaled within a picture parameter set (PPS). (Item 8) Item 5. The system of item 4, wherein the first scaling constant is signaled as a function of a pps_pic_width_in_luma_samples parameter, a pps_scaling_win_right_offset parameter, and a pps_scaling_win_left_offset parameter. (Item 9) Item 10. The system of item 1, wherein the position of the first subframe within the first frame is signaled within a PPS. (Item 10) an entropy decoder processor configured to receive the bitstream and decode the bitstream into quantized coefficients; an inverse quantization and inverse transform processor, the inverse quantization and inverse transform processor configured to process the quantized coefficients including performing inverse discrete cosine; A deblocking filter; A frame buffer and an intra-prediction processor; Item 1. The decoder of item 1, further comprising: (Item 11) 1. A method comprising: receiving a bitstream; For a first frame including a first subframe and a second subframe, determining a first scaling constant associated with the first subframe; determining a second scaling constant associated with the second subframe; reconstructing pixel data of the first frame using the first scaling constant and the second scaling constant, wherein the first scaling constant and the second scaling constant characterize different values; A method comprising: (Item 12) Item 12. The method of item 11, wherein the first scaling constant includes a vertical scaling component and a horizontal scaling component. (Item 13) Item 12. The method of item 11, wherein reconstructing pixel data of the first frame includes reconstructing pixel data of the first sub-frame and reconstructing pixel data of a second frame. (Item 14) Item 12. The method of item 11, wherein the first scaling constant is signaled within the bitstream and the second scaling constant is signaled within the bitstream. (Item 15) Item 15. The method of item 14, wherein the first scaling constant is signaled in the bitstream as an index to a predetermined value. (Item 16) Item 16. The decoder of item 15, wherein the second scaling constant is signaled in the bitstream using at least a picture parameter. (Item 17) Item 15. The decoder of item 14, wherein the first scaling constant is signaled within a picture parameter set (PPS). (Item 18) Item 15. The system of item 14, wherein the first scaling constant is signaled as a function of a pps_pic_width_in_luma_samples parameter, a pps_scaling_win_right_offset parameter, and a pps_scaling_win_left_offset parameter. (Item 19) Item 12. The system of item 11, wherein the position of the first subframe within the first frame is signaled within a PPS. (Item 20) At least one of the receiving, determining, and reconstructing is performed by a decoder, the decoder comprising: an entropy decoder processor configured to receive the bitstream and decode the bitstream into quantized coefficients; an inverse quantization and inverse transform processor, the inverse quantization and inverse transform processor configured to process the quantized coefficients including performing inverse discrete cosine; A deblocking filter; A frame buffer and an intra-prediction processor; Item 12. The method of item 11, comprising: [Brief explanation of the drawings]

[0010] For the purpose of illustrating the invention, the drawings show aspects of one or more embodiments of the invention, it being understood, however, that the invention is not limited to the precise arrangements and instrumentality shown in the drawings.

[0011] [Figure 1]FIG. 1 is a diagram of exemplary reference frames and exemplary predicted frames at various resolution scales. [Figure 2] FIG. 2 is a diagram depicting an example reference frame, an example rescaled reference frame, and an example subsequent block prediction process. [Figure 3] FIG. 3 illustrates several frames and subframes, including subframes with different resolutions. [Figure 4] FIG. 4 is a process flow diagram illustrating an example process according to some implementations of the present subject matter. [Figure 5] FIG. 5 is a system block diagram illustrating an example decoder capable of decoding a bitstream in accordance with some implementations of the present subject matter. [Figure 6] FIG. 6 is a process flow diagram illustrating an exemplary process for encoding video according to some implementations of the present subject matter. [Figure 7] FIG. 7 is a system block diagram illustrating an example video encoder in accordance with some implementations of the present subject matter. [Figure 8] FIG. 8 is a block diagram of a computing system that may be used to implement any one or more of the methodologies disclosed herein and in any one or more portions thereof.

[0012] The drawings are not necessarily to scale and may be illustrated by phantom lines, schematic representations, and partial views. In some instances, details that are not necessary for an understanding of the embodiments or that make other details difficult to perceive may be omitted. Like reference symbols in various drawings indicate like elements. DETAILED DESCRIPTION OF THE INVENTION

[0013] Detailed Description In many current state-of-the-art encoders, resolution is managed by recoding and retransmitting entire portions of video known as groups of pictures (GOPs). This requires transmitting intra-frames (I-frames), which can incur additional cost, since these frames contribute most of the bits within a GOP.

[0014]

[0003] Embodiments described in this disclosure relate to adaptive resolution management (ARM), a technique that enables additional flexibility for video encoders / decoders, enabling bitrate savings in various use cases. Generally, ARM involves performing prediction using reference frames of a different resolution than the current frame. In current coding standards, the reference frames have the same resolution as the predicted frame. In ARM, the reference frames can be of a lower or higher resolution than the frame being predicted. This approach can be used to downscale video resolution, thus reducing bitrate, or upscale video resolution, thus enhancing the display characteristics of video playback.

[0015] ARM may alternatively, or equivalently, be referred to as reference picture resampling (RPR) for purposes of this disclosure, and RPR and ARM may be used synonymously.

[0016] Some implementations of the present subject matter may include using ARM for any number of frames at any position within a GOP, thus eliminating the requirement for recoding I-frames.

[0017] FIG. 1 is a diagram of reference frames and predicted frames of various resolution scales. Frame 1 is smaller (lower resolution) than the reference frame, Frame 2 is the same size (same resolution), while Frame 3 is larger (higher resolution). "Resolution," as used in this disclosure, refers to the number of pixels in a picture, frame, subframe, and / or other displayed area or portion thereof used in video playback, compression, or the like, with a higher number of pixels corresponding to a higher resolution and a lower number of pixels corresponding to a lower resolution. Resolution may be measured in terms of area, for example, but not limited to, by using one or more dimensions, measured in pixels, that define an area. For example, a circular subframe or other region may have a resolution defined according to its radius. Alternatively, or in addition, resolution may be defined by the total number of pixels.

[0018] As an example, with continued reference to FIG. 1 , if the reference frame and / or subframes have a geometric form whose area can be completely defined in terms of two length parameters, such as, but not limited to, a triangle, parallelogram, and / or rectangular form, the reference frame and / or subframes may have a resolution W×H (W and H may indicate the number of pixels describing the width (or base) and height dimensions of the reference frame and / or subframe, respectively). Each predicted frame may also have a resolution that can be determined similarly to the resolution of the reference frame; for example, frame 1 may have a lower resolution WS×HS, frame 2 may have the same resolution as the reference frame W×H, and frame 3 may have a higher resolution WL×HL. The widths and heights of smaller and larger frames may be obtained by multiplying the reference width and height by an arbitrary rescaling constant (Rc), also referred to as a scaling ratio and / or constant. In the case of smaller frames, Rc may have a value between 0 and 1. In the case of larger frames, Rc may have a value greater than 1, for example, Rc may have a value between 1 and 4. Other values ​​are possible. The rescaling constants may differ from one another for one resolution dimension, for example, a rescaling constant Rch may be used to rescale the height, while another rescaling constant Rcw may be used to rescale the width.

[0019] Still referring to FIG. 1, ARM may be implemented as a mode. In the case of ARM mode activation at some point during decoding, the decoder may have already received reference frames at resolution W×H and may rescale predicted frames using a rescaling constant. In some implementations, the encoder may signal to the decoder the rescaling constant to use as a function of picture parameters, such as, for example, the pps_pic_width_in_luma_samples parameter, the pps_scaling_win_right_offset parameter, and / or the pps_scaling_win_left_offset parameter. The signaling may be performed within the sequence parameter set (SPS) corresponding to the GOP containing the current picture and / or the picture parameter set (PPS) corresponding to the current picture. For example, without limitation, an encoder may signal rescaled parameters using fields such as pps_pic_width_in_luma_samples, pps_pic_height_in_luma_samples, pps_scaling_win_left_offset, pps_scaling_win_right_offset, pps_scaling_win_top_offset, pps_scaling_win_bottom_offset, and / or sps_num_subpics_minus1. A parameter such as pps_scaling_window_explicit_signalling_flag equal to 1 may specify that a scaling window offset parameter is present in the PPS, and pps_scaling_window_explicit_signalling_flag equal to 0 may specify that a scaling window offset parameter is not present in the PPS. When sps_ref_pic_resampling_enabled_flag is equal to 0, the value of pps_scaling_window_explicit_signalling_flag may be equal to 0.pps_scaling_win_left_offset, pps_scaling_win_right_offset, pps_scaling_win_top_offset, and pps_scaling_win_bottom_offset may specify offsets to be applied to the picture size for scaling ratio calculation. When not present, the values ​​of pps_scaling_win_left_offset, pps_scaling_win_right_offset, pps_scaling_win_top_offset, and pps_scaling_win_bottom_offset may be inferred to be equal to pps_conf_win_left_offset, pps_conf_win_right_offset, pps_conf_win_top_offset, and pps_conf_win_bottom_offset, respectively.

[0020] 1 , the W and H parameters as described above may be represented using, but not limited to, the variables CurrPicScalWinWidthL and CurrPicScalWinHeightL, respectively, which may be derived from the signaled parameters as described above using one or more mathematical relationships between the signaled parameters and the variables. For example, but not limited to, CurrPicScalWinWidthL may be derived according to the following equation: CurrPicScalWinWidthL = pps_pic_width_in_luma_samples - SubWidthC * (pps_scaling_win_right_offset + pps_scaling_win_left_offset)

[0021] As a further non-limiting example, CurrPicScalWinHeightL may be derived according to the following equation: CurrPicScalWinWidthL = pps_pic_width_in_luma_samples - SubWidthC * (pps_scaling_win_right_offset + pps_scaling_win_left_offset)

[0022] Those skilled in the art will recognize, upon review of this disclosure in its entirety, various alternative calculations that may be used to derive the variables described above. The encoder may alternatively or additionally signal one or more such variables Rc, Rch, and / or Rcw directly within the PPS and / or SPS, for example, but not by way of limitation.

[0023] Alternatively, or in addition, still referring to FIG. 1, a rescaling constant and / or set of rescaling constants as described above may be signaled in the bitstream using a reference to a stored scaling constant and / or multiple scaling constants and / or an index of a frame and / or block that has previously been signaled and / or utilized using a scaling constant and / or multiple scaling constants. The reference to the index of the stored scaling constant may be explicitly signaled and / or determined from one or more additional parameters signaled in the bitstream. For example, without limitation, the decoder may identify a reference frame and / or a group of pictures containing the current frame, and if a rescaling constant has previously been signaled and / or utilized within such group of pictures, with the reference frame being signaled as applicable to the current frame and / or current group of pictures, or the like, the decoder may identify that rescaling constant for use as a rescaling constant with the current frame.

[0024] In some implementations, with continued reference to FIG. 1, ARM operations may be performed according to the block level of an encoded frame. For example, a reference frame may first be rescaled, followed by prediction as depicted in FIG. 2. FIG. 2 is a diagram depicting a reference frame, a rescaled reference frame, and a subsequent block prediction process. The block prediction process may be performed on the scaled reference frame (having a scaled resolution) rather than the original reference frame. Rescaling the reference frame may include rescaling according to any parameters signaled by the encoder, as described above; for example, but not limited to, if a reference frame to be used with the current picture is signaled via a reference to an index value associated with the reference frame or the like, the signaled reference frame may be rescaled according to any of the rescaling methods described above prior to prediction. The rescaled reference frames may be stored in memory and / or buffers, which may include, but are not limited to, a buffer that identifies the frame contained therein by an index, according to a frame retrieval that may be performed, and which may include a decoded picture buffer (DCB) and / or one or more additional buffers implemented by the decoder. The prediction process may include, for example, inter-picture prediction, including motion compensation.

[0025] Some implementations of block-based ARM may allow the flexibility of applying an optimal filter per block instead of applying the same filter across the entire frame. In some implementations, skip ARM mode may be considered a possibility, such that some blocks (e.g., based on uniformity of pixel and bitrate cost) may be in skip ARM mode (such that rescaling would not change the bitrate). Skip ARM mode may be signaled within the bitstream, for example, but not by way of limitation, skip ARM mode may be signaled within the PPS parameters. Alternatively, or in addition, the decoder may determine that skip ARM mode is active based on one or more parameters set by the decoder and / or signaled within the bitstream. Spatial filters used within block-based ARMs may include, but are not limited to, bicubic spatial filters that apply bicubic interpolation, bilinear spatial filters that apply bilinear interpolation, Lanczos filters that use Lanczos filtering, and / or sinc filters, sinc function interpolation, and / or Lanczos resampling that uses a combination of signal reconstruction techniques, or the like; those skilled in the art will recognize various filters that may be used consistently with this disclosure for interpolation upon review of the entire disclosure. Interpolation filters may include, by way of non-limiting example, any of the filters described above, such as, but not limited to, low-pass filters that may be used with an upsampling process whereby pixels between pixels of a previous block and / or frame of scaling may be initialized to zero and then the output of a low-pass filter may be taken. Alternatively, or in addition, any luma sample interpolation filtering process may be used. Luma sample interpolation may include calculating an interpolated value at a half-sample interpolation filter index that falls between two consecutive sample values ​​of an unscaled sample array.Calculation of the interpolated values ​​may be performed, without limitation, by reading coefficients and / or weights from a lookup table, with the selection of the lookup table being performed as a function of the coding unit and / or motion model of the scaling ratio, for example, as determined using the scaling constants as described above. The calculation may include, without limitation, performing a weighted sum of adjacent pixel values, where the weights are read from a lookup table. Alternatively or additionally, the calculated values ​​may be shifted, for example, without limitation, by a minimum value (4, i.e., bit depth minus 8), 6, a maximum value (2, i.e., 14-bit depth), or the like. Those skilled in the art will recognize various alternative or additional implementations that may be used for the interpolation filters upon review of the entirety of this disclosure.

[0026] In some implementations, compression efficiency may be improved by encoding sub-frames of a video frame at a lower resolution. A sub-frame, for purposes of this disclosure, is defined as a region of a frame, each of which does not contain all of the pixels of the entire frame. A region may include one or more blocks as described in this disclosure, and the one or more blocks and / or regions may have any suitable shape, including, but not limited to, a rectangular shape. A sub-frame may be coded as a tile, slice, and / or region of a frame, by way of non-limiting example. A sub-frame may include non-overlapping regions of a frame that together form a frame. Figure 3 illustrates an example embodiment of several frames and sub-frames, including sub-frames with different resolutions.

[0027] At 304, a single frame i is illustrated. Tile numbers and positions within frame i may be signaled in the picture header. In an embodiment, the signaling may be explicit, or alternatively, or in addition, the PPS may signal tile rows, columns, row heights, and / or column widths, any or all of which may be combined and / or utilized by a decoder to determine the count and / or number of tiles. For example, without limitation, a PPS parameter, denoted pps_num_exp_tile_columns_minus1, when added with 1, may explicitly specify the number of column widths of the provided tiles. As a further non-limiting example, the parameter pps_tile_column_width_minus1[i], when added with 1, may specify the width of the ith tile column, e.g., in units of coding tree blocks (CTBs), for i in the range 0 to pps_num_exp_tile_columns_minus1, inclusive. The parameter pps_tile_row_height_minus1[i] plus 1, when added with 1, may specify the height of the i-th tile row, e.g., in units of CTBs, with respect to i. The signaled parameters may alternatively or additionally specify the number and / or dimensions of slices in one or more tiles. For example, a parameter denoted pps_num_exp_slices_in_tile[i] may specify the number of slice heights explicitly provided for slices in the tile containing the i-th slice. A parameter denoted pps_slice_width_in_tiles_minus1[i], when added with 1, may specify the width of the i-th rectangular slice in units of tile rows. A parameter denoted pps_slice_height_in_tiles_minus1[i], when added with 1, may specify the height of the i-th rectangular slice in units of tile rows, e.g., when pps_num_exp_slices_in_tile[i] is equal to 0.Those skilled in the art will recognize, upon review of this disclosure in its entirety, various alternative or additional ways in which tile and / or slice parameters may be signaled and / or determined, whether implicitly or explicitly, in or from the bitstream and / or header parameters.

[0028] 3, a frame may be divided into two or more subframes. The subframes may be identified and / or signaled as one or more tiles and / or slices as described above, including but not limited to, by specification of the tiles and / or slices included within a given subframe. At 308, frame i is shown divided into two subframes (subframe 0 and subframe 1).

[0029] In some implementations, still referring to FIG. 3, the encoder may determine whether any subframes should be encoded at a rescaled resolution. The subframes may be scaled using a rescaling constant Rc. In an embodiment, without limitation, a horizontal scaling constant Rch may be applied in the horizontal dimension, and a vertical scaling constant Rcv may be applied in the vertical dimension. Rc<1 can be used to reduce the data to be encoded, thereby reducing the bit rate of the encoded video. FIG. 3 illustrates an example in which subframe 1 is rescaled to half horizontal resolution (Rch=0.5) at 312. The scaling factors Rch and Rcv may be signaled to the decoder. When Rch=Rcv, only one value is signaled to the receiver.

[0030] Still referring to FIG. 3, each subframe (subframe 0 and rescaled subframe 1) may then be divided into blocks and encoded using an available encoding algorithm. Motion compensated transform coding may be applied to the subframes. The encoded subframes may be received by a decoder for decoding. The decoded subframes at the receiver may be rescaled to the original resolution. The fully reconstructed frame may then be used for display purposes. FIG. 3 illustrates, at 316, a non-limiting example of a decoded frame i, i.e., frame i * , which may have subframe 0 at full resolution and subframe 1 at a lower resolution at the receiver. At 320, subframe 1 is shown as being rescaled to full resolution before being used for display or for use as a reference frame for illustrative purposes.

[0031] FIG. 3 illustrates additional non-limiting examples of subframe configurations at 324 and 328, for example, without limitation, there may be three or more subframes, each of which may be rescaled differently and each of which may be signaled according to any process and / or parameters for such signaling as described in this disclosure. In an embodiment, some subframes may increase in area, length, width, and / or other dimensions as a result of rescaling, while others may decrease in area, length, width, and / or other dimensions, which may allow, for example, one portion of a frame to increase in size while another portion decreases in size, such that the dimensions of the entire frame may remain the same. Alternatively, one or more subframes that increase in size may overlap and / or occlude one or more other subframes. Spatial resolution may change within a sequence, in which case only regions of previously coded frames may be present in the current frame. FIG. 4 is a process flow diagram illustrating an example process 400 of adaptive resolution management that may allow additional flexibility for video encoders and / or decoders, enabling bitrate savings in various use cases.

[0032] At step 405, still referring to FIG. 4, a bitstream is received by the decoder. A current block may be contained within the bitstream received by the decoder. The bitstream may include data found in a stream of bits that is input to the decoder when using data compression, for example. The bitstream may include information necessary to decode the video. Receiving may include extracting and / or parsing the block and associated signaling information from the bitstream. In some implementations, the current block may include, for example, without limitation, a coding tree unit (CTU), a coding unit (CU), and / or a prediction unit (PU), as described in further detail below.

[0033] 4, at step 410, a first scaling constant associated with a first subframe may be determined for a first frame including the first subframe and a second subframe. In some implementations, the first scaling constant may include a vertical scaling component and a horizontal scaling component. The first scaling constant may be signaled within the bitstream, and the second scaling constant may be signaled within the bitstream. In some implementations, the first scaling constant may be signaled within the bitstream as an index to a predetermined value.

[0034] In step 415, and still referring to FIG. 4, a second scaling constant associated with the second subframe may be determined, which may be implemented in any manner suitable for determining a first scaling constant for a first subframe, as described above.

[0035] 4, at step 420, pixel data of the first frame may be reconstructed using a first scaling constant and a second scaling constant. The first scaling constant and the second scaling constant may characterize different values. In some implementations, reconstructing the pixel data of the first frame includes reconstructing pixel data of the first sub-frame and reconstructing pixel data of the second sub-frame.

[0036] 5 is a system block diagram illustrating an example decoder 500 capable of decoding a bitstream using global motion vector-based fusion candidate reordering. The decoder 500 may include an entropy decoder processor 504, an inverse quantization and inverse transform processor 508, a deblocking filter 512, a frame buffer 516, a motion compensation processor 520, and / or an intra-prediction processor 524.

[0037] In operation, still referring to FIG. 5, a bitstream 528 may be received by the decoder 500 and input to the entropy decoder processor 504, which may entropy decode a portion of the bitstream into quantized coefficients. The quantized coefficients may be provided to the inverse quantization and inverse transform processor 508, which may perform inverse quantization and inverse transform and generate a residual signal, which may be added to the output of the motion compensation processor 520 or the intra-prediction processor 524, depending on the processing mode. The output of the motion compensation processor 520 and the intra-prediction processor 524 may include a block prediction based on previously decoded blocks. The prediction and residual sum may be processed by the deblocking filter 512 and stored in the frame buffer 516.

[0038] 6 is a process flow diagram illustrating an example embodiment of a process 600 for encoding video using adaptive resolution management, which may allow additional flexibility for a video encoder and / or decoder, enabling bitrate savings in various use cases. In step 605, a video frame may undergo initial block segmentation using, for example, a tree-structured macroblock partitioning scheme, which may include partitioning the picture frame into CTUs and / or CUs.

[0039] In step 610, still referring to FIG. 6, block-based adaptive resolution management may be performed, including, for example but not limited to, resolution scaling of a frame or portion thereof, as described above.

[0040] At step 615, and with further reference to Figure 6, the block may be encoded and included in the bitstream. Encoding may include, for example, utilizing inter-prediction and intra-prediction modes.

[0041] 7 is a system block diagram illustrating an example video encoder 700 capable of encoding video using a reordering of fusion candidates based on global motion vectors. The example video encoder 700 may receive input video 704, which may first be segmented or divided according to a processing scheme such as a tree-structured macroblock partitioning scheme (e.g., quadtree + binary tree). An example of a tree-structured macroblock partitioning scheme may include partitioning a picture frame into large block elements called coding tree units (CTUs). In some implementations, each CTU may be further partitioned one or more times into several sub-blocks, called coding units (CUs). The final result of this partitioning may include a group of sub-blocks, which may be called a prediction unit (PU). Transform units (TUs) may also be utilized.

[0042] 7, an exemplary video encoder 700 may include an intra-prediction processor 708, a motion estimation / compensation processor 712, which may also be referred to as an inter-prediction processor, which may be capable of building a motion vector candidate list, including adding global motion vector candidates to the motion vector candidate list, a transform / quantization processor 716, an inverse quantization / inverse transform processor 720, an in-loop filter 724, a decoded picture buffer 728, and / or an entropy coding processor 732. Bitstream parameters may be input to the entropy coding processor 732 for inclusion in an output bitstream 736.

[0043] 7, for each block of a frame of the input video 704, it may be determined whether to process the block via intra-picture prediction or using motion estimation / compensation. The block may be provided to an intra-prediction processor 708 or a motion estimation / compensation processor 712. If the block is to be processed via intra-prediction, the intra-prediction processor 708 may perform processing and output a predictor. If the block is to be processed via motion estimation / compensation, the motion estimation / compensation processor 712 may perform processing, including building a motion vector candidate list, including adding global motion vector candidates to the motion vector candidate list, if applicable.

[0044] Continuing with reference to FIG. 7, a residual may be formed by subtracting the predictor from the input video. The residual may be received by a transform / quantization processor 716, which may perform a transform operation (e.g., a discrete cosine transform (DCT)) to produce coefficients, which may be quantized. The quantized coefficients and any associated signaling information may be provided to an entropy coding processor 732 for entropy encoding and inclusion in an output bitstream 736. The entropy encoding processor 732 may assist in encoding signaling information related to encoding the current block. Additionally, the quantized coefficients may be combined with the predictor and provided to an inverse quantization / inverse transform processor 720, which may reconstruct pixels that may be processed by an in-loop filter 724, the output of which may be stored in a decoded picture buffer 728 for use by the motion estimation / compensation processor 712, which may build a motion vector candidate list, including adding global motion vector candidates to the motion vector candidate list.

[0045] 7, several variations have been described in detail above, but other modifications or additions are also possible. For example, in some implementations, the current block may include any symmetric block (8x8, 16x16, 32x32, 64x64, 128x128, and the like) and any asymmetric block (8x4, 16x8, and the like).

[0046] In some implementations, still referring to FIG. 7, a quadtree plus binary decision tree (QTBT) may be implemented. In QTBT, at the coding tree unit level, partition parameters of the QTBT may be dynamically derived to adapt to local characteristics without transmitting any overhead. Subsequently, at the coding unit level, a joint classifier decision tree structure may eliminate unnecessary iterations and control the risk of erroneous predictions. In some implementations, an LTR frame block update mode may be available as an additional option available per leaf node of the QTBT.

[0047] In some implementations, still referring to Figure 7, additional syntax elements may be signaled at different hierarchical levels of the bitstream. For example, a flag may be enabled throughout a sequence by including an enabled flag coded in a sequence parameter set (SPS). Furthermore, a CTU flag may be coded at the coding tree unit (CTU) level.

[0048] Some embodiments may include a non-transitory computer program product (i.e., a physically embodied computer program product) storing instructions that, when executed by one or more data processors of one or more computing systems, cause at least one data processor to perform the operations herein.

[0049] Embodiments disclosed herein may include a decoder having circuitry configured to receive a bitstream, and for a first frame including a first subframe and a second subframe, determine a first scaling constant associated with the first subframe, determine a second scaling constant associated with the second subframe, and reconstruct pixel data of the first frame using the first scaling constant and the second scaling constant, wherein the first scaling constant and the second scaling constant characterize different values.

[0050] In some embodiments, the first scaling constant may include a vertical scaling component and a horizontal scaling component. Reconstructing pixel data of the first frame may include reconstructing pixel data of the first subframe and reconstructing pixel data of the second frame. The first scaling constant may be signaled in the bitstream, and the second scaling constant may be signaled in the bitstream. The first scaling constant may be signaled in the bitstream as an index to a predetermined value. The second scaling constant may be signaled in the bitstream using at least picture parameters. The first scaling constant may be signaled in a picture parameter set (PPS). The first scaling constant may be signaled as a function of a pps_pic_width_in_luma_samples parameter, a pps_scaling_win_right_offset parameter, and a pps_scaling_win_left_offset parameter. A position of the first subframe within the first frame may be signaled in the PPS. The decoder may include an entropy decoder processor configured to receive a bitstream and decode the bitstream into quantized coefficients, an inverse quantization and inverse transform processor configured to process the quantized coefficients, including performing inverse discrete cosine, a deblocking filter, a frame buffer, and an intra prediction processor.

[0051] In embodiments disclosed herein, a method may include receiving a bitstream; for a first frame including a first subframe and a second subframe, determining a first scaling constant associated with the first subframe; determining a second scaling constant associated with the second subframe; and reconstructing pixel data of the first frame using the first scaling constant and the second scaling constant, wherein the first scaling constant and the second scaling constant characterize different values.

[0052] In some embodiments, the first scaling constant may include a vertical scaling component and a horizontal scaling component. Reconstructing pixel data of the first frame may include reconstructing pixel data of the first subframe and reconstructing pixel data of the second frame. The first scaling constant may be signaled in the bitstream, and the second scaling constant may be signaled in the bitstream. The first scaling constant may be signaled in the bitstream as an index to a predetermined value. The second scaling constant may be signaled in the bitstream using at least picture parameters. The first scaling constant may be signaled in a picture parameter set (PPS). The first scaling constant may be signaled as a function of a pps_pic_width_in_luma_samples parameter, a pps_scaling_win_right_offset parameter, and a pps_scaling_win_left_offset parameter. A position of the first subframe within the first frame may be signaled in the PPS. At least one of receiving, determining, and reconstructing is performed by a decoder including an entropy decoder processor configured to receive the bitstream and decode the bitstream into quantized coefficients, an inverse quantization and inverse transform processor configured to process the quantized coefficients including performing inverse discrete cosine, a deblocking filter, a frame buffer, and an intra prediction processor.

[0053] It should be noted that any one or more of the aspects and embodiments described herein may be conveniently implemented using digital electronic circuitry, integrated circuit network, specially designed application-specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), computer hardware, firmware, software, and / or combinations thereof, as embodied and / or implemented within one or more machines (e.g., one or more computing devices utilized as user computing devices for electronic documents, one or more server devices such as document servers, etc.) programmed according to the teachings herein, as would be apparent to one skilled in the computer arts. These various aspects or features may include implementation within one or more computer programs and / or software executable and / or interpretable on a programmable system including at least one programmable processor, which may be special-purpose or general-purpose, coupled to receive data and instructions from and transmit data and instructions to a storage system, at least one input device, and at least one output device. Appropriate software coding can be readily prepared by skilled programmers based on the teachings of the present disclosure, as would be apparent to those skilled in the software arts. The aspects and implementations discussed above that employ software and / or software modules may also include appropriate hardware to assist in implementing the machine-executable instructions of the software and / or software modules.

[0054] Such software may be a computer program product employing a machine-readable storage medium. A machine-readable storage medium may be any medium capable of storing and / or encoding sequences of instructions for execution by a machine (e.g., a computing device), causing the machine to perform any one of the methodologies and / or embodiments described herein. Examples of machine-readable storage media include, but are not limited to, magnetic disks, optical disks (e.g., CDs, CD-Rs, DVDs, DVD-Rs, etc.), magneto-optical disks, read-only memory "ROM" devices, random-access memory "RAM" devices, magnetic cards, optical cards, solid-state memory devices, EPROMs, EEPROMs, programmable logic devices (PLDs), and / or any combination thereof. As used herein, machine-readable medium is intended to include a single medium and a collection of physically separate media, such as, for example, a collection of compact discs or one or more hard disk drives in combination with computer memory. As used herein, machine-readable storage medium does not include transitory forms of signal transmission.

[0055] Such software may also include information (e.g., data) carried in a data signal on a data carrier, such as a carrier wave. For example, machine-executable information may be included as a data carrier signal embodied in a data carrier, which signal encodes a sequence of instructions, or a portion thereof, for execution by a machine (e.g., a computing device), and any associated information (e.g., data structures and data) that causes the machine to perform any one of the methodologies and / or embodiments described herein.

[0056] Examples of computing devices include, but are not limited to, e-book reading devices, computer workstations, terminal computers, server computers, handheld devices (e.g., tablet computers, smartphones, etc.), web appliances, network routers, network switches, network bridges, any machine capable of executing a sequence of instructions that define actions to be taken by the machine, and any combination thereof. In one example, the computing device may include and / or be included within a kiosk.

[0057] 8 shows a diagrammatic representation of one embodiment of a computing device in the exemplary form of a computer system 800 upon which a set of instructions for causing a control system to implement any one or more of the aspects and / or methodologies of the present disclosure may be executed. It is also contemplated that multiple computing devices may be utilized to implement a specially configured set of instructions for causing one or more of the devices to implement any one or more of the aspects and / or methodologies of the present disclosure. Computer system 800 includes a processor 804 and a memory 808, which communicate with each other and with other components via a bus 812. Bus 812 may include any of several types of bus structures, including, but not limited to, a memory bus, a memory controller, a peripheral bus, a local bus, and any combination thereof, using any of a variety of bus architectures.

[0058] Memory 808 may include a variety of components (e.g., machine-readable media), including, but not limited to, random-access memory components, read-only components, and any combination thereof. In one embodiment, a basic input / output system 816 (BIOS), containing the basic routines that help to transfer information between elements within computer system 800, such as during start-up, may be stored in memory 808. Memory 808 may also include (e.g., stored on one or more machine-readable media) instructions (e.g., software) 820 that embody any one or more of the aspects and / or methodologies of the present disclosure. In another embodiment, memory 808 may further include any number of program modules, including, but not limited to, an operating system, one or more application programs, other program modules, program data, and any combination thereof.

[0059] Computer system 800 may also include a storage device 824. Examples of a storage device (e.g., storage device 824) include, but are not limited to, a hard disk drive, a magnetic disk drive, an optical disk drive in combination with optical media, a solid-state memory device, and any combination thereof. Storage device 824 may be connected to bus 812 by an appropriate interface (not shown). Exemplary interfaces include, but are not limited to, SCSI, Advanced Technology Attachment (ATA), Serial ATA, Universal Serial Bus (USB), IEEE 1394 (FIREWIRE®), and any combination thereof. In one embodiment, storage device 824 (or one or more components thereof) may removably interface with computer system 800 (e.g., via an external port connector (not shown)). In particular, storage device 824 and associated machine-readable media 828 may provide nonvolatile and / or volatile storage of machine-readable instructions, data structures, program modules, and / or other data for computer system 800. In one embodiment, software 820 may reside, completely or partially, within machine-readable medium 828. In another embodiment, software 820 may reside, completely or partially, within processor 804.

[0060] Computer system 800 may also include input devices 832. In one embodiment, a user of computer system 800 may type commands and / or other information into computer system 800 via input devices 832. Examples of input devices 832 include, but are not limited to, an alphanumeric input device (e.g., a keyboard), a pointing device, a joystick, a gamepad, an audio input device (e.g., a microphone, a voice response system, etc.), a cursor control device (e.g., a mouse), a touchpad, an optical scanner, a video capture device (e.g., a still camera, a video camera), a touch screen, and any combination thereof. Input devices 832 may interface to bus 812 via any of a variety of interfaces (not shown), including, but not limited to, a serial interface, a parallel interface, a gameport, a USB interface, a FIREWIRE® interface, an interface directly to bus 812, and any combination thereof. Input devices 832 may include a touch screen interface, which may be part of or separate from display 836, discussed further below. The input device 832 may be utilized as a user selection device for selecting one or more graphical representations within a graphical interface such as those described above.

[0061] A user may also input commands and / or other information into computer system 800 via storage device 824 (e.g., a removable disk drive, flash drive, etc.) and / or network interface device 840. A network interface device such as network interface device 840 may be utilized to connect computer system 800 to one or more of various networks, such as network 844, and one or more remote devices 848 connected thereto. Examples of network interface devices include, but are not limited to, a network interface card (e.g., a mobile network interface card, a LAN card), a modem, and any combination thereof. Examples of networks include, but are not limited to, a wide area network (e.g., the Internet, an enterprise network), a local area network (e.g., a network associated with an office, building, campus, or other relatively small geographic space), a telephone network, a data network associated with a telephone / voice provider (e.g., a mobile communications provider's data and / or voice network), a direct connection between two computing devices, and any combination thereof. A network such as network 844 may employ wired and / or wireless modes of communication. In general, any network topology may be used. Information (e.g., data, software 820, etc.) may be communicated to and / or from computer system 800 via network interface device(s) 840.

[0062] Computer system 800 may further include a video display adapter 852 for communicating images displayable on a display device, such as display device 836. Examples of a display device include, but are not limited to, a liquid crystal display (LCD), a cathode ray tube (CRT), a plasma display, a light emitting diode (LED) display, and any combination thereof. Display adapter 852 and display device 836 may be utilized in combination with processor 804 to provide graphical representations of aspects of the present disclosure. In addition to a display device, computer system 800 may include one or more other peripheral output devices, including, but not limited to, audio speakers, a printer, and any combination thereof. Such peripheral output devices may be connected to bus 812 via a peripheral interface 856. Examples of a peripheral interface include, but are not limited to, a serial port, a USB connection, a FIREWIRE® connection, a parallel connection, and any combination thereof.

[0063] The foregoing is a detailed description of illustrative embodiments of the present invention. Various modifications and additions may be made without departing from the spirit and scope of the present invention. Features of each of the various embodiments described above may be combined, as appropriate, with features of other described embodiments to provide a combination of features in a related new embodiment. Moreover, while the foregoing describes several separate embodiments, what has been described herein merely illustrates the application of the principles of the present invention. In addition, although certain methods herein may be illustrated and / or described as being performed in a particular order, the order may be highly variable among those skilled in the art to achieve the embodiments as disclosed herein. Therefore, this description is intended to be taken as example only and is not intended to otherwise limit the scope of the present invention.

[0064] In the above description and in the claims, phrases such as "at least one of" or "one or more of" may appear and be followed by a conjunctive listing of elements or features. The term "and / or" may also appear within a listing of two or more elements or features. Unless otherwise implicitly or explicitly contradicted by the context in which such a phrase is used, this is intended to mean any of the listed elements or features individually or any of the recited elements or features in combination with any of the other recited elements or features. For example, the phrases "at least one of A and B," "one or more of A and B," and "A and / or B" are intended to mean "A alone, B alone, or A and B together," respectively. A similar interpretation is also intended with respect to listings containing three or more items. For example, the phrases "at least one of A, B, and C," "one or more of A, B, and C," and "A, B, and / or C" are intended to mean "A alone, B alone, C alone, A and B together, A and C together, B and C together, or A, B, and C together," respectively. Additionally, use of the term "based on" above and in the claims is intended to mean "based at least on," so that unrecited features or elements also qualify as permissible.

[0065] The subject matter described herein can be embodied in systems, devices, methods, and / or articles, depending on the desired configuration. The implementations described in the foregoing description do not represent all consistent implementations of the subject matter described herein. Instead, they are merely some examples consistent with aspects related to the described subject matter. While some variations have been described in detail above, other modifications or additions are possible. In particular, additional features and / or variations can be provided in addition to those described herein. For example, the implementations described above can be directed to various combinations and subcombinations of the disclosed features and / or combinations and subcombinations of some additional features disclosed above. In addition, the logic flow depicted in the accompanying figures and / or described herein does not necessarily require the particular order shown or sequential order to achieve desirable results. Other implementations may be within the scope of the following claims.

Claims

[Claim 1] The invention described in this specification.

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