Display apparatus

Abstract

SOLUTION: To provide a display apparatus according to an embodiment of the present disclosure can include a light-emitting device and an encapsulation structure, in which the light-emitting device and the encapsulation structure can be positioned on a device substrate, the encapsulation structure covering the light-emitting device can include at least one organic encapsulating layer positioned between inorganic encapsulating layers, the organic encapsulating layer can be positioned in a region defined by a dam, at least one organic insulating layer can be positioned between the device substrate and the light-emitting device, the organic insulating layer can extend outside the dam, the inorganic encapsulating layers of the encapsulation structure can be stacked on an end portion of the organic insulating layer, a first pattern can be positioned on the encapsulation structure, and the first pattern can extend along the end portion of the organic insulating layer.EFFECT: In the display apparatus, penetration of external moisture through a crack of the first pattern of the insulating layer can be prevented.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present specification relates to a display device. [Background technology]

[0002] In a display device that provides an image to a user, cracks may form in the inorganic encapsulation layer, and thus, the light emitting element of the display device may be deteriorated due to external moisture that penetrates through the cracks. Summary of the Invention [Problem to be solved by the invention]

[0003] An object of the present invention is to provide a display device that can reduce deterioration of light emitting elements due to penetration of external moisture.

[0004] Another object of the present invention is to provide a display device that can prevent moisture penetration due to cracks formed in an inorganic sealing layer of a sealing structure.

[0005] The problems to be solved are not limited to those mentioned above, and problems not mentioned here will be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0006] A display device according to the technical idea of ​​the present specification for achieving the problem to be solved includes an element substrate. A dam is located on the element substrate. The dam surrounds a display area of ​​the element substrate. An organic sealing layer is located within the area defined by the dam. A first inorganic sealing layer is located between the element substrate and the organic sealing layer. The first inorganic sealing layer extends along the surface of the dam. A second inorganic sealing layer is located on the organic sealing layer. The second inorganic sealing layer is located on the first inorganic sealing layer outside the dam. An organic insulating layer is located between the element substrate and the first inorganic sealing layer. An edge of the organic insulating layer is located outside the dam. A first pattern is located on the second inorganic sealing layer. The first pattern overlaps the edge of the organic insulating layer.

[0007] To achieve another object of the present disclosure, a display device according to the technical idea of ​​the present disclosure includes an element substrate. The element substrate includes a display area and a bezel area. The bezel area is located outside the display area. A first organic insulating layer is located on the display area of ​​the element substrate. The first organic insulating layer extends over the bezel area of ​​the element substrate. A first inorganic sealing layer is located on the first organic insulating layer. The first inorganic sealing layer extends outside the first organic insulating layer. A dam is located between the first organic insulating layer and the first inorganic sealing layer in the bezel area. An organic sealing layer is located on the first inorganic sealing layer in the display area. The organic sealing layer is surrounded by the dam. A second inorganic sealing layer is located on the organic sealing layer and the dam. The second inorganic sealing layer contacts the first inorganic sealing layer outside the dam. A first pattern is located on the second inorganic sealing layer. The first pattern is located parallel to the dam. The first pattern overlaps an edge of the first organic insulating layer.

[0008] A display device according to the technical concept of the present specification includes an organic insulating layer located on an element substrate, a first inorganic encapsulation layer, a second inorganic encapsulation layer, a dam, and a first pattern. The dam surrounding the organic encapsulation layer is located between the organic insulating layer and the first inorganic encapsulation layer in the bezel region. The first pattern is located on the second inorganic encapsulation layer that contacts the first inorganic encapsulation layer outside the dam, and an edge of the organic insulating layer parallel to the dam may overlap with the first pattern. Therefore, in the display device according to the technical concept of the present specification, the first pattern can block cracks formed in the first inorganic encapsulation layer and / or the second inorganic encapsulation layer. That is, in the display device according to the technical concept of the present specification, the first pattern can block the penetration of external moisture through cracks formed in the first inorganic encapsulation layer and / or the second inorganic encapsulation layer. Therefore, the display device according to the technical concept of the present specification can reduce degradation of light-emitting elements due to penetration of external moisture. Furthermore, the display device according to the technical concept of the present specification can extend the life of the light-emitting elements. Furthermore, the display device according to the technical idea of ​​the present specification can be driven with low power, thereby reducing power consumption. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a diagram illustrating a schematic diagram of a display device according to an embodiment of the present disclosure; [Figure 2] FIG. 2 is a diagram illustrating a circuit of a pixel area of ​​a display device according to an embodiment of the present disclosure. [Figure 3] FIG. 2 is a cross-sectional view taken along line II in FIG. [Figure 4] FIG. 2 is an enlarged view of the K region in FIG. 1. [Figure 5] FIG. 2 is a cross-sectional view taken along line II-II in FIG. [Figure 6] FIG. 5 is a cross-sectional view taken along line III-III in FIG. [Figure 7] FIG. 10 illustrates a display device according to another embodiment of the present disclosure. [Figure 8] FIG. 10 illustrates a display device according to another embodiment of the present disclosure. [Figure 9] FIG. 10 illustrates a display device according to another embodiment of the present disclosure. [Figure 10] FIG. 10 illustrates a display device according to another embodiment of the present disclosure. [Figure 11] FIG. 10 illustrates a display device according to another embodiment of the present disclosure. [Figure 12] FIG. 10 illustrates a display device according to another embodiment of the present disclosure. [Figure 13] FIG. 10 illustrates a display device according to another embodiment of the present disclosure. [Figure 14] FIG. 10 illustrates a display device according to another embodiment of the present disclosure. [Figure 15] FIG. 10 illustrates a display device according to another embodiment of the present disclosure. [Figure 16] FIG. 10 illustrates a display device according to another embodiment of the present disclosure. [Figure 17] FIG. 10 illustrates a display device according to another embodiment of the present disclosure. [Figure 18] FIG. 10 illustrates a display device according to another embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0010] The purpose, technical configuration, and operational effects of the present specification will be more clearly understood from the following detailed description with reference to the drawings illustrating examples of the present specification. The examples of the present specification are provided to fully convey the technical ideas of the present specification to those skilled in the art, and the present specification is not limited to the examples described below and may be embodied in other forms.

[0011] Furthermore, parts denoted by the same reference numerals throughout the specification refer to the same components, and in the drawings, the length and thickness of layers or regions may be exaggerated for convenience. Furthermore, when a first component is described as being "on" a second component, this includes not only the case where the first component is located above and in direct contact with the second component, but also the case where a third component is located between the first and second components.

[0012] Here, the terms "first," "second," etc. are used to describe various components and to distinguish one component from another, but the first and second components may be named arbitrarily for the convenience of those skilled in the art without departing from the technical spirit of this specification.

[0013] The terms used in the specification of this specification are used only to describe specific embodiments and are not intended to limit the technical ideas of the specification. For example, elements expressed in the singular include plural elements unless the context clearly dictates that only the singular element is used. Furthermore, in the specification of this specification, terms such as "comprise" or "have" are intended to specify the presence of features, numbers, steps, operations, elements, components, or combinations thereof described in the specification, and should be understood as not precluding the possibility of the presence or addition of one or more other features, numbers, steps, operations, elements, components, or combinations thereof.

[0014] Furthermore, unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by a person of ordinary skill in the art to which this specification pertains. Terms, such as those defined in commonly used dictionaries, should be interpreted to have a meaning consistent with the meaning they have in the context of the relevant art, and should not be interpreted in an idealized or overly formal sense unless expressly defined in the specification of this specification.

[0015] (Example) FIG. 1 is a diagram schematically illustrating a display device according to an embodiment of the present specification. FIG. 2 is a diagram illustrating a circuit in a pixel region of a display device according to an embodiment of the present specification. FIG. 3 is a diagram illustrating a cross section taken along line II in FIG. 1. FIG. 4 is an enlarged view of region K in FIG. 1. FIG. 5 is a diagram illustrating a cross section taken along line II-II in FIG. 1. FIG. 6 is a diagram illustrating a cross section taken along line III-III in FIG. 4.

[0016] 1 to 6, a display device according to an embodiment of the present disclosure includes a display panel DP. The display panel DP may generate an image to be provided to a user. For example, pixel areas PA may be located within the display panel DP. Various signals may be applied to each pixel area PA via signal lines GL, DL, and PL. For example, the signal lines GL, DL, and PL may include a gate line GL that applies a gate signal, a data line DL that applies a data signal, and a power line PL that supplies a positive power voltage.

[0017] Each pixel area PA can emit light of a specific color. For example, a driving circuit DC electrically connected to the light-emitting element 500 can be located within each pixel area PA. The driving circuit DC of each pixel area PA can control the light-emitting element 500 in the pixel area PA in response to signals applied via the signal lines GL, DL, and PL. For example, the driving circuit DC of each pixel area PA can supply a driving current corresponding to a data signal to the light-emitting element 500 in the pixel area PA in response to a gate signal. The driving circuit DC of each pixel area PA can be electrically connected to one of the gate lines GL, one of the data lines DL, and one of the power supply lines PL. The driving current supplied to the light-emitting element 500 in the pixel area PA by the driving circuit DC of each pixel area PA can be maintained for one frame. For example, the driving circuit DC of each pixel area PA can include a first thin film transistor TR1, a second thin film transistor TR2, and a storage capacitor Cst.

[0018] The first thin film transistor TR1 of each pixel area PA can transmit a data signal to the second thin film transistor TR2 of the pixel area PA in response to a gate signal. For example, the first thin film transistor TR1 of each pixel area PA can function as a switching thin film transistor. The first thin film transistor TR1 of each pixel area PA can include a first semiconductor pattern 211, a first gate electrode 213, a first drain electrode 215, and a first source electrode 217. For example, the first gate electrode 213 of each pixel area PA can be electrically connected to the corresponding gate line GL, and the first drain electrode 215 of each pixel area PA can be electrically connected to the corresponding data line DL.

[0019] The first semiconductor pattern 211 may include a semiconductor material. For example, the first semiconductor pattern 211 may include low temperature polysilicon (LTPS). The first semiconductor pattern 211 may include a first drain region, a first channel region, and a first source region. The first channel region may be located between the first drain region and the first source region. The resistance of the first drain region and the resistance of the first source region may be smaller than the resistance of the first channel region. For example, the first drain region and the first source region may include conductive impurities. The first channel region may be a region that is not doped with conductive impurities.

[0020] The first gate electrode 213 may be located on a portion of the first semiconductor pattern 211. For example, the first gate electrode 213 may overlap a first channel region of the first semiconductor pattern 211. A first drain region and a first source region of the first semiconductor pattern 211 may be located outside the first gate electrode 213. The first gate electrode 213 may include a conductive material. For example, the first gate electrode 213 may include a metal such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), and tungsten (W). The first gate electrode 213 may be spaced apart from the first semiconductor pattern 211. The first gate electrode 213 may be insulated from the first semiconductor pattern 211. For example, the first drain region of the first semiconductor pattern 211 may be electrically connected to the first source region of the first semiconductor pattern 211 in response to a signal applied to the first gate electrode 213.

[0021] The first drain electrode 215 may include a conductive material. For example, the first drain electrode 215 may include a metal such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), and tungsten (W). The first drain electrode 215 may include a different material from the first gate electrode 213. The first drain electrode 215 may be located on a different layer from the first gate electrode 213. The first drain electrode 215 may be electrically connected to the first drain region of the first semiconductor pattern 211. The first drain electrode 215 may be insulated from the first gate electrode 213.

[0022] The first source electrode 217 may include a conductive material. For example, the first source electrode 217 may include a metal such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), and tungsten (W). The first source electrode 217 may include a different material from the first gate electrode 213. The first source electrode 217 may be located on a different layer from the first gate electrode 213. For example, the first source electrode 217 may be located on the same layer as the first drain electrode 215. The first source electrode 217 may include the same material as the first drain electrode 215. The first source electrode 217 may be formed in the same process as the first drain electrode 215. For example, the first source electrode 217 may be formed simultaneously with the first drain electrode 215. The first source electrode 217 may be electrically connected to the first source region of the first semiconductor pattern 211. The first source electrode 217 may be insulated from the first gate electrode 213. The first source electrode 217 may be spaced apart from the first drain electrode 215 .

[0023] The second thin film transistor TR2 of each pixel area PA can generate a driving current corresponding to a data signal. For example, the second thin film transistor TR2 of each pixel area PA can function as a driving thin film transistor. The second thin film transistor TR2 of each pixel area PA can include a second semiconductor pattern 221, a second gate electrode 223, a second drain electrode 225, and a second source electrode 227. For example, the second gate electrode 223 of each pixel area PA can be electrically connected to the first source electrode 217 of the pixel area PA, and the second drain electrode 225 of each pixel area PA can be electrically connected to the power line PL.

[0024] The second semiconductor pattern 221 may include a semiconductor material. The second semiconductor pattern 221 may include a material different from that of the first semiconductor pattern 211. For example, the second semiconductor pattern 221 may include an oxide semiconductor such as IGZO. The second semiconductor pattern 221 may be located on a different layer from that of the first semiconductor pattern 211.

[0025] The second semiconductor pattern 221 may include a second drain region, a second channel region, and a second source region. The second channel region may be located between the second drain region and the second source region. The second drain region and the second source region may have a lower resistance than the second channel region. For example, the second drain region and the second source region may include a conductive region of an oxide semiconductor. The second channel region may be a non-conductive region of the oxide semiconductor.

[0026] The second gate electrode 223 may be located on a portion of the second semiconductor pattern 221. For example, the second gate electrode 223 may overlap the second channel region of the second semiconductor pattern 221. The second drain region and the second source region of the second semiconductor pattern 221 may be located outside the second gate electrode 223. The second gate electrode 223 may include a conductive material. For example, the second gate electrode 223 may include a metal such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), and tungsten (W). The second gate electrode 223 may be spaced apart from the second semiconductor pattern 221. The second gate electrode 223 may be insulated from the second semiconductor pattern 221. For example, the second channel region of the second semiconductor pattern 221 may have electrical conductivity corresponding to a voltage applied to the second gate electrode 223.

[0027] The second gate electrode 223 may include a different material than the first gate electrode 213. For example, the second gate electrode 223 may be located on a different layer than the first gate electrode 213.

[0028] The second drain electrode 225 may include a conductive material. For example, the second drain electrode 225 may include a metal such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), and tungsten (W). The second drain electrode 225 may include a different material from the second gate electrode 223. The second drain electrode 225 may be located on a different layer from the second gate electrode 223. The second drain electrode 225 may be electrically connected to the second drain region of the second semiconductor pattern 221. The second drain electrode 225 may be insulated from the second gate electrode 223.

[0029] The second drain electrode 225 may be located on the same layer as the first drain electrode 215. The second drain electrode 225 may include the same material as the first drain electrode 215. The second drain electrode 225 may be formed in the same process as the first drain electrode 215. For example, the second drain electrode 225 may be formed simultaneously with the first drain electrode 215.

[0030] The second source electrode 227 may include a conductive material. For example, the second source electrode 227 may include a metal such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), and tungsten (W). The second source electrode 227 may include a different material from the second gate electrode 223. The second source electrode 227 may be located on a different layer from the second gate electrode 223. The second source electrode 227 may be located on the same layer as the second drain electrode 225. The second source electrode 227 may include the same material as the second drain electrode 225. The second source electrode 227 may be formed in the same process as the second drain electrode 225. For example, the second source electrode 227 may be formed simultaneously with the second drain electrode 225. The second source electrode 227 may be electrically connected to the second source region of the second semiconductor pattern 221. The second source electrode 227 may be insulated from the second gate electrode 223. The second source electrode 227 may be spaced apart from the second drain electrode 225 .

[0031] The storage capacitor Cst of each pixel area PA can maintain the voltage applied to the second gate electrode 223 of the pixel area PA for one frame. For example, the storage capacitor Cst of each pixel area PA can be electrically connected to the second gate electrode 223 and the second source electrode 227 of the pixel area PA. The storage capacitor Cst of each pixel area PA can have a stacked structure of capacitor electrodes. For example, the storage capacitor Cst of each pixel area PA can include a first capacitor electrode electrically connected to the second gate electrode 223 of the pixel area PA and a second capacitor electrode 232 electrically connected to the second source electrode 227 of the pixel area PA. At least one of the capacitor electrodes of the storage capacitor Cst located in each pixel area PA can be formed during the formation process of the first thin film transistor TR1 and the second thin film transistor TR2 located in the pixel area PA. Therefore, the display device according to the embodiment of the present specification can simplify the process of forming the driving circuit DC in each pixel area PA.

[0032] The driving circuit DC of each pixel area PA may be supported by the device substrate 100. For example, the first thin film transistor TR1, the second thin film transistor TR2, and the storage capacitor Cst of each pixel area PA may be located on the device substrate 100. The device substrate 100 may include an insulating material. For example, the device substrate 100 may include glass or plastic.

[0033] At least one insulating layer 110, 121, 122, 130, 140, 150, 160, 170, 180, 190 for preventing unwanted electrical connection may be positioned on the device substrate 100. For example, a lower buffer layer 110, a lower gate insulating layer 121, an upper gate insulating layer 122, an isolation insulating layer 130, an upper buffer layer 140, an upper interlayer insulating layer 150, a device protection layer 160, a lower planarization layer 170, an upper planarization layer 180, and a bank insulating layer 190 may be positioned on the device substrate 100.

[0034] The lower buffer layer 110 may be disposed on the device substrate 100. The lower buffer layer 110 may prevent contamination by the device substrate 100 during the process of forming the driving circuit DC of each pixel region PA. For example, the upper surface of the device substrate 100 facing the driving circuit DC of each pixel region PA may be completely covered by the lower buffer layer 110. The first thin film transistor TR1, the second thin film transistor TR2, and the storage capacitor Cst of each pixel region PA may be disposed on the lower buffer layer 110. The lower buffer layer 110 may include an insulating material. For example, the lower buffer layer 110 may be an inorganic insulating layer made of an inorganic insulating material such as silicon oxide (SiOx) and silicon nitride (SiNx). The lower buffer layer 110 may have a multi-layer structure. For example, the lower buffer layer 110 may have a structure in which an inorganic insulating layer made of silicon oxide (SiOx) and an inorganic insulating layer made of silicon nitride (SiNx) are stacked.

[0035] The lower gate insulating layer 121 may be located on the lower buffer layer 110. The first gate electrode 213 of each pixel region PA may be insulated from the first semiconductor pattern 211 of the pixel region PA by the lower gate insulating layer 121. The lower gate insulating layer 121 may cover the first semiconductor pattern 211 of each pixel region PA. For example, the first semiconductor pattern 211 of each pixel region PA may be located between the lower buffer layer 110 and the lower gate insulating layer 121 of the pixel region PA. The first gate electrode 213 of each pixel region PA may be located on the lower gate insulating layer 121. The lower gate insulating layer 121 may include an insulating material. For example, the lower gate insulating layer 121 may be an inorganic insulating layer made of an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx).

[0036] The isolation insulating layer 130 may be located on the lower gate insulating layer 121. The first gate electrode 213 of each pixel region PA may be covered by the isolation insulating layer 130. For example, the first gate electrode 213 of each pixel region PA may be located between the lower gate insulating layer 121 and the isolation insulating layer 130 of the pixel region PA. The isolation insulating layer 130 may include an insulating material. For example, the isolation insulating layer 130 may be an inorganic insulating layer made of an inorganic insulating material. The isolation insulating layer 130 may have a different thickness from the lower gate insulating layer 121. For example, the thickness of the isolation insulating layer 130 may be greater than the thickness of the lower gate insulating layer 121.

[0037] The upper buffer layer 140 may be disposed on the isolation insulating layer 130. The upper gate insulating layer 122 may be disposed on the upper buffer layer 140. The upper buffer layer 140 and the upper gate insulating layer 122 may include an insulating material. For example, the upper buffer layer 140 and the upper gate insulating layer 122 may be inorganic insulating layers made of an inorganic insulating material such as silicon oxide (SiOx) and silicon nitride (SiNx). The upper gate insulating layer 122 may include a different material from the upper buffer layer 140.

[0038] The upper gate insulating layer 122 can insulate the second gate electrode 223 of each pixel region PA from the second semiconductor pattern 221 of the pixel region PA. The second semiconductor pattern 221 of each pixel region PA can be covered by the upper gate insulating layer 122. For example, the second semiconductor pattern 221 of each pixel region PA can be located between the upper buffer layer 140 of the pixel region PA and the upper gate insulating layer 122. The second gate electrode 223 of each pixel region PA can be located on the upper gate insulating layer 122.

[0039] A light-shielding pattern 300 may be positioned between the isolation insulating layer 130 and the upper buffer layer 140 in each pixel region PA. The light-shielding pattern 300 in each pixel region PA may overlap the second semiconductor pattern 221 in the corresponding pixel region PA. The light-shielding pattern 300 in each pixel region PA may include a material capable of blocking light. For example, the light-shielding pattern 300 in each pixel region PA may include a metal. Therefore, the display device according to the embodiment of the present specification may prevent changes in the characteristics of the second thin film transistor TR2 located in each pixel region PA due to external light entering through the device substrate 100. Therefore, the display device according to the embodiment of the present specification may improve the reliability of the driving circuit DC located in each pixel region PA.

[0040] The upper interlayer insulating layer 150 may be located on the upper gate insulating layer 122. The second drain electrode 225 and the second source electrode 227 of each pixel region PA may be insulated from the second gate electrode 223 of the pixel region PA by the upper interlayer insulating layer 150. The upper interlayer insulating layer 150 may cover the second gate electrode 223 of each pixel region PA. For example, the second gate electrode 223 of each pixel region PA may be located between the upper gate insulating layer 122 of the pixel region PA and the upper interlayer insulating layer 150. The upper interlayer insulating layer 150 may include an insulating material. For example, the upper interlayer insulating layer 150 may be an inorganic insulating layer made of an inorganic insulating material. The second drain electrode 225 and the second source electrode 227 of each pixel region PA may be located on the upper interlayer insulating layer 150. For example, the second drain electrode 225 of each pixel area PA can penetrate the upper interlayer insulating layer 150 and directly contact the second drain region of the pixel area PA, and the second source electrode 227 of each pixel area PA can penetrate the upper interlayer insulating layer 150 and directly contact the second source region of the pixel area PA.

[0041] The first drain electrode 215 and the first source electrode 217 of each pixel region PA may be located on the upper interlayer insulating layer 150. For example, the first drain electrode 215 and the first source electrode 217 of each pixel region PA may be insulated from the first gate electrode 213 of the pixel region PA by the isolation insulating layer 130, the upper buffer film 140, the upper gate insulating layer 122, and the upper interlayer insulating layer 150. The first drain electrode 215 of each pixel region PA may be in direct contact with the first drain region of the pixel region PA by passing through the isolation insulating layer 130, the upper buffer film 140, the upper gate insulating layer 122, and the upper interlayer insulating layer 150. The first source electrode 217 of each pixel region PA may be in direct contact with the first source region of the pixel region PA by passing through the isolation insulating layer 130, the upper buffer film 140, the upper gate insulating layer 122, and the upper interlayer insulating layer 150.

[0042] The device protection layer 160 may be disposed on the upper interlayer insulating layer 150. The device protection layer 160 may prevent damage to the driving circuits DC located in each pixel area PA due to external impact and moisture. The device protection layer 160 may extend along the surface of the driving circuits DC located in each pixel area PA facing the device substrate 100. For example, the first drain electrode 215, the first source electrode 217, the second drain electrode 225, and the second source electrode 227 of each pixel area PA may be covered by the device protection layer 160. The device protection layer 160 may include an insulating material. For example, the device protection layer 160 may be an inorganic insulating layer made of an inorganic insulating material.

[0043] The lower planarization layer 170 may be disposed on the device protection layer 160. The upper planarization layer 180 may be disposed on the lower planarization layer 170. For example, the lower planarization layer 170 may be disposed between the device protection layer 160 and the upper planarization layer 180. The lower planarization layer 170 and the upper planarization layer 180 may eliminate steps due to the driving circuits DC in each pixel area PA. For example, the upper surface of the upper planarization layer 180 facing the device substrate 100 may be flat. The lower planarization layer 170 and the upper planarization layer 180 may include an insulating material. The lower planarization layer 170 and the upper planarization layer 180 may include a different material from the device protection layer 160. The lower planarization layer 170 and the upper planarization layer 180 may include a material with high fluidity. For example, the lower planarization layer 170 and the upper planarization layer 180 may be an organic insulating layer made of an organic insulating material. The upper planarization layer 180 may comprise the same material as the lower planarization layer 170. For example, the boundary between the lower planarization layer 170 and the upper planarization layer 180 may be imperceptible.

[0044] The light-emitting element 500 of each pixel region PA may be located on the upper planarization layer 180. The light-emitting element 500 of each pixel region PA may emit light of a specific color. For example, the light-emitting element 500 of each pixel region PA may include a first electrode 510, a light-emitting layer 520, and a second electrode 530 stacked in this order on the upper planarization layer 180 of the pixel region PA.

[0045] The first electrode 510 may include a conductive material. The first electrode 510 may include a material having a relatively high reflectivity. For example, the first electrode 510 may include a metal such as aluminum (Al) or silver (Ag). The first electrode 510 may have a multi-layer structure. For example, the first electrode 510 may have a structure in which a reflective electrode made of a metal is located between transparent electrodes made of a transparent conductive material such as ITO or IZO.

[0046] The light-emitting layer 520 can generate light having a brightness corresponding to the voltage difference between the first electrode 510 and the second electrode 530. For example, the light-emitting layer 520 can include at least one emission material layer (EML). The emission material layer can include an organic light-emitting material, an inorganic light-emitting material, or a hybrid light-emitting material. For example, a display device according to an embodiment of the present disclosure can be an organic light-emitting display device including an organic light-emitting material.

[0047] The light-emitting layer 520 may have a multi-layer structure. For example, the light-emitting layer 520 may further include at least one of a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), and an electron injection layer (EIL). Therefore, the display device according to the embodiment of the present disclosure may improve the efficiency of the light-emitting layer 520.

[0048] The second electrode 530 may include a conductive material. The second electrode 530 may include a material different from that of the first electrode 510. The transmittance of the second electrode 530 may be higher than that of the first electrode 510. For example, the second electrode 530 may be a transparent electrode made of a transparent conductive material such as ITO or IZO. Therefore, the display device according to the embodiment of the present specification may emit light generated by the light-emitting layer 520 to the outside through the second electrode 530. The second electrode 530 may have a smaller work function than the first electrode 510. For example, the first electrode 510 may function as an anode electrode, and the second electrode 530 may function as a cathode electrode.

[0049] The bank insulating layer 190 may be disposed on the upper planarization layer 180. The first electrode 510 in each pixel region PA may be insulated from the first electrode 510 in an adjacent pixel region PA by the bank insulating layer 190. For example, the edge of the first electrode 510 in each pixel region PA may be covered by the bank insulating layer 190. The first electrode 510 in each pixel region PA may be partially exposed by the bank insulating layer 190. For example, the bank insulating layer 190 may define an emissive area EA in each pixel region PA. The emissive layer 520 and the second electrode 530 in each pixel region PA may be stacked on the first electrode 510 overlapping the emissive area EA defined in the pixel region PA by the bank insulating layer 190. For example, in the emissive area EA of each pixel region PA, the emissive layer 520 may be in direct contact with the first electrode 510 and the second electrode 530 of the pixel region PA. The bank insulating layer 190 may include an insulating material. For example, the bank insulating layer 190 may be an organic insulating layer made of an organic insulating material. The bank insulating layer 190 may comprise a different material than the upper planarizing layer 180 .

[0050] The first electrode 510 of each pixel region PA may be electrically connected to the driving circuit DC of the pixel region PA. For example, the first electrode 510 of each pixel region PA may be connected to the second source electrode 227 of the pixel region PA by passing through the device protection layer 160, the lower planarization layer 170, and the upper planarization layer 180. A region where the first electrode 510 of each pixel region PA is electrically connected to the second source electrode 227 of the pixel region PA may overlap with the bank insulating layer 190. Therefore, the display device according to the embodiment of the present disclosure may minimize positional variations of the first electrode 510 within the light-emitting region EA of each pixel region PA. For example, a portion of the first electrode 510 located within the light-emitting region EA of each pixel region PA may directly contact the upper surface of the upper planarization layer 180. Therefore, the display device according to the embodiment of the present disclosure may prevent brightness deviation due to the generation position of light emitted from the light-emitting region EA of each pixel region PA.

[0051] An intermediate electrode 400 may be located between the lower planarization layer 170 and the upper planarization layer 180, electrically connecting the light emitting element 500 in each pixel region PA to the driving circuit DC of the pixel region PA. The intermediate electrode 400 may include a conductive material. For example, the intermediate electrode 400 may include a metal such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), and tungsten (W). Each intermediate electrode 400 may directly contact the second source electrode 227 and the first electrode 510 of one of the pixel regions PA. For example, the first electrode 510 of each pixel region PA may penetrate the upper planarization layer 180 and directly contact one of the intermediate electrodes 400, and each intermediate electrode 400 may penetrate the lower planarization layer 170 and directly contact the second source electrode 227 of one of the pixel regions PA. Therefore, in the display device according to the embodiment of the present specification, the first electrode 510 of each pixel area PA can be stably connected to the second source electrode 227 of the pixel area PA. Therefore, the display device according to the embodiment of the present specification can improve the reliability of the electrical connection between the driving circuit DC and the light emitting element 500 located in each pixel area PA.

[0052] The light emitted from the light emitting element 500 in each pixel region PA may exhibit a different color from the light emitted from the light emitting element 500 in the adjacent pixel region PA. For example, the light emitting layer 520 in each pixel region PA may be separated from the light emitting layer 520 in the adjacent pixel region PA by the bank insulating layer 190. The light emitting layer 520 in each pixel region PA may include an edge portion located on the bank insulating layer 190. The light emitting layer 520 in each pixel region PA may include a different material from the light emitting layer 520 in the adjacent pixel region PA. For example, the light emitting layer 520 in each pixel region PA may have a different stack structure from the light emitting layer 520 in the adjacent pixel region PA.

[0053] The voltage applied to the second electrode 530 in each pixel region PA may be the same as the voltage applied to the second electrode 530 in the adjacent pixel region PA. The voltage applied to the second electrode 530 in each pixel region PA may be different from the voltage supplied via the power line PL. For example, a negative power supply voltage VSS may be applied to the second electrode 530 in each pixel region PA. The second electrode 530 in each pixel region PA may be electrically connected to the second electrode 530 in the adjacent pixel region PA. The second electrode 530 in each pixel region PA may include the same material as the second electrode 530 in the adjacent pixel region PA. The second electrode 530 in each pixel region PA may be formed in the same process as the second electrode 530 in the adjacent pixel region PA. For example, the second electrode 530 in each pixel region PA may be formed simultaneously with the second electrode 530 in the adjacent pixel region PA. The second electrode 530 in each pixel region PA may be in direct contact with the second electrode 530 in the adjacent pixel region PA on the bank insulating layer 190. Therefore, the display device according to the embodiment of the present specification can simplify the process of forming the second electrode 530 of each pixel area PA. Furthermore, the display device according to the embodiment of the present specification can adjust the brightness of the light generated by the light emitting layer 520 of each pixel area PA by a data signal applied to the driving circuit DC of the pixel area PA.

[0054] An encapsulation structure 600 may be disposed on the light emitting device 500 in each pixel area PA. The encapsulation structure 600 may prevent damage to the light emitting device 500 due to external moisture and impact. The encapsulation structure 600 may include an insulating material. The encapsulation structure 600 may have a multi-layer structure. For example, the encapsulation structure 600 may have a stacked structure of inorganic encapsulation layers 610 and 630 made of an inorganic insulating material and an organic encapsulation layer 620 made of an organic insulating material. The organic encapsulation layer 620 may be disposed between the inorganic encapsulation layers 610 and 630. For example, the encapsulation structure 600 may include a first inorganic encapsulation layer 610, an organic encapsulation layer 620, and a second inorganic encapsulation layer 630, which are stacked in order. The second inorganic encapsulation layer 630 may include a different material from the first inorganic encapsulation layer 610. Therefore, the display device according to the embodiment of the present specification may effectively prevent damage to the light emitting device 500 due to external moisture and impact.

[0055] Steps caused by the light-emitting elements 500 in each pixel region PA can be eliminated by the organic sealing layer 620. For example, the upper surface of the sealing structure 600 facing the element substrate 100 can be flat. The thickness of the organic sealing layer 620 may be greater than the thickness of the first inorganic sealing layer 610 and the thickness of the second inorganic sealing layer 630.

[0056] The display panel DP may include a display area AA in which the pixel area PA is located and a bezel area BZ located outside the pixel area PA. The bezel area BZ may be located outside the display area AA. The bezel area BZ may have a shape that extends along the edge of the display area AA. For example, the display area AA may be surrounded by the bezel area BZ.

[0057] A gate driver GD electrically connected to the gate lines GL, a data driver electrically connected to the data lines DL, a power supply unit electrically connected to the power supply lines PL, and a timing controller controlling the gate driver GD and the data driver may be located outside the display area AA. For example, each of the signal lines GL, DL, and PL may include an area located on the bezel area BZ. At least one of the gate driver GD, data driver, power supply unit, and timing controller may be located on the bezel area BZ. For example, a display device according to an embodiment of the present specification may be a GIP (Gate In Panel) type display device in which the gate driver GD is formed on the bezel area BZ of the device substrate 100.

[0058] A pad area PAD to which external signals are applied may be located within the bezel area BZ. Data drivers, power supply units, and timing controllers located outside the display panel DP may apply signals through the pad area PAD. For example, the data lines DL, power supply lines PL, and gate driver GD may be electrically connected to the pad area PAD. The pad area PAD may be located on one side of the display area AA. The gate driver GD and pad area PAD may be located on the other side of the display area AA. For example, the display area AA may include a first side A1 facing the pad area PAD, a second side A2 perpendicular to the first side A1, a third side A3 opposite the second side A2, and a fourth side A4 opposite the first side A1, and the gate driver GD may be located on the second side A2 of the display area AA.

[0059] A bending area BA may be located between the first side A1 of the display area AA and the pad area PAD. The bending area BA may be a flexible area. For example, a display device according to an embodiment of the present disclosure may be a flexible display device in which the pad area PAD overlaps the display area AA due to bending of the bending area BA. Therefore, the display device according to an embodiment of the present disclosure may reduce the size of the bezel area BZ perceived by a user.

[0060] At least one dam 105 may be located on the bezel region BZ of the device substrate 100. The dam 105 may block the flow of the organic encapsulation layer 620. For example, the dam 105 may surround the display region AA. The organic encapsulation layer 620 may be located within the region defined by the dam 105. For example, the organic encapsulation layer 620 may be surrounded by the dam 105. The dam 105 may be located near the display region AA. For example, the dam 105 may include a region located between the first side A1 of the display region AA and the pad region PAD and a region located between the second side A2 of the display region AA and the gate driver GD. Therefore, in the display device according to the embodiment of the present disclosure, the gate driver GD and / or the pad region PAD may not be covered by the organic encapsulation layer 620. Therefore, in the display device according to the embodiment of the present disclosure, the flow and damage of the pads located in the pad region PAD and the wiring located in the gate driver GD due to the formation process of the organic encapsulation layer 620 may be prevented. That is, the display device according to the embodiment of the present specification can prevent a decrease in reliability due to the process of forming the organic encapsulation layer 620.

[0061] The dam 105 may include an insulating material. For example, the dam 105 may include an organic insulating material. The inorganic insulating layers, that is, the lower buffer layer 110, the lower gate insulating layer 121, the upper gate insulating layer 122, the isolation insulating layer 130, the upper buffer layer 140, the upper interlayer insulating layer 150, and the device protection layer 160, may extend outside the dam 105. At least one of the organic insulating layers, that is, the lower planarization layer 170, the upper planarization layer 180, and the bank insulating layer 190, may have an end portion located outside the dam 105. For example, the end of the upper planarization layer 180 and the end of the bank insulating layer 190 may be located outside the dam 105. The end of the lower planarization layer 170 may be covered by the upper planarization layer 180. A lower buffer layer 110, a lower gate insulating layer 121, an upper gate insulating layer 122, an isolation insulating layer 130, an upper buffer layer 140, an upper interlayer insulating layer 150, an element protection layer 160, an upper planarization layer 180, and a bank insulating layer 190 may be stacked between the bezel region BZ of the device substrate 100 and the dam 105. The dam 105 may be located on the bank insulating layer 190 in the bezel region BZ. For example, the dam 105 may be in direct contact with the upper surface of the bank insulating layer 190 facing the device substrate 100.

[0062] The edge of the upper planarization layer 180 may be covered by the bank insulating layer 190. The water vapor transmission rate (WVTR) of the bank insulating layer 190 may be lower than that of the upper planarization layer 180. Therefore, the display device according to the embodiment of the present disclosure may reduce the penetration of external moisture through the edge of the upper planarization layer 180 located outside the dam 105. A first inorganic sealing layer 610 and a second inorganic sealing layer 630 may be stacked on the edge of the bank insulating layer 190. For example, the first inorganic sealing layer 610 may be in direct contact with the edge of the bank insulating layer 190. The second inorganic sealing layer 630 may be in direct contact with the first inorganic sealing layer 610 outside the dam 105. Therefore, the display device according to the embodiment of the present disclosure may reduce the penetration of external moisture through the edge of the bank insulating layer 190 by the first inorganic sealing layer 610 and the second inorganic sealing layer 630.

[0063] Stoppers 101 and 103 may be located outside the bank insulating layer 190. The flow of the organic insulating layers, the lower planarization layer 170, the upper planarization layer 180, and the bank insulating layer 190, may be blocked by the stoppers 101 and 103. The stoppers 101 and 103 may include at least one middle stopper 101 and an outer stopper 103. The outer stopper 103 may be located outside the middle stopper 101. For example, the middle stopper 101 may be located between the dam 105 and the outer stopper 103. An end of the bank insulating layer 190 may be spaced apart from the middle stopper 101. For example, the end of the bank insulating layer 190 may be located between the dam 105 and the middle stopper 101.

[0064] The middle stopper 101 and the outer stopper 103 may be formed during the formation of the lower planarization layer 170, the upper planarization layer 180, and the bank insulating layer 190. For example, the middle stopper 101 may include the same material as the upper planarization layer 180. The thickness of the outer stopper 103 may be greater than the thickness of the middle stopper 101. The outer stopper 103 may have a multi-layer structure. For example, the outer stopper 103 may have a stacked structure including a first outer layer 103a including the same material as the upper planarization layer 180, a second outer layer 103b including the same material as the bank insulating layer 190, and a third outer layer 103c including the same material as the dam 105. The first outer layer 103a may be located on the same layer as the middle stopper 101. For example, the middle stopper 101 and the first outer layer 103a may be located on the device protection layer 160 in the bezel region BZ. Therefore, the display device according to the embodiment of the present specification can effectively control the flow of the lower planarization layer 170, the upper planarization layer 180, and the bank insulating layer 190.

[0065] A first supply line V1 and a second supply line V2 may be located between the device substrate 100 and the device protection layer 160 in the bezel region BZ. The power supply line PL may be electrically connected to the first supply line V1. For example, the first supply line V1 may supply a positive power supply voltage VDD. Therefore, the display device according to the embodiment of the present specification may maintain a constant positive power supply voltage VDD applied to each pixel region PA. The second supply line V2 may be insulated from the first supply line V1. The second electrode 530 of each pixel region PA may be electrically connected to the second supply line V2. For example, the second supply line V2 may supply a negative power supply voltage VSS. The second supply line V2 may be located outside the dam 105. For example, the second supply line V2 may include a region located between the middle stopper 101 and the outer stopper 103. The second electrode 530 of each pixel region PA may be electrically connected to the second supply line V2 between the middle stopper 101 and the outer stopper 103. Therefore, the display device according to the embodiment of the present specification can simplify the process of connecting the second electrode 530 of each pixel area PA to the second supply line V2.

[0066] The first supply line V1 and the second supply line V2 may include a conductive material. The first supply line V1 and the second supply line V2 may include a material having a relatively low resistance. For example, the first supply line V1 and the second supply line V2 may include a metal. The first supply line V1 and the second supply line V2 may be formed during the formation process of the driving circuit DC located in each pixel area PA. For example, the second supply line V2 may be located on the same layer as the first supply line V1. The second supply line V2 may be spaced apart from the first supply line V1. Therefore, the display device according to the embodiment of the present specification may prevent a decrease in process efficiency due to the formation process of the first supply line V1 and the second supply line V2.

[0067] The first supply line V1 and the second supply line V2 may be located on the same layer as the second drain electrode 225 of each pixel region PA. For example, the first supply line V1 and the second supply line V2 may be located between the upper interlayer insulating layer 150 and the device protection layer 160 in the bezel region BZ. The second supply line V2 may include the same material as the first supply line V1. For example, the first supply line V1 and the second supply line V2 may include the same material as the second drain electrode 225 of each pixel region PA. The second supply line V2 may be formed in the same process as the first supply line V1. For example, the first supply line V1 and the second supply line V2 may be formed simultaneously with the second drain electrode 225 of each pixel region PA.

[0068] A touch sensor Ts may be disposed on the encapsulating structure 600. The touch sensor Ts may detect a touch by a user and / or a tool. The touch sensor Ts may detect whether or not a touch by a user and / or a tool has occurred and the location of the touch using a self-capacitance method. For example, the touch sensor Ts may include a touch electrode 710 and a touch routing line 720.

[0069] The touch electrodes 710 may overlap the display area AA of the device substrate 100. For example, the touch electrodes 710 may be arranged side by side on the encapsulation structure 600 of the display area AA. The size of each touch electrode 710 may be larger than the size of each pixel area PA. For example, each touch electrode 710 may overlap multiple pixel areas PA. Each touch electrode 710 may overlap multiple light-emitting areas EA. The touch electrode 710 may include a conductive material. The touch electrode 710 may include a transparent material. For example, each touch electrode 710 may be a transparent electrode made of a transparent conductive material such as ITO or IZO. Therefore, the display device according to the embodiment of the present specification may increase the area capable of sensing a touch by a user and / or a tool. Therefore, the display device according to the embodiment of the present specification may improve reliability in sensing a touch by a user and / or a tool.

[0070] The touch electrodes 710 may be electrically connected to the pad areas PAD via the touch routing lines 720. Each touch electrode 710 may be electrically connected to one of the touch routing lines 720. For example, each touch routing line 720 may electrically connect one of the touch electrodes 710 to the pad areas PAD. The touch routing lines 720 may be connected to the touch electrodes 710 through two opposing sides of the display area AA. For example, each touch routing line 720 may be electrically connected to the corresponding touch electrode 710 through a second side A2 or a third side A3 of the display area AA.

[0071] The touch routing line 720 may include a conductive material. The touch routing line 720 may include a material different from that of the touch electrode 710. The touch routing line 720 may include a material having a relatively low resistance. For example, the touch routing line 720 may include a metal. The touch routing line 720 may be located outside the light-emitting area EA defined in each pixel area PA. For example, the touch routing line 720 may overlap the bank insulating layer 190. Therefore, the display device according to the embodiment of the present specification may prevent a decrease in light extraction efficiency due to the touch routing line 720.

[0072] The touch routing line 720 may be located on a different layer from the touch electrode 710. For example, a touch buffer layer 701 may be located on the encapsulation structure 600, the touch routing line 720 may be located on the touch buffer layer 701, and the touch electrode 710 may be located on a touch insulation layer 750 covering the touch routing line 720. The touch buffer layer 701 and the touch insulation layer 750 may include an insulating material. For example, the touch buffer layer 701 and the touch insulation layer 750 may include an inorganic insulating material and / or an organic insulating material. The touch insulation layer 750 may include a different material from the touch buffer layer 701. For example, the touch buffer layer 701 may be an inorganic insulating film made of an inorganic insulating material, and the touch insulation layer 750 may be an organic insulating film made of an organic insulating material. The touch buffer layer 701 may extend along the second inorganic encapsulation layer 630 to the outside of the outer stopper 103. The touch insulation layer 750 may be located within the display area AA. For example, the first inorganic encapsulation layer 610, the second inorganic encapsulation layer 630, and the touch buffer layer 701 may be stacked on the middle stopper 101 and the outer stopper 103. Therefore, the display device according to the embodiment of the present disclosure may prevent external moisture from penetrating through the touch insulation layer 750 including an organic insulating material. Therefore, the display device according to the embodiment of the present disclosure may prevent a change in resistance of the touch electrode 710 due to external moisture.

[0073] A touch protective layer 800 may be disposed on the touch sensor Ts. The touch protective layer 800 may prevent damage to the touch electrode 710 due to external impact and moisture. For example, the touch electrode 710 may be completely covered by the touch protective layer 800. The touch protective layer 800 may include an insulating material. For example, the touch protective layer 800 may include an inorganic insulating material and an organic insulating material. The touch protective layer 800 may have a multi-layer structure. As a result, the display device according to the embodiment of the present disclosure may effectively prevent damage to the touch electrode 710 due to external impact and moisture. The touch protective layer 800 may be disposed within the display area AA. For example, the touch protective layer 800 may not overlap the bezel area BZ. As a result, the display device according to the embodiment of the present disclosure may reduce bending stress due to bending in the bending area BA. That is, the display device according to the embodiment of the present disclosure may reduce cracks formed in the inorganic insulating layer due to bending stress.

[0074] Voltage lines VL1 and VL2 may be located outside the touch routing line 720. Each of the voltage lines VL1 and VL2 may supply a constant voltage. The voltage lines VL1 and VL2 may be electrically connected to the pad area PAD. For example, the voltage lines VL1 and VL2 may supply a negative power supply voltage VSS. The voltage lines VL1 and VL2 may include a conductive material. The voltage lines VL1 and VL2 may include a material with a relatively low resistance. For example, the voltage lines VL1 and VL2 may include a metal. The voltage lines VL1 and VL2 may be located on the touch buffer layer 701 in the bezel area BZ. For example, the voltage lines VL1 and VL2 may include the same material as the touch routing line 720. The voltage lines VL1 and VL2 may be located on the same layer as the touch routing line 720. The voltage lines VL1 and VL2 may be formed using the same process as the touch routing line 720. For example, the voltage lines VL1 and VL2 can be formed simultaneously with the touch routing line 720.

[0075] Each voltage line VL1, VL2 may extend along an edge of the display area AA. For example, the voltage lines VL1, VL2 may include a first voltage line VL1 located on the second side A2, the third side A3, and the fourth side A4 of the display area AA, and a second voltage line VL2 located between the first side A1 of the display area AA and the pad area PAD. The first voltage line VL1 and the second voltage line VL2 may include a region located parallel to the dam 105. For example, the first voltage line VL1 may include a region located between the second side A2 of the display area AA and the gate driver GD.

[0076] The second voltage line VL2 may include the same material as the first voltage line VL1. The second voltage line VL2 may be located on the same layer as the first voltage line VL1. The second voltage line VL2 may be formed in the same process as the first voltage line VL1. For example, the second voltage line VL2 may be formed simultaneously with the first voltage line VL1. Therefore, the display device according to the embodiment of the present disclosure may block the influence of an external signal on the signal of the touch electrode 710 and / or the touch routing line 720 by using the voltage lines VL1 and VL2. That is, the display device according to the embodiment of the present disclosure may prevent distortion of a signal for touch sensing due to an external signal. Therefore, the display device according to the embodiment of the present disclosure may improve the reliability of touch sensing.

[0077] 1, 4, and 6, the second voltage line VL2 may be spaced apart from the first voltage line VL1. The second voltage line VL2 may include a region located between the first side A1 of the display area AA and the dam 105. For example, a portion of the second voltage line VL2 may overlap the organic encapsulation layer 620. An opening VLg may be formed in the portion of the second voltage line VL2 that overlaps the organic encapsulation layer 620. That is, in the display device according to the embodiment of the present disclosure, a portion of the second voltage line VL2 that overlaps the organic encapsulation layer 620 may be partially disconnected. Therefore, the display device according to the embodiment of the present disclosure may quickly release noise due to an external signal to the pad area PAD.

[0078] A first pattern BP may be located between the dam 105 and the pad region PAD. The first pattern BP may be located on the touch buffer layer 701 in the bezel region BZ. The first pattern BP may overlap an edge of the bank insulating layer 190. For example, the first pattern BP may extend along the edge of the bank insulating layer 190 between the first side A1 of the display area AA and the pad region PAD. The first pattern BP may have a lower moisture vapor transmission rate (WVTR) than the first inorganic encapsulating layer 610, the second inorganic encapsulating layer 630, and the touch buffer layer 701. For example, the first pattern BP may include a conductive material. Therefore, in the display device according to the embodiment of the present specification, the first pattern BP can block cracks formed in the first inorganic encapsulating layer 610, the second inorganic encapsulating layer 630, and / or the touch buffer layer 701 located between the dam 105 and the pad region PAD due to step and / or bending stress of the bank insulating layer 190. Therefore, the display device according to the embodiment of the present disclosure may prevent external moisture from penetrating through cracks in the first inorganic encapsulation layer 610, the second inorganic encapsulation layer 630, and / or the touch buffer layer 701 located between the dam 105 and the pad region PAD by the first pattern BP. For example, the first pattern BP may function as a moisture-proof layer that blocks external moisture from penetrating through cracks in the inorganic insulating layer at the beginning of an organic insulating layer such as the upper planarization layer 180 and the bank insulating layer 190. That is, the display device according to the embodiment of the present disclosure may reduce deterioration of the light emitting element 500 due to the penetration of external moisture.

[0079] The opening VLg of the second voltage line VL2 may be located between the display area AA and the first pattern BP. Therefore, the display device according to the embodiment of the present disclosure can prevent penetration of an external signal through the opening VLg of the second voltage line VL2 by the first pattern BP. Therefore, the display device according to the embodiment of the present disclosure can prevent a decrease in reliability of touch sensing and effectively remove noise caused by external signals.

[0080] The first pattern BP may be located on the same layer as the second voltage line VL2. The first pattern BP may include the same material as the second voltage line VL2. The first pattern BP may be formed in the same process as the second voltage line VL2. For example, the first pattern BP may be formed simultaneously with the second voltage line VL2. The first pattern BP may include the same material as at least one of the touch electrode and the touch routing line. Therefore, the display device according to the embodiment of the present disclosure may prevent a decrease in process efficiency due to the formation of the first pattern BP. Therefore, the display device according to the embodiment of the present disclosure may minimize deterioration of the light emitting element 500 due to penetration of external moisture without a decrease in process efficiency.

[0081] 1 and 5, the first voltage line VL1 may overlap an edge of the bank insulating layer 190 on the second side A2, the third side A3, and the fourth side A4 of the display area AA. For example, the first voltage line VL1 may extend along the edge of the bank insulating layer 190 on the second side A2, the third side A3, and the fourth side A4 of the display area AA. That is, in the display device according to the embodiment of the present specification, a portion of the first voltage line VL1 located on the second side A2, the third side A3, and the fourth side A4 of the display area AA may function as the first pattern BP. Therefore, in the display device according to the embodiment of the present specification, the first voltage line VL1 may prevent external moisture from penetrating through cracks in the first inorganic encapsulating layer 610, the second inorganic encapsulating layer 630, and / or the touch buffer layer 701 located on the second side A2, the third side A3, and the fourth side A4 of the display area AA. Therefore, the display device according to the embodiment of the present specification can effectively prevent the degradation of the light emitting device 500 due to the penetration of external moisture.

[0082] As a result, the display device according to the embodiment of the present specification includes a light-emitting element 500 located on the upper planarization layer 180 in the display area AA, a bank insulating layer 190 defining the light-emitting area EA in which the light-emitting element 500 is located, an encapsulation structure 600 covering the light-emitting element 500, and a touch sensor Ts located on the encapsulation structure 600, wherein the bank insulating layer 190 covering the edge of the upper planarization layer 180 extends outside the dam 105 defining the formation area of ​​the organic encapsulation layer 620, a first voltage line VL1 and a first pattern BP overlapping the edge of the bank insulating layer 190 are located on the touch buffer film 701, and the first voltage line VL1 and the first pattern BP made of the same material as the touch routing line 720 of the touch sensor Ts may extend along the edge of the bank insulating layer 190. Therefore, in the display device according to the embodiment of the present disclosure, cracks in the first inorganic encapsulation layer 610, the second inorganic encapsulation layer 630, and / or the touch buffer film 701 stacked on the end of the bank insulating layer 190 can be covered by the first voltage line VL1 or the first pattern BP. That is, in the display device according to the embodiment of the present disclosure, the first voltage line VL1 and the first pattern BP can prevent penetration of external moisture through cracks formed in the first inorganic encapsulation layer 610, the second inorganic encapsulation layer 630, and / or the touch buffer layer 701. Therefore, the display device according to the embodiment of the present disclosure can reduce deterioration of the light emitting device 500 due to penetration of external moisture. Furthermore, the display device according to the embodiment of the present disclosure can extend the life of the light emitting device 500.

[0083] In the display device according to the embodiment of the present specification, the driving circuit DC of each pixel area PA includes a first thin film transistor TR1, a second thin film transistor TR2, and a storage capacitor Cst. However, in the display device according to other embodiments of the present specification, the driving circuit DC of each pixel area PA may include a driving transistor and at least one switching transistor. For example, in the display device according to other embodiments of the present specification, the driving circuit DC of each pixel area PA may further include a third thin film transistor for initializing the storage capacitor Cst of the pixel area PA in response to a gate signal. The third thin film transistor of each pixel area PA may include a third semiconductor pattern, a third gate electrode, a third drain electrode, and a third source electrode. The third semiconductor pattern of each pixel area PA may include a semiconductor material. The third gate electrode of each pixel area PA may be electrically connected to the corresponding gate line GL. The third drain electrode of each pixel area PA may be electrically connected to an initialization line that applies an initialization signal. The third source electrode of each pixel area PA may be electrically connected to the storage capacitor Cst of the pixel area PA. Therefore, the display device according to other embodiments of the present specification may improve the flexibility in the configuration of the driving circuit DC located in each pixel area PA.

[0084] In the display device according to the embodiment of the present specification, the first drain electrode 215, the first source electrode 217, the second drain electrode 225, and the second source electrode 227 of each drive circuit DC may have different positions and electrical connections depending on the configuration of the drive circuit DC and / or the type of the thin film transistors TR1 and TR2. For example, in the display device according to the other embodiment of the present specification, the second gate electrode 223 of each drive circuit DC may be electrically connected to the first drain electrode 215 of the drive circuit DC. Therefore, the display device according to the other embodiment of the present specification can improve the flexibility in the configuration of each drive circuit DC and the type of each thin film transistor TR1 and TR2.

[0085] In the display device according to the embodiment of the present specification, the first pattern BP is located between the opening VLg of the second voltage line VL2 and the pad area PAD. However, in the display device according to the other embodiment of the present specification, the first pattern BP may be omitted. For example, referring to FIG. 7 , which schematically illustrates a plan view of a display device according to the other embodiment of the present specification, a portion of the second voltage line VL2 may be located between the dam 105 and the pad area PAD. A portion of the second voltage line VL2 located between the dam 105 and the pad area PAD may overlap an end of the bank insulating layer 190. That is, in the display device according to the other embodiment of the present specification, a portion of the second voltage line VL2 may function as the first pattern. A portion of the second voltage line VL2 located between the first side of the display area AA and the dam 105 may extend in the opposite direction to a portion of the second voltage line VL2 located between the dam 105 and the pad area PAD. For example, a portion of the second voltage line VL2 located between the first side of the display area AA and the dam 105 may cross between the display area AA and a portion of the second voltage line VL2 located between the dam 105 and the pad area PAD. Therefore, a display device according to another embodiment of the present specification may have greater flexibility in determining a method for preventing external moisture from penetrating through cracks in the first inorganic encapsulation layer 610, the second inorganic encapsulation layer 630, and / or the touch buffer layer 701 located between the first side of the display area AA and the pad area PAD.

[0086] A display device according to another embodiment of the present disclosure may prevent cracks from propagating in a direction parallel to the first pattern BP. FIG. 8 is a partially enlarged view of the periphery of the first pattern BP of a display device according to another embodiment of the present disclosure. FIG. 9 is a cross-sectional view taken along line III-III in FIG. 8. FIG. 10 is a cross-sectional view taken along line IV-IV in FIG. 8. Referring to FIGS. 8 to 10, a display device according to another embodiment of the present disclosure may include at least one second pattern CP located outside the dam 105. The second pattern CP may intersect with the first pattern BP. The second pattern CP may be located on a different layer from the first pattern BP. For example, one end of the second pattern CP may be located between the device protection layer 160 and the first inorganic encapsulation layer 610 in the bezel region BZ, and the other end of the second pattern CP may be located between the device protection layer 160 and the bank insulating layer 190 in the bezel region BZ. 10 , in a display device according to another embodiment of the present disclosure, a portion of the first inorganic encapsulation layer 610, a portion of the second inorganic encapsulation layer 630, and a portion of the touch buffer layer 701 overlapping with the first pattern BP may have an uneven shape. That is, in a display device according to another embodiment of the present disclosure, cracks propagating in a direction parallel to the first pattern BP may be blocked by the uneven shape formed by the second pattern CP. For example, the second pattern CP may function as a crack blocking layer that blocks cracks propagating along edges of organic insulating layers such as the upper planarization layer 180 and the bank insulating film 190. Therefore, a display device according to another embodiment of the present disclosure may effectively prevent external moisture from penetrating through cracks formed in the first inorganic encapsulation layer 610, the second inorganic encapsulation layer 630, and / or the touch buffer layer 701.

[0087] FIG. 11 is a partially enlarged view of the periphery of a first pattern BP of a display device according to another embodiment of the present disclosure. FIG. 12 is a cross-sectional view taken along line VV in FIG. 11. Referring to FIGS. 11 and 12, a display device according to another embodiment of the present disclosure may include a dummy layer AP located between an upper planarization film 180 and a bank insulating layer 190. The dummy layer AP may have a lower moisture permeability than the bank insulating layer 190. The dummy layer AP may be formed in the same process as the layer located between the upper planarization film 180 and the bank insulating layer 190 in the display area AA. For example, the dummy layer AP may include the same material as the first electrode of the light-emitting element located in each pixel region. The dummy layer AP may be formed in the same process as the first electrode of the light-emitting element located in each pixel region. For example, the dummy layer AP may be formed simultaneously with the first electrode of the light-emitting element located in each pixel region.

[0088] An edge of the upper planarization film 180 may be covered by a dummy layer AP. For example, the dummy layer AP may include a region located between the device protection layer 160 and the bank insulating layer 190 in the bezel region BZ. An edge of the dummy layer AP may be covered by the first inorganic encapsulation layer 610. Therefore, the display device according to another embodiment of the present specification may prevent external moisture from penetrating through the edge of the upper planarization layer 180 by the dummy layer AP. That is, the display device according to another embodiment of the present specification may block external moisture penetrating through cracks in the first inorganic encapsulation layer 610, the second inorganic encapsulation layer 630, and / or the touch buffer layer 701 by the first pattern BP and the dummy layer AP. Therefore, the display device according to another embodiment of the present specification may effectively prevent external moisture from penetrating through cracks in the first inorganic encapsulation layer 610, the second inorganic encapsulation layer 630, and / or the touch buffer layer 701.

[0089] In the display device according to the embodiment of the present specification, the second side A2, the third side A3, and the fourth side A4 of the display area AA are completely blocked by the first voltage line VL1. However, in the display device according to the other embodiment of the present specification, a portion of the first voltage line VL1 may be disconnected. For example, referring to FIG. 13, which schematically illustrates a plan view of a display device according to the other embodiment of the present specification, the first voltage line VL1 may include an opening VLg1. In the display device according to the other embodiment of the present specification, the first pattern BP1 may be located between the opening of the second voltage line VL2 and the pad area PAD, and the opening VLg1 of the first voltage line VL1 may be located between the second pattern BP2 and the dam 105. The second pattern BP2 may overlap an edge of the bank insulating layer. The second pattern BP2 may extend parallel to the dam 105. For example, the second pattern BP2 may extend along the edge of the bank insulating layer on one side of the display area AA where the opening VLg1 of the first voltage line VL1 is located. Therefore, in the display device according to another embodiment of the present specification, noise generated in the first voltage line VL1 by an external signal is quickly released to the pad area PAD, and the second pattern BP2 blocks the penetration of noise through the opening VLg1 of the first voltage line VL1, thereby effectively preventing the penetration of external moisture through cracks in the first inorganic sealing layer 610, the second inorganic sealing layer 630 and / or the touch buffer layer 701 located on one side of the display area AA where the opening VLg1 of the first voltage line VL1 is located.

[0090] The display device according to an embodiment of the present disclosure is described as having a self-capacitance type touch sensor Ts located on the encapsulation structure 600. However, display devices according to other embodiments of the present disclosure may use various types of touch sensors Ts. The display device according to other embodiments of the present disclosure may detect a touch by a user and / or a tool through a change in mutual capacitance. FIG. 14 is a plan view of a touch sensor Ts of a display device according to another embodiment of the present disclosure. FIG. 15 is an enlarged view of region R in FIG. 14. FIG. 16 is a cross-section taken along line VI-VI in FIG. 15. FIG. 17 is a cross-sectional view of the periphery of a first pattern BP of a display device according to another embodiment of the present disclosure. Referring to FIGS. 14 to 17, in the display device according to another embodiment of the present disclosure, the touch sensor Ts may include a driving touch line 910 and a sensing touch line 920.

[0091] A touch drive signal may be applied to the drive touch line 910. For example, each drive touch line 910 may include a first touch electrode 911 and a first bridge electrode 912. The first bridge electrode 912 may electrically connect the first touch electrodes 911. For example, each drive touch line 910 may include the first touch electrode 911 connected to one side by the first bridge electrode 912.

[0092] A touch sensing signal may be applied to the sensing touch line 920. For example, each sensing touch line 920 may include a second touch electrode 921 and a second bridge electrode 922. The second bridge electrode 922 may electrically connect the second touch electrodes 921. The second touch electrode 921 may be connected in a direction different from that of the first touch electrode 911. For example, the connection direction of the second touch electrode 921 by the second bridge electrode 922 may be perpendicular to the connection direction of the first touch electrode 911 by the first bridge electrode 912.

[0093] The second touch electrode 921 may be located on the same layer as the first touch electrode 911. The second touch electrode 921 may be located between the first touch electrodes 911. For example, the first touch electrode 911 and the second touch electrode 921 may be offset from each other. Each second bridge electrode 922 may cross one of the first bridge electrodes 912. The first bridge electrode 912 may be located on the same layer as the first touch electrode 911. The second bridge electrode 922 may be located on a different layer from the second touch electrode 921. For example, the touch buffer layer 901 may be located on the second inorganic encapsulation layer 630, the second bridge electrode 922 may be located on the touch buffer layer 901, and the first touch electrode 911, the first bridge electrode 912, and the second touch electrode 921 may be located on a touch insulation layer 950 that covers the second bridge electrode 922. Each second touch electrode 921 may penetrate the touch insulation layer 950 to directly contact the corresponding second bridge electrode 922.

[0094] The first touch electrode 911, the first bridge electrode 912, the second touch electrode 921, and the second bridge electrode 922 may include a conductive material. The first touch electrode 911, the first bridge electrode 912, the second touch electrode 921, and the second bridge electrode 922 may include a material having a relatively low resistance. For example, the first touch electrode 911, the first bridge electrode 912, the second touch electrode 921, and the second bridge electrode 922 may include a metal such as copper (Cu), molybdenum (Mo), titanium (Ti), or tantalum (Ta). The first touch electrode 911, the first bridge electrode 912, the second touch electrode 921, and the second bridge electrode 922 may be located outside the light-emitting area EA defined in each pixel area PA. For example, the first touch electrode 911, the first bridge electrode 912, the second touch electrode 921, and the second bridge electrode 922 may overlap the bank insulating layer 190. Each of the first touch electrode 911, the first bridge electrode 912, the second touch electrode 921, and the second bridge electrode 922 may have a mesh-shaped plane. Therefore, a display device according to another embodiment of the present disclosure may prevent a decrease in light extraction efficiency due to the first touch electrode 911, the first bridge electrode 912, the second touch electrode 921, and the second bridge electrode 922.

[0095] In the display device according to the embodiment of the present specification, the voltage lines VL1, VL2 and the first pattern BP are described as having a single-layer structure. However, in the display device according to other embodiments of the present specification, the voltage lines VL1, VL2 and / or the first pattern BP may have a multi-layer structure. For example, as shown in Figures 16 and 17, in the display device according to other embodiments of the present specification, the second voltage line VL2 may have a stacked structure of a lower supply layer LC and an upper supply layer UC, and the upper supply layer UC may be electrically connected to the lower supply layer LC. Therefore, the display device according to other embodiments of the present specification may reduce the resistance of the second voltage line VL2.

[0096] The touch insulating layer 950 may extend along the touch buffer layer 901 to the outside of the outer stopper 103. The lower supply layer LC may be located on the same layer as the second bridge electrode 922. For example, the lower supply layer LC may be located between the touch buffer layer 901 and the touch insulating layer 950 in the bezel region BZ. The lower supply layer LC may include the same material as the second bridge electrode 922. The lower supply layer LC may be formed in the same process as the second bridge electrode 922. For example, the lower supply layer LC may be formed simultaneously with the second bridge electrode 922. The upper supply layer UC may be located on the same layer as the first bridge electrode 912. For example, the upper supply layer UC may be located on the touch insulating layer 950 in the bezel region BZ. The upper supply layer UC may include the same material as the first bridge electrode 912. The upper supply layer UC may be formed in the same process as the first bridge electrode 912. For example, the upper supply layer UC may be formed simultaneously with the first bridge electrode 912. Therefore, the display device according to another embodiment of the present specification can prevent a decrease in process efficiency due to the formation of the lower supply layer LC and the upper supply layer UC.

[0097] The first pattern BP may have a stacked structure of a lower prevention layer B1 and an upper prevention layer B2. The upper prevention layer B2 may be located on the lower prevention layer B1. The upper prevention layer B2 may overlap the lower prevention layer B1. For example, each of the lower prevention layer B1 and the upper prevention layer B2 may include an area overlapping an edge of the bank insulating layer 190. Therefore, the display device according to another embodiment of the present specification can prevent external moisture from permeating through cracks in the first inorganic encapsulation layer 610, the second inorganic encapsulation layer 630, and / or the touch buffer layer 901 stacked on the edge of the bank insulating layer 190 by the lower prevention layer B1 and the upper prevention layer B2. Therefore, the display device according to another embodiment of the present specification can effectively prevent external moisture from permeating through cracks in the first inorganic encapsulation layer 610, the second inorganic encapsulation layer 630, and / or the touch buffer layer 901.

[0098] The lower preventing layer B1 may be located on the same layer as the lower supply layer LC. For example, the lower preventing layer B1 may be located between the touch buffer layer 901 and the touch insulating layer 950 in the bezel region BZ. The lower preventing layer B1 may include the same material as the lower supply layer LC. The lower preventing layer B1 may be formed in the same process as the lower supply layer LC. For example, the lower preventing layer B1 may be formed simultaneously with the lower supply layer LC. The upper preventing layer B2 may be located on the same layer as the upper supply layer UC. For example, the upper preventing layer B2 may be located on the touch insulating layer 950 in the bezel region BZ. The upper preventing layer B2 may include the same material as the upper supply layer UC. The upper preventing layer B2 may be formed in the same process as the upper supply layer UC. For example, the upper preventing layer B2 may be formed simultaneously with the upper supply layer UC. The upper preventing layer B2 may include a different material from the lower preventing layer B1. Therefore, display devices according to other embodiments of the present specification can prevent a decrease in process efficiency due to the formation of the lower preventing layer B1 and the upper preventing layer B2.

[0099] The upper prevention layer B2 may be insulated from the lower prevention layer B1. For example, the surface of the lower prevention layer B1 may be completely covered with the touch insulating layer 950. Therefore, the display device according to another embodiment of the present specification may prevent external moisture from penetrating through the contact holes for electrical connection between the lower prevention layer B1 and the upper prevention layer B2. Therefore, the display device according to another embodiment of the present specification may effectively prevent degradation of the light emitting element due to penetration of external moisture.

[0100] In a display device according to another embodiment of the present disclosure, the first pattern BP may extend along the inclined side surface of the bank insulating layer 190. The first pattern BP may overlap at least a portion of an organic insulating layer, such as the bank insulating layer 190. The inorganic encapsulation layers 610 and 630 may have characteristic variations depending on their cross-sectional shapes. For example, the inorganic encapsulation layers 610 and 630 in the flat region may have a different density from the inorganic encapsulation layers 610 and 630 in the inclined region. Therefore, in a display device according to another embodiment of the present disclosure, cracks, such as seams, that occur in the inorganic encapsulation layers 610 and 630 in the inclined region may be covered with the first pattern BP. For example, as shown in FIG. 18 , which illustrates a cross section around the first pattern BP of a display device according to another embodiment of the present disclosure, in a display device according to another embodiment of the present disclosure, a portion of the touch buffer layer 701 located between the dam 105 and the edge of the bank insulating layer 190 may be in direct contact with the first pattern BP. That is, the display device according to the other embodiments of the present specification can effectively block the penetration of external moisture through cracks that occur in the inorganic insulating layers 610, 630, and 701 due to steps between the upper planarization layer 180 and the bank insulating layer 190 in the bezel region BZ and cracks that occur due to characteristic deviations of the inorganic insulating layers 610, 630, and 701. Furthermore, the display device according to the other embodiments of the present specification can block the penetration of external moisture in the region where an organic insulating layer, such as the bank insulating layer 190, begins in the bezel region BZ by using the first pattern BP. Therefore, the display device according to the other embodiments of the present specification can significantly reduce degradation of light emitting elements due to the penetration of external moisture. [Explanation of symbols]

[0101] 100 Element substrate 105 Dam 170 Lower planarization layer 180 Top planarization layer 190 Bank insulating layer 500 light-emitting elements 610 First inorganic sealing layer 630 Second inorganic sealing layer 710 Touch Routing Line 720 Touch Electrode VL1 First voltage line VL2 Second voltage line BP 1st Pattern

Claims

1. a dam located on the element substrate and surrounding a display area; an organic encapsulation layer located within the area defined by the dam; a first inorganic sealing layer located between the element substrate and the organic sealing layer and extending along a surface of the dam; a second inorganic sealing layer positioned on the organic sealing layer and positioned on the first inorganic sealing layer outside the dam; an organic insulating layer located between the element substrate and the first inorganic sealing layer, the organic insulating layer including an end located outside the dam; a first pattern located on the second inorganic sealing layer and on the edge of the organic insulating layer; The first pattern overlaps at least a portion of the organic insulating layer.

2. The display device of claim 1 , wherein the first pattern has a moisture permeability lower than that of the first inorganic sealing layer and the second inorganic sealing layer.

3. The display device of claim 1 , wherein the first pattern comprises a conductive material.

4. further comprising a pad area located outside the dam; the end of the organic insulating layer is located between the dam and the pad region; The display device of claim 3 , wherein the first pattern is electrically connected to the pad area.

5. a second pattern located outside the dam and intersecting the first pattern; The display device of claim 1 , wherein the second pattern is located between the element substrate and the second inorganic sealing layer.

6. The display device of claim 5 , wherein the second pattern includes a first end portion located between the element substrate and the first inorganic sealing layer, and a second end portion located between the element substrate and the organic insulating layer.

7. a touch sensor located on the second inorganic sealing layer; a pad area located outside the dam, the touch sensor includes a touch electrode overlapping the display area and a touch routing line electrically connecting the touch electrode to the pad area; The display device of claim 1 , wherein the first pattern includes the same material as at least one of the touch electrode and the touch routing line.

8. The display device of claim 7 , wherein the touch routing lines are located on a different layer from the touch electrodes.

9. a touch insulating layer disposed between the touch electrode and the touch routing line; The display device of claim 7 , wherein the first pattern has a stacked structure of a lower insulating layer located between the second inorganic encapsulation layer and the touch insulating layer and an upper insulating layer located on the touch insulating layer.

10. The display device of claim 9 , wherein the upper protective layer comprises a different material from the lower protective layer.

11. an element substrate including a bezel region located outside a display region; a first organic insulating layer located on the display area and extending over the bezel area; a first inorganic sealing layer located on the first organic insulating layer and extending outside the first organic insulating layer; a dam located between the first organic insulating layer and the first inorganic sealing layer in the bezel region; an organic sealing layer located on the first inorganic sealing layer in the display area and surrounded by the dam; a second inorganic sealing layer located on the organic sealing layer and the dam and in contact with the first inorganic sealing layer outside the dam; a first pattern located on the second inorganic sealing layer and parallel to the dam; The first pattern overlaps an edge of the first organic insulating layer.

12. The display device of claim 11 , wherein the first pattern contacts the second inorganic encapsulation layer.

13. a second organic insulating layer located between the display region of the element substrate and the first organic insulating layer; a dummy layer located between the first organic insulating layer and the second organic insulating layer, The display device of claim 11 , wherein the dummy layer includes a region located outside the second organic insulating layer and between the element substrate and the first organic insulating layer.

14. The display device further includes a light-emitting element located between the second organic insulating layer and the first inorganic sealing layer in the display area, the first organic insulating layer defines a light-emitting region in which the light-emitting element is located within the display region; The display device of claim 13 , wherein the dummy layer includes the same material as the first electrode of the light-emitting element.

15. a voltage line located outside the dam and extending along an edge of the display area; the voltage line includes an opening located on one side of the display area; The display device of claim 11 , wherein the opening of the voltage line is located between the display area and the first pattern.

16. the first pattern extends along a surface of the second inorganic sealing layer in a direction toward the dam; the first organic insulating layer includes an inclined side surface located between the dam and the end of the first organic insulating layer; The display device of claim 11 , wherein the inclined side surface of the first organic insulating layer overlaps the first pattern.

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