Semiconductor module and vehicle

Abstract

To improve the reliability of a semiconductor module that uses leads as wiring members that connect electrodes of a semiconductor element to other conductors.SOLUTION: A semiconductor module (1) includes: a wiring board (2); semiconductor elements (3C, 3D) that are arranged on a conductor pattern (202) of the wiring board and are connected to the conductor pattern; and a wiring member (6B) that electrically connects electrodes provided on a surface of the semiconductor element opposite to the conductor pattern to other conductors. The wiring member includes a first conductor spacer (601), a second conductor spacer (602), and a laminate (610) in which multiple conductor foils are stacked and arranged to connect the conductor spacers to each other. The multiple conductor foils include at least one intermediate conductor foil (630), and a first conductor foil (620A) and a second conductor foil (620B) that are stacked with the intermediate conductor foil sandwiched between them. The intermediate conductor foil has a gap forming portion (651) that forms a gap (650) between the first conductor foil and the second conductor foil.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] The present invention relates to a semiconductor module and a vehicle. [Background technology]

[0002] Some semiconductor modules, in which semiconductor elements are sealed with insulating materials, are provided with plate-shaped wiring members called leads (for example, Patent Documents 1 to 9). The leads are used to connect the electrodes of the semiconductor elements to the electrodes of other semiconductor elements or to other conductive members. The leads are joined to conductors such as the electrodes of the semiconductor elements with a joining material such as solder. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2018-61066 [Patent Document 2] International Publication No. 2018 / 142863 [Patent Document 3] Japanese Patent Application Laid-Open No. 2003-188328 [Patent Document 4] International Publication No. 2020 / 255663 [Patent Document 5] Japanese Patent Publication No. 2021-108369 [Patent Document 6] Japanese Patent Application Publication No. 9-115965 [Patent Document 7] Japanese Patent Application Publication No. 7-288269 [Patent Document 8] U.S. Patent Publication No. 2008-0246130 [Patent Document 9] Japanese Patent Application Laid-Open No. 2016-92346 Summary of the Invention [Problem to be solved by the invention]

[0004] When connecting leads to conductors, such as electrodes of semiconductor elements, with a bonding material, deviations in the relative positions of the leads and conductors during the bonding process can cause variations in the shape of the bonding material for each semiconductor module. Such variations in the shape of the bonding material can be a factor in reducing the reliability of the semiconductor module.

[0005] One object of the present invention is to improve the reliability of a semiconductor module that uses leads as wiring members for connecting electrodes of a semiconductor element to other conductors. [Means for solving the problem]

[0006] According to one embodiment, the semiconductor module includes a wiring board having an insulating substrate and a conductor pattern disposed on a first surface of the insulating substrate, a semiconductor element disposed on the conductor pattern of the wiring board and connected to the conductor pattern, and a wiring member electrically connecting an electrode provided on a surface of the semiconductor element opposite the conductor pattern to another conductor. The wiring member includes a first conductor spacer bonded to the electrode of the semiconductor element, a second conductor spacer bonded to the other conductor, and a laminate including multiple conductor foils connected to the first conductor spacer and the second conductor spacer at different distances from the surface of the semiconductor element on which the electrode is formed. Each of the multiple conductor foils of the laminate has a first connection region that is a connection region with the first conductor spacer, a second connection region that is a connection region with the second conductor spacer, and a linking region between the first connection region and the second connection region. The plurality of conductor foils include at least one intermediate conductor foil, and a first conductor foil and a second conductor foil stacked on either side of the at least one intermediate conductor foil, and the intermediate conductor foil has a gap forming portion that forms a gap between the connecting region of the first conductor foil and the connecting region of the second conductor foil. [Effects of the Invention]

[0007] According to the above-described aspect, it is possible to improve the reliability of a semiconductor module that uses leads as wiring members. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a plan view of a semiconductor module according to an embodiment; [Figure 2] FIG. 2 is a cross-sectional view taken along line AA' in FIG. [Figure 3] 2 is an equivalent circuit diagram of an inverter circuit formed in the semiconductor module of FIG. 1. [Figure 4] FIG. 2 is an exploded perspective view illustrating a first configuration example of a wiring member. [Figure 5] 5A is a plan view of the wiring member illustrated in FIG. 4, and FIG. 5B is a cross-sectional view taken along line BB' in FIG. 5A. [Figure 6] FIG. 6A is a cross-sectional view illustrating a connection process for connecting an emitter electrode of a semiconductor element with a wiring member, FIG. 6B is a cross-sectional view illustrating an example of warping that occurs in a wiring board, and FIG. 6C is a cross-sectional view illustrating an example of warping of a wiring member. [Figure 7] FIG. 7A is a plan view illustrating a second configuration example of the wiring member, and FIG. 7B is a cross-sectional view taken along line CC' in FIG. 7A. [Figure 8] FIG. 10 is an exploded perspective view illustrating a third configuration example of the wiring member. [Figure 9] 9A is a plan view of the wiring member illustrated in FIG. 8, and FIG. 9B is a cross-sectional view taken along line DD' in FIG. 9A. [Figure 10] FIG. 10A is a plan view illustrating a fourth configuration example of the wiring member, and FIG. 10B is a view of the wiring member in FIG. 10A as seen from the arrow E. As shown in FIG. [Figure 11] FIG. 11A is a front view illustrating a fifth configuration example of the wiring member, and FIG. 11B is a front view illustrating a sixth configuration example of the wiring member. [Figure 12] FIG. 12A is a plan view illustrating a seventh configuration example of the wiring member, and FIG. 12B is a plan view illustrating an eighth configuration example of the wiring member. [Figure 13] 1 is a schematic plan view showing an example of a vehicle to which a semiconductor module according to an embodiment is applied; DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the following description, a "semiconductor module" refers to a semiconductor element, which may also be called a semiconductor chip or die, sealed with an insulating material. The semiconductor module may also be called a "semiconductor device."

[0010] The X-axis, Y-axis, and Z-axis in the drawings are shown for the purpose of defining planes and directions in the illustrated semiconductor module, etc. The X-axis, Y-axis, and Z-axis are perpendicular to each other and form a right-handed system. In the following description, the direction parallel to the X-axis is referred to as the X-direction, the direction parallel to the Y-axis is referred to as the Y-direction, and the direction parallel to the Z-axis is referred to as the Z-direction. Furthermore, when each of the X-axis, Y-axis, and Z-axis directions is associated with the direction of the arrows (positive and negative) of the X-axis, Y-axis, and Z-axis shown in the drawings, it is referred to as the "positive side" or "negative side."

[0011] In this specification, the Z direction may be referred to as the vertical direction or the stacking direction. In this specification, "upper" and "above" refer to the positive side of the Z direction relative to a reference surface, component, position, etc., and "lower" and "belower" refer to the negative side of the Z direction relative to a reference surface, component, position, etc. For example, when describing "component B being placed on component A," component B is placed on the positive side of component A in the Z direction. Furthermore, when describing "the top surface of component A," this surface includes the surface located at the end of component A on the positive side of the Z direction and facing the positive side of the Z direction. These directions and surfaces associated with these directions are terms used for convenience of explanation, and their correspondence with the X-axis, Y-axis, and Z-axis directions may change depending on the mounting orientation of the semiconductor module, etc. For example, in this specification, the surface of a semiconductor element facing the wiring board is referred to as the bottom surface, and the surface opposite the bottom surface is referred to as the top surface. However, this is not limited thereto; the surface facing the wiring board may be referred to as the top surface, and the surface opposite the top surface may be referred to as the bottom surface.

[0012] The aspect ratios and relative sizes of components in each diagram are merely schematic representations and do not necessarily correspond to the relationships in an actually manufactured semiconductor module. For the sake of convenience, the relative sizes of components may be exaggerated or may differ from the external shapes of components used in an actual semiconductor module. Furthermore, for the sake of convenience, some cross-sectional views show the cross-sectional configuration of a semiconductor module cut along an imaginary cutting line that cannot be accurately shown in a plan view.

[0013] In this specification, the terms "not shown," "not shown," "not shown," and the like are intended to indicate without using a specific reference symbol or a leading line which part in the figure corresponds to the component to which the term is attached. For example, "first main electrode not shown" indicates both that a part (e.g., a shape, a line, etc.) representing the first main electrode is not shown in the figure, and that there is no reference symbol or leading line clearly indicating the part corresponding to the first main electrode in the figure. Furthermore, an underlined reference symbol in the figure indicates that the reference symbol refers to the entire component, including multiple parts distinguished by multiple reference symbols.

[0014] The semiconductor module exemplified in the following description may be applied to a power conversion device such as an inverter device for industrial or electrical equipment (e.g., an in-vehicle motor). For this reason, the following description will omit detailed descriptions of configurations, functions, operations, manufacturing methods, etc. that are identical to or similar to those of known semiconductor modules.

[0015] Fig. 1 is a plan view of a semiconductor module according to an embodiment, Fig. 2 is a cross-sectional view taken along line AA' in Fig. 1, and Fig. 3 is an equivalent circuit diagram of an inverter circuit formed in the semiconductor module of Fig. 1.

[0016] The semiconductor module 1 illustrated in Figures 1 and 2 includes a wiring board 2, semiconductor elements 3A-3D, leads 5A-5C, wiring members 6A and 6B, bonding wires 7A-7D, a case 8, a sealing material (not shown), and a heat sink 9. In this specification, when multiple identical components are to be distinguished from one another, a reference symbol consisting of a number followed by an alphabetic character is used; when no distinction is required, only the number is used. For example, when referring to a specific semiconductor element among the four semiconductor elements 3A-3D, the reference symbol (any of 3A-3D) assigned to that specific semiconductor element in the drawings is used; otherwise, the element is simply referred to as "semiconductor element 3."

[0017] The wiring board 2 is an element-mounting component on which a semiconductor element 3 is mounted. The semiconductor element 3 includes, for example, a switching element 310 and a diode element 311 connected in anti-parallel to the switching element 310, as shown in Fig. 3. The semiconductor element 3 may be, for example, an RC (Reverse Conducting)-IGBT element that integrates the function of an FWD (Free Wheeling Diode) element, which is an example of the diode element 311, with an IGBT (Insulated Gate Bipolar Transistor) element, which is the switching element 310.

[0018] Wiring board 2 includes insulating substrate 200, conductor patterns 201-203 arranged on the upper surface of insulating substrate 200, and heat dissipation pattern 209 arranged on the lower surface of insulating substrate 200. Wiring board 2 may be, but is not limited to, a DCB (Direct Copper Bonding) substrate or an AMB (Active Metal Brazing) substrate.

[0019] The insulating substrate 200 may be a ceramic substrate formed from a ceramic material such as aluminum oxide (Al2O3), aluminum nitride (AlN), silicon nitride (Si3N4), or a composite material of aluminum oxide (Al2O3) and zirconium oxide (ZrO2). The insulating substrate 200 may be a substrate formed by molding an insulating resin such as epoxy resin into a sheet, a substrate formed by impregnating a base material such as glass fiber with an insulating resin, or a substrate formed by coating the surface of a flat metal core with an insulating resin.

[0020] Conductive patterns 201-203 arranged on the upper surface of insulating substrate 200 are used as wiring members in electronic circuits such as an inverter circuit formed within semiconductor module 1. Heat dissipation pattern 209 arranged on the lower surface of insulating substrate 200 is used as a thermally conductive member that conducts heat generated by semiconductor elements 3 to heat sink 9 during operation of semiconductor module 1. Conductive patterns 201-203 and heat dissipation pattern 209 are formed from, for example, a metal plate or metal foil made of copper, aluminum, or the like.

[0021] The wiring board 2 is disposed on the upper surface of the heat sink 9 together with the case 8. The case 8 includes a frame-shaped insulating member 800 having openings on the upper and lower surfaces, and a plurality of terminals 801-805 integrated with the insulating member 800. The insulating member 800 of the case 8 can accommodate the wiring board 2, the semiconductor element 3, the leads 5, the wiring member 6, the bonding wires 7, etc. when disposed on the upper surface of the heat sink 9, and can have a shape that defines a space that can be filled with a sealing material (insulating material) to seal them. The heat sink 9 may be a metal plate made of, for example, copper or aluminum. The heat dissipation pattern 209 of the wiring board 2 is connected to the upper surface of the heat sink 9 so as to be in close contact with the upper surface of the heat sink 9 by a bonding material such as solder, or a thermally conductive material such as thermal grease or thermal compound (not shown). The heat sink 9 may have a plurality of fins on its lower surface. The heat sink 9 may be a part of the cooler 10 or a component connected to the cooler 10. That is, the cooler 10 is an optional component in the semiconductor module 1 of this embodiment.

[0022] The terminals 801 to 805 of the case 8 are roughly divided into main terminals 801 to 803 and control terminals 804 and 805. The main terminals 801 to 803 and the control terminals 804 and 805 have inner terminal portions exposed to the space in which the wiring board 2, the semiconductor element 3, etc. are housed, and outer terminal portions exposed to the outside of the semiconductor module 1.

[0023] The main terminals 801 to 803 are electrically connected to electrodes that pass a main current through a switching element (e.g., an IGBT element) in the semiconductor element 3. In the case of the semiconductor module 1 having the inverter circuit illustrated in FIG. 3 formed therein, the first main terminal 801 is a P terminal connected to the positive electrode of a DC power supply for obtaining (outputting) AC, and is electrically connected to collector electrodes (not shown) of the semiconductor elements 3A and 3B arranged on the upper surface of the first conductor pattern 201 of the wiring board 2. The second main terminal 802 is an N terminal connected to the negative electrode of the DC power supply, and is electrically connected to emitter electrodes 301 of the semiconductor elements 3C and 3D arranged on the upper surface of the second conductor pattern 202 of the wiring board 2. The third main terminal 803 is an M terminal connected to a load that consumes AC converted from DC by the semiconductor module 1, and is electrically connected to the emitter electrode 301 of the semiconductor element 3 arranged on the upper surface of the first conductor pattern 201 and the collector electrode (not shown) of the semiconductor element 3 arranged on the upper surface of the second conductor pattern 202.

[0024] The control terminal 804 is electrically connected to the gate electrode 302 of the semiconductor element 3 arranged on the upper surface of the first conductor pattern 201, and the control terminal 805 is connected to the gate electrode 302 of the semiconductor element 3 arranged on the upper surface of the second conductor pattern 202.

[0025] The case 8 may be provided with additional terminals other than the main terminals 801 to 803 and the control terminals 804 and 805. For example, the case 8 may be provided with a first additional control terminal electrically connected to the emitter electrode 301 of the semiconductor element 3 arranged on the upper surface of the first conductor pattern 201, and a second additional control terminal electrically connected to the emitter electrode 301 of the semiconductor element 3 arranged on the upper surface of the second conductor pattern 202. These additional control terminals are terminals for connecting the emitter electrode 301 of the semiconductor element 3 to a gate drive circuit (not shown) connected to the gate electrode 302 of the semiconductor element 3, and are called auxiliary emitter terminals, sense-emitter terminals, emitter-sense terminals, etc. The gate drive circuit is a circuit that generates control signals for controlling the on / off of the switching element of the semiconductor element 3 using the emitter potential input via the additional control terminal as ground and applies the control signals to the gate electrode 302 of the semiconductor element 3.

[0026] Semiconductor elements 3A and 3B arranged on first conductor pattern 201 of wiring board 2 have collector electrodes (not shown) on their lower surfaces, which are joined to first conductor pattern 201 by a bonding material (not shown) such as solder. First conductor pattern 201 is electrically connected to first main terminal 801 via first lead 5A. First lead 5A is a wiring member formed by bending a metal plate such as a copper plate, and is joined to first main terminal 801 and first conductor pattern 201 by a bonding material (not shown) such as solder. Emitter electrodes 301 arranged on the upper surfaces of semiconductor elements 3A and 3B are electrically connected to first conductor block 212 arranged on the upper surface of second conductor pattern 202 via first wiring member 6A (described later). First conductor block 212 is joined to second conductor pattern 202 by a bonding material (not shown) such as solder. The second conductor pattern 202 is electrically connected to the third main terminal 803 via the second lead 5B. The second lead 5B is a wiring member formed by bending a metal plate such as a copper plate, and is joined to the second conductor pattern 202 and the third main terminal 803 by a joining material (not shown) such as solder. The gate electrodes 302 provided on the upper surfaces of the semiconductor elements 3A and 3B are electrically connected to the inner terminal portions of the control terminal 804 by bonding wires 7A and 7B.

[0027] Semiconductor elements 3C and 3D arranged on second conductor pattern 202 of wiring board 2 have collector electrodes (not shown) on their lower surfaces, which are joined to second conductor pattern 202 by a bonding material (not shown) such as solder. Emitter electrodes 301 arranged on the upper surfaces of semiconductor elements 3C and 3D are electrically connected to second conductor block 213 arranged on the upper surface of third conductor pattern 203 of wiring board 2 via second wiring member 6B (described later). Second conductor block 213 is joined to third conductor pattern 203 by a bonding material (not shown) such as solder. Third conductor pattern 203 is electrically connected to second main terminal 802 via third lead 5C. Third lead 5C is a wiring member formed by bending a metal plate such as a copper plate, and is joined to third conductor pattern 203 and second main terminal 802 by a bonding material (not shown) such as solder. Gate electrodes 302 provided on the upper surfaces of semiconductor elements 3C and 3D are electrically connected to inner terminal portions of control terminals 805 by bonding wires 7C and 7D.

[0028] Fig. 4 is an exploded perspective view illustrating a first configuration example of a wiring member. Fig. 5A is a plan view of the wiring member illustrated in Fig. 4, and Fig. 5B is a cross-sectional view taken along line B-B' in Fig. 5A. The wiring member 6 illustrated in Figs. 4, 5A, and 5B may be the first wiring member 6A and second wiring member 6B described above.

[0029] The illustrated wiring member 6 includes three conductive spacers 601 to 603 and a laminate 610 connecting the conductive spacers 601 to 603. The conductive spacers 601 to 603 are, for example, plate-shaped or block-shaped metal members such as copper plates or copper blocks. The laminate 610 is formed by stacking conductive foils such as copper foils. While FIGS. 4 and 5B illustrate a three-layer laminate 610 in which a second-shape conductive foil 630 is placed between two first-shape conductive foils 620A and 620B, the number and types of conductive foils to be stacked are not limited thereto.

[0030] The first conductive spacer 601 and the second conductive spacer 602 are disposed on the emitter electrode 301 of the semiconductor element 3 and are bonded to the emitter electrode 301 with a bonding material (not shown) such as solder. In the case of the second wiring member 6B, as illustrated in FIG. 2, the first conductive spacer 601 is bonded to the emitter electrode of the semiconductor element 3C, and the second conductive spacer 602 is bonded to the emitter electrode of the semiconductor element 3D. The third conductive spacer 603 is disposed on the opposite side of the first conductive spacer 601 from the second conductive spacer 602 and is connected to a conductor other than the emitter electrode of the semiconductor element 3. In the case of the second wiring member 6B, the third conductive spacer 603 is bonded to a second conductive block 213 disposed on the third conductive pattern 203 of the wiring board 2 with a bonding material (not shown) such as solder. As will be described later, the second conductive block 213 and the first conductive block 212 may be omitted.

[0031] The laminate 610 includes a first-shape conductor foil 620A, a second-shape conductor foil 630, and a first-shape conductor foil 620B stacked in this order. The three conductor foils 620A, 630, and 620B are stacked and arranged so that when the first conductor spacer 601 and the second conductor spacer 602 are joined to the emitter electrode 301 of the semiconductor element 3, the distances from the emitter electrode 301 are different from one another. In other words, the three conductor foils 620A, 630, and 620B are stacked and arranged on the surface (upper surface) of the first conductor spacer 601 opposite to the surface (lower surface) that faces the emitter electrode 301 of the semiconductor element 3, so that the distances from the upper surface of the first conductor spacer 601 are different from one another. The conductor foils 620A, 630, and 620B are each formed by punching a conductor foil such as a copper foil having a thickness T of about 100 μm. The laminate 610 may be formed by stacking at least three conductor foils. The thickness T of the conductor foils is not limited to a specific thickness. Conductor foils of different thicknesses may be stacked. For example, the thickness of the second-shaped conductor foil 630 placed between the two first-shaped conductor foils 620A, 620B may be thicker than the thicknesses of the first-shaped conductor foils 620A, 620B. The number of conductor foils to be stacked may be changed depending on the total thickness of the laminate 610 that satisfies the electrical characteristic requirements of the semiconductor module 1 and the thickness T of each conductor foil.

[0032] Each of the conductive foils 620A, 630, and 620B of the laminate 610 has a first connection region, a second connection region, a third connection region, and a first coupling region and a second coupling region. The first connection regions 621, 631, and 621 of the conductive foils 620A, 630, and 620B are connection regions with the first conductive spacer 601 and have a planar shape that overlaps with the upper surface of the first conductive spacer 601 in a planar view of the upper surface (XY plane) of the first conductive spacer 601. The second connection regions 622, 632, and 622 of the conductive foils 620A, 630, and 620B are connection regions with the second conductive spacer 602 and have a planar shape that overlaps with the upper surface of the second conductive spacer 602 in a planar view of the upper surface (XY plane) of the second conductive spacer 602. The third connection regions 623, 633, 623 of the conductor foils 620A, 630, 620B are connection regions with the third conductor spacer 603, and have a planar shape that overlaps with the upper surface of the third conductor spacer 603 in a plan view of the upper surface (XY plane) of the third conductor spacer 603. In the laminate 610 illustrated in Fig. 5A, the first connection region 611 is overlapped by the first connection regions 621, 631, 621 of the conductor foils 620A, 630, 620B, and the second connection region 612 is overlapped by the second connection regions 622, 632, 622 of the conductor foils 620A, 630, 620B.

[0033] The first connection regions 624, 634, 624 of the conductor foils 620A, 630, 620B are regions that connect the first connection regions 621, 631, 621 and the second connection regions 622, 632, 622. The second connection regions 625, 635, 625 of the conductor foils 620A, 630, 620B are regions that connect the first connection regions 621, 631, 621 and the third connection regions 623, 633, 623. The conductor foil 630 of the second shape disposed between the conductor foils 620A, 620B of the first shape is provided with openings 650 that form voids within each connection region in the laminate 610 in the first connection region 634 and the second connection region 635. The opening 650 is a spatial region surrounded by a wall surface 651 that connects the opening end on the upper surface and the opening end on the lower surface of the conductor foil 630. The first connection regions 624 and the second connection regions 625 of the conductor foils 620A, 620B of the first shape illustrated in FIGS. 4, 5A, and 5B have a planar shape that does not overlap the conductor foil 630 through the opening region (opening 650) within the connection region of the second conductor foil 630 in plan view. That is, in the laminate 610 illustrated in FIG. 5A, the first connection regions 614 of the conductor foils 620A, 630, 620B are laminated such that the first connection regions of the adjacent conductor foils in the lamination direction do not contact each other. Note that the two conductor foils disposed sandwiching the conductor foil 630 of the second shape are not limited to a combination of conductor foils of the same shape as illustrated in FIG. 4, and may be a combination of conductor foils of different shapes.

[0034] In the laminate 610 illustrated in FIG. 5A, the conductor foil 630 of the second shape has an outer shape that is a strip shape with a width (dimension in the X direction) W0 in plan view, and openings 650 with a width W21 (<W0) are provided in the first connection region 634 and the second connection region 635 such that the distance from the end in the width direction of the second conductor foil 630 is W22. The first connection region 624 of the conductor foils 620A, 620B of the first shape is formed in a strip shape that is narrower in width than the first connection region 621 and the second connection region 622 such that the width W1 is W21 > W1 in plan view and the distance W3 from the end in the width direction of each conductor foil 620 is W3 > W22.

[0035] In the first configuration example of the wiring member 6, the relationship between the width W21 (dimension in the X direction) of the opening 650 formed in the first connection region 634 of the conductor foil 630 having the second shape and the width W1 of the first connection region 624 of the conductor foils 620A and 620B having the first shape is not limited to the relationship of W21>W1 as illustrated in FIG. 5A. The relationship between the width W21 and the width W1 may be W21 = W1, or may be W21<W1 as long as it does not inhibit the deformation of the laminate 600 described later. Also, in the first configuration example of the wiring member 6, the relationship between the length L2 (dimension in the Y direction) of the opening 650 formed in the first connection region 634 of the conductor foil 630 having the second shape and the length L1 of the first connection region 624 of the conductor foils 620A and 620B having the first shape is not limited to the relationship of L2>L1 as illustrated in FIG. 5A. The relationship between the length L2 and the length L1 may be L2≦L1.

[0036] The laminated conductor foils 620A, 630, and 620B are joined to the upper surfaces of the conductor spacers 601 to 603 by a joining material (not shown) such as solder or by laser welding, for example, so that the connection regions overlapping each other are joined. That is, in the connection region (for example, connection regions 611 and 612 in FIG. 5A) of the laminate 610 of the wiring member 6 that overlaps the conductor spacer in plan view, the connection regions of the laminated conductor foils are joined to regulate the change in the relative position of the conductor foils, and in the connection region (for example, connection region 614 in FIG. 5A), the change in the relative position of the laminated conductor foils is allowed. In other words, the laminate 610 allows the plurality of laminated conductor foils to deform separately within the connection region.

[0037] FIG. 6A is a cross-sectional view for explaining a connection process of connecting an emitter electrode of a semiconductor element with a wiring member. FIG. 6B is a cross-sectional view for explaining an example of warpage occurring in a wiring board. FIG. 6C is a cross-sectional view for explaining an example of warpage of a wiring member. The cross-sectional views of FIGS. 6A to 6C can be partial enlarged cross-sectional views obtained by enlarging a portion corresponding to the cross-section taken along line B-B' in FIG. 5A in the cross-sectional view of the semiconductor module 1 in FIG. 2.

[0038] The manufacturing process of the semiconductor module 1 described above includes a bonding process in which conductors are bonded to each other using a bonding material such as solder. In the bonding process, for example, bonding between the conductor pattern of the wiring board 2 and the collector electrode of the semiconductor element 3, and bonding between the emitter electrode 301 of the semiconductor element 3 and the wiring member 6 are performed simultaneously. In the bonding process, as illustrated in FIG. 6A, bonding materials (solder) 11A and 11B and semiconductor elements 3C and 3D are arranged in this order on the second conductor pattern 202 of the wiring board 2, bonding materials (solder) 11C and 11D and wiring member 6B are arranged in this order on the emitter electrodes (not shown) of the semiconductor elements 3C and 3D, and then the bonding materials 11A to 11D are heated and melted. In the bonding process, bonding material (solder), a semiconductor element, bonding material (solder), and wiring member 6A are arranged in this order on the first conductor pattern 201 of the wiring board 2 and bonded in the same manner.

[0039] When bonding materials 11A-11D are heated, surrounding wiring board 2, wiring member 6B, etc. are also heated and expand. The linear expansion coefficient of the ceramic material used for insulating substrate 200 of wiring board 2 is, for example, about 3-7 ppm / °C, and the linear expansion coefficient of copper used for conductor patterns 201-203 is about 17 ppm / °C. For this reason, when bonding materials 11A-11D are heated, warping of wiring board 2 may occur, for example, as shown in FIG. 6B.

[0040] The plurality of stacked conductor foils 620A, 630, 620B in the wiring member 6B described above have a connection region where the conductor foils are not joined to each other and allow each conductor foil to deform independently between connection regions that overlap the upper surfaces of the conductor spacers 601-603 arranged on the emitter electrodes of the semiconductor element 3. Furthermore, in the connection region of the laminate 610, a gap is formed between the two first-shape conductor foils 620A, 620B due to the opening 650 in the second-shape conductor foil 630. Therefore, when the wiring board 2 warps, the wiring member 6B deforms such that the first connection region 624 of the conductor foil 620A and the first connection region 624 of the conductor foil 620B enter the opening 650 in the conductor foil 630, thereby following the warpage of the wiring board 2, as illustrated in FIG.

[0041] That is, the wiring member 6 of the first configuration example described above has higher flexibility (flexibility) than when a lead formed of a single copper plate having the same thickness as the laminate 610 is used, as described in Patent Documents 1, 2, and 8, and flexibly deforms according to the magnitude of warpage occurring in the wiring board 2. Furthermore, the two adjacent conductor foils in the wiring member 6 of the first configuration example described above include an area within the connection region of one conductor foil that does not contact the portion within the connection region of the other conductor foil. Therefore, the wiring member 6 has higher flexibility (flexibility) than when a laminate is used, as described in Patent Documents 3, 4, 6, and 7, for example, in which the entire connection region of each conductor foil is in contact with the connection region of the adjacent conductor foil, and flexibly deforms according to the magnitude of warpage occurring in the wiring board 2. When using leads formed from a single copper plate, or a laminate in which the entire connecting area of ​​each conductor foil is in contact with the connecting area of ​​an adjacent conductor foil, the wiring member 6 cannot follow the warping of the wiring board 2, and, for example, variations may occur in the shapes of the bonding materials on the emitter electrodes of multiple semiconductor elements 3 connected by the wiring member 6, or the bonding materials connecting the wiring board and the collector electrodes of the semiconductor elements 3 (i.e., the shapes of each bonding material may become uneven).

[0042] In contrast, with the wiring member 6 of the first configuration example, even if warping occurs in the wiring board 2 during the bonding process, it is possible to suppress variation in shape (i.e., non-uniform shape) between the bonding materials 11C and 11D that bond the conductive spacers 601 and 602 of the wiring member 6 to the emitter electrodes of the semiconductor elements 3C and 3D. This makes it possible to suppress variation in the electrical characteristics of each semiconductor module 1 that is caused by variation in the shape of the bonding material. Furthermore, it is possible to suppress stress concentration in the bonding material during use of the semiconductor module 1 that is caused by variation, thereby improving reliability.

[0043] Furthermore, for example, in semiconductor module 1, warping occurs in wiring board 2 due to heat generated by semiconductor element 3 during operation. In this case, too, the connecting region of wiring member 6 deforms in response to the warping of wiring board 2, thereby reducing stress applied to the joints between conductive spacers 601 and 602 and the emitter electrodes of semiconductor elements 3C and 3D, for example, and improving reliability.

[0044] Fig. 7A is a plan view illustrating a second configuration example of the wiring member, and Fig. 7B is a cross-sectional view taken along line CC' in Fig. 7A. Note that Fig. 7B illustrates only the cross-sectional configuration of a portion of the laminate 610 of the wiring member 6. The wiring member 6 illustrated in Figs. 7A and 7B may be the wiring members 6A and 6B illustrated in Figs. 1 and 2.

[0045] 7A and 7B has a five-layer structure in which three first-shape conductor foils 620A to 620C and two second-shape conductor foils 630A and 630B are alternately laminated. Openings 650 are formed in connecting regions 634 and 635 (see FIG. 4) of the second-shape conductor foils 630A and 630B.

[0046] On the other hand, the first-shape conductor foil 620 in the wiring member 6 of the second configuration example has a first connection region (first connection portion) 624 that passes through an opening region (opening 650) of the second-shape conductor foil 630 in a plan view, and a second connection portion 641 and a third connection portion 642 that overlap with respective ends of the conductor foil 630 in the width direction (X direction) in a plan view and connect the first connection region 621 and the second connection region 622. The width W4 of the second connection portion 641 and the third connection portion 642 is not limited to a specific width, but is preferably narrower than the width W1 of the first connection region (first connection portion) 624 to reduce the overlapping area with the second-shape conductor foil 630. That is, the first-shape conductor foil 620 in the wiring member 6 of the second configuration example has an opening 652 surrounded by a wall surface 653 and an opening 654 surrounded by a wall surface 655 formed in the connection region.

[0047] In such a wiring member 6, the second connecting portion 641 and the third connecting portion 642 of the conductor foil 620B disposed between the two second-shape conductor foils 630A, 630B serve as walls, and a gap is formed by the openings 652, 654 between the conductor foils 630A, 630B. This makes it possible to prevent a sealing material (insulating resin) from entering the gap (openings 652, 654) formed between the second-shape conductor foils 630A, 630B in a sealing step performed after the joining step, for example. Furthermore, in the wiring member 6 of the second configuration example, by setting the width W21 (see FIG. 5A ) of the opening 650 of the second-shape conductor foil 630 and the width W1 of the first connecting region 624 of the first-shape conductor foils 620A and 620B to be W21≈W1, it is possible to prevent the sealing material (insulating resin) from entering the opening 650 of the conductor foil 630 through the gap between the opening 650 of the conductor foil 630 and the first connecting region 624 of the conductor foil 620. By leaving the gap formed by the opening 650 of the second-shape conductor foil 630 and the gap formed by the openings 652 and 654 of the first-shape conductor foil 620 after the sealing process, the effect of allowing the connecting regions of each conductor foil to deform independently is maintained. That is, the wiring member 6 of the second configuration example prevents the flexibility (flexibility) of the wiring member 6 from being reduced due to the sealing material (insulating resin) filling the gaps.

[0048] Fig. 8 is an exploded perspective view illustrating a third configuration example of the wiring member. Fig. 9A is a plan view of the wiring member illustrated in Fig. 8, and Fig. 9B is a cross-sectional view taken along line DD' in Fig. 9A. The wiring member 6 illustrated in Figs. 8, 9A, and 9B may be the wiring members 6A and 6B illustrated in Figs. 1 and 2.

[0049] 8 includes a three-layer laminate 610 in which a second-shape conductor foil 630 having an opening region (opening 650) in a coupling region is disposed between a pair of flat conductor foils 670A and 670B. In other words, the coupling region of the laminate 610 in the wiring member 6 of the third configuration example can be said to be a cylindrical shape having a hollow portion with an axial direction extending from a connection end connected to one conductor spacer (e.g., the first conductor spacer 601) toward a connection end connected to the other conductor spacer (e.g., the second conductor spacer 602). In this example, as shown in FIGS. 9A and 9B, it is preferable that the widthwise (X-direction) dimension W21 of the opening 650 of the second-shape conductor foil 630 be increased to reduce the contact area between the conductor foils 670A and 670B in the coupling region. In the wiring member 6 of the third configuration example, the relationship between the width dimension W21 of the opening 650 in the connecting region of the second-shape conductor foil 630 and the width W5 of the connecting portion (not shown) at the end in the width direction is not limited to a specific relationship. In the semiconductor module 1 used as a power converter and operating at high frequency as exemplified in this specification, the current flowing through the laminate 610 in which the second-shape conductor foil 630 is disposed between a pair of flat conductor foils 670A and 670B is concentrated on the surface of the laminate 610 (particularly, the upper surface of the conductor foil 670A and the lower surface of the conductor foil 670B) due to the skin effect. Therefore, the width W5 of the connecting portion in the connecting region of the conductor foil 630 may be large enough to maintain the shape of the conductor foil 630, for example. In this case, the thickness T2 of the conductor foil 630 illustrated in FIG. 9B may be large enough to prevent the connecting regions of the upper and lower conductor foils 670A and 670B from contacting each other within the opening 650 of the conductor foil 630. That is, the relationship between the thickness T2 of the conductor foil 630 and the thickness T1 of the conductor foils 670A and 670B may be T2=T1.

[0050] The laminate 610 in the wiring member 6 of the third configuration example may be formed by stacking a plurality of conductor foils having the same planar shape as the conductor foil 630 of the second shape between upper and lower conductor foils 670A and 670B.

[0051] Fig. 10A is a plan view illustrating a fourth configuration example of the wiring member, and Fig. 10B is a view of the wiring member in Fig. 10A as seen from the arrow E. The wiring member 6 illustrated in Figs. 10A and 10B may be the wiring members 6A and 6B illustrated in Figs. 1 and 2.

[0052] The shapes of the conductive spacers 601 to 603 in the wiring member 6 according to this embodiment can be modified as appropriate. The conductive spacers 601 and 602 in the wiring member 6 according to the fourth configuration example shown in FIGS. 10A and 10B are rectangular parallelepipeds whose lower surfaces, which are bonded to the emitter electrodes 301 of the semiconductor elements 3C and 3D, have an area smaller than the area of ​​the upper surface of the emitter electrodes 301. Specifically, the rectangular parallelepipeds are shown as being half the area of ​​the lower surfaces. In the wiring member 6 according to the fourth configuration example shown in FIGS. 10A and 10B, the areas of the first connection region 611 and the second connection region 612 can be reduced by the reduced areas of the lower and upper surfaces of the conductive spacers 601 and 602, thereby lengthening the linking region 614 between the connection regions. The wiring member 6 according to the fourth configuration example may include a region where a gap formed in the linking region 614 in the laminate 610 overlaps with the emitter electrode 301 of the semiconductor element 3 in a plan view. That is, the wiring member 6 of the fourth configuration example can have higher flexibility (flexibility) by expanding the opening 650 of the second-shaped conductor foil 630 so that a portion of the opening 650 overlaps the emitter electrode 301 of the semiconductor element 3 in a plan view. Note that the relationship between the planar shapes of the conductor spacers 601 and 602 and the planar shape of the emitter electrode 301, the position of the conductor spacer on the emitter electrode 301, and the like are not limited to a specific relationship or position.

[0053] Fig. 11A is a front view illustrating a fifth configuration example of the wiring member, and Fig. 11B is a front view illustrating a sixth configuration example of the wiring member. The front views of Fig. 11A and Fig. 11B correspond to views seen from the arrow E in Fig. 10A. The wiring member 6 illustrated in Fig. 11A and Fig. 11B may be the wiring members 6A and 6B illustrated in Figs. 1 and 2.

[0054] In the semiconductor module 1 illustrated in FIGS. 1 and 2, the third conductive spacer 603 of the wiring member 6 is bonded to a conductive block disposed on the conductive pattern of the wiring board 2 using a bonding material. However, in the semiconductor module 1 according to this embodiment, for example, as illustrated in FIG. 11A, the height H2 of the third conductive spacer 603 of the wiring member 6 may be greater than the height H1 of the first conductive spacer 601 and the second conductive spacer 602, and the third conductive spacer 603 may be directly bonded to the conductive pattern 203 of the wiring board 2 using a bonding material. Note that the relationship between the height (thickness) HC of the semiconductor elements 3C and 3D to which the first conductive spacer 601 and the second conductive spacer 602 are connected and the height H1 of the first conductive spacer 601 and the second conductive spacer 602 is not limited to a specific relationship. The relationship H1 > HC, which is the opposite of the relationship illustrated in FIG. 11, may also be used.

[0055] Furthermore, as shown in FIG. 11B, the wiring member 6 may have conductive spacers 601 to 603 with a height H1, and the connecting region between the connection region with the first conductive spacer 601 in the laminate 610 and the connection region with the third conductive spacer 603 may be bent, so that the third conductive spacer 603 and the conductive pattern 203 of the wiring board 2 are directly bonded with a bonding material.

[0056] Fig. 12A is a plan view illustrating a seventh configuration example of the wiring member, and Fig. 12B is a plan view illustrating an eighth configuration example of the wiring member. The wiring member 6 illustrated in Figs. 12A and 12B may be the wiring members 6A and 6B illustrated in Figs. 1 and 2.

[0057] 12A shows a wiring member 6 in which the planar shape of the laminate 610 is L-shaped. With respect to each conductor foil of the laminate 610 in the wiring member 6 of the seventh configuration example illustrated in FIG. 12A, when viewed from the first connection region 611, the second connection region 612 is located on the negative side in the X direction, and the third connection region 613 is located on the negative side in the Y direction. In a first connection region 614 connecting the first connection region 611 and the second connection region 612, a connection region 624 of the first shape conductor foils 620A, 620B that passes through an opening (a region surrounded by a wall surface 651) in the connection region of the second shape conductor foil 630 extends in the direction from the first connection region toward the second connection region (X direction). In the second connection region 615 connecting the first connection region 611 and the third connection region 613, the connection region 624 of the first shape conductor foils 620A, 620B passing through the opening (the region surrounded by the wall surface 651) of the connection region of the second shape conductor foil 630 extends in the direction from the first connection region toward the third connection region (Y direction).

[0058] That is, the planar shape of wiring member 6 according to the present embodiment can be changed as appropriate depending on the layout of multiple conductors connected by one wiring member 6. For example, when the X direction and Y direction are the directions in which the end sides of wiring board 2 of semiconductor module 1 extend, wiring member 6 of the seventh configuration example in Fig. 12A can be applied to connecting emitter electrodes of semiconductor elements 3 that are arranged at positions corresponding to second connection region 612 and third connection region 613 on the upper surface of wiring board 2.

[0059] Furthermore, laminate 610 of wiring member 6 may have four or more connection regions. For example, in FIG. 12B , four semiconductor elements 3E, 3F, 3G, and 3H are arranged on second conductor pattern 202 of wiring board 2. Semiconductor elements 3E and 3F function as switching elements such as IGBT elements, and semiconductor elements 3G and 3H may function as diode elements such as FWD elements. Laminate 610 in wiring member 6 of the eighth configuration example illustrated in FIG. 12B has first connection region 611 overlapping emitter electrode 301 of semiconductor element 3E, second connection region 612 overlapping emitter electrode 301 of semiconductor element 3F, and third connection region 613 overlapping a conductor pattern other than second conductor pattern 202 (not shown). Furthermore, the laminate 610 in the wiring member 6 of the eighth configuration example has a fourth connection region 616 overlapping with the anode electrode of the semiconductor element 3G, a fifth connection region 617 overlapping with the anode electrode of the semiconductor element 3H, a third linking region 618 linking the first connection region 611 and the fourth connection region 616, and a fourth linking region 619 linking the second connection region 612 and the fifth connection region 617. Although omitted in Fig. 12B, the above-mentioned voids are formed in each of the linking regions 614, 615, 618, and 619 of the laminate 610.

[0060] As described above, the wiring member 6 according to the present embodiment allows the planar shape of the laminate 610 to be freely changed depending on the number and arrangement of conductors connected by the wiring member 6. Furthermore, the above-described wiring member 6 is not limited to a member that connects the emitter electrode 301 of the semiconductor element 3 to a conductor on the wiring board 2 (e.g., a conductor pattern or a conductor block on a conductor pattern, etc.), but may also be used as a member that connects, for example, a conductor pattern on the wiring board 2 to a main terminal of the case 8. Furthermore, the planar shape of the intermediate conductor foil disposed between two conductor foils in the laminate 610 is not limited to a shape having a rectangular opening 650 like the second-shape conductor foil 630 described above with reference to FIG. 4 etc.

[0061] The switching elements in the semiconductor module 1 described above with reference to FIGS. 1 to 3 are not limited to IGBT elements, and may be configured, for example, as power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), BJTs (Bipolar Junction Transistors), etc. When the switching elements are power MOSFETs, the electrode on the bottom surface of the semiconductor element 3 may be called the drain electrode, and the electrode on the top surface may be called the source electrode. Furthermore, the diode elements connected in anti-parallel to the switching elements may be configured, for example, as SBDs (Schottky Barrier Diodes), JBS (Junction Barrier Schottky) diodes, MPS (Merged PN Schottky) diodes, PN diodes, etc.

[0062] Although the semiconductor module 1 of the above-described embodiment is not limited to a specific application, the semiconductor module 1 equipped with the cooler 10 is particularly suitable for use in high-temperature environments. For example, the semiconductor module 1 of the above-described embodiment can be applied to a power conversion device such as an inverter device for an in-vehicle motor. A vehicle to which the semiconductor module 1 according to the present invention is applied will be described with reference to FIG. 13.

[0063] Fig. 13 is a plan view schematically illustrating an example of a vehicle to which a semiconductor module according to an embodiment is applied. Vehicle 1501 shown in Fig. 13 is, for example, a four-wheeled vehicle having four wheels 1502. Vehicle 1501 may be, for example, an electric vehicle in which the wheels are driven by a motor or the like, or a hybrid vehicle that uses power from an internal combustion engine in addition to a motor. Furthermore, vehicles to which semiconductor module 1 is applied are not limited to four-wheeled vehicles, and may also be motorcycles, railroad cars, etc.

[0064] Vehicle 1501 includes a drive unit 1503 that applies power to wheels 1502, and a control device 1504 that controls drive unit 1503. Drive unit 1503 may be configured with at least one of an engine, a motor, or a hybrid of an engine and a motor, for example.

[0065] The control device 1504 controls (e.g., controls power) the drive unit 1503. The control device 1504 includes a semiconductor module 1 including the cooler 10 according to the embodiment described above. The semiconductor module 1 can be configured to control power to the drive unit 1503.

[0066] The semiconductor module 1 according to the above-described embodiment may be applied to industrial power conversion devices, such as inverter devices for driving motors in elevators, escalators, building air conditioning systems, etc. Furthermore, the circuit formed in the semiconductor module 1 is not limited to the half-bridge inverter circuit illustrated in FIG. 3 . The circuit formed in the semiconductor module 1 may, for example, include only the upper arm (the circuit portion between the first main terminal 801 and the third main terminal 803) or the lower arm (the circuit portion between the third main terminal 803 and the second main terminal 802) of the half-bridge circuit in FIG. 3 , or may include multiple (e.g., three) half-bridge inverter circuits. The circuit formed in the semiconductor module 1 may also be a full-bridge inverter circuit. Furthermore, the circuit formed in the semiconductor module 1 is not limited to a power conversion circuit that converts direct current to alternating current, but may be another circuit, or may include a power conversion circuit and another circuit.

[0067] The features of the above-described embodiment will be summarized below. The semiconductor module according to the above-described embodiment includes a wiring board having an insulating substrate and a conductor pattern arranged on a first surface of the insulating substrate, a semiconductor element arranged on the conductor pattern of the wiring board and connected to the conductor pattern, and a wiring member that electrically connects electrodes provided on a surface of the semiconductor element opposite to the conductor pattern to other conductors, the wiring member including a first conductor spacer bonded to the electrodes of the semiconductor element, a second conductor spacer bonded to the other conductor, and a plurality of conductor foils connecting the first conductor spacer and the second conductor spacer, on which the electrodes of the semiconductor element are formed. and a laminate in which the plurality of conductor foils are stacked and arranged so that the distances from the surface where the conductor foils are stacked are different from each other, and each of the plurality of conductor foils of the laminate has a first connection region which is a connection region with the first conductor spacer, a second connection region which is a connection region with the second conductor spacer, and a connection region between the first connection region and the second connection region, and the plurality of conductor foils include at least one intermediate conductor foil, and a first conductor foil and a second conductor foil which are stacked and arranged with the at least one intermediate conductor foil sandwiched therebetween, and the intermediate conductor foil has a gap forming portion which forms a gap between the connection region of the first conductor foil and the connection region of the second conductor foil.

[0068] In the semiconductor module of the above embodiment, the laminate is cylindrical, having a gap formed by the gap-forming portion of the intermediate conductor foil, extending at least from the boundary between the first connection region and the connecting region to the boundary between the second connection region and the connecting region.

[0069] In the semiconductor module of the above embodiment, each of the multiple conductor foils of the laminate has a planar shape in a planar view of the surface on which the electrodes of the semiconductor element are formed, such that adjacent conductor foils do not overlap with each other, at least in the region within the connection region excluding the ends of the connection region.

[0070] In the semiconductor module according to the above embodiment, the void-forming portion of the intermediate conductor foil is an opening that provides an opening region within the connection region in which the surface facing the first conductor foil and the surface facing the second conductor foil are open, and the first conductor foil has a connecting portion within the connection region that connects the first connection region and the second connection region, which passes over the opening region of the intermediate conductor foil in a planar view and does not overlap with the intermediate conductor foil.

[0071] In the semiconductor module of the above embodiment, the first conductor foil has an additional connecting portion within the connecting region that, in the planar view, overlaps with a widthwise end portion of the intermediate conductor foil that is perpendicular to the connecting direction connecting the first connection region and the second connection region in the connecting region.

[0072] In the semiconductor module according to the above embodiment, a portion of the opening region of the intermediate conductor foil overlaps the electrode of the semiconductor element in a plan view of the surface on which the electrode of the semiconductor element is formed.

[0073] In the semiconductor module according to the above embodiment, the first conductor foil and the second conductor foil have the same planar shape in a plan view of the surface of the semiconductor element on which the electrodes are formed.

[0074] The semiconductor module according to the above embodiment further includes an additional semiconductor element arranged on the conductor pattern or another conductor pattern of the wiring board and connected to the conductor pattern or the other conductor pattern, and the other conductor joined to the second conductor spacer of the wiring member is an electrode of the additional semiconductor element.

[0075] In the semiconductor module according to the above embodiment, the second conductor spacer of the wiring member is electrically connected to a conductor pattern different from the conductor pattern of the wiring board.

[0076] The semiconductor module according to the above embodiment further includes a case member having leads electrically connected to the second conductive spacers of the wiring member.

[0077] In the semiconductor module according to the above embodiment, the wiring member further includes a third conductive spacer, and each of the plurality of conductor foils of the laminate has a third connection region that is a connection region with the third conductive spacer and a second connecting region between the first connection region and the third connection region, and the intermediate conductor foil has a second gap forming portion that forms a gap between the second connecting region of the first conductor foil and the second connecting region of the second conductor foil.

[0078] In the semiconductor module according to the above embodiment, the wiring board further includes a heat dissipation pattern disposed on the surface of the insulating substrate opposite to the first surface.

[0079] The semiconductor module according to the above embodiment further includes a cooler that is arranged on the surface of the wiring board opposite to the surface on which the semiconductor element is arranged and is connected to the wiring board.

[0080] The vehicle according to the above-described embodiment includes the semiconductor module according to the above-described embodiment.

[0081] The present invention is not limited to the above-described embodiments, and may be variously modified, substituted, or altered without departing from the spirit of the technical idea. Furthermore, if the technical idea can be realized in a different way due to technological advances or other derived technologies, it may be implemented using that method. Therefore, the claims cover all embodiments that may fall within the scope of the technical idea. [Industrial Applicability]

[0082] As described above, the present invention has the effect of reducing the stress applied to the joint surface between the wiring member that connects the electrodes of multiple semiconductor elements in a semiconductor module and the electrodes of the semiconductor elements, thereby suppressing a decrease in the operational reliability of the semiconductor module, and is particularly useful for industrial or vehicular semiconductor modules used as power conversion devices. [Explanation of symbols]

[0083] 1. Semiconductor module 2 Wiring board 200 insulating substrate 201, 202, 203 Conductor patterns 209 Heat dissipation pattern 3A~3H Semiconductor elements 301 Emitter electrode 5A~5B Lead 6, 6A, 6B, Wiring materials 601~605 Conductor spacer 610 Laminate 611~613, 616, 617 connection area 614, 615, 618, 619 Connected area 620, 630, 640, 660 Conductor foil 650 opening 7A~7D Bonding wire 8 cases 801~803 Main terminal 9 Heat sink 10 Cooler 1501 vehicles 1502 wheels 1503 Drive unit 1504 Control device

Claims

1. a wiring board having an insulating substrate and a conductor pattern disposed on a first surface of the insulating substrate; a semiconductor element disposed on the conductor pattern of the wiring board and connected to the conductor pattern; a wiring member that electrically connects an electrode provided on a surface of the semiconductor element opposite to the conductor pattern to another conductor, The wiring member is a first conductive spacer bonded to the electrode of the semiconductor element; a second conductor spacer joined to the other conductor; a laminate in which a plurality of conductor foils are stacked and arranged so that the distances from the surface of the semiconductor element on which the electrodes are formed are different from one another, the laminate connecting the first conductor spacer and the second conductor spacer; Each of the plurality of conductor foils of the laminated body is a first connection region that is a connection region with the first conductor spacer; a second connection region which is a connection region with the second conductive spacer; a coupling region between the first connection region and the second connection region, The plurality of conductor foils are at least one intermediate conductor foil; a first conductor foil and a second conductor foil that are stacked with the at least one intermediate conductor foil sandwiched therebetween; The intermediate conductor foil has a gap forming portion that forms a gap between the connecting region of the first conductor foil and the connecting region of the second conductor foil. Semiconductor module.

2. 2. The semiconductor module of claim 1, wherein the laminate is cylindrical and has a gap formed by the gap-forming portion of the intermediate conductor foil, the gap extending from at least the boundary between the first connection region and the connecting region to the boundary between the second connection region and the connecting region.

3. 2. The semiconductor module according to claim 1, wherein each of the plurality of conductor foils of the laminate has a planar shape in a planar view of the surface on which the electrodes of the semiconductor element are formed, such that adjacent conductor foils do not overlap with each other at least in the region within the connection region excluding the ends of the connection region.

4. the gap forming portion of the intermediate conductor foil is an opening that provides an opening region in the connecting region, in which a surface facing the first conductor foil and a surface facing the second conductor foil are open, the first conductor foil has, within the connecting region, a connecting portion that connects the first connection region and the second connection region, the connecting portion passing over the opening region of the intermediate conductor foil in a plan view and not overlapping with the intermediate conductor foil; The semiconductor module according to claim 3 .

5. 5. The semiconductor module of claim 4, wherein the first conductor foil has an additional connecting portion within the connecting region that overlaps, in the planar view, a widthwise end portion of the intermediate conductor foil that is perpendicular to a connecting direction connecting the first connection region and the second connection region in the connecting region.

6. The semiconductor module according to claim 1 , wherein a portion of the opening region of the intermediate conductor foil overlaps with the electrode of the semiconductor element in a plan view of the surface on which the electrode of the semiconductor element is formed.

7. The semiconductor module according to claim 1 , wherein the first conductor foil and the second conductor foil have the same planar shape in a plan view of the surface on which the electrodes of the semiconductor element are formed.

8. an additional semiconductor element disposed on the conductor pattern or another conductor pattern of the wiring board and connected to the conductor pattern or another conductor pattern; The other conductor bonded to the second conductor spacer of the wiring member is an electrode of the additional semiconductor element. The semiconductor module according to claim 1 .

9. 2. The semiconductor module according to claim 1, wherein the second conductive spacer of the wiring member is electrically connected to a conductive pattern different from the conductive pattern of the wiring board.

10. 2. The semiconductor module according to claim 1, further comprising a case member having leads electrically connected to said second conductive spacers of said wiring member.

11. the wiring member further includes a third conductive spacer; Each of the plurality of conductor foils of the laminated body is a third connection region which is a connection region with the third conductive spacer; a second connecting region between the first connecting region and the third connecting region; The intermediate conductor foil has a second gap forming portion that forms a gap between the second connecting region of the first conductor foil and the second connecting region of the second conductor foil. The semiconductor module according to claim 1 .

12. 2. The semiconductor module according to claim 1, wherein the wiring board further comprises a heat dissipation pattern disposed on a surface of the insulating substrate opposite to the first surface.

13. 2. The semiconductor module according to claim 1, further comprising: a cooler disposed on a surface of said wiring board opposite to a surface on which said semiconductor element is disposed, and connected to said wiring board.

14. A vehicle comprising the semiconductor module according to any one of claims 1 to 13.

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