Semiconductor device

Abstract

To provide a semiconductor device that can normally communicate with a device that superimposes a communication signal on a power supply.SOLUTION: An information processing device 10 includes a microcomputer 12 having a UART circuit 16 and a duty conversion circuit (100%→50%). The UART circuit 16 includes a receiving unit 20 that receives, from an HBS circuit 14, a communication signal with a duty of 50% that is received by the HBS circuit 14 via power supply wiring, and an acquiring unit 22 that includes a counter 24, and counts a reference clock with the counter 24 and acquires data at a timing corresponding to a predetermined duty ratio.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] Recently, a method of transmitting a communication signal on the power supply of a programmable logic controller (PLC), a home bus system (HBS), etc. has become widespread. For example, the techniques disclosed in Patent Documents 1 to 3 have been proposed.

[0003] Patent Document 1 proposes a commercial power superimposed communication device that transmits signals using a commercial power line.

[0004] Patent Document 2 describes a method of converting a unipolar NRZ signal output from a serial interface already installed in a microcomputer into an AMI signal with a pulse duty ratio of 50% using hardware.

[0005] Patent Document 3 discloses a power line communication system that uses power lines branched by a distribution board. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Publication No. 59-075724 [Patent Document 2] Japanese Patent Application Laid-Open No. 63-193748 [Patent Document 3] Japanese Patent Application Laid-Open No. 2005-295248 Summary of the Invention [Problem to be solved by the invention]

[0007] It is expected that communication signals such as HBS will be transmitted using a Universal Asynchronous Receiver Transmitter (UART), but for example, signals handled by a UART have a duty of 100%, whereas signals handled by an HBS must have a duty of 50%, so in order to receive signals via a UART, the duty must be converted from 50% to 100%.

[0008] When a 100% duty signal for asynchronous (start-stop synchronous) serial communication such as UART is generated by calculating the logical sum of a signal from a device that transmits a communication signal to a power supply such as a PLC or HBS and a signal obtained by delaying that signal, a joint (whisker) may appear in the signal depending on the delay, preventing normal communication.

[0009] The present invention has been made in consideration of the above circumstances, and has as its object to provide a semiconductor device that can properly communicate with a device that transmits a communication signal over a power supply. [Means for solving the problem]

[0010] The semiconductor device according to the first aspect includes a receiving unit that receives a communication signal from a communication circuit that communicates by superimposing the communication signal on a power supply, and an acquiring unit that acquires timing data corresponding to a predetermined duty ratio of the communication signal received by the receiving unit.

[0011] In addition, a semiconductor device according to a second aspect includes a plurality of delay circuits that delay, by different times, a communication signal received from a communication circuit that communicates by superimposing the communication signal on a power supply, and a logic circuit that performs a logical operation on the communication signal and the output of the plurality of delay circuits and outputs the result. [Brief explanation of the drawings]

[0012] [Figure 1] 1 is a block diagram showing a schematic configuration of an information processing device according to an embodiment of the present invention; [Figure 2]10A to 10C are diagrams illustrating examples of waveforms of UART data, a signal converted into a 50% duty signal, an HBS signal, and a received signal in the information processing device according to the present embodiment. [Figure 3] FIG. 1 is a block diagram showing a schematic configuration of a conventional information processing device that performs communication by superimposing a communication signal on a conventional power supply. [Figure 4] FIG. 10 is a diagram for explaining a duty conversion circuit (100% to 50%) when the UART circuit is positive logic. [Figure 5] FIG. 10 is a diagram for explaining a duty conversion circuit (100% to 50%) when the UART circuit is negative logic. [Figure 6] FIG. 10 is a diagram for explaining a duty conversion circuit (50% to 100%) when the UART circuit is positive logic. [Figure 7] FIG. 10 is a diagram for explaining a duty conversion circuit (50% to 100%) when the UART circuit is negative logic. [Figure 8] 10A and 10B are diagrams illustrating example waveforms of UART data, a signal converted into a 50% duty signal, an HBS signal, a received signal, and UART data with a signal joint in an information processing device according to a conventional embodiment. [Figure 9] FIG. 10 is a block diagram showing an example in which an acquisition unit of a UART circuit is provided with a majority circuit. [Figure 10] FIG. 10 is a block diagram showing a schematic configuration of an information processing device according to a second embodiment. [Figure 11] FIG. 10 is a diagram showing a configuration of a duty conversion circuit (50% to 100%) in an information processing device according to a second embodiment. [Figure 12] 3A and 3B are diagrams illustrating an example of waveforms of signals input to and output from a duty conversion circuit (50% to 100%) in the information processing device according to the present embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0013] An embodiment of the present invention will now be described in detail with reference to the accompanying drawings. (First embodiment) 1 is a block diagram showing a schematic configuration of an information processing device according to this embodiment. In the first embodiment, a microcomputer 12 will be described as an example of a semiconductor device.

[0014] As shown in FIG. 1, an information processing device 10 according to this embodiment includes a microcomputer 12 and an HBS (Home Bus System) circuit 14.

[0015] The microcomputer 12 transmits and receives signals to and from external devices via an HBS circuit 14, which is an example of a communication circuit that performs communication by superimposing a communication signal on a power supply.

[0016] The microcomputer 12 includes a UART (Universal Asynchronous Receiver Transmitter) circuit 16 and a duty conversion circuit (100% to 50%) 18.

[0017] The duty conversion circuit (100%→50%) 18 converts the 100% duty signal of the UART circuit 16 into a 50% duty signal and outputs it to the HBS circuit 14. Note that, although this embodiment describes an example in which the duty conversion circuit (100%→50%) 18 is provided within the microcomputer 12, it may also be provided separately from the microcomputer 12.

[0018] The UART circuit 16 is a circuit that performs mutual conversion between serial signals and parallel signals using a start-stop synchronization method. In this embodiment, as shown in FIG.

[0019] The receiving unit 20 receives from the HBS circuit 14 a communication signal with a duty of 50% that has been received by the HBS circuit 14 via the power supply wiring.

[0020] The acquiring unit 22 acquires timing data corresponding to a predetermined duty ratio of the communication signal received by the receiving unit 20. Specifically, the acquiring unit 22 includes a counter 24, which counts a reference clock to acquire timing data corresponding to the predetermined duty ratio. For example, the acquiring unit 22 acquires timing data corresponding to a duty of 1 to 5 (greater than or equal to 1 and less than 50) (0%). As an example, the acquiring unit 22 acquires timing data corresponding to a duty of 25%. Note that the timing corresponding to the predetermined duty ratio depends on the clock of the UART circuit 16. Specifically, if 16 clocks of the clock in the UART circuit 16 correspond to a 100% duty, data corresponding to a clock between 1 / 16 and 8 / 16 is acquired. For timing corresponding to a duty of 25%, timing data corresponding to a clock of 4 / 16 is acquired.

[0021] Next, an operation when transmitting a signal from the HBS circuit 14 to the UART circuit 16 in the information processing device according to this embodiment configured as described above will be described.

[0022] When UART data is transmitted from the UART circuit 16, it is converted into a 50% duty signal by a duty conversion circuit (100% to 50%) 18 and transmitted to the HBS circuit 14. The HBS circuit 14 transmits the HBS signal to the power supply wiring.

[0023] When the HBS circuit 14 receives an HBS signal from the power supply line, the HBS signal is restored and the received signal is sent to the UART circuit 16 .

[0024] In the UART circuit 16, the reception signal from the HBS circuit 14 is received by the receiving unit 20, and timing data corresponding to a predetermined duty ratio of the reception signal is acquired by the acquiring unit 22. Figure 2 shows example waveforms of the UART data, the signal converted to a 50% duty signal, the HBS signal, and the reception signal.

[0025] Here, a conventional information processing device that performs communication by superimposing a communication signal on a conventional power source will be described. Fig. 3 is a block diagram showing a schematic configuration of a conventional information processing device that performs communication by superimposing a communication signal on a conventional power source. Note that the same reference numerals will be used to denote components common to the first embodiment.

[0026] 3, the UART circuit 16 and the HBS circuit 14 are connected via a duty conversion circuit (100% → 50%) 18 and a duty conversion circuit (50% → 100%) 26. That is, the UART circuit 16 has a duty of 100%, whereas the HBS circuit 14 has a duty of 50%, so the duty ratio of the signal is converted by the duty conversion circuit (100% → 50%) 18 and the duty conversion circuit (50% → 100%) 26.

[0027] In detail, the signal transmitted from the UART circuit 16 is converted from a 100% duty signal to a 50% duty signal by the duty conversion circuit (100% to 50%) 18, and the HBS signal is transmitted to the power supply wiring via the HBS circuit 14.

[0028] On the other hand, the HBS signal received from the power supply wiring is restored by the HBS circuit 14 and transmitted to the UART circuit 16. The signal transmitted from the HBS circuit 14 to the UART circuit 16 is converted from a 50% duty signal to a 100% duty signal by a duty conversion circuit (50% to 100%) 26 and input to the UART circuit 16.

[0029] The duty conversion circuit (100% to 50%) 18 can be implemented by a logic circuit. For example, when the UART circuit 16 is positive logic, it can be implemented by a logical product circuit 28 that calculates the logical product (AND) of the UART signal and the UART source clock, as shown in FIG. 4. That is, by calculating the logical product of the UART signal (100% duty signal) and the UART source clock, a UART signal (50% duty signal) is generated. FIG. 4 is a diagram for explaining the duty conversion circuit (100% to 50%) 18 when the UART circuit 16 is positive logic.

[0030] Furthermore, when the UART circuit 16 is negative logic, this can be realized by a logical OR circuit 30 that calculates the logical OR of the UART signal and the UART source clock, as shown in Fig. 5. That is, by calculating the logical OR of the UART signal (100% duty signal) and the UART source clock, a UART signal (50% duty signal) is generated. Fig. 5 is a diagram for explaining the duty conversion circuit (100% to 50%) 18 when the UART circuit 16 is negative logic.

[0031] On the other hand, the duty conversion circuit (50% → 100%) 26 can generally be realized by a logic circuit that performs a logical operation on a signal source and a signal obtained by delaying the signal source. For example, if the UART circuit 16 is positive logic, it can be realized by a logical OR circuit 30 that calculates the logical OR of the HBS reception signal and a signal obtained by delaying the HBS reception signal using a delay circuit 32, as shown in FIG. 6. In other words, the UART signal (duty 100% signal) is generated by calculating the logical OR of the HBS reception signal (duty 50% signal) and the HBS reception signal (delayed 50% signal) that is obtained by delaying this signal by 50%. FIG. 6 is a diagram for explaining the duty conversion circuit (50% → 100%) 26 when the UART circuit 16 is positive logic.

[0032] Furthermore, when the UART circuit 16 is negative logic, this can be realized by a logical product circuit 28 that calculates the logical product of the HBS reception signal and a signal obtained by delaying the HBS reception signal using a delay circuit 32, as shown in Fig. 7. That is, the UART signal (100% duty signal) is generated by calculating the logical product of the HBS reception signal (50% duty signal) and the HBS reception signal (50% delayed signal) that is obtained by delaying this signal by 50%. Fig. 7 is a diagram for explaining the duty conversion circuit (50% to 100%) 26 when the UART circuit 16 is negative logic.

[0033] However, when a delay circuit 32 that converts from a 50% duty to a 100% duty is created as in the conventional embodiment, there is a concern that a signal joint (whisker) may appear at the position corresponding to the 50% duty, as shown in Figure 8, depending on how the delay circuit 32 is created. In the conventional embodiment, the presence of a signal joint could prevent the UART circuit 16 from receiving the signal correctly.

[0034] Therefore, in this embodiment, as described above, the duty conversion circuit (50% to 100%) 26 is omitted from the conventional embodiment. Instead, the UART circuit 16 is provided with the functions of the receiving unit 20 and the acquiring unit 22.

[0035] That is, the receiving unit 20 receives a communication signal with a duty cycle of 50% transmitted from the HBS circuit 14. Then, the acquiring unit 22 acquires data of timing corresponding to a predetermined duty cycle of the communication signal received by the receiving unit 20. For example, the acquiring unit 22 acquires data of timing corresponding to a duty cycle of 25%. As a result, since the information processing device 10 according to this embodiment does not have a duty conversion circuit (50% to 100%) 26, it is possible to transmit a signal from the HBS circuit 14 to the UART circuit 16 without the problem of being unable to receive data due to a joint in the data.

[0036] The timing at which the acquisition unit 22 acquires data may be changed depending on the communication baud rate. This makes it possible to accommodate different communication baud rates. However, this has the disadvantage of significantly limiting the accuracy of the clock of the original oscillation of the UART circuit 16, so it is recommended to generate the clock by using a crystal oscillation or ceramic oscillation.

[0037] 9, the acquisition unit 22 of the UART circuit 16 of this embodiment may include a majority circuit 34. For example, the acquisition unit 22 acquires timing data corresponding to a plurality of predetermined duty ratios, and the majority circuit 34 takes a majority vote, which is effective in reducing noise.

[0038] (Second embodiment) Next, an information processing device according to a second embodiment will be described. Fig. 10 is a block diagram showing a schematic configuration of the information processing device according to the second embodiment. In this embodiment, the configuration of the duty conversion circuit (50% → 100%) 26 is different from that of the conventional embodiment described above, and other configurations are the same as those of the conventional embodiment, so common parts will be described with the same reference numerals. Note that in the second embodiment, the duty conversion circuit (50% → 100%) 26 will be described as an example of a semiconductor device.

[0039] In this embodiment, as in the first embodiment and the conventional embodiment, the microcomputer 12 sends and receives signals to and from an external device via the HBS circuit 14.

[0040] In the information processing device 11 according to this embodiment, the UART circuit 16 and the HBS circuit 14 are connected via a duty conversion circuit (100%→50%) 18 and a duty conversion circuit (50%→100%) 26, as in the conventional embodiment.

[0041] In this embodiment, the microcomputer 12 includes a UART circuit 16, and the duty conversion circuit (100% → 50%) 18 and the duty conversion circuit (50% → 100%) 26 are provided separately from the microcomputer 12. Note that at least one of the duty conversion circuit (100% → 50%) 18 and the duty conversion circuit (50% → 100%) 26 may be provided within the microcomputer 12.

[0042] 11 is a diagram showing the configuration of a duty conversion circuit (50% to 100%) 26 in an information processing device 11 according to the second embodiment. In this embodiment, the UART circuit 16 is negative logic, but it may be positive logic. When the UART circuit 16 is positive logic, a logical OR circuit is used as the logic circuit 36.

[0043] 11, the duty conversion circuit (50% to 100%) 26 in the information processing device according to this embodiment includes a plurality of delay circuits 32 as delay circuits, and also includes a logic circuit 36. In this embodiment, the plurality of delay circuits 32 includes two delay circuits 32, a delay circuit A 32A and a delay circuit B 32B, but may include three or more delay circuits.

[0044] The plurality of delay circuits 32 delay the communication signal received by the HBS circuit 14 from the power supply wiring by different times.

[0045] In this embodiment, the delay circuit A32A delays the HBS reception signal (50% duty signal) that the HBS circuit 14 receives from the power supply wiring and transmits to the UART circuit 16 by a predetermined duty and inputs the signal to the logic circuit 36. For example, the delay circuit A32A delays the HBS reception signal (50% duty) by 30% to generate an HBS reception signal (delay 30%).

[0046] The delay circuit B32B delays the HBS reception signal (duty 50%) by a larger amount than the delay circuit A32A and inputs the signal to the logic circuit 36. The delay circuit B32B generates an HBS reception signal (duty 50%) by delaying the HBS signal (duty 50%) by 50%, for example.

[0047] In this embodiment, since the UART circuit 16 uses negative logic, a logical product circuit is used as the logic circuit 36. That is, the logic circuit 36 ​​generates a UART signal (100% duty signal) by calculating the logical product of an HBS reception signal (50% duty signal), an HBS reception signal (30% duty signal), and another HBS reception signal (50% duty signal). The logic circuit 36 ​​then transmits the generated UART signal (100% duty signal) to the UART circuit 16.

[0048] Next, an operation when transmitting a signal from the HBS circuit 14 to the UART circuit 16 in the information processing device according to this embodiment configured as described above will be described.

[0049] When UART data is transmitted from the UART circuit 16, it is converted into a 50% duty signal by a duty conversion circuit (100% to 50%) 18 and transmitted to the HBS circuit 14. The HBS circuit 14 transmits the HBS signal to the power supply wiring.

[0050] When the HBS circuit 14 receives an HBS signal from the power supply line, the HBS signal is restored and sent to the duty conversion circuit (50% to 100%) 26, where it is converted into a 100% duty signal. The converted 100% duty signal is then input to the UART circuit 16 as UART data.

[0051] FIG. 12 is a diagram showing an example of waveforms of signals input to and output from the duty conversion circuit (50%→100%) 26 in the information processing device 11 according to this embodiment.

[0052] 12, the duty conversion circuit (50% to 100%) 26 calculates the logical product of the HBS reception signal (50% duty signal) received from the HBS circuit 14, the HBS reception signal (50% duty signal) delayed by 30% using a delay circuit A 32A (delayed 30% signal), and the HBS reception signal (50% duty signal) delayed by 50% using a delay circuit B 32B (delayed 50% signal). This generates a UART signal (100% duty signal).

[0053] In this embodiment, since there is a possibility that a signal will have a joint when a single delay circuit 32 is used, as in the conventional embodiment, multiple delay circuits 32 are provided to prevent the joint from appearing in the signal. This makes it possible to generate a seamless UART signal (100% duty signal).

[0054] In the second embodiment, the HBS reception signal (50% duty signal) is converted into a UART signal (100% duty signal) using a plurality of delay circuits 32, and therefore whether communication is possible or not is considered to depend on the performance of the delay circuits 32. For this reason, it is also possible to provide a plurality of delay circuits 32 and combine the plurality of delay circuits 32 to provide flexibility in communication. For example, the plurality of delay circuits 32 may each have a different delay amount, and the delay circuit 32 to be used may be selected depending on the baud rate of the communication.

[0055] On the other hand, in the first embodiment, since the delay circuit 32 is not provided, flexible settings are possible, and good communication is possible.

[0056] In the above embodiment, the HBS circuit 14 is used as an example of a communication circuit that performs communication by superimposing a communication signal on a power supply, but this is not limited to this, and other communication circuits such as a PLC may also be used.

[0057] Furthermore, the present invention is not limited to the above, and it goes without saying that various modifications can be made without departing from the spirit of the present invention.

[0058] The following additional notes are provided regarding the above-described embodiments.

[0059] (Appendix 1) a receiving unit that receives a communication signal from a communication circuit that performs communication by superimposing the communication signal on a power supply; an acquisition unit that acquires timing data corresponding to a predetermined duty ratio of the communication signal received by the receiving unit; A semiconductor device comprising:

[0060] (Appendix 2) 2. The semiconductor device according to claim 1, wherein the acquisition unit changes the timing in accordance with a baud rate.

[0061] (Appendix 3) further comprising a majority circuit; the acquiring unit acquires timing data corresponding to a plurality of predetermined duty ratios; 3. The semiconductor device according to claim 1, wherein the majority circuit takes a majority vote on the data acquired by the acquisition unit.

[0062] (Appendix 4) 4. The semiconductor device according to claim 1, further comprising a microcomputer including the receiving unit, the acquiring unit, and a duty conversion circuit that converts a duty ratio of a signal to be transmitted to the communication circuit.

[0063] (Appendix 5) a plurality of delay circuits that delay communication signals received from a communication circuit that performs communication by superimposing the communication signals on a power supply by different times; a logic circuit that performs a logical operation on the communication signal and the outputs of the plurality of delay circuits and outputs the result; A semiconductor device comprising:

[0064] (Appendix 6) 6. The semiconductor device according to claim 5, wherein a delay circuit to be used is selected depending on a baud rate.

[0065] (Appendix 7) 7. The semiconductor device according to claim 5, wherein the logic circuit performs a logical AND operation in the case of positive logic and a logical OR operation in the case of negative logic.

[0066] (Appendix 8) 8. The semiconductor device according to claim 5, further comprising a duty conversion circuit including the delay circuit and the logic circuit in a microcomputer. [Explanation of symbols]

[0067] 10. Information processing equipment 12 Microcomputer 20 Receiving unit 22 Acquisition Department 24 Counter 26 Duty conversion circuit (50% → 100%) 34 Majority voting circuit 32 Delay circuit 32A Delay Circuit A 32B Delay circuit B 36 Logic Circuits

Claims

1. a receiving unit that receives a communication signal from a communication circuit that performs communication by superimposing the communication signal on a power supply; an acquisition unit that acquires timing data corresponding to a predetermined duty ratio of the communication signal received by the receiving unit; A semiconductor device comprising:

2. The semiconductor device according to claim 1 , wherein the acquisition section changes the timing in accordance with a baud rate.

3. further comprising a majority circuit; the acquiring unit acquires timing data corresponding to a plurality of predetermined duty ratios; The semiconductor device according to claim 1 , wherein the majority circuit takes a majority vote of the data acquired by the acquisition unit.

4. The semiconductor device according to claim 1 , further comprising a microcomputer that includes the receiving unit, the acquiring unit, and a duty conversion circuit that converts the duty ratio of a signal to be transmitted to the communication circuit.

5. a plurality of delay circuits that delay communication signals received from a communication circuit that performs communication by superimposing the communication signals on a power supply by different times; a logic circuit that performs a logical operation on the communication signal and the outputs of the plurality of delay circuits and outputs the result; A semiconductor device comprising:

6. 6. The semiconductor device according to claim 5, wherein the delay circuit to be used is selected in accordance with the baud rate.

7. 6. The semiconductor device according to claim 5, wherein the logic circuit performs a logical AND operation in the case of positive logic and a logical OR operation in the case of negative logic.

8. 6. The semiconductor device according to claim 5, wherein a duty conversion circuit including said delay circuit and said logic circuit is provided within a microcomputer.

Images