236 results about "Binary encoding" patented technology

The invention belongs to the field of storage, and discloses a high-energy-efficiency mixed-precision charge domain in-storage computing architecture and a working method thereof. Comprising a single-slope analog-to-digital converter, a sparsity perception input alignment module, a multi-bit input accumulation module, a controller and an accumulation module, wherein the single-slope analog-to-digital converter consists of an index calculation array, a mantissa calculation array, a shared ramp voltage generator and a bidirectional counter. According to the invention, serial input binary coding based on capacitor voltage is suitable for floating point and integer multiply-accumulate operation with flexible bit width; according to the invention, a shared single-slope analog-to-digital converter (SS-ADC) is introduced to realize maximum index search and index difference calculation; according to the method, a sparsity perception calculation scheme is provided, low-importance input-weight pairs are filtered out through an adjustable threshold value, and invalid power consumption is reduced; according to the method, a multi-bit input accumulation method is further combined, and an ADC redundancy optimization quantization and normalization process is utilized, so that the overall energy efficiency is improved.

The invention discloses an intelligent marketing terminal power data communication security protection method and system, and belongs to the field of power data security, and the method comprises the steps: collecting electromagnetic noise spectrum data through a built-in environment electromagnetic sensing module of a terminal, extracting electromagnetic characteristic factors, and constructing a correlation model of the electromagnetic characteristic factors and the complexity of an elliptic curve cryptosystem; building a terminal twinborn mirror image, predicting a communication instruction sequence and calculating a deviation coefficient in combination with a long-short-term memory neural network; classifying and screening the power data collected by the terminal, desensitizing privacy data, and then fusing the privacy data into the hash fragment of the unique identifier of the terminal equipment to generate a desensitized power data packet containing the terminal identity identifier; a data abstract is generated according to encryption parameters determined by the association model, the access authority is verified, a data acquisition timestamp is converted into a binary coding sequence, the data abstract is embedded, and an encrypted data packet with a time sequence traceability watermark is generated and uploaded to the block chain for evidence storage; according to the invention, full-process security management and control of power data are realized, and the communication security and the data credibility are improved.

The invention discloses a memory fault processing method and device during writing, a terminal and a storage medium, and belongs to the field of memorys.The method comprises the steps that when a memory unrecoverable fault processing method is executed, whether a memory synchronization fault exists or not is judged, and when the memory synchronization fault exists, context register information of an interrupted process is obtained, and a value of a program counter is obtained; determining an address of the interrupted instruction, reading a binary code corresponding to the interrupted instruction based on the address of the interrupted instruction, and analyzing an operation code in the binary code; determining whether the currently interrupted process is in a write operation stage or not according to the analysis result of the operation code, and when the currently interrupted process is in the write operation stage, determining that a memory fault occurs during writing; when anonymous mapping is carried out, a new physical page frame is distributed, and the new physical page frame is used for replacing an original faulty physical page frame; determining all page table items related to the original fault physical page frame; and replacing the original information in all the page table entries with new physical page frame information.

In some example embodiments, there may be provided a method that includes receiving, by a machine learning encoder as part of a training phase, channel state information as data samples; generating, by the machine learning encoder, a latent variable comprising a log likelihood ratio value representation for the channel state information, wherein the latent variable provides a lower dimension binary representation when compared to the received channel state information to enable compression of the received channel state information; generating, by the binary sampler, a binary coding value representation of the latent variable, wherein the binary coding value converts the latent variable to a binary form; and generating, by the machine learning decoder, a reconstructed channel state information, wherein the generating is based in part on the binary coding value representation of the latent variable generated by the binary sampler. Related systems, methods, and articles of manufacture are also disclosed.

A hardware module for performing dot product operations includes receiver circuitry receiving a first vector and a second vector, each comprising at least two elements of a binary encoded integer. Logic generates an array of partial products of N rows of bits for a dot product operation between the first vector and the second vector. Grouping circuitry groups bits of the elements of the second vector into a binary number, wherein each binary number is associated with a respective row of the N rows of bits, and selector circuitry selects a partial product value for each of the N rows of bits based on the binary number that is associated with the respective row, such that one partial product is generated per binary number. The hardware module also comprises adder circuitry configured to perform adding the N rows of bits together to compute an output associated with the dot product operation between the first and second vectors.

The invention discloses a graph database decimal index coding and decoding method based on key value storage, and belongs to the technical field of graph database management. The coding method comprises the following steps: receiving numerical values to be coded and sorting direction parameters thereof; normalizing the to-be-coded numerical value, and extracting a symbol, a weight and a digital array of the normalized to-be-coded numerical value; dynamically generating a coding auxiliary parameter set based on the sorting direction parameters and the symbols, the coding auxiliary parameter set comprising sorting masks, escape characters and filling characters; converting the symbol, the weight and the digital array into a binary coded stream according to the coding auxiliary parameter set; adding a data termination mark consisting of escape characters at the tail of the binary coded stream; and outputting the binary coded stream for orderly storage and retrieval of the data. According to the method, the decimal value is decomposed into the symbol, the weight and the digital array, and then the compact binary coding mode is adopted for coding, so that efficient storage and query of the graph database index are realized.

The invention belongs to the technical field of document encryption, and discloses a document encryption traceability method based on document parameterization characteristics, which comprises the following steps of: selecting the parameterization characteristics related to characters in a document as a carrier of password information, and respectively representing 1 and 0 of binary codes by adopting numerical ranges of two parameter values which are not overlapped. During encryption, the parameter size of the corresponding feature in the document is adjusted corresponding to 1 and 0. And during decryption, parameter values of corresponding characteristics in the document are obtained, and size judgment is carried out. On one hand, parameterized features related to characters are features which can be directly measured in a document image, and parameter values of the parameterized features can be directly calculated and obtained based on image data and can be easily and directly obtained in the image processing process of the document. And on the other hand, during encryption and decryption, other elements except the document do not need to be depended on, a feature comparison step does not exist, a large amount of model training for feature comparison does not need to be carried out, and the complexity of the encryption and decryption process and the difficulty of feature recognition are effectively reduced.

An apparatus for generating a data stream according to an embodiment is provided. The apparatus is configured to generate the data stream, such that the data stream has header data and payload data. The apparatus is configured to generate the header data such that the header data comprises a synchronization header. Moreover, the apparatus is configured to generate the synchronization header using binary coding. Furthermore, the apparatus is configured to generate the synchronization header such that the synchronization header comprises a synchronization sequence being a predefined bit sequence having a plurality of bits.

The invention discloses a method and device for improving the reuse rate of a hardening module of a digital circuit and optimizing the time sequence, power consumption and area, and the method comprises the following steps: determining the instantiation times of the hardening module to be optimized, and calculating and determining the bit width w of a coding input signal; creating a new module, removing all instantiated parameters and constant value input ports, and adding a coding input port; creating a temporary variable in the new module; establishing a mapping relation in the new module; instantiating the original module internally by using the temporary variable; all original instances are re-instantiated using a new module, and the encoded value is assigned to the encoding input port. The optimization method provided by the invention is simple in steps, and not only can perform coding optimization on input parameters and constant values on the boundary of the hardened module by adopting a minimum bit width binary coding mode according to the multiplexing times of the hardened module on the premise of ensuring the logic equivalence of a digital circuit, but also can perform coding optimization on the input parameters and constant values on the boundary of the hardened module. And the time sequence, the power consumption and the area in the hardening module can be optimized to the greatest extent.

A circuit for encoding a C-PHY signal, a decoding circuit and a transmission device, the encoding circuit being characterized by: obtaining a C-PHY line state, forming a line state block, mapping the line state block into a binary number capable of uniquely identifying the line state block, and setting different line state blocks for an HS mode, an LP mode and an ALP mode, and binary coding mapping is carried out according to the corresponding line state block, so that the coding efficiency is improved under different conditions. Furthermore, a flag bit is set, so that the bit number of binary coding is reduced, and the coding efficiency is improved. According to the invention, the complexity of a coding circuit is reduced, the integrity of coding information is kept, and the coding and decoding efficiency and the transmission real-time performance are improved from multiple angles through a series of methods such as flag bits and line state sub-blocks.

The application discloses an image size calibration method based on an improved Zhang Zhengyou calibration method and a wood defect area calculation method. When the Zhang Zhengyou calibration method uses an L-M method to solve a maximum likelihood estimation minimum value, a problem of easily falling into a local extreme value is solved by using the advantage of globally searching for an optimal value of a genetic algorithm to optimize the defect that the L-M algorithm easily falls into a local minimum value. In the genetic algorithm, binary coding is selected as an encoding type according to a parameter type. On the basis of considering calculation efficiency, a function f(x) = e st is selected as a use function. A roulette method is selected as a selection operation method. A simple and effective one-point crossover is selected as a crossover operation method. Then, only an approximate solution is obtained near a global optimal solution by using the genetic algorithm. Then, the approximate solution is optimized by using an L-M local search algorithm. The advantages of the global genetic algorithm and the local optimization L-M method are effectively combined.

This invention provides a reference voltage buffer circuit and calibration method for a high-precision analog-to-digital converter (ADC). The circuit includes a first operational amplifier whose inverting input is connected to a reference voltage, and whose output is fed back to the non-inverting input via a first driving transistor and a voltage divider circuit. A second operational amplifier's non-inverting input is connected to a first voltage divider node, its inverting input is connected to a second voltage divider node, and its output is connected to the gates of several third driving transistors and a second driving transistor. The drains of the third driving transistors are all connected to the first voltage divider node via switches. The width-to-length ratios of the second driving transistors and the several third driving transistors are linearly related. The switches are all input with logic control signals to control their states for linear calibration of the reference voltage. This invention uses binary encoding to control the switch states for linear calibration of the output reference voltage and significantly reduces the total resistance by designing a linear relationship between the resistors, thus reducing chip area and cost.

This invention discloses a method for porting a digital signal processor (DSP) assembler based on a processor architecture description, comprising the following steps: S1. Based on the processor architecture description, a lexical analysis and syntax analysis part of the assembler is constructed to realize the parsing of special assembly instructions; S2. Taking the parsed instruction data or instruction binary code as input, dynamic encoding and decoding of instructions are implemented according to the instruction definition, thereby realizing the conversion between the object file and the assembly file. This DSP assembler porting method further improves the performance of the assembler and automates the porting process, adapting it to the digital signal processor architecture. It also provides support for single instruction multiple data, very long instruction words, and instruction validity checks. While ensuring that the program execution result meets expectations, it greatly reduces the number of clock cycles required for execution, possesses universality, and meets the needs of rapid processor architecture updates.

The invention belongs to the technical field of compound screening, and provides a method for rapidly screening mass spectrum positive signals of organophosphorus ester compounds, which comprises the following steps of: performing binary coding on OPEs compounds and non-OPEs compounds to establish a mass spectrum database, training a machine learning model by using a data set in the mass spectrum database, and screening the mass spectrum positive signals of the organophosphorus ester compounds to obtain the mass spectrum positive signals of the organophosphorus ester compounds. And after training is completed, the machine learning model is used for predicting a mass spectrum to be detected, and screening of the organophosphate compounds is completed. According to the method, manual mass spectrum comparison is not needed, the screening flux is improved, a foundation is laid for standardized application of the screening process, and the screening efficiency is improved; in the screening process of an actual sample, the screening efficiency is improved from the original hour level to the minute level, and the purpose of rapidly screening the organophosphate compounds is achieved.

The invention discloses an important data error correction method suitable for an aerospace power supply and distribution single machine. According to the method, the Hamming code principle and the binary coding principle are utilized, and the characteristics of a microcontroller of the aerospace power supply and distribution stand-alone are combined, so that an error correction coding and decoding method is designed. According to the method, the single-machine micro-control system can correct a certain degree of data bit flipping errors under the condition that the data bit flipping errors occur under the influence of space environments such as space single particles, errors of important data caused by the space environments are reduced, and then part of autonomous control operations threatening spacecraft safety are prevented from occurring.

The present application relates to the technical field of charging pile management data storage, in particular to an interactive platform information storage method based on data coding. The method comprises the following steps: dividing the operation data of the charging pile in a historical time period to obtain multiple segments of operation data, and performing binary coding on each segment of operation data to obtain an initial coding sequence of each segment of operation data; based on the discrete index corresponding to each segment of operation data and the total number of charging transactions in each segment of operation data, obtaining the number of layers of down-sampling corresponding to the initial coding sequence of each segment of operation data; performing XOR operation and transposition XOR operation on two-by-two coding in the initial coding sequence of each segment of operation data based on the number of layers of down-sampling, obtaining the XOR coding sequence of each layer corresponding thereto, and storing the XOR coding sequence of each layer. The present application improves the security of charging pile operation data storage.

This invention discloses a route trajectory query method and terminal. The method obtains the binary encoding value corresponding to a latitude and longitude map and constructs a tree-like index structure based on the binary encoding value. It receives second route trajectory data, performs binary encoding on the second route trajectory data to obtain a third binary encoding value corresponding to the second route trajectory data, and searches for target route trajectory data corresponding to the second route trajectory data from the tree-like index structure based on the third binary encoding value. Unlike existing technologies that rely on GeoHash value comparison for querying, this method searches for matching route trajectories by retrieving the tree-like index structure, enabling rapid retrieval of relevant route trajectories, reducing computation time, and thus improving the efficiency of route trajectory querying.

A method and system for controlling a pixel of a display using pulse width modulation (PWM). A desired grayscale value for the pixel is processed to generate a binary encoding having a plurality of select bits encoding a select value, and a dither bit encoding a dither value, encoded by a scheme in which a first select value and a first dither value indicate a center-aligned pulse of a first width having a leading edge at a first temporal position, a second select value and the first dither value indicates a center-aligned pulse of a second width having a leading edge at a second temporal position, and the first select value and a second dither value indicate a center-aligned pulse of a second width having a leading edge at the first temporal position. The binary encoding is provided to the display for pulse width modulation of the pixel.

An approach is proposed for processing a value determined from a set of N ternary memory cells, comprising the steps of: (i) reading the set of ternary memory cells and determining the ternary symbol H, M, or L contained in each ternary memory cell, (ii) determining a first binary sequence based on the ternary symbols H of the set of read ternary memory cells, (iii) determining a second binary sequence based on the ternary symbols H and M of the set of read ternary memory cells, (iv) determining a third binary sequence based on the first binary sequence and the second binary sequence, reducing the number of bits in the third binary sequence compared to the number of bits in the first binary sequence and the second binary sequence.(v) Determining a composite binary value based on the binary-coded first binary sequence and the binary-coded third binary sequence and (vi) processing the composite binary value.

The invention relates to the technical field of decoration, and discloses a decoration interface combination processing method based on an MAHE method, and the method comprises the steps: S1, obtaining the decoration demands of a customer for three decoration interfaces of a wall surface, a ceiling and the ground; s2, the decoration requirements are analyzed, and respective configuration levels of the wall surface, the ceiling and the ground are determined; s3, calling corresponding wall surface, ceiling and ground components from a preset component library according to the numerical value of each bit of the three-bit binary code, and combining to generate a fabricated decoration scheme; and S4, on the basis of the three-bit binary code, performing weighted summation on each bit numerical value and a corresponding preset difference sequence weight value, and calculating to obtain an overall evaluation value of the fabricated decoration scheme. According to the invention, through artificial intelligence semantic recognition and a three-bit binary coding technology, automatic conversion of customer decoration requirements, systematic generation of the fabricated decoration scheme and objective quantitative evaluation of the comprehensive value of the scheme are realized.

The invention relates to a wide-range negative gain programmable gain amplifier circuit applied to audio analog output. The front-path adjustable resistor array adopts an R-2R topological structure, one end of each resistor with the resistance value of 2R is connected with a complementary switch, and the reference voltage or the input end of the amplifier can be selectively accessed. The complementary switch is controlled by digital logic. The digital logic coding is different from the traditional thermometer or binary coding, and is coded according to the dichotomy characteristic of the R-2R resistance network. Under the coding, the circuit realizes 121 gain steps, the gain step length is approximately equal to 0.5 dB, and the gain adjustable range is 0-60 dB. According to the invention, the requirements of small step length, large-range negative gain and high linearity of an audio programmable gain amplifier circuit are met.

The invention relates to the technical field of photoelectric data processing, provides a light wave chromatography computer coding method, system and architecture based on a toning principle, and aims to break through the performance bottleneck of traditional electronic calculation. According to the method, physical-level color processing is realized through color binary coding and light wave state discrete mapping based on an optical toning principle. The system integrates a digital input interface, a wavelength coding converter, a light wave operation core and a wavelength analysis unit, and supports efficient optical signal direct operation. On the architecture level, an extended von Neumann design is adopted, a three-level Clos-WSS optical interconnection network, a photon ALU and a PCM holographic main memory are included, and femtosecond-level delay, low power consumption and high parallelism are achieved. Advantages include physical level computational accuracy, nearly zero data handling energy consumption, and large scale wavelength level parallel processing. The method is suitable for 8K video real-time color modulation, industrial sorting and other high-requirement scenes, and a subversive solution is provided for the fields of automatic driving, digital twinning and the like.

A method and system for controlling pixels of a display using pulse width modulation (PWM). A desired gray scale value for a pixel is processed to generate a binary encoding having a plurality of select bits encoding select values and dither bits encoding dither values, the binary encoding encoded by a scheme in which a first select value and a first dither value indicate a center-aligned pulse having a first width and a leading edge at a first time position, a second select value and the first dither value indicate a center-aligned pulse having a second width and a leading edge at a second time position, and the first select value and a second dither value indicate a center-aligned pulse having the second width and a leading edge at the first time position. The binary encoding is provided to the display for pulse width modulation of the pixel.

The application relates to the field of high polymer synthesis, in particular to a digital coding macromolecule in the anti-counterfeiting application of ink. The application provides a compound with a general formula I. The digital coding macromolecule of the application introduces a rigid structure triphenylmethyl at the end of a molecular chain, introduces different tag label information in the macromolecule, expands the information carrying capacity of the same binary coding macromolecule, and applies the macromolecule to ink, so that the function of anti-counterfeiting identification is realized.

The invention discloses an underwater sound wave communication method, which comprises the following steps of: sampling, quantizing and binary coding an original analog signal of information to be transmitted at a transmitting end to obtain a binary bit stream; performing channel coding on the binary bit stream to obtain a coded code stream; sound source coding is carried out on the coded code stream to form a sound source array fuze so as to trigger and control corresponding sound sources to produce sound, and each sound source in a sound source array is uniquely determined by coordinates, sound frequency, sound intensity and a serial number; monitoring the frequency of a sound source at a receiving end, and matching a sounding sound source according to the arrival time, the arrival angle and the arrival intensity of the sound source signal; and decoding the bit code corresponding to the sounding source to extract transmission information. According to the scheme, a traditional complex modulation mode is abandoned, and the transmission efficiency, the transmission distance, the stability and the environmental adaptability of underwater acoustic communication can be improved.

This invention relates to a multi-satellite joint regional coverage planning method based on an improved multi-objective evolutionary algorithm, comprising the following steps: decomposing the area to be covered into discrete strip sets of all remote sensing satellites based on the imaging conditions of each satellite; binary encoding the strips in the discrete strip sets, using all encoded individuals as input to the improved multi-objective evolutionary algorithm, which employs a combination of the NSGA-III and S-CDAS algorithms to achieve an extreme solution preservation mechanism; constructing a multi-objective optimization model composed of multiple objective functions, and solving the multi-objective optimization model using the improved multi-objective evolutionary algorithm to obtain the regional coverage result. The improved multi-objective evolutionary algorithm in this invention can preserve extreme solutions, thus achieving satisfactory regional coverage results, and can also optimize the rationality of the regional coverage scheme from other objective dimensions.

The present invention relates to a method for generating coding tables for sensor signals of a vehicle, comprising: detecting the occurrence frequencies of the sensor signals; dividing the sensor signals into different levels according to the occurrence frequencies, wherein the numbers of the levels correlate with the number of coding bits, whereby with increasing occurrence frequency the numbers of the levels become smaller and the corresponding number of coding bits decreases;Assigning binary codes to the sensor signals, wherein the binary codes have a single middle bit position, as well as front bit positions and back bit positions, wherein a first bit value is written into the middle bit position, the number of front bit positions representing the level, and a second bit value is written, wherein the number of back bit positions depends on the number of front bit positions, and the value of the sensor signal is represented by means of the bit value of the back bit positions; generating a coding table to establish a correspondence between the sensor signals and the binary codes. The present invention further relates to a corresponding coding method, a corresponding decoding method, a corresponding computer program product, and a corresponding processing device. This makes it possible to reduce the internal memory required for recording the sensor signals.

The invention relates to a decoding method, which comprises the following steps of: acquiring an X-bit binary number, and directly mapping the binary number into a line state block for representing a line state; the binary numbers are in one-to-one correspondence with the line state blocks; the line state block comprises one or N line state values; according to the line state value of the line state block, an A line, a B line and a C line of the C-PHY are driven to be in line states corresponding to the line state value, and the line states are voltage combinations of the A line, the B line and the C line. Furthermore, a flag bit is set, so that the bit number of binary coding is reduced, and the coding efficiency is improved. The complexity of a coding and decoding circuit is reduced, the integrity of information transmitted in the coding and decoding process is kept, and the coding and decoding efficiency and the transmission real-time performance are improved from multiple angles through a series of methods such as flag bits and line state sub-blocks.

A data compression method is provided. The method comprises the following steps: performing binary coding on an input sequence based on a predetermined coding scheme to obtain a coded binary sequence; determining a sequence of observed values based on the encoded binary sequence, wherein two adjacent bits in the encoded binary sequence are configured as observed values in the sequence of observed values; and performing recursive approximation on the observed value sequence through a predetermined binary polynomial autoregressive (BPAR) model to obtain a compression result of the input sequence.

The invention provides an encoding method of a spherical equal-product hexagonal grid system, and relates to the technical field of geographic information system spatial data management, and the method comprises the steps: determining the grid resolution and hierarchy required by a target application scene based on icosahedron subdivision Snyder equal-product projection, and constructing a global discrete grid model; performing recursive and staggered seven-way tree subdivision on each triangular surface in the global discrete grid model to form a multi-level hexagonal grid system with approximately equal area; a binary code is distributed to each grid unit in the multi-level hexagonal grid system; and based on the binary codes, defining addition and subtraction operation rules between the grid codes, and calculating the relative displacement of the two grids in the space through the addition and subtraction operation rules of the codes. According to the technical scheme, the recursive hexagonal equal-product grid coding system with clear father-son affiliation can be adaptively constructed, and efficient space calculation and indexing are achieved through binary coding operation.