Memory system having combined high density low bandwidth memory and low density high bandwidth memory

Abstract

To provide an electronic system including a DRAM.SOLUTION: A memory system 10 includes at least two types of DRAMs, which differ in at least one characteristic. For example, one DRAM type may be a high density DRAM, while the other DRAM type may have lower density but may also have lower latency and higher bandwidth than a first DRAM type. The DRAM of the first type may be on one or more first integrated circuits, and the DRAM of a second type may be on one or more second integrated circuits. The first and second integrated circuits may be coupled to each other in a stack. The second integrated circuit may include a physical layer circuit to couple to other circuits (for example, an integrated circuit having a memory controller, such as a system on a chip(SOC)), and the physical layer circuit may be shared by the DRAM in the first integrated circuits.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] SUMMARY OF THE INVENTION The embodiments described herein relate to electronic systems that include dynamic random access memory (DRAM). [Background technology]

[0002] As DRAM continues to evolve, DRAM design is complicated by the differing ideal goals of DRAM, such as high-density storage with high bandwidth, large capacity, and low power consumption (high energy efficiency). Design choices that improve density / capacity tend to reduce (or at least not increase) bandwidth. Design choices that may increase bandwidth tend to reduce (or at least not increase) capacity and energy efficiency. Summary of the Invention

[0003] In one embodiment, a memory system can include at least two types of DRAM that differ in at least one characteristic. For example, one DRAM type can be a high-density DRAM, while the other DRAM type can have a lower density than the first DRAM type, but also a lower latency and higher bandwidth. The first type of DRAM can be in one or more first integrated circuits, and the second type of DRAM can be in one or more second integrated circuits. Providing a memory system with two types of DRAM (e.g., one high-density and one low-latency, high-bandwidth) can enable very energy-efficient operation, thereby making the memory system suitable for portable and other devices where energy efficiency and performance per unit of energy consumed are important attributes.

[0004] In one embodiment, a first integrated circuit and a second integrated circuit can be connected to each other in a stack. The second integrated circuit can include physical layer circuitry for connecting to other circuitry (e.g., an integrated circuit with a memory controller, such as a system-on-chip (SOC)), and this physical layer circuitry can be shared by the DRAM of the first integrated circuit. In some embodiments, this memory can be used to achieve high energy efficiency, high capacity, and low latency. The following detailed description refers to the accompanying drawings, which are briefly described below. [Brief explanation of the drawings]

[0005] [Figure 1] FIG. 1 is a block diagram of one embodiment of a system on a chip (SOC) having a memory controller and physical layer circuitry to main memory and cache memory. [Figure 2] FIG. 10 is a block diagram of another embodiment of a SOC having a memory controller and physical layer circuitry to a cache memory with another physical layer circuitry from the cache memory to a main memory. [Figure 3] FIG. 10 is a block diagram of another embodiment having a memory controller and physical layer circuit to a cache memory and a main memory and another physical layer circuit from the cache memory to the main memory. [Figure 4] FIG. 1 is a block diagram illustrating a system on chip (SOC) and memory for one embodiment. [Figure 5] 1 is a block diagram illustrating a SOC including one or more caches and a main memory connected to the SOC / cache for one embodiment. [Figure 6] FIG. 2 is a block diagram illustrating a SOC and multiple memories for one embodiment. [Figure 7] FIG. 1 is a block diagram illustrating a SOC including one or more caches and multiple main memories for one embodiment. [Figure 8]FIG. 1 is a block diagram of one embodiment of a system having main memory and cache memory in a package-on-package (POP) configuration. [Figure 9] FIG. 1 is a block diagram of another embodiment of a system having main memory and cache memory in a package-on-package (POP) configuration. [Figure 10] FIG. 1 is a block diagram of one embodiment of a system having a main memory and a cache memory, the main memory being packaged separately. [Figure 11] FIG. 1 is a block diagram of another embodiment of a system having a main memory and a cache memory, the main memory being packaged separately. [Figure 12] FIG. 1 is a block diagram of one embodiment of a system including a cache and a main memory dynamic random access memory (DRAM). [Figure 13] FIG. 2 is a block diagram of another embodiment of the present system. [Figure 14] FIG. 2 is a block diagram of yet another embodiment of the present system. DETAILED DESCRIPTION OF THE INVENTION

[0006] While the embodiments described in this disclosure may be susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the drawings and detailed description relating to the drawings are not intended to limit the embodiments to the particular forms disclosed; rather, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the appended claims. The headings used herein are for organizational purposes only and are not intended to be used to limit the scope of the description. As used throughout this application, the word "may" is used in its permissive sense (i.e., meaning having the possibility) rather than its obligatory sense (i.e., meaning must). Similarly, the words "include," "including," and "includes" mean "including, but not limited to."

[0007] Within this disclosure, various entities (which may be variously referred to as “units,” “circuits,” other components, etc.) may be described or claimed as being “configured” to perform one or more tasks or operations. The express phrase “entity” configured to “perform one or more tasks” is used herein to refer to a structure (i.e., a physical thing, such as an electronic circuit). More specifically, the express phrase is used to indicate that the structure is arranged to perform one or more tasks during operation. A structure may be said to be “configured to” perform a task even if the structure is not currently operating. For example, a “clock circuit configured to generate an output clock signal” is intended to cover a circuit that performs this function during operation even if the circuit is not currently in use (e.g., no power is connected to the circuit). Thus, an entity described or claimed as being “configured” to perform a task refers to a physical thing, such as an executable device, circuitry, memory having program instructions stored thereon, etc., that implements the task. The phrase is not used herein to refer to intangible things. In general, circuitry forming a structure corresponding to "configured to" may include hardware circuitry. Hardware circuitry may include any combination of combinational logic circuits, clocked storage devices such as flops, registers, latches, etc., finite state machines, memories such as static random access memories or embedded dynamic random access memories, custom-designed circuits, analog circuits, programmable logic arrays, etc. Similarly, various units / circuits / components may be described as performing a task(s) for ease of description. Such descriptions should be interpreted as including the phrase "configured to."

[0008] The term "configured to" is not intended to mean "configurable to." For example, an unprogrammed FPGA may be "configurable to" perform some particular function, but would not be considered "configured to" perform that function. After appropriate programming, the FPGA can then be configured to perform that function.

[0009] Any recitation in the accompanying claims of a unit / circuit / component or other structure configured to perform one or more tasks is expressly intended not to invoke 35 U.S.C. 112(f) construction for that claim element. Accordingly, none of the claims in this application as filed are intended to be construed as having means-plus-function elements. If an applicant wishes to invoke 35 U.S.C. 112(f) during prosecution, it will recite the claim element using the construction "means for" [performing a function].

[0010] In one embodiment, a hardware circuit according to the present disclosure may be implemented by coding a description of the circuit in a hardware description language (HDL), such as Verilog or VHDL. The HDL description may be synthesized against a library of cells designed for a given integrated circuit manufacturing technology and modified for timing, power, and other reasons, resulting in a final design database that can be sent to a foundry to generate masks and ultimately manufacture the integrated circuit. Some hardware circuits, or portions thereof, may also be custom designed in a schematic editor and incorporated into the integrated circuit design along with the synthesized circuit. An integrated circuit may include transistors and may further include other circuit elements (e.g., passive elements such as capacitors, resistors, inductors, etc.) and interconnections between the transistors and circuit elements. Some embodiments may implement multiple integrated circuits connected together to realize the hardware circuit, and / or some embodiments may use discrete elements. Alternatively, the HDL design may be integrated into or implemented in a programmable logic array, such as a field programmable gate array (FPGA).

[0011] As used herein, the terms "based on" or "depending on" are used to describe one or more factors that influence the determination. This term does not exclude the possibility that additional factors may influence the determination. That is, the determination may be based only on the specified factors, or on the specified factors as well as other unspecified factors. Consider the phrase "determining A based on B." This phrase specifies that B is a factor used to determine A or that influences the determination of A. This phrase does not exclude that the determination of A may also be based on some other factor, such as C. This phrase is intended to cover embodiments in which A is determined solely based on B. As used herein, the phrase "based on" is synonymous with the phrase "based at least in part on."

[0012] The specification includes reference to various embodiments to indicate that the disclosure is not intended to refer to any particular implementation, but rather to a range of embodiments falling within the spirit of the disclosure, including the appended claims. Particular features, structures, or characteristics may be combined in any suitable manner consistent with the disclosure.

[0013] Referring now to FIG. 1, a block diagram of one embodiment of a system including a memory system 10 and an integrated circuit 12 is shown. In the illustrated embodiment, the integrated circuit 12 is a system-on-chip (SOC), and other embodiments in this disclosure use SOCs as examples. However, any integrated circuit may be used in various embodiments. In the embodiment of FIG. 1, the memory 10 includes multiple main DRAM chips (DRAMs) 16A-16D and a cache DRAM 18. The main DRAMs 16A-16D include a physical layer circuit (PHY) 60A, and the cache DRAM 18 includes a PHY 60B. PHY 60A is connected to a PHY 60C in SOC 12, and PHY 60B is connected to a PHY 60D in SOC 12. More specifically, PHY 60C may be connected to a main memory controller (MC) block 28A, and PHY 60D may be connected to a cache controller block (CC) 28B, both of which may be part of the memory controller 28 (Mem) in FIG. 1.

[0014] Memory system 10 can include two different types of DRAM, and for these DRAMs, memory controller 28 of SOC 12 can independently control main DRAMs 16A-16D and cache DRAM 18. The combination of main DRAMs 16A-16D and cache DRAM 18 provides high bandwidth to memory agents in SOC 12, while also providing high overall storage capacity and low power. Storage capacity can be provided by main DRAMs 16A-16D, which can have memory designed for density and capacity. High bandwidth can be provided by a wide interface between cache DRAM 18 and SOC 12. The wider interface allows for clocking at slower clock speeds, saving power compared to the high-speed, narrow interface of traditional synchronous DRAMs. In one embodiment, the interface between cache DRAM 18 and SOC 12 and the interface between main DRAMs 16A-16D and SOC 12 may have different widths (e.g., cache DRAM 18 may have an interface that is more than twice as wide as main DRAMs 16A-16D, and in some embodiments, may be two to four times wider). Furthermore, cache DRAM 18 may include a relatively small memory array that is less dense but can achieve higher bandwidth with less energy. For example, the memory array may have more banks, a smaller page size, lower latency, more channels, etc., compared to conventional DRAM or DRAMs 16A-16D. In some embodiments, the memory array may include one or more of fewer memory cells per bit line, fewer memory cells per word line, and / or smaller banks compared to similar characteristics of DRAMs 16A-16D to reduce power. More specifically, in one embodiment, the memory array of cache DRAM 18 may trade off lower density than main DRAMs 16A-16D for reduced energy consumption.Lower density can be achieved in cache DRAM 18 by one or more of fewer memory cells per bit line, fewer memory cells per word line, more banks, and / or smaller banks (compared to main DRAMs 16A-16D). In one embodiment, cache DRAM 18 can have a memory array that is 4 to 16 times less dense, and preferably 6 to 8 times less dense, than the memory arrays of main DRAMs 16A-16D. Data path designs within the banks and from the banks to PHY 60B can be optimized. Furthermore, the data path from cache DRAM 18 to SOC 12 can be a point-to-point, low-capacitance, low-voltage connection.

[0015] When two types of DRAM form a memory system, in some embodiments, one of them can be optimized for bandwidth and the other can be optimized for capacity, achieving both the goals of increased bandwidth and increased capacity. Furthermore, energy efficiency can be managed in the high-bandwidth portion of the memory (which can be smaller / more compact and therefore less dense). The portion of the memory optimized for capacity can have a lower bandwidth goal and a gentler (longer) latency goal, because these goals can be served by the portion optimized for bandwidth. Similarly, the portion of the memory optimized for bandwidth can have a lower area efficiency goal, but can improve latency and energy efficiency. In some embodiments, an overall high-bandwidth, low-latency, energy-efficient, and large-capacity memory system can be achieved at low cost. In particular, by implementing the high density portion (main DRAMs 16A-16D) and the high bandwidth, low latency portion (cache DRAM 18) on separate chips that together form main memory system 10, it is possible to improve energy efficiency for each memory 16A-16D and 18, thereby providing a highly energy efficient memory solution that is also high performance and high bandwidth. Specific optimizations that may be made to each memory in various embodiments are discussed in further detail below with respect to Figures 12-14.

[0016] In one embodiment, cache DRAM 18 may implement a simplified command set to reduce the number of commands sent to cache DRAM 18 per access. For example, main DRAMs 16A-16D may include an activate command, a column address strobe (CAS) command for each read or write access, and an optional recharge command. On the other hand, cache DRAM 18 may support a read command for a read access and a write command for a write access. Within cache DRAM 18, a read or write command may trigger multiple internal operations, such as activation, one or more CAS reads or writes (respectively), and precharge. Because only a few commands are sent over the interface for a given access, energy consumption for the access may be reduced.

[0017] As shown, the memory controller 28 independently controls the main DRAMs 16A-16D and the cache DRAM 18. In particular, in one embodiment, a main memory controller block 28A and a cache controller block 28B are illustrated. The main memory controller block 28A can control the main DRAMs 16A-16D, and the cache controller block 28B can control the cache DRAM 18. Caching of data from the main DRAMs 16A-16D to the cache DRAM 18 is under the control of the memory controller 28 and can be performed by moving data from the main DRAMs 16A-16D to the cache DRAM 18 through the SOC 12. That is, the caching policy, allocation, and deallocation of cache lines can be determined by the memory controller 28. By storing frequently accessed data in the high-bandwidth, low-power cache DRAM 18, the effective memory bandwidth can be increased compared to that of the main DRAMs 16A-16D, while still benefiting from the large capacity of the main DRAMs 16A-16D. In addition to main memory controller block 28A and cache controller block 28B, additional circuitry in memory controller 28 may coordinate caching policies, data transfers, etc., or blocks 28A-28B may interact directly to perform caching operations.

[0018] Figure 2 is a block diagram of another embodiment of main DRAMs 16A-16D and cache DRAM 18 connected to SOC 12. In the embodiment of Figure 2, a single PHY 60D can be implemented in SOC 12, which is connected to a single PHY 60B in cache DRAM 18. There may be logic that can decode operations intended for main DRAMs 16A-16D, and the decoded operations can be forwarded to DRAMs 16A-16D through PHYs 60C and 60A as shown in Figure 2.

[0019] 3 is a block diagram of a third embodiment of the cache DRAM 18 connected to the main DRAMs 16A-16D and the SOC 12. In the embodiment of FIG. 3, separate PHYs 60D and 60C may be implemented for the cache controller block 28B to communicate with the cache DRAM 18 (PHY 60B) and for the main memory controller block 28B to communicate with the main DRAMs 16A-16B (PHY 60A). However, the cache DRAM 18 may act as a host for the transport layer to the main DRAMs 16A-16D, communicating with PHY 60F of the main DRAMs 16A-16D via PHY 60E, as shown in FIG.

[0020] 1-3 show, in some embodiments, the PHY protocol for cache DRAM 18 may be different from the PHY protocol for main DRAMs 16A-16D, and various configurations may support both protocols. In other embodiments, the same PHY protocol may be used.

[0021] FIGS. 4-7 illustrate the scalability of memory system 10 for different applications based on various embodiments that package cache DRAM 18 and main DRAMs 16A-16D with SOC 12. For example, in FIGS. 4 and 6, main DRAMs 16A-16D and cache DRAM 18 (i.e., main memory 10) are packaged separately from SOC 12. Small form factor devices, such as mobile phones, can use a system like that of FIG. 4, with memory system 10 on one side of SOC 12. Larger form factor devices, such as tablet computers, laptops, or desktop computers, can use an embodiment like that of FIG. 6, with memory system 10 formed from multiple sections on various sides of SOC 12 (e.g., sections 10A, 10B, 10C, and 10D in FIG. 6). Various embodiments can use any number of sections. FIGS. 5 and 7 illustrate embodiments in which SOC 12 and cache DRAM 18 are packaged together and interface to main DRAMs 16A-16D. FIG. 5 is similar to FIG. 4 and shows main DRAMs 16A-16D on one side of SOC 12 / cache DRAM 18, e.g., for small form factor devices such as mobile phones. However, for larger form factor devices, an embodiment such as FIG. 7 can be used. In FIG. 7, multiple instances of main DRAMs 16A-16D are shown on various sides of SOC 12 and cache DRAM 18. The cache DRAM 18 packaged with SOC 12 is also scalable in different implementations, as desired. See, for example, FIGS. 8 and 9 below. Any number of instances can be used in various embodiments. As previously mentioned, each of main DRAMs 16A-16D shown in FIGS. 4-7 can be a single DRAM or multiple DRAMs, as desired in various embodiments.

[0022] FIG. 8 is a block diagram of one embodiment of a system showing a package 50 including a SOC 12 and a cache DRAM 18. Optionally, some embodiments may include multiple instances of the cache DRAM 18 (e.g., a second cache DRAM 18 is shown in dashed form in FIG. 8). The package may also include a connection layer 14 including relatively short interconnects to the cache DRAM 18 (e.g., see FIG. 12 and discussion below for further details). One or more main DRAMs 16A-16D may be assembled with the SOC 12 / cache DRAM 18 in a package-on-package (POP) configuration using a POP substrate 52, which may be connected between the main DRAMs 16A-16D and the connection layer 14 (and further to the SOC 12 and to wiring in the connection layer 14 and POP substrate 52, not shown in FIG. 8). FIG. 9 is another example of POP packaging using one or more main DRAMs 16A-16D and a SOC 12 / cache DRAM 18. 9 embodiment, cache DRAM 18 (or in some embodiments, multiple cache DRAMs 18) is mounted on SOC 12 using any desired technique, such as chip-on-wafer (COW) packaging, wafer-on-wafer (WOW) packaging, and chip-on-chip (COC) packaging.

[0023] In other embodiments, main DRAM 16A-16D may be packaged separately from SOC 12 and cache DRAM 18. For example, FIGS. 10 and 11 show SOC 12 / cache DRAM 18 as shown in FIGS. 8 and 9, respectively, but with separately packaged main DRAM 16A-16D connected to a system substrate or main board 54. In some implementations, the embodiments of FIGS. 10 and 11 may be multi-chip modules (MCMs), and substrate 54 may be an MCM substrate. In other embodiments, main board 54 may be various types of circuit boards, such as a printed circuit board (PCB). While two sets of main DRAM 16A-16D are shown, each DRAM may be one or more DRAMs, and there may be one DRAM / DRAM set or multiple DRAM sets, as shown in FIGS. 6 and 7.

[0024] 12-14 illustrate various exemplary 2.5-dimensional (D) and 3D configurations of SOC 12, cache DRAM 18, and main DRAMs 16A-16D, although it should be noted that in other embodiments, any packaging solution may be used, including various other 2.5D and / or 3D solutions.

[0025] Referring now to FIG. 12, a block diagram of one embodiment of a system including a memory system 10 and a SOC 12 connected through a connection layer 14 is shown. In the embodiment of FIG. 1, memory 10 includes multiple main DRAM chips (DRAMs) 16A-16D and a cache DRAM 18. Each main DRAM 16A-16B includes one or more memory arrays 20A-20H, as shown in FIG. 1. Cache DRAM 18 includes a memory array 22 and a physical layer interface circuit (PHY circuit 24). PHY circuit 24 is connected to connection layer 14 through pins of cache DRAM 18, connected through connection layer 14 to pins of SOC 12, and then connected to a corresponding PHY circuit 26 of SOC 12. PHY 26 is connected to a memory controller 28 of SOC 12, which further includes various other circuits 30 (e.g., a processor, peripherals, etc.). The other circuits 30 are connected to the other side of connection layer 14 through other pins of SOC 12 and may be connected to other components of the system.

[0026] As mentioned above, memory system 10 can include two different types of DRAMs, for which memory controller 28 of SOC 12 can independently control main DRAMs 16A-16D and cache DRAM 18. Note that while one PHY circuit 24 and one PHY circuit 26 are shown in the embodiment of Figure 1, other embodiments can have separate PHY circuits 24 and 26 for cache DRAM 18 and for main DRAMs 16A-16D, as described above with respect to PHY circuits 60A-60D (and 60E and 60F in the embodiment of Figure 3).

[0027] As described above, memory arrays 20A-20H can be designed for density to provide high storage capacity per unit area of ​​DRAMs 16A-16D. DRAMs 16A-16D can implement, for example, a larger page size compared to cache DRAM 18. DRAMs 16A-16D can include fewer banks compared to cache DRAM 18. To further increase density, some control logic for DRAMs 16A-16D, such as test circuitry, redundancy control, error correction code (ECC) mechanisms, reference voltage logic, and temperature control reference logic, can be located on cache DRAM 18.

[0028] Smaller page sizes in cache DRAM 18 (and larger numbers of open pages due to the increased number of banks in cache DRAM 18) may encourage frequent small accesses (compared to the page size) by a large number of memory agents in SOC 12. For example, processors tend to read only one or a few cache lines of data, where traditional page sizes in DRAM may be 2-4 kilobytes in size. Each time a page is opened, the entire page of data is read from the memory array and can be captured in sense amplifiers and / or registers for access. When that page is closed and a new page is opened, the entire new page of data is read. On the other hand, reading smaller pages consumes proportionally less power. When a large number of agents are competing for access to memory, page contention and page opens / closes may become more frequent, and reduced power consumption per page can result in reduced overall power consumption.

[0029] Thus, memory controller 28 can be configured to write data read from main DRAM 16A-16D to cache DRAM 18 if the data can be reused. Various caching schemes can be used. However, cache DRAM 18 is denser than on-SOC static RAM (SRAM), allowing for larger caches to be implemented than would be possible using SRAM. Furthermore, DRAM contains fewer transistors per bit of stored data than SRAM (e.g., one transistor per bit compared to six transistors per bit), and therefore DRAM has lower leakage power than SRAM on a per-bit basis. Furthermore, in some embodiments, the silicon die area savings of SOC 12 by eliminating on-chip memory cache can offset the expense of cache DRAM 18 to some extent.

[0030] The main DRAMs 16A-16D may employ through-silicon via (TSV) interconnects (e.g., TSV 32 shown in FIG. 12 ) to reduce interconnect length and capacitance. The TSV 32 may be formed, for example, using known TSV fabrication techniques. The TSV 32 may connect to each other when the DRAMs 16A-16D are stacked between the memories through pins. The DRAM 16D (the main DRAM at the bottom of the stack) may connect to the cache DRAM 18 through pins, which may route signals to the PHY circuit 24. The PHY circuit 24 may have output terminals to and / or input terminals from the PHY circuit 26 physically located along the edges of the cache DRAM 18, and the input / output terminals of the PHY circuit 26 may be similarly physically located along the edges of the SOC 12. In this manner, short wiring paths through the connection layer 14 may be used to connect the PHY circuits 24 / 26. PHY circuits 24 and 26 can be designed to communicate with small, fixed loads through connection layer 14 via relatively short interconnects, allowing the use of small, low-power drivers compared to conventional DRAM interfaces that have longer interconnects and multiple DRAM loads.

[0031] Additionally, the TSVs can be more freely located within the main DRAMs 16A-16D because the cache DRAM 18 routes the TSV interconnects to desired locations at the edges of the cache DRAM 18. In some embodiments, this can reduce congestion and provide more interconnects than is possible in conventional DRAMs.

[0032] While the illustrated embodiment uses TSVs, other embodiments may use silicon interposer interconnect or fanout technology, such as integrated fanout (InFO) available from Taiwan Semiconductor Manufacturing Company™ (TSMC). The pins referred to herein may be any form of chip-to-chip interconnect. For example, the pins may be "microbumps," or may be solder balls or other pin-forming materials. While other embodiments explicitly show solder balls, other pin configurations may be used in those embodiments as well.

[0033] The connection layer 14 may be any form of chip-to-chip interconnect, for example, the connection layer 14 may be a silicon interposer, a redistribution layer, a ceramic, an organic, or a printed circuit board-like substrate.

[0034] 13 is a block diagram of another embodiment of memory system 10 on SOC 12. In the embodiment of FIG. 2, the pins connecting PHY circuit 24 to PHY circuit 26 do not need to be on one edge because the packages are directly connected rather than through connection layer 14. Pins (not shown) on the bottom side of SOC 12 can be used to connect the SOC to the rest of the system. As mentioned above, other embodiments can have separate PHY circuits 24 for cache DRAM 18 and for main DRAMs 16A-16D.

[0035] 14 is a block diagram of a third embodiment of a memory system in which cache DRAM 18 is implemented in a stack with SOC 12 and main DRAMs 16A-16D are connected to SOC 12 through connection layer 14. In this embodiment, main DRAMs 16A-16D are stacked on a base die 40, which routes signals from TSVs 32 to PHY circuit 24 and then to PHY 26 in SOC 12 through short (edge-near) interconnects.

[0036] The DRAM 18 and the SOC 12 can be connected using various packaging techniques. Either the DRAM 18 or the SOC 12 can be the "top" chip (where "top" is relative to the orientation of FIG. 14). Any 3D chip packaging technique can be used. For example, in various embodiments, one or more of TSV connections, COW packaging, WOW packaging, POP packaging, etc. can be used.

[0037] Numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated, and it is intended that the following claims be interpreted to embrace all such variations and modifications.

Claims

1. at least one first integrated circuit including a first type of dynamic random access memory (DRAM); at least one second integrated circuit including a second type of DRAM, the second type of DRAM having a lower density than the first type of DRAM, and accessing the second type of DRAM consuming less energy than accessing the first type of DRAM; a third integrated circuit packaged with the second integrated circuit, the third integrated circuit reducing the length and capacitance of a connection between the third integrated circuit and the second integrated circuit compared to a connection between the first integrated circuit and the third integrated circuit, the third integrated circuit including a memory controller configured to control access to the memory; A system comprising:

2. 2. The system of claim 1, wherein the second integrated circuit includes the first type of DRAM and the second type of DRAM and comprises a physical layer circuit configured to communicate for the memory.

3. 2. The system of claim 1, further comprising a plurality of said first integrated circuits including a plurality of said first type of DRAMs.

4. The system of claim 3 , wherein the plurality of first integrated circuits are connected in a stack by through-silicon via (TSV) interconnects.

5. 4. The system of claim 3, wherein the stack of the plurality of first integrated circuits is connected to the second integrated circuit, and the TSV interconnects are connected to physical layer circuitry of the second integrated circuit.

6. the second DRAM is connected to the physical layer circuit; 6. The system of claim 5, wherein the physical layer circuitry includes a communication line for the first plurality of DRAMs to the third integrated circuit and a communication line for the second DRAM to the third integrated circuit.

7. The system of claim 1 , wherein the second integrated circuit and the third integrated circuit are packaged using chip-on-wafer packaging techniques.

8. The system of claim 1 , wherein the second integrated circuit and the third integrated circuit are packaged using wafer-on-wafer packaging techniques.

9. The system of claim 1 , wherein the second integrated circuit and the third integrated circuit are packaged using chip-on-chip packaging techniques.

10. The system of claim 1 , wherein the first integrated circuit is stacked on a package of the second integrated circuit and the third integrated circuit.

11. 11. The system of claim 10, wherein the first integrated circuit is packaged in a package-on-package configuration with the package containing the second integrated circuit and the third integrated circuit.

12. 10. The system of claim 1, wherein the first integrated circuit is disposed on a side of the package containing the first integrated circuit and the second integrated circuit.

13. 2. The system of claim 1, wherein the first integrated circuit is one of a plurality of first integrated circuits, the plurality of first integrated circuits being disposed on multiple sides of the package containing the second integrated circuit and the third integrated circuit.

14. 2. The system of claim 1, wherein the memory controller is configured to cache data from a plurality of DRAMs, the first type of DRAM, in at least one second DRAM of the second type of DRAM.

15. 2. The system of claim 1, wherein the second type of DRAM includes fewer memory cells per bit line than the first type of DRAM.

16. 2. The system of claim 1, wherein said second type DRAM includes fewer memory cells per word line than said first type DRAM.

17. 2. The system of claim 1, wherein the second type of DRAM includes fewer banks than the first type of DRAM.

18. 2. The system of claim 1, wherein the second type of DRAM includes more banks than the first type of DRAM.

19. 2. The system of claim 1, wherein the second type of DRAM is between 4 and 16 times less dense than the first type of DRAM.

20. 20. The system of claim 19, wherein the second type of DRAM is six to eight times less dense than the first type of DRAM.

21. the predetermined access to the first type of DRAM includes a plurality of commands via a first interface to the first integrated circuit; 2. The system of claim 1, wherein a given access to the second type of DRAM comprises a single command via a second interface to the second integrated circuit.

22. a memory including a first type of dynamic random access memory (DRAM) in at least one first integrated circuit and a second type of DRAM in at least one second integrated circuit, the first type of DRAM and the second type of DRAM differing in at least one characteristic, the second integrated circuit including a first physical layer circuit; a third integrated circuit coupled to the memory, the third integrated circuit including a memory controller and a second physical layer circuit; A system comprising: the first physical layer circuit is connected to the second physical layer circuit and configured to communicate with the second physical layer circuit for both the first integrated circuit and the second integrated circuit.

23. 23. The system of claim 22, wherein the at least one first integrated circuit is a plurality of integrated circuits in a stack, the plurality of integrated circuits being connected to the first physical layer circuit.

24. 24. The system of claim 23, wherein the plurality of integrated circuits include through silicon vias forming a portion of an interconnect to the first physical layer circuitry.

25. 23. The system of claim 22, wherein the memory controller is configured to operate the second type of DRAM as a cache for the first type of DRAM.

26. 23. The system of claim 22, wherein the second type of DRAM has a higher bandwidth than the first type of DRAM.

27. 23. The system of claim 22, wherein the second type of DRAM has a lower latency than the first type of DRAM.

28. 23. The system of claim 22, wherein the first type of DRAM is denser than the second type of DRAM.

29. one or more first integrated circuits including a first dynamic random access memory (DRAM) of a first type; a second integrated circuit connected to the one or more first integrated circuits in the stack, the second integrated circuit including a second DRAM of a second DRAM type, the second integrated circuit further including physical layer circuitry configured to communicate for the first DRAM and the second DRAM; A memory comprising:

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