Storage system and storage system management method

Abstract

To provide a storage system and a storage system management method that are capable of providing continuous I / O processing by switching a queue used for I / O control on a controller side.SOLUTION: A storage system includes a first protocol chip and a second protocol chip for receiving I / O commands from a host, and a first controller including a first CPU and a second controller including a second CPU. In accordance with an instruction from the first controller, the first protocol chip halts the first CPU, and switches a Qset for sending the I / O commands received by the first protocol chip from Qset 11 to Qset 12.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a storage system and a method for managing a storage system. [Background technology]

[0002] The storage system comprises a protocol chip and a controller. The protocol chip receives IO commands from the host and sends them to the controller. The controller receives IO commands from the protocol chip and performs IO control. In the storage system, a configuration is adopted in which the protocol chip and the controller are connected in a one-to-one relationship via a PCI (Peripheral Component Interconnect) bus.

[0003] The interface between the protocol chip and the controller's CPU uses a queue control method, and the CPU uses a queue to receive IO commands received by the protocol chip and to request IO processing from the protocol chip. A queue is assigned to each core or each CPU.

[0004] Controllers sometimes use multi-core CPUs with AMP (Asymmetrical Multiprocessing)-OS. In an AMP-OS CPU, a separate operating system (OS) runs on each core. When updating the OS, it is possible to update each OS running on each core of the CPU individually. Therefore, even if the protocol chip and controller are connected in a one-to-one relationship, cores other than the one being updated can take over IO control, allowing for non-disruptive OS updates without stopping IO control for communication with the host server.

[0005] In contrast, controllers may use multi-core CPUs with SMP (Symmetric Multiprocessing)-OS. In an SMP-OS CPU, one OS runs on multiple cores. When updating the OS, the protocol chip and controller are connected in a one-to-one relationship, and the OS cannot be updated for each core as with an AMP-OS CPU, so multiple cores of the CPU must be stopped simultaneously.

[0006] When the CPU is completely stopped, there are no CPU cores in charge of IO processing, and so there are no cores left to handle IO processing. The queues also become unusable, and the IO control information contained in them is lost. Furthermore, all IO commands received by the protocol chip from the host server while the CPU was stopped are lost. These issues mean that SMP-OS updates can cause IO processing to stop and the link with the host server to be severed.

[0007] Such problems can also occur in other cases, such as when a fault occurs that stops the entire CPU. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] Special Publication No. 2012-514776 [Patent Document 2] International Publication No. 2016 / 006111 Summary of the Invention [Problem to be solved by the invention]

[0009] Therefore, when all CPUs of a controller are stopped, a mechanism is required to continue IO control by switching the queue used for IO control on the controller side from the queue assigned to the stopped CPU to a queue assigned to another controller CPU that is not stopped. Note that Patent Documents 1 and 2 do not describe a mechanism for switching the queue used for IO control on the controller side from the queue assigned to the stopped CPU to a queue assigned to another controller CPU that is not stopped, as in the present invention.

[0010] One object of the present invention is to provide a storage system and a storage system management method that can continue IO processing by switching the queue used for IO control on the controller side. [Means for solving the problem]

[0011] In order to solve the above problem, the storage system of the present invention includes a first protocol chip and a second protocol chip that receive IO commands from a host, a first controller having a first CPU to which a queue used for control communication with the first protocol chip and a queue used for control communication with the second protocol chip are assigned, a second controller having a second CPU to which a queue used for control communication with the first protocol chip and a queue used for control communication with the second protocol chip are assigned, and a communication path between the first protocol chip and the first CPU and the second CPU, the communication path being provided between the first protocol chip and the first CPU, and the second CPU. a first PCI switch that sets a communication path between the second protocol chip and the second CPU, and a second PCI switch that is provided between the second protocol chip and the first CPU and a communication path between the second protocol chip and the second CPU, wherein each of the first protocol chip and the second protocol chip has queue control information that specifies a queue to which the IO command received from the host is to be sent, and the first PCI switch and the second PCI switch set the communication path through which the IO command passes to the communication path in accordance with the queue control information.

[0012] a first communication path between the first protocol chip and the first controller, a second communication path between the second protocol chip and the second controller, a third communication path between the first protocol chip and the second controller, and a fourth communication path between the second protocol chip and the first controller; a first PCI switch for switching the communication path through which the IO commands received by the first protocol chip are passed to either the first communication path or the third communication path in response to a command from the controller; and a second PCI switch for switching the communication path through which the IO commands received by the second protocol chip are passed to either the second communication path or the fourth communication path in response to a command from the controller.

[0013] The method for managing a storage system of the present invention includes a first protocol chip and a second protocol chip that receive IO commands from a host, a first controller having a first CPU to which a queue used for control communication with the first protocol chip and a queue used for control communication with the second protocol chip are assigned, a second controller having a second CPU to which a queue used for control communication with the first protocol chip and a queue used for control communication with the second protocol chip are assigned, and a communication path between the first protocol chip and the first CPU and a communication path between the first protocol chip and the second CPU that is provided between the first protocol chip and the first CPU and a communication path between the first protocol chip and the second CPU. a second protocol chip, and a second PCI switch provided between the first CPU and the second CPU, the second PCI switch setting a communication path between the second protocol chip and the first CPU and a communication path between the second protocol chip and the second CPU, wherein each of the first protocol chip and the second protocol chip has queue control information that specifies a queue to which the IO command received from the host is to be sent, and the first PCI switch and the second PCI switch set the communication path through which the IO command passes to the communication path in accordance with the queue control information. [Effects of the Invention]

[0014] According to the present invention, the IO processing can be continued by switching the queue used for IO control on the controller side. Note that the effects described here are not necessarily limited to those described herein, and may be any of the effects described in this disclosure. [Brief explanation of the drawings]

[0015] [Figure 1] FIG. 1 is a diagram showing an example of the configuration of a system including a storage system according to an embodiment. [Figure 2] FIG. 2 is a diagram for explaining the interruption table. [Figure 3] FIG. 3 is a diagram for explaining the OXID table. [Figure 4] FIG. 4 is a diagram for explaining the port management table. [Figure 5] FIG. 5 is a diagram for explaining the queue combination table. [Figure 6] FIG. 6 is a diagram for explaining IO control before queue switching. [Figure 7] FIG. 7 is a diagram for explaining control when issuing a queue switching instruction. [Figure 8] FIG. 8 is a diagram for explaining control after a queue switching instruction is issued. [Figure 9] FIG. 9 is a diagram for explaining control after a queue switching instruction is issued. [Figure 10] FIG. 10 is a diagram for explaining control after a queue switching instruction is issued. [Figure 11] FIG. 11 is a diagram for explaining control after a queue switching instruction is issued. [Figure 12] FIG. 12 is a diagram for explaining control after the queue switching is completed. [Figure 13] FIG. 13 is a flowchart showing the process flow of the queue creation process executed by the CPU. [Figure 14] FIG. 14 is a flowchart showing the process flow of the queue combination table update process executed by the first protocol chip using FW (Firmware). [Figure 15] FIG. 15 is a flowchart showing the process flow of the RQ queue processing executed by the first protocol chip using FW. [Figure 16] FIG. 16 is a flowchart showing the process flow of the queue processing of the WQ executed by the first protocol chip using the FW. [Figure 17] FIG. 17 is a flowchart showing the process flow of the CQ queue processing executed by the first protocol chip using FW. [Figure 18]FIG. 18 is a flowchart showing the process flow of the queue switching process executed by the first protocol chip using FW. [Figure 19A] FIG. 19A is a flowchart showing the process flow of the queue switching process executed by the first CPU according to a program. [Figure 19B] FIG. 19B is a flowchart showing the process flow of the queue switching process executed by the first CPU according to a program. [Figure 20A] FIG. 20A is a sequence diagram showing the operation when updating the SMP-OS running on the first CPU. [Figure 20B] FIG. 20B is a sequence diagram showing the operation when updating the SMP-OS running on the first CPU. DETAILED DESCRIPTION OF THE INVENTION

[0016] Hereinafter, embodiments of the present invention will be described with reference to the drawings. Note that in all drawings of the embodiments, the same or corresponding parts may be assigned the same reference numerals. In the following description, various information may be described using expressions such as "table," "record," "column," and "row," but the various information may be expressed using data structures other than these. Furthermore, when describing identification information, expressions such as "number," "name," and "identifier" are used, but these are interchangeable. Furthermore, when describing identification information, other expressions may be used.

[0017] <<Embodiment>> A storage system 200 according to an embodiment of the present invention will now be described. Fig. 1 shows an example of the configuration of a system including the storage system 200 according to the embodiment. As shown in Fig. 1, the system includes host servers 100a and 100b, and a storage system 200. Note that host servers 100a and 100b may be referred to as "host servers 100" or "hosts" when there is no need to particularly distinguish between them.

[0018] The host server 100 and storage system 200 are connected via a SAN (Storage Area Network) and a fibre channel switch 300 so that data can be sent and received.

[0019] The Fibre Channel switch 300 has multiple ports and connects multiple host servers 100 to a first controller unit 400a and a second controller unit 400b of the storage system 200. The Fibre Channel switch 300 controls the sending and receiving of data, and ensures network availability and performance.

[0020] The host server 100 is a computer (server device) that issues IO requests. The host server 100 may be a physical computer or a virtual computer. The host server 100 includes an HBA (host bus adapter).

[0021] The storage system 200 includes a first controller unit 400a, a second controller unit 400b, and a plurality of drive boxes 500. When there is no particular need to distinguish between the first controller unit 400a and the second controller unit 400b, they may be referred to as "controller units 400." The first controller unit 400a and the second controller unit 400b may also be referred to as "storage controllers 400."

[0022] The first controller unit 400a includes a first controller 410a, a first CHB 420a, a first PCI switch 430a, a first DKB 440a, and a first GUM 450a.

[0023] The first controller 410a includes a first CPU 411a, two first DIMMs 412a, a first CFM 413a, a first LANC 414a, a first GCTL 415a, a first NTB 416a, and a first environmental microcomputer 417a.

[0024] The first CPU 411a is a multi-core processor with four built-in cores. Each core executes calculations independently and executes multiple processes in parallel. An SMP (Symmetric Multiprocessing)-OS runs on the first CPU 411a.

[0025] The first DIMM 412a is a memory module (Dual In-line Memory Module) in which multiple DRAM chips are mounted on a printed circuit board. Multiple queues are created in the first DIMM 412a. The first DIMM 412a may be referred to as the "first memory 412a."

[0026] The first CFM 413a is a cache flash memory.

[0027] The first LANC 414a is a controller (Local Area Network Controller) that manages data communication within a LAN (Local Area Network) and ensures efficient communication between devices.

[0028] The first GCTL 415a is a control device for setting and controlling the controllers. The first NTB 416a is a non-transparent bridge connected to the first CPU 411a. The first NTB 416a is a device for connecting the first controller 410a and the second controller 410b so that they can communicate with each other. The first CPU 411a and the second CPU 411b are connected so that they can communicate with each other via a non-transparent link. The first environmental microcomputer 417a is a microcomputer used to monitor, control, or manage environmental conditions.

[0029] The first CHB (Channel Board) 420a is a board for controlling data transfer between the storage system 200 and the host server 100. The first CHB 420a includes an FC port 420a1 (see FIG. 6, etc.) and a first protocol chip 421a that is responsible for communication between the storage system 200 and the host server 100.

[0030] The FC port 420a1 is a Fibre Channel port for connecting the first CHB 420a to the host server 100 via a SAN. The first protocol chip 421a is an ASIC chip (Application-Specific Integrated Circuit) for processing a communication protocol between the storage system 200 and the host server 100. The first protocol chip 421a processes IO commands from the host server 100 to a drive 501 (volume) associated with the host server 100, and controls data transfer between the host server 100 and the drive 501 (volume).

[0031] The first PCI switch 430a connects multiple PCI devices and coordinates communication between these devices. The first PCI switch 430a has multiple ports, and connects PCI devices to each PCI port. Specifically, the first PCI switch 430a has a port connected to the first protocol chip 421a, a port connected to the first CPU 411a, and a port connected to the second CPU 411b.

[0032] The first DKB (Disk Board) 440a is an interface that connects the first controller 410a and the drive box 500.

[0033] The first GUM (Gateway for Unified Management) 450a is a computer that has basic maintenance and management functions for the storage system 200. When maintaining and managing the storage system 200 from the outside, communication is performed with the first GUM 450a.

[0034] The second controller unit 400b includes a second controller 410b, a second CHB 420b, a second PCI switch 430b, a second DKB 440b, and a second GUM 450b. The second CHB 420b includes an FC port 420b1 (see FIG. 6, etc.) and a second protocol chip 421b that handles communication between the storage system 200 and the host server 100.

[0035] The second controller 410b includes a second CPU 411b, two second DIMMs 412b, a second CFM 413b, a second LANC 414b, a second GCTL 415b, a second NTB 416b, and a second environment microcomputer 417b. The second DIMMs 412b may be referred to as the "second memory 412b."

[0036] The details of the second CPU 411b, two second DIMMs 412b, second CFM 413b, second LANC 414b, and second environment microcomputer 417b are similar to those of the first CPU 411a, two first DIMMs 412a, first CFM 430a, first LANC 414a, and first environment microcomputer 417a. The second CHB 420b (second protocol chip 421b), second PCI switch 430b, second DKB 440b, and second GUM 450b are similar to those of the first CHB 420a (first protocol chip 421a), first DKB 440a, and first GUM 450a. The second PCI switch 430b has a port connected to the second protocol chip 421b, a port connected to the first CPU 411a, and a port connected to the second CPU 411b.

[0037] The first controller 410a and the second controller 410b may be referred to as the "controller 410" when there is no need to distinguish between them. The first CPU 411a and the second CPU 411b may be referred to as the "CPU 411" when there is no need to distinguish between them. The first DIMM 412a and the second DIMM 412b may be referred to as the "DIMM 412" when there is no need to distinguish between them. The first CHB 420a and the second CHB 420b may be referred to as the "CHB 420" when there is no need to distinguish between them. The first protocol chip 421a and the second protocol chip 421b may be referred to as the "protocol chip 421" when there is no need to distinguish between them.

[0038] The first CHB 420a (first protocol chip 421a) is communicatively connected to the first controller 410a (first CPU 411a) and the second controller 410b (second CPU 411b) via a PCI (Peripheral Component Interconnect) bus 431 and a first PCI switch 430a.

[0039] The second CHB 420b (second protocol chip 421b) is communicatively connected to the first controller 410a (first CPU 411a) and the second controller 410b (second CPU 411b) via a PCI (Peripheral Component Interconnect) bus 431 and a second PCI switch 430b.

[0040] The PCI bus 431 between the first protocol chip 421a and the first controller 410a (first CPU 411a) may be referred to as the "first communication path."

[0041] The PCI bus 431 between the second protocol chip 421b and the second controller 410b (second CPU 411b) may be referred to as a "second communication path."

[0042] The PCI bus 431 between the first protocol chip 421a and the second controller 410b (second CPU 411b) may be referred to as a "third communication path."

[0043] The PCI bus 431 between the second protocol chip 421b and the first controller 410a (first CPU 411a) may be referred to as a "fourth communication path."

[0044] The first PCI switch 430a is configured to be able to switch the communication path through which the IO command received by the first protocol chip 421a passes between the first communication path and the third communication path. The first protocol chip 421a refers to the queue combination table 5000 (FIG. 5) and instructs the first PCI switch 430a on the IO command to be sent and the destination of the IO command (first CPU 411a (communication path)). In response to the instruction, the first PCI switch 430a switches the communication path through which the IO command passes between the first communication path and the third communication path.

[0045] The second PCI switch 430b is configured to be able to switch the communication path through which the IO command received by the second protocol chip 421b passes between the second communication path and the fourth communication path. The second protocol chip 421b refers to the queue combination table 5000 and instructs the second PCI switch 430b on the IO command to be sent and the destination of the IO command (the second CPU 411b (communication path)). In response to the instruction, the second PCI switch 430b switches the communication path through which the IO command passes between the first communication path and the third communication path.

[0046] The drive box 500 is equipped with a plurality of drives 501 such as SSDs and HDDs, and an ENC (drive enclosure) 502. The plurality of drives 501 equipped in the drive box 500 constitute a plurality of volumes, which are logical recording areas that are the targets of IO requests from the host server 100.

[0047] 2 is a diagram illustrating the interruption table 2000. The interruption table 2000 is stored in the DIMM 412. As shown in FIG. 2, the interruption table 2000 includes columns for storing information (values), such as #1 2001, Chip #2002, Port #2003, Host #2004, Processor #2005, OX_ID 2006, RX_ID 2007, SEQ_ID 2008, Command 2009, and interruption flag 2010. In the interruption table 2000, information corresponding to each column regarding IOs interrupted on the first CPU 411a side when completing the queue switching process is associated with each other and stored as row-by-row information (records).

[0048] Specifically, #1 2001 stores an identification number for identifying each row (record). Chip #2002 stores an identification number for identifying the protocol chip 421. Port #2003 stores an identifier for identifying a port of the CHB 420. Host #2004 stores an identifier for identifying the host server 100 (a port of the host server 100). Processor #2005 stores the name of the processor (CPU 411) for identifying the processor (CPU 411). OX_ID 2006 stores an exchange ID assigned by the host server 100 to one IO command. RX_ID 2007 stores an exchange ID assigned by the protocol chip 421 to one IO command. SEQ_ID 2008 stores a sequence identifier that specifies a frame group being exchanged between the protocol chip 421 and the host server 100. Command 2009 stores the type of IO command. The interruption flag 2010 stores information (flag) indicating the execution state of IO.

[0049] FIG. 3 is a diagram illustrating the OXID table 3000. The OXID table 3000 is stored in an internal memory incorporated in the protocol chip 421. As shown in FIG. 3, the OXID table 3000 includes columns for storing information (values): #1 3001, Chip #3002, Port #3003, Host #3004, Uncompleted OX_ID 3005, RX_ID 3006, and Completed flag 3007. In the OXID table 3000, information corresponding to each column regarding remaining IOs after the queue switching process has started is stored as information (records) in rows, in association with each other, as columns for storing information (values). Remaining IOs refer to IOs in progress (being processed) in the queue from which the queue is being switched.

[0050] Specifically, #1 3001 stores an identification number for identifying each row (record). Chip #3002 stores an identification number for identifying the protocol chip 421. Port #3003 stores an identifier for identifying a port of the CHB 420. Host #3004 stores an identifier for identifying the host server 100 (a port of the host server 100). Incomplete OX_ID 3005 stores an exchange ID assigned by the host server 100 to one IO command. RX_ID 3006 stores an exchange ID assigned by the protocol chip 421 to one IO command. Completion flag 3007 stores information (flag) indicating the completion status of the IO. Incomplete indicates a state in which the corresponding IO has not been completed. Suspended indicates that the corresponding IO is suspended. Suspended completed indicates that the corresponding suspended IO has been completed. Transfer completion indicates that the data transfer for the corresponding IO has finished, the exchange is in a completed state, and the IO control information (IO resources) has been released.

[0051] 4 is a diagram illustrating the port management table 4000. The port management table 4000 is stored in the DIMM 412 on the CPU 411 side where the target port is located. As shown in FIG. 4, the port management table 4000 includes columns for storing information (values): #1 4001, Chip #4002, Port #4003, Host #4004, and LU #4005.

[0052] In the port management table 4000, information corresponding to each column regarding the correspondence between the host server 100, the port, and the drive 501 accessible by the host server 100 is stored as information (records) in rows, with the information corresponding to each column being associated with each other as columns for storing information (values). Specifically, #1 4001 stores an identification number for identifying each row (record). Chip #4002 stores an identification number for identifying the protocol chip 421. Port #4003 stores an identifier for identifying the port of the CHB 420. Host #4004 stores an identifier for identifying the host server 100. LU #4005 stores the Logical Unit number of the volume accessible by the corresponding host server 100.

[0053] When performing IO control, the protocol chip 421 manages, for each of its own ports (D_ID), the assignment of the port (S_ID) of the connected host server 100 and the Logical Unit numbers of the volumes accessible by that host server 100. The CPU 411 maintains the correspondence between the ID of the host server 100, the ID of its own port, and the Logical Unit numbers of the volumes in a port management table 4000. The CPU 411 executes IO operations using the control information maintained in this port management table 4000. Note that if conventional technology is used, the own port will stop (the path on the side of the controller 410 performing the OS update will stop), so it is necessary to switch the port ID assigned to the host server 100 from the port ID corresponding to the first controller 410a to the port ID corresponding to the second controller 410b before starting the OS update. In contrast, in this embodiment, the path on the side of the controller 410 that is performing the OS update is stopped, but the path on the side of the controller 410 that is not performing the OS update is not stopped, so the correspondence between the port ID and the ID of the host server 100 can be maintained, and there is no need to switch the port ID assigned to the host server 100.

[0054] Fig. 5 is a diagram for explaining the queue combination table 5000. The queue combination table 5000 is stored in an internal memory built into the protocol chip 421. Fig. 5 shows the queue combination table 5000 stored in the internal memory of the first protocol chip 421a. The queue combination table 5000 is sometimes referred to as "queue control information."

[0055] 5, the queue combination table 5000 includes columns for storing information (values), such as Port # 5001, CPU # 5002, Qset allocation 5003, command transfer flag 5004, RQ status 5005, WQ status 5006, and CQ status 5007. The queue combination table 5000 stores, as columns for storing information (values), information corresponding to each column relating to the correspondence between the CPU 411 and the Qset allocated to the CPU 411 and the destination of the IO command, in correspondence with each other, as information (records) on a row-by-row basis. Specifically, the Port # 5001 stores an identifier of a port of the CHB 420. The CPU # 5002 stores the name of the CPU 411 for identifying the CPU 411. The Qset allocation 5003 stores the name of the Qset allocated to the CPU 411. The command transfer flag 5004 stores information indicating whether or not transfer of a command to the corresponding Qset is permitted ("enabled" or "disabled"). The RQ status 5005 stores information indicating the operating status of the RQ of the corresponding Qset. The WQ status 5006 stores information indicating the operating status of the WQ of the corresponding Qset. The CQ status 5007 stores information indicating the operating status of the CQ of the corresponding Qset.

[0056] <Summary> <Basic operation> First, to facilitate understanding of the present invention, we will explain IO control, which is the basic operation of the protocol chip 421 and the CPU 411 of the controller 410. The protocol chip 421 has a receive queue buffer. The receive queue buffer is an area for temporarily storing data and is located in internal memory built into the protocol chip 421. The protocol chip 421 temporarily stores IO commands received from the host server 100 in the receive queue buffer. Control communication between the protocol chip 421 and the CPU 411 uses queue control to exchange IO control information. The protocol chip 421 and the CPU 411 perform IO control using Qsets assigned to them. The Qset includes an RQ that receives IO commands asynchronously from the protocol chip 421, a WQ that is a message send queue that requests IO execution, and a CQ that is a message receive queue that receives completion of IO data transfer initiated by an IO execution request.

[0057] The protocol chip 421 monitors the RQ, and when there is space in the RQ, it loads the IO commands accumulated in the receive queue buffer into the RQ. The CPU 411 of the controller 410 monitors the RQ, and by reaping and processing the IO commands queued (held) in the RQ, it interprets the IO commands and initiates an IO transfer request.

[0058] The CPU 411 of the controller 410 monitors the WQ, and when there is free space in the WQ, loads the initiated IO transfer request into the WQ and stores the data to be transferred by the IO transfer request in a data buffer. The data buffer is a storage area for temporarily storing data, and is provided in the DIMM 412, for example.

[0059] The protocol chip 421 receives IO transfer requests by monitoring the WQ and reaping and processing IO transfer requests queued (held) by the WQ.

[0060] When the protocol chip 421 receives an IO transfer request, it performs data transfer. In response to the IO transfer request, data is transferred from the host server 100 to the protocol chip 421, or data is transferred from the protocol chip 421 to the host server 100 (in this example, an example is shown in which data is transferred from the protocol chip 421 to the host server 100).

[0061] The protocol chip 421 monitors the CQ, and when the IO transfer is completed, it places a notification of the IO transfer completion in the CQ. Note that one IO transfer completion is placed in the CQ for one IO transfer request. The CPU 411 receives the notification of the IO transfer completion by monitoring the CQ and acquiring the notification of the IO transfer completion from the CQ. This completes the IO control for processing one IO command.

[0062] <Operation overview> 6 to 12, an example will be described in which the first CPU 411a is stopped in response to a command from the first controller 410a, and the Qset to which the first protocol chip 421a sends IO commands is switched from Qset11 to Qset12. Such a Qset switch is performed when updating the SMP-OS running on the CPU 411. In the SMP-OS CPU 411, one OS runs on multiple cores. When updating the OS, the protocol chip 421 and the controller 410 are connected in a one-to-one relationship, and multiple cores of the CPU 411 must be stopped simultaneously. If the CPU 411 is completely stopped, there will be no CPU core responsible for IO processing, resulting in no cores being responsible for IO processing. Furthermore, the queue becomes unusable, and the IO control information stored in the queue is lost. Furthermore, all IO commands received by the protocol chip 421 from the host server 100 while the CPU 411 was stopped may be lost. Therefore, when the first CPU 411a of the first controller 410a is completely stopped to update the SMP-OS, the queue used for IO control is switched from the queue assigned to the stopped first CPU 411a to the queue assigned to the second CPU 411b of another second controller 410b that is not stopped, in response to a command from the first controller 410a.

[0063] Fig. 6 is a diagram for explaining IO control before queue switching. In Fig. 6, NportID refers to the above-mentioned port D_ID.

[0064] Qset11 and Qset22 are created in the first memory 412a of the first controller 410a. Qset11 and Qset22 are assigned to the first CPU 411a. Qset11 is associated with the first protocol chip 421a, and Qset22 is associated with the second protocol chip 421b.

[0065] Qset21 and Qset12 are created in the second memory 412b of the second controller 410b. Qset21 and Qset12 are assigned to the second CPU 411b. Qset21 is associated with the second protocol chip 421b, and Qset12 is associated with the first protocol chip 421a.

[0066] Qset11 includes CQ1, RQ1, and WQ1. Qset11 is referred to as the first hot cue set, and the queues included in Qset11 are referred to as the first hot cues. Qset12 includes CQ2, RQ2, and WQ2. Qset12 is referred to as the first standby queue set, and the queues included in Qset12 are referred to as the first standby queues. The first hot cue set is used to process IO commands received by the first protocol chip 421a through IO control with the first CPU 411a when the first CPU 411a is not stopped. The first standby queue set is used to process IO commands received by the first protocol chip 421a through IO control between the first protocol chip 421a and the second CPU 411b when the first CPU 411a is stopped.

[0067] Qset21 includes CQ1, RQ1, and WQ1. Qset21 is referred to as the second hot cue set, and the queues included in Qset21 are referred to as the second standby queues. Qset22 includes CQ2, RQ2, and WQ2. Qset22 is referred to as the second standby queue set, and the queues included in Qset22 are referred to as the second standby queues.

[0068] The second hot queue set is used to process IO commands received by the second protocol chip 421b through IO control between the second protocol chip 421b and the second CPU 411b when the second CPU 411b is not stopped. The second standby queue set is used to process IO commands received by the second protocol chip 421b through IO control between the second protocol chip 421b and the first CPU 411a when the second CPU 411b is stopped.

[0069] The first hot cue set and the second hot cue set may be referred to as "hot cue sets" when there is no need to distinguish between them. The first hot cue and the second hot cue may be referred to as "hot cues" when there is no need to distinguish between them. The first standby cue set and the second standby cue set may be referred to as "standby cue sets" when there is no need to distinguish between them. The first standby cue and the second standby cue may be referred to as "standby cues" when there is no need to distinguish between them.

[0070] Before the first protocol chip 421a switches Qset11, which processes the received IO commands, to Qset12, the first protocol chip 421a monitors RQ1 of Qset11, and when there is free space in RQ1, it loads the IO commands accumulated in the receive queue buffer into RQ1. The first CPU 411a monitors RQ1 and initiates an IO transfer request by reaping and processing the IO commands queued (held) in RQ1.

[0071] The first CPU 411a monitors WQ1 of Qset11, and when there is free space in WQ1, it loads the initiated IO transfer request into WQ1. The first protocol chip 421a monitors WQ1 of Qset11, and receives IO transfer requests by reaping and processing IO transfer requests queued (held) in WQ1. When the first protocol chip 421a receives an IO transfer request, it transfers data.

[0072] The first protocol chip 421a monitors CQ1 of Qset11, and when the data transfer is complete, it loads a notification of IO transfer completion into CQ1. The first CPU 411a monitors CQ1 of Qset11 and receives the notification of IO transfer completion, thereby completing one IO control.

[0073] The second protocol chip 421b monitors RQ1 of Qset21, and when there is free space in RQ1, it loads the IO commands accumulated in the receive queue buffer into RQ1. The second CPU 411b monitors RQ1 of Qset21, and initiates an IO transfer request by reaping and processing the IO commands queued (held) in RQ1.

[0074] The second CPU 411b monitors WQ1 of Qset21, and when there is free space in WQ1, it loads the initiated IO transfer request into WQ1. The second protocol chip 421b monitors WQ1 of Qset21, and receives IO transfer requests by reaping and processing IO transfer requests queued (held) in WQ1. When the second protocol chip 421b receives an IO transfer request, it transfers data.

[0075] The second protocol chip 421b monitors CQ1, and when the data transfer is complete, it places a notification of IO transfer completion into the CQ. The second CPU 411b monitors CQ1 in Qset21 and receives the notification of IO transfer completion, thereby completing one IO control.

[0076] 7 is a diagram for explaining control when issuing a queue switching instruction. The second CPU 411b issues a stop start instruction to the first CPU 411a. When the first CPU 411a receives the stop start instruction, the first CPU 411a sends a Qset switching instruction to the first protocol chip 421a. The first protocol chip 421a updates the queue combination table 5000 so that the command transfer flag 5004 corresponding to the first CPU 411a in the queue combination table 5000 is changed from enabled to disabled, and the command transfer flag 5004 corresponding to the second CPU 411b is changed from disabled to enabled. At this time, the second protocol chip 421b processes the IO command it received using Qset21, as described above (the same applies to the following FIGS. 8 to 12).

[0077] FIG. 8 is a diagram for explaining control after issuing a queue switching instruction. When the first protocol chip 421a updates the queue combination table 5000, the destination of the IO command switches from Qset11 to Qset12 (i.e., the destination switches from the first CPU 411a to the second CPU 411b), and the IO command received by the first protocol chip 421a is processed by Qset12. Specifically, the first protocol chip 421a monitors RQ2 of Qset12, and when there is free space in RQ2, it loads the IO command accumulated in the receive queue buffer into RQ2. The second CPU 411b monitors RQ2, and initiates an IO transfer request by reaping and processing the IO command queued (held) in RQ2 of Qset12. The second CPU 411b monitors WQ2 of Qset12, and when there is free space in WQ2, it loads the initiated IO transfer request into WQ2.

[0078] The first protocol chip 421a receives IO transfer requests by monitoring WQ2 of Qset12 and reaping and processing IO transfer requests queued (held) by WQ2. When the first protocol chip 421a receives an IO transfer request, it performs data transfer.

[0079] The first protocol chip 421a monitors CQ2 of Qset12, and when the data transfer is completed, it stores a notification of IO transfer completion in CQ2. The second CPU 411b monitors CQ2 of Qset12 and receives the notification of IO transfer completion by acquiring the notification. This completes the control of one IO.

[0080] Before Qset11 stops, it is necessary to complete the unprocessed IO control (in-progress IOs (remaining IOs)) in Qset11. Therefore, it is necessary to process the queue elements (queue information) loaded in Qset11 before Qset11 stops. Therefore, the first protocol chip 421a receives IO transfer requests by monitoring WQ1 of Qset11 and reaping and processing the IO transfer requests queued (held) by WQ1. When the first protocol chip 421a receives an IO transfer request, it performs data transfer.

[0081] 9 is a diagram for explaining control after issuing a queue switching instruction. The first CPU 411a copies the data of RQ1 to DMY-RQ2 in the second memory 412b of the second controller 410b.

[0082] The second CPU 411b monitors DMY-RQ2 and RQ2 of Qset12, and initiates an IO transfer request by reaping and processing the IO commands queued (held) by DMY-RQ2 and RQ2. At this time, the second CPU 411b preferentially retrieves and processes the IO commands queued (held) by DMY-RQ2 over the IO commands queued by RQ2, thereby preferentially processing the IO commands of the remaining pending IOs.

[0083] 10 is a diagram for explaining the control after the queue switching instruction is issued. The first protocol chip 421a checks the status of the in-progress IO and stops Qset11.

[0084] FIG. 11 is a diagram for explaining control after a queue switching instruction is issued. The first protocol chip 421a notifies the first CPU 411a of queue switching completion (Swap complete). Upon receiving the queue switching completion notification, the first CPU 411a creates remaining IO information. Depending on the IO status (external factors), the IO transfer completion notification may not be returned from the first protocol chip 421a or may be delayed by 10 seconds or more. Simply waiting for the time would prevent the OS update from starting during that time, resulting in an increase in update time. Therefore, for any remaining IO that could not be processed at the time of receiving the switching completion notification, the IO is suspended, and the remaining IO information regarding the suspended remaining IO is sent to the second controller 410b as suspension target information. This prevents the update time from increasing.

[0085] FIG. 12 is a diagram for explaining control after the completion of queue switching. The first CPU 411a transfers the remaining IO information to the interruption target information in the second memory 412b of the second controller 410b. Then, the second CPU 411b issues an interrupt transfer request instruction to the first protocol chip 421a via Qset12. The first protocol chip 421a references the interruption target information and clears the internal resources corresponding to the remaining IO. Note that the internal resources refer to the IO control information stored inside the protocol chip 421. For each IO, one internal resource for IO control is generated and used to perform the IO transfer. The protocol chip 421 secures and executes this IO resource when executing the IO transfer, and releases the IO resource after the IO transfer is complete. The number of these resources is limited by the internal memory capacity of the protocol chip 421. If this resource remains in the protocol chip 421 while the IO transfer is in progress, and if the resource continues to be consumed, new resources cannot be secured, resulting in the IO operation stalling. Therefore, it is necessary for the CPU 411 to issue an interruption process to the protocol chip 421 to release the IO resources in the protocol chip 421 when the IO resource is interrupted.

[0086] <Specific operation> 13 is a flowchart showing the process flow of queue creation processing executed by the CPU 411. The CPU 411 executes this process flow at the timing of initial setup and initial startup to create queues (RQ, CQ, WQ) in the DIMM 412. The CPU 411 starts processing from step 1300 in FIG. 13, and after executing the processes of steps 1300 to 1320 described below, proceeds to step 1395 and temporarily ends this process flow.

[0087] Step 1305: The CPU 411 creates a hot cue (hot cue set).

[0088] Step 1310: The CPU 411 creates a standby queue (standby queue set).

[0089] Step 1315: The CPU 411 creates the queue combination table 5000 and sets (stores) it in the internal memory of the protocol chip 421.

[0090] Step 1320: The CPU 411 completes the creation of the queue.

[0091] In the case of the conventional technology, when switching the queue set that transmits the IO command received by the first protocol chip 421a from the queue set assigned to the first CPU 411a to the queue set assigned to the second CPU 411b, it is necessary to recreate the queues and change the queue addresses every time the switching occurs. In contrast, in this embodiment, since the queue set can be switched by updating the queue combination table, only one setting process (the process in FIG. 13) is required, and it is not necessary to recreate the queues and change the queue addresses every time the switching occurs.

[0092] 14 is a flowchart showing the processing flow of the queue combination table 5000 update processing executed by the first protocol chip 421a using FW (Firmware) included in the first protocol chip 421a. When the first protocol chip 421a receives an instruction to switch Qset from the CPU 411, it starts processing from step 1400 in Fig. 14 and proceeds to step 1405, where it updates the queue combination table 5000 to execute new connection route setting processing for the IO command. Specifically, when it receives an instruction to switch Qset from the first CPU 411a, the first protocol chip 421a changes the command transfer flag 5004 corresponding to the first CPU 411a from disabled to enabled, and changes the command transfer flag 5004 corresponding to the second CPU 411b from enabled to disabled.

[0093] 15 is a flowchart showing the processing flow of the RQ queuing process executed by the first protocol chip 421a using FW. The first protocol chip 421a starts processing from step 1500 in FIG. 15, proceeds to step 1505 to start queuing the RQ, and proceeds to step 1510.

[0094] When the first protocol chip 421a proceeds to step 1510, it determines whether or not the command transfer flag 5004 corresponding to the first CPU 411a in the queue combination table 5000 is invalid.

[0095] If the command transfer flag 5004 corresponding to the first CPU 411a is not invalid (i.e., valid), the first protocol chip 421a determines "NO" in step 1510 and proceeds to step 1515, where it loads the IO command held in the receive queue buffer into RQ1 according to the availability of RQ1 in Qset11. After that, the first protocol chip 421a proceeds to step 1595 and temporarily ends this processing flow.

[0096] If the command transfer flag 5004 corresponding to the first CPU 411a is disabled, the first protocol chip 421a judges "YES" in step 1510 and proceeds to step 1520, where it determines whether the RQ status 5005 (i.e., the operating status of RQ2) corresponding to Qset12 in the queue combination table 5000 is in operation.

[0097] If the RQ state 5005 corresponding to Qset12 in the queue combination table 5000 is not in operation, the first protocol chip 421a determines "NO" in step 1520, proceeds to step 1595, and temporarily ends this processing flow.

[0098] If the RQ state 5005 corresponding to Qset12 in the queue combination table 5000 is in operation, the first protocol chip 421a judges "YES" in step 1520 and proceeds to step 1525, where it places the IO command held in the receive queue buffer into RQ2 depending on the availability of RQ2 in Qset12.

[0099] The second protocol chip 421b also executes the same processing flow as in Fig. 15. The processing flow executed in this case is the same as that in Fig. 15 except that the first CPU 411a is replaced with the second CPU 411b, Qset11 is replaced with Qset21, and Qset12 is replaced with Qset22.

[0100] 16 is a flowchart showing the processing flow of WQ queuing executed by the first protocol chip 421a using FW. The first protocol chip 421a starts processing from step 1600 in FIG. 16, proceeds to step 1605 to start WQ queuing processing, and proceeds to step 1610.

[0101] In step 1610, the first protocol chip 421a determines whether the command transfer flag 5004 corresponding to the first CPU 411a in the queue combination table 5000 is invalid.

[0102] If the command transfer flag 5004 corresponding to the first CPU 411a is not invalid (i.e., valid), the first protocol chip 421a determines "NO" in step 1610 and proceeds to step 1615, where it removes the IO transfer requests queued (held) by WQ1 from WQ1 of Qset11. Thereafter, the first protocol chip 421a proceeds to step 1695, where it temporarily ends this processing flow.

[0103] If the command transfer flag 5004 corresponding to the first CPU 411a is enabled, the first protocol chip 421a judges "YES" in step 1610 and proceeds to step 1620 to determine whether the WQ status 5006 (i.e., the operating status of WQ1) corresponding to Qset11 in the queue combination table 5000 is in operation.

[0104] If the WQ state 5006 corresponding to Qset11 in the queue combination table 5000 is not in operation, the first protocol chip 421a determines "NO" in step 1620 and proceeds to step 1625, where it harvests the IO transfer request from WQ2 of Qset12. After that, the first protocol chip 421a proceeds to step 1695, where it temporarily ends this processing flow.

[0105] If the WQ status 5006 corresponding to Qset11 in the queue combination table 5000 is in operation, the first protocol chip 421a determines "YES" in step 1620 and proceeds to step 1630, where it prunes IO transfer requests from WQ1 of Qset11 and WQ2 of Qset12. As a result, after the start of the queue switch process, IO transfer requests remaining in WQ1 of Qset11 and IO transfer requests for WQ2 of Qset12 due to IO commands sent to Qset12 after the start of the queue switch are pruned. Thereafter, the first protocol chip 421a proceeds to step 1695 and temporarily ends this processing flow.

[0106] The second protocol chip 421b also executes the same processing flow as in Fig. 16. The processing flow executed in this case is the same as that in Fig. 16 except that the first CPU 411a is replaced with the second CPU 411b, Qset11 is replaced with Qset21, and Qset12 is replaced with Qset22.

[0107] 17 is a flowchart showing the processing flow of the CQ queue processing executed by the first protocol chip 421a using the FW. The first protocol chip 421a needs to load the IO transfer completion into the same Qset as the Qset from which the IO transfer request was harvested. If the IO transfer completion is loaded into the CQ of a different Qset, an error occurs. By executing the processing flow shown in FIG. 17, the first protocol chip 421a loads the IO transfer completion into the same Qset as the Qset from which the IO transfer request was harvested.

[0108] The first protocol chip 421a starts processing from step 1700 in FIG. 17, proceeds to step 1705, starts queue processing of the CQ, and proceeds to step 1710.

[0109] When the first protocol chip 421a proceeds to step 1710, it determines whether or not the command transfer flag 5004 corresponding to the first CPU 411a in the queue combination table 5000 is invalid.

[0110] If the command transfer flag 5004 corresponding to the first CPU 411a is not disabled, the first protocol chip 421a determines "NO" in step 1710 and proceeds to step 1715 to determine whether the completed IO transfer is an execution in response to a request from Qset11.

[0111] If the completed IO transfer is execution in response to a request from Qset11, the first protocol chip 421a determines "YES" in step 1715 and proceeds to step 1720, where it loads a notification of the IO transfer completion into CQ1 of Qset11. After that, the first protocol chip 421a proceeds to step 1795 and temporarily ends this processing flow.

[0112] If the completed IO transfer is not an execution of a request from Qset11, the first protocol chip 421a determines "NO" in step 1715 and proceeds to step 1725, where it loads a notification of the IO transfer completion into CQ2 of Qset12. After that, the first protocol chip 421a proceeds to step 1795 and temporarily ends this processing flow.

[0113] If the command transfer flag 5004 corresponding to the first CPU 411a is invalid in step 1710, the first protocol chip 421a judges "YES" in step 1710 and proceeds to step 1730, where it determines whether the CQ1 state (CQ state 5007 corresponding to Qset11) in the queue combination table 5000 is in operation.

[0114] If the CQ1 state of the queue combination table 5000 (CQ state 5007 corresponding to Qset11) is in operation, the first protocol chip 421a judges "YES" in step 1730 and proceeds to step 1735 to determine whether the completed IO transfer is an execution in response to a request from Qset11.

[0115] If the completed IO transfer is execution in response to a request from Qset11, the first protocol chip 421a determines "YES" in step 1735 and proceeds to step 1740, where it loads a notification of the IO transfer completion into CQ1 of Qset11. After that, the first protocol chip 421a proceeds to step 1795, where it ends this processing flow.

[0116] If the completed IO transfer is not an execution of a request from Qset11, the first protocol chip 421a determines "NO" in step 1735 and proceeds to step 1745, where it sends a notification of the completion of the IO transfer to CQ2 of Qset12.

[0117] If the CQ1 state of the queue combination table 5000 (CQ state 5007 corresponding to Qset11) is not in operation in step 1730, the first protocol chip 421a determines "NO" in step 1730 and proceeds to step 1750 to determine whether the completed IO transfer is an execution in response to a request from Qset11.

[0118] If the completed IO transfer is execution in response to a request from Qset11, the first protocol chip 421a determines "YES" in step 1750 and proceeds to step 1755, where the first protocol chip 421a discards the notification of IO transfer completion because it cannot load the IO transfer completion into CQ1, where it needs to be loaded. After that, the first protocol chip 421a proceeds to step 1795 and temporarily ends this processing flow.

[0119] If the completed IO transfer is not execution in response to a request from Qset11, the first protocol chip 421a determines "NO" in step 1750 and proceeds to step 1760, where it sends a notification of the completion of the IO transfer to CQ2 of Qset12. After that, the first protocol chip 421a proceeds to step 1795 and temporarily ends this processing flow.

[0120] The second protocol chip 421b also executes the same processing flow as in Fig. 17. The processing flow executed in this case is the same as that in Fig. 16 except that the first CPU 411a is replaced with the second CPU 411b, Qset11 is replaced with Qset21, and Qset12 is replaced with Qset22.

[0121] 18 is a flowchart showing the processing flow of the queue switching process executed by the first protocol chip 421a using FW. The first protocol chip 421a starts processing from step 1800 in Fig. 18, and after sequentially executing the processing of steps 1805 to 1815 described below, proceeds to step 1820.

[0122] Step 1805: The first protocol chip 421a creates an OXID table 3000 for the remaining IOs on the active side (the hot cue set to be switched). As mentioned above, the OXID table 3000 contains information indicating the status of the IOs (remaining IOs) in progress on the first CPU 411a side (the hot cue set to be switched).

[0123] Step 1810: The first protocol chip 421a sets a TOV (Time Out Value) value to be used in the switching process. The TOV value is a threshold value for the timer. The timer starts counting time from the start of the queue switching process. If the timer exceeds the TOV value, the IOs in the middle of IO processing (uncompleted IOs) are interrupted and the switching process is terminated. Note that there are cases where processing of all remaining IOs is finished (completed) before the timer exceeds the TOV value.

[0124] Step 1815: The first protocol chip 421a switches the command transfer flag 5004 in the queue combination table 5000 from RQ1 to RQ2. That is, the first protocol chip 421a changes the command transfer flag 5004 corresponding to Qset11 including RQ1 in the queue combination table 5000 from enabled to disabled, and changes the command transfer flag 5004 corresponding to Qset12 including RQ2 from disabled to enabled.

[0125] In step 1820, the first protocol chip 421a determines whether or not there are any unsent IO commands remaining to be sent to RQ1 of Qset11.

[0126] If there are any unsent IO commands remaining before being sent to RQ1 of Qset11, the first protocol chip 421a judges "YES" in step 1820, sends the remaining IO commands to RQ2 of Qset12, returns to step 1820, and executes the processing of step 1820 again.

[0127] If there are no unsent IO commands remaining to be sent to RQ1 of Qset11, the first protocol chip 421a judges "NO" in step 1820 and proceeds to step 1825, where it stops RQ1 of Qset11 and proceeds to step 1835.

[0128] When the first protocol chip 421a proceeds to step 1835, it determines whether or not there are any unprocessed IO transfer requests remaining in WQ1 of Qset11. If there are any unprocessed IO transfer requests remaining in WQ1 of Qset11, the first protocol chip 421a determines "YES" in step 1835 and proceeds to step 1840, where it prunes and executes the unprocessed IO transfer requests. Thereafter, the first protocol chip 421a returns to step 1835 and executes the processing of step 1835 again.

[0129] If there are no unprocessed IO transfer requests remaining in WQ1 of Qset11, the first protocol chip 421a determines "NO" in step 1835 and proceeds to step 1845, where it stops WQ1 of Qset11 and proceeds to step 1855.

[0130] When the first protocol chip 421a proceeds to step 1855, it refers to the OXID table 3000 to determine whether or not there are any remaining IOs (uncompleted IOs (ie, IOs left behind in CQ1 of Qset11)).

[0131] If there are remaining IOs, the first protocol chip 421a determines "YES" in step 1855 and proceeds to step 1860 to determine whether the remaining IOs have been completed.

[0132] If the remaining IOs are completed, the first protocol chip 421a judges "YES" in step 1860 and proceeds to step 1865, where it puts a completion notification of the completed remaining IOs into CQ1 and deletes the information (record) corresponding to the corresponding remaining IOs from the OXID table 3000. After that, the first protocol chip 421a returns to step 1855 and executes the processing of step 1855 described above.

[0133] If the remaining IOs have not been completed, the first protocol chip 421a determines "NO" in step 1860 and proceeds to step 1870 to determine whether the timer has exceeded the TOV.

[0134] If the timer has not exceeded the TOV, the first protocol chip 421a determines "NO" in step 1870, returns to step 1855, and executes the processing of step 1855 already described.

[0135] If the timer has exceeded the TOV, the first protocol chip 421a determines "YES" in step 1870 and proceeds to step 1875, where it notifies the first CPU 411a of the OXID table 3000 of the remaining IOs, and then returns to step 1855 and executes the processing of step 1855. In this case, the remaining IOs become IOs to be suspended, and when it proceeds to step 1855, it is determined that there are no remaining IOs.

[0136] If there are no remaining IOs in step 1855, the first protocol chip 421a judges "NO" in step 1855, executes the processes of steps 1880 and 1885 described below in order, and then proceeds to step 1895 to temporarily terminate this processing flow (switching processing).

[0137] Step 1880: The first protocol chip 421a stops CQ1. At this point, all of RQ1, WQ1, and CQ1 in Qset11 have been stopped.

[0138] Step 1885: The first protocol chip 421a notifies the first CPU 411a of the completion of the queue switching.

[0139] The second protocol chip 421b also executes the same processing flow as in Fig. 18. The processing flow executed in this case is the same as that in Fig. 18 except that the first CPU 411a is replaced with the second CPU 411b, the second CPU 411b is replaced with the first CPU 411a, Qset11 is replaced with Qset21, and Qset12 is replaced with Qset22.

[0140] 19A and 19B are flowcharts showing the process flow of queue switching processing executed by the first CPU 411a according to a program. By executing this process flow, the first CPU 411a processes RQ1, WQ1, and CQ1 of Qset11 not only on the first protocol chip 421a side but also on the first controller 410a side after the queue switching completion notification (after all RQ1, WQ1, and CQ1 of Qset11 have stopped).

[0141] The first CPU 411a starts the switching process from step 1900 in FIG. 19A, and after sequentially executing the processes of steps 1905 to 1915 described below, proceeds to step 1920.

[0142] Step 1905: The first CPU 411a obtains the remaining number of IO transfer requests for WQ1 waiting to be executed by counting the pointer of WQ1 in Qset11. The first CPU 411a stops loading new IO transfer requests into WQ1 in Qset11.

[0143] Step 1910: The first CPU 411a sends a queue switching instruction to the first protocol chip 421a.

[0144] Step 1915: The first CPU 411a receives a queue switching completion notification from the first protocol chip 421a, and receives the OXID table 3000 indicating the remaining IOs from the first protocol chip 421a.

[0145] When the first CPU 411a proceeds to step 1920, it determines whether or not there is a queue switching completion notification. If there is no queue switching completion notification, the first CPU 411a determines "NO" in step 1920 and executes the processing of step 1920 again.

[0146] If there is a queue switching completion notification, the first CPU 411a determines "YES" in step 1920 and proceeds to step 1925, where the first CPU 411a determines whether or not there are any IO commands remaining in RQ1 of Qset11.

[0147] If there is an IO command remaining in RQ1 of Qset11, the first CPU 411a judges "YES" in step 1925 and proceeds to step 1930, copies the IO command to DMY-RQ2 of Qset12, returns to step 1925, and executes the processing of step 1925 described above.

[0148] If there are no IO commands remaining in RQ1 of Qset11, the first CPU 411a determines "NO" in step 1925 and proceeds to step 1935 to determine whether there are any IO transfer requests remaining in WQ1 of Qset11.

[0149] If there is an IO transfer request remaining in WQ1 of Qset11, the first CPU 411a determines "YES" in step 1935, proceeds to step 1940, copies the IO transfer request to WQ2 of Qset12, and returns to step 1935.

[0150] If there are no remaining IO transfer requests in WQ1 of Qset11, the first CPU 411a judges "NO" in step 1935 and proceeds to step 1945 to determine whether there are any remaining IOs (IO transfer completion notifications for remaining IOs) remaining in CQ1 of Qset11.

[0151] If there are remaining IOs (IO transfer completion notifications for remaining IOs) in CQ1 of Qset11, the first CPU 411a judges "YES" in step 1945 and proceeds to step 1950, where it copies the IO transfer completion notification from CQ1 of Qset11 to CQ2 of Qset12, then returns to step 1945 and executes the processing of step 1945 described above.

[0152] When there is no remaining I / O (notification of completion of I / O transfer for remaining I / O) in CQ1 of Qset11, the first CPU 411a determines "NO" in step 1945 and proceeds to step 1955, where it creates an interrupt table 2000 from the OXID table 3000 of the remaining I / O. The first CPU 411a notifies the second CPU 411b of the interrupt table 2000 and sends a notification of completion of stop preparation to the second CPU 411b.

[0153] Note that the second CPU 411b also executes the same processing flow as shown in FIGS. 19A and 19B. The processing flow executed in this case is the same as that in FIGS. 19A and 19B, except that the first CPU 411a is replaced by the second CPU 411b, the second CPU 411b is replaced by the first CPU 411a, Qset11 is replaced by Qset21, and Qset12 is replaced by Qset22.

[0154] <OS update> FIGS. 20A and 20B are sequence diagrams showing the operations when updating the SMP-OS operating on the first CPU 411a.

[0155] In the storage system 200, the operations of steps 2100 to 2131 described below are executed. Note that the first CPU 411a executes the operations described below by the control program PG1, the second CPU 411b executes the operations described below by the control program PG2, and the first protocol chip 421a executes the operations described below by the switching program PG3.

[0156] Step 2100: The terminal t1 instructs the second CPU 411b to start OS update.

[0157] Step 2101: The second CPU 411b starts the stop process of the first controller 410a and sends a stop instruction to the first CPU 411a.

[0158] Step 2102: When the first CPU 411a receives a stop instruction from the second CPU 411b, it sends a queue switching process instruction (queue swap instruction) to the first protocol chip 421a.

[0159] Step 2103: The first protocol chip 421a sets a new connection route (updates the queue combination table 5000).

[0160] Step 2104: The first protocol chip 421a executes the queue switching process (the process flow shown in the flowchart of FIG. 18).

[0161] Step 2105: The first protocol chip 421a sends a queue switching completion notification to the first CPU 411a.

[0162] Step 2106: The first CPU 411a sends the remaining IO information to the second CPU 411b.

[0163] Step 2107: When the first CPU 411a completes the preparation for stopping, it transmits a completion notice to the second CPU 411b.

[0164] Step 2108: The second CPU 411b sends a reboot instruction to the first CPU 411a.

[0165] Step 2109: The first CPU 411a starts the OS update and reboot.

[0166] Step 2110: The first CPU 411a sends an update start notification to the second CPU 411b.

[0167] Step 2111: The second CPU 411b transmits an update start notification to the terminal t1.

[0168] Step 2112: The second CPU 411b sends a remaining IO transfer instruction (transfer execution / interruption instruction) to the first protocol chip 421a.

[0169] Step 2113: The first protocol chip 421a executes the remaining IO processing.

[0170] Step 2114: The first protocol chip 421a transfers the queue element to the second controller 410b, and notifies the second CPU 411b of the completion of the interruption.

[0171] Step 2115: The first CPU 411a executes the OS update process and reboots.

[0172] Step 2116: The first CPU 411a transmits an OS update completion notification to the second CPU 411b.

[0173] Step 2117: The second CPU 411b transmits an OS update completion notification to the terminal t1.

[0174] Step 2118: The terminal t1 transmits a state restoration instruction to the second CPU 411b.

[0175] Step 2119: The second CPU 411b issues a start-up instruction to the first CPU 411a to start the controller startup.

[0176] Step 2120: The first CPU 411a sends a queue switching processing instruction (queue swap instruction) to the first protocol chip 421a.

[0177] Step 2121: The first protocol chip 421a sets a new connection route (updates the queue combination table 5000).

[0178] Step 2122: The first protocol chip 421a executes queue switching processing (Qset12 → Qset11) in which the switching of Qset is reversed with respect to the processing flow shown in the flowchart of FIG. 18. The processing flow executed in this case is the same as the processing flow of FIG. 18 except that the first CPU 411a and the second CPU 411b are swapped with each other, and Qset11 and the queues contained therein and Qset12 and the queues contained therein are swapped with each other.

[0179] Step 2123: The first protocol chip 421a sends a queue switching completion notification to the first controller 410a.

[0180] Step 2124: The first CPU 411a completes preparation for return and transmits a return preparation completion notification to the second CPU 411b.

[0181] Step 2125: The second CPU 411b receives the controller startup completion notification.

[0182] Step 2126: The second CPU 411b notifies the terminal t1 of the completion of the update.

[0183] Step 2127: The terminal t1 completes the OS update.

[0184] Step 2128: The second CPU 411b sends the remaining IO information to the first CPU 411a.

[0185] Step 2129: The first CPU 411a sends a remaining IO transfer instruction (transfer execution / interruption instruction) to the first protocol chip 421a.

[0186] Step 2130: The first protocol chip 421a executes the remaining IO processing.

[0187] Step 2131: The first protocol chip 421a transfers the queue element to the first controller 410a and notifies the first CPU 411a of the completion of the interruption.

[0188] <Effects> As described above, the storage system 200 according to an embodiment of the present invention can continue IO processing by switching the queue used for IO control according to an instruction from the controller 410 when the CPU 411 is stopped. When rebooting the CPU 411 of the controller 410, the storage system 200 according to the embodiment can reduce the possibility that a command received by the controller 410 will be lost. When changing queue mapping, the storage system 200 according to the embodiment does not need to change the settings of the protocol chip 421 (reset the protocol chip 421), and therefore can reduce the possibility of link disconnection and IO loss due to a reset.

[0189] Furthermore, the storage system 200 according to an embodiment of the present invention processes not only new IOs but also remaining IOs after queue switching processing, thereby reducing the possibility of IO control being incomplete and reducing the possibility of IO loss.

[0190] Furthermore, the storage system 200 according to the embodiment of the present invention prevents an increase in the OS update time by suspending the remaining IOs if a predetermined time has passed without processing the remaining IOs after the queue switching process.

[0191] Furthermore, the storage system 200 according to the embodiment of the present invention can solve the problems of the prior art described below.

[0192] With conventional technology, when the multi-queue function is used, it is possible to prepare two or more queues in advance and assign a separate CPU to each. However, in order to distribute commands to these queues, it is necessary to distribute commands received from the host server to which of the multiple queues they should be delivered using the Fibre Channel port ID, so a separate port ID is required for distribution. When separate port IDs are used, the host server needs to understand the differences between each port ID and distribute IO control, which poses the issue that this is not suitable for systems with general FC.

[0193] In contrast to this, the storage system 200 according to the embodiment of the present invention can use the queue combination table 5000 to allocate queues to which IO commands are to be sent, thereby solving the above problem.

[0194] <<Modifications>> The present invention is not limited to the above-described embodiment, and various modifications can be adopted within the scope of the present invention. The above-described embodiment may be applied to a case where the CPU 411 of the controller 410 stops due to a failure. For example, when the first CPU 411a of the first controller stops due to a failure, the queue combination table 5000 may be updated so that the queue to which the IO command of the first protocol chip 421a corresponding to the first controller 410a is sent becomes a queue assigned to the second CPU 411b other than the first CPU 411a that stopped due to the failure, thereby switching the communication path of the IO command.

[0195] In the above embodiment, the second CPU 411b may be stopped in response to a command from the second controller 410b, and the Qset to which the second protocol chip 421b sends the received IO command may be switched from Qset21 to Qset22. [Explanation of symbols]

[0196] 100a, 100b... host servers, 200... storage system, 300... fibre channel switch, 400a... first controller unit, 400b... second controller unit, 410a... first controller, 410b... second controller, 411a... first CPU, 411b... second CPU, 421a... first protocol chip, 421b... second protocol chip, 430a... first PCI switch, 430b... second PCI switch, 500... drive box, 420a... first CHB, 420b... second CHB, 412a... first DIMM, 412b... second DIMM, 5000... queue combination table

Claims

1. a first protocol chip and a second protocol chip for receiving IO commands from a host; a first controller having a first CPU to which a queue used for control communication with the first protocol chip and a queue used for control communication with the second protocol chip are assigned; a second controller having a second CPU to which a queue used for control communication with the first protocol chip and a queue used for control communication with the second protocol chip are assigned; a first PCI switch provided between the first protocol chip and the first and second CPUs, the first PCI switch setting a communication path between the first protocol chip and the first CPU and a communication path between the first protocol chip and the second CPU; a second PCI switch provided between the second protocol chip and the first and second CPUs, the second PCI switch setting a communication path between the second protocol chip and the first CPU and a communication path between the second protocol chip and the second CPU; Equipped with Each of the first protocol chip and the second protocol chip comprises: queue control information that defines a queue to which the IO command received from the host is to be sent; setting a communication path through which the I / O command passes to the communication path in accordance with the queue control information by the first PCI switch and the second PCI switch; It was configured as follows: Storage system.

2. 2. The storage system according to claim 1, One of the first controller and the second controller sending a queue switching command to either the first protocol chip or the second protocol chip; It is configured as follows: Either the first protocol chip or the second protocol chip that receives the queue switching command updating the queue control information in response to the queue switching command, thereby switching the communication path through which the I / O command passes to the communication path in accordance with the updated queue control information; It was configured as follows: Storage system.

3. 3. The storage system according to claim 2, a communication path between the first protocol chip and the first CPU is a communication path for normal I / O processing to be used when the first CPU is not stopped, and a communication path between the first protocol chip and the second CPU is a communication path for alternative I / O processing to be used when the first CPU is stopped, The first controller When the first CPU is stopped, the queue switching command is sent to the first protocol chip. It is configured as follows: The first protocol chip includes: in response to the queue switching command, switching the communication path through which the IO command received by the first protocol chip passes from the communication path for normal IO processing to the communication path for alternative IO processing; It is configured as follows: Storage system.

4. 4. The storage system according to claim 3, The communication path between the second protocol chip and the second CPU includes: a communication path for normal I / O processing used when the second CPU is not stopped, The communication path between the second protocol chip and the first CPU includes: an alternative communication path for I / O processing to be used when the second CPU is stopped; The second controller When the second CPU is stopped, the queue switching command is sent to the second protocol chip. It is configured as follows: The second protocol chip is In response to the queue switching command, the communication path through which the IO command received by the second protocol chip passes is switched from the communication path for normal IO processing to the communication path for alternative IO processing. It was configured as follows: Storage system.

5. 3. The storage system according to claim 2, each of the first CPU and the second CPU is a multi-core CPU of an SMP-OS; The first protocol chip includes: When updating the SMP-OS running on the first CPU, the queue control information is updated so that a queue to which the I / O command received by the first protocol chip is to be sent is switched from a queue assigned to the first CPU to a queue assigned to the second CPU. It was configured as follows: Storage system.

6. 6. The storage system according to claim 5, The second protocol chip is When updating the SMP-OS running on the second CPU, the queue control information is updated so that a queue to which the I / O command received by the second protocol chip is to be sent is switched from a queue assigned to the second CPU to a queue assigned to the first CPU. It was configured as follows: Storage system.

7. 3. The storage system according to claim 2, A queue set including an RQ for receiving the IO command, a WQ which is a message transmission queue for requesting IO execution, and a CQ which is a message reception queue for receiving completion of IO data transfer started by the IO execution request is assigned to each of the first CPU and the second CPU, Either the first protocol chip or the second protocol chip that receives the queue switching command The remaining status of unprocessed queue information in the queue set from which the switch is made is checked, and processing is performed according to the remaining status. It was configured as follows: Storage system.

8. 8. The storage system according to claim 7, Either the first protocol chip or the second protocol chip that receives the queue switching command Check the remaining status of the I / O commands, which are queue information of the RQ of the switching source, copy and load the I / O commands remaining in the RQ into the queue of the switching destination, and process the unprocessed queue information. It was configured as follows: Storage system.

9. 8. The storage system according to claim 7, Either the first protocol chip or the second protocol chip that receives the queue switching command Checking the remaining status of I / O transfer requests, which are the queue information of the WQ from which the switch is made, and processing the I / O transfer requests remaining in the WQ. It was configured as follows: Storage system.

10. 8. The storage system according to claim 7, Either the first protocol chip or the second protocol chip that receives the queue switching command Check the remaining IOs for which IO completion notifications have not yet been sent in the CQ from which the switch is made, and if a predetermined condition is met, notify either the first controller or the second controller that sent the queue switch command of information about the remaining IOs, and suspend processing of the remaining IOs. It was configured as follows: Storage system.

11. 8. The storage system according to claim 7, the first controller comprises a first memory; the second controller comprises a second memory; a first hot queue set is created in the first memory of the first controller as the queue set, the first hot queue set being used to process the IO command received by the first protocol chip when the first CPU is not stopped; a first standby queue set is created in the second memory of the second controller as the queue set, the first standby queue set being used to process the IO commands received by the first protocol chip when the first CPU is stopped; a second hot queue set is created in the second memory of the second controller as the queue set, the second hot queue set being used to process the IO command received by the second protocol chip when the second CPU is not stopped; In the first memory of the first controller, a second standby queue set is created as the queue set, the second standby queue set being used to process the I / O commands received by the second protocol chip when the second CPU is stopped. Storage system.

12. 12. The storage system according to claim 11, The first protocol chip includes: When the first CPU of the first controller is stopped, a communication path is switched so that the first protocol chip transmits the IO command received from the host to the first standby queue set; The second protocol chip is When the second CPU of the second controller is stopped, a communication path is switched so that the second protocol chip transmits the I / O command received from the host to the second standby queue set. It was configured as follows: Storage system.

13. 3. The storage system according to claim 2, Either the first protocol chip or the second protocol chip When either the first CPU or the second CPU stops due to a failure, the queue control information is updated so that a queue to which the received I / O command is to be sent becomes a queue assigned to either the first CPU or the second CPU that is not stopped due to a failure. It was configured as follows: Storage system.

14. a first protocol chip and a second protocol chip for receiving IO commands from a host; a first controller and a second controller each having a CPU that receives the IO commands from the first protocol chip and the second protocol chip; a first communication path between the first protocol chip and the first controller; a second communication path between the second protocol chip and the second controller; a third communication path between the first protocol chip and the second controller; a fourth communication path between the second protocol chip and the first controller; a first PCI switch for switching a communication path through which the IO command received by the first protocol chip passes to either the first communication path or the third communication path in response to a command from a controller side; a second PCI switch for switching the communication path through which the IO command received by the second protocol chip passes to either the second communication path or the fourth communication path in response to an instruction from the controller side.

15. a first protocol chip and a second protocol chip for receiving IO commands from a host; a first controller having a first CPU to which a queue used for control communication with the first protocol chip and a queue used for control communication with the second protocol chip are assigned; a second controller having a second CPU to which a queue used for control communication with the first protocol chip and a queue used for control communication with the second protocol chip are assigned; a first PCI switch provided between the first protocol chip and the first and second CPUs, the first PCI switch setting a communication path between the first protocol chip and the first CPU and a communication path between the first protocol chip and the second CPU; a second PCI switch provided between the second protocol chip and the first and second CPUs, the second PCI switch setting a communication path between the second protocol chip and the first CPU and a communication path between the second protocol chip and the second CPU; A storage system management method applied to a storage system comprising: Each of the first protocol chip and the second protocol chip comprises: queue control information that defines a queue to which the IO command received from the host is to be sent; setting a communication path through which the I / O command passes to the communication path in accordance with the queue control information by the first PCI switch and the second PCI switch; A method for managing a storage system.

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