Glass substrate for semiconductor package

Abstract

To provide a substrate structure that, when laying out various semiconductor chips, electrical components, interposer substrates, etc., on a package substrate, offers a high design margin against overall substrate warpage even when circuit patterns, semiconductors, and electronic components are mounted on only one side, and also provide high overall substrate temperature uniformity and heat dissipation, enabling the mounted substrate to be fixed to a frame, etc., without applying stress to the substrate.SOLUTION: A laminated glass substrate is a laminated structure in which a metal sheet 20, bonded to the glass substrate, is interposed between two glass substrates 1, 4, additionally, as necessary, the diameter of the metal sheet within a through-hole 9 between the top and bottom surfaces of the glass substrate is larger than the diameter of the through-hole in the glass substrate itself, and a metal wire 30 conducts electricity through the through-hole 9 to metal patterns 5 and 8 on the surfaces of the glass substrates 1, 4.SELECTED DRAWING: Figure 16

Description

[Technical Field]

[0001] The present invention relates to a substrate for semiconductor packages, which is a glass substrate for surface mounting semiconductor chips and interposer substrates, and which can significantly reduce warping of the substrate due to temperature changes, has a large margin for wiring pattern design, and has excellent features such as uniform substrate temperature, heat dissipation, and stability of fixation to a frame. [Background technology]

[0002] In recent years, advances in high-speed signal transmission, such as 5G and next-generation 6G communications, as well as CPUs, GPUs, and AI systems, have necessitated configurations with low signal transmission loss. To achieve this, the substrate's dielectric loss, i.e., low relative permittivity Dk and low dielectric dissipation factor Df, is required, and low conductor loss and scattering loss, i.e., the resistance and smoothness of the copper pattern, are also important.

[0003] Additionally, heterogeneous integrated packages have been proposed, in which semiconductor chips with various functions are densely mounted on the same package substrate. The substrate specifications required for high-density mounting include pattern accuracy, a coefficient of linear expansion (CTE) equivalent to that of the semiconductor chip, and heat resistance. Conventionally used substrates include glass cloth epoxy substrates and polyimide film substrates, but their CTE is between 10 and several tens of ppm / K, which is different from the approximately 4 ppm / K of silicon chips. Therefore, care must be taken in terms of the positional accuracy of pattern formation and stress generation during chip mounting.

[0004] For high-density packaging, chip-to-wafer bonding (CoW) and direct wafer-to-wafer bonding (WoW) are being considered, and this is called hybrid bonding, which involves direct bonding of 1 μm-wide Cu to Cu or direct bonding between passivation films. In this case, high dimensional accuracy and flatness are required, and the difference in CTE must also be minimized.

[0005] Attempts are being made to solve these problems by using glass substrates. Alkali-free glass substrate materials are available that have a CTE almost identical to that of silicon wafer materials over a wide temperature range, and they also have extremely high flatness. By increasing the precision of polishing, an optical contact method is also possible, in which glass pieces are joined together at room temperature and atmospheric pressure, as in the production of prisms. A common method that does not require high flatness is to provide bumps on an interposer substrate or a semiconductor chip and bond the bumps to conductive pattern electrodes on a glass substrate.

[0006] The challenge with using glass substrates is that, like conventional glass epoxy substrates, the conductive wiring material is copper (Cu), which has a CTE of approximately 17 ppm / K, which is significantly different from the CTE of glass substrates, which is approximately 4 ppm / K. High-speed transmission requires reducing wiring resistance, and since pattern width is limited by factors such as circuit density, it requires as thick a pattern width as possible. For this reason, copper patterns are often formed on glass substrates using the damascene process to a thickness of, for example, 5 μm or more.

[0007] However, when a Cu pattern is formed on one side of a glass core substrate, warping occurs depending on the difference in CTE as the temperature changes. For example, in the thermal shock test specified in Section 9.2 of JIS C5012-1993 (Condition 1: 175°C and -65°C, Condition 2: 125°C and -65°C), the substrate will warp significantly, which can result in serious problems such as electrical joint destruction due to peeling at the joints.

[0008] Generally, even in the case of core boards made of conventional glass epoxy base material, the layout is designed so that the patterns and component layouts on the top and bottom of the board are symmetrical to cancel out warping, which requires design know-how and advanced simulation technology.

[0009] This issue is no different for glass substrates, and if the CTE of the glass substrate is 3.9 ppm / K, the same as that of the silicon chip, then the copper plating layer has a CTE of 17 ppm / K, resulting in a CTE difference of 13.1 ppm per 1°C temperature change, which means that copper expands and contracts significantly, causing substrate warpage due to temperature changes. To resolve this issue, it is necessary to provide a circuit using a Cu pattern on the opposite side of the glass substrate, but there is a need for a method to expand the design margin for the layout of the Cu pattern, semiconductor chip, interposer, etc. [Prior art documents] [Patent documents]

[0010] [Patent Document 1] Patent Publication No. 2017-216398 (Patent No. 6747063) [Patent Document 2] Patent Publication No. 2022-517062 (Patent No. 7087205) [Patent Document 3] Patent Publication No. 2004-337927 (Patent No. 3848989) Summary of the Invention [Problem to be solved by the invention]

[0011] The present invention provides a glass substrate structure for semiconductor packages that allows for a high design margin for pattern placement and component layout in response to ambient temperature changes, particularly warpage of the glass substrate during thermal shock testing, and ideally allows circuit patterns and component mounting to be placed on one side of the substrate, while at the same time quickly diffusing and uniforming heat generated by the components.

[0012] In conventional glass substrates, the thickness of the glass substrate is increased, for example to 1 mm, to strengthen the glass and reduce the amount of warping due to temperature changes. However, from the perspective of the process of creating through-holes (TGV: Through Glass Via) to ensure electrical continuity between the top and bottom, thinner glass is preferable; these two points are contradictory.

[0013] The conductive patterns on the glass substrate must be arranged equally on the top and bottom so that the amount of warping of the substrate is offset on the top and bottom surfaces, and making the glass substrate thinner also reduces the design margin. Also, the TGV is not only used to set up the BGA (Ball Grid Array) that interfaces the package with the external circuit, but also to configure the circuit on the opposite side to prevent the substrate from warping.

[0014] In heterogeneous integrated packages, where semiconductors with various functions are mounted on the same substrate, the heat generated by each semiconductor chip varies. Normally, heat is dissipated from the top surface of the chip directly into the air or through a heat sink, but no temperature equalization or heat dissipation measures are taken within the package substrate itself.

[0015] Unlike glass epoxy boards, glass boards are easily damaged by stress or impact even when they are only 1 mm thick. Therefore, fixing the glass board itself to a frame or similar is highly risky.

[0016] The present invention has been made in consideration of the various circumstances described above, and provides a glass package substrate that suppresses warping of the substrate due to temperature changes even when components such as RDLs and semiconductor chips are mounted on only one side of the substrate, and further promotes temperature uniformity on the substrate side for heat generated by the chip, leading to a high-speed heat dissipation structure outside the periphery of the substrate. [Means for solving the problem]

[0017] The present invention sandwiches a metal sheet having a larger CTE than the glass substrate between two glass substrates, and forms the glass substrate with a tightly laminated structure using the sheet and the glass substrate. This makes it possible to suppress the amount of warping due to temperature changes even when wiring patterns and component mounting formed on the glass substrate are laid out on one side of the substrate, thereby significantly improving the pattern design margin.

[0018] Therefore, in the present invention, it is possible to provide a package specification in which components such as circuits, semiconductors, and connectors are mounted on only one side of the substrate without providing through holes. Of course, through holes may be provided, or wiring layers and components may be mounted on the opposite side of the substrate without providing through holes.

[0019] Furthermore, as a method for achieving electrical continuity between patterns above and below the substrate, a through hole can be formed in the glass substrate, and the upper and lower patterns can be made conductive by passing a metal wire through the through hole, as shown in the priority patent, without making the inner wall of the through hole conductive by plating or the like.

[0020] The diameter of the through-holes in the laminated metal sheet is made larger than the diameter of the glass substrate. This prevents electrical short-circuiting between the metal wire and the metal sheet. Furthermore, by forming an insulating film around the inner wall of the through-holes in the metal sheet, such as aluminum oxide by anodization after the through-holes are formed, electrical short-circuiting does not occur even if the diameter of the through-holes is the same as the diameter of the glass.

[0021] By bonding the glass and metal sheet in the glass package area and leaving the area outside this area as a non-bonded area, the metal sheet can be made larger than the outer dimensions of the glass substrate, and the protruding metal sheet part can be thermally bonded to an external heat sink to improve heat dissipation performance or used to secure the part to the frame. [Effects of the Invention]

[0022] According to the present invention, which involves inserting and joining a metal sheet having a CTE greater than that of the glass between two glass substrates, even if wiring patterns or components are mounted on one of the glass substrates, warping can be kept close to 0 mm even when subjected to temperature changes in a thermal shock test. Furthermore, thin glass substrates can be used, the process load can be reduced even when processing through holes, and the overall thickness and weight can be made thinner and lighter than that of a 1 mm thick glass substrate.

[0023] Conduction between the top and bottom of the board is achieved using metal wires rather than plating the inner walls of the holes, resulting in stable, low-resistance conductivity. Since the material passes through air, it has a relative permittivity of 1 and a dielectric dissipation factor of 0, resulting in low loss. (Priority claimed: Patent application 2024-041792, filing date: March 17, 2024)

[0024] By utilizing an inserted metal sheet, a glass package substrate is provided which has high temperature uniformity and heat dissipation properties across the entire substrate, and which can be fixed to a frame or the like without applying stress to the mounting substrate. [Brief explanation of the drawings]

[0025] [Figure 1] FIG. 1 is a cross-sectional view of a two-layer structure in which a Cu plating layer is formed on one side of a glass substrate. [Figure 2] FIG. 2 is a graph showing the change in the amount of warpage of the glass substrate depending on the Cu plating thickness in the structure shown in FIG. [Figure 3] FIG. 3 is a cross-sectional view of a laminate in which Cu plating layers are formed on both sides of a glass substrate. [Figure 4] 4 is a cross-sectional view showing an example in which a conventional example is mounted on a general glass package substrate. [Figure 5] FIG. 5 is a cross-sectional view of a four-layer structure with an interposed metal sheet according to the present invention. [Figure 6] FIG. 6 is a graph comparing the amount of warpage between the conventional two-layer structure (FIG. 1) and the four-layer structure of the present invention (FIG. 5). [Figure 7] Figure 7 is a graph showing the change in the amount of warpage caused by the glass substrate thickness and Cu plating thickness when an inserted Cu metal sheet is 1 mm thick. [Figure 8] Figure 8 is a graph showing the change in the amount of warpage caused by the Cu plating thickness when the inserted Al metal sheet is 1 mm thick. [Figure 9] FIG. 9 is a cross-sectional view of a structure in which an intercalating metal sheet and a glass substrate are bonded together with an organic polymer adhesive sheet. [Figure 10] FIG. 10 is a graph showing the amount of warpage when the inserted metal sheet is a 1.0 mm Al sheet and the glass substrate thickness is changed. [Figure 11]FIG. 11 is a graph showing the change in warpage when the Cu alloy-based sheet intercalation is 0.5 / 0.7 mm, the glass substrate thickness is 0.25 mm, and the organic polymer-based adhesive film is 0.1 mm. [Figure 12] FIG. 12 is a plan view and a cross-sectional view showing an example of the layout of package substrates on a large glass substrate (510×515 mm). [Figure 13] FIG. 13 is a cross-sectional view of an example in which wiring layers and components are mounted on one side of a package substrate according to the present invention. [Figure 14] FIG. 14 is a cross-sectional view showing the positional relationship of the glass substrate, metal sheet, bonding film, etc. in the present invention after TGV processing. [Figure 15] FIG. 15 is a cross-sectional view of an assembled TGV-processed laminated glass substrate according to the present invention. [Figure 16] FIG. 16 is a cross-sectional view of a laminated glass substrate according to the present invention in which the inside of the TGV is made conductive by a metal wire. [Figure 17] FIG. 17 is a cross-sectional view of a laminated glass substrate according to the present invention, one side of which has been flattened by grinding-CMP. [Figure 18] FIG. 18 shows an example of a finished laminated glass substrate with TGV according to the present invention. [Figure 19] FIG. 19 is a cross-sectional view of a laminated glass substrate showing a warpage adjusting sheet. [Figure 20] FIG. 20 is an example showing the effect of the Cu warpage adjusting sheet when the thin glass substrate according to the present invention is used. [Figure 21] FIG. 21 is an example showing the effect of the Al warpage adjustment sheet when a thin glass substrate according to the present invention is used. DETAILED DESCRIPTION OF THE INVENTION

[0026] Hereinafter, an embodiment of the present invention will be described with reference to the drawings, but the present invention is not limited to this embodiment. Since the actual wiring patterns and component mounting layouts vary widely, this invention considers them as being replaced with the thickness of the Cu wiring pattern. In other words, assuming a normal thickness of one layer of, say, 5 μm, we propose a stacked structure in which the amount of warpage does not change significantly even if the number of layers increases.

[0027] Temperature changes were measured using a thermal shock test specified in Section 9.2 of JIS C5012-1993 (Condition 1: 175°C and -65°C, Condition 2: 125°C and -65°C), and the warpage at the high temperature of Condition 1 or Condition 2 is set to 0 mm, and the amount of warpage at the low temperature is shown. Convex (mountain warpage) is shown as a positive value, and concave (valley warpage) as a negative value.

[0028] The glass substrate currently under consideration is 510 x 515 mm, and four 240 x 240 mm pieces are laid out within it, so we will consider the warpage over a length of 240 mm.

[0029] The main cause of warpage is the difference in CTE between the copper wiring material and the glass substrate material. Table 1 shows the main physical properties of each material. Table 1 TIFF2025142185000002.tif4779

[0030] FIG. 1 is a cross-sectional view of a laminate in which a copper (Cu) plating film 5 is formed on one surface of a glass substrate 1 using a seed layer 10 based on, for example, titanium (Ti) or the like. Figure 2 shows the results of calculations using a program to calculate the amount of warpage of a printed circuit board, assuming the configuration of Figure 1, with an alkali-free glass substrate 1 having a CTE of 3.9 ppm / K and a Young's modulus E of 77 GPa, and copper 5 having a CTE of 17 ppm / K and an E of 210 GPa. The length of the board is 240 mm, and the thicknesses are 1.0 mm and 0.5 mm.

[0031] As a result, even with a glass thickness of 1.0 mm, the amount of warping increases in proportion to the plating thickness. Therefore, it is necessary to form a Cu wiring pattern on the underside opposite the substrate to offset the warping. Figure 3 is a diagram that illustrates this, and shows that no warping occurs on the substrate 1.

[0032] Figure 4 shows an example of an actual glass package substrate. A wiring layer 2 using a Cu pattern 5 is formed on the top surface of a glass substrate 1, and a semiconductor chip 10 is mounted on top of that using bumps 11. A wiring layer 3 using a Cu pattern 6 is formed on the bottom surface, and a BGA 12 using solder balls is formed on the bottom surface. Furthermore, a through hole 13 is formed in the glass substrate 1, and the inner wall is made conductive by copper plating or the like, thereby electrically connecting the wiring layer 2 and the wiring layer 3.

[0033] As described above, a major challenge is to develop design technology that optimizes the wiring patterns 5 and 6 and component mounting 10 while maintaining a balance so that warpage caused by CTE does not occur on the top and bottom of the glass substrate 1. Furthermore, the process of forming the wiring layers 2 and 3 on both sides of a large 510 x 515 mm glass substrate is a production process that places a heavy load on the process.

[0034] The present invention provides a laminated structure using a glass substrate that does not warp significantly due to temperature changes even when wiring layers and component mounting are formed on only one side of the substrate 1. Of course, if necessary, through holes can be formed to provide a BGA or wiring layer on the opposite side of the substrate 1.

[0035] 5 is a cross-sectional view showing the concept of the laminated structure according to claim 1 of the present invention. A metal sheet 20 is sandwiched between glass substrates 1 and 2, and the interfaces are bonded together with an adhesive, a silane coupling adhesive, or an inorganic thin film. A Cu wiring pattern 5 is formed on one side of the surface of the laminate. Even if the thickness of the Cu pattern increases, if the increase in the amount of warping is only a small change, it will be possible to form a wiring layer on only one side of the board and even mount components, thereby significantly reducing the design and production loads.

[0036] As explained in Figure 3, even if the wiring layer 5 is made of a copper material having a CTE of 17 ppm / K on the surface of the glass substrate 1 having a CTE of 3.9 ppm / K, no warping will occur if copper wiring 6 is formed on the opposite surface. However, even if the thickness of the wiring layer 5 increases, instead of increasing the thickness of the wiring layer 6, a sheet 20 having a thickness greater than the thickness of the wiring layer 5 can be laminated, and its influence can be suppressed by the glass substrate 4 on which it is further laminated, thereby making it possible to keep the change in warping to a minimum and not increase proportionally with the increase in thickness of the wiring layer 5.

[0037] Fig. 6 compares the amount of warpage between the two-layer structure consisting of the glass substrate 1 (thickness: 0.1 mm to 1.0 mm) and Cu plating layer 5 (thickness: 5 μm) shown in Fig. 1 and the four-layer structure shown in Fig. 5, using the thickness of the substrate as a variable. The four-layer structure is a laminated structure in which a 10 μm-thick Cu metal sheet 20 is inserted between a 0.5 mm glass substrate 1 and a glass substrate 4 on which a 5 μm-thick Cu plating layer has been formed, and the graph shows the change in the amount of warpage as the thickness of the glass substrate 4 is changed from 0.1 mm to 1.0 mm.

[0038] As is clear from this, in a two-layer structure, as the glass thickness becomes thinner, the warpage increases due to the difference in CTE with Cu, but in a four-layer structure, even if the base glass substrate 4 is made thinner, the amount of warpage is low and stable, and the amount of change is minimal, which shows that two thin glass substrates that are easy to process can be used and single-sided RDL and mounting can be performed.

[0039] In the laminated structure of Figure 5, when metal sheet 20 is a 1.0 mm copper sheet and the thickness of glass substrates 1 and 4 and the Cu plating thickness are changed, the change in the amount of warpage is shown in Table 2. The graph is shown in Figure 7. Table 2: Amount of warpage of the board (mm) TIFF2025142185000003.tif4185The temperature range is the thermal shock test (condition 2: 125°C and -65°C) specified in Section 9.2 of JIS C5012-1993, and the warpage is 0mm on the high temperature side of 125°C for a length of 240mm, and the warpage is shown on the low temperature side of -65°C.In this configuration, all are on the positive side, indicating a convex warp. It can be seen that a glass thickness of 0.1 mm results in the smallest change in warpage relative to variations in plating thickness, but other glass thicknesses are also less than 0.5 mm.

[0040] In an ideal case, if the amount of warpage is 0 mm at an intermediate temperature between high and low temperatures, i.e., 30°C, the amount of warpage on the high temperature side will be half the concave warpage shown in Table 2, pass through a flat state at the intermediate temperature, and then become convex warpage on the low temperature side. Naturally, the actual state of warpage after mounting etc. is important, but in the laminate structure of this invention, although the amount of change in plating thickness was assumed to be a load component of the layout such as wiring pattern and component mounting, it is clear from the results in Table 2 that the design margin is very large.

[0041] Although the present invention can minimize board warpage even when wiring patterns and components are mounted on one side of the board, this does not preclude the provision of wiring patterns on the opposite side to the mounted side in order to further reduce warpage. In other words, in the cross-sectional view of Figure 5, a metal pattern or the like can be used on the surface of glass substrate 4 to ensure high flatness of the entire board or important areas. In this case, if circuit connections are not required, through holes are also unnecessary.

[0042] Table 3 shows the change in the amount of warpage when the thickness of the glass substrates 1 and 4 and the Cu plating thickness were changed, using a 1.0 mm aluminum sheet as the inserting metal sheet. Figure 8 shows the graph. Table 3 TIFF2025142185000004.tif3280

[0043] Unlike when the inserted metal sheet is Cu 1.0mm, the glass thickness of 0.1mm varies greatly, with 0.2~0.3mm being the minimum. If two sheets of glass with the same thickness are used overall, it can be seen that 0.25mm is the best thickness, but the optimum condition for glass packaging is determined by various factors.

[0044] The bonding between the inserted metal sheet and the glass substrate is achieved at each interface as described in claim 1. The bonding can be achieved by various bonding methods, such as chemical bonding using a coupling agent, atomic diffusion of inorganic materials, bonding between inorganic materials, or bonding using the van der Waals force of adhesives or pressure sensitive adhesives, or a combination of these.

[0045] This invention bonds the surface of a glass substrate to a copper or aluminum metal sheet inserted between the glass substrates, but various film deposition processes, such as the deposition of a silicon film for surface activated bonding, or the deposition of a few microns of other metal on the surface of the copper or aluminum sheet to pretreat the bonding or change the CTE, or the deposition of films on both sides of the sheet, do not have a significant effect. Even when a coupling agent is adsorbed, the adsorption thickness is on the nanometer level, so the adsorption thickness does not affect warping.

[0046] When using a pressure sensitive adhesive sheet or adhesive sheet as a bonding agent, the sheet thickness is generally 10 μm or more, and the CTE, E (Young's modulus), and thickness can ultimately affect warpage, as explained below.

[0047] As shown in Figure 9(A), glass substrates 1 and 4 are joined together using a metal sheet 20 and an adhesive sheet 21. In this state, as can be seen from the cross section, the glass substrates are symmetrical from top to bottom, and no warping occurs. Next, a seed layer is formed on the surface of glass surface 1, and a copper wiring pattern 5 is then formed, followed by the formation of a redistribution layer (RDL) and lands for mounting components.

[0048] Figure 10 shows the change in substrate warpage as a function of the amount of Cu plating 5 when using an organic polymer adhesive sheet 21 (100 μm thick, E=1 GPa, CTE=100 ppm / K) as shown in Figure 9(B), with glass thicknesses of 0.20 mm, 0.25 mm, and 0.30 mm. The inserted metal sheet 20 is 1.0 mm aluminum. The inflection point in the warpage direction is between glass thicknesses of 0.20 mm and 0.30 mm, and at a thickness of 0.25 mm, no substrate warpage occurs even when the Cu plating wiring layer is increased.

[0049] When the inserting metal sheet 20 is made of a copper-based material, an inflection point exists when the CTE of pure copper (17.7 ppm / K) is made closer to the CTE of aluminum (23.9 ppm / K). Table 4 shows the types of copper-based alloys and their representative physical properties.

[0050] Table 4 TIFF2025142185000005.tif2799

[0051] Among these, C2680 and C2801, which have CTEs close to that of aluminum, were used as the metal sheet 20, and the specifications for the sheet thickness, glass thickness, etc. and the amount of warpage depending on the Cu plating thickness are shown in Table 5. The graph is also shown in Figure 11. In a thermal shock temperature test (125°C → -65°C), Sample-A, which uses 0.5mm of C2801 with a CTE of 20.8ppm / K, exhibited concave warping, while Sample-B, which uses 0.5mm of C2680 with a CTE of 20.3ppm / K, exhibited convex warping. After examining a structure that was intermediate between these, that is, one that would only produce minute warping, Sample-C (metal sheet C2680 0.7mm, glass thickness 0.25mm, adhesive sheet 0.1mm) was selected.

[0052] Table 5 TIFF2025142185000006.tif4286

[0053] The present invention constructs a glass package substrate by inserting a copper, aluminum, or alloy sheet 20 between two alkali-free glass substrates having properties close to the CTE of a Si chip and bonding the interfaces using various bonding techniques. The basic structure is a stacked package that is symmetrical from top to bottom but has strong resistance to warping caused by loads that destroy the symmetry, such as RDL. In other words, due to the mutual influence of the thickness, length, CTE, Young's modulus, etc. of each constituent material, a package stack structure is provided that is extremely resistant to warping of the substrate due to temperature changes, even when a copper wiring pattern, interposer substrate, semiconductor chip, electronic components, etc. are mounted on one side of the substrate. However, there is no single solution, and the structure can be selected depending on the materials used, application, etc.

[0054] As shown in Figure 12, the glass package is formed by laying out four package units 50, each measuring 240 x 240 mm, in two columns and two rows, on a large glass substrate 100 measuring, for example, 510 x 515 mm. A metal sheet 20 is inserted within the package units 50, and processing is performed so that the glass substrates 1, 4 and the metal sheet 20 are bonded only in the area of ​​the package units 50. The processing is performed according to the bonding method, such as adsorption processing on the surface, film formation processing, and adhesive sheet lamination processing.

[0055] By providing sealing 22 using, for example, UV resin around the periphery of the large substrate, it can be treated as a single substrate, and it is easy to apply not only plating processes but also processes for flat displays such as organic EL to the surface of the glass substrate 1 to form films, RDL formation processes using photolithography, and active elements. If the process does not affect the material of the metal sheet 20, it is also possible to select a method in which the dimensions of the metal sheet 22 and the bonding treatment area 21 are the same as those of the substrates 1 and 2, and bonding is limited to the periphery, without sealing.

[0056] 13 shows an example according to the present invention, in which a wiring layer 2 is formed on a substrate 1 and a semiconductor element 10 with bumps 11 is mounted on it. Connection to an external circuit can be achieved via input / output terminals 14 using, for example, a connector, ACF (anisotropic conductive film), or soldering. Fixing to the frame can be achieved by using fixing holes provided around the periphery of the metal sheet, allowing the package substrate to be held without applying stress to the glass substrate.

[0057] In the laminated structure according to the present invention, through holes (TGVs) can be provided to obtain electrical continuity between both surfaces of the glass substrate, as in the conventional case. In the case of conventional package substrates that use a single glass substrate, thick glass substrates, such as 1 mm thick, have been proposed to prevent warping, but this poses challenges in terms of reliability, as well as the need for TGV processing with a via diameter of 50 μm, i.e., an aspect ratio of 1:20, and the need to plate the inner walls to make them conductive.

[0058] In the present invention, the upper and lower glass substrates 1 and 4 to be bonded to the interposed metal sheet 20 can be very thin, e.g., 0.2 mm, making via processing easy. Furthermore, via processing in the interposed metal sheet can be performed using laser processing, etching, punching, machining, and other methods. The surface condition of the glass substrates 1 and 4 and the interposed metal sheet 20 does not require a high degree of flatness when an organic polymer adhesive sheet is used. However, bonding methods such as surface activated bonding and atomic diffusion bonding require a high degree of flatness on the surface of the material, and therefore require treatments such as polishing, adsorption, and film formation appropriate for the bonding method.

[0059] In the laminated structure of the glass substrate for packaging according to the present invention, the metal sheet 20 is inserted, so the method of making the inner wall of the TGV conductive cannot be used, and therefore two methods are proposed. The first method is described in Japanese Patent Application No. 2024-041792 (priority claimed), in which a metal wire is passed through the via hole space without contacting the wall surface, and both ends are bonded to electrodes on the glass substrates 1 and 4. The second method is to make the metal sheet 20, preferably the aluminum sheet, at least in the vicinity of the via holes an insulating film such as aluminum oxide, which makes it possible to make the inner walls conductive by plating, and can also be used to make the first metal wire conductive.

[0060] An example of the first method will be described. As shown in Figure 14, through-holes 9 are formed in glass substrates 1 and 4 by either laser processing or photolithographic etching. Next, a titanium (Ti) seed layer is vacuum-formed over the entire surface of one side, followed by a Cu film several micrometers thick formed by electroplating. When the glass thickness is 0.2 mm, the Ti film thickness is 500 nm (CTE = 8.5 ppm / K, E = 107 GPa), the Cu film thickness is 2 μm, and the plating temperature is 40°C, the linear warpage of L = 510 mm is approximately 3 mm, and warpage is not a major problem in actual sheet shapes.

[0061] Through holes are also formed in the metal sheet 20 in the areas corresponding to the via holes in the glass substrate, but if the material is copper, copper alloy, or a general aluminum sheet, the diameter of the through holes is made larger than the diameter of the through holes in the glass substrates 1 and 4 to prevent electrical shorts with the metal wires that pass through. Figure 15 shows a cross-sectional view of the glass substrates 1 and 4 and metal sheet 20 bonded together in this state. For positioning during bonding, via holes for pattern recognition or alignment can be created in multiple locations and used for mechanical alignment.

[0062] 16 shows an example in which a metal wire, for example, a metal wire 30 for wire bonding, is passed through a through hole 9 and ball bonded 31 or wedge bonded to a metal pattern 8 on the surface of glass substrates 1 and 4 using, for example, an ultrasonic bonding device. It is preferable that the through hole 9 be sealed from both sides of the substrate, and if sealing is not complete using wedge bonding or the like, it is better to perform a sealing process using low-melting point solder or the like.

[0063] FIG. 17 is a cross-sectional view showing a state where the wiring pattern surface 8 including the bonding portion 31 of the glass substrate 1 has been flattened by grinding or CMP. This substrate can be treated like a single glass substrate 100, and various wiring patterns, active elements, etc. can be formed using processes such as CVD film formation for flat displays, sputtering film formation, and photolithography.

[0064] Fig. 19 is a cross-sectional view of a laminate relating to claim 7, in which a warpage-adjusting metal sheet 24 is attached to the back surface of the glass substrate 4 of the laminate (Fig. 5) according to the present invention. The Cu plating thickness is set to 50µm as a CTE-related load of the wiring layer, interposer, components, etc. formed on the glass substrate 1 side, and the temperature change is set to a thermal shock test (condition 2: 125°C and -65°C) specified in Section 9.2 of JIS C5012-1993, to see the effect of the thickness of the warpage-adjusting sheet 24.

[0065] Figure 20 and Table 7 show the effect of using 0.4mm thick Al as the inserted metal sheet, a laminate of two 0.3mm and two 0.15mm glass substrates, and a Cu sheet as the warpage adjustment sheet. As a reference, the 2-layer G1.0mm shows the change in warpage when the glass substrate is 1.0mm thick. The four-layer structure of the present invention provides a better adjustment effect against warpage in the Cu sheet. At the same time, the four-layer structure also has the advantage of being lighter and thinner in terms of weight and thickness.

[0066] Table 6 TIFF2025142185000007.tif56109

[0067] Figure 21 and Table 7 show the effect when an Al sheet is used as a warpage adjustment sheet in a laminate consisting of an Al 0.4 mm thick inserted metal sheet, two 0.5 mm, two 0.3 mm, and two 0.15 mm glass substrates. As a reference, the 2-layer G1.0 mm shows the change in warpage with a glass substrate thickness of 1.0 mm, but the warpage is far from the vicinity of 0 mm, indicating that the Al adjustment sheet has almost no effect.

[0068] In the four-layer structure of the present invention, it has been shown that even in the case of a two-ply 0.5 mm glass structure or a two-ply 0.15 mm glass structure, the amount of warpage can be adjusted to nearly 0 mm using an Al adjustment sheet, and the thickness and weight can also be made equal or less.

[0069] Table 7 TIFF2025142185000008.tif56133

[0070] The embodiments have been described above taking into account the effects of the present invention. However, the present invention is not limited to the above-described embodiments, and various modifications are possible within the scope of the gist of the present invention, since the optimal combination varies depending on the physical properties of the actual materials used. [Industrial Applicability]

[0071] To provide a laminated glass substrate for semiconductor packages with fine wiring and high density mounting, which realizes a state in which the glass substrate is almost free from warping not only when wiring is mounted on both sides of the glass substrate but also when wiring is mounted on one side, and further realizes a fixing method that quickly diffuses and dissipates heat generated from mounted semiconductors and the like, and minimizes stress applied to the glass substrate. [Explanation of symbols]

[0072] 1 Glass substrate A 2 Wiring layer A (RDL) 3 Wiring layer B (RDL) 4. Glass substrate B 5 Plating seed layer + Cu plating layer 6 Wiring Pattern 7 Wiring Pattern 8 plating seed layer + Cu plating layer 9 Through holes 10 Semiconductor chips 11 Bump 12 Solder resist 13 BGA 14 Input / Output Junction 20 metal sheets 21 Bonding sheet (bonding treatment layer) 22 Sealant 23 Joint 30 Metal Wire 31 Bonding section 50 per package 51 Fixing hole 100 large boards

Claims

1. A glass substrate for semiconductor packaging, characterized in that a metal sheet is inserted between glass substrate A and glass substrate B, and each interface is laminated and bonded by an organic material adhesive, a silane coupling agent, or thin film bonding using an inorganic thin film formed on the surface of each interface, or a combination thereof.

2. 2. The glass substrate for semiconductor packaging according to claim 1, wherein a seed layer for Cu plating is formed by vacuum deposition or the like on one side of a glass substrate having through holes at predetermined positions, and further plated as necessary, and the non-seed layer surface of said glass substrate A and substrate B is laminated and bonded at predetermined positions to a metal sheet surface having through holes with a diameter equal to or larger than the diameter of said through holes.

3. 3. The glass substrate for semiconductor packaging according to claim 2, wherein the glass substrates are laminated by inserting a metal sheet between the glass substrates A and B, and electrical continuity of the through holes of the glass substrates is achieved by forming an alloy of both ends of a metal wire inserted into the through holes with the seed metal layers of the substrates A and B or with a metal formed on the seed metal layers, or by mechanically fixing and electrically joining the both ends of the metal wire with lead-free solder.

4. 3. The glass substrate for semiconductor packaging according to claim 1, wherein the final outer dimensions of the metal sheet to be laminated and joined are made larger than the final outer dimensions of the glass substrate, so that the metal sheet serves to uniformize heat generated from the semiconductor mounting portion and diffuse it to the outside.

5. 3. The glass substrate for semiconductor packaging according to claim 1 or 2, wherein the final outer dimensions of the metal sheet to be laminated and joined are made larger than the final outer dimensions of the glass substrate, and the outer periphery is used for fixing to an external frame or the like, thereby mitigating direct mechanical stress on the glass substrate.

6. 3. The glass substrate for semiconductor packaging according to claim 1, wherein the metal sheet to be laminated and bonded is copper, aluminum, an alloy thereof, or a laminate thereof.

7. 3. A semiconductor package substrate according to claim 1 or 2, characterized in that in a laminated substrate formed by inserting and bonding a metal sheet between glass substrate A and glass substrate B, warping of the substrate due to temperature changes is minimized by attaching a Cu sheet or an Al sheet to the entire surface or a part of glass substrate B according to the thermal expansion coefficient load of the wiring pattern and component mounting on glass substrate A.

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