Display device

Abstract

To provide a low-cost display device.SOLUTION: A display device has a pixel and an IC chip. The pixel has a first pixel circuit having a display element, and a second pixel circuit having a light-receiving element. In one IC chip, a control circuit, a data driver circuit, and a readout circuit are provided. The first and second pixel circuits are electrically connected to the readout circuit. The control circuit has a function of controlling driving of the data driver circuit or the readout circuit. The data driver circuit has a function of supplying image data to the first pixel circuit. The readout circuit has a function of, in the case where monitoring current flows in the first pixel circuit, outputting a monitoring signal corresponding to the monitoring current. The readout circuit has a function of outputting an imaging signal corresponding to imaging data acquired by the second pixel circuit.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] BACKGROUND OF THE INVENTION 1. Field of the Invention One embodiment of the present invention relates to a display device and a driving method thereof, or to a semiconductor device and a driving method thereof.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. One embodiment of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. One embodiment of the present invention relates to a process, a machine, a manufacture, or a composition of matter. Therefore, more specific examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices, input / output devices, driving methods thereof, and manufacturing methods thereof.

[0003] In this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. Semiconductor elements such as transistors, as well as semiconductor circuits, arithmetic devices, and memory devices are examples of semiconductor devices. Imaging devices, display devices, liquid crystal display devices, light-emitting devices, input devices, input / output devices, electro-optical devices, power generation devices (including thin-film solar cells, organic thin-film solar cells, etc.), and electronic devices may include semiconductor devices. [Background technology]

[0004] In recent years, mobile information terminals such as smartphones and tablet terminals have become widespread. These mobile information terminals often use display devices equipped with an active matrix display unit, a touch sensor, etc. Patent Document 1 discloses a technology in which a single IC serves as both a drive circuit for the display unit and a drive circuit for the touch sensor.

[0005] Light-emitting elements that utilize electroluminescence (EL) have been attracting attention as display elements for pixels arranged in a matrix in a display section of a display device. Known examples of such light-emitting elements include organic EL elements and inorganic EL elements. These light-emitting elements emit light themselves, providing higher visibility of displayed images than display devices that use liquid crystal elements. Other advantages include the absence of a backlight and a fast response speed.

[0006] An organic EL element includes a layer (hereinafter referred to as an EL layer) containing a light-emitting organic compound between a pair of electrodes. When a voltage is applied between the pair of electrodes, light is emitted from the EL layer. An example of a display device using such an organic EL element is disclosed in Patent Document 2. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Japanese Patent Application Laid-Open No. 2017-16098 [Patent Document 2] Japanese Patent Application Laid-Open No. 2002-324673 Summary of the Invention [Problem to be solved by the invention]

[0008] When light-emitting elements such as organic EL elements are used as display elements, an image can be displayed on a display unit by controlling the current flowing through the light-emitting elements. Here, if the threshold voltage of a driving transistor, which is electrically connected to the light-emitting elements and has a function of controlling the current flowing through the light-emitting elements according to image data written to the pixels, varies from pixel to pixel, display unevenness or the like may occur. Therefore, a display device having light-emitting elements preferably has a function of reading out the magnitude of the current flowing between the drain and source of the driving transistor as monitor current data. Display unevenness or the like can be reduced by correcting the threshold voltage or the like of the driving transistor based on the current value represented by the monitor current data.

[0009] As a method for providing a display device with a function as a touch sensor, for example, a method for providing a light receiving element in a pixel where a display element is provided can be given. By providing a pixel with not only a display element but also a light receiving element, it is possible to detect a finger or the like touching the display unit where the pixel is provided.

[0010] If a display device having light-emitting elements is provided with both a function for reading monitor current data and a function such as a touch sensor, the display device can detect, for example, a finger touching the display while reducing display unevenness. In this case, the display device must be provided with not only a data driver circuit that supplies image data to pixels, but also a circuit that reads monitor current data and a circuit that reads imaging data acquired using light-receiving elements. Here, for example, if the data driver circuit, the circuit that reads monitor current data, and the circuit that reads imaging data are provided in different ICs (semiconductor integrated circuits), the number of ICs required in the display device will increase, which will increase the manufacturing cost of the display device.

[0011] An object of one embodiment of the present invention is to provide a display device that functions as a sensor. Another object is to provide a low-cost display device. Another object is to provide a display device that can display a high-quality image. Another object is to provide a display device whose driving can be easily controlled. Another object is to provide a display device that can display a high-brightness image. Another object is to provide a display device with low power consumption. Another object is to provide a highly reliable display device. Another object is to provide a novel display device. Another object is to provide a novel semiconductor device.

[0012] Another object is to provide a method for driving a display device having a function as a sensor. Another object is to provide a low-cost method for driving a display device. Another object is to provide a method for driving a display device that can display a high-quality image. Another object is to provide a method for driving a display device that can be easily controlled. Another object is to provide a method for driving a display device that can display a high-brightness image. Another object is to provide a method for driving a display device that consumes low power. Another object is to provide a method for driving a highly reliable display device. Another object is to provide a novel method for driving a display device. Another object is to provide a novel method for driving a semiconductor device.

[0013] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these can be extracted from the description of the specification, drawings, claims, etc. [Means for solving the problem]

[0014] One embodiment of the present invention is a display device including a pixel and an IC chip. The pixel includes a first pixel circuit having a display element and a second pixel circuit having a light-receiving element. The IC chip includes a control circuit, a data driver circuit, and a readout circuit. The first pixel circuit and the readout circuit are electrically connected to each other through a first wiring, and the second pixel circuit and the readout circuit are electrically connected to each other through a second wiring. The control circuit has a function of supplying a clock signal to the data driver circuit and the readout circuit. The data driver circuit has a function of supplying image data to the first pixel circuit. The readout circuit has a function of outputting a first signal corresponding to a potential of the first wiring. The readout circuit has a function of outputting a second signal corresponding to a potential of the second wiring.

[0015] Alternatively, in the above aspect, the readout circuit may have an A / D conversion circuit, and the A / D conversion circuit may have a first transistor, a second transistor, and a comparison circuit, one of the source or drain of the first transistor may be electrically connected to a first wiring, one of the source or drain of the second transistor may be electrically connected to a second wiring, the other of the source or drain of the first transistor and the other of the source or drain of the second transistor may be electrically connected to a first input terminal of the comparison circuit, and the first and second signals may be digital signals output from the A / D conversion circuit.

[0016] Alternatively, in the above aspect, the readout circuit may include a reference signal generation circuit, and the reference signal generation circuit may be electrically connected to the second input terminal of the comparison circuit.

[0017] Alternatively, in the above aspect, the readout circuit may include an A / D conversion circuit, and the A / D conversion circuit may include a first transistor, a second transistor, a third transistor, a first capacitor, and a comparison circuit, wherein one of a source or a drain of the first transistor is electrically connected to a first wiring, one of a source or a drain of the second transistor is electrically connected to a second wiring, the other of the source or the drain of the first transistor and the other of the source or the drain of the second transistor are electrically connected to one of a source or a drain of the third transistor, the other of the source or the drain of the third transistor is electrically connected to one electrode of the first capacitor, and the other electrode of the first capacitor is electrically connected to a first input terminal of the comparison circuit.

[0018] Alternatively, in the above aspect, the readout circuit may include a reference signal generating circuit, the A / D conversion circuit may include a fourth transistor and a second capacitor, the reference signal generating circuit may be electrically connected to one of the source or drain of the fourth transistor, the other of the source or drain of the fourth transistor may be electrically connected to one electrode of the second capacitor, and the other electrode of the second capacitor may be electrically connected to a second input terminal of the comparison circuit.

[0019] Alternatively, in the above aspect, the A / D conversion circuit may have a fifth transistor and a sixth transistor, one of the source or drain of the fifth transistor being electrically connected to one electrode of the first capacitor, one of the source or drain of the sixth transistor being electrically connected to one electrode of the second capacitor, and the other of the source or drain of the fifth transistor and the other of the source or drain of the sixth transistor being electrically connected to a power supply line.

[0020] Alternatively, in the above embodiment, the second transistor may have a metal oxide in a channel formation region.

[0021] Alternatively, one embodiment of the present invention includes pixels arranged in a matrix, an IC chip, a gate driver circuit, and a row driver circuit. The pixels include a first pixel circuit having a display element and a second pixel circuit having a light-receiving element. One IC chip includes a control circuit, a data driver circuit, and a readout circuit. The control circuit has a function of supplying a clock signal to the gate driver circuit, the row driver circuit, the data driver circuit, and the readout circuit. The gate driver circuit has a function of supplying a first scan signal to the first pixel circuit to select the first pixel circuit to which image data is supplied. The row driver circuit A display device having a function of selecting a second pixel circuit from which imaging data is to be read out by supplying a second scanning signal to the second pixel circuit, a data driver circuit having a function of supplying image data to a first pixel circuit selected by a gate driver circuit, a readout circuit having a function of reading out imaging data from a second pixel circuit selected by a row driver circuit, a gate driver circuit having a function of outputting a first scanning signal during a period in which the row driver circuit is not outputting a second scanning signal, and a row driver circuit having a function of outputting a second scanning signal during a period in which the gate driver circuit is not outputting the first scanning signal.

[0022] Alternatively, in the above aspect, the first pixel circuit may include a display element and a driving transistor, the readout circuit may include an A / D conversion circuit, the A / D conversion circuit may include a first transistor, a second transistor, and a comparison circuit, one electrode of the display element may be electrically connected to one of a source or a drain of the driving transistor, one of the source or the drain of the first transistor may be electrically connected to the first pixel circuit, one of the source or the drain of the second transistor may be electrically connected to the second pixel circuit, the other of the source or the drain of the first transistor and the other of the source or the drain of the second transistor may be electrically connected to a first input terminal of the comparison circuit, the A / D conversion circuit may have a function of outputting a signal corresponding to a current flowing between the drain and source of the driving transistor, and the A / D conversion circuit may have a function of outputting an imaging signal corresponding to imaging data.

[0023] Alternatively, in the above aspect, the readout circuit may include a reference signal generation circuit, and the reference signal generation circuit may be electrically connected to the second input terminal of the comparison circuit.

[0024] Alternatively, in the above aspect, the first pixel circuit includes a display element and a driving transistor, the readout circuit includes an A / D conversion circuit, and the A / D conversion circuit includes a first transistor, a second transistor, a third transistor, a first capacitor, and a comparison circuit, one electrode of the display element is electrically connected to one of a source or a drain of the driving transistor, one of a source or a drain of the first transistor is electrically connected to the first pixel circuit, one of a source or a drain of the second transistor is electrically connected to the second pixel circuit, The other of the source or drain of the driving transistor and the other of the source or drain of the second transistor are electrically connected to one of the source or drain of a third transistor, the other of the source or drain of the third transistor is electrically connected to one electrode of a first capacitor, and the other electrode of the first capacitor is electrically connected to a first input terminal of a comparison circuit, and the A / D conversion circuit has a function of outputting a signal corresponding to a current flowing between the drain and source of the driving transistor, and the A / D conversion circuit may have a function of outputting an imaging signal corresponding to imaging data.

[0025] Alternatively, in the above aspect, the readout circuit may include a reference signal generating circuit, the A / D conversion circuit may include a fourth transistor and a second capacitor, the reference signal generating circuit may be electrically connected to one of the source or drain of the fourth transistor, the other of the source or drain of the fourth transistor may be electrically connected to one electrode of the second capacitor, and the other electrode of the second capacitor may be electrically connected to a second input terminal of the comparison circuit.

[0026] Alternatively, in the above aspect, the A / D conversion circuit may have a fifth transistor and a sixth transistor, one of the source or drain of the fifth transistor being electrically connected to one electrode of the first capacitor, one of the source or drain of the sixth transistor being electrically connected to one electrode of the second capacitor, and the other of the source or drain of the fifth transistor and the other of the source or drain of the sixth transistor being electrically connected to a power supply line.

[0027] Alternatively, in the above embodiment, the second transistor may have a metal oxide in a channel formation region. [Effects of the Invention]

[0028] According to one embodiment of the present invention, a display device having a function as a sensor can be provided. Alternatively, a low-cost display device can be provided. Alternatively, a display device capable of displaying a high-quality image can be provided. Alternatively, a display device whose driving can be easily controlled can be provided. Alternatively, a display device capable of displaying a high-brightness image can be provided. Alternatively, a display device with low power consumption can be provided. Alternatively, a highly reliable display device can be provided. Alternatively, a novel display device can be provided. Alternatively, a novel semiconductor device can be provided.

[0029] Alternatively, a method for driving a display device having a function as a sensor can be provided. Alternatively, a method for driving a low-cost display device can be provided. Alternatively, a method for driving a display device capable of displaying a high-quality image can be provided. Alternatively, a method for driving a display device that can be easily controlled can be provided. Alternatively, a method for driving a display device that can display a high-brightness image can be provided. Alternatively, a method for driving a display device with low power consumption can be provided. Alternatively, a method for driving a display device with high reliability can be provided. Alternatively, a novel method for driving a display device can be provided. Alternatively, a novel method for driving a semiconductor device can be provided.

[0030] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Note that effects other than these will become apparent from the description in the specification, drawings, claims, etc., and it is possible to extract other effects from the description in the specification, drawings, claims, etc. [Brief explanation of the drawings]

[0031] [Figure 1] 1A and 1B are schematic diagrams showing configuration examples of a display device. [Figure 2] 2A and 2B are block diagrams showing examples of the configuration of a display device. [Figure 3] Figure 3A and Figures 3D to 3F are schematic diagrams showing examples of pixel configurations, and Figures 3B and 3C are cross-sectional views showing examples of the configuration of a display device. [Figure 4] FIG. 4 is a block diagram showing an example of the configuration of the display device. [Figure 5] FIG. 5 is a timing chart showing an example of a method for driving a display device. [Figure 6] FIG. 6 is a block diagram showing an example of the configuration of a display device. [Figure 7] FIG. 7 is a block diagram showing an example of the configuration of a display device. [Figure 8] FIG. 8 is a circuit diagram showing an example of the configuration of a pixel. [Figure 9] FIG. 9 is a circuit diagram showing an example of the configuration of a pixel. [Figure 10] FIG. 10 is a circuit diagram showing an example of the configuration of a pixel. [Figure 11] Fig. 11A is a circuit diagram showing an example of the configuration of a pixel, and Fig. 11B is a timing chart showing an example of a method for driving the pixel. [Figure 12] 12A and 12B are circuit diagrams showing examples of the configuration of a display device. [Figure 13] FIG. 13 is a timing chart showing an example of a method for driving a display device. [Figure 14] 14A and 14B are circuit diagrams showing configuration examples of a display device. [Figure 15] FIG. 15 is a timing chart showing an example of a method for driving a display device. [Figure 16] FIG. 16 is a circuit diagram showing an example of a method for driving a display device. [Figure 17] 17A and 17B are circuit diagrams showing an example of a method for driving a display device. [Figure 18]18A and 18B are circuit diagrams showing an example of a method for driving a display device. [Figure 19] FIG. 19 is a timing chart showing an example of a method for driving a display device. [Figure 20] 20A and 20B are circuit diagrams showing an example of a method for driving a display device. [Figure 21] FIG. 21 is a timing chart showing an example of a method for driving a display device. [Figure 22] 22A and 22B are circuit diagrams showing an example of a method for driving a display device. [Figure 23] 23A to 23C are cross-sectional views showing configuration examples of a display device. [Figure 24] 24A to 24C are cross-sectional views showing configuration examples of a display device. [Figure 25] 25A to 25C are cross-sectional views showing configuration examples of a display device. [Figure 26] 26A to 26C are cross-sectional views showing configuration examples of a display device. [Figure 27] FIG. 27 is a cross-sectional view showing an example of the configuration of a display device. [Figure 28] 28A and 28B are cross-sectional views showing configuration examples of a display device. [Figure 29] 29A and 29B are cross-sectional views showing configuration examples of a display device. [Figure 30] FIG. 30 is a cross-sectional view showing an example of the configuration of a display device. [Figure 31] FIG. 31 is a cross-sectional view showing a configuration example of a semiconductor device. [Figure 32] FIG. 32 is a cross-sectional view showing an example of the configuration of a semiconductor device. [Figure 33] 33A to 33C are cross-sectional views showing examples of the configuration of a transistor. [Figure 34] 34A is a top view illustrating an example of the structure of a transistor, and FIGS. 34B and 34C are cross-sectional views illustrating an example of the structure of a transistor. [Figure 35]35A is a top view illustrating an example of the structure of a transistor, and FIGS. 35B and 35C are cross-sectional views illustrating an example of the structure of a transistor. [Figure 36] Figure 36A is a diagram explaining the classification of IGZO crystal structures, Figure 36B is a diagram explaining the XRD spectrum of a CAAC-IGZO film, and Figure 36C is a diagram explaining the electron microbeam diffraction pattern of a CAAC-IGZO film. [Figure 37] 37A and 37B are perspective and cross-sectional views showing an example of an electronic device. [Figure 38] 38A to 38D are diagrams showing an example of an electronic device. [Figure 39] 39A to 39F are diagrams showing an example of an electronic device. DETAILED DESCRIPTION OF THE INVENTION

[0032] Hereinafter, embodiments will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways, and that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the following embodiments. In the configuration of the invention described below, the same parts or parts having similar functions will be denoted by the same reference numerals in different drawings, and repeated descriptions thereof will be omitted.

[0033] In addition, in this specification, the following embodiments can be combined as appropriate. In addition, when multiple configuration examples are shown in one embodiment, the configuration examples can be combined as appropriate.

[0034] In addition, in the drawings, the size, layer thickness, or area may be exaggerated for clarity. Therefore, it is not necessarily limited to the scale. Note that the drawings are schematic illustrations of ideal examples, and are not limited to the shapes, values, etc. shown in the drawings.

[0035] Furthermore, the terms "electrode" and "wiring" used in this specification and elsewhere do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, the terms "electrode" and "wiring" also include cases where multiple "electrodes" or "wirings" are integrally formed.

[0036] Furthermore, voltage often refers to the potential difference between a certain potential and a reference potential (for example, ground potential or source potential). Therefore, voltage and potential can often be interchanged. In this specification and the like, unless otherwise specified, voltage and potential can be interchanged.

[0037] In addition, ordinal numbers such as "first" and "second" used in this specification are used to avoid confusion between components, and do not indicate any order or ranking, such as the order of processes or stacking. Even if a term does not have an ordinal number in this specification, an ordinal number may be added in the claims to avoid confusion between components. Even if a term has an ordinal number in this specification, a different ordinal number may be added in the claims. Even if a term has an ordinal number in this specification, the ordinal number may be omitted in the claims.

[0038] In this specification, the "conducting state" of a transistor refers to a state in which the source and drain of the transistor are considered to be electrically short-circuited. The "non-conducting state" of a transistor refers to a state in which the source and drain of the transistor are considered to be electrically disconnected. For example, a transistor in a conducting state can be operated in a linear region.

[0039] In this specification, the term "on-state current" may refer to a current that flows between the source and drain when a transistor is in a conductive state, and the term "off-state current" may refer to a current that flows between the source and drain when a transistor is in a non-conductive state.

[0040] (Embodiment 1) In this embodiment, a display device according to one embodiment of the present invention will be described.

[0041] One embodiment of the present invention relates to a display device in which pixels, each having a light-emitting element and a light-receiving element, are arranged in a matrix. By providing a pixel with not only a light-emitting element but also a light-receiving element, the display device can not only display an image but also have a function such as a touch sensor. On the other hand, when a pixel includes a light-emitting element and a light-receiving element, the display device needs to include not only a data driver circuit that supplies image data representing an image displayed using the light-emitting element to the pixel, but also a circuit (readout circuit) that reads image data acquired using the light-receiving element. In one embodiment of the present invention, the data driver circuit and the readout circuit are provided on the same IC chip. This allows the display device to be manufactured at a lower cost than when the data driver circuit and the readout circuit are provided on different IC chips.

[0042] Furthermore, when a light-emitting element is used as a display element for displaying an image, an image can be displayed on a display unit by controlling the light-emitting luminance by controlling the current flowing through the light-emitting element. Here, if the threshold voltage of a driving transistor, which is electrically connected to the light-emitting element and has a function of controlling the current flowing through the light-emitting element according to image data written to the pixel, varies from pixel to pixel, display unevenness or the like may occur. Therefore, a display device including a light-emitting element preferably has a function of reading the magnitude of a current flowing between the drain and source of the driving transistor as monitor current data. Display unevenness or the like can be reduced by correcting the threshold voltage or the like of the driving transistor based on the current value represented by the monitor current data. In one embodiment of the present invention, the monitor current data is read using the same circuit as a circuit having a function of reading imaging data. That is, the imaging data and the monitor current data are read using the same readout circuit. As described above, image data can be supplied to pixels, imaging data can be read, and the monitor current data can be read using the same IC chip. Therefore, the display device can be made more inexpensive than when image data is supplied to pixels, imaging data can be read, and the monitor current data can be read using different IC chips.

[0043] <Example of display device configuration> 1A is a schematic diagram illustrating a configuration example of a display device 10, which is a display device according to one embodiment of the present invention. The display device 10 includes a display unit 11, a gate driver circuit 13, a row driver circuit 19, an IC 20, and flexible printed circuits (FPCs) 25 on a substrate 18. The row driver circuit may also be referred to as a gate driver circuit. For example, in this specification, the gate driver circuit 13 may be referred to as a first gate driver circuit, and the row driver circuit 19 may be referred to as a second gate driver circuit.

[0044] Pixels 12 are arranged in a matrix on the display unit 11. The IC 20 can be mounted as an IC chip on the substrate 18. The IC 20 is electrically connected to a circuit provided outside the substrate 18 via an FPC 25.

[0045] The IC 20 may be mounted on the display device 10 by a packaging method such as a COF (Chip On Film) method or a TCP (Tape Carrier Package) method. Fig. 1B shows an example in which the IC 20 is mounted on an FPC 25. By mounting the IC 20 on the FPC 25, the area of ​​the substrate 18 can be reduced, and the display device 10 can be made smaller.

[0046] The gate driver circuit 13 or the row driver circuit 19 may be implemented as an IC. In this case, an FPC electrically connected to the gate driver circuit 13 or an FPC electrically connected to the row driver circuit 19 may be provided on the substrate 18. The gate driver circuit 13 or the row driver circuit 19 may also be provided on the display device 10 using a COF method, a TCP method, or the like.

[0047] 2A and 2B are schematic diagrams showing an example of the configuration of display device 10, which is a modified example of the configuration shown in Fig. 1A. Display device 10 having the configuration shown in Fig. 2A and 2B differs from display device 10 having the configuration shown in Fig. 1A in that it has a laminated structure of layer 140 and layer 150.

[0048] The layer 140 is provided with a substrate 18, and the layer 150 is provided with an insulating film 151 that functions as an interlayer insulating film. In the display device 10 configured as shown in FIG. 2A, the IC 20 and the FPC 25 are provided on the substrate 18, and the display unit 11, the gate driver circuit 13, and the row driver circuit 19 are provided on the insulating film 151. In the display device 10 configured as shown in FIG. 2B, the gate driver circuit 13, the row driver circuit 19, the IC 20, and the FPC 25 are provided on the substrate 18, and the display unit 11 is provided on the insulating film 151.

[0049] 2A or 2B, the display unit 11 can be provided so as to have an area overlapping with the IC 20. This allows the area of ​​the display unit 11 to be increased, making the display unit 10 a large-screen display device. In addition, the frame of the display unit 10 can be narrowed.

[0050] Furthermore, by configuring the display device 10 as shown in FIG. 2A or 2B, the area occupied by the IC 20 can be increased. This allows for a larger number of transistors and other components to be included in the IC 20. As will be described in detail later, the IC 20 has a function of controlling the driving of, for example, pixels 12 provided in the display unit 11. If the number of pixels 12 controlled by the IC 20 is large, the circuit configuration provided in the IC 20 becomes more complex, resulting in a larger number of transistors and other components being included in the IC 20. As described above, by configuring the display device 10 as shown in FIG. 2A or 2B, the number of pixels 12 controlled by the IC 20 can be increased. Therefore, the number of pixels 12 provided in the display unit 11 can be increased. This allows for a higher pixel density of the display device 10. Furthermore, the display device 10 can be used as a large-screen display device.

[0051] Fig. 3A is a schematic diagram showing an example configuration of a pixel 12. The pixel 12 configured as shown in Fig. 3A includes a pixel circuit 14R having a function of emitting red light 16R, a pixel circuit 14G having a function of emitting green light 16G, a pixel circuit 14B having a function of emitting blue light 16B, and a pixel circuit 15 having a function of detecting light 17. A light-emitting element is provided in each of the pixel circuits 14R, 14G, and 14B, and an image can be displayed on the display unit 11 using the pixel circuit 14. In addition, a light-receiving element is provided in the pixel circuit 15.

[0052] In this specification, for example, pixel circuit 14R, pixel circuit 14G, and pixel circuit 14B are collectively referred to as pixel circuit 14. Also, for example, light 16R, light 16G, and light 16B are collectively referred to as light 16.

[0053] 3B and 3C are schematic diagrams showing examples of the cross-sectional configuration of the display device 10. As shown in Fig. 3B and 3C, pixel circuits 14 and 15 are provided between substrates 18 and 121.

[0054] The display device 10 includes not only pixel circuits 14 each having a light-emitting element but also pixel circuits 15 each having a light-receiving element, allowing the display device 10 to function as an image sensor or a touch sensor. For example, the display device 10 can acquire image data by detecting light irradiated onto the light-receiving element. Furthermore, as shown in FIG. 3B , an object such as a finger touching the display device 10 can be detected. For example, when a finger 122 touching the display device 10 reflects light 16 emitted by a light-emitting element included in the pixel circuit 14, the light-receiving element included in the pixel circuit 15 detects the reflected light as light 17. This allows the display device 10 to detect that the finger 122 has touched the display device 10.

[0055] The display device 10 may have a function to detect an object that is close to the display device 10 but is not in contact with the display device 10. This allows the display device 10 to function as a near-touch sensor. Also, as shown in FIG. 3C , the display device 10 can detect the eyes 123 of the user of the display device 10. By detecting the eyes 123, the display device 10 can detect the facial expression, eye movement, pupil diameter, etc. of the user of the display device 10.

[0056] Furthermore, the display device 10 can acquire data such as fingerprints, palm prints, or irises. As described above, the display device 10 can be a display device having a function for biometric authentication. In this case, the light receiving element provided in the pixel circuit 15 can be said to function as a biometric authentication sensor, and the display device 10 can be said to have a built-in biometric authentication sensor. By having a built-in biometric authentication sensor in the display device 10, the number of components in an electronic device in which the display device 10 is provided can be reduced compared to when a biometric authentication sensor is provided separately from the display device 10. This allows the electronic device to be made smaller and lighter.

[0057] As described above, the display device 10 can acquire data such as facial expressions, eye movements, or changes in pupil diameter of the user of the display device 10 using light-emitting elements and light-receiving elements. By analyzing this data, it is possible to acquire mental and physical information about the user of the display device 10. By changing the output content of one or both of the display and audio based on this information, it becomes possible for the user of a device, for example, for VR (Virtual Reality), AR (Augmented Reality), or MR (Mixed Reality), to safely use the device.

[0058] As described above, in the display device 10, when light 16 emitted by the light-emitting element is reflected by an object, the light-receiving element can detect the reflected light as light 17. Therefore, imaging and the like can be performed even in dark places.

[0059] 3A shows an example of a configuration of the pixel 12 in which the pixel circuit 14R, the pixel circuit 14G, the pixel circuit 14B, and the pixel circuit 15 are arranged in a 2 × 2 matrix, but one embodiment of the present invention is not limited to this. As shown in FIG. 3D, the pixel circuit 14R, the pixel circuit 14G, the pixel circuit 14B, and the pixel circuit 15 may be arranged in a horizontal row.

[0060] 3E, pixel 12 may have pixel circuit 14W having a function of emitting white light, in addition to pixel circuit 14R, pixel circuit 14G, pixel circuit 14B, and pixel circuit 15. When pixel 12 has the configuration shown in FIG. 3E, pixel circuit 14R, pixel circuit 14G, pixel circuit 14B, and pixel circuit 14W can be collectively referred to as pixel circuit 14.

[0061] Furthermore, as shown in FIG. 3F , the pixel 12 may include a pixel circuit 14IR capable of emitting infrared light in addition to the pixel circuits 14R, 14G, 14B, and 15. In this case, the pixel circuit 15 preferably has a function of detecting infrared light. The pixel circuit 15 may also have a function of detecting both visible light and infrared light. By providing the pixel 12 with the pixel circuit 14IR capable of emitting infrared light and the pixel circuit 15 having a function of detecting infrared light, the display device 10 can detect an object such as a finger 122 or an eye 123 with high accuracy. Note that the pixel 12 may include both the pixel circuit 14W and the pixel circuit 14IR.

[0062] It can be said that the pixel circuit 14R, pixel circuit 14G, and pixel circuit 14B shown in FIGS. 3A, 3D to 3F, the pixel circuit 14W shown in FIG. 3E, and the pixel circuit 14IR shown in FIG. 3F are all pixel circuits 14.

[0063] Fig. 4 is a block diagram showing an example configuration of the display device 10. As shown in Fig. 4, the IC 20 is provided with an interface circuit 21, a control circuit 22, a memory circuit 26, a data driver circuit 23, and a readout circuit 24. The control circuit 22 also has a timing signal generation circuit 101 and a level shift circuit 102.

[0064] In Fig. 4, three pixel circuits 14 are provided per pixel 12. For example, if the pixel 12 has the configuration shown in Fig. 3A or 3D, the three pixel circuits 14 may be pixel circuit 14R, pixel circuit 14G, and pixel circuit 14B. Note that if the pixel 12 has the configuration shown in Fig. 3E or 3F, for example, it can be said that four pixel circuits 14 are provided per pixel 12.

[0065] In this specification, when the same reference numeral is used for multiple elements, particularly when it is necessary to distinguish between them, the reference numeral may be accompanied by an identifying symbol such as "[1]", "[m]", "[1,1]", or "[m,n]". For example, the pixel 12 in the first row and first column will be referred to as pixel 12[1,1], and the pixel 12 in the mth row and nth column will be referred to as pixel 12[m,n]. Furthermore, the pixel circuit 14 and pixel circuit 15 included in pixel 12[1,1] will be referred to as pixel circuit 14[1,1] and pixel circuit 15[1,1], respectively, and the pixel circuit 14 and pixel circuit 15 included in pixel 12[m,n] will be referred to as pixel circuit 14[m,n] and pixel circuit 15[m,n], respectively.

[0066] The gate driver circuit 13 is electrically connected to the pixel circuits 14 via wiring 31. The gate driver circuit 13 is also electrically connected to the pixel circuits 14 via wiring 36. The row driver circuit 19 is electrically connected to the pixel circuits 15 via wiring 32. The data driver circuit 23 is electrically connected to the pixel circuits 14 via wiring 33. The readout circuit 24 is electrically connected to the pixel circuits 14 via wiring 34 and is electrically connected to the pixel circuits 15 via wiring 35.

[0067] 4 illustrates a configuration in which pixels 12 in the same row are electrically connected to the same wiring 31, the same wiring 36, and the same wiring 32, and pixels 12 in the same column are electrically connected to the same wiring 33, the same wiring 34, and the same wiring 35. In this specification and the like, for example, the wirings 31, 36, and 32 electrically connected to the pixels 12 in the first row are respectively referred to as wiring 31[1], wiring 36[1], and wiring 32[1], and the wirings 31, 36, and 32 electrically connected to the pixels 12 in the mth row are respectively referred to as wiring 31[m], wiring 36[m], and wiring 32[m]. Furthermore, for example, wiring 33, wiring 34, and wiring 35 electrically connected to pixels 12 in the first column will be described as wiring 33[1], wiring 34[1], and wiring 35[1], respectively, and wiring 33, wiring 34, and wiring 35 electrically connected to pixels 12 in the nth column will be described as wiring 33[n], wiring 34[n], and wiring 35[n], respectively.

[0068] The gate driver circuit 13 has a function of selecting the pixels 12 to which image data is written. Specifically, the pixels 12 to which image data is written can be selected by outputting a signal to the wiring 31. Here, the gate driver circuit 13 outputs the signal in order from wiring 31[1] to wiring 31[m], thereby writing image data in order from the pixels 12 in the first row to the pixels 12 in the mth row. Therefore, the signal that the gate driver circuit 13 supplies to the pixels 12 via the wiring 31 can be said to be a scanning signal, and the wiring 31 can be said to be a scanning line.

[0069] One of the electrodes of the light-emitting element in the pixel circuit 14 is electrically connected to one of the source and drain of the drive transistor. The drive transistor has a function of controlling the current flowing through the light-emitting element according to image data written to the pixel 12. By controlling the current flowing through the light-emitting element, the light-emitting brightness of the light-emitting element can be controlled. Here, if the threshold voltage of the drive transistor varies from pixel circuit 14 to pixel circuit 14, display unevenness and the like may occur. The display device 10 has a function of reading out the magnitude of the current flowing between the drain and source of the drive transistor provided in the pixel circuit 14 as monitor current data. By correcting the threshold voltage of the drive transistor and the like based on the current value represented by the monitor current data, display unevenness and the like can be reduced. Therefore, high-quality images can be displayed on the display unit 11.

[0070] The gate driver circuit 13 has a function of selecting a pixel from which the monitor current data is to be read out. Specifically, by outputting a signal to the wiring 36, the pixel 12 from which the monitor current data is to be read out can be selected.

[0071] The row driver circuit 19 has a function of selecting the pixels 12 from which imaging data acquired by the pixel circuits 15 having light receiving elements is to be read. Specifically, the row driver circuit 19 can select the pixels 12 from which imaging data is to be read by outputting a signal to the wiring 32. Here, the row driver circuit 19 can read imaging data sequentially from the pixels 12 in the first row to the pixels 12 in the mth row by outputting the signal in order from the wiring 32[1] to the wiring 32[m]. Therefore, the signal that the row driver circuit 19 supplies to the pixels 12 via the wiring 32 can be said to be a scanning signal, and the wiring 32 can be said to be a scanning line.

[0072] As described above, the signal that the gate driver circuit 13 supplies to the pixel circuit 14 via the wiring 31 and the signal that the row driver circuit 19 supplies to the pixel circuit 15 via the wiring 32 can both be said to be scanning signals. Therefore, in this specification and the like, for example, the signal that the gate driver circuit 13 supplies to the pixel circuit 14 via the wiring 31 may be referred to as a first scanning signal, and the signal that the row driver circuit 19 supplies to the pixel circuit 15 via the wiring 32 may be referred to as a second scanning signal. Furthermore, the wiring 31 may be referred to as a first scanning line, and the wiring 32 may be referred to as a second scanning line.

[0073] The interface circuit 21 has a function of receiving a clock signal CLK1 and a digital image signal GS_D input from a circuit (not shown) electrically connected to the FPC 25. Here, the digital image signal GS_D is a digital signal representing image data to be written to the pixels 12. The interface circuit 21 also has a function of supplying the received clock signal CLK1 to a timing signal generation circuit 101 included in the control circuit 22, and supplying the received digital image signal GS_D to the memory circuit 26. Note that, for example, if the signal received by the interface circuit 21 is a serial signal, it can be converted into a parallel signal and supplied to the control circuit 22, memory circuit 26, etc.

[0074] The control circuit 22 has a function of generating a start pulse signal and a clock signal and supplying them to the gate driver circuit 13, the row driver circuit 19, the data driver circuit 23, the readout circuit 24, and the memory circuit 26. This allows the control circuit 22 to control the driving of the gate driver circuit 13, the row driver circuit 19, the data driver circuit 23, the readout circuit 24, and the memory circuit 26. Here, it is preferable to control the driving of the gate driver circuit 13, the row driver circuit 19, the data driver circuit 23, the readout circuit 24, and the memory circuit 26 by a single control circuit 22 provided in the IC 20, because this allows the driving of the above circuits to be related to each other by a simple control method.

[0075] The timing signal generation circuit 101 included in the control circuit 22 has a function of generating a start pulse signal SP_D and a clock signal CLK1_D and supplying them to the data driver circuit 23. The timing signal generation circuit 101 also has a function of generating a start pulse signal SP_R and a clock signal CLK1_R and supplying them to the read circuit 24. The timing signal generation circuit 101 also has a function of generating a start pulse signal SP_M and a clock signal CLK1_M and supplying them to the memory circuit 26. The timing signal generation circuit 101 also has a function of generating a start pulse signal GDSP and a clock signal GDCLK1, as well as a start pulse signal RDSP and a clock signal RDCLK1, and supplying them to the level shift circuit 102. The clock signal CLK1_D, the clock signal CLK1_R, the clock signal CLK1_M, the clock signal GDCLK1, and the clock signal RDCLK1 can be generated by, for example, dividing the frequency of the clock signal CLK1. Here, dividing the frequency of the clock signal CLK1 means changing the frequency of the clock signal CLK1 by 1 / N (N is an integer equal to or greater than 1) times.

[0076] The level shift circuit 102 included in the control circuit 22 has a function of generating a start pulse signal GDSP_LS by changing the potential level of the start pulse signal GDSP and supplying it to the gate driver circuit 13. The level shift circuit 102 also has a function of generating a clock signal GDCLK1_LS by changing the potential level of the clock signal GDCLK1 and supplying it to the gate driver circuit 13. The level shift circuit 102 also has a function of generating a start pulse signal RDSP_LS by changing the potential level of the start pulse signal RDSP and supplying it to the row driver circuit 19. The level shift circuit 102 also has a function of generating a clock signal RDCLK1_LS by changing the potential level of the clock signal RDCLK1 and supplying it to the row driver circuit 19.

[0077] The driving of the gate driver circuit 13 can be controlled by a start pulse signal GDSP_LS and a clock signal GDCLK1_LS. For example, when the start pulse signal GDSP_LS is input to the gate driver circuit 13, first scan signals are sequentially output to the wirings 31[1] to 31[m] in response to the rising or falling edges of the clock signal GDCLK1_LS. The driving of the row driver circuit 19 can be controlled by a start pulse signal RDSP_LS and a clock signal RDCLK1_LS. For example, when the start pulse signal RDSP_LS is input to the row driver circuit 19, second scan signals are sequentially output to the wirings 32[1] to 32[m] in response to the rising or falling edges of the clock signal RDCLK1_LS.

[0078] The memory circuit 26 has a function of temporarily storing the digital image signal GS_D and supplying it to the data driver circuit 23 at a predetermined timing. The timing at which the memory circuit 26 supplies the stored digital image signal GS_D to the data driver circuit 23 can be controlled by a start pulse signal SP_M and a clock signal CLK1_M. It can be said that the memory circuit 26 functions as a frame memory. The memory circuit 26 can be configured using storage elements such as DRAM (Dynamic Random Access Memory) or SRAM (Static Random Access Memory).

[0079] The data driver circuit 23 has a function of supplying image data represented by the digital image signal GS_D to the pixels 12 via the wiring 33. Specifically, the data driver circuit 23 has a function of supplying image data represented by the digital image signal GS_D to the pixels 12 selected by the gate driver circuit 13 outputting a first scanning signal to the wiring 31. Note that since the image data represented by the digital image signal GS_D is supplied to the pixels 12 via the wiring 33, the wiring 33 can be said to be a data line.

[0080] The driving of the data driver circuit 23 can be controlled by a start pulse signal SP_D and a clock signal CLK1_D. For example, when the start pulse signal SP_D is input to the data driver circuit 23, the digital image signal GS_D is sequentially output to the wirings 33[1] to 33[n] in response to the rising or falling edges of the clock signal CLK1_D.

[0081] The readout circuit 24 has a function of reading out monitor current data. Specifically, the readout circuit 24 has a function of reading out monitor current data of a pixel circuit 14 selected by the gate driver circuit 13 outputting a signal to the wiring 36. The readout circuit 24 also has a function of reading out imaging data. Specifically, the readout circuit 24 has a function of reading out imaging data written to a pixel 12 selected by the row driver circuit 19 outputting a second scanning signal to the wiring 32. Here, the readout circuit 24 has a function of outputting the read data as a data signal DS_OUT and supplying it to the interface circuit 21. Therefore, the data signal DS_OUT can be a signal representing monitor current data or a signal representing imaging data.

[0082] The drive of the readout circuit 24 can be controlled by a start pulse signal SP_R and a clock signal CLK1_R. For example, when the start pulse signal SP_R is input to the readout circuit 24, monitor current data input to the readout circuit 24 via wirings 34[1] to 34[n] is sequentially output as a data signal DS_OUT in response to the rising or falling edges of the clock signal CLK1_R. Alternatively, when the start pulse signal SP_R is input to the readout circuit 24, imaging data input to the readout circuit 24 via wirings 35[1] to 35[n] is sequentially output as a data signal DS_OUT in response to the rising or falling edges of the clock signal CLK1_R.

[0083] Since a monitor current flows through the wiring 34, the wiring 34 can be said to be a monitor line. Furthermore, since the imaging data written to the pixel circuit 15 is output to the wiring 35, the wiring 35 can be said to be a data line.

[0084] In this specification and the like, the data signal DS_OUT corresponding to the monitor current data may be referred to as a monitor signal or a first data signal, and the data signal DS_OUT corresponding to the imaging data may be referred to as an imaging signal or a second data signal.

[0085] As shown in FIG. 4 , in one embodiment of the present invention, both the data driver circuit 23 and the readout circuit 24 are provided in the IC 20. That is, the data driver circuit 23 and the readout circuit 24 are provided on the same IC chip. In addition, in one embodiment of the present invention, both the imaging data and the monitor current data are read out using the readout circuit 24. As described above, the supply of image data to the pixels 12, the reading of imaging data, and the reading of monitor current data can be performed using the same IC chip. Therefore, the display device 10 can be manufactured at a lower price than when the supply of image data to the pixels 12, the reading of imaging data, and the reading of monitor current data are performed using different IC chips.

[0086] <Example of a method for driving a gate driver circuit and a row driver circuit> 5 is a timing chart showing an example of a method for driving the gate driver circuit 13 and the row driver circuit 19. Specifically, FIG. 5 is a timing chart showing the change over time in the potential of a wiring 31 electrically connected to the gate driver circuit 13 and the potential of a wiring 32 electrically connected to the row driver circuit 19. In the timing chart shown in FIG. 5, a high potential is indicated by "H" and a low potential is indicated by "L". This is also true for other timing charts. For ease of explanation, the effects of various resistances such as wiring resistance, parasitic capacitance of transistors and wiring, and threshold voltages of transistors are not taken into consideration. This is also true for other timing charts.

[0087] Here, the potential of the wiring 31 to which the first scanning signal is output is set to a high potential. Also, the potential of the wiring 32 to which the second scanning signal is output is set to a high potential. Note that the potential of other wirings may also be set to a high potential when a signal is output to the wiring.

[0088] During the period T1[1], the gate driver circuit 13 sequentially outputs the first scanning signal to the wirings 31[1] to 31[3], for example. On the other hand, the row driver circuit 19 does not output the second scanning signal to the wiring 32.

[0089] During the period T2[1], the row driver circuit 19 sequentially outputs the second scanning signal to the wirings 32[1] to 32[3], for example. On the other hand, the gate driver circuit 13 does not output the first scanning signal to the wirings 31.

[0090] During the period T1[2], the gate driver circuit 13 sequentially outputs the first scanning signal to the wirings 31[4] to 31[6], for example. On the other hand, the row driver circuit 19 does not output the second scanning signal to the wiring 32.

[0091] During the period T2[2], the row driver circuit 19 sequentially outputs the second scanning signal to the wirings 32[4] to 32[6], for example. On the other hand, the gate driver circuit 13 does not output the first scanning signal to the wiring 31.

[0092] As described above, the output of the first scanning signal to the wiring 31 by the gate driver circuit 13 and the output of the second scanning signal to the wiring 32 by the row driver circuit 19 are alternately performed.

[0093] During the period T1[n / 3], the gate driver circuit 13 sequentially outputs the first scanning signal to the wirings 31[n-2] to 31[n], for example. On the other hand, the row driver circuit 19 does not output the second scanning signal to the wiring 32.

[0094] During the period T2[n / 3], the row driver circuit 19 sequentially outputs the second scanning signal to the wirings 32[n-2] to 32[n], for example. On the other hand, the gate driver circuit 13 does not output the first scanning signal to the wirings 31.

[0095] As described above, during period T1, the gate driver circuit 13 generates the first scan signal and outputs it to the wiring 31, but the row driver circuit 19 does not generate the second scan signal. Therefore, period T1 can be said to be a scan period for the gate driver circuit 13 and a pause period for the row driver circuit 19. On the other hand, during period T2, the row driver circuit 19 generates the second scan signal and outputs it to the wiring 32, but the gate driver circuit 13 does not generate the first scan signal. Therefore, period T2 can be said to be a pause period for the gate driver circuit 13 and a scan period for the row driver circuit 19.

[0096] As described above, in one embodiment of the present invention, when one of the gate driver circuit 13 and the row driver circuit 19 is in a scanning period, the other of the gate driver circuit 13 and the row driver circuit 19 is in a rest period. This makes it possible to prevent interference between driving of the pixel circuit 14 to which the gate driver circuit 13 supplies a first scan signal and driving of the pixel circuit 15 to which the row driver circuit 19 supplies a second scan signal. Therefore, noise included in the data output by the pixel circuit 14 and the data output by the pixel circuit 15 can be reduced. In particular, since noise included in the image data output by the pixel circuit 15 can be reduced, the display device 10 can detect an object such as a finger with high accuracy.

[0097] 5, the period T1 and the period T2 are repeated multiple times within one frame period. That is, for example, the first scan signal is not sequentially output to all of the wirings 31[1] to 31[m] in the period T1[1], and then the second scan signal is not sequentially output to all of the wirings 32[1] to 32[m] in the period T2[1]. By repeating the period T1 and the period T2 multiple times, flickering can be suppressed in an image displayed on the display unit 11 using the pixel circuit 14. Therefore, a high-quality image can be displayed on the display unit 11. Note that the period T1 and the period T2 may each be provided once within one frame period. That is, for example, the first scan signal may be sequentially output to all of the wirings 31[1] to 31[m] in the period T1[1], and then the second scan signal may be sequentially output to all of the wirings 32[1] to 32[m] in the period T2[1].

[0098] 5, a period that is a scan period for the gate driver circuit 13 is a pause period for the row driver circuit 19, and a period that is a pause period for the gate driver circuit 13 is a scan period for the row driver circuit 19. Therefore, the driving of the gate driver circuit 13 and the driving of the row driver circuit 19 are not independent but are related to each other. Therefore, it is preferable to control the driving of the gate driver circuit 13 and the driving of the row driver circuit 19 using the same circuit, as this simplifies the control of the driving of the gate driver circuit 13 and the row driver circuit 19. FIG. 4 shows a configuration in which the driving control of the gate driver circuit 13 and the driving control of the row driver circuit 19 are both performed using a control circuit 22.

[0099] 5 illustrates a case in which the gate driver circuit 13 outputs the first scan signal to three wirings 31 in the period T1, and then the row driver circuit 19 outputs the second scan signal to three wirings 32 in the period T2; however, one embodiment of the present invention is not limited to this. After the gate driver circuit 13 outputs the first scan signal to one or two wirings 31 in the period T1, the row driver circuit 19 may output the second scan signal to one or two wirings 32 in the period T2. Alternatively, after the gate driver circuit 13 outputs the first scan signal to four or more wirings 31 in the period T1, the row driver circuit 19 may output the second scan signal to four or more wirings 32 in the period T2.

[0100] <Data driver circuit configuration example> 6 is a block diagram showing a configuration example of the data driver circuit 23. The data driver circuit 23 has a shift register circuit 111, a latch circuit 112, a level shift circuit 113, a D / A (Digital to Analog) conversion circuit 114, and an amplifier circuit 115. Here, the latch circuits 112, the level shift circuits 113, the D / A conversion circuits 114, and the amplifier circuits 115 can be provided in numbers corresponding to the number of columns of pixels 12 provided in the display unit 11. For example, a configuration can be adopted in which n each of the latch circuits 112, the level shift circuits 113, the D / A conversion circuits 114, and the amplifier circuits 115 are provided.

[0101] A start pulse signal SP_D and a clock signal CLK1_D can be supplied to the shift register circuit 111. Furthermore, a digital image signal GS_D can be supplied to the latch circuit 112.

[0102] The shift register circuit 111 has a function of generating a signal for controlling the driving of the latch circuit 112. The latch circuit 112 has a function of holding or outputting the digital image signal GS_D. For example, when a start pulse signal SP_D is input to the shift register circuit 111, the held digital image signal GS_D can be sequentially output from the latch circuits 112[1] to 112[n] in response to the rising or falling edge of the clock signal CLK1_D.

[0103] The level shift circuit 113 has a function of changing the potential level of the digital image signal GS_D output from the latch circuit 112. The D / A conversion circuit 114 has a function of converting the digital image signal output from the level shift circuit 113 into an analog image signal. The amplifier circuit has a function of amplifying the analog image signal output from the D / A conversion circuit 114 and outputting it as an analog image signal GS_A to the wiring 33. By providing the amplifier circuit 115, image data represented by the analog image signal GS_A can be stably supplied to the pixel 12. A voltage follower circuit having an operational amplifier or the like can be used as the amplifier circuit 115. Note that when a circuit having a differential input circuit is used as the amplifier circuit, it is preferable that the offset potential of the differential input circuit be as close to 0 V as possible.

[0104] <Example of readout circuit configuration> 7 is a block diagram showing an example configuration of the readout circuit 24. The readout circuit 24 has a reference signal generation circuit 41, an A / D (Analog to Digital) conversion circuit 42, a shift register circuit 43, and a clock signal generation circuit 44. Here, the A / D conversion circuits 42 can be provided in numbers corresponding to the number of columns of pixels 12 provided in the display unit 11, for example. In other words, the readout circuit 24 can be provided with, for example, A / D conversion circuits 42[1] to 42[n].

[0105] The reference signal generation circuit 41 has a function of generating a reference signal REF and supplying it to the A / D conversion circuit 42. Here, the reference signal REF can be, for example, a ramp signal whose potential changes continuously. The A / D conversion circuit 42 has a function of converting an analog monitor signal MS_A representing monitor current data acquired by the pixel circuit 14 or an analog imaging signal IS_A representing imaging data acquired by the pixel circuit 15 into a digital signal and outputting it as a data signal DS_OUT.

[0106] The shift register circuit 43 has a function of generating a signal for controlling the driving of the A / D conversion circuit 42. For example, by inputting a start pulse signal SP_R to the shift register circuit 43, data signals DS_OUT can be sequentially output from the A / D conversion circuits 42[1] to 42[n] in response to the rising or falling edges of the clock signal CLK1_R.

[0107] The clock signal generation circuit 44 has a function of generating a clock signal CLK2 and supplying it to the A / D conversion circuit 42. Based on the reference signal REF and the clock signal CLK2, the A / D conversion circuit 42 can convert the analog monitor signal MS_A or the analog imaging signal IS_A into a digital signal and output it as a data signal DS_OUT.

[0108] <Pixel configuration example> Fig. 8 is a circuit diagram showing a configuration example of the pixel 12. Fig. 8 also shows the electrical connection relationship between the pixel 12 and the A / D conversion circuit 42. In the configuration example shown in Fig. 8, the pixel 12 includes a pixel circuit 14R, a pixel circuit 14G, a pixel circuit 14B, and a pixel circuit 15.

[0109] 8, all the transistors are n-channel transistors, but some or all of the transistors may be p-channel transistors by appropriately reversing the magnitude relationship of the potentials, etc. The same applies to circuit diagrams other than FIG.

[0110] Each of the pixel circuits 14 (pixel circuits 14R, 14G, and 14B in FIG. 8) includes a light-emitting element 60, a transistor 61, a transistor 62, a transistor 63, and a capacitor 64.

[0111] It is preferable to use an EL element such as an OLED (Organic Light Emitting Diode) or a QLED (Quantum-dot Light Emitting Diode) as the light-emitting element 60. Examples of light-emitting materials that the EL element has include a material that emits fluorescence (fluorescent material), a material that emits phosphorescence (phosphorescent material), an inorganic compound (quantum dot material, etc.), and a material that exhibits thermally activated delayed fluorescence (thermally activated delayed fluorescence (TADF) material). Also, an LED such as a micro LED (Light Emitting Diode) can be used as the light-emitting element.

[0112] Here, when a color filter system is applied to the display device 10, the light-emitting element 60 of the pixel circuit 14R, the light-emitting element 60 of the pixel circuit 14G, and the light-emitting element 60 of the pixel circuit 14B can all be light-emitting elements that emit white light. On the other hand, when a color-coded system is applied to the display device 10, the light-emitting element 60 of the pixel circuit 14R can be a light-emitting element that emits red light, the light-emitting element 60 of the pixel circuit 14G can be a light-emitting element that emits green light, and the light-emitting element 60 of the pixel circuit 14B can be a light-emitting element that emits blue light.

[0113] One electrode of the light-emitting element 60 is electrically connected to one of the source and drain of the transistor 62. One of the source and drain of the transistor 62 is electrically connected to one of the source and drain of the transistor 63. One of the source and drain of the transistor 63 is electrically connected to one electrode of the capacitor 64. One of the source and drain of the transistor 61 is electrically connected to the gate of the transistor 62. The gate of the transistor 62 is electrically connected to the other electrode of the capacitor 64.

[0114] The other electrode of the light-emitting element 60 is electrically connected to a wiring 65. The gate of the transistor 61 is electrically connected to a wiring 31. The other of the source and the drain of the transistor 61 is electrically connected to a wiring 33. The other of the source and the drain of the transistor 62 is electrically connected to a wiring 37. The gate of the transistor 63 is electrically connected to a wiring 36. The other of the source and the drain of the transistor 63 is electrically connected to a wiring 34. The wiring 34 is electrically connected to the A / D conversion circuit 42.

[0115] As described above, the wiring 31 functions as a scan line, the wiring 33 functions as a data line, and the wiring 34 functions as a monitor line. The wiring 37 and the wiring 65 function as power supply lines. For example, when one of the source and drain of the transistor 62 is electrically connected to the anode of the light-emitting element 60, the wiring 37 can be set to a high potential and the wiring 65 can be set to a low potential.

[0116] When the gate driver circuit 13 outputs a first scan signal to the wiring 31, the wiring 31 to which the first scan signal is output becomes high potential. Therefore, the transistor 61 electrically connected to the wiring 31 becomes conductive, and the image data output to the wiring 33 by the data driver circuit 23 is written to the pixel circuit 14. Specifically, the potential of the gate of the transistor 62 becomes a potential corresponding to the image data. As a result, a current having a magnitude corresponding to the potential of the gate of the transistor 62 flows between the drain and source of the transistor 62 and through the light-emitting element 60. Therefore, the light-emitting element 60 emits light at a luminance corresponding to the potential of the gate of the transistor 62, and an image can be displayed on the display unit 11.

[0117] From the above, it can be said that the transistor 62 has a function of controlling the current flowing through the light-emitting element 60 in accordance with image data written to the pixel circuit 14. Therefore, it can be said that the transistor 62 has a function of controlling the driving of the light-emitting element 60. Therefore, it can be said that the transistor 62 is a driving transistor.

[0118] Here, if the threshold voltage of the transistor 62 varies from pixel circuit 14 to pixel circuit 14, display unevenness may occur. Therefore, display unevenness can be reduced by correcting the threshold voltage of the transistor 62. The threshold voltage of the transistor 62 can be calculated by measuring the current flowing between the drain and source of the transistor 62. In the pixel circuit 14 configured as shown in FIG. 8, by turning on the transistor 63, an analog monitor signal MS_A representing the current flowing between the drain and source of the transistor 62 is output to the A / D conversion circuit 42 via the wiring 34.

[0119] The pixel circuit 15 includes a light-receiving element 70, a transistor 71, a transistor 72, a transistor 73, a transistor 74, and a capacitor 75. Note that if the gate capacitance of the transistor 73 is sufficiently large, the capacitor 75 is not necessarily provided.

[0120] The light receiving element can be, for example, a pn-type or pin-type photodiode. The light receiving element functions as a photoelectric conversion element that detects irradiated light and generates electric charge. The amount of electric charge generated is determined based on the amount of light irradiated onto the light receiving element.

[0121] In particular, it is preferable to use an organic photodiode having a layer containing an organic compound as the light-receiving element. Organic photodiodes can be easily made thin, lightweight, and large in area, and have a high degree of freedom in shape and design, making them applicable to a variety of display devices.

[0122] In one embodiment of the present invention, for example, an organic EL element is used as the light-emitting element, and an organic photodiode is used as the light-receiving element. Many layers of an organic photodiode can be configured in common with those of an organic EL element. Therefore, a light-receiving element can be incorporated into the display device 10 without significantly increasing the number of manufacturing steps. For example, an active layer of the light-receiving element and a light-emitting layer of the light-emitting element can be separately formed, and the other layers can be configured identically for the light-emitting element and the light-receiving element.

[0123] One electrode of the light-receiving element 70 is electrically connected to one of the source and the drain of the transistor 71. The other of the source and the drain of the transistor 71 is electrically connected to one of the source and the drain of the transistor 72. The one of the source and the drain of the transistor 72 is electrically connected to the gate of the transistor 73. The gate of the transistor 73 is electrically connected to one electrode of the capacitor 75. The one of the source and the drain of the transistor 73 is electrically connected to one of the source and the drain of the transistor 74. The other of the source and the drain of the transistor 74 is electrically connected to the wiring 35. The gate of the transistor 74 is electrically connected to the wiring 32.

[0124] The wiring 35 is electrically connected to the A / D conversion circuit 42 and the current source 131. The current source 131 may be, for example, a transistor that operates in a saturation region. When a transistor is used as the current source 131, the transistor can be said to be a bias transistor, and the potential of the gate of the transistor can be said to be a bias potential.

[0125] When the transistor 71 is turned on, the potential of the gate of the transistor 73 becomes a potential corresponding to the illuminance of light irradiating the light receiving element 70. This allows the pixel circuit 15 to acquire imaging data. Thereafter, when the row driver circuit 19 outputs a second scanning signal to the wiring 32, the wiring 32 to which the second scanning signal is output becomes high potential. Therefore, the transistor 74 electrically connected to the wiring 32 becomes conductive, and the potential of the wiring 35 becomes a potential corresponding to the potential of the gate of the transistor 73. As a result, the imaging data acquired by the pixel circuit 15 is supplied as an analog imaging signal IS_A to the A / D conversion circuit 42 via the wiring 35.

[0126] In the pixel 12 having the configuration shown in Fig. 8, the pixel circuit 14R, the pixel circuit 14G, the pixel circuit 14B, and the pixel circuit 15 are arranged in one column, but this is not a limitation of one embodiment of the present invention. For example, they may be arranged in two rows and two columns. Fig. 9 shows an example configuration of the pixel 12 in which the pixel circuit 14R is arranged in the first row and the first column, the pixel circuit 14G is arranged in the first row and the second column, the pixel circuit 14B is arranged in the second row and the first column, and the pixel circuit 15 is arranged in the second row and the second column.

[0127] Fig. 10 is a modification of the configuration shown in Fig. 8, and differs from the configuration shown in Fig. 8 in that a CDS circuit 80 is provided. The CDS circuit 80 includes a capacitive element 76, a transistor 77, a transistor 78, and a transistor 79.

[0128] One electrode of the capacitor 76 is electrically connected to the wiring 35. The other electrode of the capacitor 76 is electrically connected to one of the source and the drain of the transistor 77. The one of the source and the drain of the transistor 77 is electrically connected to the gate of the transistor 78. The one of the source and the drain of the transistor 78 is electrically connected to one of the source and the drain of the transistor 79. The one of the source and the drain of the transistor 79 is electrically connected to the wiring 38. The wiring 38 is electrically connected to the A / D conversion circuit 42.

[0129] By providing a CDS circuit 80 between the pixel circuit 15 and the A / D conversion circuit 42, it is possible to perform correlated double sampling (CDS) on the imaging data acquired by the pixel circuit 15. Here, correlated double sampling on the imaging data acquired by the pixel circuit 15 refers to taking the difference between the potential of the wiring 35 when the imaging data written in the pixel circuit 15 is read out and the potential of the wiring 35 when the imaging data written in the pixel circuit 15 is reset. By performing correlated double sampling, the analog imaging signal IS_A supplied to the A / D conversion circuit 42 can be a signal with reduced noise.

[0130] 11A shows an example of the configuration of the pixel circuit 14, which is a modified example of the configuration of the pixel circuit 14 shown in FIGS. 8 to 10. The pixel circuit 14 shown in FIG. 11A includes a light-emitting element 60, a transistor 61a, a transistor 61b, a transistor 62, a transistor 63, a transistor 66, a capacitor 64, and a capacitor 67. The pixel circuit 14 shown in FIG. 11A is electrically connected to the wiring 31a and the wiring 31b as the wiring 31.

[0131] One electrode of the light-emitting element 60 is electrically connected to one of the source or drain of a transistor 62. One of the source or drain of the transistor 62 is electrically connected to one of the source or drain of a transistor 63. The gate of the transistor 62 is electrically connected to one of the source or drain of a transistor 61a. One of the source or drain of the transistor 61a is electrically connected to one electrode of a capacitor 64. The other electrode of the capacitor 64 is electrically connected to one of the source or drain of a transistor 61b. One of the source or drain of the transistor 61b is electrically connected to one of the source or drain of a transistor 66. One of the source or drain of the transistor 66 is electrically connected to one electrode of a capacitor 67.

[0132] The other electrode of the light-emitting element 60 is electrically connected to a wiring 65. The gate of the transistor 61a and the gate of the transistor 66 are electrically connected to a wiring 31a. The gate of the transistor 61b is electrically connected to a wiring 31b. The other of the source or the drain of the transistor 61a and the other of the source or the drain of the transistor 61b are electrically connected to a wiring 33. The other of the source or the drain of the transistor 62 and the other electrode of the capacitor 67 are electrically connected to a wiring 37. The gate of the transistor 63 is electrically connected to a wiring 36. The other of the source or the drain of the transistor 63 is electrically connected to a wiring 34. The other of the source or the drain of the transistor 66 is electrically connected to a wiring 68.

[0133] Here, a node FD11 is a node where one of the source or drain of the transistor 61a, the gate of the transistor 62, and one electrode of the capacitor 64 are electrically connected. A node FD12 is a node where one of the source or drain of the transistor 61b, the other electrode of the capacitor 64, one of the source or drain of the transistor 66, and one electrode of the capacitor 67 are electrically connected.

[0134] The wiring 68 functions as a power supply line. The potential of the wiring 68 is set to a potential V0.

[0135] 11A, the potential of the node FD11 can be maintained by turning off the transistor 61a. Furthermore, the potential of the node FD12 can be maintained by turning off the transistors 61b and 66. Furthermore, by turning off the transistor 61a and changing the potential of the node FD12, the potential of the node FD11 can be changed by capacitive coupling via the capacitor 64.

[0136] Here, it is preferable to use a transistor with low off-state current as the transistor 61a because the potential of the node FD11 can be held for a long period of time. It is also preferable to use transistors with low off-state current as the transistors 61b and 66 because the potential of the node FD12 can be held for a long period of time. An example of a transistor with low off-state current is a transistor using a metal oxide in a channel formation region (hereinafter referred to as an OS transistor).

[0137] The OS transistor preferably includes a metal oxide in a channel formation region, and the metal oxide used in the OS transistor preferably contains at least one of indium (In) and zinc (Zn).

[0138] Examples of such oxides include In-M-Zn oxide, In-M oxide, Zn-M oxide, and In-Zn oxide (wherein element M is, for example, one or more selected from aluminum (Al), gallium (Ga), yttrium (Y), tin (Sn), boron (B), silicon (Si), titanium (Ti), iron (Fe), nickel (Ni), germanium (Ge), zirconium (Zr), molybdenum (Mo), lanthanum (La), cerium (Ce), neodymium (Nd), vanadium (V), beryllium (Be), hafnium (Hf), tantalum (Ta), and tungsten (W)). Representative examples of In-M-Zn oxide include In-Ga-Zn oxide, In-Sn-Zn oxide, and In-Ga-Sn-Zn oxide.

[0139] The OS transistor has an off-state current of 1 yA / μm per 1 μm of channel width (y: yocto, 10 -24 ) or more than 1zA / μm (z: Zepto, 10 -21 ) or less.

[0140] It is preferable to use a cloud-aligned composite (CAC)-OS transistor as the OS transistor, the details of which will be described in a later embodiment.

[0141] In addition to the transistors 61a, 61b, and 66, OS transistors may be used as the transistors 62 and 63. That is, OS transistors may be used as all the transistors included in the pixel circuit 14. This allows all the transistors included in the pixel circuit 14 to be formed in the same process. Furthermore, in addition to the transistors 61a, 61b, 62, 63, and 66, OS transistors may be used as the transistors 71 to 74 included in the pixel circuit 15. That is, OS transistors may be used not only for the transistors included in the pixel circuit 14 but also for the transistors included in the pixel circuit 15.

[0142] Transistors using silicon in a channel formation region (hereinafter referred to as Si transistors) or the like may be used as the transistors 61a, 61b, and 66. Si transistors may be used as the transistors 62 and 63. Si transistors may be used as the transistors 71 to 74 included in the pixel circuit 15. Examples of silicon include amorphous silicon, crystalline silicon (low-temperature polysilicon, single-crystal silicon, etc.), and the like.

[0143] If all the transistors included in the pixel 12 are the same type of transistors, all the transistors included in the pixel 12 can be formed in the same process, which reduces the number of manufacturing steps for the display device 10, thereby making it possible to reduce the cost of the display device 10.

[0144] The transistors 61a, 61b, and 66 may be transistors other than OS transistors that have low off-state current. For example, transistors using a semiconductor with a wide band gap may be used. A wide band gap semiconductor may refer to a semiconductor with a band gap of 2.2 eV or more. Examples of such semiconductors include silicon carbide, gallium nitride, and diamond.

[0145] 11B is a timing chart showing an example of a method for driving the pixel circuit 14 having the configuration shown in FIG. 11A. In the driving method shown in FIG. 11B, one frame period is divided into periods T101, T102, and T103. In period T101, a potential VDa corresponding to data Da is supplied to node FD11, and in period T103, a potential VDb corresponding to data Db is supplied to node FD12. Note that, in periods T101 to T103, the potential of the wiring 36 is set to a low potential, and the transistor 63 is set to a non-conductive state. This prevents current flowing between the drain and source of the transistor 62, which is a driving transistor, from flowing to the wiring 34 via the transistor 63, thereby allowing the current flowing between the drain and source of the transistor 62 to flow efficiently to the light-emitting element 60.

[0146] In period T101, the potential of the wiring 31a is set to a high potential, thereby turning on the transistors 61a and 66. Furthermore, data Da is supplied to the pixel circuit 14 through the wiring 33. By turning on the transistor 66, the potential of the node FD12 becomes the potential V0. This allows the potential of the node FD12 to be reset. Furthermore, by turning on the transistor 61a and supplying the data Da to the pixel circuit 14, the potential of the node FD11 becomes the potential VDa. In this way, the data Da is written to the pixel circuit 14.

[0147] In the period T102, the potential of the wiring 31a is set to low to turn off the transistor 61a and the transistor 66. As a result, the supply of the potential VDa to the node FD11 and the supply of the potential V0 to the node FD12 are stopped.

[0148] In period T103, the potential of the wiring 31b is set to high, thereby turning on the transistor 61b. Furthermore, data Db is supplied to the pixel circuit 14 via the wiring 33. As a result, the potential of the node FD12 becomes the potential VDb. Therefore, the potential of the node FD12 changes by the potential "VDb-V0". As a result, the data Db is written to the pixel circuit 14.

[0149] Here, due to the capacitive coupling of the capacitive element 64, the potential of the node FD11 changes in response to a change in the potential of the node FD12. Specifically, if the capacitive coupling coefficient of the node FD11 is c (c is a real number between 0 and 1), the potential of the node FD11 changes by a potential "c(VDb-V0)". Here, the potential of the node FD11 in the period T102 is the potential VDa. Therefore, in the period T103, the potential of the node FD11 becomes a potential "VDa+c(VDb-V0)". Note that although FIG. 11B shows the potential VDb as being higher than the potential V0, the potential VDb may be lower than the potential V0.

[0150] The capacitive coupling coefficient c is roughly determined by the capacitance value of the capacitive element 64 and the capacitance value of the parasitic capacitance of the node FD11, such as the gate capacitance of the transistor 62. If the capacitance value of the capacitive element 64 is larger than the parasitic capacitance of the node FD11, the value of c becomes larger and approaches 1, and therefore the potential of the node FD11 in the period T103 becomes close to the potential "VDa+VDb-V0."

[0151] As described above, the pixel circuit 14 configured as shown in FIG. 11A can combine two types of data. This allows the image displayed on the display unit 11 using the pixel circuit 14 to be corrected within the pixel circuit 14. For example, one of the data Da and the data Db can be image data, and the other of the data Da and the data Db can be correction data. For example, the data Da can be correction data and the data Db can be image data. By using the data Da as correction data and the data Db as image data and employing a transistor with a low off-state current, such as an OS transistor, as the transistor 61a, the correction data can be retained in the pixel circuit 14 for a long period of time. This eliminates the need to write correction data to the pixel circuit 14 for each frame, thereby reducing the frequency with which correction data is written to the pixel circuit 14. This reduces the power consumption of the display device 10.

[0152] Alternatively, both the data Da and the data Db may be image data. This allows an image obtained by superimposing two images to be displayed on the display unit 11. The magnitude of the potential VDa corresponding to the data Da and the magnitude of the potential VDb corresponding to the data Db are limited by the withstand voltage of the data driver circuit 23, etc. Therefore, by superimposing the data Da and the data Db, the potential of the node FD11 can be made higher than the maximum potential that the data driver circuit 23 can output. For example, if the capacitive coupling coefficient c of the node FD11 is 1, the maximum value of the potential of the node FD11 can be made twice the maximum potential that the data driver circuit 23 can output. Therefore, a potential higher than the maximum potential that the data driver circuit 23 can output can be applied to the gate of the transistor 62, which is the driving transistor, allowing a large current to flow through the light-emitting element 60. This increases the luminance of the light-emitting element 60, allowing a high-luminance image to be displayed on the display unit 11. Furthermore, the dynamic range, which is the difference between the maximum and minimum luminance of the light-emitting element 60, can be expanded when an image is displayed on the display unit 11. Note that the image corresponding to data Da and the image corresponding to data Db may be the same or different. Furthermore, as described above, when a transistor with a low off-state current, such as an OS transistor, is used as transistor 61a, it is not necessary to write data Da to pixel circuit 14 for each frame, and the frequency at which data Da is written to pixel circuit 14 can be reduced compared to the frequency at which data Db is written.

[0153] 3A to 3C can be increased by increasing the light emission brightness of the light emitting element 60. This increases the brightness of the light 17, which is reflected by an object such as a finger 122 or an eye 123 and is irradiated onto the pixel circuit 15. This increases the object detection sensitivity of the pixel circuit 15.

[0154] ​Fig. 12A is a circuit diagram showing an example of the configuration of the A / D conversion circuit 42. Note that Fig. 12A also shows the electrical connection relationship between the pixel circuits 14 and 15 and the A / D conversion circuit 42.

[0155] The A / D conversion circuit 42 includes a transistor 51a, a transistor 51b, a capacitor 52, a comparator circuit 53, and a counter circuit 54. Note that the capacitor 52 is not necessarily provided.

[0156] One of the source and drain of the transistor 51a is electrically connected to the pixel circuit 14 through a wiring 34. The gate of the transistor 51a is electrically connected to a wiring 55a. One of the source and drain of the transistor 51b is electrically connected to the pixel circuit 15 through a wiring 35. The gate of the transistor 51b is electrically connected to a wiring 55b. When a CDS circuit 80 is provided as shown in FIG. 10 , one of the source and drain of the transistor 51b is electrically connected to the CDS circuit 80 through a wiring 38.

[0157] The other of the source and the drain of the transistor 51a is electrically connected to the other of the source and the drain of the transistor 51b. The other of the source and the drain of the transistor 51b is electrically connected to one electrode of the capacitor 52. The other electrode of the capacitor 52 is electrically connected to a wiring 59. The one electrode of the capacitor 52 is electrically connected to a first input terminal of the comparison circuit 53. A second input terminal of the comparison circuit 53 is electrically connected to the reference signal generation circuit 41. An output terminal of the comparison circuit 53 is electrically connected to a counter circuit 54.

[0158] In this specification and the like, a first input terminal of a comparison circuit refers to either the non-inverting input terminal or the inverting input terminal of the comparison circuit, and a second input terminal of the comparison circuit refers to the other of the non-inverting input terminal or the inverting input terminal of the comparison circuit. In the following description, the first input terminal of the comparison circuit 53 is the non-inverting input terminal, and the second input terminal of the comparison circuit 53 is the inverting input terminal. However, by appropriately reversing the magnitude relationship of the potentials, the first input terminal may be the inverting input terminal, and the second input terminal may be the non-inverting input terminal.

[0159] The wiring 59 functions as a power supply line. The potential of the wiring 59 can be, for example, a low potential.

[0160] The transistors 51a and 51b function as switches that select a signal to be A / D converted. For example, when the potential of the wiring 55a is high and the potential of the wiring 55b is low, the transistor 51a is conductive and the transistor 51b is non-conductive. In this case, the A / D conversion circuit 42 performs A / D conversion on the analog monitor signal MS_A output from the pixel circuit 14 to the wiring 34, and can output the resulting digital signal as the data signal DS_OUT. On the other hand, when the potential of the wiring 55a is low and the potential of the wiring 55b is high, the transistor 51a is non-conductive and the transistor 51b is conductive. In this case, the A / D conversion circuit 42 performs A / D conversion on the analog image signal IS_A output from the pixel circuit 15 to the wiring 35, and can output the resulting digital signal as the data signal DS_OUT.

[0161] By providing transistors 51a and 51b, the analog monitor signal MS_A output from pixel circuit 14 and the analog imaging signal IS_A output from pixel circuit 15 can be converted into digital signals using the same A / D conversion circuit.

[0162] The comparator circuit 53 has a function of comparing the potential of the non-inverting input terminal with the potential of the inverting input terminal and outputting a comparison signal CMP from the output terminal. Specifically, when the potential of the non-inverting input terminal is higher than the potential of the inverting input terminal, the potential of the comparison signal CMP is high. On the other hand, when the potential of the non-inverting input terminal is lower than the potential of the inverting input terminal, the potential of the comparison signal CMP is low.

[0163] The counter circuit 54 has a function of outputting a digital data signal DS_OUT based on the comparison signal CMP, the signal supplied from the shift register circuit 43, and the clock signal CLK2. For example, the counter circuit 54 has a function of counting the number of rising edges of the clock signal CLK2 when the comparison signal CMP is at a low potential, and stopping the counting when the comparison signal CMP is at a high potential. The counter circuit 54 may also have a function of counting the number of falling edges of the clock signal CLK2. The counter circuit 54 may also have a function of counting both the number of rising edges and the number of falling edges of the clock signal CLK2. The counter circuit 54 may also have a function of counting the number of rising edges or the number of falling edges of the clock signal CLK2 when the comparison signal CMP is at a high potential, and stopping the counting when the comparison signal CMP is at a low potential.

[0164] 12A, the transistors 51a and 51b are provided in the A / D conversion circuit 42, but as shown in FIG. 12B, the transistors 51a and 51b may be provided outside the A / D conversion circuit 42. For example, the transistors 51a and 51b may be provided outside the IC 20.

[0165] FIG. 13 is a timing chart showing an example of a method for driving the A / D conversion circuit 42 configured as shown in FIG. 12A or 12B.

[0166] ​During the period T, the potential of the reference signal REF is higher than the potential of the analog monitor signal MS_A or the potential of the analog imaging signal IS_A, so the potential of the comparison signal CMP becomes low.

[0167] During a period T, the counter circuit 54 counts the number of rising edges of the clock signal CLK2. Specifically, the counter circuit 54 outputs a data signal DS_OUT having a digital value corresponding to the number of rising edges of the clock signal CLK2. In Fig. 13, the data signal DS_OUT is shown as (the number of rising edges of the clock signal CLK during the period T - 1).

[0168] During the period T, the potential of the reference signal REF is continuously decreased. When the potential of the reference signal REF becomes equal to or lower than the potential of the analog monitor signal MS_A or the potential of the analog imaging signal IS_A, the potential of the comparison signal CMP becomes high. When the potential of the comparison signal CMP becomes high, the period T ends.

[0169] After the period T ends, the counter circuit 54 does not count the number of rising edges of the clock signal CLK2. Therefore, after the period T ends, the counter circuit 54 continues to output the data signal DS_OUT having a digital value corresponding to the number of rising edges of the clock signal CLK2 from the start to the end of the period T.

[0170] Using the above method, the A / D conversion circuit 42 can convert the analog monitor signal MS_A or the analog imaging signal IS_A into a digital signal. Specifically, the A / D conversion circuit 42 can output a data signal DS_OUT having a digital value corresponding to the potential of the analog monitor signal MS_A or the potential of the analog imaging signal IS_A. When the analog monitor signal MS_A is A / D converted, the potential of the analog monitor signal MS_A represented by the data signal DS_OUT can be converted into a current to calculate the value of the monitor current. The calculation of the value of the monitor current can be performed, for example, by a circuit provided in the IC 20. For example, the calculation of the value of the monitor current can be performed by the interface circuit 21.

[0171] 14A is a circuit diagram showing an example of the configuration of the A / D conversion circuit 42, which is different from that of FIG. 12A. The A / D conversion circuit 42 shown in FIG. 14A includes a transistor 51a, a transistor 51b, a transistor 81, a transistor 82a, a transistor 82b, a transistor 83a, a transistor 83b, a transistor 85, a transistor 86, a capacitor 52, a capacitor 84a, a capacitor 84b, a comparator circuit 53, and a counter circuit 54. Note that the capacitor 52 is not necessarily provided.

[0172] One of the source and the drain of the transistor 51a is electrically connected to the pixel circuit 14 through a wiring 34. One of the source and the drain of the transistor 51b is electrically connected to the pixel circuit 15 through a wiring 35. When a CDS circuit 80 is provided as shown in FIG. 10, one of the source and the drain of the transistor 51b is electrically connected to the CDS circuit 80 through a wiring 38.

[0173] ​The other of the source and the drain of the transistor 51a is electrically connected to the other of the source and the drain of the transistor 51b. The other of the source and the drain of the transistor 51b is electrically connected to one electrode of the capacitor 52. One electrode of the capacitor 52 is electrically connected to one of the source and the drain of the transistor 81. The one of the source and the drain of the transistor 81 is electrically connected to one of the source and the drain of the transistor 82a. The other of the source and the drain of the transistor 82a is electrically connected to one of the source and the drain of the transistor 83a. The one of the source and the drain of the transistor 83a is electrically connected to one electrode of the capacitor 84a. The other electrode of the capacitor 84a, the one of the source and the drain of the transistor 85, and the first input terminal of the comparison circuit 53 are electrically connected to a wiring 56.

[0174] One of the source and the drain of the transistor 82b is electrically connected to the reference signal generation circuit 41. The other of the source and the drain of the transistor 82b is electrically connected to one of the source and the drain of the transistor 83b. The one of the source and the drain of the transistor 83b is electrically connected to one electrode of the capacitor 84b. The other electrode of the capacitor 84b, the second input terminal of the comparison circuit 53, and one of the source and the drain of the transistor 86 are electrically connected to a wiring 57. The output terminal of the comparison circuit 53 is electrically connected to the counter circuit 54 and the other of the source and the drain of the transistor 86.

[0175] The gate of the transistor 51a is electrically connected to a wiring 55a. The gate of the transistor 51b is electrically connected to a wiring 55b. The other electrode of the capacitor 52 is electrically connected to a wiring 59. The gate of the transistor 81 is electrically connected to a wiring 91. The other of the source and the drain of the transistor 81 is electrically connected to a wiring 92. The gates of the transistors 82a and 82b are electrically connected to a wiring 93. The gates of the transistors 83a and 83b are electrically connected to a wiring 94. The other of the source and the drain of the transistor 83a and the other of the source and the drain of the transistor 83b are electrically connected to a wiring 95. The gates of the transistors 85 and 86 are electrically connected to a wiring 96. The other of the source and the drain of the transistor 85 is electrically connected to a wiring 97. In addition to the wiring 59, the wirings 92, 95, and 97 also function as power supply lines.

[0176] The node to which the pixel circuit 14 and one of the source and drain of the transistor 51a are electrically connected is referred to as a node FD1, where the parasitic capacitance of the node FD1 is referred to as a parasitic capacitance PC.

[0177] A node where the other of the source and drain of the transistor 82a, one of the source and drain of the transistor 83a, and one electrode of the capacitor 84a are electrically connected is referred to as node FD2a. A node where the other of the source and drain of the transistor 82b, one of the source and drain of the transistor 83b, and one electrode of the capacitor 84b are electrically connected is referred to as node FD2b. A node where the reference signal generation circuit 41 and one of the source and drain of the transistor 82b are electrically connected is referred to as node FD3.

[0178] By configuring the A / D conversion circuit 42 as shown in FIG. 14A, the monitor current I can be calculated by the following formula, where C FD1 indicates the capacitance value of the node FD1 when the transistor 51a is in a conductive state, and ΔVFD1 / Δt represents the change in the potential of the node FD1 over time. In the configuration shown in FIG. 14A, the capacitance value C FD1 can be the sum of the capacitance value of the parasitic capacitance PC and the capacitance value of the capacitive element 52. As described above, the value of the monitor current can be calculated by, for example, a circuit provided in the IC 20. For example, the value of the monitor current can be calculated by the interface circuit 21.

[0179]

number

[0180] If the capacitance value of the parasitic capacitance PC is small, the capacitance value C FD1 becomes smaller, and ΔV FD1 In other words, the potential of the node FD1 changes significantly in a short time. This may make it impossible to calculate the monitor current I with high accuracy. In this case, by increasing the capacitance of the capacitive element 52, the capacitance C of the node FD1 when the transistor 51a is in a conductive state can be reduced. FD1 By increasing the value of the saturation voltage, the monitor current I can be calculated with high accuracy.

[0181] 14A, the value of the monitor current can be calculated taking into account the parasitic capacitance PC of the wiring 34, etc. Therefore, the value of the monitor current can be calculated with high accuracy, and therefore, for example, the threshold voltage of the transistor 62 that functions as the drive transistor of the pixel circuit 14 can be corrected with high accuracy. Therefore, for example, display unevenness can be reduced, and a high-quality image can be displayed on the display unit 11.

[0182] 14A, the transistors 51a and 51b are provided in the A / D conversion circuit 42, but as shown in FIG. 14B, the transistors 51a and 51b may be provided outside the A / D conversion circuit 42. For example, the transistors 51a and 51b may be provided outside the IC 20.

[0183] An example of a method for driving the A / D conversion circuit 42 will be described below.

[0184] [Capacitance value C FD1 Example of calculation method] FIG. 15 shows the capacitance C of the node FD1 when the transistor 51a is in a conductive state in the case where the A / D conversion circuit 42 has the configuration shown in FIG. 14A or FIG. 14B. FD1 10 is a timing chart showing an example of a calculation method of

[0185] In the method shown in FIG. 15, the capacitance C of the node FD1 when the transistor 51a is in a conductive state is FD1 When calculating the period during which the A / D converter circuit 42 operates, the period can be divided into periods T11 to T15. In the periods T11 to T15, the potential of the wiring 55a is set to high to turn on the transistor 51a. On the other hand, the potential of the wiring 55b is set to low to turn off the transistor 51b.

[0186] 16 to 18 are circuit diagrams showing an example of a method for driving the A / D conversion circuit 42 and the like in each period shown in FIG. 15. Specifically, FIG. 16 is a circuit diagram showing an example of a method for driving the A / D conversion circuit 42 and the like in period T11, FIG. 17A is a circuit diagram showing an example of a method for driving the A / D conversion circuit 42 and the like in period T12, FIG. 17B is a circuit diagram showing an example of a method for driving the A / D conversion circuit 42 and the like in period T13, FIG. 18A is a circuit diagram showing an example of a method for driving the A / D conversion circuit 42 and the like in period T15. Note that in FIGS. 16 to 18, the transistors in the A / D conversion circuit 42 are shown as switches to indicate their conductive and non-conductive states. Similar notations may be used in other circuit diagrams showing examples of a method for driving the A / D conversion circuit 42 and the like.

[0187] ​16 to 18, in the periods T11 to T15, the transistor 63 provided in the pixel circuit 14 and electrically connected to the wiring 34 is turned off. The potentials of the wiring 92, the wiring 95, and the wiring 97, which function as power supply lines, are set to the potentials VPRE, VCOM1, and VCOM2, respectively. Here, the potential VPRE is set to be higher than the potential VCOM1. As described above, the potential of the wiring 59 can be set to a low potential.

[0188] 15 and 16, in the period T11, the potential of the wiring 91 is set to high, thereby turning on the transistor 81. Furthermore, the potential of the wiring 93 is set to low, thereby turning off the transistors 82a and 82b. Furthermore, the potential of the wiring 94 is set to high, thereby turning on the transistors 83a and 83b. As a result, the potential of the node FD1 becomes the potential VPRE, and the potentials of the nodes FD2a and FD2b become the potential VCOM1. Because the potential of the node FD1 is precharged to the potential VPRE, the period T11 can be considered a precharge period.

[0189] 15 and 16, during the period T11, the potential of the wiring 96 is set to a high potential, thereby turning on the transistors 85 and 86. By turning on the transistor 85, the potential of the wiring 56 becomes the potential VCOM2. By turning on the transistor 86, the output terminal of the comparator circuit 53 and the second input terminal of the comparator circuit 53 become electrically connected. That is, feedback, for example, negative feedback, is applied to the comparator circuit 53. As a result, the potential of the comparison signal CMP output from the output terminal of the comparator circuit 53 becomes the potential obtained by adding the offset potential Voffset to the potential VCOM2. Therefore, the potential of the wiring 57 electrically connected to the second input terminal of the comparator circuit 53 also becomes the potential obtained by adding the offset potential Voffset to the potential VCOM2. As a result, a charge corresponding to the offset potential Voffset is accumulated in the capacitor 84b. Specifically, a charge corresponding to the difference between the potential VCOM1 of the node FD2b and the potential “VCOM2+Voffset” of the wiring 57 is accumulated in the capacitor 84b. Therefore, the offset of the comparison circuit 53 can be corrected.

[0190] 15 and 17A, in the period T12[1], the potential of the wiring 91 is set to low to turn off the transistor 81. This ends the precharging of the node FD1.

[0191] As shown in FIGS. 15 and 17B, in the period T13[1], the potential of the wiring 93 is set to a high potential, thereby turning on the transistors 82a and 82b. The potential of the wiring 94 is set to a low potential, thereby turning off the transistors 83a and 83b. As a result, the nodes FD1 and FD2a are brought into conduction, while the node FD2a is brought into non-conduction, and the node FD2a is brought into non-conduction. As a result, the nodes FD1 and FD2a are electrically connected, while both the nodes FD1 and FD2a are electrically floating. Therefore, when the transistor 51a is in a conductive state, charge sharing occurs between the capacitance of the node FD1 (parasitic capacitance PC, capacitor 52, etc.) and the capacitance of the node FD2a (capacitor 84a, etc.), and the potential Vs[1] of the nodes FD1 and FD2a is expressed by the following equation. Here, the capacitance value C FD2a indicates the capacitance value of node FD2a.

[0192]

number

[0193] As described above, the potential VPRE of the node FD1 in the period T12[1] is higher than the potential VCOM1 of the node FD2a in the period T12[1]. Therefore, the potential of the node FD1 decreases in the period T13[1].

[0194] As shown in FIGS. 15 and 17A, in the period T12[2], the potential of the wiring 93 is set to low, and the transistors 82a and 82b are set to a non-conducting state. As a result, the nodes FD1 and FD2a are set to a non-conducting state. In addition, the potential of the wiring 94 is set to high, and the transistors 83a and 83b are set to a conductive state. As a result, the potentials of the nodes FD2a and FD2b are set to the potential VCOM1. Here, since the nodes FD1 and FD2a are set to a non-conducting state, the potential Vs[1] of the node FD1 in the period T13[1] is held at the node FD1 during the period T12[2].

[0195] 15 and 17B, in the period T13[2], the potential of the wiring 93 is set to high and the potential of the wiring 94 is set to low. As a result, similar to the period T13[1], charge sharing occurs between the capacitance of the node FD1 and the capacitance of the node FD2a, and the potential Vs[2] of the node FD1 and the node FD2a becomes as shown in the following equation.

[0196]

number

[0197] The potential Vs[1] of node FD1 during period T12[2] is higher than the potential VCOM1 of node FD2a during period T12[2]. Therefore, the potential of node FD1 decreases during period T13[2]. Note that, as shown in Equation 3, the equation representing the potential Vs[2] includes the potential Vs[1]. Therefore, the equation representing the potential Vs can be said to be a recurrence formula.

[0198] In this way, by repeating the periods T12 and T13 multiple times, the potential of the node FD1 can be significantly reduced. Figure 15 shows a case where the operation of the period T12 is performed five times and the operation of the period T13 is performed four times. Note that the operation of the period T12 may be performed twice and the operation of the period T13 may be performed once. Alternatively, the operation of the period T12 may be performed three times and the operation of the period T13 may be performed two times. Alternatively, the operation of the period T12 may be performed four times and the operation of the period T13 may be performed three times. Furthermore, the operation of the period T12 may be performed six or more times and the operation of the period T13 may be performed five or more times.

[0199] The potential VPRE may be set to be equal to or lower than the potential VCOM1. When the potential VPRE is set to be lower than the potential VCOM1, the potential of the node FD1 increases due to the operations in the periods T12 and T13.

[0200] During period T12, the potential of node FD2a is reset to potential VCOM1. Therefore, period T12 can be said to be a reset period. Furthermore, during period T13, charge sharing occurs between the capacitance of node FD1 and the capacitance of node FD2a. Therefore, period T13 can be said to be a charge sharing period.

[0201] 15, the period T14 begins after the end of the period T12[5]. As shown in FIGS. 15 and 18A, in the period T14, the potential of the wiring 93 is set to high, so that the transistors 82a and 82b are turned on. The potential of the wiring 94 is set to low, so that the transistors 83a and 83b are turned off. Furthermore, the potential of the wiring 96 is set to low, so that the transistors 85 and 86 are turned off.

[0202] The potential of the node FD2a in the period T12[5] is the potential VCOM1. Then, in the period T14, the transistor 82a is turned on and the transistor 83a is turned off, so that the potential of the node FD2a electrically connected to one electrode of the capacitor 84a is the potential Vs[4]. That is, from the period T12[5] to the period T14, the potential of the node FD2a increases by the potential "Vs[4]-VCOM1." Furthermore, by turning the transistor 85 off, the wiring 56 electrically connected to the other electrode of the capacitor 84a is brought into an electrically floating state. As described above, if the capacitive coupling coefficient of the wiring 56 is 1, the potential of the wiring 56 also increases by the potential "Vs[4]-VCOM1" from the period T12[5] to the period T14.

[0203] The potential of the wiring 56 in the period T12[5] is the potential VCOM2. As a result, the potential of the wiring 56 in the period T14 is the potential "Vs[4]-VCOM1+VCOM2." Therefore, the potential of the first input terminal of the comparator circuit 53 is a potential corresponding to the potential Vs[4].

[0204] By turning on the transistor 82b and turning off the transistor 83b, the reference signal REF is supplied to the node FD2b electrically connected to one electrode of the capacitor 84b. By turning off the transistor 86, the wiring 57 electrically connected to the other electrode of the capacitor 84b is brought into an electrically floating state. As a result, the potential of the wiring 57 corresponds to the reference signal REF.

[0205] By turning off transistor 86, no feedback is applied to the comparator circuit 53. Therefore, during period T14, the potential of the comparison signal CMP output by the comparator circuit 53 is high when the potential of the non-inverting input terminal is higher than the potential of the inverting input terminal, and is low when the potential of the non-inverting input terminal is lower than the potential of the inverting input terminal. In FIG. 15, the potential of the reference signal REF during period T14, that is, the potential of node FD3, is higher than the potential of node FD2a. Therefore, the potential of wiring 57 is higher than the potential of wiring 56. Therefore, the potential of the comparison signal CMP is low.

[0206] During the period T14, the same operation as during the period T shown in Fig. 13 is performed. That is, for example, the potential of the reference signal REF is continuously decreased, and the counter circuit 54 counts the number of rising or falling edges of the clock signal CLK2.

[0207] When the potential of the comparison signal CMP becomes high, the period T14 ends and a transition to the period T15 occurs.

[0208] During period T15, the same operation as that after the end of period T shown in Fig. 13 is performed. That is, during period T15, the digital data signal DS_OUT continues to be output, the digital value of which corresponds to the number of times the clock signal CLK2 rises or falls from the start to the end of period T14.

[0209] By the above method, the A / D conversion circuit 42 can output a data signal DS_OUT corresponding to, for example, the potential Vs[4]. As described above, the potential Vs can be expressed by a recurrence formula. Also, as shown in Equation 2, the potential Vs[1] can be expressed by the potential VPRE, the potential VCOM1, the capacitance value C FD1 , and capacitance value C FD2a From the above, the potential Vs[4], the potential VPRE, the potential VCOM1, and the capacitance value C FD2a When the transistor 51a is in a conductive state, the capacitance C of the node FD1 is calculated by using FD1 can be calculated.

[0210] If the operation in period T12 is performed k+1 times (k is an integer greater than or equal to 1) and the operation in period T13 is performed k times, then in period T15, the A / D conversion circuit 42 outputs a data signal DS_OUT corresponding to a potential Vs[k]. The potential Vs[k] is expressed by the following equation:

[0211]

number

[0212] As shown in Equation 4, the equation representing the potential Vs[k] includes the potential Vs[k-1]. Therefore, Equation 4 can be said to be a recurrence formula. When the recurrence formula shown in Equation 4 is solved using Equation 2 representing the potential Vs[1], the potential Vs[k] is expressed by the following equation.

[0213]

number

[0214] Therefore, the capacitance value C FD1 is expressed by the following formula:

[0215]

number

[0216] From the above, the potential Vs[k], the potential VPRE, the potential VCOM1, and the capacitance value C FD2a When the transistor 51a is in a conductive state, the capacitance C of the node FD1 is calculated by using FD1 can be calculated using Equation 6.

[0217] By increasing k, that is, by increasing the number of times the operation in the period T12 and the number of times the operation in the period T13 are performed, the potential of the node FD1 can be greatly changed from the potential VPRE, which is the precharge potential. FD1 can be calculated with high accuracy.

[0218] The parasitic capacitance PC included in the capacitance of node FD1 includes capacitance formed outside IC20. Therefore, for example, when measuring the capacitance value of node FD1 when transistor 51a is in a conductive state using a measuring device, it is more expensive than when measuring the capacitance values ​​of capacitive elements 84a and the like included in IC20 using a measuring device. On the other hand, when the capacitance of node FD1 is calculated using the methods shown in Figures 15 to 18, for example, the capacitance of node FD1 can be calculated without using a measuring device. Therefore, the display device 10 can be made inexpensive.

[0219] 15 to 18, when the capacitance of the node FD1 is calculated while the transistor 51a is in an on state, it is preferable to hold charge at the node FD1 for a long period of time, because this allows the capacitance of the node FD1 to be calculated with high accuracy. Therefore, it is preferable to use transistors with low off-state current for the transistors 51b, 81, 82a, 83a, and 63. For example, it is preferable to use OS transistors.

[0220] Note that OS transistors may be applied to other transistors included in the A / D conversion circuit 42. Furthermore, OS transistors may be applied to all transistors included in IC20. If all transistors included in IC20 are OS transistors, all transistors included in IC20 can be formed in the same process. Furthermore, OS transistors may be applied to all transistors included in IC20 and all transistors included in the pixel 12. If all transistors included in IC20 and all transistors included in the pixel 12 are OS transistors, all transistors included in IC20 and all transistors included in the pixel 12 can be formed in the same process. Furthermore, if all transistors included in the display device 10 are OS transistors, all transistors included in the display device 10 can be formed in the same process. As described above, the number of manufacturing processes for the display device 10 can be reduced, and thus the display device 10 can be manufactured at a low price.

[0221] Furthermore, some or all of the transistors included in the display device 10 may be Si transistors or the like. For example, Si transistors may be applied to the transistors included in the IC 20. In particular, when a transistor including crystalline silicon (typically, low-temperature polysilicon, single-crystal silicon, or the like) is used as the Si transistor, the on-current of the transistor can be increased. Therefore, the display device 10 can be driven at high speed.

[0222] [Example of how to calculate the monitor current] The following describes an example of a method for calculating the monitor current using the capacitance value of node FD1 when transistor 51a is in a conductive state, calculated by the method shown in Figures 15 to 18. Figure 19 is a timing chart showing an example of a method for performing A / D conversion on analog monitor signal MS_A.

[0223] 19, when the analog monitor signal MS_A is A / D converted, the period during which the A / D converter circuit 42 is driven can be divided into periods T21 to T25. During the periods T21 to T25, the potential of the wiring 55a is set to high to turn on the transistor 51a. Meanwhile, the potential of the wiring 55b is set to low to turn off the transistor 51b. Also during the periods T21 to T25, as in the periods T11 to T15, the potentials of the wiring 92, the wiring 95, and the wiring 97, which function as power supply lines, are set to potentials VPRE, VCOM1, and VCOM2, respectively. Here, the potential VPRE is set to be lower than the potential VCOM1, for example.

[0224] Fig. 20A is a circuit diagram showing an example of a method for driving the A / D conversion circuit 42 etc. during a period T23. Fig. 20B is a circuit diagram showing an example of a method for driving the A / D conversion circuit 42 etc. during a period T24.

[0225] As shown in FIG. 19, in the period T21, the potential of the wiring 36 is set to low, thereby turning off the transistor 63. Furthermore, the potential of the wiring 91 is set to high, thereby turning on the transistor 81. Furthermore, the potential of the wiring 93 is set to low, thereby turning off the transistors 82a and 82b. Furthermore, the potential of the wiring 94 is set to high, thereby turning on the transistors 83a and 83b. As a result, the potential of the node FD1 becomes the potential VPRE, and the potentials of the nodes FD2a and FD2b become the potential VCOM1. Because the potential of the node FD1 is precharged to the potential VPRE, the period T21 can be considered a precharge period.

[0226] In the period T21, the potential of the wiring 96 is set to a high potential, thereby turning on the transistors 85 and 86. As a result, the potential of the comparison signal CMP becomes a potential obtained by adding the offset potential Voffset to the potential VCOM2, and the offset of the comparator circuit 53 can be corrected.

[0227] From the above, it can be said that the period T21 is a period in which the same operation as that of the period T11 is performed.

[0228] 19, in the period T22, the potential of the wiring 91 is set to low to turn off the transistor 81. This ends the precharging of the node FD1. The period T22 can be said to be a period in which the same operation as that in the period T12 is performed.

[0229] 19 and 20A, in the period T23, the potential of the wiring 36 is set to a high potential to turn on the transistor 63. As a result, the potential of the node FD1 increases in response to the analog monitor signal MS_A.

[0230] 19 and 20B, in the period T24, the potential of the wiring 36 is first set to low to turn off the transistor 63. Next, the potential of the wiring 93 is set to high to turn on the transistors 82a and 82b. The potential of the wiring 94 is set to low to turn off the transistors 83a and 83b. Furthermore, the potential of the wiring 96 is set to low to turn off the transistors 85 and 86.

[0231] By turning off the transistor 63, the potential of the node FD1 is held. The held potential is set to the potential VMS. With the potential of the node FD1 held, the transistor 82a is turned on and the transistors 83a and 85 are turned off, so that the potential of the wiring 56 becomes the potential "VMS-VCOM1+VCOM2." Therefore, the potential of the first input terminal of the comparator circuit 53 becomes a potential corresponding to the potential VMS.

[0232] When the transistor 82b is turned on and the transistor 83b is turned off, the reference signal REF is supplied to the node FD2b, and the potential of the wiring 57 becomes a potential corresponding to the reference signal REF.

[0233] Furthermore, by turning off transistor 86, the potential of the comparison signal CMP output by comparator circuit 53 becomes high when the potential of the non-inverting input terminal is higher than the potential of the inverting input terminal, and becomes low when the potential of the non-inverting input terminal is lower than the potential of the inverting input terminal. In FIG. 19, the potential of reference signal REF during period T24, i.e., the potential of node FD3, is higher than the potential of node FD2a. Therefore, the potential of wiring 57 becomes higher than the potential of wiring 56. Therefore, the potential of comparison signal CMP becomes low.

[0234] During period T24, the same operation as during period T shown in Fig. 13 is performed. That is, for example, the potential of the reference signal REF is continuously decreased, and the counter circuit 54 counts the number of rising or falling edges of the clock signal CLK2. When the potential of the comparison signal CMP becomes high, period T24 ends and a transition to period T25 occurs.

[0235] From the above, it can be said that the period T24 is a period in which the same operation as the period T14 is performed.

[0236] During period T25, the same operation as that after the end of period T shown in Fig. 13 is performed. In other words, during period T25, a data signal DS_OUT having a digital value corresponding to the number of times the clock signal CLK2 rose or fell from the start to the end of period T24 is continuously output. From the above, it can be said that period T25 is a period during which the same operation as period T15 is performed.

[0237] As described above, the analog monitor signal MS_A can be converted into a digital signal by the operations in periods T21 to T25. Specifically, the A / D conversion circuit 42 can output a data signal DS_OUT having a digital value corresponding to the potential VMS of the analog monitor signal MS_A. This allows the potential VMS to be calculated.

[0238] After calculating the potential VMS, the monitor current I is calculated using Equation 1. Here, ΔV FD1 may be the potential "VMS-VPRE", and Δt may be the length of the period T23.

[0239] 15 to 18, the capacitance value of node FD1 when transistor 51a is in a conductive state is calculated, and then the value of the monitor current is calculated by the methods shown in FIG. 19 and FIGS. 20A and 20B, thereby making it possible to calculate the value of the monitor current taking into account the parasitic capacitance PC of wiring 34, etc. Therefore, the value of the monitor current can be calculated with high accuracy, and therefore, for example, the threshold voltage of transistor 62 functioning as a drive transistor of pixel circuit 14 can be corrected with high accuracy. Therefore, for example, display unevenness can be reduced, and high-quality images can be displayed on the display unit 11.

[0240] [An example of A / D conversion method for analog imaging signals] Next, an example of a method for A / D conversion of the analog imaging signal IS_A will be described. FIG. 21 is a timing chart showing an example of a method for A / D conversion of the analog imaging signal IS_A. When A / D conversion is performed on the analog imaging signal IS_A using the method shown in FIG. 21, the period during which the A / D conversion circuit 42 is driven can be divided into periods T21 to T25, as in the case shown in FIG. 19. When A / D conversion is performed on the analog imaging signal IS_A, the potential of the wiring 55a is set to low during periods T21 to T25, thereby turning off the transistor 51a. Meanwhile, the potential of the wiring 55b is set to high, thereby turning on the transistor 51b.

[0241] Fig. 22A is a circuit diagram showing an example of a method for driving the A / D conversion circuit 42 and the like during a period T23 when A / D conversion is performed on the analog imaging signal IS_A. Fig. 22B is a circuit diagram showing an example of a method for driving the A / D conversion circuit 42 and the like during a period T24 when A / D conversion is performed on the analog imaging signal IS_A.

[0242] The following describes operations from period T21 to period T25 shown in Fig. 21. Note that descriptions of operations similar to those from period T21 to period T25 shown in Fig. 19 may be omitted.

[0243] 21, in a period T21, the potential of the wiring 32 is set to a low potential, thereby turning off the transistor 74 that is provided in the pixel circuit 15 and electrically connected to the wiring 35. In the period T21, the node FD1 is precharged, the offset of the comparator circuit 53 is corrected, and the like. Then, in a period T22, the precharging of the node FD1 is stopped.

[0244] 21 and 22A, during a period T23, the potential of the wiring 32 is set to a high potential, thereby turning on the transistor 74. This causes the potential of the wiring 35 to become a potential VIS corresponding to the analog imaging signal IS_A. When performing A / D conversion on the analog imaging signal IS_A, it is not necessary to measure the change in the potential of the wiring 35 over time. Therefore, it is preferable to continue the operation during the period T23 until the potential of the wiring 35 reaches a steady state. This allows for highly accurate A / D conversion of the analog imaging signal IS_A.

[0245] As shown in FIGS. 21 and 22B, in the period T24, first, the potential of the wiring 32 is set to low, thereby turning off the transistor 74. Next, the transistors 82a and 82b are turned on, and the transistors 83a, 83b, 85, and 86 are turned off. By turning on the transistor 82a and turning off the transistors 83a and 85, the potential of the wiring 56 becomes the potential "VIS-VCOM1+VCOM2." Therefore, the potential of the first input terminal of the comparator circuit 53 becomes a potential corresponding to the potential VIS. Furthermore, by turning on the transistor 82b and turning off the transistor 83b, the reference signal REF is supplied to the node FD2b, and the potential of the wiring 57 becomes a potential corresponding to the reference signal REF.

[0246] Furthermore, by turning off transistor 86, the potential of the comparison signal CMP output by comparator circuit 53 becomes high when the potential of the non-inverting input terminal is higher than the potential of the inverting input terminal, and becomes low when the potential of the non-inverting input terminal is lower than the potential of the inverting input terminal. In FIG. 21, the potential of reference signal REF during period T24, i.e., the potential of node FD3, is higher than the potential of node FD2a. Therefore, the potential of wiring 57 becomes higher than the potential of wiring 56. Therefore, the potential of comparison signal CMP becomes low.

[0247] During period T24, the same operation as during period T shown in Fig. 13 is performed. During period T25, the same operation as that after the end of period T shown in Fig. 13 is performed. In this way, the analog imaging signal IS_A can be converted into a digital signal. Specifically, the A / D conversion circuit 42 can output a data signal DS_OUT having a digital value corresponding to the potential of the analog imaging signal IS_A.

[0248] The above is an example of a method for driving the A / D conversion circuit 42 and the like configured as shown in FIG. 14A or 14B.

[0249] Note that one embodiment of the present invention can be applied even when the pixel 12 does not include the pixel circuit 15. For example, the structure in which the display portion 11 is provided so as to have a region overlapping with the IC 20, as shown in FIG. 2A or 2B, can be applied even when the pixel 12 does not include the pixel circuit 15. Furthermore, the structures shown in FIGS. 12A and 12B and 14A and 14B can be applied even when the pixel 12 does not include the pixel circuit 15. Note that when the structures shown in FIGS. 12A and 12B and 14A and 14B are applied to a display device that does not include the pixel circuit 15, the transistors 51a and 51b can be omitted.

[0250] At least a part of the configuration examples exemplified in this embodiment and the corresponding drawings can be implemented by appropriately combining with other configuration examples or drawings.

[0251] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0252] (Embodiment 2) In this embodiment, an example of a cross-sectional structure of a display device according to one embodiment of the present invention will be described.

[0253] FIG. 23A shows a cross-sectional view of the display device 10A.

[0254] The display device 10A includes a light receiving element 70 and a light emitting element 60.

[0255] The light receiving element 70 includes a pixel electrode 411 , a common layer 412 , an active layer 413 , a common layer 414 , and a common electrode 415 .

[0256] The light emitting element 60 includes a pixel electrode 191 , a common layer 412 , a light emitting layer 193 , a common layer 414 , and a common electrode 415 .

[0257] The pixel electrode 411, the pixel electrode 191, the common layer 412, the active layer 413, the light-emitting layer 193, the common layer 414, and the common electrode 415 may each have a single-layer structure or a laminated structure.

[0258] The pixel electrode 411 and the pixel electrode 191 are located on the insulating layer 214. The pixel electrode 411 and the pixel electrode 191 can be formed using the same material and in the same process.

[0259] The common layer 412 is located on the pixel electrode 411 and the pixel electrode 191. The common layer 412 is a layer that is used in common by the light receiving element 70 and the light emitting element 60.

[0260] The active layer 413 overlaps with the pixel electrode 411 via the common layer 412. The light-emitting layer 193 overlaps with the pixel electrode 191 via the common layer 412. The active layer 413 includes a first organic compound, and the light-emitting layer 193 includes a second organic compound different from the first organic compound.

[0261] The common layer 414 is located on the common layer 412, the active layer 413, and the light-emitting layer 193. The common layer 414 is a layer that is used in common by the light-receiving element 70 and the light-emitting element 60.

[0262] The common electrode 415 has a portion overlapping with the pixel electrode 411 via the common layer 412, the active layer 413, and the common layer 414. The common electrode 415 also has a portion overlapping with the pixel electrode 191 via the common layer 412, the light-emitting layer 193, and the common layer 414. The common electrode 415 is a layer used in common by the light-receiving element 70 and the light-emitting element 60.

[0263] In the display device of this embodiment, an organic compound is used for the active layer 413 of the light-receiving element 70. The layers of the light-receiving element 70 other than the active layer 413 can have a common configuration with the light-emitting element 60 (EL element). Therefore, by simply adding a step of forming the active layer 413 to the manufacturing process of the light-emitting element 60, the light-receiving element 70 can be formed in parallel with the formation of the light-emitting element 60. Furthermore, the light-emitting element 60 and the light-receiving element 70 can be formed on the same substrate. Therefore, the light-receiving element 70 can be built into the display device without significantly increasing the number of manufacturing steps.

[0264] The display device 10A shows an example in which the light receiving element 70 and the light emitting element 60 have a common configuration, except that the active layer 413 of the light receiving element 70 and the light emitting layer 193 of the light emitting element 60 are fabricated separately. However, the configuration of the light receiving element 70 and the light emitting element 60 is not limited to this. The light receiving element 70 and the light emitting element 60 may have layers fabricated separately from each other, in addition to the active layer 413 and the light emitting layer 193 (see display devices 10K, 10L, and 10M described below). It is preferable that the light receiving element 70 and the light emitting element 60 have one or more layers used in common (common layers). This allows the light receiving element 70 to be incorporated into the display device without significantly increasing the number of fabrication steps.

[0265] The display device 10A includes a light receiving element 70, a light emitting element 60, a transistor 341, a transistor 342, and the like between a pair of substrates (substrate 451 and substrate 452).

[0266] In the light-receiving element 70, the common layer 412, active layer 413, and common layer 414, which are respectively located between the pixel electrode 411 and the common electrode 415, can also be called organic layers (layers containing an organic compound). The pixel electrode 411 preferably has a function of reflecting visible light. The edge of the pixel electrode 411 is covered with a partition wall 216. The common electrode 415 has a function of transmitting visible light.

[0267] The light receiving element 70 has a function of detecting light. Specifically, the light receiving element 70 is a photoelectric conversion element that receives light 17 incident from outside the display device 10A and converts it into an electrical signal. The light 17 can also be said to be light emitted by the light emitting element 60 and reflected by an object. The light 17 may also be incident on the light receiving element 70 through a lens, which will be described later.

[0268] A light-shielding layer BM is provided on the surface of substrate 452 facing substrate 451. The light-shielding layer BM has openings at positions overlapping with the light-receiving element 70 and the light-emitting element 60. By providing the light-shielding layer BM, the range in which the light-receiving element 70 detects light can be controlled.

[0269] The light-shielding layer BM can be made of a material that blocks light emitted from the light-emitting element. The light-shielding layer BM preferably absorbs visible light. For example, the light-shielding layer BM can be made of a black matrix using a metal material or a resin material containing a pigment (carbon black, etc.) or a dye. The light-shielding layer BM may have a laminated structure of a red color filter, a green color filter, and a blue color filter.

[0270] Here, the display device 10A can detect the detection target by using the light receiving element 70 to detect light emitted by the light emitting element 60 and reflected by the detection target. However, there is a case where the light emitted by the light emitting element 60 is reflected within the display device 10A and enters the light receiving element 70 without passing through the detection target. The light-shielding layer BM can suppress the influence of such stray light. For example, if the light-shielding layer BM is not provided, the light 423a emitted by the light emitting element 60 may be reflected by the substrate 452, and the reflected light 423b may enter the light receiving element 70. By providing the light-shielding layer BM, it is possible to prevent the reflected light 423b from entering the light receiving element 70. This reduces noise and improves the sensitivity of the sensor using the light receiving element 70.

[0271] In the light-emitting element 60, the common layer 412, the light-emitting layer 193, and the common layer 414, which are respectively located between the pixel electrode 191 and the common electrode 415, can also be referred to as EL layers. The pixel electrode 191 preferably has a function of reflecting visible light. An end of the pixel electrode 191 is covered with a partition wall 216. The pixel electrode 411 and the pixel electrode 191 are electrically insulated from each other by the partition wall 216. The common electrode 415 has a function of transmitting visible light.

[0272] The light-emitting element 60 has a function of emitting visible light. Specifically, the light-emitting element 60 is an electroluminescent element that emits light toward the substrate 452 by applying a voltage between the pixel electrode 191 and the common electrode 415 (see light 16).

[0273] The light-emitting layer 193 is preferably formed so as not to overlap the light-receiving region of the light-receiving element 70. This makes it possible to suppress the light-emitting layer 193 from absorbing the light 17, and to increase the amount of light irradiated onto the light-receiving element 70.

[0274] The pixel electrode 411 is electrically connected to the source or drain of the transistor 341 through an opening provided in the insulating layer 214. An edge of the pixel electrode 411 is covered with a partition wall 216.

[0275] The pixel electrode 191 is electrically connected to a source or a drain of the transistor 342 through an opening provided in the insulating layer 214. An end portion of the pixel electrode 191 is covered with a partition wall 216. The transistor 342 has a function of controlling driving of the light-emitting element 60.

[0276] The transistor 341 and the transistor 342 are adjacent to each other on the same layer (substrate 451 in FIG. 23A).

[0277] At least a part of the circuit electrically connected to the light receiving element 70 is preferably formed using the same material and in the same process as the circuit electrically connected to the light emitting element 60. This allows the display device to be thinner and the manufacturing process to be simplified compared to when the two circuits are formed separately.

[0278] The light receiving element 70 and the light emitting element 60 are preferably covered with a protective layer 195. In FIG. 23A, the protective layer 195 is provided on and in contact with the common electrode 415. By providing the protective layer 195, it is possible to prevent impurities such as water from entering the light receiving element 70 and the light emitting element 60, thereby improving the reliability of the light receiving element 70 and the light emitting element 60. In addition, the protective layer 195 and the substrate 452 are bonded together by an adhesive layer 442.

[0279] 24A, a protective layer does not necessarily have to be provided on the light receiving element 70 and the light emitting element 60. In FIG. 24A, the common electrode 415 and the substrate 452 are bonded together by an adhesive layer 442.

[0280] [Display device 10B] 23B shows a cross-sectional view of display device 10B. In the following description of the display device, the description of the same configuration as the display device described above may be omitted.

[0281] The display device 10B shown in FIG. 23B includes a lens 449 in addition to the configuration of the display device 10A.

[0282] The display device of this embodiment may include a lens 449. The lens 449 is provided at a position overlapping with the light receiving element 70. In the display device 10B, the lens 449 is provided in contact with the substrate 452. The lens 449 included in the display device 10B has a convex surface facing the substrate 451. Alternatively, the lens 449 may have a convex surface facing the substrate 452.

[0283] When both the light-shielding layer BM and the lenses 449 are formed on the same surface of the substrate 452, the order of formation does not matter. Although Fig. 23B shows an example in which the lenses 449 are formed first, the light-shielding layer BM may also be formed first. In Fig. 23B, the edges of the lenses 449 are covered with the light-shielding layer BM.

[0284] The display device 10B is configured such that light 17 is incident on the light receiving element 70 via the lens 449. The inclusion of the lens 449 allows the imaging range of the light receiving element 70 to be narrower than when the lens 449 is not included, and overlapping of the imaging ranges of adjacent light receiving elements 70 can be suppressed. This allows for capturing clear images with less blur. Furthermore, for the same imaging range of the light receiving element 70, the inclusion of the lens 449 allows for a larger pinhole size (corresponding to the size of the opening of the BM that overlaps with the light receiving element 70 in FIG. 23B) than when the lens 449 is not included. Therefore, the inclusion of the lens 449 allows for an increased amount of light incident on the light receiving element 70.

[0285] The display devices shown in FIGS. 24B and 24C each have a configuration in which light 17 enters light receiving element 70 via lens 449, similar to display device 10B shown in FIG. 23B.

[0286] 24B, a lens 449 is provided in contact with the upper surface of the protective layer 195. The lens 449 included in the display device shown in FIG.

[0287] 24C has a lens array 446 provided on the display surface side of a substrate 452. Lenses included in the lens array 446 are provided at positions overlapping with the light receiving elements 70. A light-shielding layer BM is preferably provided on the surface of the substrate 452 facing the substrate 451.

[0288] As a method for forming lenses used in the display device of this embodiment, lenses such as microlenses may be formed directly on the substrate or on the light receiving element, or a lens array such as a separately prepared microlens array may be bonded to the substrate.

[0289] FIG. 23C shows a cross-sectional view of the display device 10C.

[0290] 23C differs from display device 10A in that display device 10C does not have substrate 451, substrate 452, and partition wall 216, but has substrate 453, substrate 454, adhesive layer 455, insulating layer 212, and partition wall 217.

[0291] The substrate 453 and the insulating layer 212 are bonded together by an adhesive layer 455. The substrate 454 and the protective layer 195 are bonded together by an adhesive layer 442.

[0292] The display device 10C is manufactured by transferring the insulating layer 212, the transistor 341, the transistor 342, the light-receiving element 70, the light-emitting element 60, and the like, which are formed on a manufacturing substrate, onto a substrate 453. The substrate 453 and the substrate 454 are preferably flexible, which can increase the flexibility of the display device 10C. For example, the substrate 453 and the substrate 454 are preferably made of a resin.

[0293] Substrate 453 and substrate 454 can be made of polyester resin such as polyethylene terephthalate (PET) or polyethylene naphthalate (PEN), polyacrylonitrile resin, acrylic resin, polyimide resin, polymethyl methacrylate resin, polycarbonate (PC) resin, polyethersulfone (PES) resin, polyamide resin (nylon, aramid, etc.), polysiloxane resin, cycloolefin resin, polystyrene resin, polyamideimide resin, polyurethane resin, polyvinyl chloride resin, polyvinylidene chloride resin, polypropylene resin, polytetrafluoroethylene (PTFE) resin, ABS resin, cellulose nanofiber, etc. One or both of substrates 453 and 454 may be made of glass having a thickness sufficient to provide flexibility.

[0294] The substrate of the display device of this embodiment may be formed using a film having high optical isotropy, such as a triacetyl cellulose (TAC, also called cellulose triacetate) film, a cycloolefin polymer (COP) film, a cycloolefin copolymer (COC) film, or an acrylic resin.

[0295] The partition wall 217 preferably absorbs light emitted by the light-emitting element. For example, a black matrix can be formed as the partition wall 217 using a resin material containing a pigment or a dye. Alternatively, the partition wall 217 can be formed of a colored insulating layer by using a brown resist material.

[0296] Light 423c emitted by the light-emitting element 60 is reflected by the substrate 452 and the partition wall 217, and reflected light 423d may be incident on the light-receiving element 70. Furthermore, when the light 423c passes through the partition wall 217 and is reflected by a transistor, wiring, or the like, the reflected light may be incident on the light-receiving element 70. The light 423c is absorbed by the partition wall 217, so that the reflected light 423d can be prevented from being incident on the light-receiving element 70. This reduces noise and increases the sensitivity of the sensor using the light-receiving element 70.

[0297] It is preferable that the partition 217 absorbs at least the wavelength of light detected by the light receiving element 70. For example, when the light receiving element 70 detects green light emitted by the light emitting element 60, it is preferable that the partition 217 absorbs at least the green light. For example, if the partition 217 has a red color filter, it can absorb the green light 423c and prevent the reflected light 423d from entering the light receiving element 70.

[0298] FIG. 25A shows a cross-sectional view of the display device 10D.

[0299] The display device 10D shown in FIG. 25A differs from the display device 10A in that it includes a color filter 460. The color filter 460 is provided to have an area overlapping the light-emitting element 60. The color filter 460 has the function of transmitting light of a specific color (wavelength) and absorbing light of other colors (wavelengths). For example, a color filter 460 that transmits red light can be provided to have an area overlapping the pixel circuit 14R that emits red light 16R shown in Embodiment 1. A color filter 460 that transmits green light can be provided to have an area overlapping the pixel circuit 14G that emits green light 16G. A color filter 460 that transmits blue light can be provided to have an area overlapping the pixel circuit 14B that emits blue light 16B.

[0300] In the display device 10D, for example, a light-emitting layer that emits white light can be used as the light-emitting layer 193. This eliminates the need to paint the light-emitting layer 193 differently depending on the color of light emitted by the pixel circuit 14, thereby enabling the pixels 12 to have high definition. Furthermore, this reduces the manufacturing cost of the display device, allowing the display device 10D to be made inexpensively.

[0301] FIG. 25B shows a cross-sectional view of the display device 10E.

[0302] 25B differs from display device 10A in that it includes a lens 461. Lens 461 can be provided in contact with the upper surface of protective layer 195 so as to have an area overlapping with light-emitting element 60. Lens 461 has a convex surface facing substrate 452.

[0303] FIG. 25C shows a cross-sectional view of the display device 10F.

[0304] 25C differs from display device 10A in that it includes a lens array 462. Lens array 462 can be provided on the display surface side of substrate 452. Lenses included in lens array 462 are provided so as to have areas overlapping with light-emitting elements 60.

[0305] As in the display device 10E or the display device 10F, by providing a lens so as to have an area overlapping with the light emitting element 60, it is possible to increase the extraction efficiency of the light 16 emitted by the light emitting layer 193. Therefore, it is possible to display a high-brightness image on the display unit 11 in which the light emitting element 60 is provided.

[0306] FIG. 26A shows a cross-sectional view of the display device 10K, FIG. 26B shows a cross-sectional view of the display device 10L, and FIG. 26C shows a cross-sectional view of the display device 10M.

[0307] The display device 10K differs from the display device 10A in that it does not have a common layer 414, but has a buffer layer 184 and a buffer layer 194. The buffer layer 184 and the buffer layer 194 may each have a single-layer structure or a stacked-layer structure.

[0308] In the display device 10K, the light receiving element 70 has a pixel electrode 411, a common layer 412, an active layer 413, a buffer layer 184, and a common electrode 415. In the display device 10K, the light emitting element 60 has a pixel electrode 191, a common layer 412, a light emitting layer 193, a buffer layer 194, and a common electrode 415.

[0309] The display device 10L differs from the display device 10A in that it does not have a common layer 412, but has a buffer layer 182 and a buffer layer 192. The buffer layer 182 and the buffer layer 192 may each have a single-layer structure or a stacked-layer structure.

[0310] In the display device 10L, the light-receiving element 70 has a pixel electrode 411, a buffer layer 182, an active layer 413, a common layer 414, and a common electrode 415. In the display device 10L, the light-emitting element 60 has a pixel electrode 191, a buffer layer 192, a light-emitting layer 193, a common layer 414, and a common electrode 415.

[0311] The display device 10M differs from the display device 10A in that it does not have the common layer 412 and the common layer 414, but has the buffer layer 182, the buffer layer 184, the buffer layer 192, and the buffer layer 194.

[0312] In the display device 10M, the light-receiving element 70 has a pixel electrode 411, a buffer layer 182, an active layer 413, a buffer layer 184, and a common electrode 415. In the display device 10M, the light-emitting element 60 has a pixel electrode 191, a buffer layer 192, a light-emitting layer 193, a buffer layer 194, and a common electrode 415.

[0313] In the manufacture of the light receiving element 70 and the light emitting element 60, not only can the active layer 413 and the light emitting layer 193 be separately manufactured, but other layers can also be separately manufactured.

[0314] In the display device 10K, an example is shown in which a buffer layer 184 between the common electrode 415 and the active layer 413 and a buffer layer 194 between the common electrode 415 and the light-emitting layer 193 are separately formed. As the buffer layer 194, for example, one or both of an electron injection layer and an electron transport layer can be formed.

[0315] The display device 10L shows an example in which a buffer layer 182 between the pixel electrode 411 and the active layer 413 and a buffer layer 192 between the pixel electrode 191 and the light-emitting layer 193 are separately formed. As the buffer layer 192, for example, one or both of a hole injection layer and a hole transport layer can be formed.

[0316] The display device 10M shows an example in which the light receiving element 70 and the light emitting element 60 do not have a common layer between a pair of electrodes (the pixel electrode 411 or the pixel electrode 191 and the common electrode 415). The light receiving element 70 and the light emitting element 60 of the display device 10M can be manufactured by forming the pixel electrode 411 and the pixel electrode 191 on the insulating layer 214 using the same material and in the same process, forming the buffer layer 182, the active layer 413, and the buffer layer 184 on the pixel electrode 411, forming the buffer layer 192, the light emitting layer 193, and the buffer layer 194 on the pixel electrode 191, and then forming the common electrode 415 to cover the pixel electrode 411, the buffer layer 182, the active layer 413, the buffer layer 184, the pixel electrode 191, the buffer layer 192, the light emitting layer 193, and the buffer layer 194. The order in which the stacked structure of the buffer layer 182, the active layer 413, and the buffer layer 184 and the stacked structure of the buffer layer 192, the light-emitting layer 193, and the buffer layer 194 are formed is not particularly limited. For example, the buffer layer 192, the light-emitting layer 193, and the buffer layer 194 may be formed after the buffer layer 182, the active layer 413, and the buffer layer 184 are formed. Conversely, the buffer layer 192, the light-emitting layer 193, and the buffer layer 194 may be formed before the buffer layer 182, the active layer 413, and the buffer layer 184 are formed. Furthermore, the buffer layer 182, the buffer layer 192, the active layer 413, the light-emitting layer 193, and the like may be formed alternately in this order.

[0317] A display device 400A shown in FIG. 27 includes a transistor 201, a transistor 205, a transistor 206, a light-emitting element 60, a light-receiving element 70, and the like between a substrate 451 and a substrate 452.

[0318] The substrate 452 and the insulating layer 214 are bonded via an adhesive layer 442. A solid sealing structure, a hollow sealing structure, or the like can be applied to seal the light emitting element 60 and the light receiving element 70. In FIG. 27 , a space 443 surrounded by the substrate 452, the adhesive layer 442, and the insulating layer 214 is filled with an inert gas (nitrogen, argon, etc.), and a hollow sealing structure is applied. The adhesive layer 442 may be provided so as to overlap the light emitting element 60. Furthermore, the space 443 surrounded by the substrate 452, the adhesive layer 442, and the insulating layer 214 may be filled with a resin different from the adhesive layer 442.

[0319] The light-emitting element 60 has a layered structure in which a pixel electrode 191, a common layer 412, a light-emitting layer 193, a common layer 414, and a common electrode 415 are stacked in this order from the insulating layer 214 side. The pixel electrode 191 is connected to a conductive layer 222b of the transistor 206 through an opening provided in the insulating layer 214. The transistor 206 has a function of controlling driving of the light-emitting element 60. An end of the pixel electrode 191 is covered with a partition wall 216. The pixel electrode 191 contains a material that reflects visible light, and the common electrode 415 contains a material that transmits visible light.

[0320] The light-receiving element 70 has a layered structure in which a pixel electrode 411, a common layer 412, an active layer 413, a common layer 414, and a common electrode 415 are layered in this order from the insulating layer 214 side. The pixel electrode 411 is electrically connected to a conductive layer 222b of the transistor 205 through an opening provided in the insulating layer 214. An end of the pixel electrode 411 is covered with a partition wall 216. The pixel electrode 411 contains a material that reflects visible light, and the common electrode 415 contains a material that transmits visible light.

[0321] Light emitted by the light-emitting element 60 is emitted toward the substrate 452. Furthermore, light is incident on the light-receiving element 70 via the substrate 452 and the space 443. The substrate 452 is preferably made of a material that is highly transparent to visible light.

[0322] The pixel electrode 411 and the pixel electrode 191 can be manufactured using the same material and the same process. The common layer 412, the common layer 414, and the common electrode 415 are used for both the light receiving element 70 and the light emitting element 60. The light receiving element 70 and the light emitting element 60 can have the same configuration except for the configurations of the active layer 413 and the light emitting layer 193. This allows the light receiving element 70 to be built into the display device 400A without significantly increasing the number of manufacturing processes.

[0323] A light-shielding layer BM is provided on the surface of the substrate 452 facing the substrate 451. The light-shielding layer BM has openings at positions overlapping the light receiving element 70 and the light emitting element 60. By providing the light-shielding layer BM, the range in which the light receiving element 70 detects light can be controlled. Furthermore, by providing the light-shielding layer BM, it is possible to prevent light from being directly incident on the light receiving element 70 from the light emitting element 60 without passing through an object. Therefore, a sensor with low noise and high sensitivity can be realized.

[0324] The transistor 201, the transistor 205, and the transistor 206 are all formed over a substrate 451. These transistors can be manufactured using the same material and through the same process.

[0325] An insulating layer 211, an insulating layer 213, an insulating layer 215, and an insulating layer 214 are provided over the substrate 451 in this order. A part of the insulating layer 211 functions as a gate insulating layer for each transistor. A part of the insulating layer 213 functions as a gate insulating layer for each transistor. The insulating layer 215 is provided to cover the transistor. The insulating layer 214 is provided to cover the transistor and functions as a planarization layer. Note that the number of gate insulating layers and the number of insulating layers covering the transistors are not limited, and each may be a single layer or two or more layers.

[0326] At least one insulating layer covering the transistor is preferably made of a material that is resistant to the diffusion of impurities such as water and hydrogen. This allows the insulating layer to function as a barrier layer. With this structure, it is possible to effectively prevent impurities from diffusing into the transistor from the outside, thereby improving the reliability of the display device.

[0327] It is preferable to use an inorganic insulating film for each of the insulating layers 211, 213, and 215. Examples of inorganic insulating films that can be used include a silicon nitride film, a silicon oxynitride film, a silicon oxide film, a silicon nitride oxide film, an aluminum oxide film, and an aluminum nitride film. Alternatively, a hafnium oxide film, an yttrium oxide film, a zirconium oxide film, a gallium oxide film, a tantalum oxide film, a magnesium oxide film, a lanthanum oxide film, a cerium oxide film, a neodymium oxide film, or the like may be used. Two or more of the above insulating films may be stacked.

[0328] Here, organic insulating films often have lower barrier properties than inorganic insulating films. Therefore, it is preferable that the organic insulating film has an opening near the edge of the display device 400A. This can prevent impurities from entering from the edge of the display device 400A through the organic insulating film. Alternatively, the organic insulating film may be formed so that the edge of the organic insulating film is located inside the edge of the display device 400A, so that the organic insulating film is not exposed at the edge of the display device 400A.

[0329] An organic insulating film is suitable for the insulating layer 214, which functions as a planarizing layer. Materials that can be used for the organic insulating film include acrylic resin, polyimide resin, epoxy resin, polyamide resin, polyimideamide resin, siloxane resin, benzocyclobutene resin, phenol resin, and precursors of these resins.

[0330] 27, an opening is formed in the insulating layer 214. This makes it possible to prevent impurities from entering the display unit 11 from the outside through the insulating layer 214, even when an organic insulating film is used for the insulating layer 214. This makes it possible to improve the reliability of the display device 400A.

[0331] The transistor 201, the transistor 205, and the transistor 206 each include a conductive layer 221 that functions as a gate, an insulating layer 211 that functions as a gate insulating layer, conductive layers 222a and 222b that function as a source and a drain, a semiconductor layer 231, an insulating layer 213 that functions as a gate insulating layer, and a conductive layer 223 that functions as a gate. Here, the same hatching pattern is applied to multiple layers obtained by processing the same conductive film. The insulating layer 211 is located between the conductive layer 221 and the semiconductor layer 231. The insulating layer 213 is located between the conductive layer 223 and the semiconductor layer 231.

[0332] The structure of the transistor included in the display device of this embodiment is not particularly limited. For example, a planar transistor, a staggered transistor, an inverted staggered transistor, or the like can be used. Furthermore, either a top-gate transistor or a bottom-gate transistor structure may be used. Alternatively, gates may be provided above and below a semiconductor layer in which a channel is formed.

[0333] The transistors 201, 205, and 206 each have a structure in which a semiconductor layer in which a channel is formed is sandwiched between two gates. The two gates may be connected and supplied with the same signal to drive the transistor. Alternatively, the threshold voltage of the transistor may be controlled by applying a potential for controlling the threshold voltage to one of the two gates and a potential for driving to the other.

[0334] The crystallinity of a semiconductor material used for a transistor is not particularly limited, and any of an amorphous semiconductor, a single crystal semiconductor, and a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part) may be used. The use of a single crystal semiconductor or a semiconductor having crystallinity other than single crystal is preferable because it can suppress deterioration of transistor characteristics.

[0335] The semiconductor layer of the transistor preferably contains a metal oxide (also referred to as an oxide semiconductor). Alternatively, the semiconductor layer of the transistor may contain silicon. Examples of silicon include amorphous silicon and crystalline silicon (such as low-temperature polysilicon and single-crystal silicon).

[0336] The semiconductor layer preferably contains, for example, indium, M (wherein M is one or more elements selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium), and zinc. In particular, M is preferably one or more elements selected from aluminum, gallium, yttrium, and tin.

[0337] In particular, it is preferable to use an oxide containing indium (In), gallium (Ga), and zinc (Zn) (also referred to as IGZO) as the semiconductor layer.

[0338] When the semiconductor layer is an In-M-Zn oxide, the sputtering target used to deposit the In-M-Zn oxide preferably has an atomic ratio of In equal to or greater than the atomic ratio of M. Examples of atomic ratios of metal elements in such sputtering targets include In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=2:1:3, In:M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4.1, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5:1:8, In:M:Zn=6:1:6, and In:M:Zn=5:2:5.

[0339] As the sputtering target, a target containing a polycrystalline oxide is preferably used because it facilitates the formation of a crystalline semiconductor layer. The atomic ratio of the semiconductor layer to be formed can vary by ±40% of the atomic ratio of the metal elements contained in the sputtering target. For example, if the composition of the sputtering target used for the semiconductor layer is In:Ga:Zn=4:2:4.1 [atomic ratio], the composition of the semiconductor layer to be formed may be close to In:Ga:Zn=4:2:3 [atomic ratio].

[0340] When describing an atomic ratio of In:Ga:Zn=4:2:3 or thereabout, this includes a case where, when the atomic ratio of In is 4, the atomic ratio of Ga is 1 or more and 3 or less, and the atomic ratio of Zn is 2 or more and 4 or less. When describing an atomic ratio of In:Ga:Zn=5:1:6 or thereabout, this includes a case where, when the atomic ratio of In is 5, the atomic ratio of Ga is more than 0.1 and 2 or less, and the atomic ratio of Zn is 5 or more and 7 or less. When describing an atomic ratio of In:Ga:Zn=1:1:1 or thereabout, this includes a case where, when the atomic ratio of In is 1, the atomic ratio of Ga is more than 0.1 and 2 or less, and the atomic ratio of Zn is more than 0.1 and 2 or less.

[0341] The transistors included in the circuit 164 may have the same structure as or different from the transistors included in the display portion 11. The transistors included in the circuit 164 may all have the same structure or may have two or more types of structures. Similarly, the transistors included in the display portion 11 may all have the same structure or may have two or more types of structures. Note that the circuit 164 can be the gate driver circuit 13 or the row driver circuit 19 described in Embodiment 1, for example.

[0342] A connection portion 204 is provided in an area of ​​the substrate 451 where the substrate 452 does not overlap. In the connection portion 204, the wiring 165 is electrically connected to the FPC 172 via a conductive layer 166 and a connection layer 242. The conductive layer 166, which is obtained by processing the same conductive film as the pixel electrode 191, is exposed on the upper surface of the connection portion 204. This allows the connection portion 204 and the FPC 172 to be electrically connected via the connection layer 242.

[0343] Various optical members can be arranged on the outside of substrate 452. Examples of optical members include a polarizing plate, a retardation plate, a light diffusion layer (such as a diffusion film), an anti-reflection layer, and a light collecting film. In addition, an antistatic film that suppresses the adhesion of dust, a water-repellent film that makes it difficult for dirt to adhere, a hard coat film that suppresses the occurrence of scratches during use, an impact absorbing layer, etc. may be arranged on the outside of substrate 452.

[0344] The substrate 451 and the substrate 452 can be made of glass, quartz, ceramic, sapphire, resin, etc. When the substrate 451 and the substrate 452 are made of a flexible material, the flexibility of the display device can be increased.

[0345] The adhesive layer can be made of various curable adhesives, such as photo-curable adhesives (e.g., ultraviolet curable), reactive curable adhesives, thermosetting adhesives, and anaerobic adhesives. Examples of such adhesives include epoxy resin, acrylic resin, silicone resin, phenolic resin, polyimide resin, imide resin, PVC (polyvinyl chloride) resin, PVB (polyvinyl butyral) resin, and EVA (ethylene vinyl acetate) resin. Materials with low moisture permeability, such as epoxy resin, are particularly preferred. Two-component resins may also be used. Adhesive sheets, etc., may also be used.

[0346] The connection layer 242 may be made of an anisotropic conductive film (ACF), an anisotropic conductive paste (ACP), or the like.

[0347] The light-emitting element 60 may be of a top emission type, a bottom emission type, a dual emission type, etc. A conductive film that transmits visible light is used for the electrode on the light extraction side. It is also preferable that a conductive film that reflects visible light is used for the electrode on the non-light extraction side.

[0348] The light-emitting element 60 has at least the light-emitting layer 193. The light-emitting element 60 may further have, in addition to the light-emitting layer 193, a layer containing a substance with a high hole-injection property, a substance with a high hole-transport property, a hole-blocking material, a substance with a high electron-transport property, a substance with a high electron-injection property, or a bipolar substance (a substance with high electron-transport property and hole-transport property). For example, the common layer 412 preferably has one or both of a hole-injection layer and a hole-transport layer. For example, the common layer 414 preferably has one or both of an electron-transport layer and an electron-injection layer.

[0349] Both low molecular weight compounds and high molecular weight compounds may be used, and may contain inorganic compounds, for the common layer 412, the light emitting layer 193, and the common layer 414. The layers constituting the common layer 412, the light emitting layer 193, and the common layer 414 can be formed by a method such as vapor deposition (including vacuum vapor deposition), a transfer method, a printing method, an inkjet method, or a coating method.

[0350] The light-emitting layer 193 may contain an inorganic compound such as quantum dots as a light-emitting material.

[0351] The active layer 413 of the light-receiving element 70 includes a semiconductor. Examples of the semiconductor include inorganic semiconductors such as silicon, and organic semiconductors containing organic compounds. In this embodiment, an example is shown in which an organic semiconductor is used as the semiconductor of the active layer. By using an organic semiconductor, the light-emitting layer 193 of the light-emitting element 60 and the active layer 413 of the light-receiving element 70 can be formed by the same method (for example, vacuum deposition), which is preferable because it allows the use of common manufacturing equipment.

[0352] The active layer 413 has an n-type semiconductor material, such as fullerene (e.g., C 60 , C 70Examples of the p-type semiconductor material of the active layer 413 include electron-accepting organic semiconductor materials such as copper(II) phthalocyanine (CuPc) and tetraphenyldibenzoperiflanthene (DBP).

[0353] For example, the active layer 413 is preferably formed by co-evaporating an n-type semiconductor and a p-type semiconductor.

[0354] Materials that can be used for the gate, source, and drain of a transistor as well as conductive layers such as various wirings and electrodes that constitute a display device include metals such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, and tungsten, and alloys containing these as main components, etc. Films containing these materials can be used as a single layer or a stacked layer structure.

[0355] Examples of light-transmitting conductive materials include conductive oxides such as indium oxide, indium tin oxide, indium zinc oxide, zinc oxide, and zinc oxide containing gallium, or graphene. Alternatively, metal materials such as gold, silver, platinum, magnesium, nickel, tungsten, chromium, molybdenum, iron, cobalt, copper, palladium, and titanium, and alloy materials containing these metal materials, can be used. Alternatively, nitrides of these metal materials (e.g., titanium nitride) can be used. When using metal materials or alloy materials (or their nitrides), it is preferable to thin them thin enough to have light-transmitting properties. A stacked film of the above materials can also be used as a conductive layer. For example, a stacked film of an alloy of silver and magnesium and indium tin oxide is preferable because it can increase conductivity. These can also be used for conductive layers such as various wirings and electrodes constituting a display device, and conductive layers (conductive layers functioning as pixel electrodes or common electrodes) of display elements.

[0356] Examples of insulating materials that can be used for each insulating layer include resins such as acrylic resin and epoxy resin, and inorganic insulating materials such as silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, and aluminum oxide.

[0357] FIG. 28A shows a cross-sectional view of the display device 400B.

[0358] The display device 400B differs from the display device 400A mainly in that the display device 400B has a lens 449 and a protective layer 195.

[0359] By providing a protective layer 195 that covers the light receiving element 70 and the light emitting element 60, impurities such as water can be prevented from entering the light receiving element 70 and the light emitting element 60, thereby improving the reliability of the light receiving element 70 and the light emitting element 60.

[0360] In a region 228 near the edge of the display device 400B, it is preferable that the insulating layer 215 and the protective layer 195 contact each other through the opening in the insulating layer 214. In particular, it is preferable that the inorganic insulating film of the insulating layer 215 and the inorganic insulating film of the protective layer 195 contact each other. This makes it possible to prevent impurities from entering the display unit 11 from the outside through the organic insulating film. This can therefore improve the reliability of the display device 400B.

[0361] 28B shows an example in which the protective layer 195 has a three-layer structure. In Fig. 28B, the protective layer 195 has an inorganic insulating layer 195a on the common electrode 415, an organic insulating layer 195b on the inorganic insulating layer 195a, and an inorganic insulating layer 195c on the organic insulating layer 195b.

[0362] The ends of the inorganic insulating layer 195a and the inorganic insulating layer 195c extend outward beyond the ends of the organic insulating layer 195b and are in contact with each other. The inorganic insulating layer 195a is in contact with the insulating layer 215 (inorganic insulating layer) through an opening in the insulating layer 214 (organic insulating layer). This allows the insulating layer 215 and the protective layer 195 to surround the light receiving element 70 and the light emitting element 60, thereby improving the reliability of the light receiving element 70 and the light emitting element 60.

[0363] In this way, the protective layer 195 may have a laminated structure of an organic insulating film and an inorganic insulating film. In this case, it is preferable that the end of the inorganic insulating film extends further outward than the end of the organic insulating film.

[0364] A lens 449 is provided on the surface of substrate 452 facing substrate 451. Lens 449 has a convex surface facing substrate 451. It is preferable that the light receiving region of light receiving element 70 overlaps lens 449 but does not overlap light emitting layer 193. This can improve the sensitivity and accuracy of a sensor using light receiving element 70.

[0365] The lens 449 preferably has a refractive index of 1.3 or more and 2.5 or less. The lens 449 can be formed using an inorganic material or an organic material. For example, a material containing resin can be used for the lens 449. Alternatively, a material containing oxide or sulfide can be used for the lens 449.

[0366] Specifically, a resin containing chlorine, bromine, or iodine, a resin containing a heavy metal atom, a resin containing an aromatic ring, a resin containing sulfur, or the like can be used for the lens 449. Alternatively, a material containing a resin and nanoparticles of a material with a higher refractive index than the resin can be used for the lens 449. Titanium oxide, zirconium oxide, or the like can be used for the nanoparticles.

[0367] Furthermore, cerium oxide, hafnium oxide, lanthanum oxide, magnesium oxide, niobium oxide, tantalum oxide, titanium oxide, yttrium oxide, zinc oxide, oxides containing indium and tin, or oxides containing indium, gallium, and zinc can be used for the lens 449. Alternatively, zinc sulfide or the like can be used for the lens 449.

[0368] In the display device 400B, the protective layer 195 and the substrate 452 are bonded together by an adhesive layer 442. The adhesive layer 442 is provided so as to overlap the light receiving element 70 and the light emitting element 60, respectively, and a solid sealing structure is applied to the display device 400B.

[0369] FIG. 29A shows a cross-sectional view of a display device 400C.

[0370] The display device 400C differs from the display device 400B in the structure of the transistors.

[0371] The display device 400C includes a transistor 208, a transistor 209, and a transistor 210 over a substrate 451.

[0372] The transistor 208, the transistor 209, and the transistor 210 each include a conductive layer 221 functioning as a gate, an insulating layer 211 functioning as a gate insulating layer, a semiconductor layer including a channel formation region 231i and a pair of low-resistance regions 231n, a conductive layer 222a connected to one of the pair of low-resistance regions 231n, a conductive layer 222b connected to the other of the pair of low-resistance regions 231n, an insulating layer 225 functioning as a gate insulating layer, a conductive layer 223 functioning as a gate, and an insulating layer 215 covering the conductive layer 223. The insulating layer 211 is located between the conductive layer 221 and the channel formation region 231i. The insulating layer 225 is located between the conductive layer 223 and the channel formation region 231i.

[0373] The conductive layer 222a and the conductive layer 222b are connected to the low-resistance region 231n through openings provided in the insulating layer 225 and the insulating layer 215, respectively. One of the conductive layer 222a and the conductive layer 222b functions as a source, and the other functions as a drain.

[0374] The pixel electrode 191 of the light emitting element 60 is electrically connected to one of a pair of low resistance regions 231n of the transistor 208 via the conductive layer 222b.

[0375] The pixel electrode 411 of the light receiving element 70 is electrically connected to the other of the pair of low resistance regions 231n of the transistor 209 via the conductive layer 222b.

[0376] 29A shows an example in which the insulating layer 225 covers the top and side surfaces of the semiconductor layer. On the other hand, in FIG. 29B, the insulating layer 225 overlaps with the channel formation region 231i of the semiconductor layer 231 but does not overlap with the low-resistance region 231n. For example, the structure shown in FIG. 29B can be manufactured by processing the insulating layer 225 using the conductive layer 223 as a mask. In FIG. 29B, the insulating layer 215 is provided to cover the insulating layer 225 and the conductive layer 223, and the conductive layer 222a and the conductive layer 222b are each connected to the low-resistance region 231n through openings in the insulating layer 215. Furthermore, an insulating layer 218 may be provided to cover the transistor.

[0377] FIG. 30 shows a cross-sectional view of a display device 400D.

[0378] Display device 400D differs from display device 400C mainly in that it does not have substrate 451 and substrate 452, but has substrate 453, substrate 454, adhesive layer 455, and insulating layer 212, and in that it has lens 449.

[0379] The substrate 453 and the insulating layer 212 are bonded together by an adhesive layer 455. The substrate 454 and the protective layer 195 are bonded together by an adhesive layer 442.

[0380] The display device 400D is manufactured by transferring the insulating layer 212, the transistor 208, the transistor 209, the transistor 210, the light-receiving element 70, the light-emitting element 60, and the like, which are formed over a manufacturing substrate, onto a substrate 453. The substrate 453 and the substrate 454 are preferably flexible, which can increase the flexibility of the display device 400D.

[0381] The insulating layer 212 can be formed using the inorganic insulating film that can be used for the insulating layers 211, 213, and 215.

[0382] The display device 400C does not include a lens 449, whereas the display device 400D includes a lens 449. The lens 449 can be provided as appropriate depending on the application of the sensor.

[0383] As described above, the display device of this embodiment has a light-receiving element and a light-emitting element in the display portion, and the display portion has both a function of displaying an image and a function of detecting light. This allows the electronic device to be made smaller and lighter than when a sensor is provided outside the display portion or the display device. Furthermore, by combining the sensor provided outside the display portion or the display device, a more multifunctional electronic device can be realized.

[0384] At least one layer of the light-receiving element, other than the active layer, can be configured in common with the light-emitting element (EL element). Furthermore, all layers of the light-receiving element, other than the active layer, can be configured in common with the light-emitting element (EL element). For example, by simply adding a process for forming an active layer to the manufacturing process of the light-emitting element, the light-emitting element and the light-receiving element can be formed on the same substrate. Furthermore, the pixel electrode and the common electrode of the light-receiving element and the light-emitting element can be formed using the same material and in the same process, respectively. Furthermore, by manufacturing the circuit electrically connected to the light-receiving element and the circuit electrically connected to the light-emitting element using the same material and in the same process, the manufacturing process of the display device can be simplified. In this way, a highly convenient display device incorporating a light-receiving element can be manufactured without complex processes.

[0385] The display device of this embodiment also includes a colored layer between the light-receiving element and the light-emitting element. The colored layer may also serve as a partition wall that electrically insulates the light-receiving element from the light-emitting element. The colored layer can absorb stray light in the display device, thereby increasing the sensitivity of a sensor using the light-receiving element.

[0386] At least a part of the configuration examples exemplified in this embodiment and the corresponding drawings can be implemented by appropriately combining with other configuration examples or drawings.

[0387] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0388] (Embodiment 3) In this embodiment, a configuration example of a semiconductor device applicable to the IC 20 described in Embodiment 1 will be described. As an example, a configuration in which transistors having different electrical characteristics are stacked will be described. By using this configuration, the degree of freedom in designing the semiconductor device can be increased. In addition, by stacking transistors having different electrical characteristics, the degree of integration of the semiconductor device can be increased.

[0389] A portion of the cross-sectional structure of a semiconductor device is shown in Fig. 31. The semiconductor device shown in Fig. 31 has a transistor 550, a transistor 500, and a capacitor 600. Fig. 33A is a cross-sectional view of the transistor 500 in the channel length direction, Fig. 33B is a cross-sectional view of the transistor 500 in the channel width direction, and Fig. 33C is a cross-sectional view of the transistor 550 in the channel width direction.

[0390] The transistor 500 is an OS transistor. The off-state current of the transistor 500 is extremely low. Therefore, a data voltage or charge written to a storage node through the transistor 500 can be held for a long period of time. That is, the frequency of refresh operations of the storage node can be reduced or no refresh operations are required, thereby reducing the power consumption of the semiconductor device.

[0391] In FIG. 31, the transistor 500 is provided above the transistor 550 , and the capacitor 600 is provided above the transistor 550 and the transistor 500 .

[0392] The transistor 550 is provided over a substrate 311 and includes a conductor 316, an insulator 315, a semiconductor region 313 made of part of the substrate 311, and low-resistance regions 314a and 314b functioning as source and drain regions.

[0393] 33C , in the transistor 550, the top surface and the side surfaces in the channel width direction of the semiconductor region 313 are covered with a conductor 316 via an insulator 315. By forming the transistor 550 as a fin type in this manner, the effective channel width is increased, thereby improving the on-state characteristics of the transistor 550. Furthermore, the contribution of the electric field of the gate electrode can be increased, thereby improving the off-state characteristics of the transistor 550.

[0394] Note that the transistor 550 may be either a p-channel transistor or an n-channel transistor.

[0395] The region where the channel of the semiconductor region 313 is formed, the region nearby, the low-resistance region 314a that serves as the source region or the drain region, and the low-resistance region 314b preferably contain a semiconductor such as a silicon-based semiconductor, and preferably contain single crystal silicon. Alternatively, they may be formed of a material containing Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), or the like. A structure using silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may also be used. Alternatively, the transistor 550 may be a HEMT by using GaAs and GaAlAs, or the like.

[0396] The low resistance region 314a and the low resistance region 314b contain, in addition to the semiconductor material applied to the semiconductor region 313, an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron.

[0397] The conductor 316 functioning as the gate electrode can be made of a conductive material such as a semiconductor material such as silicon containing an element that imparts n-type conductivity such as arsenic or phosphorus, or an element that imparts p-type conductivity such as boron, a metal material, an alloy material, or a metal oxide material.

[0398] Since the work function is determined by the material of the conductor, the threshold voltage of the transistor can be adjusted by selecting the material of the conductor. Specifically, it is preferable to use a material such as titanium nitride or tantalum nitride as the conductor. Furthermore, in order to achieve both conductivity and embeddability, it is preferable to use a metal material such as tungsten or aluminum as the conductor in a laminated state, and tungsten is particularly preferable in terms of heat resistance.

[0399] The transistor 550 may be formed using an SOI (Silicon on Insulator) substrate or the like.

[0400] The SOI substrate may be a SIMOX (Separation by Implanted Oxygen) substrate formed by implanting oxygen ions into a mirror-polished wafer and then heating it at a high temperature to form an oxide layer to a certain depth from the surface and eliminate defects that have occurred in the surface layer, or an SOI substrate formed using the Smart Cut method, ELTRAN (registered trademark: Epitaxial Layer Transfer) method, or the like, which cleaves a semiconductor substrate by utilizing the growth of microvoids formed by hydrogen ion implantation through heat treatment. A transistor formed using a single crystal substrate has a single crystal semiconductor in the channel formation region.

[0401] 31 is just an example, and the present invention is not limited to this configuration. An appropriate transistor may be used depending on the circuit configuration and driving method. For example, when the semiconductor device is configured as a unipolar circuit including only OS transistors (meaning transistors with the same polarity, such as only n-channel transistors), the transistor 550 may have the same configuration as the transistor 500, as shown in FIG. 32. The details of the transistor 500 will be described later.

[0402] An insulator 320, an insulator 322, an insulator 324, and an insulator 326 are stacked in this order to cover the transistor 550.

[0403] The insulators 320, 322, 324, and 326 can be formed using, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like.

[0404] In this specification, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen, aluminum oxynitride refers to a material whose composition contains more oxygen than nitrogen, and aluminum nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0405] The insulator 322 may function as a planarizing film that flattens steps caused by the transistor 550 or the like provided thereunder. For example, the top surface of the insulator 322 may be planarized by planarization treatment using a chemical mechanical polishing (CMP) method or the like to improve the planarity.

[0406] The insulator 324 is preferably a film having a barrier property that prevents hydrogen or impurities from diffusing from the substrate 311, the transistor 550, or the like to a region where the transistor 500 is provided.

[0407] An example of a film having a barrier property against hydrogen is silicon nitride formed by a CVD method. Here, hydrogen diffusion into a semiconductor element having an oxide semiconductor, such as the transistor 500, may degrade the characteristics of the semiconductor element. Therefore, it is preferable to use a film that suppresses hydrogen diffusion between the transistor 500 and the transistor 550. Specifically, the film that suppresses hydrogen diffusion is a film that releases a small amount of hydrogen.

[0408] The amount of desorbed hydrogen can be analyzed using, for example, thermal desorption spectroscopy (TDS). For example, the amount of desorbed hydrogen from the insulator 324 is calculated as 10×10 per area of ​​the insulator 324 when the surface temperature of the film is in the range of 50° C. to 500° C. in TDS analysis. 15 atoms / cm 2 Less than or equal to 5 x 10 15 atoms / cm 2 The following is fine.

[0409] It is preferable that the insulator 326 has a lower dielectric constant than the insulator 324. For example, the relative dielectric constant of the insulator 326 is preferably less than 4, and more preferably less than 3. Furthermore, for example, the relative dielectric constant of the insulator 326 is preferably 0.7 times or less, and more preferably 0.6 times or less, the relative dielectric constant of the insulator 324. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance that occurs between wirings can be reduced.

[0410] Furthermore, the insulators 320, 322, 324, and 326 are embedded with the capacitor 600 or the conductors 328 and 330 connected to the transistor 500. The conductors 328 and 330 function as plugs or wiring. Furthermore, for conductors that function as plugs or wiring, the same reference numeral may be used to denote multiple components. Furthermore, in this specification and the like, the wiring and the plug connected to the wiring may be integrated. That is, there are cases where a part of the conductor functions as the wiring, and cases where a part of the conductor functions as the plug.

[0411] The materials for each plug and wiring (conductor 328, conductor 330, etc.) can be a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material, and can be used in a single layer or a stacked layer. It is preferable to use a high-melting-point material such as tungsten or molybdenum, which has both heat resistance and conductivity, and tungsten is preferred. Alternatively, it is preferable to form the wiring from a low-resistance conductive material such as aluminum or copper. Using a low-resistance conductive material can reduce the wiring resistance.

[0412] A wiring layer may be provided over the insulator 326 and the conductor 330. For example, in FIG. 31 , an insulator 350, an insulator 352, and an insulator 354 are stacked in this order. A conductor 356 is formed in the insulator 350, the insulator 352, and the insulator 354. The conductor 356 functions as a plug or wiring connected to the transistor 550. Note that the conductor 356 can be formed using a material similar to that of the conductor 328 and the conductor 330.

[0413] Note that, for example, the insulator 350 preferably uses an insulator having a barrier property against hydrogen, similar to the insulator 324. The conductor 356 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 350 having a barrier property against hydrogen. With this structure, the transistor 550 and the transistor 500 can be separated by a barrier layer, and diffusion of hydrogen from the transistor 550 to the transistor 500 can be suppressed.

[0414] Note that, for example, tantalum nitride or the like is preferably used as a conductor having a barrier property against hydrogen. Stacking tantalum nitride and highly conductive tungsten can suppress diffusion of hydrogen from the transistor 550 while maintaining the conductivity of the wiring. In this case, it is preferable that the tantalum nitride layer having a barrier property against hydrogen be in contact with the insulator 350 having a barrier property against hydrogen.

[0415] A wiring layer may be provided over the insulator 354 and the conductor 356. For example, in FIG. 31 , an insulator 360, an insulator 362, and an insulator 364 are stacked in this order. A conductor 366 is formed in the insulator 360, the insulator 362, and the insulator 364. The conductor 366 functions as a plug or a wiring. The conductor 366 can be formed using a material similar to that of the conductors 328 and 330.

[0416] Note that, for example, the insulator 360 preferably uses an insulator having a barrier property against hydrogen, similar to the insulator 324. The conductor 366 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 360 having a barrier property against hydrogen. With this structure, the transistor 550 and the transistor 500 can be separated by a barrier layer, and diffusion of hydrogen from the transistor 550 to the transistor 500 can be suppressed.

[0417] A wiring layer may be provided over the insulator 364 and the conductor 366. For example, in FIG. 31 , an insulator 370, an insulator 372, and an insulator 374 are stacked in this order. A conductor 376 is formed in the insulator 370, the insulator 372, and the insulator 374. The conductor 376 functions as a plug or a wiring. The conductor 376 can be formed using a material similar to that of the conductors 328 and 330.

[0418] Note that, for example, the insulator 370 preferably uses an insulator having a barrier property against hydrogen, similar to the insulator 324. The conductor 376 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 370 having a barrier property against hydrogen. With this structure, the transistor 550 and the transistor 500 can be separated by a barrier layer, and diffusion of hydrogen from the transistor 550 to the transistor 500 can be suppressed.

[0419] A wiring layer may be provided over the insulator 374 and the conductor 376. For example, in FIG. 31 , an insulator 380, an insulator 382, ​​and an insulator 384 are stacked in this order. A conductor 386 is formed in the insulator 380, the insulator 382, ​​and the insulator 384. The conductor 386 functions as a plug or a wiring. The conductor 386 can be formed using a material similar to that of the conductors 328 and 330.

[0420] Note that, for example, the insulator 380 preferably uses an insulator having a barrier property against hydrogen, similar to the insulator 324. The conductor 386 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 380 having a barrier property against hydrogen. With this structure, the transistor 550 and the transistor 500 can be separated by a barrier layer, and diffusion of hydrogen from the transistor 550 to the transistor 500 can be suppressed.

[0421] In the above, a wiring layer including the conductor 356, a wiring layer including the conductor 366, a wiring layer including the conductor 376, and a wiring layer including the conductor 386 have been described, but the semiconductor device according to this embodiment is not limited to this. There may be three or fewer wiring layers similar to the wiring layer including the conductor 356, or there may be five or more wiring layers similar to the wiring layer including the conductor 356.

[0422] An insulator 510, an insulator 512, an insulator 514, and an insulator 516 are stacked in this order over the insulator 384. Any of the insulator 510, the insulator 512, the insulator 514, and the insulator 516 is preferably formed using a substance that has a barrier property against oxygen and hydrogen.

[0423] For example, the insulator 510 and the insulator 514 are preferably formed using a film having a barrier property against hydrogen and impurities in a region from the substrate 311 or a region where the transistor 550 is provided to a region where the transistor 500 is provided. Therefore, a material similar to that of the insulator 324 can be used.

[0424] An example of a film having a barrier property against hydrogen is silicon nitride formed by a CVD method. Here, hydrogen diffusion into a semiconductor element including an oxide semiconductor, such as the transistor 500, may degrade the characteristics of the semiconductor element. Therefore, a film that suppresses hydrogen diffusion is preferably used between the transistor 500 and the transistor 550.

[0425] As a film having a barrier property against hydrogen, for example, the insulators 510 and 514 are preferably made of a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide.

[0426] In particular, aluminum oxide has a high blocking effect of preventing the permeation of both oxygen and impurities such as hydrogen and moisture, which can cause fluctuations in the electrical characteristics of a transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from entering the transistor 500 during and after the transistor manufacturing process. Furthermore, aluminum oxide can suppress the release of oxygen from the oxide that constitutes the transistor 500. Therefore, aluminum oxide is suitable for use as a protective film for the transistor 500.

[0427] For example, the insulator 512 and the insulator 516 can be formed using a material similar to that of the insulator 320. By using a material with a relatively low dielectric constant for these insulators, parasitic capacitance between wirings can be reduced. For example, the insulators 512 and 516 can be formed using a silicon oxide film, a silicon oxynitride film, or the like.

[0428] A conductor 518, a conductor constituting the transistor 500 (for example, the conductor 503), and the like are embedded in the insulators 510, 512, 514, and 516. The conductor 518 functions as a plug or wiring connected to the capacitor 600 or the transistor 550. The conductor 518 can be formed using a material similar to that of the conductor 328 and the conductor 330.

[0429] In particular, the conductor 518 in the region in contact with the insulator 510 and the insulator 514 is preferably a conductor that has a barrier property against oxygen, hydrogen, and water. With this structure, the transistor 550 and the transistor 500 can be separated by a layer that has a barrier property against oxygen, hydrogen, and water, and diffusion of hydrogen from the transistor 550 to the transistor 500 can be suppressed.

[0430] Above the insulator 516 is the transistor 500 .

[0431] As shown in Figures 33A and 33B, transistor 500 has a conductor 503 arranged so as to be embedded in insulator 514 and insulator 516, an insulator 520 arranged on insulator 516 and conductor 503, an insulator 522 arranged on insulator 520, an insulator 524 arranged on insulator 522, an oxide 530a arranged on insulator 524, an oxide 530b arranged on oxide 530a, conductors 542a and 542b arranged apart from each other on oxide 530b, an insulator 580 arranged on conductors 542a and 542b and having an opening formed therein overlapping with conductors 542a and 542b, an insulator 545 arranged on the bottom and side surfaces of the opening, and a conductor 560 arranged on the surface on which insulator 545 is formed.

[0432] 33A and 33B, it is preferable that insulator 544 be disposed between oxide 530a, oxide 530b, conductor 542a, and conductor 542b and insulator 580. It is preferable that conductor 560 have conductor 560a provided inside insulator 545 and conductor 560b provided so as to be embedded inside conductor 560a. It is preferable that insulator 574 be disposed on insulator 580, conductor 560, and insulator 545, as shown in FIGS.

[0433] In this specification and the like, the oxide 530a and the oxide 530b may be collectively referred to as the oxide 530.

[0434] Note that although the transistor 500 has a structure in which two layers of the oxide 530a and the oxide 530b are stacked in and around a channel formation region, the present invention is not limited to this. For example, a single layer of the oxide 530b or a stacked structure of three or more layers may be used.

[0435] Although the transistor 500 has a two-layer structure in which the conductor 560 is stacked, the present invention is not limited to this. For example, the conductor 560 may have a single-layer structure or a stacked structure of three or more layers. The transistor 500 illustrated in FIGS. 31, 32, and 33A is merely an example and is not limited to this structure. An appropriate transistor may be used depending on the circuit configuration, driving method, and the like.

[0436] Here, the conductor 560 functions as the gate electrode of the transistor, and the conductors 542a and 542b function as the source and drain electrodes, respectively. As described above, the conductor 560 is formed so as to be embedded in the opening of the insulator 580 and in the region sandwiched between the conductors 542a and 542b. The arrangements of the conductors 560, 542a, and 542b are selected in a self-aligned manner with respect to the opening of the insulator 580. That is, in the transistor 500, the gate electrode can be positioned between the source and drain electrodes in a self-aligned manner. Therefore, the conductor 560 can be formed without providing an alignment margin, thereby reducing the area occupied by the transistor 500. This allows for miniaturization and high integration of semiconductor devices.

[0437] Furthermore, since the conductor 560 is formed in a self-aligned manner in the region between the conductor 542a and the conductor 542b, the conductor 560 does not have a region that overlaps with the conductor 542a or the conductor 542b. This reduces the parasitic capacitance formed between the conductor 560 and the conductor 542a and between the conductor 560 and the conductor 542b. This improves the switching speed of the transistor 500, thereby improving the frequency characteristics of the transistor 500.

[0438] The conductor 560 may function as a first gate (also referred to as a top gate) electrode. The conductor 503 may function as a second gate (also referred to as a bottom gate) electrode. In this case, the threshold voltage of the transistor 500 can be controlled by changing the potential applied to the conductor 503 independently of the potential applied to the conductor 560. In particular, applying a negative potential to the conductor 503 can increase the threshold voltage of the transistor 500 and reduce the off-state current. Therefore, applying a negative potential to the conductor 503 can reduce the drain current when the potential applied to the conductor 560 is 0 V compared to not applying a negative potential to the conductor 503.

[0439] The conductor 503 is arranged to overlap the oxide 530 and the conductor 560. In this way, when a potential is applied to the conductor 560 and the conductor 503, the electric field generated from the conductor 560 and the electric field generated from the conductor 503 are connected, and a channel formation region formed in the oxide 530 can be covered.

[0440] In this specification and the like, a transistor configuration in which a channel formation region is electrically surrounded by the electric field of a pair of gate electrodes (a first gate electrode and a second gate electrode) is referred to as a surrounded channel (s-channel) configuration. The s-channel configuration disclosed in this specification and the like differs from the fin type configuration and the planar type configuration. The adoption of the s-channel configuration increases resistance to the short channel effect, in other words, makes it possible to provide a transistor in which the short channel effect is less likely to occur.

[0441] The conductor 503 has a structure similar to that of the conductor 518, in which the conductor 503a is formed in contact with the inner walls of the openings of the insulators 514 and 516, and the conductor 503b is formed further inward. Note that although the transistor 500 has a structure in which the conductors 503a and 503b are stacked, the present invention is not limited to this. For example, the conductor 503 may have a single layer structure or a stacked structure of three or more layers.

[0442] Here, the conductor 503a is preferably made of a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, copper atoms, etc. (the impurities are less likely to permeate). Alternatively, it is preferably made of a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) (the oxygen is less likely to permeate). In this specification, the function of suppressing the diffusion of impurities or oxygen refers to the function of suppressing the diffusion of any one or all of the impurities or oxygen.

[0443] For example, the conductor 503a has a function of suppressing the diffusion of oxygen, so that the conductor 503b can be prevented from being oxidized and its conductivity from decreasing.

[0444] Furthermore, when the conductor 503 also functions as a wiring, it is preferable that the conductor 503b be made of a highly conductive material containing tungsten, copper, or aluminum as a main component. Note that, although the conductor 503 is illustrated in this embodiment as a stack of the conductors 503a and 503b, the conductor 503 may have a single-layer structure.

[0445] The insulators 520, 522, and 524 function as a second gate insulating film.

[0446] Here, the insulator 524 in contact with the oxide 530 preferably contains more oxygen than the oxygen required for the stoichiometric composition. The oxygen is easily released from the film by heating. In this specification and the like, oxygen released by heating may be referred to as "excess oxygen." In other words, the insulator 524 preferably has a region containing excess oxygen (also referred to as an "excess oxygen region"). By providing such an insulator containing excess oxygen in contact with the oxide 530, oxygen vacancies (V O When hydrogen enters the oxygen vacancy in the oxide 530, the defect (hereinafter referred to as V O H.) functions as a donor and may generate electrons as carriers. In addition, some of the hydrogen may bond with oxygen that is bonded to a metal atom to generate electrons as carriers. Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen is likely to have normally-on characteristics. Furthermore, hydrogen in an oxide semiconductor is easily moved by stress such as heat or an electric field. Therefore, if an oxide semiconductor contains a large amount of hydrogen, the reliability of the transistor may be reduced. In one embodiment of the present invention, V in the oxide 530 O It is preferable to reduce H as much as possible to obtain high-purity intrinsic or substantially high-purity intrinsic V.O To obtain an oxide semiconductor with sufficiently reduced H, it is important to remove impurities such as moisture and hydrogen from the oxide semiconductor (also called "dehydration" or "dehydrogenation treatment") and to supply oxygen to the oxide semiconductor to compensate for oxygen vacancies (also called "oxygenation treatment"). O When an oxide semiconductor in which H is sufficiently reduced is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0447] Specifically, it is preferable to use an oxide material from which some oxygen is released by heating as an insulator having an excess oxygen region. An oxide from which oxygen is released by heating is an oxide from which the amount of released oxygen converted to oxygen atoms is 1.0 × 10 in TDS analysis. 18 atoms / cm 3 or more, preferably 1.0 × 10 19 atoms / cm 3 More preferably, 2.0 × 10 19 atoms / cm 3 or more, or 3.0 x 10 20 atoms / cm 3 The oxide film is one having the above properties. The surface temperature of the film during the TDS analysis is preferably in the range of 100°C or higher and 700°C or lower, or 100°C or higher and 400°C or lower.

[0448] Furthermore, the oxide 530 may be brought into contact with the insulator having the excess oxygen region and subjected to one or more of heat treatment, microwave treatment, and RF treatment. By performing such treatment, water or hydrogen in the oxide 530 can be removed. For example, a reaction occurs in the oxide 530 that breaks the VOH bond, in other words, "V O The reaction "H → Vo + H" occurs, resulting in dehydrogenation. Some of the generated hydrogen may combine with oxygen to form HO, which may be removed from the oxide 530 or an insulator near the oxide 530. Some of the hydrogen may also be gettered to the conductor 542a or the conductor 542b.

[0449] The microwave treatment is preferably performed using, for example, an apparatus having a power source for generating high-density plasma or an apparatus having a power source for applying RF to the substrate side. For example, high-density oxygen radicals can be generated by using an oxygen-containing gas and high-density plasma, and the oxygen radicals generated by the high-density plasma can be efficiently introduced into the oxide 530 or an insulator near the oxide 530 by applying RF to the substrate side. The microwave treatment is performed at a pressure of 133 Pa or higher, preferably 200 Pa or higher, and more preferably 400 Pa or higher. The gases introduced into the microwave treatment apparatus may be, for example, oxygen and argon, with an oxygen flow ratio (O2 / (O2+Ar)) of 50% or lower, preferably 10% to 30%.

[0450] During the manufacturing process of the transistor 500, heat treatment is preferably performed with the surface of the oxide 530 exposed. The heat treatment may be performed, for example, at a temperature of 100° C. to 450° C., more preferably 350° C. to 400° C. Note that the heat treatment is performed in a nitrogen gas or inert gas atmosphere, or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. For example, the heat treatment is preferably performed in an oxygen atmosphere. This supplies oxygen to the oxide 530, thereby eliminating oxygen vacancies (V O ) can be reduced. The heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas after the heat treatment in a nitrogen gas or inert gas atmosphere to compensate for the desorbed oxygen. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas, and then the heat treatment may be performed in a nitrogen gas or inert gas atmosphere.

[0451] By subjecting the oxide 530 to oxygen addition treatment, the oxygen vacancies in the oxide 530 can be repaired by the supplied oxygen, in other words, the reaction "Vo + O → null" can be promoted. Furthermore, the supplied oxygen reacts with the hydrogen remaining in the oxide 530, and the hydrogen can be removed as H2O (dehydration). As a result, the hydrogen remaining in the oxide 530 recombines with the oxygen vacancies to form V O The formation of H can be suppressed.

[0452] When the insulator 524 has an excess oxygen region, the insulator 522 preferably has a function of suppressing the diffusion of oxygen (for example, oxygen atoms, oxygen molecules, etc.) (preferably making the oxygen less permeable).

[0453] The insulator 522 preferably has a function of suppressing diffusion of oxygen and impurities, which prevents oxygen contained in the oxide 530 from diffusing toward the insulator 520. Furthermore, reaction of the conductor 503 with oxygen contained in the insulator 524 or the oxide 530 can be suppressed.

[0454] The insulator 522 is preferably a single-layer or multi-layer insulator containing a high-k material, such as aluminum oxide, hafnium oxide, oxide containing aluminum and hafnium (hafnium aluminate), tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST). As transistors become smaller and more highly integrated, thinner gate insulating films can cause problems such as leakage current. Using a high-k material for the insulator that functions as the gate insulating film makes it possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

[0455] In particular, an insulator containing an oxide of one or both of aluminum and hafnium, which is an insulating material that has the function of suppressing the diffusion of impurities and oxygen (i.e., is difficult for oxygen to permeate), is preferably used. As an insulator containing an oxide of one or both of aluminum and hafnium, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used. When the insulator 522 is formed using such a material, the insulator 522 functions as a layer that suppresses oxygen release from the oxide 530 and the intrusion of impurities such as hydrogen into the oxide 530 from the periphery of the transistor 500.

[0456] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked on the above insulators.

[0457] Furthermore, it is preferable that the insulator 520 be thermally stable. For example, silicon oxide and silicon oxynitride are suitable because they are thermally stable. Furthermore, by combining a high-k insulator with silicon oxide or silicon oxynitride, it is possible to obtain the insulator 520 having a thermally stable layered structure with a high dielectric constant.

[0458] 33A and 33B illustrates the second gate insulating film having a three-layer structure including the insulators 520, 522, and 524, but the second gate insulating film may have a single-layer, two-layer, or four or more-layer structure. In this case, the second gate insulating film is not limited to a stack structure made of the same material and may have a stack structure made of different materials.

[0459] The transistor 500 uses a metal oxide functioning as an oxide semiconductor for the oxide 530 including the channel formation region. For example, a metal oxide such as In-M-Zn oxide (wherein M is one or more elements selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, tin, magnesium, or the like) can be used as the oxide 530.

[0460] The metal oxide functioning as an oxide semiconductor may be formed by a sputtering method or an ALD (Atomic Layer Deposition) method. Note that the metal oxide functioning as an oxide semiconductor will be described in detail in other embodiments.

[0461] The metal oxide that functions as a channel formation region in the oxide 530 preferably has a band gap of 2 eV or more, preferably 2.5 eV or more. By using a metal oxide with a wide band gap, the off-state current of the transistor can be reduced.

[0462] The oxide 530 has the oxide 530a below the oxide 530b, and thus can suppress the diffusion of impurities from components formed below the oxide 530a to the oxide 530b.

[0463] Note that oxide 530 preferably has a stacked structure of multiple oxide layers with different atomic ratios of each metal atom. Specifically, the atomic ratio of element M among the constituent elements in the metal oxide used for oxide 530a is preferably greater than the atomic ratio of element M among the constituent elements in the metal oxide used for oxide 530b. Furthermore, the atomic ratio of element M to In in the metal oxide used for oxide 530a is preferably greater than the atomic ratio of element M to In in the metal oxide used for oxide 530b. Furthermore, the atomic ratio of In to element M in the metal oxide used for oxide 530b is preferably greater than the atomic ratio of In to element M in the metal oxide used for oxide 530a.

[0464] The energy of the conduction band minimum of the oxide 530a is preferably higher than that of the oxide 530b, or in other words, the electron affinity of the oxide 530a is preferably smaller than that of the oxide 530b.

[0465] Here, the energy level of the conduction band minimum changes gradually at the junction between the oxide 530a and the oxide 530b. In other words, the energy level of the conduction band minimum at the junction between the oxide 530a and the oxide 530b changes continuously or forms a continuous junction. To achieve this, it is preferable to reduce the defect level density of the mixed layer formed at the interface between the oxide 530a and the oxide 530b.

[0466] Specifically, when the oxide 530a and the oxide 530b have a common element (main component) other than oxygen, a mixed layer with a low density of defect states can be formed. For example, when the oxide 530b is an In-Ga-Zn oxide, the oxide 530a may be an In-Ga-Zn oxide, a Ga-Zn oxide, a gallium oxide, or the like.

[0467] In this case, the oxide 530b serves as the main carrier path. By configuring the oxide 530a as described above, the defect state density at the interface between the oxide 530a and the oxide 530b can be reduced. As a result, the influence of interface scattering on carrier conduction is reduced, and the transistor 500 can obtain a high on-state current.

[0468] Conductors 542a and 542b, which function as a source electrode and a drain electrode, are provided on oxide 530b. Conductors 542a and 542b are preferably made of a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, or an alloy containing any of the above metal elements or an alloy combining any of the above metal elements. For example, tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel is preferably used. In addition, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or materials that maintain conductivity even when absorbing oxygen.Furthermore, metal nitride films such as tantalum nitride are preferred because they have barrier properties against hydrogen or oxygen.

[0469] 33A shows the conductor 542a and the conductor 542b as a single layer, they may also be stacked with two or more layers. For example, a tantalum nitride film and a tungsten film may be stacked. Alternatively, a titanium film and an aluminum film may be stacked. Alternatively, a two-layer structure in which an aluminum film is stacked on a tungsten film, a two-layer structure in which a copper film is stacked on a copper-magnesium-aluminum alloy film, a two-layer structure in which a copper film is stacked on a titanium film, or a two-layer structure in which a copper film is stacked on a tungsten film may also be used.

[0470] Further, there are three-layer structures in which a titanium film or titanium nitride film is laminated on the titanium film or titanium nitride film, an aluminum film or copper film is laminated on the titanium film or titanium nitride film, and a titanium film or titanium nitride film is further formed thereon, a three-layer structure in which a molybdenum film or molybdenum nitride film is laminated on the molybdenum film or molybdenum nitride film, an aluminum film or copper film is laminated on the molybdenum film or molybdenum nitride film, and a molybdenum film or molybdenum nitride film is further formed thereon, etc. Note that a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may also be used.

[0471] 33A, regions 543a and 543b may be formed as low-resistance regions at and near the interface of the oxide 530 with the conductor 542a (conductor 542b). In this case, the region 543a functions as one of the source region and the drain region, and the region 543b functions as the other of the source region and the drain region. A channel formation region is formed in the region sandwiched between the regions 543a and 543b.

[0472] By providing the conductor 542a (conductor 542b) so as to be in contact with the oxide 530, the oxygen concentration in the region 543a (region 543b) may be reduced. Also, a metal compound layer containing the metal contained in the conductor 542a (conductor 542b) and components of the oxide 530 may be formed in the region 543a (region 543b). In such a case, the carrier density in the region 543a (region 543b) increases, and the region 543a (region 543b) becomes a low-resistance region.

[0473] The insulator 544 is provided to cover the conductors 542a and 542b and suppresses oxidation of the conductors 542a and 542b. In this case, the insulator 544 may be provided to cover the side surface of the oxide 530 and to be in contact with the insulator 524.

[0474] The insulator 544 can be a metal oxide containing one or more elements selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, neodymium, lanthanum, magnesium, etc. Alternatively, the insulator 544 can be silicon nitride oxide, silicon nitride, or the like.

[0475] In particular, it is preferable to use, as the insulator 544, an insulator containing an oxide of either or both of aluminum and hafnium, such as aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate). Hafnium aluminate is particularly preferable because it has higher heat resistance than a hafnium oxide film. Therefore, it is less likely to crystallize during heat treatment in a later step. Note that the insulator 544 is not an essential component if the conductors 542a and 542b are made of oxidation-resistant materials or if their conductivity does not decrease significantly even when they absorb oxygen. The insulator 544 may be designed appropriately depending on the desired transistor characteristics.

[0476] The insulator 544 can prevent impurities such as water and hydrogen contained in the insulator 580 from diffusing into the oxide 530b through the insulator 545. Furthermore, the conductor 560 can be prevented from being oxidized by excess oxygen contained in the insulator 580.

[0477] The insulator 545 functions as a first gate insulating film. Like the insulator 524, the insulator 545 is preferably formed using an insulator that contains excess oxygen and releases oxygen by heating.

[0478] Specifically, silicon oxide having excess oxygen, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, and silicon oxide having vacancies can be used. In particular, silicon oxide and silicon oxynitride are preferable because they are stable against heat.

[0479] By using an insulator containing excess oxygen as the insulator 545, oxygen can be effectively supplied from the insulator 545 to the channel formation region of the oxide 530b. Similarly to the insulator 524, the concentration of impurities such as water or hydrogen in the insulator 545 is preferably reduced. The thickness of the insulator 545 is preferably 1 nm to 20 nm.

[0480] Furthermore, a metal oxide may be provided between the insulator 545 and the conductor 560 to efficiently supply excess oxygen contained in the insulator 545 to the oxide 530. The metal oxide preferably suppresses oxygen diffusion from the insulator 545 to the conductor 560. By providing a metal oxide that suppresses oxygen diffusion, the diffusion of excess oxygen from the insulator 545 to the conductor 560 is suppressed. That is, a decrease in the amount of excess oxygen supplied to the oxide 530 can be suppressed. Furthermore, oxidation of the conductor 560 due to excess oxygen can be suppressed. As the metal oxide, any material that can be used for the insulator 544 may be used.

[0481] Note that the insulator 545 may have a layered structure, similar to the second gate insulating film. As transistors become smaller and more highly integrated, thinner gate insulating films can cause problems such as leakage current. Therefore, by using a layered structure of a high-k material and a thermally stable material for the insulator that functions as the gate insulating film, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness. Furthermore, a layered structure that is thermally stable and has a high dielectric constant can be achieved.

[0482] The conductor 560 functioning as the first gate electrode is shown as having a two-layer structure in FIGS. 33A and 33B, but may have a single-layer structure or a stacked structure of three or more layers.

[0483] The conductor 560a is preferably made of a conductive material that suppresses the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (NO, NO, NO, etc.), and copper atoms. Alternatively, a conductive material that suppresses the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.) is preferably used. The conductor 560a has the function of suppressing the diffusion of oxygen, which can suppress the oxidation of the conductor 560b due to oxygen contained in the insulator 545 and a decrease in conductivity. Examples of conductive materials that suppress the diffusion of oxygen include tantalum, tantalum nitride, ruthenium, and ruthenium oxide. Alternatively, the conductor 560a can be made of an oxide semiconductor that can be used for the oxide 530. In this case, the conductor 560b can be formed by sputtering to reduce the electrical resistance of the conductor 560a, thereby making it a conductor. This can be called an OC (Oxide Conductor) electrode.

[0484] The conductor 560b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. Since the conductor 560b also functions as wiring, it is preferable to use a conductor with high conductivity. For example, a conductive material containing tungsten, copper, or aluminum as a main component can be used. The conductor 560b may have a layered structure, such as a layered structure of titanium or titanium nitride and the above-mentioned conductive material.

[0485] The insulator 580 is provided over the conductor 542a and the conductor 542b with the insulator 544 interposed therebetween. The insulator 580 preferably has an excess oxygen region. For example, the insulator 580 preferably includes silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, silicon oxide having voids, or a resin. Silicon oxide and silicon oxynitride are particularly preferred because they are thermally stable. Silicon oxide and silicon oxide having voids are particularly preferred because they allow for easy formation of excess oxygen regions in a later step.

[0486] The insulator 580 preferably has an excess oxygen region. By providing the insulator 580 from which oxygen is released by heating, oxygen in the insulator 580 can be efficiently supplied to the oxide 530. Note that the concentration of impurities such as water or hydrogen in the insulator 580 is preferably reduced.

[0487] The opening of the insulator 580 is formed to overlap the region between the conductor 542a and the conductor 542b, so that the conductor 560 is formed to be embedded in the opening of the insulator 580 and the region sandwiched between the conductor 542a and the conductor 542b.

[0488] When miniaturizing semiconductor devices, it is necessary to shorten the gate length, but it is also necessary to prevent the conductivity of the conductor 560 from decreasing. If the film thickness of the conductor 560 is increased to achieve this, the conductor 560 may have a shape with a high aspect ratio. In this embodiment, the conductor 560 is provided so as to be embedded in the opening of the insulator 580. Therefore, even if the conductor 560 has a shape with a high aspect ratio, the conductor 560 can be formed without collapsing during the process.

[0489] The insulator 574 is preferably provided in contact with the top surface of the insulator 580, the top surface of the conductor 560, and the top surface of the insulator 545. By forming the insulator 574 by a sputtering method, excess oxygen regions can be provided in the insulator 545 and the insulator 580. This allows oxygen to be supplied from the excess oxygen regions to the oxide 530.

[0490] For example, the insulator 574 can be a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, and the like.

[0491] In particular, aluminum oxide has high barrier properties and can suppress the diffusion of hydrogen and nitrogen even when it is a thin film with a thickness of 0.5 nm to 3.0 nm. Therefore, aluminum oxide formed by sputtering can function as both an oxygen source and a barrier film against impurities such as hydrogen.

[0492] An insulator 581 functioning as an interlayer film is preferably provided over the insulator 574. Like the insulator 524 and the like, the insulator 581 preferably has a reduced concentration of impurities such as water or hydrogen.

[0493] Furthermore, the conductor 540a and the conductor 540b are placed in openings formed in the insulator 581, the insulator 574, the insulator 580, and the insulator 544. The conductor 540a and the conductor 540b are provided opposite each other with the conductor 560 interposed therebetween. The conductor 540a and the conductor 540b have the same structure as the conductor 546 and the conductor 548, which will be described later.

[0494] An insulator 582 is provided over the insulator 581. The insulator 582 is preferably formed using a substance that has a barrier property against oxygen and hydrogen. Therefore, the insulator 582 can be formed using a material similar to that of the insulator 514. For example, the insulator 582 is preferably formed using a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide.

[0495] In particular, aluminum oxide has a high blocking effect of preventing the permeation of both oxygen and impurities such as hydrogen and moisture, which can cause fluctuations in the electrical characteristics of a transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from entering the transistor 500 during and after the transistor manufacturing process. Furthermore, aluminum oxide can suppress the release of oxygen from the oxide that constitutes the transistor 500. Therefore, aluminum oxide is suitable for use as a protective film for the transistor 500.

[0496] An insulator 586 is provided over the insulator 582. The insulator 586 can be formed using a material similar to that of the insulator 320. By using a material with a relatively low dielectric constant for these insulators, parasitic capacitance between wirings can be reduced. For example, a silicon oxide film, a silicon oxynitride film, or the like can be used as the insulator 586.

[0497] Furthermore, conductors 546, conductors 548, etc. are embedded in insulators 520, 522, 524, 544, 580, 574, 581, 582, and 586.

[0498] The conductor 546 and the conductor 548 function as plugs or wirings that connect to the capacitor 600, the transistor 500, or the transistor 550. The conductor 546 and the conductor 548 can be formed using the same materials as the conductor 328 and the conductor 330.

[0499] After the transistor 500 is formed, an opening may be formed to surround the transistor 500, and an insulator with high barrier properties against hydrogen or water may be formed to cover the opening. By surrounding the transistor 500 with the insulator with high barrier properties, it is possible to prevent moisture and hydrogen from entering from the outside. Alternatively, multiple transistors 500 may be collectively surrounded by an insulator with high barrier properties against hydrogen or water. When forming an opening to surround the transistor 500, for example, it is preferable to form an opening that reaches the insulator 522 or the insulator 514 and form the insulator with high barrier properties in contact with the insulator 522 or the insulator 514, because this can serve as part of the manufacturing process of the transistor 500. For example, the insulator with high barrier properties against hydrogen or water may be made of a material similar to that of the insulator 522 or the insulator 514.

[0500] Subsequently, a capacitor 600 is provided above the transistor 500. The capacitor 600 has a conductor 610, a conductor 620, and an insulator 630.

[0501] A conductor 612 may be provided over the conductor 546 and the conductor 548. The conductor 612 functions as a plug or a wiring connected to the transistor 500. The conductor 610 functions as an electrode of the capacitor 600. Note that the conductor 612 and the conductor 610 can be formed at the same time.

[0502] A metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium, or a metal nitride film containing any of the above elements (tantalum nitride film, titanium nitride film, molybdenum nitride film, tungsten nitride film), or the like can be used for the conductor 612 and the conductor 610. Alternatively, a conductive material such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide to which silicon oxide is added can also be used.

[0503] In this embodiment, the conductor 612 and the conductor 610 have a single-layer structure, but the present invention is not limited to this structure and may have a stacked structure of two or more layers. For example, a conductor having a barrier property and a conductor having high adhesion to the conductor having high conductivity may be formed between a conductor having a barrier property and a conductor having high conductivity.

[0504] The conductor 620 is provided so as to overlap with the conductor 610 with the insulator 630 interposed therebetween. Note that the conductor 620 can be formed using a conductive material such as a metal material, an alloy material, or a metal oxide material. It is preferable to use a high-melting-point material such as tungsten or molybdenum that has both heat resistance and conductivity, and tungsten is particularly preferable. Furthermore, when the conductor 620 is formed simultaneously with other components such as a conductor, a low-resistance metal material such as Cu (copper) or Al (aluminum) can be used.

[0505] An insulator 640 is provided over the conductor 620 and the insulator 630. The insulator 640 can be provided using a material similar to that of the insulator 320. The insulator 640 may also function as a planarizing film that covers the uneven shape underneath.

[0506] With this structure, miniaturization or high integration can be achieved in a semiconductor device including a transistor including an oxide semiconductor.

[0507] 33A and 33B can be applied to the transistors included in the pixel 12 described in Embodiment 1. As described above, the transistors with the structures shown in FIGS. 33A and 33B occupy a small area. Therefore, the pixel 12 can have high definition, and the pixel density of the display device 10 can be increased. For example, by using the structure shown in FIG. 2A or 2B for the display device 10 and applying the structures shown in FIGS. 33A and 33B to all of the transistors included in the pixel 12, the pixel density of the display device 10 can be increased to 1000 ppi or more, 3000 ppi or more, or 5000 ppi or more.

[0508] Examples of a substrate that can be used for the semiconductor device of one embodiment of the present invention include a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, a metal substrate (e.g., a stainless steel substrate, a substrate having stainless steel foil, a tungsten substrate, a substrate having tungsten foil, etc.), a semiconductor substrate (e.g., a single crystal semiconductor substrate, a polycrystalline semiconductor substrate, or a compound semiconductor substrate), an SOI (Silicon on Insulator) substrate, and the like. A plastic substrate having heat resistance that can withstand the processing temperature of this embodiment may also be used. Examples of glass substrates include barium borosilicate glass, aluminosilicate glass, aluminoborosilicate glass, and soda-lime glass. Alternatively, crystallized glass or the like can be used.

[0509] Alternatively, a flexible substrate, a laminated film, paper containing a fibrous material, a base film, or the like can be used as the substrate. Examples of flexible substrates, laminated films, base films, and the like include the following: Plastics, such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), and polytetrafluoroethylene (PTFE). Synthetic resins, such as acrylic resins, are also available. Other examples include polypropylene, polyester, polyvinyl fluoride, and polyvinyl chloride. Other examples include polyamide, polyimide, aramid resin, epoxy resin, inorganic vapor-deposited film, and paper. In particular, by manufacturing transistors using semiconductor substrates, single-crystal substrates, SOI substrates, and the like, transistors with small size, high current capacity, and little variation in characteristics, size, and shape can be manufactured. Constructing a circuit using such transistors can reduce the power consumption of the circuit or increase the circuit integration.

[0510] Alternatively, a flexible substrate may be used as the substrate, and transistors, resistors, and / or capacitors may be formed directly on the flexible substrate. Alternatively, a release layer may be provided between the substrate and the transistors, resistors, and / or capacitors. The release layer can be used to separate a semiconductor device, after a part or all of the semiconductor device is completed thereon, from the substrate and transfer it to another substrate. In this case, the transistors, resistors, and / or capacitors can be transferred to a substrate with poor heat resistance or a flexible substrate. Note that the release layer may be, for example, a laminated structure of an inorganic film such as a tungsten film and a silicon oxide film, a structure in which an organic resin film such as polyimide is formed on a substrate, or a silicon film containing hydrogen.

[0511] That is, the semiconductor device may be formed on a certain substrate and then transferred to another substrate. Examples of substrates onto which the semiconductor device may be transferred include, in addition to the substrates on which the above-mentioned transistors can be formed, paper substrates, cellophane substrates, aramid film substrates, polyimide film substrates, stone substrates, wood substrates, cloth substrates (including natural fibers (silk, cotton, linen), synthetic fibers (nylon, polyurethane, polyester), or recycled fibers (acetate, cupra, rayon, recycled polyester)), leather substrates, rubber substrates, etc. By using these substrates, it is possible to manufacture semiconductor devices that are flexible, durable, heat-resistant, lightweight, or thin.

[0512] By providing a semiconductor device over a flexible substrate, an increase in weight can be suppressed and a semiconductor device that is less likely to be damaged can be provided.

[0513] <Transistor variation 1> A transistor 500A illustrated in Figures 34A, 34B, and 34C is a variation of the transistor 500 having the structure illustrated in Figures 33A and 33B. Figure 34A is a top view of the transistor 500A, Figure 34B is a cross-sectional view of the transistor 500A in the channel length direction, and Figure 34C is a cross-sectional view of the transistor 500A in the channel width direction. Note that some elements are omitted from the top view in Figure 34A for clarity. The structures illustrated in Figures 34A, 34B, and 34C can also be applied to other transistors, such as the transistor 550, included in the semiconductor device of one embodiment of the present invention.

[0514] 34A, 34B, and 34C differs from the transistor 500 shown in FIGS. 33A and 33B in that the transistor 500A includes an insulator 552, an insulator 513, and an insulator 404. The transistor 500A also differs from the transistor 500 shown in FIGS. 33A and 33B in that the insulator 552 is provided in contact with the side surface of the conductor 540a and the insulator 552 is provided in contact with the side surface of the conductor 540b. The transistor 500A also differs from the transistor 500 shown in FIGS. 33A and 33B in that the insulator 520 is not provided.

[0515] 34A, 34B, and 34C, the insulator 513 is provided over the insulator 512. The insulator 404 is provided over the insulator 574 and the insulator 513.

[0516] 34A, 34B, and 34C, the insulators 514, 516, 522, 524, 544, 580, and 574 are patterned, and the insulator 404 covers them. That is, the insulator 404 is in contact with the top surface of the insulator 574, the side surface of the insulator 574, the side surface of the insulator 580, the side surface of the insulator 544, the side surface of the insulator 524, the side surface of the insulator 522, the side surface of the insulator 516, the side surface of the insulator 514, and the top surface of the insulator 513. As a result, the oxide 530 and the like are isolated from the outside by the insulators 404 and 513.

[0517] The insulators 513 and 404 preferably have a high function of suppressing diffusion of hydrogen (for example, at least one of hydrogen atoms, hydrogen molecules, and the like) or water molecules. For example, silicon nitride or silicon nitride oxide, which are materials with high hydrogen barrier properties, are preferably used for the insulators 513 and 404. This can suppress diffusion of hydrogen and the like into the oxide 530, thereby suppressing deterioration in the characteristics of the transistor 500A. Therefore, the reliability of the semiconductor device of one embodiment of the present invention can be improved.

[0518] The insulator 552 is provided in contact with the insulator 581, the insulator 404, the insulator 574, the insulator 580, and the insulator 544. The insulator 552 preferably has a function of suppressing diffusion of hydrogen or water molecules. For example, the insulator 552 is preferably formed using an insulator with high hydrogen barrier properties, such as silicon nitride, aluminum oxide, or silicon nitride oxide. Silicon nitride is particularly suitable for use as the insulator 552 because it has high hydrogen barrier properties. Using a material with high hydrogen barrier properties for the insulator 552 can suppress diffusion of impurities such as water or hydrogen from the insulator 580 or the like to the oxide 530 through the conductors 540a and 540b. Furthermore, oxygen contained in the insulator 580 can be prevented from being absorbed by the conductors 540a and 540b. Thus, the reliability of the semiconductor device of one embodiment of the present invention can be improved.

[0519] <Transistor variation 2> An example configuration of a transistor 500B will be described using Figures 35A, 35B, and 35C. Figure 35A is a top view of the transistor 500B. Figure 35B is a cross-sectional view of the L1-L2 portion indicated by the dashed dotted line in Figure 35A. Figure 35C is a cross-sectional view of the W1-W2 portion indicated by the dashed dotted line in Figure 35A. Note that in the top view of Figure 35A, some elements are omitted for clarity.

[0520] The transistor 500B is a modified example of the transistor 500 and can be substituted for the transistor 500. Therefore, to avoid repetition of the description, the differences between the transistor 500B and the transistor 500 will be mainly described.

[0521] The conductor 560 functioning as the first gate electrode includes a conductor 560a and a conductor 560b on the conductor 560a. The conductor 560a is preferably made of a conductive material that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms. Alternatively, the conductor 560a is preferably made of a conductive material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, and the like).

[0522] The conductor 560a has the function of suppressing oxygen diffusion, which improves the material selectivity of the conductor 560b. That is, the presence of the conductor 560a suppresses oxidation of the conductor 560b, thereby preventing a decrease in conductivity.

[0523] Furthermore, it is preferable to provide an insulator 544 so as to cover the top surface and side surfaces of the conductor 560 and the side surfaces of the insulator 545. Note that the insulator 544 is preferably made of an insulating material that has a function of suppressing the diffusion of impurities such as water or hydrogen and oxygen. For example, it is preferable to use aluminum oxide or hafnium oxide. Other examples that can be used include metal oxides such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, and tantalum oxide, silicon nitride oxide, and silicon nitride.

[0524] Providing the insulator 544 can suppress oxidation of the conductor 560. Furthermore, including the insulator 544 can suppress diffusion of impurities such as water and hydrogen contained in the insulator 580 into the transistor 500B.

[0525] The transistor 500B tends to have larger parasitic capacitance than the transistor 500 because the conductor 560 overlaps with part of the conductor 542a and part of the conductor 542b. Therefore, the operating frequency of the transistor 500B tends to be lower than that of the transistor 500. However, the transistor 500B has higher productivity than the transistor 500 because it does not require a step of forming an opening in the insulator 580 or the like and filling it with the conductor 560, the insulator 545, or the like.

[0526] The configurations, structures, methods, and the like described in this embodiment can be used in appropriate combination with the configurations, structures, methods, and the like described in other embodiment modes and examples.

[0527] (Fourth embodiment) In this embodiment, an oxide semiconductor, which is a type of metal oxide, will be described.

[0528] The metal oxide preferably contains at least indium or zinc. It is particularly preferable that it contains indium and zinc. In addition to these, it is preferable that it contains aluminum, gallium, yttrium, tin, etc. It may also contain one or more elements selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, etc.

[0529] <Classification of crystal structures> First, classification of crystal structures in oxide semiconductors will be described with reference to Fig. 36A, which is a diagram for explaining classification of crystal structures of oxide semiconductors, typically IGZO (a metal oxide containing In, Ga, and Zn).

[0530] As shown in FIG. 36A, oxide semiconductors are broadly classified into "amorphous," "crystalline," and "crystal." "Amorphous" includes completely amorphous. "Crystalline" includes c-axis-aligned crystalline (CAAC), nanocrystalline (nc), and cloud-aligned composite (CAC). The "Crystalline" classification excludes single crystal, polycrystal, and completely amorphous. "Crystalline" includes single crystal and polycrystal.

[0531] The structure within the bold frame in Figure 36A is an intermediate state between "Amorphous" and "Crystal" and belongs to a new boundary region (New crystalline phase). In other words, this structure can be described as a structure that is completely different from the energetically unstable "Amorphous" and "Crystal."

[0532] The crystalline structure of a film or substrate can be evaluated using X-ray diffraction (XRD) spectroscopy. Figure 36B shows an XRD spectrum obtained by GIXD (Grazing-Incidence XRD) measurement of a CAAC-IGZO film classified as "Crystalline." The GIXD method is also known as the thin-film method or the Seemann-Bohlin method. Hereinafter, the XRD spectrum obtained by GIXD measurement shown in Figure 36B will be simply referred to as the XRD spectrum. The vertical axis of Figure 36B represents intensity, and the horizontal axis represents 2θ. The composition of the CAAC-IGZO film shown in Figure 36B is approximately In:Ga:Zn=4:2:3 [atomic ratio]. The thickness of the CAAC-IGZO film shown in Figure 36B is 500 nm.

[0533] As shown in Figure 36B, a clear peak indicating crystallinity is detected in the XRD spectrum of the CAAC-IGZO film. Specifically, a peak indicating c-axis orientation is detected near 2θ=31° in the XRD spectrum of the CAAC-IGZO film. As shown in Figure 36B, the peak near 2θ=31° is asymmetric with respect to the angle at which the peak intensity is detected.

[0534] The crystalline structure of a film or substrate can be evaluated by a diffraction pattern (also called a nanobeam electron diffraction pattern) observed using nanobeam electron diffraction (NBED). The diffraction pattern of a CAAC-IGZO film is shown in Figure 36C. Figure 36C shows a diffraction pattern observed using NBED, in which an electron beam is incident parallel to the substrate. The composition of the CAAC-IGZO film shown in Figure 36C is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. In nanobeam electron diffraction, electron diffraction is performed using a probe diameter of 1 nm.

[0535] As shown in Figure 36C, multiple spots indicating c-axis orientation are observed in the diffraction pattern of the CAAC-IGZO film.

[0536] <<Oxide semiconductor structure>> Note that oxide semiconductors may be classified differently from those shown in FIG. 36A when focusing on their crystal structures. For example, oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include the above-mentioned CAAC-OS and nc-OS. Non-single-crystal oxide semiconductors include polycrystalline oxide semiconductors, amorphous-like oxide semiconductors (a-like OSs), amorphous oxide semiconductors, and the like.

[0537] Here, the above-mentioned CAAC-OS, nc-OS, and a-like OS will be described in detail.

[0538] [CAAC-OS] CAAC-OS is an oxide semiconductor having multiple crystalline regions, each with its c-axis aligned in a specific direction. The specific direction can be the thickness direction of the CAAC-OS film, the normal direction to the surface on which the CAAC-OS film is formed, or the normal direction to the surface of the CAAC-OS film. A crystalline region is a region with periodic atomic arrangement. Considering an atomic arrangement as a lattice arrangement, a crystalline region can also be a region with a uniform lattice arrangement. Furthermore, CAAC-OS has a region where multiple crystalline regions are connected in the ab-plane direction, and the region may have distortion. The distortion refers to a location where the lattice orientation changes between a region with a uniform lattice arrangement and a region with a different uniform lattice arrangement in the region where multiple crystalline regions are connected. In other words, CAAC-OS is an oxide semiconductor with a c-axis aligned but no clear orientation in the ab-plane direction.

[0539] Each of the multiple crystalline regions is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of one minute crystal, the maximum diameter of the crystalline region is less than 10 nm. When a crystalline region is composed of many minute crystals, the size of the crystalline region may be several tens of nm.

[0540] In an In-M-Zn oxide (wherein element M is one or more elements selected from aluminum, gallium, yttrium, tin, titanium, etc.), the CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter referred to as an In layer) and a layer containing element M, zinc (Zn), and oxygen (hereinafter referred to as an (M, Zn) layer) are stacked. Note that indium and element M are mutually substituted. Therefore, the (M, Zn) layer may contain indium. Furthermore, the In layer may contain element M. Furthermore, the In layer may contain Zn. The layered structure is observed as a lattice image in a high-resolution TEM image, for example.

[0541] When the CAAC-OS film is subjected to structural analysis using, for example, an XRD apparatus, a peak indicating c-axis orientation is detected at or near 2θ=31° in out-of-plane XRD measurement using θ / 2θ scan. Note that the position of the peak indicating c-axis orientation (2θ value) may vary depending on the type and composition of the metallic elements constituting the CAAC-OS.

[0542] Furthermore, for example, in the electron diffraction pattern of the CAAC-OS film, multiple bright spots are observed, and the spots are observed at positions that are point-symmetric with respect to the spot of the incident electron beam that has passed through the sample (also called the direct spot).

[0543] When the crystalline region is observed from the specific direction, the lattice arrangement in the crystalline region is basically a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be non-regular hexagonal. The distortion may also have a pentagonal, heptagonal, or other lattice arrangement. In the CAAC-OS, no clear grain boundaries can be identified even near the distortion. This indicates that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is thought to be because the CAAC-OS can tolerate distortion due to the lack of close-packed oxygen atom arrangement in the ab-plane direction and the change in interatomic bond distance caused by metal atom substitution.

[0544] A crystal structure with clear grain boundaries is called polycrystalline. Grain boundaries act as recombination centers, trapping carriers and potentially causing a decrease in the on-state current and field-effect mobility of a transistor. Therefore, CAAC-OS, which lacks clear grain boundaries, is one of the crystalline oxides with a crystal structure suitable for use in the semiconductor layer of a transistor. Zn is preferred for use in CAAC-OS. For example, In-Zn oxide and In-Ga-Zn oxide are suitable because they can suppress the generation of grain boundaries more effectively than In oxide.

[0545] CAAC-OS is an oxide semiconductor with high crystallinity and no clear grain boundaries. Therefore, it can be said that the CAAC-OS is less susceptible to a decrease in electron mobility due to grain boundaries. Furthermore, since the crystallinity of an oxide semiconductor can be reduced by the inclusion of impurities or the generation of defects, the CAAC-OS can also be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Therefore, oxide semiconductors with CAAC-OS have stable physical properties. Therefore, oxide semiconductors with CAAC-OS are heat-resistant and highly reliable. Furthermore, the CAAC-OS is stable even under high temperatures (so-called thermal budget) during the manufacturing process. Therefore, using a CAAC-OS for an OS transistor can increase the flexibility of the manufacturing process.

[0546] [nc-OS] The nc-OS has periodic atomic arrangement in a microscopic region (e.g., a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In other words, the nc-OS has microcrystalline structures. The size of the microcrystalline structures is, for example, 1 nm to 10 nm, particularly 1 nm to 3 nm, and therefore these microcrystalline structures are also called nanocrystalline structures. Furthermore, the nc-OS exhibits no regularity in the crystal orientation between different nanocrystalline structures. Therefore, the entire film lacks orientation. Therefore, depending on the analytical method, the nc-OS may be indistinguishable from an a-like OS or an amorphous oxide semiconductor. For example, when a structural analysis of an nc-OS film is performed using an XRD system, no peaks indicating crystallinity are detected in out-of-plane XRD measurements using θ / 2θ scanning. Furthermore, when an nc-OS film is subjected to electron diffraction (also known as selected-area electron diffraction) using an electron beam with a probe diameter larger than that of nanocrystalline structures (e.g., 50 nm or larger), a halo-like diffraction pattern is observed. On the other hand, when electron diffraction (also called nanobeam electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter close to or smaller than the size of the nanocrystals (for example, 1 nm to 30 nm), an electron diffraction pattern can be obtained in which multiple spots are observed within a ring-shaped region centered on the direct spot.

[0547] [a-like OS] The a-like OS is an oxide semiconductor having a structure between the nc-OS and the amorphous oxide semiconductor. The a-like OS has a pore or low-density region. That is, the a-like OS has lower crystallinity than the nc-OS and CAAC-OS. Furthermore, the a-like OS has a higher hydrogen concentration in the film than the nc-OS and CAAC-OS.

[0548] <<Oxide semiconductor structure>> Next, the above-mentioned CAC-OS will be described in detail, which relates to the material composition.

[0549] [CAC-OS] CAC-OS is a material structure in which elements constituting a metal oxide are unevenly distributed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or in the vicinity thereof. Note that, hereinafter, a metal oxide in which one or more metal elements are unevenly distributed and the regions containing the metal elements are mixed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or in the vicinity thereof, is also referred to as a mosaic or patch state.

[0550] Furthermore, CAC-OS has a mosaic structure in which the material is separated into first and second regions, and the first regions are distributed throughout the film (hereinafter also referred to as a cloud structure). That is, CAC-OS is a composite metal oxide having a structure in which the first and second regions are mixed.

[0551] Here, the atomic ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in the In-Ga-Zn oxide are denoted as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS in the In-Ga-Zn oxide, the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film. The second region is a region where [Ga] is larger than [Ga] in the composition of the CAC-OS film. Alternatively, for example, the first region is a region where [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region. The second region is a region where [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.

[0552] Specifically, the first region is a region whose main component is indium oxide, indium zinc oxide, or the like. The second region is a region whose main component is gallium oxide, gallium zinc oxide, or the like. In other words, the first region can be rephrased as a region whose main component is In. The second region can be rephrased as a region whose main component is Ga.

[0553] It should be noted that there are cases where a clear boundary between the first region and the second region cannot be observed.

[0554] For example, in the case of CAC-OS in In-Ga-Zn oxide, EDX mapping obtained using EDX (Energy Dispersive X-ray spectroscopy) confirms that the CAC-OS has a structure in which a region mainly composed of In (first region) and a region mainly composed of Ga (second region) are unevenly distributed and mixed.

[0555] When CAC-OS is used in a transistor, the conductivity due to the first region and the insulating property due to the second region act in a complementary manner, thereby providing the CAC-OS with a switching function (the ability to turn on and off). In other words, CAC-OS has a conductive function in part of the material and an insulating function in part of the material, and the material as a whole functions as a semiconductor. By separating the conductive function from the insulating function, both functions can be maximized. Therefore, by using CAC-OS in a transistor, a high on-current (I on ), high field-effect mobility (μ), and good switching behavior can be achieved.

[0556] Oxide semiconductors have a variety of structures and each has different characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, a CAC-OS, an nc-OS, and a CAAC-OS.

[0557] <Transistors containing oxide semiconductors> Next, a case where the oxide semiconductor is used in a transistor will be described.

[0558] By using the oxide semiconductor for a transistor, a transistor with high field-effect mobility and high reliability can be realized.

[0559] For the transistor, an oxide semiconductor with a low carrier concentration is preferably used. For example, the carrier concentration of the oxide semiconductor is 1×10 17 cm -3 Less than 1 × 10 15 cm -3 or less, more preferably 1 × 10 13 cm -3 Less than or equal to 1×10 11 cm -3 or less, more preferably 1 × 10 10 cm -3 Less than 1 x 10 -9 cm-3 The above is the case. Note that in order to reduce the carrier concentration of an oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be reduced to reduce the density of defect states. In this specification and the like, a semiconductor having a low impurity concentration and a low density of defect states is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. Note that an oxide semiconductor having a low carrier concentration may also be referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor.

[0560] Furthermore, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states, and therefore the density of trap states may also be low.

[0561] Furthermore, charges trapped in the trap states of an oxide semiconductor take a long time to disappear and may behave like fixed charges. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states may have unstable electrical characteristics.

[0562] Therefore, in order to stabilize the electrical characteristics of a transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. Furthermore, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the adjacent film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0563] <Impurities> Here, the influence of each impurity in an oxide semiconductor will be described.

[0564] When an oxide semiconductor contains silicon or carbon, which is one of the Group 14 elements, defect levels are formed in the oxide semiconductor. Therefore, the concentrations of silicon or carbon in the oxide semiconductor and those near the interface with the oxide semiconductor (concentrations obtained by secondary ion mass spectrometry (SIMS)) are calculated as follows: 18 atoms / cm 3 Less than or equal to 2 x 10 17atoms / cm 3 The following applies.

[0565] Furthermore, when an oxide semiconductor contains an alkali metal or alkaline earth metal, defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or alkaline earth metal is likely to have normally-on characteristics. For this reason, when the concentration of the alkali metal or alkaline earth metal in the oxide semiconductor obtained by SIMS is 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 16 atoms / cm 3 Do the following:

[0566] Furthermore, when nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier concentration increases, and the semiconductor is likely to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have normally-on characteristics. Alternatively, when nitrogen is contained in an oxide semiconductor, trap states may be formed. As a result, the electrical characteristics of the transistor may become unstable. For this reason, the nitrogen concentration in the oxide semiconductor obtained by SIMS is set to 5×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 Less than 5 × 10, more preferably 17 atoms / cm 3 Do the following:

[0567] Furthermore, hydrogen contained in an oxide semiconductor may react with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy. When hydrogen enters the oxygen vacancy, electrons serving as carriers may be generated. Furthermore, some of the hydrogen may bond with oxygen bonded to a metal atom to generate electrons serving as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. For this reason, it is preferable to reduce the amount of hydrogen in the oxide semiconductor as much as possible. Specifically, the hydrogen concentration in an oxide semiconductor measured by SIMS is 1×10 20 atoms / cm 3 Less than 1 x 10 19 atoms / cm 3 less than 5 × 10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 Make it less than.

[0568] When an oxide semiconductor with sufficiently reduced impurities is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0569] The configurations, structures, methods, and the like described in this embodiment can be used in appropriate combination with the configurations, structures, methods, and the like described in other embodiment modes and examples.

[0570] (Embodiment 5) In this embodiment, electronic devices of one embodiment of the present invention will be described with reference to FIGS. 37, 38, and 39.

[0571] The electronic devices of this embodiment include the display device of one embodiment of the present invention. For example, the display device of one embodiment of the present invention can be applied to a display portion of the electronic device. The display device of one embodiment of the present invention has a function of detecting light, and therefore, biometric authentication can be performed or touch or near-touch can be detected in the display portion. This can improve the functionality, convenience, and the like of the electronic device.

[0572] Examples of electronic devices include electronic devices with relatively large screens such as television sets, desktop or notebook personal computers, computer monitors, digital signage, large game machines such as pachinko machines, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and sound playback devices.

[0573] The electronic device of this embodiment may have a sensor (including a function to measure force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays).

[0574] The electronic device of the present embodiment can have various functions, such as a function to display various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function to display a calendar, date, time, etc., a function to execute various software (programs), a wireless communication function, a function to read out programs or data recorded on a recording medium, etc.

[0575] Electronic device 6500 shown in FIG. 37A is a portable information terminal that can be used as a smartphone.

[0576] The electronic device 6500 includes a housing 6501, a display portion 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, and a light source 6508. The display portion 6502 has a touch panel function.

[0577] The display device of one embodiment of the present invention can be applied to the display portion 6502. This makes the electronic device 6500 inexpensive.

[0578] FIG. 37B is a schematic cross-sectional view including the end of the housing 6501 on the microphone 6506 side.

[0579] A light-transmitting protective member 6510 is provided on the display surface side of the housing 6501, and a display panel 6511, optical members 6512, a touch sensor panel 6513, a printed circuit board 6517, a battery 6518, etc. are arranged in the space surrounded by the housing 6501 and the protective member 6510.

[0580] A display panel 6511, an optical member 6512, and a touch sensor panel 6513 are fixed to the protective member 6510 by adhesive layers (not shown).

[0581] In an area outside the display unit 6502, a part of the display panel 6511 is folded back, and an FPC 6515 is connected to the folded back part. An IC 6516 is mounted on the FPC 6515. The FPC 6515 is connected to a terminal provided on a printed circuit board 6517.

[0582] The flexible display of one embodiment of the present invention can be applied to the display panel 6511. Therefore, an extremely lightweight electronic device can be realized. In addition, since the display panel 6511 is extremely thin, a large-capacity battery 6518 can be mounted thereon while keeping the thickness of the electronic device small. Furthermore, by folding back a part of the display panel 6511 and arranging a connection portion with the FPC 6515 on the back side of the pixel portion, an electronic device with a narrow frame can be realized.

[0583] 38A shows an example of a television device. A television device 7100 has a display unit 7000 built into a housing 7101. Here, the housing 7101 is supported by a stand 7103.

[0584] The display device of one embodiment of the present invention can be applied to the display portion 7000. This makes the television set 7100 inexpensive.

[0585] 38A can be operated using an operation switch provided on the housing 7101 or a separate remote control 7111. Alternatively, a touch sensor may be provided in the display unit 7000, and the television 7100 may be operated by touching the display unit 7000 with a finger or the like. The remote control 7111 may have a display unit that displays information output from the remote control 7111. The channel and volume can be controlled using the operation keys or touch panel provided on the remote control 7111, and the video displayed on the display unit 7000 can be controlled.

[0586] The television device 7100 is configured to include a receiver, a modem, and the like. The receiver can receive general television broadcasts. In addition, by connecting to a wired or wireless communication network via the modem, it is possible to perform one-way (from sender to receiver) or two-way (between sender and receiver, or between receivers, etc.) information communication.

[0587] 38B shows an example of a laptop personal computer 7200. The laptop personal computer 7200 includes a housing 7211, a keyboard 7212, a pointing device 7213, an external connection port 7214, and the like. A display portion 7000 is incorporated in the housing 7211.

[0588] The display device of one embodiment of the present invention can be applied to the display portion 7000. This enables the notebook personal computer 7200 to be manufactured at low cost.

[0589] 38C and 38D show an example of digital signage.

[0590] 38C includes a housing 7301, a display unit 7000, and a speaker 7303. The digital signage 7300 may further include an LED lamp, operation keys (including a power switch or an operation switch), a connection terminal, various sensors, a microphone, and the like.

[0591] 38D shows a digital signage 7400 attached to a cylindrical pillar 7401. The digital signage 7400 has a display unit 7000 provided along the curved surface of the pillar 7401.

[0592] 38C and 38D, the display device of one embodiment of the present invention can be applied to the display portion 7000. This makes it possible to reduce the cost of the digital signage 7300 and the digital signage 7400.

[0593] The larger the display unit 7000, the more information can be provided at one time. Also, the larger the display unit 7000, the more easily it will attract people's attention, which can increase the advertising effectiveness of, for example, advertisements.

[0594] Applying a touch panel to the display unit 7000 is preferable because it not only displays images or videos on the display unit 7000 but also allows the user to intuitively operate it. Furthermore, when used to provide information such as route information or traffic information, the intuitive operation can improve usability.

[0595] 38C and 38D, it is preferable that the digital signage 7300 or the digital signage 7400 can wirelessly link with an information terminal 7311 or an information terminal 7411 such as a smartphone carried by a user. For example, advertising information displayed on the display unit 7000 can be displayed on the screen of the information terminal 7311 or the information terminal 7411. Furthermore, the display on the display unit 7000 can be switched by operating the information terminal 7311 or the information terminal 7411.

[0596] Furthermore, it is also possible to cause the digital signage 7300 or the digital signage 7400 to execute a game using the screen of the information terminal 7311 or the information terminal 7411 as an operation means (controller), thereby allowing an unspecified number of users to simultaneously participate in and enjoy the game.

[0597] The electronic device shown in Figures 39A to 39F has a housing 9000, a display unit 9001, a speaker 9003, operation keys 9005 (including a power switch or an operation switch), a connection terminal 9006, a sensor 9007 (including a function to measure force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor or infrared rays), a microphone 9008, etc.

[0598] 39A to 39F have various functions. For example, they may have a function to display various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function to display a calendar, date, time, etc., a function to control processing using various software (programs), a wireless communication function, a function to read and process programs or data recorded on a recording medium, etc. Note that the functions of the electronic device are not limited to these, and the electronic device may have various other functions. The electronic device may have multiple display units. Furthermore, the electronic device may have a function to include a camera or the like to capture still images or videos and store them on a recording medium (external or built-in to the camera), a function to display the captured images on the display unit, etc.

[0599] The electronic device shown in FIGS. 39A to 39F will be described in detail below.

[0600] FIG. 39A is a perspective view showing a mobile information terminal 9101. The mobile information terminal 9101 can be used as, for example, a smartphone. The mobile information terminal 9101 may be provided with a speaker 9003, a connection terminal 9006, a sensor 9007, and the like. The mobile information terminal 9101 can display text and image information on multiple surfaces thereof. FIG. 39A shows an example in which three icons 9050 are displayed. Information 9051, indicated by a dashed rectangle, can also be displayed on another surface of the display unit 9001. Examples of the information 9051 include notifications of incoming emails, SNS messages, phone calls, etc., the title of the email or SNS message, the sender's name, the date and time, the remaining battery level, the strength of antenna reception, and the like. Alternatively, the icon 9050 or the like may be displayed in the position where the information 9051 is displayed.

[0601] 39A, the display device of one embodiment of the present invention can be applied to the display portion 9001. This makes it possible to reduce the cost of the portable information terminal 9101.

[0602] FIG. 39B is a perspective view showing mobile information terminal 9102. Mobile information terminal 9102 has a function of displaying information on three or more sides of display unit 9001. Here, an example is shown in which information 9052, information 9053, and information 9054 are displayed on different sides. For example, while carrying mobile information terminal 9102 in a breast pocket of clothes, the user can check information 9053 displayed in a position that can be observed from above mobile information terminal 9102. The user can check the display without taking mobile information terminal 9102 out of their pocket and decide, for example, whether to answer a call.

[0603] 39B, the display device of one embodiment of the present invention can be applied to the display portion 9001. This makes it possible to reduce the cost of the portable information terminal 9102.

[0604] FIG. 39C is a perspective view showing a wristwatch-type mobile information terminal 9200. The mobile information terminal 9200 can be used as, for example, a smart watch (registered trademark). The display surface of the display unit 9001 is curved, and display can be performed along the curved display surface. The mobile information terminal 9200 can also perform hands-free calling by communicating with, for example, a headset capable of wireless communication. The mobile information terminal 9200 can also perform data transmission and reception with other information terminals and charge itself via a connection terminal 9006. Note that charging may be performed by wireless power supply.

[0605] 39C, the display device of one embodiment of the present invention can be applied to the display portion 9001. This makes it possible to reduce the cost of the portable information terminal 9200.

[0606] 39D, 39E, and 39F are perspective views showing a foldable mobile information terminal 9201. FIG. 39D shows the mobile information terminal 9201 in an unfolded state, FIG. 39F shows it in a folded state, and FIG. 39E is a perspective view showing a state in the process of changing from one of FIG. 39D and FIG. 39F to the other. The mobile information terminal 9201 is highly portable when folded, and has a seamless, wide display area when unfolded, providing excellent viewability of the display. A display unit 9001 of the mobile information terminal 9201 is supported by three housings 9000 connected by hinges 9055. For example, the display unit 9001 can be bent with a curvature radius of 0.1 mm or more and 150 mm or less.

[0607] 39A to 39F, the display device of one embodiment of the present invention can be applied to the display portion 9001. This makes it possible to reduce the cost of the portable information terminal 9201.

[0608] At least a part of the configuration examples exemplified in this embodiment and the corresponding drawings can be implemented by appropriately combining with other configuration examples or drawings.

[0609] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification. [Explanation of symbols]

[0610] 10: display device, 10A: display device, 10B: display device, 10C: display device, 10D: display device, 10E: display device, 10F: display device, 10K: display device, 10L: display device, 10M: display device, 11: display unit, 12: pixel, 13: gate driver circuit, 14: pixel circuit, 14B: pixel circuit, 14G: pixel circuit, 14IR: pixel circuit, 14R: pixel circuit, 14W: pixel circuit, 15: pixel circuit, 16: light, 16B: light, 16G: light, 16R: light, 17: light, 18: substrate, 19: row driver circuit, 20: IC, 21: interface circuit, 22: control circuit , 23: Data driver circuit, 24: Circuit, 25: FPC, 26: Memory circuit, 31: Wiring, 31a: Wiring, 31b: Wiring, 32: Wiring, 33: Wiring, 34: Wiring, 35: Wiring, 36: Wiring, 37: Wiring, 38: Wiring, 41: Reference signal generation circuit, 42: A / D conversion circuit, 43: Shift register circuit, 44: Clock signal generation circuit, 51a: Transistor, 51b: Transistor, 52: Capacitor element, 53: Comparison circuit, 54: Counter circuit, 55a: Wiring, 55b: Wiring, 56: Wiring, 57: Wiring, 59: Wiring, 60: Light-emitting element, 61: Transistor, 61a : transistor, 61b: transistor, 62: transistor, 63: transistor, 64: capacitor, 65: wiring, 66: transistor, 67: capacitor, 68: wiring, 70: photodetector, 71: transistor, 72: transistor, 73: transistor, 74: transistor, 75: capacitor, 76: capacitor, 77: transistor, 78: transistor, 79: transistor, 80: CDS circuit, 81: transistor, 82a: transistor, 82b: transistor, 83a: transistor, 83b: transistor, 84a: capacitor, 84b: capacitor Element, 85: transistor, 86: transistor, 91: wiring, 92: wiring, 93: wiring, 94: wiring, 95: wiring, 96: wiring, 97: wiring, 101: timing signal generation circuit, 102: level shift circuit, 111: shift register circuit, 112: latch circuit, 113: level shift circuit, 114: D / A conversion circuit, 115: amplifier circuit, 121: substrate, 122: finger, 123: eye, 131: current source, 140: layer, 150: layer, 151: insulating film, 164: circuit, 165: wiring, 166: conductive layer, 172: FPC, 182: buffer layer, 184: buffer layer,191: pixel electrode, 192: buffer layer, 193: light-emitting layer, 194: buffer layer, 195: protective layer, 195a: inorganic insulating layer, 195b: organic insulating layer, 195c: inorganic insulating layer, 201: transistor, 204: connecting portion, 205: transistor, 206: transistor, 208: transistor, 209: transistor, 210: transistor, 211: insulating layer, 212: insulating layer, 213: insulating layer, 214: insulating layer, 215: insulating layer, 216: partition wall, 217: partition wall, 218: insulating layer, 221: conductive layer, 222a: conductive layer, 222b: conductive layer, 223: conductive layer, 22 5: insulating layer, 228: region, 231: semiconductor layer, 231i: channel formation region, 231n: low resistance region, 242: connection layer, 311: substrate, 313: semiconductor region, 314a: low resistance region, 314b: low resistance region, 315: insulator, 316: conductor, 320: insulator, 322: insulator, 324: insulator, 326: insulator, 328: conductor, 330: conductor, 341: transistor, 342: transistor, 350: insulator, 352: insulator, 354: insulator, 356: conductor, 360: insulator, 362: insulator, 364: insulator, 366: conductor, 370: insulator body, 372: insulator, 374: insulator, 376: conductor, 380: insulator, 382: insulator, 384: insulator, 386: conductor, 400A: display device, 400B: display device, 400C: display device, 400D: display device, 404: insulator, 411: pixel electrode, 412: common layer, 413: active layer, 414: common layer, 415: common electrode, 423a: light, 423b: reflected light, 423c: light, 423d: reflected light, 442: adhesive layer, 443: space, 446: lens array, 449: lens, 451: substrate, 452: substrate, 453: substrate, 454: substrate, 455: adhesive layer, 460: color filter, 461: lens, 462: lens array, 500: transistor, 500A: transistor, 500B: transistor, 503: conductor, 503a: conductor, 503b: conductor, 510: insulator, 512: insulator, 513: insulator, 514: insulator, 516: insulator, 518: conductor, 520: insulator, 522: insulator, 524: insulator, 530: oxide, 530a: oxide, 530b: oxide, 540a: conductor, 540b: conductor, 542a: conductor, 542b: conductor, 543a: region, 543b: region, 544: insulator,545: insulator, 546: conductor, 548: conductor, 550: transistor, 552: insulator, 560: conductor, 560a: conductor, 560b: conductor, 574: insulator, 580: insulator, 581: insulator, 582: insulator, 586: insulator, 600: capacitor, 610: conductor, 612: conductor, 620: conductor, 630: insulator, 640: insulator, 6500: electronic device, 6501: housing , 6502: display unit, 6503: power button, 6504: button, 6505: speaker, 6506: microphone, 6507: camera, 6508: light source, 6510: protective member, 6511: display panel, 6512: optical member, 6513: touch sensor panel, 6515: FPC, 6516: IC, 6517: printed circuit board, 6518: battery, 7000: display unit, 7100: television device ,7101: Housing, 7103: Stand, 7111: Remote control device, 7200: Notebook personal computer, 7211: Housing, 7212: Keyboard, 7213: Pointing device, 7214: External connection port, 7300: Digital signage, 7301: Housing, 7303: Speaker, 7311: Information terminal, 7400: Digital signage, 7401: Pillar, 7411: Information terminal, 9000: housing, 9001: display unit, 9003: speaker, 9005: operation keys, 9006: connection terminal, 9007: sensor, 9008: microphone, 9050: icon, 9051: information, 9052: information, 9053: information, 9054: information, 9055: hinge, 9101: portable information terminal, 9102: portable information terminal, 9200: portable information terminal, 9201: portable information terminal,

Claims

1. It has a display unit, the display unit has the plurality of pixels, each of the plurality of pixels includes a first pixel circuit and a second pixel circuit; the first pixel circuit includes a first transistor and a light receiving element; the second pixel circuit is a display device having a second transistor and a light-emitting element, a first insulating layer, a second insulating layer, a first pixel electrode, a second pixel electrode, a first common layer, an active layer, a light-emitting layer, a second common layer, a common electrode, a third insulating layer, a fourth insulating layer, and a fifth insulating layer; the first insulating layer is a first inorganic insulating layer and has a region located above the first transistor and a region located above the second transistor; the second insulating layer has a region located above the first insulating layer; the first pixel electrode has a region located above the second insulating layer and functions as one of a pair of electrodes of the light receiving element; the second pixel electrode has a region located above the second insulating layer and functions as one of a pair of electrodes of the light-emitting element; the first common layer has a region located above the first pixel electrode and a region located above the second pixel electrode, and functions as one or both of a hole injection layer and a hole transport layer; the active layer has a region overlapping with the first pixel electrode via the first common layer; the light-emitting layer has a region overlapping with the second pixel electrode via the first common layer, the second common layer has a region located above the active layer and a region located above the light-emitting layer, and functions as one or both of an electron transport layer and an electron injection layer; the common electrode has a region overlapping with the active layer via the second common layer and a region overlapping with the light-emitting layer via the second common layer, and functions as the other of the pair of electrodes of the light-receiving element and also functions as the other of the pair of electrodes of the light-emitting element; the third insulating layer is a second inorganic insulating layer and has a region located above the common electrode; the fourth insulating layer is an organic insulating layer and has a region located above the third insulating layer; the fifth insulating layer is a third inorganic insulating layer and has a region located above the fourth insulating layer; the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, and the fifth insulating layer are disposed across the display unit, the third insulating layer has a region in contact with the fifth insulating layer outside the display section, A display device, wherein the first insulating layer has a region in contact with the third insulating layer in a region outside the display section.

2. a first layer having a display portion; a second layer having control circuitry, data driver circuitry, and readout circuitry; the first layer is disposed above the second layer; the display unit has the plurality of pixels, each of the plurality of pixels includes a first pixel circuit and a second pixel circuit; the first pixel circuit includes a first transistor and a light receiving element; the second pixel circuit includes a second transistor and a light-emitting element; the first pixel circuit and the readout circuit are electrically connected via a first wiring; the second pixel circuit and the readout circuit are electrically connected via a second wiring; the control circuit has a function of supplying a clock signal to the data driver circuit and the read circuit; the data driver circuit has a function of supplying image data to the second pixel circuit; the readout circuit has a function of outputting a first signal corresponding to monitor current data of the second pixel circuit; the readout circuit has a function of outputting a second signal corresponding to imaging data acquired using the light receiving element in the first pixel circuit, a first insulating layer, a second insulating layer, a first pixel electrode, a second pixel electrode, a first common layer, an active layer, a light-emitting layer, a second common layer, a common electrode, a third insulating layer, a fourth insulating layer, and a fifth insulating layer; the first insulating layer is a first inorganic insulating layer and has a region located above the first transistor and a region located above the second transistor; the second insulating layer has a region located above the first insulating layer; the first pixel electrode has a region located above the second insulating layer and functions as one of a pair of electrodes of the light receiving element; the second pixel electrode has a region located above the second insulating layer and functions as one of a pair of electrodes of the light-emitting element; the first common layer has a region located above the first pixel electrode and a region located above the second pixel electrode, and functions as one or both of a hole injection layer and a hole transport layer; the active layer has a region overlapping with the first pixel electrode via the first common layer; the light-emitting layer has a region overlapping with the second pixel electrode via the first common layer, the second common layer has a region located above the active layer and a region located above the light-emitting layer, and functions as one or both of an electron transport layer and an electron injection layer; the common electrode has a region overlapping with the active layer via the second common layer and a region overlapping with the light-emitting layer via the second common layer, and functions as the other of the pair of electrodes of the light-receiving element and also functions as the other of the pair of electrodes of the light-emitting element; the third insulating layer is a second inorganic insulating layer and has a region located above the common electrode; the fourth insulating layer is an organic insulating layer and has a region located above the third insulating layer; the fifth insulating layer is a third inorganic insulating layer and has a region located above the fourth insulating layer; the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, and the fifth insulating layer are disposed across the display unit, the third insulating layer has a region in contact with the fifth insulating layer outside the display section, A display device, wherein the first insulating layer has a region in contact with the third insulating layer in a region outside the display section.

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