Arithmetic circuit, memory system, and control method

Abstract

To restrain the scale of an arithmetic circuit.SOLUTION: An arithmetic circuit comprises a matrix calculation section and at least p evaluation sections. The matrix calculation section calculates a matrix corresponding to a linearizing polynomial included in an affine polynomial obtained by decomposing an error position polynomial. Each of the evaluation sections calculates a first multiplication result obtained by multiplying a matrix by a first multiplication value based on a substitution value substituted for the error position polynomial, calculates a second multiplication result obtained by multiplying a second multiplication value based on a substitution value by an evaluation term for each of at least one evaluation term other than a linearizing polynomial, and outputs error position information based on a value obtained by adding the first multiplication result and the second multiplication result.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] FIELD Embodiments of the present invention relate to an arithmetic circuit, a memory system, and a control method. [Background technology]

[0002] In a memory system, in order to protect data stored in a memory such as a NAND flash memory, error correction coded data is stored in the memory. Therefore, when reading data stored in the memory, the error correction coded data (also called a received word) read from the memory is decoded to restore the data before being error correction coded.

[0003] For error-correcting codes, decoding techniques using error locator polynomials are known. For example, Chien search is known as a method for calculating error locations using an error locator polynomial. Chien search is a method in which values ​​are sequentially substituted into the error locator polynomial and the error location is searched for based on the value that makes the output value of the error locator polynomial zero. In the decoding process, the scale of the calculation circuitry for the process of searching for the root of the error locator polynomial, such as Chien search, tends to become large. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] U.S. Patent No. 6,643,819 [Patent Document 2] US Patent Application Publication No. 2015 / 0155885 [Patent Document 3] US Patent Application Publication No. 2013 / 0326315 [Non-patent literature]

[0005] [Non-Patent Document 1] SV Fedorenko, et al., “Finding roots of polynomials over finite fields”, IEEE Transactions on Communications (Volume: 50, Issue: 11, November 2002) Summary of the Invention [Problem to be solved by the invention]

[0006] An object of the embodiment of the present invention is to reduce the scale of an arithmetic circuit used for operations such as decoding processing. [Means for solving the problem]

[0007] An arithmetic circuit according to an embodiment includes a matrix calculation unit and p or more evaluation units. The matrix calculation unit calculates a matrix according to a linearization polynomial included in an affine polynomial obtained by decomposing an error locator polynomial. Each evaluation unit calculates a first multiplication result by multiplying the matrix by a first multiplication value based on an assignment value to be assigned to the error locator polynomial, calculates a second multiplication result by multiplying the evaluation term by a second multiplication value based on the assignment value for each of one or more evaluation terms other than the linearization polynomial, and outputs error location information based on a value obtained by adding the first multiplication result and the second multiplication result. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a block diagram of a memory system according to an embodiment. [Figure 2] FIG. 2 is a block diagram of a decoding unit according to the embodiment. [Figure 3] FIG. 10 is a diagram showing a configuration example of an error position calculation unit in which substitution processing is parallelized. [Figure 4] FIG. 2 is a diagram showing an example of the configuration of an error position calculation unit. [Figure 5] FIG. 2 is a diagram showing an example of the configuration of an error position calculation unit. [Figure 6] FIG. 10 is a diagram showing an example of the configuration of a Δ0(j) calculation unit. [Figure 7]FIG. 10 is a diagram for explaining an example of matrix multiplication in an evaluation unit. [Figure 8] FIG. 2 is a diagram showing an example of the configuration of an error position calculation unit. [Figure 9] FIG. 10 is a diagram showing an example of the configuration of a Δ1(j) calculation unit. [Figure 10] 10 is a flowchart of a decoding process according to an embodiment. [Figure 11] FIG. 10 is a diagram showing an example of the configuration of an error position calculation unit according to the second embodiment. [Figure 12] FIG. 10 is a diagram showing an example of the configuration of a chain-type Δ1(j) calculation unit. DETAILED DESCRIPTION OF THE INVENTION

[0009] A preferred embodiment of an arithmetic circuit according to the present invention will be described in detail below with reference to the accompanying drawings. The following description will be given taking as an example a memory system including an arithmetic circuit that searches for the roots of an error locator polynomial when decoding an error correction code. The configuration using the arithmetic circuit is not limited to this example, and any system (device, equipment) may be used.

[0010] (First embodiment) First, a memory system according to this embodiment will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing a schematic configuration example of a memory system according to this embodiment. As shown in FIG. 1, the memory system 1 includes a memory controller 10 and a nonvolatile memory 20. The memory system 1 can be connected to a host 30, and FIG. 1 shows the memory system 1 connected to the host 30. The host 30 may be, for example, an electronic device such as a personal computer or a mobile terminal.

[0011] The nonvolatile memory 20 is a nonvolatile memory that stores data nonvolatilely, such as a NAND flash memory (hereinafter simply referred to as a NAND memory). In the following description, a case where a NAND memory is used as the nonvolatile memory 20 will be exemplified, but it is also possible to use storage devices other than a NAND memory, such as a three-dimensional structure flash memory, a ReRAM (Resistive Random Access Memory), or an FeRAM (Ferroelectric Random Access Memory), as the nonvolatile memory 20. Furthermore, it is not essential that the nonvolatile memory 20 be a semiconductor memory, and this embodiment can also be applied to various storage media other than semiconductor memories.

[0012] The memory system 1 may be any of various memory systems equipped with a nonvolatile memory 20, such as a so-called SSD (Solid State Drive) or a memory card in which a memory controller 10 and a nonvolatile memory 20 are configured as a single package.

[0013] The memory controller 10 controls writing to the nonvolatile memory 20 in accordance with a write request from the host 30. The memory controller 10 also controls reading from the nonvolatile memory 20 in accordance with a read request from the host 30. The memory controller 10 is a semiconductor integrated circuit configured as, for example, an SoC (System on a Chip). The memory controller 10 includes a host I / F (host interface) 15, a memory I / F (memory interface) 13, a control unit 11, an encoding / decoding unit (codec) 14, and a data buffer 12. The host I / F 15, the memory I / F 13, the control unit 11, the encoding / decoding unit 14, and the data buffer 12 are interconnected by an internal bus 16. Some or all of the operations of the components of the memory controller 10 described below may be implemented by a CPU (Central Processing Unit) executing firmware, or may be implemented by hardware.

[0014] The host I / F 15 performs processing in accordance with the interface standard with the host 30, and outputs commands received from the host 30, user data to be written, etc. to the internal bus 16. The host I / F 15 also transmits user data read and restored from the nonvolatile memory 20, responses from the control unit 11, etc. to the host 30.

[0015] The memory I / F 13 performs a write process to the nonvolatile memory 20 based on an instruction from the control unit 11. The memory I / F 13 also performs a read process from the nonvolatile memory 20 based on an instruction from the control unit 11.

[0016] The control unit 11 performs overall control of each component of the memory system 1. When the control unit 11 receives an instruction from the host 30 via the host I / F 15, it performs control in accordance with the instruction. For example, the control unit 11 instructs the memory I / F 13 to write user data and parity to the nonvolatile memory 20 in accordance with the instruction from the host 30. The control unit 11 also instructs the memory I / F 13 to read user data and parity from the nonvolatile memory 20 in accordance with the instruction from the host 30.

[0017] Furthermore, when the control unit 11 receives a write request from the host 30, it determines a storage area (memory area) on the nonvolatile memory 20 for the user data stored in the data buffer 12. That is, the control unit 11 manages the write destination of the user data. The correspondence between the logical address of the user data received from the host 30 and the physical address indicating the storage area on the nonvolatile memory 20 where the user data is stored is stored as an address conversion table.

[0018] Furthermore, when the control unit 11 receives a read request from the host 30, it converts the logical address specified by the read request into a physical address using the address conversion table described above, and instructs the memory I / F 13 to read from the physical address.

[0019] In NAND memory, data is generally written and read in units of data called pages, and erased in units of data called blocks. In this embodiment, a plurality of memory cells connected to the same word line are called a memory cell group. When the memory cells are single-level cells (SLC: Single Level Cell), one memory cell group corresponds to one page. When the memory cells are multi-level cells (MLC: Multiple Level Cell), one memory cell group corresponds to multiple pages. In this description, MLC includes triple-level cells (TLC) and quad-level cells (QLC). Each memory cell is connected to a word line and also to a bit line. Therefore, each memory cell can be identified by an address that identifies the word line and an address that identifies the bit line.

[0020] The data buffer 12 temporarily stores user data received by the memory controller 10 from the host 30 before storing the data in the nonvolatile memory 20. The data buffer 12 also temporarily stores user data read from the nonvolatile memory 20 before transmitting the data to the host 30. The data buffer 12 may be a general-purpose memory such as an SRAM (Static Random Access Memory) or a DRAM (Dynamic Random Access Memory). The data buffer 12 may not be built into the memory controller 10 but may be mounted outside the memory controller 10.

[0021] User data transmitted from the host 30 is transferred to the internal bus 16 and temporarily stored in the data buffer 12. The encoding / decoding unit 14 encodes the user data stored in the nonvolatile memory 20 to generate code words. The encoding / decoding unit 14 also decodes received words, which are data read from the nonvolatile memory 20, to restore the user data. Therefore, the encoding / decoding unit 14 includes an encoding unit (Encoder) 17 and a decoding unit (Decoder) 18. Note that the data encoded by the encoding / decoding unit 14 may include control data used inside the memory controller 10 in addition to the user data.

[0022] Next, the write process of this embodiment will be described. When writing user data to the nonvolatile memory 20, the control unit 11 instructs the encoding unit 17 to encode the user data. At that time, the control unit 11 determines a storage location (storage address) of the code word in the nonvolatile memory 20, and also instructs the memory I / F 13 of the determined storage location.

[0023] The encoding unit 17 encodes the user data in the data buffer 12 to generate code words based on instructions from the control unit 11. Examples of encoding methods that can be used include encoding methods using algebraic codes such as BCH (Bose-Chaudhuri-Hocquenghem) codes and RS (Reed-Solomon) codes, as well as encoding methods (such as product codes) that use these codes as row- and column-oriented component codes. The memory I / F 13 controls the storage of code words in memory locations in the nonvolatile memory 20 instructed by the control unit 11. The following describes an example in which a BCH code that corrects errors of t bits or less is used.

[0024] Next, a description will be given of the processing performed when reading data from the nonvolatile memory 20 in this embodiment. When reading data from the nonvolatile memory 20, the control unit 11 specifies an address on the nonvolatile memory 20 and instructs the memory I / F 13 to read. The control unit 11 also instructs the decoding unit 18 to start decoding. In accordance with the instruction from the control unit 11, the memory I / F 13 reads data from the specified address in the nonvolatile memory 20 and inputs the read data to the decoding unit 18 as a received word. The decoding unit 18 decodes the received word, which is the data read from the nonvolatile memory 20.

[0025] The decoding unit 18 decodes the received word, which is data read from the nonvolatile memory 20. The decoding unit 18 performs calculation of an error locator polynomial using, for example, the Peterson-Gorenstein-Zierler (PGZ) method, the Berlekamp-Massey (BM) method, or the Euclidean method.

[0026] Fig. 2 is a block diagram showing an example of the configuration of the decoding unit 18 according to this embodiment. As shown in Fig. 2, the decoding unit 18 includes a syndrome calculation unit 101, an error position polynomial calculation unit 102, an error position calculation unit 103 as an arithmetic circuit, and a correction unit 104.

[0027] The syndrome calculation unit 101 calculates a syndrome using a received word (read sequence), which is data read from the non-volatile memory 20. The syndrome calculation unit 101 may calculate a syndrome using any conventional method. Depending on the number of corrections, multiple syndromes may be calculated. If all the syndrome values ​​are 0, it can be determined that there is no error in the received word, and the decoding unit 18 can terminate the decoding process without performing any further processing.

[0028] The error locator polynomial calculation unit 102 uses the syndrome to calculate the error locator polynomial by the PGZ method, the BM method, the Euclidean method, etc. Some of the coefficients of the error locator polynomial are calculated by adding and multiplying the syndrome.

[0029] The syndrome and the coefficient σ calculated using the syndrome are elements of the Galois field. m It is a set with m elements (m is an integer greater than or equal to 1) and the four arithmetic operations are defined and characterized by a primitive polynomial of degree m.

[0030] The error locator polynomial calculation unit 102 outputs the coefficients of the calculated error locator polynomial and the degree of the error locator polynomial. The degree of the error locator polynomial corresponds to the estimated number of errors. The coefficients of the t-th degree error locator polynomial are expressed as σ i (i is an integer that satisfies 0≦i≦t). The t-th degree error locator polynomial σ(x) is expressed, for example, by the following equation (1). Note that the degree of the error locator polynomial does not necessarily have to be output. In the error locator polynomial, the non-zero coefficient (σ i ≠0) corresponds to the number of errors, that is, argmax(σ i ≠0) corresponds to the number of errors. Therefore, the error position calculation unit 103 can estimate the number of errors by observing the coefficients of the error position polynomial.

number

[0031] Coefficient σ i is expressed in the Galois field GF(2 m ) where α is a primitive element of a Galois field. Non-zero elements of a Galois field can be expressed as powers of the primitive element α.

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[0032] The error location calculation unit 103 calculates an error location using the error location polynomial calculated by the error location polynomial calculation unit 102. The process of calculating the error location (searching process) may be realized by any method, but for example, Chien search can be used. Chien search is a method of sequentially substituting values ​​into the error location polynomial and searching for the error location based on the value (root of the error location polynomial) that makes the output value of the error location polynomial 0.

[0033] The correction unit 104 performs error correction by inverting (bit flipping) the bit at the error position calculated by the search process.

[0034] The error location calculation unit 103 is realized by, for example, a register, an adder, a multiplier, a selector, and other computing units. The syndrome calculation unit 101 and the error location polynomial calculation unit 102 are also realized by, for example, a register, an adder, a multiplier, a selector, and other computing units. The correction unit 104 is realized by, for example, an adder that adds a bit sequence reflecting the error location information output from the error location calculation unit 103 and a read sequence, but may be realized by other computing units. Here, the bit sequence reflecting the error location information corresponds to, for example, a binary vector that is the output of a polynomial evaluation unit (described later). Furthermore, when the error location calculation unit 103 outputs a root of an error location polynomial as the error location information, the correction unit 104 may be realized by a computing unit that inverts the bit of the error location corresponding to the root. The register is realized by, for example, a logic circuit such as a flip-flop. The adder, multiplier, selector, and other computing units are realized by, for example, a logic circuit.

[0035] The Chien search is a technique for searching for an error location by sequentially substituting values ​​into an error location polynomial, and is sometimes configured to execute the substitution process in parallel in order to further reduce latency.

[0036] Here, a specific example of the parallelized assignment process will be described. FIG. 3 is a diagram showing a comparative example of the configuration of an error position calculation unit (hereinafter, error position calculation unit 103C) that parallelizes the assignment process. As shown in FIG. 3, the error position calculation unit 103C includes a coefficient update unit 450 and a polynomial evaluation unit 400.

[0037] Hereinafter, the degree of parallelism (number of parallel operations) of the assignment process is denoted as p. p can be interpreted as corresponding to the number of assignment values input in parallel among the assignment values input to the error position polynomial. p is an integer satisfying 1 ≤ p < n. n is an integer of 2 or more representing the code length (bits) of the error correction code. The number of cycles r in which the assignment process is repeated is calculated by r = ceiling(n / p). ceiling(x) is a ceiling function that outputs the smallest integer greater than or equal to x.

[0038] The coefficient update unit 450 includes t selectors 453-1 to 453-t, (t + 1) registers 451-0 to 451-t, and t multipliers 452-1 to 452-t.

[0039] The selector 453-i (here, i is an integer satisfying 1 ≤ i ≤ t) outputs either the coefficient σ i or the output of the multiplier 452-i to the register 451-i.

[0040] The registers 451-0 to 451-t are composed of storage elements such as flip-flops, for example. When the coefficients of the error position polynomial are elements of the Galois field GF(2 m ), each element is represented by m bits. Therefore, each register 451-0 to 451-t is a 5-bit storage element.

[0041] The register 451-0 stores the coefficient σ0 of the 0th order. The register 451-i stores the value input from the selector 453-i for one cycle period and outputs it to the multiplier 452-i and the subsequent polynomial evaluation unit 400. For example, in the j-th cycle (j is an integer satisfying 0 ≤ j ≤ r - 1), the registers 451-0 to 451-t store the coefficients σ0 (j) ~σ t(j) (j) is a symbol indicating that it is the value of the jth cycle.

[0042] The registers 451-i (where i is an integer satisfying 1≦i≦t) except for the register 451-0 may be implemented with a selector 453-i and a multiplier 452-i.

[0043] Next, a description will be given of the operation of the coefficient update unit 450. At the start of operation, all registers 451-0 to 451-t are initialized to store values ​​of 0. Furthermore, all selectors 453-i are set to output the coefficients input from the error locator polynomial calculation unit 102 to the registers 451-i.

[0044] The coefficient σ of the error location polynomial input from the error location polynomial calculation unit 102 i is stored in the corresponding register 451-i via the selector 453-i. The coefficient σ0 does not have a corresponding selector, so it is stored directly in the register 451-0. (0) =σ0, σ1 (0) =σ1, , σ t (0) =σ t The coefficients are set as follows:

[0045] The assignment process is repeated r times, starting from cycle 0 (j=0). In cycle 0, all selectors 453-i are set to output the value input from multiplier 452-i to the corresponding register 451-i. The values ​​σ0 stored in registers 451-0 to 451-t are (0) ~σ t (0) is output to the polynomial evaluation unit 400. (0) Excluding σ1 (0) ~σ t (0) is output to the corresponding multiplier among the multipliers 452-1 to 452-t. The multiplier 452-i multiplies the input value by α ip For example, when the parallelism p=5, the multipliers 452-1, 452-2, and 452-t multiply α 5 , α10 , α t5 The value after the multiplication process by the multiplier 452-i is input to the register 451-i via the selector 453-i. (1) =σ0, σ1 (1) =σ1 (0) α 5 , σ2 (1) =σ2 (0) α 10 , , σ t (1) =σ t (0) α t5 , and each coefficient is set as follows. (j) The value of is not updated from the input value σ0 in any cycle.

[0046] In the subsequent j cycles (j=1, 2, , r-1), the same process as in the 0 cycle is performed to obtain σ0 (j+1) =σ0, σ1 (j+1) =σ1 (j) α 5 , σ2 (j+1) =σ2 (j) α 10 , , σ t (j+1) =σ t (j) α t5 The coefficients are set as follows:

[0047] Next, a description will be given of the configuration of the polynomial evaluation unit 400. As shown in Fig. 3, the polynomial evaluation unit 400 includes p evaluation units 401-1 to 401-p. The evaluation units 401-1 to 401-p evaluate the error locator polynomial σ input from the coefficient update unit 450. (j) For the argument x of (x), the element α q+s Substituting the error locator polynomial value σ (j) (α q+s ) is evaluated to see if it becomes 0. (j) (x) means the error location polynomial output in the jth cycle. q is a number between 0 and 2. ms is an integer between 0 and p-1. For example, q can be set to 0, but the value of q may be changed as appropriate depending on the implementation. s is an integer between 0 and p-1.

[0048] The evaluation units 401-1 to 401-p have the same functions except that they use different substitution values. The following mainly describes the configuration of the evaluation unit 401-1. Note that the evaluation unit 401-1 corresponds to s=0. The other evaluation units 401-2 to 401-p correspond to a configuration in which s (=0) of the evaluation unit 401-1 is replaced with the corresponding value (1 to p-1).

[0049] As shown in FIG. 3, the evaluation unit 401-1 includes t multipliers 402-1 to 402-t, an adder 403, and a comparison circuit 404.

[0050] The multiplier 402-i (i is an integer satisfying 1≦i≦t) multiplies the corresponding coefficient σ i (j) To, α i(q+s) The adder 403 multiplies the multiplication results of the t multipliers 402-1 to 402-t by the coefficient σ0 (j) A comparison circuit 404 outputs 1 if the output of the adder 403 is 0, and outputs 0 if the output is not 0.

[0051] Next, the operation of the polynomial evaluation unit 400 will be described. In each of j cycles (j=0 to r-1), the coefficient σ0 (j) ~σ t (j) Among them, coefficient σ1 excluding coefficient σ0 (j) ~σ t (j) For each, α by the corresponding multiplier 402-1 to 402-t i(q+s) The t multiplication results are output to the adder 403.

[0052] The adder 403 adds the t multiplication results and σ0 (j)and outputs the addition result to the comparison circuit 404. The comparison circuit 404 determines whether the value input from the adder 403 is 0 or not, and outputs 1 if it is 0, and 0 otherwise.

[0053] The polynomial evaluation unit 400 includes p evaluation units 401-1 to 401-p that perform such operations. As described above, the p evaluation units 401-1 to 401-p evaluate α i(q+s) Specifically, s takes a different value from 0 to p-1 for each of the evaluators 401-1 to 401-p. The polynomial evaluator 400 outputs a binary vector of length p whose elements are binary values ​​(1 or 0) output from each of the p evaluators 401-1 to 401-p.

[0054] Next, a specific example of the evaluation of the error locator polynomial will be explained. In the following example, the degree of the error locator polynomial is 4 (t=4), the parallelism p is 5, the code length n of the error correcting code is 30, and the degree m of the primitive polynomial is 5 (the Galois field is GF(2 5 )).

[0055] GF(2 5 The primitive polynomial that constitutes the error locator polynomial 102 is expressed by the following equation (3), and the root of the primitive polynomial is expressed as α. The error locator polynomial obtained by the error locator polynomial calculation unit 102 is expressed by the following equation (4).

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[0056] The error location polynomial σ(x) in equation (4) has four roots because it is of degree 4. Therefore, in the error location calculation, 5 ) elements 1, α, α 2 , , α 29 Four elements that are roots of the error locator polynomial σ(x) are searched for in

[0057] When the parallelism is p=5, the error locator polynomial with five elements substituted simultaneously is evaluated in one cycle. Specifically, σ(x=α 5j+q ), σ(x=α 5j+q+1 ), σ(x=α 5j+q+2 ), σ(x=α 5j+q+3 ), σ(x=α 5j+q+4 ) is evaluated. In this example, j is the index of the cycle, which ranges from 0 to 5.

[0058] Next, the complexity of the circuit of the error-position calculation unit 103C will be described. In the error-position calculation unit 103C, the circuits that contribute to the complexity are multipliers, adders, and registers. In the example of Fig. 3, the coefficient update unit 450 includes t multipliers 452-1 to 452-t and (t+1) registers 451-0 to 451-t. The polynomial evaluation unit 400 includes p x t multipliers (t multipliers 402-1 to 402-t for each of the p evaluation units 401-1 to 401-p) and p x t adders. This is because one adder 403 corresponds to t adders with two inputs and one output.

[0059] From the above, the complexity of the error location calculation unit 103C is (p+1)×t multipliers, (t+1) registers, and p×t adders. In the case of a substitution process with a parallelism of 5 (p=5) for a 4th degree (t=4) error location polynomial, there are 24 multipliers, 5 registers, and 20 adders. Note that one register is a 5-bit storage element, so five registers will result in a 25-bit storage element. In the Galois field GF(2 m In the case of the error location calculation unit 103C for the error location polynomial on , one register becomes an m-bit storage element.

[0060] As a method for reducing the complexity of a circuit for error location calculation, a method for contracting a polynomial using affine decomposition has been proposed (for example, Non-Patent Document 1).

[0061] For example, the t-th degree error locator polynomial σ(x) can be transformed into the following equation (5) by applying affine decomposition, where k is an integer ranging from 0 to K. K is the smallest integer (ceiling((t-4) / 5)) that is equal to or greater than (t-4) / 5.

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[0062] (5) L in Eq. k (x) is expressed by the following equation (6): Furthermore, equation (6) can be transformed into the following equation (7): Note that Q in equation (7) is an m × m binary matrix equivalent to a squaring operation, and satisfies Qx = x.

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[0063] The second term on the right side of equation (5) corresponds to one or more affine polynomials obtained by decomposing the error locator polynomial. Each affine polynomial is a linearized polynomial L k (x) and the constant term σ 5k As shown in equation (7), the linearized polynomial L k (x) is a binary matrix (two-dimensional matrix) Δ k can be transformed into a form that multiplies x. In the following, the matrix Δ k is called the linearized polynomial matrix.

[0064] When t=4, k takes only the value 0, and the error locator polynomial to which the affine decomposition is applied is transformed as shown in the following equation (8). L0(x) in equation (8) is expressed as the following equation (9).

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[0065] As described above, L0(x) in equation (9) is a linearized polynomial, and can be calculated by multiplying x by the linearized polynomial matrix Δ0. The following equation (10) shows the error locator polynomial expressed in a format using the linearized polynomial matrix Δ0.

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[0066] Furthermore, GF(2 5 ), so Δ0 is a 5×5 binary matrix. m ), then Δ0 is an m×m binary matrix.

[0067] From the above, the complexity of the error locator polynomial σ(x) can be evaluated by the error locator polynomial σ(x) in equation (10). Equation (10) clearly has fewer multiplications and additions than equation (4).

[0068] Conventionally (for example, Non-Patent Document 1), application of affine decomposition to a configuration that evaluates error location polynomials in parallel has not been considered, and a method for applying affine decomposition to an error location calculation unit (hereinafter referred to as a parallel error location calculation unit) that calculates error polynomials in parallel, such as the error location calculation unit 103C, has not been made clear.

[0069] In the parallel error location calculation unit, the evaluation unit that performs the substitution process into the polynomial uses a fixed value α q+s The circuit is to substitute the coefficient σ of the polynomial i (j) is updated every cycle in the coefficient update unit. When affine decomposition is applied to such a parallel error location calculation unit, the linearization polynomial L0(x) also needs to be updated every cycle.

[0070] As a configuration for applying affine decomposition to the parallel error location calculation unit, for example, a configuration in which the linearization polynomial is updated within the evaluation unit can be considered. In such a configuration, since each of the multiple evaluation units needs to individually perform the calculation for updating the linearization polynomial, it is not possible to efficiently reduce the circuit size (complexity).

[0071] Therefore, in this embodiment, a configuration of a parallel error location calculation unit to which affine decomposition is applied, which can further reduce the complexity, will be described.

[0072] Fig. 4 is a diagram showing an example of the configuration of the error position calculation unit 103 according to the embodiment. The error position calculation unit 103 in Fig. 4 is different from the error position calculation unit 103C in Fig. 3 and corresponds to an error position calculation unit to which affine decomposition is applied.

[0073] 4, the error position calculation unit 103 includes a coefficient update unit 450, a matrix calculation unit 260, and a polynomial evaluation unit 200. The coefficient update unit 450 has the same configuration as the coefficient update unit 450 included in the error position calculation unit 103C in FIG. 3, and therefore the same reference numerals are used and the description thereof will be omitted.

[0074] The matrix calculation unit 260 calculates a linearization polynomial matrix, which is a binary matrix corresponding to the linearization polynomial. For example, the matrix calculation unit 260 calculates a linearization polynomial matrix Δ k (j) The matrix calculation unit 260 will be described in detail below with reference to the following drawings, taking the cases of t=4 and t=7 as examples.

[0075] As shown in the above equation (7), in the calculation of the linearized polynomial matrix, the coefficient σ for i=5k+1, 5k+2, 5k+4, 5k+8 i (j) Therefore, the coefficient update unit 450 outputs the coefficients σ corresponding to i=5k+1, 5k+2, 5k+4, and 5k+8. i (j) is input to the matrix calculation unit 260 (input 271 in FIG. 4). i (j)is input from the coefficient update unit 450 to the polynomial evaluation unit 200. The matrix calculation unit 260 outputs the linearized polynomial matrix Δ k (j) (k=0 to K) are calculated and output to the polynomial evaluation unit 200 (output 272 in FIG. 4). Among the multiple coefficients of the error locator polynomial, the coefficients used in the matrix calculation (coefficients σ corresponding to i=5k+1, 5k+2, 5k+4, 5k+8) are i (j) ) will be referred to as the target coefficient below. Furthermore, among the multiple coefficients of the error locator polynomial, coefficients other than the target coefficient will be referred to as non-target coefficients below.

[0076] The polynomial evaluation unit 200 evaluates in parallel the values ​​of the error locator polynomials into which the substitution values ​​have been substituted. The polynomial evaluation unit 200 includes p evaluation units 201-1 to 201-p.

[0077] The evaluation units 201-1 to 201-p calculate the error location polynomial σ (j) For the argument x of (x), the element α q+s Substituting the error locator polynomial value σ (j) (α q+s ) becomes 0. In this embodiment, the evaluation units 201-1 to 201-p include a circuit configured to use the linearized polynomial matrix output from the matrix calculation unit 260.

[0078] An example will be described using the evaluation unit 201-1 corresponding to s = 0. The other evaluation units 201-2 to 201-p correspond to circuits in which s (= 0) of the evaluation unit 201-1 is replaced with the corresponding value (1 to p-1).

[0079] As shown in FIG. 4, the evaluation unit 201-1 includes multipliers 211-1, 211-3, . . . , 211-t, an adder 203, and a comparison circuit 204.

[0080] In this embodiment, the m×m binary matrix (linearized polynomial matrix) output from the matrix calculation unit 260 and the α iIn some cases, a multiplication (hereinafter referred to as matrix multiplication) between a linearized polynomial matrix and α is performed. In the figures from FIG. 4 onward, matrix multiplication is represented by a symbol with a circled "*". The multiplier 211-1 multiplies a linearized polynomial matrix by α q This corresponds to a circuit that calculates a multiplication result (first multiplication result) obtained by matrix multiplying σ (corresponding to the first multiplication value based on the substituted value) and σ. Whether or not to perform matrix multiplication depends on the degree t of the error locator polynomial. Therefore, there may be cases where the multiplier 211-t in FIG. 4 performs matrix multiplication. In addition, the coefficient σ stored in the register 451-t t (j) may be output to the matrix calculation unit 260 as a target coefficient.

[0081] The multiplier 211-3 does not perform matrix multiplication, but corresponds to a circuit that performs multiplication of one or more evaluation terms other than the linearized polynomial that are included in the affine polynomial. For example, the multiplier 211-3 performs multiplication of α 3q (corresponding to the second multiplication value based on the substitution value) and the coefficient σ3 corresponding to the evaluation term other than the linearized polynomial (j) The multiplication result (second multiplication result) obtained by multiplying and is calculated. In this way, any of the non-target coefficients corresponds to the evaluation term.

[0082] The evaluation units 201-1 to 201-p of this embodiment do not need to have t multipliers like the evaluation units 401-1 to 401-p of FIG. 3, but have multipliers in a number corresponding to a portion of the t coefficients σ.

[0083] The adder 203 multiplies the multiplication results of the multipliers 211-1, 211-3, . . . , 211-t by the coefficient σ0 input from the coefficient update unit 450. (j) A comparison circuit 204 outputs 1 if the output of the adder 203 is 0, and outputs 0 if the output is not 0.

[0084] Next, a configuration example of the error location calculation unit 103 when t=4, p=5, and m=5 will be described. As described above, when t=4, the error location polynomial is expressed by equation (8) by applying affine decomposition. Fig. 5 is a diagram showing a configuration example of the error location calculation unit 103 for the error location polynomial of equation (8).

[0085] 5, the error position calculation unit 103 includes a coefficient update unit 450, a matrix calculation unit 260a, and a polynomial evaluation unit 200a. The coefficient update unit 450 is similar to the coefficient update unit 450 in FIGS. 3 and 4, except that t is set to 4.

[0086] The matrix calculation unit 260a calculates Δ0 (j) Calculation unit 261a is provided. Δ0 (j) The calculation unit 261a calculates the linearized polynomial matrix Δ (j) As shown in equation (9), when t=4, the coefficient σ1 for i=1, 2, 4 is calculated. (j) , σ2 (j) , σ4 (j) is used as the target coefficient. Therefore, the coefficient update unit 450 outputs the coefficient σ1 (j) , σ2 (j) , σ4 (j) is input to the matrix calculation unit 260a. (j) The calculation unit 261a) calculates Δ0 (j) is calculated and output to the polynomial evaluation unit 200a. (j) The details of the calculation unit 261a will be described later.

[0087] The polynomial evaluation unit 200a includes p evaluation units 201a-1 to 201a-p. An example of the evaluation unit 201a-1 will be described. The evaluation unit 201a-1 includes multipliers 211-1 and 211-3, an adder 203, and a comparison circuit 204.

[0088] The multiplier 211-1 multiplies the linearized polynomial matrix Δ (j) and α q The multiplier 211-3 multiplies the coefficient σ3 input from the coefficient update unit 450 by the coefficient σ3 (j) and α 3q and multiply (in Galois field GF(2 5 The adder 203 multiplies the multiplication results of the multipliers 211-1 and 211-3 and outputs the multiplication results. (j) Calculate the value obtained by adding

[0089] Figure 6 shows the Δ0 (j) 10 is a diagram illustrating an example of the configuration of the calculation unit 261a. Since m=5, the calculated Δ0 (j) is five elements Δ0 (j) [0], Δ0 (j) [1], Δ0 (j) [2], Δ0 (j) [3], Δ0 (j) [4]. Each of the five elements corresponds to a 5-by-1 vector. The linearized polynomial matrix Δ0 (j) corresponds to a 5-by-5 ​​matrix with five elements concatenated in the column direction.

[0090] Δ0 (j) Calculation unit 261a includes adders 602-0 and 602-g and multipliers 601-1-g, 601-2-g, and 601-3-g, where g is an integer ranging from 1 to 4 (corresponding to m-1).

[0091] The adder 602-0 calculates the coefficient σ1 (j) , σ2 (j) , σ4 (j) Add the result and subtract Δ0 (j) Output as [0].

[0092] The multiplier 601-1-g multiplies the coefficient σ (j) Multiplication value α 1×g (first multiplication unit). The multiplier 601-2-g multiplies the coefficient σ2 (j) Multiplication value α 2×g The multiplier 601-3-g multiplies the coefficient σ4 (j) Multiplication value α 4×g Multiplication value α 1×g , multiplication value α 2×g , multiplication value α 4×g corresponds to a predetermined multiplication value (third multiplication value) that differs depending on the plurality of target coefficients.

[0093] The adder 602-g adds the multiplication results (third multiplication results) of the multipliers 601-1-g, 601-2-g, and 601-3-g, and multiplies the sum by Δ0 (j) Output as [g].

[0094] Δ0 in Figure 6 (j) The calculation unit 261a calculates the matrix Δ0 (j) The basis for the calculation will be explained below.

[0095] The above equation (4) representing the fourth-order error locator polynomial σ(x) can be transformed into the following equation (11).

number

[0096] Here, x is expressed in the basis {b i When decomposed into x (where i is an integer from 0 to m-1), x can be expressed by the following formula (12).

number

[0097] Using equation (12), the matrix (xx 2 x 4 ) can be transformed into the following equation (13): Furthermore, by using equation (13), equation (11) can be expressed as the following equation (14).

number

number

[0098] Δ0[i] in equation (14) corresponds to the i-th column of the linearized polynomial matrix Δ0, and is expressed by the following equation (15).

number

[0099] Δ0 in Figure 6 (j) The calculation unit 261a calculates the basis {b i}, and α i This corresponds to a circuit that calculates the linearized polynomial matrix Δ0 as in equation (15) using

[0100] Next, the matrix multiplication in the evaluation units 201a-1 to 201a-p will be described. As described above, in the example of FIG. 5, the multiplier 211-1 multiplies the linearized polynomial matrix Δ0 (j) and α q This matrix multiplication corresponds to the multiplication in the second term on the right side of the second line in equation (14), for example, and is expressed by the following equation (16): (α q ) i is α q Represents the i-th bit of

number

[0101] That is, the matrix multiplication in equation (16) is α q Δ0 corresponding to the index i that is 1 when expressed as a vector (j) [i] corresponds to the result of adding [i] on GF(2). q Since is a constant value, the index that determines the column to be added does not change for each cycle. (j) The calculation unit calculates α for each of the evaluation units 201a-1 to 201a-p. q Δ0 corresponding to the index uniquely determined from (j) It can be configured as a circuit that multiplies [i].

[0102] FIG. 7 is a diagram for explaining an example of matrix multiplication in the evaluation units 201a-1 to 201a-p. It is assumed that each column of the linearized polynomial matrix Δ0 has a value as shown in equation 701. Equations 711 and 712 are expressed as follows: q (vector representation of the matrix multiplication) and the matrix multiplication formula in the evaluation unit.

[0103] Next, a configuration example of the error location calculation unit 103 when t=7, p=5, and m=5 will be described. When t=7, the error location polynomial is expressed by the following equation (17). Also, the error location polynomial obtained by applying affine decomposition to equation (17) is expressed by the following equation (18).

number

number

[0104] Δ0x and Δ1x in equation (18) are expressed by the following equations (19) and (20), respectively.

number

number

[0105] 8 is a diagram showing an example of the configuration of the error position calculation unit 103 for the error position polynomial of equation (18). As shown in FIG. 8, the error position calculation unit 103 includes a coefficient update unit 450, a matrix calculation unit 260b, and a polynomial evaluation unit 200b. The coefficient update unit 450 is the same as the coefficient update unit 450 in FIG. 3 and FIG. 4, except that t is specified as 7. Note that the coefficient update unit 450 in FIG. 8 calculates the coefficient σ1 (j) , σ2 (j) , σ4 (j) The functions related to this are described in a simplified form.

[0106] The matrix calculation unit 260b calculates Δ0 (j) Calculation unit 261a and Δ1 (j) Calculation unit 262b. Δ0 (j) The calculation unit 261a has the same functions as those in FIG. 5 when t=4, so it is given the same reference numeral and the description thereof will be omitted.

[0107] When t=7, k takes the value of 0 or 1. Therefore, the matrix calculation unit 260b calculates the linearized polynomial matrix Δ k (j) As a result, Δ0 (j) and Δ1 (j) Calculate Δ1 (j) The calculation unit 262b calculates the linearized polynomial matrix Δ (j) This corresponds to a circuit that calculates

[0108] As shown in equation (20), Δ1 (j)In the calculation of i=6, 7, the coefficient σ6 (j) , σ7 (j) is used as the target coefficient. Therefore, the coefficient update unit 450 outputs the coefficient σ1 (j) , σ2 (j) , σ4 (j) In addition, the coefficient σ6 (j) , σ7 (j) is input to the matrix calculation unit 260a. Also, the matrix calculation unit 260b calculates Δ0 (j) and Δ1 (j) is calculated and output to the polynomial evaluation unit 200b. (j) The details of the calculation unit 262b will be described later.

[0109] Polynomial evaluation unit 200b includes p evaluation units 201b-1 to 201b-p. An example of evaluation unit 201b-1 will be described. Evaluation unit 201b-1 includes multipliers 211-1, 211-3, and 211-5, an adder 203b, and a comparison circuit 204.

[0110] The functions of the multipliers 211-1 and 211-3 are the same as those in FIG. 5. The evaluation unit 201b-1 calculates the linearized polynomial matrix Δ1 (j) The multiplier 211-5 corresponds to a circuit that performs the calculation of the fourth term on the right side of equation (18). The multiplier 211-5 includes a multiplier 221b-5, an adder 222b-5, and a multiplier 223b-5.

[0111] The multiplier 221b-5 multiplies the linearized polynomial matrix Δ (j) and α q The adder 222b-5 multiplies (matrix multiplies) the coefficient σ5 input from the coefficient update unit 450 by the first multiplication value σ5 (corresponding to the first multiplication value based on the substituted value) and outputs the multiplication result. (j) The multiplier 223b-5 adds the result of the addition by the adder 222b-5 and α 5q (corresponding to the first multiplication value based on the assigned value) and multiply (in the Galois field GF(2 m The multiplication result by the multiplier 223b-5 is output as the multiplication result (first multiplication result) of the multiplier 211-5.

[0112] The adder 203b adds the multiplication results of the multipliers 211-1, 211-3, and 211-5 together with the coefficient σ0 (j) Calculate the value obtained by adding

[0113] Figure 9 shows the Δ1 (j) 10 is a diagram illustrating an example of the configuration of the calculation unit 262b. Since m=5, the calculated Δ1 (j) is the five elements Δ1 (j) [0], Δ1 (j) [1], Δ1 (j) [2], Δ1 (j) [3], Δ1 (j) [4]. Each of the five elements corresponds to a 5-by-1 vector. The linearized polynomial matrix Δ1 (j) corresponds to a 5-by-5 ​​matrix with five elements concatenated in the column direction.

[0114] Δ1 (j) Calculation unit 262b includes adders 612-0 and 612-g and multipliers 611-1-g and 611-2-g, where g is an integer ranging from 1 to 4 (corresponding to m-1).

[0115] The adder 612-0 calculates the coefficient σ6 (j) , σ7 (j) Add the result and subtract Δ1 (j) Output as [0].

[0116] The multiplier 611-1-g multiplies the coefficient σ6 (j) Multiplication value α 1×g The multiplier 611-2-g multiplies the coefficient σ7 (j) Multiplication value α 2×g Multiplication value α 1×g , multiplication value α 2×g corresponds to a predetermined multiplication value (third multiplication value) that varies depending on a plurality of coefficients.

[0117] The adder 612-g adds the multiplication results of the multipliers 611-1-g and 611-2-g. In the example of FIG. 9, the addition result by the adder 612-g is Δ1 (j) It will be output as [g].

[0118] Δ1 in Figure 9 (j) The calculation unit 262b calculates the matrix Δ1 (j) The basis for the calculation will be explained below.

[0119] The above equation (17) representing the seventh-degree error locator polynomial σ(x) can be transformed into the following equation (21).

number

[0120] Using the above equation (12), the matrix (xx 2 ) can be transformed into the following equation (22): Furthermore, by using the above equations (13) and (22), equation (21) can be expressed as the following equation (23).

number

number

[0121] Δ1[i] in equation (23) corresponds to the i-th column of the linearized polynomial matrix Δ1, and is expressed by the following equation (24).

number

[0122] Δ1 in Figure 9 (j) The calculation unit 262b calculates the basis {b i}, and α i This corresponds to a circuit that calculates the linearized polynomial matrix Δ1 as in equation (24) using

[0123] Up to now, we have mainly explained the cases where t=4 or t=7, that is, where k is 0 or k is 0 and 1. t is not limited to 4 or 7, and can have any value. When t is a large value, k can take a value of 2 or more. In such cases, Δ0 (j) Calculation unit 261a and Δ1 (j)Similarly to the calculation unit 262b, Δ k (j) (k is an integer greater than or equal to 2) to calculate Δ k (j) That is, the matrix calculation unit 260 can calculate k Δ k (j) The device may be configured to include a calculation unit.

[0124] Next, a description will be given of the flow of the decoding process performed by the memory system 1. Fig. 10 is a flowchart showing an example of the decoding process in this embodiment.

[0125] The control unit 11 reads out the error correction code from the nonvolatile memory 20 and obtains the received word (step S101). The control unit 11 also instructs the decoding unit 18 to start decoding.

[0126] The syndrome calculation unit 101 of the decoding unit 18 calculates syndromes from the received word (step S102). The decoding unit 18 determines whether or not the values ​​of all the calculated syndromes are 0 (step S103).

[0127] If all the syndromes are 0 (step S103: Yes), it can be determined that there is no error in the received word, and the decoding unit 18 ends the decoding process. If all the syndromes are not 0 (step S103: No), the error locator polynomial calculation unit 102 calculates an error locator polynomial using the syndromes (step S104).

[0128] The error position calculation unit 103 searches for an error position using the calculated error position polynomial (step S105). The correction unit 104 corrects the error by inverting (bit flipping) the bit at the error position found by the search (step S106), and the decoding process ends.

[0129] In this embodiment, the matrix calculation unit 260 calculates a linearization polynomial matrix that can be used in common by multiple evaluation units. Therefore, for example, each of the multiple evaluation units does not need to have an individual function for updating the linearization polynomial, and the circuit size (complexity) can be further reduced.

[0130] (Second embodiment) In the first embodiment, the basis {b i} as α i In the second embodiment, a basis different from that in the first embodiment is used. Specifically, in the second embodiment, the basis {b i}, and α ip is used.

[0131] In the second embodiment, the configuration of the error position calculation unit is different from that in the first embodiment. An example of the configuration of the error position calculation unit 103-2 in the second embodiment will be described below.

[0132] Fig. 11 is a diagram showing an example of the configuration of the error position calculation unit 103-2 of the second embodiment. As shown in Fig. 11, the error position calculation unit 103-2 includes a coefficient update unit 450-2, a matrix calculation unit 260-2b, and a polynomial evaluation unit 200-2b. Note that in Fig. 11, for ease of explanation, some lines are drawn in formats other than solid lines (dotted lines, dashed-dotted lines, broken lines). Lines other than solid lines do not mean that values ​​are not input, but rather, like solid lines, mean that values ​​are input to each computing unit at the end of the arrow.

[0133] The coefficient update unit 450-2 updates the linearized polynomial matrix Δ k The coefficient σ used in the calculation of (i=5k+1, 5k+2, 5k+4, 5k+8) is the coefficient σ i (j) ) is updated. For example, when t=7, the linearized polynomial matrix Δ k The calculation of the coefficient σ1 (j) , σ2 (j) , σ4 (j) , σ6 (j) , σ7 (j)Therefore, the coefficient update unit 450-2 uses σ3 (j) , σ5 (j) As above, σ0 (j) The value of is not updated from the input value, but is output from coefficient update unit 450-2. Note that the following mainly describes an example where t=7, p=3, and m=5.

[0134] The matrix calculation unit 260-2b calculates a chain type Δ0 (j) Calculation unit 261-2a and chain type Δ1 (j) A calculation unit 262-2b is provided. (j) The calculation unit 261-2a calculates the linearized polynomial matrix Δ (j) This is a circuit that calculates the chain type Δ1 (j) The calculation unit 262-2b calculates the linearized polynomial matrix Δ (j) This is a circuit that calculates

[0135] Chain type Δ0 (j) Calculation unit 261-2a and chain type Δ1 (j) As described above, the calculation unit 262-2b calculates α, which includes the parallelism p as an exponent. ip base {b i} is used as Δ0 (j) Calculation unit 261a and Δ1 (j) This is different from the calculation unit 262b. (j) Calculation unit 261-2a and chain type Δ1 (j) The calculation unit 262-2b will be described in detail later. Note that the chained type means that it is configured to include arithmetic units that are chained so as to use values ​​calculated by adjacent arithmetic units, as will be described below.

[0136] Polynomial evaluation unit 200-2b includes p evaluation units 201-2b-1 to 201-2b-p. In the following, an example in which the degree of parallelism p=3 will be mainly described.

[0137] In this embodiment, as in the first embodiment, the linearized polynomial matrix Δ i (j) and α in two-dimensional vector representation qA matrix multiplication is performed, which is the multiplication of the linearized polynomial matrix Δ i (j) is an m×m (5×5 when m=5) binary matrix. The linearized polynomial matrix Δ i (j) Element Δ i (j) [g] is Δ i (j) is the binary vector in the gth column of (5-bit binary vector when m=5).

[0138] As shown above, matrix multiplication is q The binary vector Δ corresponding to the index (here, g) that is 1 when expressing i (j) [g] corresponds to the result of adding [g] over GF(2). In other words, in the addition equivalent to matrix multiplication, the corresponding binary vector Δ i (j) [g] is used.

[0139] Therefore, the element Δ i (j) The circuit of each evaluation unit can be implemented so that only [g] is connected to adders 221-2 and 222-2 to perform an operation equivalent to matrix multiplication. Figure 11 shows an example of each evaluation unit when implemented in this way. That is, in Figure 11, the linearized polynomial matrix Δ i (j) or element Δ i (j) Only the connection with [g] is expressed.

[0140] This will be explained using the example of the evaluation unit 201-2b-1. The evaluation unit 201-2b-1 includes adders 221-2 and 222-2, a multiplier 223-2, a multiplier 224-2, and an adder 225-2.

[0141] The adders 221-2 and 222-2 are connected to the linearized polynomial matrix Δ (j) , Δ1 (j)Among the elements (columns), an index (α q The coefficients input from the coefficient update unit 450-2 (adder 221-2 is σ0 (j) , adder 222-2 is σ5 (j) ) and . For example, in the example of FIG. 11, the index corresponding to the evaluation unit 201-2b-1 is (0,1,0,0,0), where all elements except the second element are 0. In this case, the adder 221-2 adds the linearized polynomial matrix Δ0 (j) The second column element of Δ0 (j) [1] and coefficient σ0 (j) The adder 222-2 adds the linearized polynomial matrix Δ (j) The second column element of Δ1 (j) [1] and coefficient σ5 (j) Add and.

[0142] In the case of the evaluation unit 201-2b-2, in which the corresponding indexes are all 0 except for the fifth element (0,0,0,0,1), the adders 221-2 and 222-2 of the evaluation unit 201-2b-2 calculate the Δ0 (j) [4], Δ1 (j) Add [4] to each.

[0143] When the corresponding index is (1, 1, 0, 0, 1) as in the evaluation unit 201-2b-3 (corresponding to the evaluation unit 201-2b-p when p=3), the adder 221-2 of the evaluation unit 201-2b-3 calculates Δ0 (j) [0], Δ0 (j) [1], Δ0 (j) [4], and the adder 222-2 adds Δ1 (j) [0], Δ1 (j) [1], Δ1 (j) Add [4].

[0144] In this way, α q The binary vector Δ corresponding to the index g that is 1 when i (j)[g] is coupled to adders 221-1 and 222-2. That is, adders 221-1 and 222-2 couple the combined binary vector Δ i (j) [g] (adder 221-2 is Δ0 (j) [g], adder 222-2 is Δ1 (j) [g]) is added.

[0145] In FIG. 11, when i=1 (Δ1 (j) ) only expresses the coupling with the adder 222-2 for each element, but (j) ), only the elements used in the operation are coupled to adder 221-2.

[0146] The multiplier 223-2 multiplies the coefficient σ5 input from the coefficient update unit 450-2. (j) and a multiplication value α according to the evaluation unit 201-2b-1. 3q In the case of the evaluation unit 201-2b-2 and the evaluation unit 201-2b-3, the multiplication value is α 3(q+1) , α 3(q+2) can be replaced by

[0147] The multiplier 224-2 multiplies the result of addition by the adder 222-2 by a multiplication value α according to the evaluation unit 201-2b-1. 5q In the case of the evaluation unit 201-2b-2 and the evaluation unit 201-2b-3, the multiplication value is α 5(q+1) , α 5(q+2) can be replaced by

[0148] The adder 225-2 adds the addition result from the adder 221-2, the multiplication result from the multiplier 223-2, and the multiplication result from the multiplier 224-2.

[0149] Although omitted in FIG. 11, the evaluation unit 201-2b-1 may include a comparison circuit (corresponding to the comparison circuit 204) that outputs 1 when the output of the adder 225-2 is 0 and outputs 0 when the output is not 0.

[0150] Figure 12 shows the chain type Δ1 (j)10 is a diagram illustrating an example of the configuration of a calculation unit 262-2b. (j) The calculation unit 262b includes adders 612-0 and 612-g, multipliers 611-1-g and 611-2-g, a multiplier 613-f, a selector 614-f, and a register 615-e. g is an integer ranging from 1 to 4+r-1. f is an integer ranging from 0 to 4+r-2. e is an integer ranging from 0 to 4+r-1. r represents the number of cycles as described above and is calculated by r=ceiling(n / p).

[0151] The adders 612-0 and 612-g and the multipliers 611-1-g and 611-2-g are the same as those of the first embodiment. (j) Since the configuration is the same as that in the calculation unit 262b, the same reference numerals are used and the description will be omitted.

[0152] The multiplier 613-f multiplies the multiplication value α 5p The second multiplier multiplies the fourth multiplied value by the value stored in register 615-(f+1). The value stored in register 615-(f+1) corresponds to the value calculated in the previous cycle by the calculator adjacent to multiplier 613-f (multiplier 613-(f+1)).

[0153] In the 0th cycle (j=0), the selector 614-f selects the addition result by the adder 612-f, and in the 1st cycle and thereafter (j=1 to r, the second cycle and thereafter), the selector 614-f selects the multiplication result (fourth multiplication result) by the multiplier 613-f.

[0154] Registers 615-0 to 615-(4+r-2) store the selection results of the selector 614-f. Register 615-(4+r-1) stores the addition result of the adder 612-(4+r-1).

[0155] Chain type Δ1 in Figure 12 (j) The calculation unit 262-2b calculates the matrix Δ1 (j) The basis for the calculation will be explained below.

[0156] When a certain cycle of substitution processing is performed using the error locator polynomial σ(x) in Equation (23), in the next cycle, x is replaced by xα p The following equation (25) is used to substitute x with xα p This corresponds to a modified version of equation (23) where

number

[0157] In the second embodiment, the basis {b i} to α ip This basis α ip Using this, equation (25) can be transformed into the following equation (26).

number

[0158] For example, x in equation (26) i (α 5p Δ1[i+1]) corresponds to multiplication by the multiplier 613-f. "i+1" corresponds to using the value calculated in the previous cycle by the adjacent calculator. (j) For the calculation part, multiplication from adjacent arithmetic units is α 5p However, the chain type Δ k (j) In the case of the calculation part, α 5kp is multiplied.

[0159] In addition, chain type Δ0 (j) The calculation unit 261-2a calculates Δ1 (j) The calculation unit 262b is a chain type Δ1 (j) Δ0 by the same method as the method for changing to the calculation unit 262-2b (j) This can be achieved by modifying the calculation unit 261a.

[0160] Δ1 in the first embodiment (j) The calculation unit 262b (FIG. 9) calculates the updated coefficient σ6 (j) , σ7 (j) In contrast, the chain type Δ1(j) The calculation unit 262-2b calculates the coefficient σ6 in the first cycle (0 cycle). (j) , σ7 (j) After this is entered, the coefficient σ6 (j) , σ7 (j) does not need to be entered. Instead, the chained type Δ (j) In the following cycles (1st cycle to r-1th cycle), the calculation unit 262-2b calculates the matrix Δ1 using the calculation result in the previous cycle. (j) Calculate.

[0161] Therefore, the number of multipliers and adders used in the calculation in the first cycle is 2(m-1) and m, respectively, which is the same as in the first embodiment. On the other hand, in the second and subsequent cycles, the linearized polynomial matrix Δ1 is calculated by operating only (m+r-2) multipliers (4+r-1 multipliers when m=5) (multipliers 613-0 to 613-(4+r-2)). (j) Therefore, power consumption can be reduced compared to the first embodiment.

[0162] As described above, this embodiment can reduce the scale of the circuit used for the process of searching for the root of the error locator polynomial by Chien search, etc. In other words, it can reduce the scale of the arithmetic circuit used for the calculation of the decoding process, etc.

[0163] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0164] 1. Memory System 10 Memory Controller 11 Control section 12 Data Buffers 13 Memory I / F 14 Encoding / Decoding Unit 15 Host I / F 16 Internal Bus 17 Encoding section 18 Decoding section 20 Non-volatile memory 30 hosts 101 Syndrome Calculation Unit 102 Error location polynomial calculation unit 103 Error location calculation unit 104 Corrections Department

Claims

1. a matrix calculation unit that calculates one or more matrices according to one or more linearization polynomials included in one or more affine polynomials obtained by decomposing an error locator polynomial for an error-correcting code having a code length of n bits (n is an integer of 2 or more); For each of the one or more matrices, calculate a first multiplication result obtained by multiplying the matrix by a first multiplication value based on an input value to be input into the error locator polynomial; calculating a second multiplication result obtained by multiplying a second multiplication value based on the substitution value by each of one or more evaluation terms other than the linearization polynomial that are included in the affine polynomial; outputting error location information based on a value obtained by adding the first multiplication result and the second multiplication result; p or more evaluation units (p is an integer satisfying 1≦p<n), the p or more evaluation units calculate the error location information using the substitution values ​​that are different from each other; Arithmetic circuit.

2. The matrix calculation unit a first multiplication unit that multiplies at least one or more target coefficients used in the matrix calculation among the coefficients of the error locator polynomial by a third multiplication value that is determined in advance and that differs depending on the target coefficient, and outputs a plurality of third multiplication results; an adder that adds a plurality of the third multiplication results and outputs the addition result, The arithmetic circuit according to claim 1 .

3. performing a process of substituting the substituted value in each of r cycles (r is the smallest integer equal to or greater than n / p); The matrix calculation unit a second multiplication unit that multiplies the matrix from one cycle before by a predetermined fourth multiplication value in a second or subsequent cycle and outputs a fourth multiplication result; a selector that selects either the addition result or the fourth multiplication result; a register that stores a selection result by the selector and outputs the selection result as the matrix, The arithmetic circuit according to claim 2 .

4. the evaluation term is any one of one or more non-target coefficients that are coefficients other than the target coefficients among the multiple coefficients of the error locator polynomial, The arithmetic circuit according to claim 2 .

5. the p or more evaluation units input the substitution values ​​different from each other to the error locator polynomial in parallel to calculate the error location information; The arithmetic circuit according to claim 1 .

6. The error correction code is a BCH (Bose-Chaudhuri-Hocquenghem) code or an RS (Reed-Solomon) code. The arithmetic circuit according to claim 1 .

7. a non-volatile memory; a memory controller that writes an error correction code having a code length of n bits (n is an integer of 2 or more) into the nonvolatile memory; The memory controller The error correction code is read from the nonvolatile memory. calculating a syndrome using the read error correction code as a received word; determining coefficients of an error locator polynomial based on the syndrome; a calculation circuit that uses the coefficients to output error position information; The arithmetic circuit comprises: a matrix calculation unit that calculates one or more matrices according to one or more linearization polynomials included in one or more affine polynomials obtained by decomposing an error locator polynomial for an error-correcting code having a code length of n bits (n is an integer of 2 or more); For each of the one or more matrices, calculate a first multiplication result obtained by multiplying the matrix by a first multiplication value based on an input value to be input into the error locator polynomial; calculating a second multiplication result obtained by multiplying a second multiplication value based on the substitution value by each of one or more evaluation terms other than the linearization polynomial that are included in the affine polynomial; outputting error location information based on a value obtained by adding the first multiplication result and the second multiplication result; p or more evaluation units (p is an integer satisfying 1≦p<n), the p or more evaluation units calculate the error location information using the substitution values ​​that are different from each other; Memory system.

8. A control method for controlling a nonvolatile memory, comprising: storing an error correction code having a code length of n bits (n is an integer of 2 or more) in the nonvolatile memory; reading the error correction code from the nonvolatile memory; calculating a syndrome using the read error correction code as a received word; determining coefficients of an error locator polynomial based on the syndrome; calculating one or more matrices corresponding to one or more linearization polynomials included in one or more affine polynomials obtained by decomposing an error locator polynomial for an error-correcting code having a code length of n bits (n is an integer of 2 or more); Each of p or more evaluation units (p is an integer satisfying 1≦p<n) For each of the one or more matrices, calculate a first multiplication result obtained by multiplying the matrix by a first multiplication value based on an input value to be input into the error locator polynomial; calculating a second multiplication result obtained by multiplying a second multiplication value based on the substitution value by each of one or more evaluation terms other than the linearization polynomial that are included in the affine polynomial; outputting error location information based on a value obtained by adding the first multiplication result and the second multiplication result; This includes: the p or more evaluation units calculate the error location information using the substitution values ​​that are different from each other; Control method.

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