Ion trap device and ion trap system

Abstract

To realize an ion trap integrated with optical circuits that improves the electrical and thermal environments.SOLUTION: An ion trap device 100 includes a trap chip 110 having a plurality of electrodes for spatially trapping atomic ions by applying AC and DC voltages to the plurality of electrodes, and an optical circuit chip 120 having an irradiation unit for irradiating the atomic ions with electromagnetic waves. The trap chip 110 and the optical circuit chip 120 are flip-chip integrated such that there is a hollow space between the trap chip 110 and the optical circuit chip 120, and the trap chip 110 suspends the atomic ions in this hollow space.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to an ion trap device and an ion trap system including the ion trap device. [Background technology]

[0002] Among the many quantum technologies in recent years, trapped ion technology has attracted attention as a promising platform for both quantum computing and quantum communication due to its high quantum manipulation precision, homogeneity, and the feasibility of optical connection. Trapped ion technology involves levitating atomic ions in an ultra-high vacuum using an electromagnetic field and controlling the quantum state of the atomic ions using electromagnetic waves such as lasers and microwaves.

[0003] Conventional ion trap quantum technology uses free-space optics, in which many optical elements are fixed on a vibration isolation table. In order to modularize ion trap quantum technology and realize the connection of many quantum nodes, a technology has been proposed in recent years in which the conventional free-space optics is replaced with an optical circuit consisting of optical elements on a small chip, integrating the optical circuit with the ion trap.

[0004] For example, Non-Patent Document 1 discloses a technique in which a window hole is provided in a substrate electrode for ion trapping (hereinafter referred to as a "trap chip"), a light-emitting element such as a grating is mounted directly below the trap chip, and a laser is irradiated from the light-emitting element through the window hole toward atomic ions trapped by the trap chip. Non-Patent Document 2 discloses a technique in which a superconducting nanowire single-photon detector (SNSPD) for measuring the quantum state of atomic ions is placed in a relatively large window hole provided in the trap chip, and the entire substrate is cooled to a low temperature for operation. [Prior art documents] [Non-patent literature]

[0005] [Non-Patent Document 1] R. J. Niffenegger, J. Stuart, C. Sorace-Agaskar, D. Kharas, S. Bramhavar, C. D. Bruzewicz, W. Loh, R. T. Maxson, R. McConnell, D. Reens, G. N. West, J. M. Sage, and J. Chiaverini, “Integrated multi-wavelength control of an ion qubit,” Nature volume 586, pp.538-542 (2020).

Non-Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0006] However, in conventional ion traps integrated with optical circuits, an oscillating voltage of at least 10 V is constantly applied to the substrate electrode to form a potential for ion trapping, which causes the following two problems. First, the electric field generated by the oscillating voltage fills the entire trap chip, which may introduce noise into the optical elements of the optical circuit and cause malfunctions. Second, almost all of the power of the oscillating voltage (on the order of 1 W to 10 W) is consumed in the trap chip, which may cause a temperature rise in the entire chip and a deterioration in the performance of the optical elements. In particular, the SNSPD made of a superconductor disclosed in Non-Patent Document 2 cannot operate if the temperature of the entire chip rises.

[0007] The present invention has been made in view of the above problems, and has as its object to realize an ion trap integrated with an optical circuit that improves the electrical and thermal environments. [Means for solving the problem]

[0008] The ion trap device according to the present invention comprises a trap chip having a plurality of electrodes for spatially trapping atomic ions by applying AC and DC voltages to the plurality of electrodes, and an optical circuit chip having an irradiation unit for irradiating the atomic ions with electromagnetic waves. The trap chip and the optical circuit chip are flip-chip integrated so that there is a hollow space between them, and the trap chip levitates the atomic ions in the hollow space.

[0009] An ion trap system according to the present invention comprises the above-described ion trap device and an optical detection device for detecting the quantum state of atomic ions. [Effects of the Invention]

[0010] According to the present invention, the trap chip and the optical circuit chip are flip-chip integrated so that there is a hollow space between the trap chip and the optical circuit chip, thereby making it possible to avoid the effects of the electric field and heat caused by the ion trap. [Brief explanation of the drawings]

[0011] [Figure 1] 1 is a perspective view of an ion trap device according to an embodiment of the present invention. [Figure 2A] FIG. 2 is a cross-sectional view taken along the line IIA-IIA in FIG. 1. [Figure 2B] FIG. 2 is a cross-sectional view taken along the line IIB-IIB in FIG. [Figure 2C] FIG. 2 is a cross-sectional view taken along the line IIC-IIC in FIG. [Figure 3] 1 is a schematic diagram of an ion trap system according to an embodiment of the present invention. [Figure 4] 1 is an example of an electrode pattern of a trap chip. [Figure 5] 1 is an example of a circuit configuration of an optical circuit chip. [Figure 6] FIG. 1 is a schematic diagram of laser irradiation of atomic ions by an optical circuit chip. [Figure 7] 10 is a graph showing the film thickness dependency of the shielding effect of a metal film. [Figure 8] FIG. 2 is a schematic diagram showing the results of a thermal analysis of an ion trap device. DETAILED DESCRIPTION OF THE INVENTION

[0012] Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. The same or similar components are designated by the same reference numerals throughout the drawings. The drawings are schematic, and the relationship between planar dimensions and thickness, and the thickness ratio of each component, differ from the actual ones. Furthermore, it goes without saying that the dimensional relationships and ratios of each component differ between the drawings.

[0013] FIG. 1 shows a perspective view of an ion trap device 100 according to this embodiment, FIG. 2A shows a cross-sectional view taken along the line IIA-IIA in FIG. 1, FIG. 2B shows a cross-sectional view taken along the line IIB-IIB in FIG. 1, and FIG. 2C shows a cross-sectional view taken along the line IIC-IIC in FIG. 1.

[0014] The ion trap device 100 is housed in a vacuum chamber and includes a trap chip 110, which is a substrate electrode for spatially trapping atomic ions, and an optical circuit chip 120 that irradiates the atomic ions with electromagnetic waves such as a laser. The trap chip 110 and the optical circuit chip 120 are flip-chip integrated so that there is a hollow space between them. The trap chip 110 suspends the atomic ions in the hollow space.

[0015] As shown in FIG. 2A, the trapping chip 110 and the optical circuit chip 120 are bonded via spacers 230 and 232. This aligns the trapping chip 110 and the optical circuit chip 120 in the direction perpendicular to the surface. The spacers 230 and 232 are made of a metal (e.g., a eutectic material such as PbCu) or an insulator (e.g., SiO2, Al2O3) and are rectangular parallelepiped or cylindrical, but are not limited to these materials and shapes. The height (length in the direction perpendicular to the surface) of the spacers 230 and 232 is, for example, 100 μm to 500 μm, but is not limited to this. The number of spacers may be one or more.

[0016] The trapping chip 110 has three holes 112, 114, and 116 (see FIGS. 2B and 2C) for in-plane alignment with the optical circuit chip 120. The optical circuit chip 120 has three holes 122, 124, and 126 (see FIGS. 1, 2B, and 2C) for in-plane alignment with the trapping chip 110.

[0017] As shown in FIGS. 2B and 2C, alignment components 242 are inserted into holes 112 and 122, alignment components 244 are inserted into holes 114 and 124, and alignment components 246 are inserted into holes 116 and 126. This structure aligns the trap chip 110 and the optical circuit chip 120 in the in-plane direction. Examples of alignment components 242, 244, and 246 include rod-shaped members such as pins. In FIG. 1, alignment components 242, 244, and 246 are omitted. Note that although FIGS. 1, 2B, and 2C show examples in which each chip has three holes, more than three holes may be included. Also, although FIGS. 2B and 2C show examples in which each hole is a through-hole, they do not have to be through-holes as long as the structure allows for alignment.

[0018] The trap chip 110 includes a substrate 210 and a conductive film 212 laminated on the substrate 210 and having an electrode pattern for ion trapping (see FIG. 4). The substrate 210 is made of a semiconductor or insulator such as Si, SiO2, SiC, or Al2O3, and has a thickness of 100 μm to 2 mm. The conductive film 212 is made of a metal such as Au, Al, or Nb, and has a thickness of 10 nm to 10,000 nm.

[0019] The optical circuit chip 120 includes a substrate 220, a first low refractive index layer 222 stacked on the substrate 220, a high refractive index layer 224 stacked on the first low refractive index layer 222, a second low refractive index layer 226 stacked on the high refractive index layer 224, and a metal protective film 228 stacked on the second low refractive index layer 226. By flipping the optical circuit chip 120 (face down), a structure is formed in which the conductive film 212 of the trap chip 110 and the metal protective film 228 of the optical circuit chip 120 face each other.

[0020] The substrate 220 is made of a semiconductor or insulator such as Si, SiO2, or SiC, and has a thickness of 100 μm to 2 mm. The first low-refractive index layer 222 and the second low-refractive index layer 226 are made of a low-refractive index material such as SiO2, and have a thickness of 100 nm to 20,000 nm. The high-refractive index layer 224 is made of a high-refractive index material such as SiN, SiC, or Si, and have a thickness of 20 nm to 1,000 nm. An optical circuit (see FIG. 5) is embedded in the first low-refractive index layer 222, the high-refractive index layer 224, and the second low-refractive index layer 226. The metal protective film 228 is made of a metal such as Au, Al, or Ti, and has a thickness of 10 nm to 10,000 nm. The metal protective film 228 protects the optical circuit chip 120 from the effects of electric fields and heat caused by ion traps.

[0021] The optical circuit chip 120 is provided with a slit 130 (see FIGS. 1 and 3) aligned with the arrangement of multiple atomic ions. As shown in FIG. 3, a photodetector 310 is disposed above the ion trap device 100, constituting an ion trap system 300. The photodetector 310 includes a photomultiplier tube, a CMOS camera, etc., and acquires a fluorescent image of the atomic ions floating between the trap chip 110 and the optical circuit chip 120 via the slit 130. This makes it possible to observe the quantum state of the atomic ions. Alternatively, the optical circuit chip 120 may have a transparent substrate, and an optical circuit (see FIG. 5) may be provided on the transparent substrate. If a transparent substrate is used, the slit 130 is not necessary.

[0022] 4 shows an example of the electrode pattern of the trapping tip 110. The trapping tip 110 has multiple electrodes, and by applying an alternating current (AC) voltage and a direct current (DC) voltage to these electrodes, atomic ions are trapped at a predetermined height (e.g., 30 μm to 200 μm) from the trapping tip 110.

[0023] FIG. 5 shows an example of the circuit configuration of the optical circuit chip 120. The optical circuit chip 120 includes an irradiation unit 540 that irradiates atoms or atomic ions with laser light. The irradiation unit 540 includes gratings 542, 544, 546, and 548 as light-emitting elements. The ion trap device 100 has four functions: ionization of atoms (e.g., Sr) introduced from an atom generator (not shown), laser cooling of atomic ions, quantum state control, and quantum state readout. The gratings 542, 544, 546, and 548 each emit laser light of a different wavelength depending on their function. Note that while FIG. 5 shows four gratings 542, 544, 546, and 548, the number of gratings is not limited.

[0024] Grating 542 is connected to spot size converter 522 via optical waveguide 532, and spot size converter 522 is connected to optical fiber 512. Spot size converter 522 converts the spot size of the laser light incident from optical fiber 512 to the size of optical waveguide 532. Similarly, grating 544 is connected to spot size converter 524 via optical waveguide 534, and spot size converter 524 is connected to optical fiber 514. Grating 546 is connected to spot size converter 526 via optical waveguide 536, and spot size converter 526 is connected to optical fiber 516. Grating 548 is connected to spot size converter 528 via optical waveguide 538, and spot size converter 528 is connected to optical fiber 518.

[0025] Window holes 612, 614, 616, and 618 (see FIG. 6) are provided on the surface of the optical circuit chip 120 facing the trapping chip 110, respectively, for transmitting the laser beams emitted from the gratings 542, 544, 546, and 548. As shown in FIG. 6, the laser beams that have passed through the window holes 612, 614, 616, and 618 are irradiated onto atoms or atomic ions 620.

[0026] According to the ion trap device 100 of this embodiment, the trap chip 110 and the optical circuit chip 120 are flip-chip integrated, thereby making it possible to avoid the influence of the electric field and heat caused by the ion trap.

[0027] Regarding the influence of the electric field, consider a situation in which two spatial regions are separated by a gold film and a 40 MHz plane electromagnetic wave is incident from one spatial region to the other. Figure 7 shows the results of estimating the film thickness dependence of the electric field attenuation in the other spatial region. From Figure 7, it can be seen that a film thickness of 1 μm (= 1000 nm) provides a shielding effect of 80 dB in terms of power, and that using a thicker metal film can be expected to further improve the shielding effect. Therefore, the electrical shielding effect can be improved by increasing the thickness of the metal protective film 228 of the optical circuit chip 120.

[0028] Regarding the influence of heat, Fig. 8 shows the results of a thermal analysis of the ion trap device 100. Here, it is assumed that radio frequency (RF) is consumed on the surface of the trap chip 110 as a heat source. The trap chip 110 has gold electrodes (conductive film 212) on a 1 mm-thick alumina substrate (substrate 210), and the optical circuit chip 120 has 4 μm-thick SiO2 and a gold thin film coating (metal protective film 228) on a 500 μm-thick silicon substrate (substrate 220). The bottom surface (substrate 210 side) of the trap chip 110 and the top surface (substrate 220 side) of the optical circuit chip 120 are thermally anchored to 300 K. The trap chip 110 and the optical circuit chip 120 are bonded via copper spacers 230 and 232, each 200 μm square and 300 μm high.

[0029] Figure 8 shows the heat distribution in the ion trap device 100 in a steady state. As can be seen from Figure 8, the temperature near the heat source rises to over 400 K, but the temperature rise in the optical circuit chip 120 is limited to a few K, meaning that the impact of the temperature rise of the heat source on the optical circuit chip 120 is minor. Therefore, by adopting flip-chip integration, it is possible to avoid performance degradation of the optical elements of the optical circuit chip 120 due to the temperature rise of the heat source. This opens up the possibility of stably mounting various optical elements (such as phase modulators and single-photon detectors) on the optical circuit chip 120.

[0030] Furthermore, flip-chip integration increases the degree of freedom in the design of each chip. In fact, it is possible to design and evaluate the trap chip 110 and the optical circuit chip 120 completely independently.

[0031] The present invention is not limited to the above-described embodiments, and various modifications are possible within the scope of the spirit of the present invention. Other embodiments and modifications made by those skilled in the art are also included in the present invention. [Explanation of symbols]

[0032] 100 Ion trap device 110 Trap Tip Holes 112, 114, and 116 120 Optical Circuit Chip 122, 124, 126 holes 130 slit 210 Substrate 212 Conductive film 220 board 222 First low refractive index layer 224 High refractive index layer 226 Second low refractive index layer 228 Metal protective film 230, 232 spacer 242, 244, 246 Alignment parts 300 Ion Trap System 310 Photodetector 512, 514, 516, 518 Optical Fiber 522, 524, 526, 528 Spot Size Converters 532, 534, 536, 538 optical waveguide 540 Irradiation unit 542, 544, 546, 548 Grating 612, 614, 616, 618 Window holes 620 atomic ions

Claims

1. a trap tip having a plurality of electrodes, which spatially traps atomic ions by applying AC voltages and DC voltages to the plurality of electrodes; an optical circuit chip having an irradiation unit that irradiates the atomic ions with electromagnetic waves, the trap chip and the optical circuit chip are flip-chip integrated so that there is a hollow space between the trap chip and the optical circuit chip; The trap tip suspends the atomic ions in the hollow space.

2. 2. The ion trap device according to claim 1, wherein the optical circuit chip has a metal protective film for protecting the optical circuit chip at least in an area other than the irradiation portion on the trap chip side.

3. 2. The ion trap device according to claim 1, wherein the optical circuit chip has a slit for observing the atomic ions.

4. 2. The ion trap device according to claim 1, wherein the optical circuit chip has a transparent substrate, and at least the irradiation unit is provided on the transparent substrate.

5. 2. The ion trap device according to claim 1, wherein the trap chip and the optical circuit chip are aligned in a direction perpendicular to the surface via a spacer.

6. the trap chip has at least three holes for aligning with the optical circuit chip in an in-plane direction; the optical circuit chip has at least three holes for in-plane alignment with the trap chip; 2. The ion trap device according to claim 1, wherein three alignment components are inserted into the at least three holes of the trap chip and the at least three holes of the optical circuit chip, respectively.

7. An ion trap device according to any one of claims 1 to 6; a photodetector for detecting the quantum state of the atomic ions; An ion trap system comprising:

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