Memory control circuit of micro computer

Abstract

To provide a memory control circuit of a micro computer that can enhance a processing speed of the micro computer in comparison with conventional arts.SOLUTION: A micro computer memory control circuit comprises: a memory read control circuit that stores an address where a processor reads a command from a memory, and a next address in a memory address register, stores a command of the address and a command of a next address in a command memory, and stores the next address and a command of the next address in a first command cache; and a cache controller that, when the processor reads a next command from the memory, if the address stored in the memory address register and the address stored in the first command cache are mismatched, stores the address stored in the memory address register, the command of the address and a frequency of the mismatch in a second command cache.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a memory control circuit for a microcomputer. [Background technology]

[0002] Patent Document 1 discloses a cache memory control technique that speeds up program processing by keeping the instruction sequence of a currently running program loop resident in cache memory until the end of loop processing. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 04-333929 Summary of the Invention [Problem to be solved by the invention]

[0004] When the addresses read from the CPU (Central Processing Unit) are consecutive, they can be read from the cache memory at high speed. However, when an interrupt occurs or a branch instruction is received, the addresses to be read are not consecutive, so reading is performed from the slow memory instead of the high-speed cache memory, which causes a problem of a decrease in the processing speed of the microcomputer.

[0005] The present disclosure has been made in consideration of the above points, and aims to provide a memory control circuit for a microcomputer that can improve the processing speed of a microcomputer compared to conventional microcomputers. [Means for solving the problem]

[0006] According to one aspect of the present disclosure, there is provided a memory control circuit for a microcomputer comprising a memory in which instructions are stored and a processor that reads and executes instructions from the memory, the memory control circuit comprising: a memory read control circuit that stores an address from which the processor reads instructions from the memory and a next address in a memory address register, an instruction at that address and an instruction at the next address in an instruction memory, and stores the next address and the instruction at the next address in a first instruction cache; and a cache controller that, when the processor reads the next instruction from the memory, if there is a mismatch between the address stored in the memory address register and the address stored in the first instruction cache, stores the address stored in the memory address register, the instruction at that address, and the number of times the mismatch occurred in a second instruction cache.

[0007] The memory control circuit of the microcomputer may further include a consecutive branch detector that, when the address stored in the memory address register and the address stored in the first instruction cache are mismatched when the processor reads the next instruction from the memory, causes the cache controller to delete the address stored in the memory address register from the second instruction cache if the address branches consecutively.

[0008] When the processor reads the next instruction from the memory and there is a mismatch between the address stored in the memory address register and the address stored in the first instruction cache, the cache controller may store the address stored in the memory address register, the instruction at that address, and the number of mismatches in a third instruction cache when the address, the instruction at that address, and the number of mismatches stored in the memory address register have been stored up to the upper limit of the storage area of ​​the second instruction cache. [Effects of the Invention]

[0009] According to the present disclosure, it is possible to provide a memory control circuit for a microcomputer that can improve the processing speed of the microcomputer compared to the prior art. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a diagram illustrating a configuration of a memory control circuit of a microcomputer according to an embodiment of the disclosed technique. [Figure 2] FIG. 10 is a diagram illustrating an example of information stored in a second instruction cache. [Figure 3] 2 is a diagram illustrating an instruction read operation of the microcomputer shown in FIG. 1. [Figure 4] 1 is a diagram illustrating a configuration of a memory control circuit of a microcomputer according to an embodiment of the disclosed technique. [Figure 5] FIG. 10 is a diagram illustrating an example of information stored in a third instruction cache. [Figure 6] FIG. 10 is a diagram illustrating a memory control circuit of a microcomputer as a comparative example of an embodiment of the disclosed technology. [Figure 7] 7 is a diagram illustrating an instruction read operation of the microcomputer shown in FIG. 6. DETAILED DESCRIPTION OF THE INVENTION

[0011] An example of an embodiment of the present disclosure will be described below with reference to the drawings. The same reference numerals are used throughout the drawings to designate identical or equivalent components and parts. The dimensional proportions of the drawings are exaggerated for illustrative purposes and may differ from the actual proportions.

[0012] Before describing the embodiments of the present disclosure, a memory control circuit of a microcomputer that serves as a comparative example to the embodiments of the present disclosure will be described. Figure 6 is a diagram illustrating a memory control circuit of a microcomputer that serves as a comparative example to the embodiments of the present disclosure.

[0013] The microcomputer shown in FIG. 6 includes a CPU 101, a bus 102, a memory address register 103, an instruction memory 104, an instruction cache 105, a memory read control circuit 106, and a memory 107.

[0014] The CPU 101 reads instructions from a memory 107 storing the instructions via a bus 102. A memory address register 103 stores address information of the instructions read by the CPU 101. An instruction memory 104 stores instruction information of the instructions read by the CPU 101. Storage in the memory address register 103 and the instruction memory 104 is performed by a memory read control circuit 106.

[0015] An instruction cache 105 reads and stores the memory address of the instruction next to the address currently being read by the CPU 101 from the memory 107. A memory read control circuit 106 stores address information of the instruction read by the CPU 101 in a memory address register 103 and instruction information in an instruction memory 104. The memory 107 stores instructions to be executed by the CPU 101.

[0016] When the memory read control circuit 106 stores address information in the memory address register 103 and instruction information in the instruction memory 104, the number of instructions read from the memory 107 is two, and the read cycle is two cycles.

[0017] When the CPU 101 goes to read the next instruction from the memory 107, it compares the address stored in the memory address register 103 with the address stored in the instruction cache 105, and if they match, the instruction is returned from the instruction cache 105 to the CPU 101. In this case, the CPU 101 reads from the instruction cache 105, which can be read at high speed, rather than from the slow memory 107, so that the read can be completed in one cycle.

[0018] 6, if the addresses read by the CPU 101 are consecutive, they can be read from the instruction cache 105 at high speed, but if an interrupt occurs or a branch instruction is received, the addresses read by the CPU 101 are not consecutive. In such cases, the CPU 101 reads from the slow memory 107 rather than from the instruction cache 105, which reduces the processing speed of the microcomputer.

[0019] Fig. 7 is a diagram showing the instruction read operation of the microcomputer shown in Fig. 6. In the first cycle T0, the CPU 101 has no data to read, and no data has been written in the instruction memory 104. Then, in cycle T0, the instruction cache 105 preemptively reads the next instruction address A3.

[0020] In cycle T1, the CPU 101 reads the instruction R1 from the instruction cache 105. The next address that the CPU 101 processes is A2. Also, in cycle T1, there is no data to be written to the instruction memory 104.

[0021] In cycle T2, instruction cache 105 stores address A3 and instructions R3 and R4. When CPU 101 starts reading address A3 at the timing of cycle T2, instruction R3 is already stored in instruction cache 105. Therefore, by reading instruction R3 from instruction cache 105 instead of memory 107 in cycle T3, instruction R3 can be read in one cycle.

[0022] Next, in cycle T3, instruction cache 105 stores instruction R4 at address A4, but the addresses do not match because CPU 101 reads address A21 in cycle T3. Therefore, CPU 101 reads instruction R21 from instruction memory 104 two cycles later in cycle T5.

[0023] In the subsequent cycle T7, the instruction cache 105 stores the instruction R24 at the address A24, but the CPU 101 reads the address A21 in cycle T7, so the addresses do not match. Therefore, the CPU 101 reads the instruction R21 from the instruction memory 104 in cycle T9, two cycles later.

[0024] In this way, when the address read by CPU 101 differs from the address stored in instruction cache 105, CPU 101 will read the instruction two cycles later instead of one cycle later, resulting in a decrease in processing speed. To avoid the decrease in processing speed, one method focuses on branch instructions and, after CPU 101 reads the branch instruction, pre-reads an instruction from the branch destination address prior to executing the branch instruction. However, if the address is switched by an interrupt, the first instruction is read from memory 107, and therefore, this method is not sufficiently effective. Furthermore, if highly accurate branch prediction is attempted, the circuit size increases.

[0025] Therefore, in an embodiment of the present disclosure, an instruction cache is added, the address and instruction when a branch is detected are stored in the added instruction cache, and the instruction is read out at high speed the next time a branch at the same address is detected, thereby providing a memory control circuit for a microcomputer that can improve processing speed compared to the configuration shown in FIG.

[0026] FIG. 1 is a diagram illustrating the configuration of a memory control circuit of a microcomputer according to an embodiment of the present disclosure.

[0027] The microcomputer shown in FIG. 1 includes a CPU 1, a bus 2, a memory address register 3, an instruction memory 4, a first instruction cache 5, a memory read control circuit 6, a memory 7, a cache controller 9, and a second instruction cache 11.

[0028] CPU 1 reads instructions from memory 7, which stores the instructions, via bus 2. Memory address register 3 stores address information of the instructions read by CPU 1. Instruction memory 4 stores instruction information of the instructions read by CPU 1. Storing in memory address register 3 and instruction memory 4 is performed by memory read control circuit 6.

[0029] The first instruction cache 5 reads and stores the memory address and instruction of the instruction next to the address currently being read by the CPU 1 from the memory 7. The memory read control circuit 6 stores the address information of the instruction read by the CPU 1 in the memory address register 3 and the instruction information in the instruction memory 4. The memory 7 stores the instructions to be executed by the CPU 1.

[0030] In response to the detection of consecutive instruction branches by the consecutive branch detector 8, the cache controller 9 stores memory addresses and instructions in the second instruction cache 11. The second instruction cache 11 stores memory addresses, instructions, and the number of branch occurrences.

[0031] When CPU 1 goes to read the next instruction from memory 7, it compares the address stored in memory address register 3 with the address stored in first instruction cache 5, and if they match, the instruction is returned from instruction cache 5 to CPU 1. When CPU 1 goes to read the next instruction from memory 7, if the address stored in memory address register 3 does not match the address stored in first instruction cache 5, a branch detection signal is passed from first instruction cache 5 to cache controller 9.

[0032] 2 is a diagram showing an example of information stored in the second instruction cache 11. Upon receiving a branch detection signal, the cache controller 9 stores the post-branch memory address, instruction, and number of occurrences in the second instruction cache 11. That is, each time a branch detection signal is issued, the post-branch memory address, instruction, and number of occurrences are stored in the second instruction cache 11. If the address is already stored in the second instruction cache 11, the cache controller 9 increments the number of occurrences of that address.

[0033] Figure 3 is a diagram showing the instruction read operation of the microcomputer shown in Figure 1. In the first cycle T0, the CPU 1 has no data to read, and no data has been written to the instruction memory 4. Then, in cycle T0, the first instruction cache 5 proactively reads the next instruction address A3.

[0034] In cycle T1, CPU1 reads instruction R1 from the first instruction cache 5. The next address that CPU1 processes is A2. Also, in cycle T1, there is no data to be written to the instruction memory 4.

[0035] In cycle T2, first instruction cache 5 stores address A3 and instructions R3 and R4. When CPU 1 starts reading address A3 at cycle T2, instruction R3 is already stored in instruction cache 5, so by reading instruction R3 from first instruction cache 5 instead of memory 7 in cycle T3, instruction R3 can be read in one cycle.

[0036] Next, in cycle T3, the first instruction cache 5 stores instruction R4 at address A4, but because CPU1 reads address A21 in cycle T3, the addresses do not match. In other words, an instruction branch has occurred. Therefore, CPU1 reads instruction R21 from instruction memory 4 two cycles later in cycle T5. In this cycle T3, a branch detection signal is issued from the first instruction cache 5, and the cache controller 9 stores address A21 in the second instruction cache 11.

[0037] In the subsequent cycle T5, CPU1 reads instruction R21 from memory 7. The next address that CPU1 processes is A22, and instruction R21 and instruction R22 at the next address A22 are stored in instruction memory 4. Address A23 and instructions R23 and R24 are stored first in first instruction cache 5. Then, at the timing when CPU1 reads instruction R21 at address A21 from memory 7, instruction R21 and instruction R22 at the next address A22 are stored in second instruction cache 11.

[0038] In the subsequent cycle T7, the first instruction cache 5 stores instruction R24 at address A24, but CPU1 reads address A21 in cycle T7. Here, address A21 and instruction R21 are stored in the second instruction cache 11, so CPU1 reads instruction R21 from the second instruction cache 11, and in the next cycle T8, instruction R21 is read into the read data of CPU1.

[0039] In this way, the microcomputer shown in FIG. 1 adds a second instruction cache 11, stores the address and instruction when a branch is detected in the second instruction cache 11, and next time a branch at the same address is detected, reads the instruction from the second instruction cache 11 at high speed, thereby making it possible to improve processing speed compared to the configuration shown in FIG. 6.

[0040] When address branching occurs in an operation that expects a state transition, such as polling processing, speeding up the instruction read cycle cannot be expected to improve the processing speed of the microcomputer. Therefore, in the memory control circuit of the microcomputer according to the embodiment of the present disclosure, if branching occurs consecutively, the cache controller 9 may delete the information of the corresponding address stored in the second instruction cache 11.

[0041] In addition, when memory addresses and instructions are stored in all of the storage areas of the second instruction cache 11, the memory control circuit of the microcomputer according to an embodiment of the present disclosure may further store the memory address, instruction, and number of occurrences after the branch when the branch detection signal is issued in a new instruction cache.

[0042] 4 is a diagram illustrating the configuration of a memory control circuit of a microcomputer according to an embodiment of the present disclosure. The microcomputer illustrated in FIG. 4 has a configuration in which a consecutive branch detector 8, a low-speed counter 10, and a third instruction cache 12 are added to the microcomputer illustrated in FIG. 1.

[0043] The consecutive branch detector 8 stores the memory address after branching when a branch detection signal is generated. If consecutive branches occur at the memory address, the consecutive branch detector 8 deletes the information of the corresponding address stored in the second instruction cache 11 via the cache controller 9.

[0044] When memory addresses and instructions are stored in all of the storage areas of the second instruction cache 11, the third instruction cache 12 stores the memory address, instruction, and occurrence count after the branch when the branch detection signal is issued. Figure 5 is a diagram showing an example of information stored in the third instruction cache 12. As shown in Figure 5, the third instruction cache 12 stores one set of memory address, instruction, and occurrence count. If the occurrence count stored in the third instruction cache 12 is greater than the occurrence count stored in the second instruction cache 11, the cache controller 9 overwrites the corresponding area of ​​the second instruction cache 11 with the information of the memory address, instruction, and occurrence count from the third instruction cache 12, and deletes the information stored in the third instruction cache 12.

[0045] The low-speed counter 10 is a counter that counts a predetermined time. When the cache controller 9 is notified that the low-speed counter 10 has counted the predetermined time, the cache controller 9 deletes the information stored in the third instruction cache 12. When the information in the third instruction cache 12 is updated by the cache controller 9, an update flag is issued from the third instruction cache 12. Upon receiving the update flag, the cache controller 9 issues a counter reset signal to the low-speed counter 10, resetting the count value of the low-speed counter 10.

[0046] 4, when consecutive branches occur, the cache controller 9 prevents the second instruction cache 11 from holding information about the corresponding addresses, thereby enabling effective use of the second instruction cache 11. Also, when consecutive branches occur, the memory control circuit of the microcomputer shown in FIG. 4, when consecutive branches occur, deletes information that is used less frequently from the second instruction cache 11, thereby enabling effective use of the second instruction cache 11.

[0047] Although the embodiments of the present disclosure have been described in detail above with reference to the accompanying drawings, the technical scope of the present disclosure is not limited to such examples. The above-described embodiments are illustrative and do not limit the technical scope of the present disclosure. It is clear that a person skilled in the art of the present disclosure can conceive of various modifications or alterations within the scope of the technical idea described in the claims, and it is understood that these modifications or alterations also naturally fall within the technical scope of the present disclosure.

[0048] Furthermore, the effects described in the above embodiments are explanatory or exemplary and are not limited to those described in the above embodiments. In other words, the technology according to the present disclosure may achieve other effects that are obvious to a person skilled in the art of the present disclosure from the description in the above embodiments, in addition to or instead of the effects described in the above embodiments. [Explanation of symbols]

[0049] 1 CPU 2. Bus 3 Memory Address Register 4. Instruction Memory 5 First instruction cache 6 Memory read control circuit 7. Memory 8. Continuous Branch Detector 9 Cache Controller 10 Low-Speed ​​Counter 11 Secondary instruction cache 12 Third instruction cache

Claims

1. a memory in which instructions are stored; a processor that reads and executes instructions from the memory; A memory control circuit for a microcomputer comprising: a memory read control circuit that stores an address and a next address from which the processor reads an instruction from the memory in a memory address register, an instruction at the address and an instruction at the next address in an instruction memory, and stores the next address and an instruction at the next address in a first instruction cache; a cache controller that, when the address stored in the memory address register and the address stored in the first instruction cache do not match when the processor reads the next instruction from the memory, stores the address stored in the memory address register, the instruction at the address, and the number of times the mismatch occurred in a second instruction cache; A memory control circuit for a microcomputer comprising:

2. 2. A memory control circuit for a microcomputer according to claim 1, further comprising a consecutive branch detector that, when the address stored in said memory address register and the address stored in said first instruction cache do not match when said processor reads the next instruction from said memory, causes said cache controller to delete the address stored in said memory address register from said second instruction cache if the address branches consecutively.

3. 2. A memory control circuit for a microcomputer as described in claim 1, wherein, when the address stored in the memory address register and the address stored in the first instruction cache do not match when the processor reads the next instruction from the memory, the cache controller stores the address stored in the memory address register, the instruction at that address, and the number of times the mismatch occurred in the third instruction cache when the address stored in the memory address register, the instruction at that address, and the number of times the mismatch occurred are stored up to the upper limit of the storage area of ​​the second instruction cache.

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