Display device

Abstract

To provide a display device that can minimize misalignment of a circuit board at high resolution.SOLUTION: A display device comprises: a display panel; pixels arranged in a display area of the display panel; a plurality of circuit boards connected to a non-display area of the display panel; and a plurality of driving circuits on the plurality of circuit boards. Each of the plurality of circuit boards includes one cluster terminal (terminal group) connected to pads of the non-display area, the cluster terminal (terminal group) includes a plurality of terminals arranged adjacent to each other on the circuit board, and cluster terminals (terminal groups) of at least two circuit boards have different widths (dimensions of the plurality of circuit boards in an arrangement direction).SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a display device, and more particularly to a display device that can minimize circuit board misalignment at high resolutions. [Background technology]

[0002] Organic light emitting diode displays (OLEDs) have self-luminous properties and, unlike liquid crystal displays (LCDs), do not require a separate light source, which allows for reduced thickness and weight. Furthermore, OLEDs have high-quality properties such as low power consumption, high brightness, and fast response speed, making them garnering attention as next-generation display devices for TVs, monitors, and portable electronic devices.

[0003] As the resolution of a display device increases, the display device includes more data lines, which requires more driver circuits and more circuit boards to drive the data lines. Therefore, as the resolution of a display device increases, more driver circuits must be mounted within the limited area of ​​the display panel, and the spacing between circuit boards and the terminal pitch of those circuit boards must be reduced.

[0004] Since the alignment between circuit boards is confirmed by the alignment keys disposed between the circuit boards, as described above, if the spacing between the terminals of the circuit boards is reduced, the area for arranging the alignment keys may be insufficient, resulting in a problem of the alignment keys not being able to be formed. In such cases, misalignment between the circuit boards may occur. Furthermore, if the terminal pitch of the circuit boards is reduced, misalignment may occur between the terminals of the circuit boards and the pads of the display panel. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Patent Publication No. 2023-167715 (JP2023-167715A) [Patent Document 2] Korean Patent Publication No. 2022-0046040 (KR10-2022-0046040A) Summary of the Invention [Problem to be solved by the invention]

[0006] The present invention aims to provide a display device that can minimize misalignment of circuit boards at high resolutions.

[0007] The objectives of the present invention are not limited to those mentioned above, and other technical objectives not mentioned will be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0008] To achieve the above-mentioned object, a display device according to one embodiment of the present invention includes a display panel; pixels arranged in a display area of ​​the display panel; a plurality of circuit boards connected to a non-display area of ​​the display panel; and a plurality of driving circuits on the plurality of circuit boards, each of the plurality of circuit boards including a cluster terminal (group of terminals) connected to a pad in the non-display area, the cluster terminal (group of terminals) including a plurality of terminals arranged adjacent to each other on the circuit board, and the cluster terminals (group of terminals) of at least two circuit boards having widths (dimensions in the arrangement direction of the plurality of circuit boards) that are different from each other.

[0009] The plurality of circuit boards includes a first outermost circuit board; a second outermost circuit board; and an intermediate circuit board between the first outermost circuit board and the second outermost circuit board.

[0010] The cluster terminals on at least one of the first outermost circuit board and the second outermost circuit board and the cluster terminals on the intermediate circuit board have different widths.

[0011] A width of the cluster terminals on the intermediate circuit board is smaller than a width of the cluster terminals on at least one of the first outermost circuit board and the second outermost circuit board.

[0012] It further includes a first alignment key disposed between adjacent circuit boards.

[0013] The first alignment key is disposed between the first outermost circuit board and the middle circuit board.

[0014] The distance between any one of the opposing sides of the first outermost circuit board and the intermediate circuit board and the center of the first alignment key is the same as the distance between the other of the opposing sides and the center of the first alignment key.

[0015] The distance between one of the opposing sides of the terminal of the first outermost circuit board and the terminal of the intermediate circuit board and the center of the first alignment key is different from the distance between the other of the opposing sides and the center of the first alignment key.

[0016] One of the opposing sides is a side of a terminal of the first outermost circuit board, and the other of the opposing sides is a side of a terminal of the first outermost circuit board.

[0017] The first alignment key is disposed between the second outermost circuit board and the middle circuit board.

[0018] The distance between any one of the opposing sides of the second outermost circuit board and the intermediate circuit board and the center of the first alignment key is the same as the distance between the other of the opposing sides and the center of the first alignment key.

[0019] The distance between one of the opposing sides of the terminal of the second outermost circuit board and the terminal of the intermediate circuit board and the center of the first alignment key is different from the distance between the other of the opposing sides and the center of the first alignment key.

[0020] One of the opposing sides is a side of a terminal of the second outermost circuit board, and the other of the opposing sides is a side of a terminal of the second outermost circuit board, and the distance between the one side and the first alignment key is greater than the distance between the other side and the first alignment key.

[0021] The intermediate circuit boards include a first intermediate circuit board and a second intermediate circuit board, and the first alignment key is disposed between the first intermediate circuit board and the second intermediate circuit board.

[0022] The distance between any one of the opposing sides of the first intermediate circuit board and the second intermediate circuit board and the center of the first alignment key is the same as the distance between the other of the opposing sides and the center of the first alignment key.

[0023] The distance between one of the opposing sides of the terminal of the first intermediate circuit board and the terminal of the second intermediate circuit board and the center of the first alignment key is the same as the distance between the other of the opposing sides and the center of the first alignment key.

[0024] At least two of the circuit boards have different widths.

[0025] Circuit boards having cluster terminals of different widths have different widths.

[0026] A circuit board containing larger width cluster terminals has a larger width than a circuit board containing smaller width cluster terminals.

[0027] The pixel array further includes a fan-out line connected to one side of each of the pads and the pixel.

[0028] The semiconductor device further includes dummy lines connected to the other side of each of the pads.

[0029] The circuit further includes second alignment keys disposed between adjacent dummy lines.

[0030] The second alignment key is disposed on the same layer as the active layer of the pixel.

[0031] The second alignment key has a triangular shape.

[0032] Among the pads, a plurality of cluster pads (a plurality of pad groups) including adjacently arranged pads are respectively connected to a plurality of cluster terminals (a plurality of terminal groups).

[0033] The second alignment key includes a plurality of alignment keys, and the alignment keys in the second alignment key pass through a portion of the cluster pad that corresponds to 1 / 2 of the width of the cluster pad and are positioned near an imaginary center line that extends parallel to the extension direction of each pad.

[0034] When the total number of pads included in the cluster pad is odd, the center line is located near the center of a central pad located at the center of the cluster pad, and the plurality of alignment keys in the second alignment key are located on both sides of a dummy line connected to the central pad.

[0035] If the total number of pads included in the cluster pad is an even number, the alignment keys of the second alignment key are arranged on both sides of the nth dummy line to the left of the center line, where n is a natural number less than k / 2 and k is the total number of pads included in the cluster pad.

[0036] If the total number of pads included in the cluster pad is an even number, the alignment keys are arranged on both sides of the nth dummy line to the right of the center line, where n is a natural number less than k / 2 and k is the total number of pads included in the cluster pad.

[0037] The second alignment key includes a plurality of alignment keys arranged on both sides of the dummy line with the dummy line interposed therebetween, and each of the plurality of alignment keys in the second alignment key has a triangular shape.

[0038] The pads include an outermost cluster pad connected to the first outermost circuit board and an intermediate cluster pad connected to the intermediate circuit board, and the distance between one of the opposing sides of the pads included in the outermost cluster pad and the pads included in the intermediate cluster pad and the center of the first alignment key is different from the distance between the other of the opposing sides and the center of the first alignment key.

[0039] The distance between any one of the sides and the center of the first alignment key is greater than the distance between the other side and the first alignment key.

[0040] The spacing between adjacent circuit boards is the same.

[0041] Specific details of other embodiments are included in the detailed description and drawings. [Effects of the Invention]

[0042] The display device according to the present invention can minimize misalignment of the circuit board at high resolutions.

[0043] It should be noted that the effects obtained by the present invention are not limited to those mentioned above, and other effects not mentioned will be clearly understood by those having ordinary skill in the art to which the present invention pertains from the following description. [Brief explanation of the drawings]

[0044] [Figure 1] 1 is a plan view showing a display device according to an embodiment. [Figure 2] FIG. 2 is a plan view showing the display panel of FIG. [Figure 3] FIG. 2 is an enlarged view of part A1 in FIG. [Figure 4] FIG. 2 is an enlarged view of part A2 in FIG. [Figure 5] FIG. 3 is an enlarged view of part A3 in FIG. 2. [Figure 6] FIG. 3 is an enlarged view of part A4 in FIG. 2. [Figure 7] FIG. 2 is a circuit diagram of one pixel of a display device according to an embodiment. [Figure 8] 1 is a cross-sectional view of a display device according to an embodiment. [Figure 9] FIG. 3 is an enlarged view of part A5 in FIG. 2. [Figure 10] FIG. 10 is a cross-sectional view taken along line II' in FIG. [Figure 11] FIG. 10 is a cross-sectional view taken along line II-II' in FIG. [Figure 12] FIG. 10 is a cross-sectional view taken along line III-III' in FIG. [Figure 13] FIG. 10 is a cross-sectional view taken along line IV-IV' in FIG. [Figure 14] 10A and 10B are diagrams illustrating the position of a fifth alignment key according to an embodiment when the number of pads in a cluster pad is odd. [Figure 15] 10A and 10B are diagrams illustrating the positions of the fifth alignment keys according to an embodiment when the number of pads in the cluster pad is an even number. DETAILED DESCRIPTION OF THE INVENTION

[0045] The advantages and features of the present invention, as well as methods for achieving them, will become clearer with reference to the following detailed embodiments in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, and can be realized in various different forms. The present embodiments are provided solely for the purpose of complete disclosure of the present invention and to fully convey the scope of the invention to those skilled in the art to which the present invention pertains. The present invention is defined solely by the scope of the claims.

[0046] When elements or layers are referred to as being "on" other elements or layers, this includes all cases where other layers or elements are directly on or between the other elements. The same reference numerals refer to the same components throughout the specification. The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments are merely examples, and the present invention is not limited to the details shown.

[0047] Although terms such as "first" and "second" are used to describe various components, it is understood that these components are not limited by these terms. These terms are used merely to distinguish one component from another. Therefore, it is understood that a "first" component referred to below may be a "second" component within the technical concept of the present invention.

[0048] The features of the various embodiments of the present invention may be partially or wholly combined or combined with one another, and may be technically interlocked and driven in various ways, and each embodiment may be implemented independently of the others or in conjunction with one another.

[0049] Hereinafter, specific embodiments will be described with reference to the accompanying drawings.

[0050] Fig. 1 is a plan view of a display device 100 according to an embodiment. Fig. 2 is a plan view of a display panel 110 of Fig. 1. For example, Fig. 2 illustrates only the remaining components of Fig. 1, excluding a data driver.

[0051] 1 and 2, the display device 100 is a device for displaying moving images and still images, and can be used as a display screen for a variety of products, including portable electronic devices such as mobile phones, smartphones, tablet personal computers (PCs), smart watches, watch phones, mobile communication terminals, electronic organizers, electronic books, portable multimedia players (PMPs), navigation systems, and ultra-mobile PCs (UMPCs), as well as televisions, notebook computers, monitors, billboards, and Internet of Things (IoT) devices. These are merely exemplary embodiments, and the display device 100 can also be used in other electronic devices.

[0052] The display device 100 may be, but is not limited to, an emissive display device such as an organic light-emitting display device including an organic light-emitting diode, a quantum dot light-emitting display device including a quantum dot light-emitting layer, an inorganic light-emitting display device including an inorganic semiconductor, or a micro-light-emitting display device including a micro- or nano light-emitting diode (micro LED or nano LED). For example, the display device 100 may be a type of display device other than an emissive display device. Hereinafter, an embodiment in which the display device 100 is an emissive display device (an organic light-emitting display device, as an example) will be disclosed.

[0053] The display device 100 may include a display panel 110, a gate driver GD, an emission driver ED, and a data driver DD that supply driving signals to pixels PX of the display panel 110. Here, the pixels PX may be disposed in a display area of ​​the display panel 110, the gate driver and the emission driver may be disposed in a non-display area NDA of the display panel 110, and the data driver may be connected to the non-display area NDA of the display panel 110 via a circuit board.

[0054] The display device 100 may further include a power supply and a timing control unit. The power supply can supply power voltages to the pixels PX, the gate drivers, the light emitting drivers, and the data drivers. The timing control unit can control the operations of the first gate driver GD1, the second gate driver GD2, the first light emitting driver ED1, the second light emitting driver ED2, and the data driver.

[0055] The display panel 110 has a rectangular shape in a plan view. Although FIGS. 1 and 2 show the display panel 110 in which the horizontal length is longer than the vertical length, the shape of the display panel 110 is not limited to this. For example, the display panel 110 may have a shape in which the vertical length is longer than the horizontal length, or may have a square shape, etc. The display panel 110 may have angular corners or rounded corners.

[0056] The planar shape of the display panel 110 is not limited to the illustrated rectangular shape, and other shapes may be used. For example, the display panel 110 may have a non-rectangular polygonal shape, a circle, an ellipse, an irregular shape, or other different shapes in plan view.

[0057] The display panel 110 may be provided as a rigid panel that is substantially undeformed, or as a flexible panel that can be deformed by at least partially folding, warping, rolling, etc. The display panel 110 may be provided to the display device 100 in an unbent state or in a bent state in some sections.

[0058] The display panel 110 may include a display area DA and a non-display area NDA.

[0059] A plurality of pixels PX are arranged in the display area DA. The pixels PX can display an image. The pixels PX can be connected to gate lines GL, emission control lines EML, data lines DL, and power lines. The gate lines GL and emission control lines EML can extend along a first direction DR1, and the data lines DL can extend along a second direction DR2.

[0060] The non-display area NDA is disposed around the periphery of the display area DA. In one embodiment, the non-display area NDA may surround the display area DA.

[0061] The display area DA may have various shapes depending on the embodiment. For example, the display area DA may have a rectangular shape, a non-rectangular polygonal shape, a circular shape, an elliptical shape, an irregular shape, or other different shapes. In one embodiment, the display area DA may have a shape that is suitable for the shape of the display panel 110.

[0062] 2, the non-display area NDA may include a pad area PA in which a plurality of pads PD are arranged. For example, the pad area PA is arranged in a non-display area (NDA; e.g., a lower non-display area) located below the display area. The plurality of pads PD are arranged along a first direction DR1.

[0063] The non-display area NDA is provided with a gate driver GD and a light-emitting driver ED. For example, the gate driver GD may include a first gate driver GD1 and a second gate driver GD2, and the light-emitting driver ED may include a first light-emitting driver ED1 and a second light-emitting driver ED2. Here, the first gate driver GD1 and the first light-emitting driver ED1 may be disposed in the non-display area (NDA; e.g., the left non-display area) located on the left side of the display area DA, and the second gate driver GD2 and the second light-emitting driver ED2 may be disposed in the non-display area (NDA; e.g., the right non-display area) located on the right side of the display area DA.

[0064] The gate driver GD drives the gate lines GL. For example, the first gate driver GD1 and the second gate driver GD2 can respectively supply gate signals to the gate lines GL. The gate lines GL can be connected to the first gate driver GD1 and the second gate driver GD2. For example, one side of each gate line GL can be electrically connected to the first gate driver GD1, and the other side of each gate line GL can be electrically connected to the second gate driver GD2.

[0065] The light-emitting driver ED drives the light-emitting control line EML. For example, the first light-emitting driver ED1 and the second light-emitting driver ED2 may each supply a light-emitting control signal to the light-emitting control line EML. The light-emitting control line EML may be connected to the first light-emitting driver ED1 and the second light-emitting driver ED2. For example, one side of each light-emitting control line EML may be electrically connected to the first light-emitting driver ED1, and the other side of each light-emitting control line EML may be electrically connected to the second light-emitting driver ED2.

[0066] As shown in FIGS. 1 and 2, the circuit boards CB1, CB2, CB3, CB4, and CB5 may be electrically connected to the display panel 110 via pads PD. The circuit boards CB1 to CB5 may include a first circuit board CB1, a second circuit board CB2, a third circuit board CB3, a fourth circuit board CB4, and a fifth circuit board CB5. In one embodiment, the first to fifth circuit boards CB1 to CB5 may be connected to at least one of a timing control unit and a power supply unit via another circuit board, a connector, or the like. In one embodiment, each of the circuit boards CB1 to CB5 may be a flexible printed circuit board (FPCB), a printed circuit board (PCB), or a flexible film such as a chip on film (COF), but is not limited to these.

[0067] The spacing between adjacent circuit boards (e.g., the spacing in the first direction DR1) may be the same. For example, the spacing between the first circuit board CB1 and the second circuit board CB2, the spacing between the second circuit board CB2 and the third circuit board CB3, the spacing between the third circuit board CB3 and the fourth circuit board CB4, and the spacing between the fourth circuit board CB4 and the fifth circuit board CB5 may be the same.

[0068] Each of the circuit boards CB1-CB5 may include cluster terminals (or cluster bumps). For example, the first circuit board CB1 may include a first cluster terminal BP1, the second circuit board CB2 may include a second cluster terminal BP2, the third circuit board CB3 may include a third cluster terminal BP3, the fourth circuit board CB4 may include a fourth cluster terminal BP4, and the fifth circuit board CB5 may include a fifth cluster terminal BP5.

[0069] The first cluster terminals BP1 may include a plurality of first terminals (or bumps; C1, P1, D1) arranged adjacently on the first circuit board CB1, the second cluster terminals BP2 may include a plurality of second terminals P2, D2 arranged adjacently on the second circuit board CB2, the third cluster terminals BP3 may include a plurality of third terminals P3, D3 arranged adjacently on the third circuit board CB3, the fourth cluster terminal BP4 may include a plurality of fourth terminals P4, D4 arranged adjacently on the fourth circuit board CB4, and the fifth cluster terminal BP5 may include a plurality of fifth terminals C2, P5, D5 arranged adjacently on the fifth circuit board CB5. Although five circuit boards CB1 to CB5 are disclosed in this embodiment, the number of circuit boards is not limited thereto.

[0070] The data driver DD may include a plurality of driver circuits (DDC1, DDC2, DDC3, DDC4, and DDC5; hereinafter, referred to as data driver circuits) arranged along a first direction DR1. For example, the data driver DD may include a first data driver circuit DDC1 mounted on a first circuit board CB1, a second data driver circuit DDC2 mounted on a second circuit board CB2, a third data driver circuit DDC3 mounted on a third circuit board CB3, a fourth data driver circuit DDC4 mounted on a fourth circuit board CB4, and a fifth data driver circuit DDC5 mounted on a fifth circuit board CB5. Each of the data driver circuits DDC1 to DDC5 may include, for example, an integrated circuit.

[0071] The data driving circuits DDC1 to DDC5 can be electrically connected to the pads PD of the display panel 110 via the respective circuit boards CB1 to CB5. For example, the first data driving circuit DDC1 may be electrically connected to the first pads C11, P11, and D11 of the display panel 110 via the first terminals C1, P1, and D1 of the first circuit board CB1, the second data driving circuit DDC2 may be electrically connected to the second pads P22 and D22 of the display panel 110 via the second terminals P2 and D2 of the second circuit board CB2, the third data driving circuit DDC3 may be electrically connected to the third pads P33 and D33 of the display panel 110 via the third terminals P3 and D3 of the third circuit board CB3, the fourth data driving circuit DDC4 may be electrically connected to the fourth pads P44 and D44 of the display panel 110 via the fourth terminals P4 and D4 of the fourth circuit board CB4, and the fifth data driving circuit DDC5 may be electrically connected to the fifth pads C22, P55, and D55 of the display panel 110 via the fifth terminals C2, P5, and D5 of the fifth circuit board CB5.

[0072] The plurality of data lines DL are connected to a data driver DD. For example, the plurality of data lines DL may be divided and connected to a plurality of data driving circuits DDC1 to DDC5. As a specific example, the plurality of data lines DL may include a plurality of first data lines connected to a first data driving circuit DDC1, a plurality of second data lines connected to a second data driving circuit DDC2, a plurality of third data lines connected to a third data driving circuit DDC3, a plurality of fourth data lines connected to a fourth data driving circuit DDC4, and a plurality of fifth data lines connected to a fifth data driving circuit DDC5.

[0073] The first terminals (C1, P1, D1; for example, the first cluster terminals BP1) (group of) may include a plurality of first control terminals C1, a plurality of first power supply terminals P1, and a plurality of first data terminals D1 arranged along a first direction DR1 on the first circuit board CB1. The first control terminal C1 may be connected to a timing control unit arranged on another circuit board (hereinafter, an external circuit board). The first power supply terminal P1 may be connected to a power supply unit arranged on the external circuit board. The first data terminal D1 may be connected to a first data driving circuit DDC1.

[0074] The second terminals (P2, D2; for example, the second cluster terminals BP2) (group of) may include a plurality of second power supply terminals P2 and a plurality of second data terminals D2 arranged along the first direction DR1 on the second circuit board CB2. The second power supply terminals P2 may be connected to a power supply unit arranged on an external circuit board. The second data terminals D2 may be connected to a second data driving circuit DDC2.

[0075] The third terminals (P3, D3; for example, the third cluster terminals BP3) (group of terminals) may include a plurality of third power supply terminals P3 and a plurality of third data terminals D3 arranged along the first direction DR1 on the third circuit board CB3. The third power supply terminals P3 may be connected to a power supply unit arranged on an external circuit board. The third data terminals D3 may be connected to the third data driving circuit DDC3.

[0076] The fourth terminals (P4, D4; for example, the fourth cluster terminals BP4) (group of terminals) may include a plurality of fourth power supply terminals P4 and a plurality of fourth data terminals D4 arranged along the first direction DR1 on the fourth circuit board CB4. The fourth power supply terminals P4 may be connected to a power supply unit arranged on an external circuit board. The fourth data terminals D4 may be connected to a fourth data driving circuit DDC4.

[0077] The fifth terminals (C2, P5, D5; for example, the fifth cluster terminal BP5) (group of) may include a plurality of second control terminals C2, a plurality of fifth power supply terminals P5, and a plurality of fifth data terminals D5 arranged along the first direction DR1 on the fifth circuit board CB5. The second control terminal C2 may be coupled to a timing control unit arranged on the external circuit board. The fifth power supply terminal P5 may be coupled to a power supply unit arranged on the external circuit board. The fifth data terminal D5 may be coupled to a fifth data driving circuit DDC5.

[0078] The first terminals C1, P1, D1 of the first circuit board CB1, the second terminals P2, D2 of the second circuit board CB2, the third terminals P3, D3 of the third circuit board CB3, the fourth terminals P4, D4 of the fourth circuit board CB4, and the fifth terminals C2, P5, D5 of the fifth circuit board CB5 may be respectively connected to the first pads C11, P11, D11, the second pads P22, D22, the third pads P33, D33, the fourth pads P44, D44, and the fifth pads C22, P55, D55 of the display panel 110.

[0079] The first terminals C1, P1, D1 and the first pads C11, P11, D11 can be electrically connected directly or via connecting members such as conductive balls, the second terminals P2, D2 and the second pads P22, D22 can be electrically connected directly or via connecting members such as conductive balls, the third terminals P3, D3 and the third pads P33, D33 can be electrically connected directly or via connecting members such as conductive balls, the fourth terminals P4, D4 and the fourth pads P44, D44 can be electrically connected directly or via connecting members such as conductive balls, and the fifth terminals C2, P5, D5 and the fifth pads C22, P55, D55 can be electrically connected directly or via connecting members such as conductive balls.

[0080] The first pads C11, P11, and D11 may include a plurality of first control pads C11, a plurality of first power pads P11, and a plurality of first data pads D11 arranged along a first direction DR1 on the pad area PA of the display panel 110. The first control pads C11 may be connected to the first control terminals C1. The first control pads C11 may be connected to the first gate driver GD1 and the first light-emitting driver ED1. The first power pads P11 may be connected to the first power terminals P1. The first power pads P11 may be connected to the first gate driver GD1, the first light-emitting driver ED1, and the pixels PX. The first data pads D11 may be connected to the first data terminals D1. The first data pads D11 may be connected to the first data lines.

[0081] The second pads P22, D22 may include a plurality of second power supply pads P22 and a plurality of second data pads D22 arranged along the first direction DR1 on the pad area PA of the display panel 110. The second power supply pads P22 may be connected to the second power supply terminals P2, respectively. The second power supply pads P22 may be connected to the pixels PX. The second data pads D22 may be connected to the second data terminals D2, respectively. The second data pads D22 may be connected to the second data lines, respectively.

[0082] The third pads P33, D33 may include a plurality of third power supply pads P33 and a plurality of third data pads D33 arranged along the first direction DR1 on the pad area PA of the display panel 110. The third power supply pads P33 may be connected to the third power supply terminals P3, and the third power supply pads P33 may be connected to the pixels PX. The third data pads D33 may be connected to the third data terminals D3, and the third data pads D33 may be connected to the third data lines.

[0083] The fourth pads P44, D44 may include a plurality of fourth power supply pads P44 and a plurality of fourth data pads D44 arranged along the first direction DR1 on the pad region PA of the display panel 110. The fourth power supply pads P44 may be connected to the fourth power supply terminals P4, respectively. The fourth power supply pads P44 may also be connected to the pixels PX. The fourth data pads D44 may also be connected to the fourth data terminals D4, respectively. The fourth data pads D44 may also be connected to the fourth data lines, respectively.

[0084] The fifth pads C22, P55, and D55 may include a plurality of second control pads C22, a plurality of fifth power pads P55, and a plurality of fifth data pads D55 arranged along the first direction DR1 on the pad area PA of the display panel 110. The second control pads C22 may be connected to the second control terminals C2, and the second control pads C22 may be connected to the second gate driver GD2 and the second light-emitting driver ED2. The fifth power pads P55 may be connected to the fifth power terminals P5, and the fifth power pads P55 may be connected to the pixels PX. The fifth data pads D55 may be connected to the fifth data terminals D5, and the fifth data pads D55 may be connected to the fifth data lines.

[0085] The first control pad C11 and the first gate driver GD1 mentioned above can be electrically connected to each other through the corresponding fan-out line FL, and another first control pad C11 and the first light-emitting driver ED1 can be electrically connected to each other through the corresponding fan-out line FL.

[0086] The second control pad C22 and the second gate driver GD2 mentioned above may be electrically connected to each other via the corresponding fan-out line FL, and another second control pad C22 and the second light-emitting driver ED2 may be electrically connected to each other via the corresponding fan-out line FL.

[0087] The first to fifth data pads D11, D22, D33, D44, and D55 may be electrically connected to the first to fifth data lines through the fan-out line FL.

[0088] A gate timing control signal, a light-emitting timing control signal, a gate clock signal, a light-emitting clock signal, a gate start signal, a light-emitting start signal, a high potential voltage, and a low potential voltage from the timing control unit may be supplied to the first gate driver GD1 and the first light-emitting driver ED1 via the first control terminal C1 of the first circuit board CB1 and the first control pad C11 of the display panel 110. For example, the gate timing control signal, the gate clock signal, the gate start signal, the high potential voltage, and the low potential voltage may be supplied to the first gate driver GD1, and the light-emitting timing control signal, the light-emitting clock signal, the light-emitting start signal, the high potential voltage, and the low potential voltage may be supplied to the first light-emitting driver ED1. A power signal from the power supply unit may be supplied to the first gate driver GD1, the first light-emitting driver ED1, and the pixel PX via the first power terminal P1 of the first circuit board CB1 and the first power pad P11 of the display panel 110. The power supply signal may include, for example, a driving voltage (VD in FIG. 7), a common voltage (VS in FIG. 7), a first initialization voltage (VI1 in FIG. 7), a second initialization voltage (VI2 in FIG. 7), and a bias voltage (VB in FIG. 7). Data signals from the first data driving circuit DDC1 may be supplied to the first data lines via the first data terminal D1 of the first circuit board CB1 and the first data pad D11 of the display panel 110, respectively.

[0089] A power signal from the power supply unit can be supplied to the pixel PX via the second power terminal P2 of the second circuit board CB2 and the second power pad P22 of the display panel 110. A data signal from the second data driving circuit DDC2 can be supplied to the second data line via the second data terminal D2 of the second circuit board CB2 and the second data pad D22 of the display panel 110.

[0090] A power signal from the power supply unit may be supplied to the pixel PX via the third power terminal P3 of the third circuit board CB3 and the third power pad P33 of the display panel 110. A data signal from the third data driving circuit DDC3 may be supplied to the third data line via the third data terminal D3 of the third circuit board CB3 and the third data pad D33 of the display panel 110.

[0091] A power signal from the power supply unit may be supplied to the pixel PX via a fourth power terminal P4 of the fourth circuit board CB4 and a fourth power pad P44 of the display panel 110. A data signal from the fourth data driving circuit DDC4 may be supplied to the fourth data line via a fourth data terminal D4 of the fourth circuit board CB4 and a fourth data pad D44 of the display panel 110.

[0092] A gate timing control signal, a light-emitting timing control signal, a gate clock signal, a light-emitting clock signal, a high potential voltage, and a low potential voltage from the timing controller may be supplied to the second gate driver GD2 and the second light-emitting driver ED2 via the second control terminal C2 of the fifth circuit board CB5 and the second control pad C22 of the display panel 110. For example, the gate timing control signal, the gate clock signal, the high potential voltage, and the low potential voltage are supplied to the second gate driver GD2, and the light-emitting timing control signal, the light-emitting clock signal, the high potential voltage, and the low potential voltage are supplied to the second light-emitting driver ED2. A power signal from the power supply may be supplied to the second gate driver GD2, the second light-emitting driver ED2, and the pixel PX via the fifth power terminal P5 of the fifth circuit board CB5 and the fifth power pad P55 of the display panel 110. A data signal from the fifth data driver circuit DDC5 may be supplied to the fifth data line via the fifth data terminal D5 of the fifth circuit board CB5 and the fifth data pad D55 of the display panel 110. The high potential voltage may be greater than the driving voltage, and the low potential voltage may be less than the common voltage.

[0093] 1, the width (W1; hereinafter, the first cluster terminal width W1) of the first cluster terminals BP1 including the first terminals C1, P1, and D1 can be defined as the size in the arrangement direction of the first terminals C1, P1, and D1 (e.g., the first direction DR1). For example, the first cluster terminal width W1 can be defined as the distance between the outer edge (hereinafter, the first outer edge) of a first terminal among the first terminals C1, P1, and D1 of the first circuit board CB1 that is arranged on one side edge (e.g., the first control terminal C1 that is arranged on the outermost side among the first control terminals C1) and the outer edge (hereinafter, the second outer edge) of a first terminal among the first terminals C1, P1, and D1 of the first circuit board CB1 that is arranged on the other side edge (e.g., the first power supply terminal P1 that is arranged on the outermost side among the first power supply terminals P1). Here, the first outer edge is disposed adjacent to a first edge of the first circuit board CB1 that intersects with one side (e.g., the lower side) of the display panel 110, and the second outer edge is disposed adjacent to a second edge of the first circuit board CB1 that intersects with one side (e.g., the lower side) of the display panel 110. That is, the second edge faces the first edge.

[0094] In a similar manner, the width (W2; hereinafter, second cluster terminal width W2) of the second cluster terminal BP2 including the second terminals P2 and D2 can be defined as the size in the arrangement direction of the second terminals P2 and D2 (e.g., the first direction DR1), the width (W3; hereinafter, third cluster terminal width W3) of the third cluster terminal BP3 including the third terminals P3 and D3 can be defined as the size in the arrangement direction of the third terminals P3 and D3 (e.g., the first direction DR1), the width (W4; hereinafter, fourth cluster terminal width W4) of the fourth cluster terminal BP4 including the fourth terminals P4 and D4 can be defined as the size in the arrangement direction of the fourth terminals P4 and D4 (e.g., the first direction DR1), and the width (W5; hereinafter, fifth cluster terminal width W5) of the fifth cluster terminal BP5 including the fifth terminals C2, P5, and D5 can be defined as the size in the arrangement direction of the fifth terminals C2, P5, and D5 (e.g., the first direction DR1).

[0095] According to one embodiment, at least two circuit boards may have different cluster terminal widths. For example, the remaining circuit boards, except for the outermost circuit board, may have a smaller cluster terminal width than the outermost circuit board. Here, if the outermost circuit boards are defined as the first outermost circuit board and the second outermost circuit board, respectively, and the circuit board (or group of circuit boards) between the first outermost circuit board and the second outermost circuit board is defined as an intermediate circuit board, the cluster terminal width of the intermediate circuit board may be smaller than the cluster terminal width of the first outermost circuit board (or the second outermost circuit board). According to one embodiment, the first outermost circuit board may be the first circuit board CB1, the second outermost circuit board may be the fifth circuit board CB5, and the intermediate circuit board may be at least one of the second through fourth circuit boards CB2, CB3, and CB4. For example, as shown in FIG. 1, the second cluster terminal width W2 of the second circuit board CB2 may be smaller than the first cluster terminal width W1 of the first circuit board CB1.

[0096] According to one embodiment, the cluster terminal width of the first outermost circuit board may be the same as the cluster terminal width of the second outermost circuit board, for example, the first cluster terminal width W1 of the first circuit board CB1 may be the same as the fifth cluster terminal width W5 of the fifth circuit board CB5.

[0097] According to one embodiment, the cluster terminal widths of the intermediate circuit boards may be the same, for example, the second cluster terminal width W2 of the second circuit board CB2, the third cluster terminal width W3 of the third circuit board CB3, and the fourth cluster terminal width W4 of the fourth circuit board CB4 may be the same.

[0098] 2, the width (W11; hereinafter, referred to as the first cluster pad width W11) of the first cluster pad PD1 including the first pads C11, P11, and D11 can be defined as the size in the arrangement direction of the first pads C11, P11, and D11 (e.g., the first direction DR1). For example, the first cluster pad width W11 can be defined as the distance between the outer edge (hereinafter, referred to as the left edge) of a first pad among the first pads C11, P11, and D11 arranged on one side edge (e.g., the first control pad C11 arranged on the outermost side among the first control pads C11) and the outer edge (hereinafter, referred to as the right edge) of a first pad among the first pads C11, P11, and D11 arranged on the other side edge (e.g., the first power supply pad P11 arranged on the outermost side among the first power supply pads P11). Here, the left side may be positioned adjacent to a first side of the first circuit board CB1 that intersects with one side (e.g., the bottom side) of the display panel 110, and the right side may be positioned adjacent to a second side of the first circuit board CB1 that intersects with one side (e.g., the bottom side) of the display panel 110.

[0099] Similarly, the width (W22; hereinafter, referred to as the second cluster pad width W22) of the second cluster pad PD2 including the second pads P22 and D22 can be defined as the size in the arrangement direction of the second pads P22 and D22 (e.g., the first direction DR1), and the width (W33; hereinafter, referred to as the third cluster pad width W33) of the third cluster pad PD3 including the third pads P33 and D33 can be defined as the size in the arrangement direction of the third pads P33 and D33 (e.g., the first direction DR1). The width (W44; hereinafter, the fourth cluster pad width W44) of the fourth cluster pad PD4 including the pads P44 and D44 can be defined as the size in the arrangement direction of the fourth pads P44 and D44 (e.g., the first direction DR1), and the width (W55; hereinafter, the fifth cluster pad width W55) of the fifth cluster pad PD5 including the fifth pads C22, P55, and D55 can be defined as the size in the arrangement direction of the fifth pads C22, P55, and D55 (e.g., the first direction DR1).

[0100] According to one embodiment, at least two cluster pads may have different cluster pad widths. For example, the remaining cluster pads, except for the outermost cluster pad, may have a smaller cluster pad width than the outermost cluster pad. Here, if the outermost cluster pads are designated the first and second outermost cluster pads, respectively, and the series of pads between the first and second outermost cluster pads are designated intermediate cluster pads, the cluster pad width of the intermediate cluster pad may be smaller than the cluster pad width of the first outermost cluster pad (or the second outermost cluster pad). According to one embodiment, the first outermost cluster pad may be the first cluster pad PD1, the second outermost cluster pad may be the fifth cluster pad PD5, and the intermediate cluster pad may be at least one of the second through fourth cluster pads PD2, PD3, and PD4. For example, as shown in FIG. 2, the second cluster pad width W22 of the second cluster pad PD2 may be smaller than the first cluster pad width W11 of the first cluster pad PD1.

[0101] According to one embodiment, the pad width of the first outermost cluster pad may be the same as the pad width of the second outermost cluster pad, for example, the first cluster pad width W11 of the first cluster pad PD1 may be the same as the fifth cluster pad width W55 of the fifth cluster pad PD5.

[0102] According to one embodiment, the cluster pad widths of the middle cluster pads may be the same, for example, the second cluster pad width W22 of the second cluster pad PD2, the third cluster pad width W33 of the third cluster pad PD3, and the fourth cluster pad width W44 of the fourth cluster pad PD4 may be the same.

[0103] According to one embodiment, corresponding cluster terminals and cluster pads may have the same width. For example, the first cluster terminal BP1 of the first circuit board CB1 and the first cluster pad PD1 covered by the first circuit board CB1 may have the same width. In other words, the first cluster terminal width W1 and the first cluster pad width W11 may be the same. Similarly, the second cluster terminal width W2 may be the same as the second cluster pad width W22, the third cluster terminal width W3 may be the same as the third cluster pad width W33, the fourth cluster terminal width W4 may be the same as the fourth cluster pad width W44, and the fifth cluster terminal width W5 may be the same as the fifth cluster pad width W55.

[0104] According to one embodiment, corresponding cluster terminals and cluster pads may have different widths. For example, the first cluster terminal BP1 of the first circuit board CB1 and the first cluster pad PD1 covered by the first circuit board CB1 may have different widths. Specifically, the first cluster terminal width W1 may be greater than the first cluster pad width W11. Similarly, the second cluster terminal width W2 may be greater than the second cluster pad width W22, the third cluster terminal width W3 may be greater than the third cluster pad width W33, the fourth cluster terminal width W4 may be greater than the fourth cluster pad width W44, and the fifth cluster terminal width W5 may be greater than the fifth cluster pad width W55. In other words, for corresponding cluster terminal widths and cluster pad widths, the cluster terminal width may be greater than the cluster pad width.

[0105] At least one alignment key is arranged in the non-display area NDA. For example, a first alignment key AK1, a second alignment key AK2, a third alignment key AK3, and a fourth alignment key AK4 are arranged in the non-display area NDA. For example, the first alignment key AK1 may be arranged between the first and second circuit boards CB1 and CB2 adjacent to each other in the first direction DR1 in the non-display area NDA. The second alignment key AK2 may be arranged between the second and third circuit boards CB2 and CB3 adjacent to each other in the first direction DR1 in the non-display area NDA. The third alignment key AK3 may be arranged between the third and fourth circuit boards CB3 and CB4 adjacent to each other in the first direction DR1 in the non-display area NDA. The fourth alignment key AK4 may be arranged between the fourth and fifth circuit boards CB4 and CB5 adjacent to each other in the first direction DR1 in the non-display area NDA. The first through fourth alignment keys AK1-AK4 may be marks for aligning the circuit boards CB1-CB5 and the display panel 110. The first through fourth alignment keys AK1 through AK4 align the circuit boards CB1 through CB5 with the display panel 110. The first through fourth alignment keys AK1 through AK4 also allow confirmation of whether the circuit boards CB1 through CB5 are accurately aligned with the display panel 110. The first through fourth alignment keys AK1 through AK4 may each have a cross shape, for example.

[0106] FIG. 3 is an enlarged view of part A1 in FIG.

[0107] As shown in FIG. 3, a first circuit board CB1 and a second circuit board CB2 having different cluster terminal widths can be aligned based on a first alignment key AK1.

[0108] Among the edges of the first circuit board CB1, the edges that are arranged opposite each other in the first direction DR1 and that intersect (or overlap) with one side edge (SS110; e.g., the lower edge) of the display panel 110 are defined as the first edge SS1 and the second edge SS2 of the first circuit board CB1, respectively. The second edge SS2 of the first circuit board CB1 can be positioned adjacent to the first alignment key AK1.

[0109] If the edges of the second circuit board CB2 that are arranged opposite each other in the first direction DR1 and that intersect (or overlap) with one side edge (SS110; e.g., the lower edge) of the display panel 110 are defined as the third edge SS3 and the fourth edge SS4 of the second circuit board CB2, respectively, the third edge SS3 of the second circuit board CB2 can be arranged so as to be close to the first alignment key AK1.

[0110] Opposing sides (e.g., sides facing each other in the first direction DR1) of the first and second circuit boards CB1 and CB2, which have different cluster terminal widths and are arranged adjacent to each other, may be the same distance from the first alignment key AK1 in the first direction DR1. The same distance refers to the length from the center of the first alignment key AK1 in the first direction DR1 to each side. In other words, the sides of the circuit boards arranged close to each other (or facing each other) across the first alignment key AK1 are positioned the same distance from the first alignment key AK1. For example, in the first direction DR1, the distance ds1 between the first alignment key AK1 and the second side SS2 of the first circuit board CB1 may be the same as the distance ds2 between the first alignment key AK1 and the third side SS3 of the second circuit board CB2. In other words, if an imaginary line passing through the center of the first alignment key AK1 and extending parallel to the second side is defined as the alignment line LL1, the distance between the alignment line LL1 and the second side SS2 (ds1; e.g., the distance in the first direction DR1) may be the same as the distance between the alignment line LL and the third side SS3 (ds2; e.g., the distance in the first direction DR1).

[0111] In addition, in a first circuit board CB1 and a second circuit board CB2 that have different cluster terminal widths and are arranged adjacent to each other, the distance ds3 between one of the opposing sides of the terminal of the first circuit board CB1 and the terminal of the second circuit board CB2 and the first alignment key AK1 may be different from the distance ds4 between the other of the opposing sides and the first alignment key AK1. For example, if the first terminals C1, P1, and D1 of a first circuit board CB1 that are located on the outermost side of the first circuit board CB1 so as to be closest to the first alignment key AK1 are designated (defined) as the first outermost terminal of the first circuit board CB1, and the second terminals P2 and D2 of a second circuit board CB2 that have a different cluster terminal width from the first circuit board CB1 and that are located on the outermost side of the second circuit board CB2 so as to be closest to the first alignment key AK1 are designated (defined) as the second outermost terminal of the second circuit board CB2, the first outermost terminal and the second outermost terminal may be located at different distances from the first alignment key AK1. For example, a distance ds3 between the first alignment key AK1 and the first outermost terminal of the first circuit board CB1 may be different from a distance ds4 between the first alignment key AK1 and the second outermost terminal of the second circuit board CB2. In other words, the distance (ds3; e.g., the distance in the first direction DR1) between the alignment line LL and the first outermost terminal (or the outer edge SS22 of the first outermost terminal) may be different from the distance (ds4; e.g., the distance in the first direction DR1) between the alignment line LL and the second outermost terminal (or the outer edge SS33 of the second outermost terminal). For example, the distance ds3 between the first outermost terminal of the first circuit board CB1, which has a relatively larger cluster terminal width, and the first alignment key AK1 may be greater than the distance ds4 between the second outermost terminal of the second circuit board CB2, which has a relatively smaller width, and the first alignment key AK1.

[0112] Similarly, the opposing sides (e.g., opposing sides in the first direction DR1) of the fourth circuit board CB4 and the fifth circuit board CB5, which have different cluster terminal widths and are arranged adjacent to each other, may be the same distance from the fourth alignment key AK4 therebetween in the first direction DR1.

[0113] Similarly, the distance between the fourth alignment key AK4 and the outermost terminal of the fifth circuit board CB5 may be greater than the distance between the fourth alignment key AK4 and the outermost terminal of the fourth circuit board CB4.

[0114] In addition, the first cluster terminal width W1 of the first circuit board CB1 described above can be defined as the distance between the outer edge SS11 of the first terminal (e.g., the first control terminal C1) located on the outermost side of one side of the first circuit board CB1 and the outer edge SS22 of the first terminal (e.g., the first power supply terminal P1) located on the outermost side of the other side of the first circuit board CB1.

[0115] Similarly, the second cluster terminal width W2 of the second circuit board CB2 described above can be defined as the distance between the outer edge SS33 of the second terminal (e.g., the second power terminal P2) located on the outermost side of one side of the second circuit board CB2 and the outer edge SS44 of the second terminal (e.g., the second power terminal P2) located on the outermost side of the other side of the second circuit board CB2.

[0116] At least two of the circuit boards CB1-CB5 may have different widths. For example, a circuit board having a larger cluster terminal width may have a larger width. In other words, the width of the outermost circuit board may be larger than the width of the middle circuit board. For example, the width W10 of the first circuit board CB1 may be larger than the width W20 of the second circuit board CB2. Here, the width of a circuit board may be a dimension in the first direction DR1. For example, as illustrated in FIG. 3, the width W10 of the first circuit board CB1 may be the distance between the first side SS1 of the first circuit board CB1 and the second side SS2 of the first circuit board CB1, and the width W20 of the second circuit board CB2 may be the distance between the third side SS3 of the second circuit board CB2 and the fourth side SS4 of the second circuit board CB2.

[0117] At least two of the intermediate circuit boards may have the same width as each other. For example, the width W20 of the second circuit board CB2, the width W30 of the third circuit board CB3, and the width W40 of the fourth circuit board CB4 may be the same as each other.

[0118] The widths of the data driving circuits DDC1 to DDC5 may be the same regardless of the width of the circuit board. For example, the widths of the first data driving circuit DDC1, the second data driving circuit DDC2, the third data driving circuit DDC3, the fourth data driving circuit DDC4, and the fifth data driving circuit DDC5 may be the same. Here, the widths of the data driving circuits may be the dimensions in the first direction DR1.

[0119] FIG. 4 is an enlarged view of part A2 in FIG.

[0120] As shown in FIG. 4, the third circuit board CB3 and the fourth circuit board CB4, which have the same cluster terminal width, can be aligned using the third alignment key AK3 as a reference.

[0121] If the edges of the third circuit board CB3 that are arranged opposite each other in the first direction DR1 and that intersect (or overlap) with one side edge (SS110; e.g., the lower edge) of the display panel 110 are defined as the first edge SS5 and the second edge SS6 of the third circuit board CB3, respectively, the second edge SS6 of the third circuit board CB3 can be positioned so as to be close to the third alignment key AK3.

[0122] If the edges of the fourth circuit board CB4 that are arranged opposite each other in the first direction DR1 and that intersect (or overlap) with one side edge (SS110; e.g., the lower edge) of the display panel 110 are defined as the third edge SS7 and the fourth edge SS8 of the fourth circuit board CB4, respectively, the third edge SS7 of the fourth circuit board CB4 can be positioned so as to be close to the third alignment key AK3.

[0123] The opposing sides (e.g., opposing sides in the first direction DR1) of the third and fourth circuit boards CB3 and CB4, which have the same cluster terminal width and are arranged adjacent to each other, may be positioned the same distance from the third alignment key AK3. In other words, the sides of the circuit boards arranged close to (or facing) each other across the third alignment key AK3 may be positioned the same distance from the third alignment key AK3. For example, the distance ds5 between the third alignment key AK3 and the second side SS6 of the third circuit board CB3 may be the same as the distance ds6 between the third alignment key AK3 and the third side SS7 of the fourth circuit board CB4. In other words, if an imaginary line passing through the center of the third alignment key AK3 and extending parallel to the second side SS6 is defined as the alignment line LL11, the distance between the alignment line and the second side SS6 (ds5; for example, the distance in the first direction DR1) may be the same as the distance between the alignment line LL11 and the third side SS7 (ds6; for example, the distance in the first direction DR1). Note that the above-mentioned distances ds1, ds2, ds5, and ds6 may all be the same or different from one another.

[0124] Furthermore, if the third terminals P3 and D3 of the third circuit board CB3 that are arranged on the outermost side of the third circuit board CB3 so as to be closest to the third alignment key AK3 are defined as the first outermost terminal of the third circuit board CB3, and the second terminals P2 and D2 of the fourth circuit board CB4 that have the same cluster terminal width as the third circuit board CB3 and that are arranged on the outermost side of the fourth circuit board CB4 so as to be closest to the third alignment key AK3 are defined as the second outermost terminal of the fourth circuit board CB4, the first outermost terminal and the second outermost terminal may be disposed at the same distance from the third alignment key AK3. For example, the distance ds7 between the third alignment key AK3 and the first outermost terminal of the third circuit board CB3 may be the same as the distance ds8 between the third alignment key AK3 and the second outermost terminal of the fourth circuit board CB4. In other words, the distance (ds7; e.g., the distance in the first direction DR1) between the alignment line LL11 and the first outermost terminal (or the outer edge SS66 of the first outermost terminal) may be the same as the distance (ds8; e.g., the distance in the first direction DR1) between the alignment line LL11 and the second outermost terminal (or the outer edge SS77 of the second outermost terminal). For example, the distance ds7 between the first outermost terminal and the first alignment key AK1 of the third circuit board CB3 may be the same as the distance ds8 between the second outermost terminal and the first alignment key AK1 of the fourth circuit board CB4.

[0125] Similarly, the opposing sides (e.g., opposing sides in the first direction DR1) of the second circuit board CB2 and the third circuit board CB3, which have the same cluster terminal width and are arranged adjacent to each other, can be positioned at the same distance from the second alignment key AK2 therebetween.

[0126] Similarly, the distance between the second alignment key AK2 and the outermost terminal of the second circuit board CB2 may be the same as the distance between the second alignment key AK2 and the outermost terminal of the third circuit board CB3.

[0127] The third cluster terminal width W3 of the third circuit board CB3 described above can be defined as the distance between the outer edge SS55 of the third terminal arranged outermost on one side of the third circuit board CB3 (e.g., the third power terminal P3 at the left end) and the outer edge SS66 of the third terminal arranged outermost on the other side of the third circuit board CB3 (e.g., the third power terminal P3 at the right end).

[0128] Similarly, the fourth cluster terminal width W4 of the fourth circuit board CB4 described above can be defined as the distance between the outer edge SS77 of the fourth terminal arranged outermost on one side of the fourth circuit board CB4 (e.g., the fourth power terminal P4 at the left end) and the outer edge SS88 of the fourth terminal arranged outermost on the other side of the fourth circuit board CB4 (e.g., the fourth power terminal P4 at the right end).

[0129] At least two of the circuit boards may have the same width. For example, circuit boards having the same cluster terminal width may have the same width. For example, the width of the first circuit board CB1 may be the same as the width of the fifth circuit board CB5. The width of the second circuit board CB2, the width of the third circuit board CB3, and the width of the fourth circuit board CB4 may be the same as the width of the fourth circuit board CB4. Here, the width of the circuit board may be the size in the third direction. As illustrated in FIG. 4, the distance between the first side SS5 of the third circuit board CB3 and the second side SS6 of the third circuit board CB3 may be the same as the distance between the third side SS7 of the fourth circuit board CB4 and the fourth side SS8 of the fourth circuit board CB4.

[0130] Relatively, a circuit board having a larger cluster terminal width may have a larger width. For example, the width of a first circuit board CB1 may be larger than the width of a second circuit board CB2. Here, the width of a circuit board may be a dimension in a first direction DR1. For example, as illustrated in FIG. 3, the width of the first circuit board CB1 may be the distance between a first side SS1 of the first circuit board CB1 and a second side SS2 of the first circuit board CB1, and the width of the second circuit board CB2 may be the distance between a third side SS3 of the second circuit board CB2 and a fourth side SS4 of the second circuit board CB2.

[0131] According to one embodiment, the width W2 of the cluster terminals of an intermediate circuit board (e.g., CB2) is smaller than the width W1 of the cluster terminals of an outermost circuit board (e.g., CB1). Therefore, the distance between the cluster terminals of adjacent circuit boards (e.g., the sum of ds3 and ds4 in FIG. 3) can be increased, and therefore the distance between the cluster pads corresponding to those cluster terminals (e.g., the distance between the first pad P11 located on the right edge and the second pad P22 located on the left edge in FIG. 2) can also be increased. Therefore, the distance between the cluster pads PD1 to PD5 is increased, and a sufficient margin area for arranging the first alignment key AK1 can be secured. Therefore, the alignment between the circuit boards CB1 to CB5 can be easily confirmed, thereby minimizing misalignment between the circuit boards CB1 to CB5.

[0132] FIG. 5 is an enlarged view of part A3 in FIG.

[0133] The outermost cluster pad and the adjacent intermediate cluster pad may be at different distances in the first direction DR1 from the alignment key disposed therebetween. For example, as shown in FIG. 5 , the distance ds10 in the first direction DR1 between the alignment line LL1 passing through the center of the first alignment key AK1 and the second cluster pad PD2 may be smaller than the distance ds9 in the first direction DR1 between the alignment line LL1 and the first cluster pad PD1. For example, since the first power supply pad P11 of the first cluster pad PD1 and the second power supply pad P22 of the second cluster pad PD2 face each other across the first alignment key AK1, the distance ds10 in the first direction DR1 between the alignment line LL1 of the first alignment key AK1 and the outer edge SS20 of the second power supply pad P22 may be smaller than the distance ds9 in the first direction DR1 between the alignment line LL1 and the outer edge SS10 of the first power supply pad P11. Here, the outer side SS10 of the first power supply pad P11 and the outer side SS20 of the second power supply pad P22 face each other in the first direction DR1 with the first alignment key AK1 in between.

[0134] Similarly, the distance in the first direction DR1 between the alignment line passing through the center of the fourth alignment key AK4 and the fourth cluster pad DP4 may be smaller than the distance in the first direction DR1 between the alignment line passing through the center of the fourth alignment key AK4 and the fifth cluster pad PD5.

[0135] FIG. 6 is an enlarged view of part A4 in FIG.

[0136] The intermediate cluster pads may be spaced the same distance from the alignment key disposed therebetween in the first direction DR1. For example, as shown in FIG. 6 , the distance ds11 in the first direction DR1 between the alignment line LL11 passing through the center of the third alignment key AK3 and the third cluster pad PD3 may be the same as the distance ds12 in the first direction DR1 between the alignment line LL11 and the fourth cluster pad PD4. For example, since the third power supply pad P33 of the third cluster pad PD3 and the fourth power supply pad P44 of the fourth cluster pad PD4 face each other across the third alignment key AK3, the distance ds11 in the first direction DR1 between the alignment line LL11 of the third alignment key AK3 and the outer edge SS15 of the third power supply pad P33 may be the same as the distance ds12 in the first direction DR1 between the alignment line LL11 and the outer edge SS25 of the fourth power supply pad P44. Here, the outer side SS15 of the third power supply pad P33 and the outer side SS25 of the fourth power supply pad P44 face each other in the first direction DR1 with the third alignment key AK3 in between.

[0137] Similarly, the distance in the first direction DR1 between the alignment line passing through the center of the second alignment key AK2 and the second cluster pad DP2 may be the same as the distance in the first direction DR1 between the alignment line passing through the center of the second alignment key AK2 and the third cluster pad PD3.

[0138] 7 is a circuit diagram of one pixel PX of a display device according to an embodiment, for example, the pixel PX of FIG.

[0139] As shown in FIG. 7, the pixel PX may be connected to a first gate line GWL, a second gate line GCL, a third gate line GIL, a fourth gate line EBL, an emission control line EML, a data line DL, a driving voltage line VDL, a common voltage line VSL, a first initialization voltage line VIL1, a second initialization voltage line VIL2, and a bias voltage line VBL.

[0140] The pixel PX may include a pixel circuit PC and a light-emitting element ED. The pixel circuit PC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a capacitor Cst.

[0141] The first transistor T1 may include a gate electrode, a source electrode, and a drain electrode. The first transistor T1 can control a source-drain current (hereinafter, referred to as a drive current) in response to a data voltage applied to the gate electrode. The drive current (e.g., Isd) flowing through the channel region of the first transistor T1 is proportional to the square of the difference between the voltage (Vsg) between the source electrode and gate electrode of the first transistor T1 and the threshold voltage (Vth) of the first transistor T1 (Isd=k×(Vsg−Vth)). 2 ) where k is a proportionality coefficient determined by the structure and physical characteristics of the first transistor T1, Vsg is the source-gate voltage of the first transistor T1, and Vth is the threshold voltage of the first transistor T1.

[0142] The light emitting element ED receives the driving current Isd and emits light, and the amount of light emitted or the brightness of the light emitting element ED is proportional to the magnitude of the driving current Isd.

[0143] The light-emitting element ED may be an organic light-emitting diode including a first electrode, a second electrode, and an organic light-emitting layer disposed between the first and second electrodes. As another example, the light-emitting element ED may be an inorganic light-emitting element including a first electrode, a second electrode, and an inorganic semiconductor disposed between the first and second electrodes. As yet another example, the light-emitting element ED may be a quantum dot light-emitting element including a first electrode, a second electrode, and a quantum dot light-emitting layer disposed between the first and second electrodes. As yet another example, the light-emitting element ED may be a micro light-emitting diode.

[0144] A first electrode of the light-emitting element ED may be electrically connected to the fourth node N4. The first electrode of the light-emitting element ED may be connected to the drain electrode of the sixth transistor T6 and the source electrode of the seventh transistor T7 via the fourth node N4. A second electrode of the light-emitting element ED may be connected to the second driving voltage line VSL. The second electrode of the light-emitting element ED may receive a second driving voltage (VS; for example, a low-potential voltage) from the common voltage line VSL.

[0145] The second transistor T2 may be turned on by a first gate signal GW of the first gate line GWL to electrically connect the data line DL to a first node N1, which is the source electrode of the first transistor T1. The second transistor T2 may be turned on based on the first gate signal GW to supply a data voltage to the first node N1. The gate electrode of the second transistor T2 may be electrically connected to the first gate line GWL, the source electrode may be electrically connected to the data line DL, and the drain electrode may be electrically connected to the first node N1.

[0146] The third transistor T3 may be turned on by a second gate signal GC on the second gate line GCL to electrically connect the second node N2, which is the drain electrode of the first transistor T1, to the third node N3, which is the gate electrode of the first transistor T1. The third transistor T3 may be connected between the third node N3 and the second node N2. For example, the gate electrode of the third transistor T3 may be electrically connected to the second gate line GCL, the source electrode may be electrically connected to the third node N3, and the drain electrode may be electrically connected to the second node. The third transistor T3 may be turned on by a second gate signal on the second gate line GCL to electrically connect the second node N2, which is the drain electrode of the first transistor T1, to the third node N3, which is the gate electrode of the first transistor T1. The third transistor T3 may be a double-gate transistor having two gate electrodes (e.g., a gate electrode and an opposing gate electrode). The gate electrode and the opposing gate electrode are arranged to face each other on different layers.

[0147] The fourth transistor T4 may be turned on by a third gate signal GI on a third gate line GIL to electrically connect a third node N3, which is the gate electrode of the first transistor T1, to a first initialization voltage line VIL1. The fourth transistor T4 may be connected in series between the third node N3 and the first initialization voltage line VIL1. For example, the gate electrode of the fourth transistor T4 may be electrically connected to the third gate line GIL, the source electrode may be electrically connected to the third node N3, and the drain electrode may be electrically connected to the first initialization voltage line VIL1. The fourth transistor T4 may be a double-gate transistor. The first initialization voltage line VIL1 may transmit a first initialization voltage VI1.

[0148] The fifth transistor T5 may be turned on by an emission control signal EM of the emission control line EML to electrically connect the driving voltage line VDL to a first node N1, which is the source electrode of the first transistor T1. The fifth transistor T5 may have a gate electrode electrically connected to the emission control line EML, a source electrode electrically connected to the driving voltage line VDL, and a drain electrode electrically connected to the first node N1.

[0149] The sixth transistor T6 may be turned on by an emission control signal EM of the light control line EML to electrically connect the second node N2, which is the drain electrode of the first transistor T1, to the fourth node N4, which is the first electrode of the light emitting element ED. The gate electrode of the sixth transistor T6 may be electrically connected to the emission control line EML, the source electrode may be electrically connected to the second node N2, and the drain electrode may be electrically connected to the fourth node N4.

[0150] When the fifth transistor T5, the first transistor T1 and the sixth transistor T6 are all turned on, a driving current can be supplied to the light emitting element ED.

[0151] The seventh transistor T7 is turned on by a fourth gate signal EB of the fourth gate line EBL to electrically connect a fourth node N4, which is a first electrode of the light emitting element ED, to a second initialization voltage line VIL2. The seventh transistor T7 is turned on based on the fourth gate signal to discharge the first electrode of the light emitting element ED to a second initialization voltage VI2. The gate electrode of the seventh transistor T7 is electrically connected to the fourth gate line EBL, the source electrode is electrically connected to the fourth node N4, and the drain electrode is electrically connected to the second initialization voltage line VIL2. The second initialization voltage line VIL2 can transmit the second initialization voltage VI2.

[0152] The eighth transistor T8 may be turned on by a fourth gate signal EB of the fourth gate line EBL to electrically connect the bias voltage line VBL to a first node N1, which is the source electrode of the first transistor T1. The eighth transistor T8 may be turned on based on the fourth gate signal EB to supply a bias voltage VB to the first node N1. The eighth transistor T8 may improve hysteresis of the first transistor T1 by supplying the bias voltage VB to the source electrode of the first transistor T1. The gate electrode of the eighth transistor T8 may be electrically connected to the fourth gate line EBL, the source electrode may be electrically connected to the bias voltage line VBL, and the drain electrode may be electrically connected to the first node N1.

[0153] Each of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 may include a silicon-based active layer. For example, each of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 may be a p-type transistor including an active layer made of low-temperature polycrystalline silicon (LTPS). An active layer made of low-temperature polycrystalline silicon has high electron mobility and excellent turn-on characteristics. Therefore, by including transistors with excellent turn-on characteristics, the display device 100 can stably and efficiently drive the multiple pixels PX. Each of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 can output a current flowing into a source electrode to a drain electrode based on a gate low voltage applied to the gate electrode.

[0154] The third transistor T3 and the fourth transistor T4 may be n-type transistors including oxide-based active layers. The transistors including oxide-based active layers may have a coplanar structure with a gate electrode disposed thereon. The transistors including oxide-based active layers may output current flowing into the drain electrode to the source electrode based on a gate high voltage applied to the gate electrode.

[0155] The capacitor Cst may be electrically connected between a third node N3, which is the gate electrode of the first transistor T1, and the driving voltage line VDL. For example, a first electrode of the capacitor Cst is electrically connected to the third node N3, and a second electrode of the capacitor Cst is electrically connected to the driving voltage line VDL, thereby maintaining a potential difference between the driving voltage line VDL and the gate electrode of the first transistor T1.

[0156] FIG. 8 is a cross-sectional view of a display device according to an embodiment.

[0157] 8, the display device 100 may include a substrate SUB, a barrier layer BR, a thin film transistor layer TFTL, a light-emitting element layer EMTL, and an encapsulation layer ENC. The barrier layer BR, the thin film transistor layer TFTL, the light-emitting element layer EMTL, and the encapsulation layer ENC are sequentially arranged on the substrate SUB along a third direction DR3.

[0158] The substrate SUB may be a rigid substrate or a flexible substrate that allows bending, folding, rolling, etc. The substrate SUB is made of an insulating material such as glass, quartz, or polymer resin. Examples of polymer materials include polyethersulfone (PES), polyacrylate (PA), polyarylate (PAR), polyetherimide (PEI), polyethylene napthalate (PEN), polyethylene terepthalate (PET), polyphenylene sulfide (PPS), polyallylate, polyimide (PI), polycarbonate (PC), cellulose triacetate (CAT), cellulose acetate propionate (CAP), or a combination thereof. Alternatively, the substrate SUB may include a metallic material.

[0159] 8, a barrier layer BR is disposed on the substrate SUB. The barrier layer BR is disposed on the entire surface of the substrate SUB. The barrier layer BR can be a film for protecting the transistors T1 to T8 of the thin film transistor layer TFTL and the light-emitting layer EL of the light-emitting element layer EMTL from moisture that penetrates through the substrate SUB, which is susceptible to moisture permeation.

[0160] The barrier layer BR is made of a plurality of inorganic films stacked alternately. For example, the barrier layer BR may be formed of a multi-layer structure (e.g., a first barrier layer BR1 and a second barrier layer BR2) in which one or more inorganic films selected from the group consisting of silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, and aluminum oxide are stacked alternately.

[0161] 8, a first pattern layer is disposed on the barrier layer BR. For example, a light-shielding layer BML is disposed on the barrier layer BR. The light-shielding layer BML is disposed on the barrier layer BR so as to cover the overlapping region (e.g., the first channel region CH1) between the first gate electrode GE1 and the first active layer ACT1. In other words, the light-shielding layer BML is disposed on the barrier layer BR so as to overlap with the channel region CH1 of the first transistor T1, which is a drive transistor.

[0162] The light-shielding layer BML is made of a metal material such as chromium (Cr) or molybdenum (Mo), or black ink or black dye. If the light-shielding layer BML is made of a metal material, the light-shielding layer BML can be supplied with a constant power source. This prevents the light-shielding layer BML from floating electrically, and the electrical characteristics of the transistor (e.g., the first transistor T1) on the light-shielding layer BML can be stabilized.

[0163] 8, a buffer layer BF is disposed on the light-shielding layer BML. The buffer layer BF is disposed on the entire surface of the substrate SUB including the barrier layer BR. The buffer layer BF can be a film for protecting the transistors T1 to T8 of the thin-film transistor layer TFTL and the light-emitting layer EL of the light-emitting element layer EMTL from moisture that penetrates through the substrate SUB, which is susceptible to moisture permeation.

[0164] The buffer layer BF may be formed of a multi-layer structure (e.g., a first buffer layer BR1 and a second buffer layer BR2) in which one or more inorganic layers selected from the group consisting of silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, and aluminum oxide are alternately stacked.

[0165] A second pattern layer is disposed on the buffer layer BF. For example, a first active layer ACT1 is disposed on the barrier layer BR. As shown in FIG. 8 , the first active layer ACT1 may include a first channel region CH1 of the first transistor T1, a second electrode E12 of the first transistor T1, a first channel region CH1 of the first transistor T1, a first electrode E61 of the sixth transistor T6, a second electrode E62 of the sixth transistor T6, and a sixth channel region CH6 of the sixth transistor T6.

[0166] The first active layer ACT1 may be an active layer made of low temperature polycrystalline silicon (LTPS).

[0167] A first gate insulating layer GTI1 is disposed on the second pattern layer. For example, as shown in FIG. 8, the first gate insulating layer GTI1 is disposed on the first active layer ACT1. In this case, the first gate insulating layer GTI1 is disposed on the entire surface of the substrate SUB including the first active layer ACT1.

[0168] The first gate insulating layer GTI1 may include at least one of tetraethoxysilane (tetraethylorthosilicate, TEOS), silicon nitride (SiNx), and silicon oxide (SiO2). For example, the first gate insulating layer GTI1 may have a double-layer structure in which a silicon nitride layer having a thickness of 40 nm and a tetraethoxysilane layer having a thickness of 80 nm are stacked in order.

[0169] A third pattern layer is disposed on the first gate insulating layer GTI1. For example, the second gate electrode GE2, the first gate electrode GE1, the eighth gate electrode GE8, the emission control line EML, the fifth gate electrode GE5, and the sixth gate electrode GE6 are disposed on the first gate insulating layer GTI1.

[0170] 8 shows an example in which the first gate electrode GE1, the sixth gate electrode GE6, and the emission control line EML are arranged on the first gate insulating layer GTI1. The first gate electrode GE1 is arranged on the first gate insulating layer GTI1 so as to overlap with the first channel region CH1 of the first active layer ACT1. The sixth gate electrode GE6 of the emission control line EML is arranged on the first gate insulating layer GTI1 so as to overlap with the sixth channel region CH6 of the first active layer ACT1.

[0171] The third pattern layer includes at least one of molybdenum (Mo), copper (Cu), aluminum, and titanium (Ti) and is formed as a single layer or multiple layers. For example, the first gate electrode GE1 includes a triple layer including a titanium film, an aluminum film, and a titanium film sequentially disposed on the first gate insulating layer GTI1 along the third direction DR3.

[0172] A second gate insulating layer GTI2 is disposed on the third pattern layer. For example, as shown in FIG. 8, the second gate insulating layer GTI2 is disposed on the first gate electrode GE1, the sixth gate electrode GE6, and the emission control line EML. In this case, the second gate insulating layer GTI2 is disposed on the entire surface of the substrate SUB, including the first gate electrode GE1, the sixth gate electrode GE6, and the emission control line EML.

[0173] The second gate insulating layer GTI2 may include the same material and structure as the first gate insulating layer GTI1 described above.

[0174] A fourth pattern layer is disposed on the second gate insulating layer GTI2. For example, a fourth opposing gate electrode GEb4, a third opposing gate electrode GEb3, and a capacitor electrode CPE are disposed on the second gate insulating layer GTI2. FIG. 8 shows an example in which the capacitor electrode CPE and the third opposing gate electrode GEb3 are disposed on the second gate insulating layer GTI2. The capacitor electrode CPE is disposed on the second gate insulating layer GTI2 so as to overlap with the first gate electrode GE1. A capacitor Cst may be formed between the capacitor electrode CPE and the first gate electrode GE1.

[0175] The fourth pattern layer may have the same material or structure as the third pattern layer described above.

[0176] A first interlayer insulating layer ITL1 is disposed on the fourth pattern layer. For example, as shown in Fig. 8, the first interlayer insulating layer ITL1 is disposed on the capacitor electrode CPE and the third opposing gate electrode GEb3. In this case, the first interlayer insulating layer ITL1 is disposed on the entire surface of the substrate SUB, including the capacitor electrode CPE and the third opposing gate electrode GEb3.

[0177] The first interlayer insulating layer ITL1 may include an inorganic film such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer, or may include multiple inorganic films.

[0178] A fifth pattern layer is disposed on the first interlayer insulating layer ITL1. For example, a second active layer ACT2 is disposed on the first interlayer insulating layer ITL1. As shown in FIG. 8, the second active layer ACT2 is disposed on the first interlayer insulating layer ITL1 so as to overlap with the third opposing gate electrode GEb3. The second active layer ACT2 may include a first electrode E31 of the third transistor T3, a second electrode E32 of the third transistor T3, and a third channel region CH3 of the third transistor T3. The third channel region CH3 of the second active layer ACT2 may overlap with the third opposing gate electrode GEb3.

[0179] The second active layer ACT2 may be an oxide-based active layer, for example, an oxide semiconductor including indium-gallium-zinc-oxide (IGZO) or indium-gallium-zinc-tin-oxide (IGZTO).

[0180] A third gate insulating layer GTI3 is disposed on the fifth pattern layer. For example, as shown in FIG. 8, the third gate insulating layer GTI3 is disposed on the second active layer ACT2. The third gate insulating layer GTI3 is disposed on the entire surface of the substrate SUB including the second active layer ACT2.

[0181] The third gate insulating layer GTI3 may have the same material and structure as the first gate insulating layer GTI1 described above.

[0182] A sixth pattern layer is disposed on the third gate insulating layer GTI3. For example, the fourth gate electrode GE4 and the third gate electrode GE3 are disposed on the third gate insulating layer GTI3.

[0183] 8 shows an example in which the third gate electrode GE3 is arranged on the third gate insulating layer GTI3. The third gate electrode GE3 is arranged so as to overlap with the third channel region CH3 of the second active layer ACT2.

[0184] The sixth pattern layer may have the same material or structure as the third pattern layer described above.

[0185] A second interlayer insulating layer ITL2 is disposed on the sixth pattern layer. For example, as shown in FIG. 8, the second interlayer insulating layer ITL2 is disposed on the third gate electrode GE3. The second interlayer insulating layer ITL2 is disposed on the entire surface of the substrate SUB including the third gate electrode GE3.

[0186] The second interlayer insulating layer ITL2 may have the same material and structure as the first interlayer insulating layer ITL1 described above.

[0187] A seventh pattern layer is disposed on the second interlayer insulating layer ITL2. For example, the first initialization voltage line VIL1, the third gate line GIL, the data connecting electrode DCE, the first gate line GWL, the second gate line GCL, the gate connecting electrode GCE, the active connecting electrode ACE, the bias voltage line VBL, the capacitor connecting electrode CCE, the lower pixel connecting electrode PCEa, the fourth gate line EBL, and the second initialization voltage line VIL2 are disposed on the second interlayer insulating layer ITL2.

[0188] 8 illustrates an example in which the gate connecting electrode GCE, the active connecting electrode ACE, the bias voltage line VBL, and the lower pixel connecting electrode PCEa are disposed on the second interlayer insulating layer ITL2. The lower pixel connecting electrode PCEa may be connected to the second electrode E62 of the sixth transistor T6 via a first contact hole CT1 that penetrates the second interlayer insulating layer ITL2, the third gate insulating layer GTI3, the first interlayer insulating layer ITL1, the second gate insulating layer GTI2, and the first gate insulating layer GTI1. The active connecting electrode ACE may be connected to the second electrode E12 of the first transistor T1 and the first electrode E61 of the sixth transistor T6 via a second contact hole CT2 that penetrates the second interlayer insulating layer ITL2, the third gate insulating layer GTI3, the first interlayer insulating layer ITL1, the second gate insulating layer GTI2, and the first gate insulating layer GTI1. The active connecting electrode ACE may be connected to the second electrode E32 of the third transistor T3 via a fifth contact hole CT5 that penetrates the second interlayer insulating layer ITL2 and the third gate insulating layer GTI3. The gate connecting electrode GCE may be connected to the first gate electrode GE1 via a third contact hole CT3 that penetrates the second interlayer insulating layer ITL2, the third gate insulating layer GTI3, the first interlayer insulating layer ITL1, the hole 40 of the capacitor electrode CPE, and the second gate insulating layer GTI2. The gate connecting electrode GCE may be connected to the first electrode E31 of the third transistor T3 via a fourth contact hole CT4 that penetrates the second interlayer insulating layer ITL2 and the third gate insulating layer GTI3.

[0189] The seventh pattern layer may have the same material or structure as the third pattern layer described above.

[0190] A first planarization layer VA1 is disposed on the seventh pattern layer. For example, the first planarization layer VA1 is disposed on the gate connecting electrode GCE, the active connecting electrode ACE, the bias voltage line VBL, and the lower pixel connecting electrode PCEa. The first planarization layer VA1 is disposed on the entire surface of the substrate SUB, including the gate connecting electrode GCE, the active connecting electrode ACE, the bias voltage line VBL, and the lower pixel connecting electrode PCEa.

[0191] The first planarization layer VA1 can include an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0192] An eighth pattern layer is disposed on the first planarization layer VA1. For example, the first data line DL1, the driving voltage line VDL, and the upper pixel connecting electrode PCEb are disposed on the second interlayer insulating layer ITL2. FIG. 8 shows an example in which the driving voltage line VDL and the upper pixel connecting electrode PCEb are disposed on the first planarization layer VA1.

[0193] The upper pixel connecting electrode PCEb may be connected to the lower pixel connecting electrode PCEa through a sixth contact hole CT6 penetrating the first planarization layer VA1.

[0194] The eighth pattern layer may have the same material or structure as the third pattern layer described above.

[0195] A second planarization layer VA2 is disposed on the eighth pattern layer. For example, the second planarization layer VA2 is disposed on the driving voltage line VDL and the upper pixel connecting electrode PCEb. The second planarization layer VA2 is disposed on the entire surface of the substrate SUB, including the driving voltage line VDL and the upper pixel connecting electrode PCEb.

[0196] The second planarization layer VA2 may have the same material and structure as the first planarization layer VA1 described above.

[0197] A ninth pattern layer is disposed on the second planarization layer VA2. For example, as shown in FIG. 8, a light emitting element layer EMTL including the ninth pattern layer is disposed on the second planarization layer VA2. For example, as shown in FIG. 8, a pixel electrode PE is disposed as the ninth pattern layer on the third planarization layer VA3. The pixel electrode PE may be connected to the upper pixel connecting electrode PCEb via a seventh contact hole CT7 penetrating the second planarization layer VA2.

[0198] The light emitting element layer EMTL may further include a light emitting element LEL and a bank (or pixel defining layer) in addition to the ninth patterned layer.

[0199] The light-emitting element LEL may include a pixel electrode PE, an emitting layer EL, and a common electrode CM. The emitting area EA is an area where the pixel electrode PE, the emitting layer EL, and the common electrode CM are sequentially stacked, and where holes from the pixel electrode PE and electrons from the common electrode CM are combined in the emitting layer to emit light. In this case, the pixel electrode PE may be the anode electrode of the light-emitting element LEL, and the common electrode CM may be the cathode electrode of the light-emitting element LEL.

[0200] In a top emission structure in which light is emitted from the light emitting layer EL toward the common electrode CM, the pixel electrode PE can be formed of a single layer of molybdenum (Mo), titanium (Ti), copper (Cu), or aluminum (Al), or to enhance reflectivity, it can be formed of a laminated structure of aluminum and titanium (Ti / Al / Ti), a laminated structure of aluminum and ITO (ITO / Al / ITO), an APC alloy, or a laminated structure of APC alloy and ITO (ITO / APC / ITO). APC alloy is an alloy of silver (Ag), palladium (Pd), and copper (Cu).

[0201] The bank (PDL; or pixel defining layer) may serve to define the light-emitting area EA of the pixel PX. To this end, the bank PDL may be disposed on the third planarization layer VA3 to expose a portion of the pixel electrode PE. The bank PDL may cover the edge of the pixel electrode PE. The bank PDL may also be disposed in a seventh contact hole CT7 penetrating the third planarization layer VA3. This allows the seventh contact hole CT7 penetrating the third planarization layer VA3 to be filled with the bank PDL. The bank PDL may be formed of an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0202] As shown in Figure 8, a spacer SPC is disposed on the bank PDL. The spacer SPC can serve to support a mask during the process of manufacturing the light-emitting layer EL. The spacer SPC can be formed of an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0203] An emitting layer EL is formed on the pixel electrode PE. The emitting layer EL contains an organic material and emits a predetermined color. For example, the emitting layer EL may include a hole transporting layer, an organic material layer, and an electron transporting layer. The organic material layer may include a host and a dopant. The organic material layer may include a material that emits a predetermined light, and may be formed using a phosphorescent material or a fluorescent material.

[0204] The light emitting element LEL is provided for each pixel PX. For example, the first pixel PX includes a first light emitting element, the second pixel PX includes a second light emitting element, and the third pixel PX includes a third light emitting element. The first, second, and third light emitting elements can provide light of different colors. For example, the first light emitting element can emit light of a first color, the second light emitting element can emit light of a second color, and the third light emitting element can emit light of a third color.

[0205] For example, the organic material layer of the first light-emitting layer in the first light-emitting region that emits light of a first color may be a phosphorescent material containing a host material including CBP (carbazole biphenyl) or mCP (1,3-bis(carbazol-9-yl)) and a dopant including at least one selected from PIQIr(acac) (bis(1-phenylisoquinoline)acetylacetonate iridium), PQIr(acac) (bis(1-phenylquinoline)acetylacetonate iridium), PQIr (tris(1-phenylquinoline)iridium), and PtOEP (octaethylporphyrin platinum). Alternatively, the organic material layer of the first light-emitting layer in the first light-emitting region may be a fluorescent material including, but not limited to, PBD:Eu(DBM)3(Phen) or Perylene.

[0206] The organic material layer of the second light-emitting layer in the second light-emitting region that emits light of the second color may be a phosphorescent material containing a host material including CBP or mCP and a dopant material including Ir(ppy)3 (fac tris(2-phenylpyridine)iridium). Alternatively, the organic material layer of the second light-emitting layer in the second light-emitting region that emits light of the second color may be a fluorescent material including Alq3 (tris(8-hydroxyquinolino)aluminum), but is not limited to this.

[0207] The organic material layer of the light-emitting layer of the third light-emitting region that emits light of a third color may be, but is not limited to, a phosphorescent material containing a host material including CBP or mCP and a dopant material including (4,6-F2ppy)2Irpic or L2BD111.

[0208] The common electrode CM is disposed on the first, second, and third light-emitting layers (e.g., EL). The common electrode CM is disposed to cover the first, second, and third light-emitting layers. The common electrode CM may be a common layer disposed in common to the first to third light-emitting layers. A capping layer may be formed on the common electrode CM.

[0209] In the top emission structure, the common electrode CM can be made of a transparent conductive material (TCO) such as ITO or IZO, which transmits light, or a semi-transmissive metallic material such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag). When the common electrode CM is made of a semi-transmissive metallic material, the light output efficiency increases due to the microcavities.

[0210] The encapsulation layer ENC may be formed on the light-emitting element layer EMTL. The encapsulation layer ENC may include at least one inorganic film TFE1, TFE3 to prevent oxygen or moisture from penetrating into the light-emitting element layer EMTL. The encapsulation layer ENC may also include at least one organic film to protect the light-emitting element layer EMTL from foreign matter such as dust. For example, the encapsulation layer ENC may include a first encapsulation inorganic film TFE1, a encapsulation organic film TFE2, and a second encapsulation inorganic film TFE3.

[0211] The first sealing inorganic film TFE1 is disposed on the common electrode CM, the sealing organic film TFE2 is disposed on the first sealing inorganic film TFE1, and the second sealing inorganic film TFE3 is disposed on the sealing organic film TFE2. The first sealing inorganic film TFE1 and the second sealing inorganic film TFE3 may be formed as a multi-layer structure in which one or more inorganic films selected from the group consisting of silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, and aluminum oxide are alternately stacked. The sealing organic film TFE2 may be an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0212] 9 is an enlarged view of part A5 in FIG. 2, FIG. 10 is a cross-sectional view taken along line II' in FIG. 9, FIG. 11 is a cross-sectional view taken along line II-II' in FIG. 9, and FIG. 12 is a cross-sectional view taken along line III-III' in FIG. 9.

[0213] 9 shows four first pads (e.g., four first data pads D11). For example, the four first data pads D11 may be first data pads D11 connected to different first data lines.

[0214] One side of the first data pad D11 may be connected to the fan-out line FL, and the other side of the first data pad D11 may be connected to the dummy line DML. For example, the first data pad D11 may be connected to the fan-out line FL via a first connecting electrode CNE1 and to the dummy line DML via a second connecting electrode CNE2. The dummy line DML may be part of a test line for applying a test signal during a manufacturing process of the display device 100. For example, after a test process of the display device 100 using the test line is completed, the test line may be cut during a scribing process, and therefore the dummy line DML may be part of the cut test line.

[0215] The fan-out lines FL and the dummy lines DML are disposed on the first gate insulating layer GTI1. The fan-out lines FL and the dummy lines DML are each made of the same material as the third pattern layer described above.

[0216] The first connecting electrode CNE1 is disposed on the fan-out line FL, and the second connecting electrode CNE2 is disposed on the dummy line DML. For example, the first connecting electrode CNE1 is disposed on the second interlayer insulating layer ITL2 to overlap the fan-out line FL, and the second connecting electrode CNE2 is disposed on the second interlayer insulating layer ITL2 to overlap the dummy line DML. The first connecting electrode CNE1 may be connected to the fan-out line FL via a first contact hole CT11 and a second contact hole CT22 that penetrate the second interlayer insulating layer ITL2, the third gate insulating layer GTI3, the first interlayer insulating layer ITL1, and the second gate insulating layer GTI2. The second connecting electrode CNE2 may be connected to the dummy line DML via a third contact hole CT33 and a fourth contact hole CT44 that penetrate the second interlayer insulating layer ITL2, the third gate insulating layer GTI3, the first interlayer insulating layer ITL1, and the second gate insulating layer GTI2. The first connecting electrode CNE1 and the second connecting electrode CNE2 are each made of the same material as the seventh pattern layer described above.

[0217] The first data pad D11 is disposed on the first connecting electrode CNE1 and the second connecting electrode CNE2. For example, the first data pad D11 is disposed on the first connecting electrode CNE1 and the second connecting electrode CNE2 so as to overlap the first connecting electrode CNE1 and the second connecting electrode CNE2. The first data pad D11 may be directly connected to (or in direct contact with) the first connecting electrode CNE1 and the second connecting electrode CNE2, respectively. The first data pad D11 is made of the same material as the aforementioned eighth pattern layer.

[0218] A second planarization layer VA2 is disposed on the first data pad D11. The second planarization layer VA2 may have a pad contact hole PCH exposing at least a portion of the first data pad D11. For example, the pad contact hole PCH penetrates the second planarization layer VA2. The terminal (e.g., the first data terminal D1) may be connected to the first data pad D11 through the pad contact hole PCH. For example, the first data terminal D1 and the first data pad D11 may be electrically connected through an anisotropic conductive layer disposed on the pad contact hole PCH.

[0219] The fifth alignment keys AK5 are arranged in the non-display area NDA. For example, the fifth alignment keys AK5 are arranged in the non-display area NDA between adjacent dummy lines DML. The fifth alignment keys AK5 may be marks for alignment between the circuit boards CB1 to CB5 and the display panel 110. For example, the fifth alignment keys AK5 may be marks for alignment between the terminals C1, P1, D1, P2, D2, P3, D3, P4, D4, P5, D5, and C2 of the circuit boards CB1 to CB5 and the pads C11, P11, D11, P22, D22, P33, D33, P44, D44, P55, D55, and C22 of the display panel 110. The fifth alignment key AK5 aligns the terminals C1, P1, D1, P2, D2, P3, D3, P4, D4, P5, D5, and C2 with the pads C11, P11, D11, P22, D22, P33, D33, P44, D44, P55, D55, and C22. The fifth alignment key AK5 also confirms whether the terminals C1, P1, D1, P2, D2, P3, D3, P4, D4, P5, D5, and C2 are accurately aligned with the pads C11, P11, D11, P22, D22, P33, D33, P44, D44, P55, D55, and C22. The fifth alignment key AK5 may have, for example, a triangular shape.

[0220] The fifth alignment keys AK5 are arranged on both sides of the dummy line DML. For example, the fifth alignment keys AK5 are arranged on opposite sides of the dummy line DML. The fifth alignment key AK5 arranged on one side of the dummy line DML and the fifth alignment key AK5 arranged on the other side of the dummy line DML may be symmetrical with respect to the dummy line DML therebetween.

[0221] The fifth alignment key AK5 is disposed on the buffer layer BF. For example, the fifth alignment key AK5 is disposed between the second buffer layer BF2 and the first gate insulating layer GTI1. The fifth alignment key AK5 is made of the same material as the second pattern layer described above. For example, the fifth alignment key AK5 is made of the same material as the first active layer ACT1 described above. Specifically, the fifth alignment key AK5 is made of the same material as the first electrode E61 of the first active layer ACT1. The fifth alignment key AK5 can be observed from the back surface of the substrate SUB. Figure 13 is a cross-sectional view taken along line IV-IV' in Figure 9.

[0222] The display device 100 of Fig. 13 differs from the display device 100 of Fig. 9 in that the fan-out line FL is disposed on the first gate insulating layer GTI1. Therefore, the following description will focus on this difference.

[0223] 13, the fan-out line FL is disposed on the first gate insulating layer GTI1. For example, the fan-out line FL is made of the same material as the fourth pattern layer described above.

[0224] 13, adjacent fan-out lines FL are arranged on different layers. For example, one of the adjacent fan-out lines FL is made of the third pattern layer, and the other is made of the fourth pattern layer. In other words, if the fan-out line FL made of the third pattern layer is named (defined) as the first fan-out line and the fan-out line FL made of the fourth pattern layer is named (defined) as the second fan-out line, the first fan-out line and the second fan-out line are arranged alternately along the first direction DR1.

[0225] FIG. 14 is a diagram illustrating the position of the fifth alignment key AK5 according to an embodiment when the number of pads in the cluster pad is odd.

[0226] 14 shows an example in which one cluster pad (e.g., PD1) includes five pads PD10, PD20, PD30, PD40, and PD50. Here, a first dummy line DML1 may be connected to the first pad PD10, a second dummy line DML2 may be connected to the second pad PD20, a third dummy line DML3 may be connected to the third pad PD30, a fourth dummy line DML4 may be connected to the fourth pad PD40, and a fifth dummy line DML5 may be connected to the fifth pad PD50.

[0227] 14, the fifth align key AK5 is disposed near a virtual center line CTL1 that passes through a portion of the cluster pad PD1 that corresponds to half the width W11 of the cluster pad PD1 and extends parallel to the second direction (DR2; e.g., the extension direction of a pad (e.g., PD30)). For example, as shown in FIG. 14, if the total number of pads PD10, PD20, PD30, PD40, and PD50 included in the cluster pad PD1 is odd (e.g., five), the center line CTL1 may be located at the center of the third pad PD30 that is disposed at the center of the cluster pad PD1. In this case, the fifth align key AK5 may be disposed on both sides of the third dummy line DML3 connected to the third pad PD30. For example, the fifth align keys AK5 may be disposed to face each other in the first direction DR1 across the third dummy line DML3. In other words, three of the fifth alignment keys AK5 can be arranged between the second dummy line DML2 and the third dummy line DML3, and the other three of the fifth alignment keys AK5 can be arranged between the third dummy line DML3 and the fourth dummy line DML4.

[0228] FIG. 15 is a diagram illustrating the position of the fifth alignment key AK5 according to an embodiment when the number of pads in the cluster pad is even.

[0229] 15 shows an example in which one cluster pad (e.g., PD1) includes six pads PD10, PD20, PD30, PD40, PD50, and PD60. Here, a first dummy line DML1 may be connected to the first pad PD10, a second dummy line DML2 may be connected to the second pad PD20, a third dummy line DML3 may be connected to the third pad PD30, a fourth dummy line DML4 may be connected to the fourth pad PD40, a fifth dummy line DML5 may be connected to the fifth pad PD50, and a sixth dummy line DML6 may be connected to the sixth pad PD60.

[0230] As shown in FIG. 15, the fifth alignment key AK5 is located in the cluster pad (pad group) PD1, passes through a portion corresponding to 1 / 2 of the width W11 of the cluster pad PD1, and is positioned near a virtual center line CTL2 extending parallel to the second direction (DR2; for example, the extension direction of the pad (e.g., PD30)). For example, as shown in FIG. 15, if the total number of pads PD10, PD20, PD30, PD40, PD50, and PD60 included in cluster pad PD1 is an even number (e.g., six), center line CTL2 may be located between third pad PD30 and fourth pad PD40, which are located at the center of cluster pad PD1. In this case, fifth align keys AK5 may be located on both sides of the first third dummy line DML3 to the left of center line CTL2 (e.g., in the opposite direction of first direction DR1 (hereinafter, referred to as the first opposite direction)). For example, fifth align keys AK5 may be located opposite each other in first direction DR1 with third dummy line DML3 in between. In other words, three of fifth align keys AK5 may be located between center line CTL2 (or fourth dummy line DML4) and third dummy line DML3, and the other three of fifth align keys AK5 may be located between third dummy line DML3 and second dummy line DML2.

[0231] As described above, when the total number of pads PD10, PD20, PD30, PD40, PD50, and PD60 included in cluster pad PD1 is an even number, the fifth align keys AK5 may be arranged on both sides of the first fourth dummy line DML4 to the right of center line CTL2 (e.g., in the first direction DR1). For example, the fifth align keys AK5 may be arranged to face each other in the first direction DR1 with the fourth dummy line DML4 interposed therebetween. In other words, three of the fifth align keys AK5 may be arranged between the center line (CTL2 or the third dummy line DML3) and the fourth dummy line DML4, and the other three of the fifth align keys AK5 may be arranged between the fourth dummy line DML4 and the fifth dummy line DML5.

[0232] According to one embodiment, if the total number of pads PD10, PD20, PD30, PD40, PD50, and PD60 included in cluster pad PD1 is an even number, the fifth align key AK5 is disposed on both sides of the nth dummy line to the left of center line CTL2 (e.g., in the first reverse direction) or on both sides of the nth dummy line to the right of center line CTL2 (e.g., in the first direction) DR1. Here, n may be a natural number. Preferably, n may be a natural number less than k / 2. Here, k may be the total number of pads included in one cluster pad. For example, as shown in FIG. 15, if cluster pad PD1 includes a total of six pads PD10, PD20, PD30, PD40, PD50, and PD60, k may be 3 (=6 / 2), and therefore n may be 1 or 2.

[0233] Those skilled in the art will understand that the present specification can be embodied in other specific forms without changing the technical spirit or essential features thereof. Therefore, the above-described embodiments should be understood to be illustrative in all respects and not limiting. The scope of the present specification is defined by the claims below, rather than the above detailed description, and all modifications and variations derived from the meaning and scope of the claims and their equivalents should be construed as being within the scope of the present specification.

[0234] In addition, the present specification and drawings disclose preferred embodiments of the present specification, and specific terms are used, but these are used in a general sense merely to easily explain the technical content of the specification and to aid in understanding the invention, and are not intended to limit the scope of the specification. In addition to the embodiments disclosed herein, it is obvious to a person skilled in the art to which the present specification pertains that other modifications can be made based on the technical ideas of the present specification.

[0235] According to a preferred specific embodiment, it is as follows:

[0236] The background and issues of this case are as follows (i) to (vi).

[0237] (i) In the case of a display panel such as an organic light-emitting display panel, when a relatively large size (for example, a diagonal dimension of 10 inches or more or 12 inches or more) and high resolution (for example, full HD (1,920 x 1,080) or more) is required, such as a computer display, three or more (for example, four to eight) film-like wiring circuit boards (circuit boards CB1 and CB2 of the present application) equipped with driver ICs are mounted in the non-display area on one edge of the display panel using the COF (Chip On Film) method.

[0238] (ii) In a single display panel, all of the film-type wiring boards (circuit boards CB1 and CB2 of the present application) of the COF (Chip On Film) method generally have the same dimensions. In particular, the left-right dimensions (dimensions along the edge of the board; width in the present application) of the terminal groups on the back surfaces of the film-type wiring circuit boards (circuit boards CB1 and CB2 of the present application) generally all have the same dimensions.

[0239] (iii) FIG. 3 of Patent Document 1 and the related explanation show that the left and right dimensions of the COF wiring boards at both ends are made larger than those of the others in order to supply power to the “common wirings 16, 18.”

[0240] (iv) In order to align the COF wiring board and the display panel body, alignment marks have been provided on both of them. That is, in the case of a liquid crystal display panel or the like, the COF wiring board is attached while aligning the position while illuminating the position of the alignment mark from the back side of the display panel body made of a transparent substrate and taking an image with a camera.

[0241] (v) When providing alignment marks on the display panel body, it is efficient in terms of process to form them simultaneously with the pad group in the non-display peripheral portion of the display panel body. Therefore, the alignment marks on the display panel body are positioned based on the positions of both ends of each pad group.

[0242] (vi) Furthermore, if the display panel is a front-emitting type and the transparency of the substrate constituting the display panel is not sufficient, the alignment mark on the display panel body may be placed, for example, in the gap between the pad groups, particularly in the center of this gap.

[0243] In specific embodiments of the present application, the following A1 to A6 are particularly mentioned.

[0244] A1 The left-right dimension (width) of the output terminal group (cluster terminals BP1) of the COF wiring board (circuit board CB1) located at both left-right ends and the left-right dimension (width) of the input pad group (pads C1, P1, D1) of the display panel main body connected thereto are larger than the left-right dimension (width) of the output terminal group (cluster terminals BP2) of the COF wiring board (circuit board CB2) located at any other left-right end and the left-right dimension (width) of the input pad group (pads P2, D2) of the display panel main body connected thereto. Accordingly, the left-right dimension (width) of the COF wiring board (circuit board CB1) located at both left-right ends is larger than that of the COF wiring board (circuit board CB2) located at any other left-right end. (Fig. 3 of the present application)

[0245] A2 The alignment marks (first alignment keys AK1 to AK4) on the display panel body for the operation of mounting the COF wiring boards (circuit boards CB1, CB2) are not positioned in the center of the gap between the pad groups in the left-right direction, but are positioned in the center of the gap between the intended placement locations of the COF wiring boards (circuit boards CB1, CB2) in the left-right direction.

[0246] A3 By making the alignment marks (first alignment keys AK1 to AK4) particularly cross-shaped, alignment can be achieved not only in the left-right direction (first direction DR1) but also in the depth direction (second direction DR2; up-down direction on a plane). For example, the positional relationship (distances in the left-right and depth directions) between the left and right sides and front and back sides of the COF wiring board (circuit boards CB1, CB2) and the alignment marks (first alignment keys AK1 to AK4) can be confirmed by camera imaging, and then the alignment can be performed before mounting.

[0247] A precision alignment mark (second alignment key AK5) for precise left-right alignment is provided on the back surface of the A4 COF wiring substrate (circuit boards CB1 and CB2), particularly in the center of the array area of ​​the output terminal group (cluster terminals BP1 and BP2) (Fig. 9 of the present application).

[0248] A5 On the side of the display panel body, a "dummy wiring DML" is provided that corresponds to the precision alignment mark (second alignment key AK5) of the COF wiring substrate (circuit boards CB1, CB2). This dummy wiring DML is a wiring that extends from a pad (pad D2) located in the center of the input pad group on the display panel body to the outside of the substrate in the depth direction (second direction DR2; up-and-down direction on the plane).

[0249] A6 The precision alignment marks (second alignment keys AK5) may be provided in multiple pairs (three pairs in the example of FIG. 9) on either side of the dummy wiring DML. In particular, they may be triangular, wedge-shaped, or the like, pointing to the side of the dummy wiring DML. This makes it possible to check the left-right deviation from the target position with high precision. The precision alignment marks (second alignment keys AK5) can be used during the alignment and mounting process, or for checking after mounting. In addition, the multiple pairs of precision alignment marks (second alignment keys AK5) can be used to precisely align the input pads in the depth direction (second direction DR2; vertical direction on a plane) and check the alignment accuracy. In some cases, they can also detect undesired tilt (rotation around the direction perpendicular to the panel surface (third direction DR3)). [Explanation of symbols]

[0250] 110 Display panel DA display area NDA Hidden Area ED1 First light emitting driver GD1 First gate driver CB1 First Circuit Board CB2 Second Circuit Board DR1 1st direction DR2 2nd direction DR3 3rd direction DDC1 First data driving circuit DDC2 Second data drive circuit AK1 First alignment key AK2 Second Alignment Key AK3 3rd alignment key AK4 4th Alignment Key BP1 First cluster terminal BP2 Second cluster terminal C1 First control terminal P1 1st power supply terminal P2 2nd power supply terminal D1 First data terminal D2 Second data terminal SS1 First Side SS2 Side 2 SS3 Third Side SS4 4th side SS11, SS22, SS33, SS44 outer edge W1, W2 width ds1,ds2,ds3,ds4 ​​distance LL1 Alignment Line W10, W20, W30, W40, W50 width

Claims

1. Display panel; pixels arranged in a display area of ​​the display panel; a plurality of circuit boards coupled to a non-display area of ​​the display panel; and a plurality of driver circuits on the plurality of circuit boards; Each of the plurality of circuit boards includes a cluster terminal coupled to a pad in the non-display area; the cluster terminal includes a plurality of terminals arranged adjacent to each other on the circuit board; A display device, wherein the cluster terminals on at least two circuit boards have widths that are different from each other.

2. The plurality of circuit boards include: a first outermost circuit board; a second outermost circuit board; and 10. The display device of claim 1, further comprising an intermediate circuit board between said first outermost circuit board and said second outermost circuit board.

3. 3. The display device of claim 2, wherein the cluster terminals on at least one of the first outermost circuit board and the second outermost circuit board and the cluster terminals on the intermediate circuit board have widths that are different from each other.

4. 4. The display device of claim 3, wherein a width of the cluster terminals on the intermediate circuit board is smaller than a width of the cluster terminals on at least one of the first outermost circuit board and the second outermost circuit board.

5. The display device of claim 3 further comprising a first alignment key disposed between adjacent circuit boards.

6. The display device of claim 5 , wherein the first alignment key is disposed between the first outermost circuit board and the intermediate circuit board.

7. 7. The display device of claim 6, wherein the distance between any one of the opposing sides of the first outermost circuit board and the intermediate circuit board and the center of the first alignment key is the same as the distance between the other of the opposing sides and the center of the first alignment key.

8. 7. The display device of claim 6, wherein the distance between one of the opposing sides of the terminal of the first outermost circuit board and the terminal of the intermediate circuit board and the center of the first alignment key is different from the distance between the other of the opposing sides and the center of the first alignment key.

9. one of the opposing sides is a side of a terminal of the first outermost circuit board; The display device according to claim 8 , wherein the other of the opposing sides is a side of a terminal of the intermediate circuit board.

10. The display device of claim 5 , wherein the first alignment key is disposed between the second outermost circuit board and the intermediate circuit board.

11. 11. The display device of claim 10, wherein the distance between any one of the opposing sides of the second outermost circuit board and the intermediate circuit board and the center of the first alignment key is the same as the distance between the other of the opposing sides and the center of the first alignment key.

12. 11. The display device of claim 10, wherein the distance between one of the opposing sides of the terminal of the second outermost circuit board and the terminal of the intermediate circuit board and the center of the first alignment key is different from the distance between the other of the opposing sides and the center of the first alignment key.

13. one of the opposing sides is a side of a terminal of the second outermost circuit board; the other of the opposing sides is a side of a terminal of the second outermost circuit board; The display device of claim 12 , wherein a distance between the one side and the first alignment key is greater than a distance between the other side and the first alignment key.

14. the intermediate circuit boards include a first intermediate circuit board and a second intermediate circuit board; The display device of claim 5 , wherein the first alignment key is disposed between the first intermediate circuit board and the second intermediate circuit board.

15. 15. The display device of claim 14, wherein the distance between any one of the opposing sides of the first intermediate circuit board and the second intermediate circuit board and the center of the first alignment key is the same as the distance between the other of the opposing sides and the center of the first alignment key.

16. 15. The display device of claim 14, wherein the distance between one of the opposing sides of the terminal of the first intermediate circuit board and the terminal of the second intermediate circuit board and the center of the first alignment key is the same as the distance between the other of the opposing sides and the center of the first alignment key.

17. 10. The display device of claim 1, wherein at least two of the circuit boards have different widths.

18. 18. The display device of claim 17, wherein the circuit boards having cluster terminals of different widths have different widths.

19. 20. The display device of claim 18, wherein the circuit board including the larger width cluster terminals has a larger width than the circuit board including the smaller width cluster terminals.

20. The display device of claim 1 , further comprising a fan-out line connected to one side of each of the pads and the pixel.

21. The display device of claim 1 , further comprising a dummy line connected to the other side of each of the pads.

22. The display device of claim 21 , further comprising a second alignment key disposed between adjacent dummy lines.

23. 23. The display device of claim 22, wherein the second alignment keys are disposed on the same layer as the active layer of the pixels.

24. 23. The display device of claim 22, wherein the second alignment key has a triangular shape.

25. The display device of claim 21 , wherein a plurality of cluster pads, including adjacently arranged pads among the plurality of pads, are connected to a plurality of cluster terminals.

26. the second sorting key includes a plurality of sorting keys; 26. The display device of claim 25, wherein the alignment key of the second alignment key passes through a portion of the cluster pad that corresponds to 1 / 2 of the width of the cluster pad and is positioned near an imaginary center line that extends parallel to the extension direction of each of the pads.

27. When the total number of pads included in the cluster pad is odd, the center line is located near the center of a central pad located at the center of the cluster pad, The display device according to claim 26 , wherein the alignment keys in the second alignment key group are arranged on both sides of a dummy line connected to the center pad.

28. When the total number of pads included in the cluster pad is an even number, the alignment keys of the second alignment key are arranged on both sides of an n-th dummy line to the left of the center line, The n is a natural number smaller than k / 2, The display device of claim 26, wherein k is the total number of pads included in the cluster pad.

29. When the total number of pads included in the cluster pad is an even number, the alignment keys of the second alignment key are arranged on both sides of an n-th dummy line to the right of the center line, The n is a natural number smaller than k / 2, The display device of claim 26, wherein k is the total number of pads included in the cluster pad.

30. the second alignment keys include a plurality of alignment keys arranged on both sides of the dummy line with the dummy line interposed therebetween, The display device of claim 24 , wherein each of the plurality of alignment keys in the second alignment key group has a triangular shape.

31. the pads include an outermost cluster pad coupled to the first outermost circuit board and an intermediate cluster pad coupled to the intermediate circuit board; 9. The display device of claim 8, wherein a distance between one of opposing sides of the pads included in the outermost cluster pad and the pads included in the intermediate cluster pad and a center of the first alignment key is different from a distance between the other of the opposing sides and the center of the first alignment key.

32. The display device according to claim 8 , wherein a distance between the one side and a center of the first alignment key is greater than a distance between the other side and the first alignment key.

33. 10. The display device of claim 1, wherein the spacing between adjacent circuit boards is the same.

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