Semiconductor Devices

Abstract

To provide a display device having a driver circuit formed of a thin film transistor having a channel formation region in an oxide semiconductor that reduces a shift in a threshold voltage of the thin film transistor and reduce a current flowing between a source and a drain when the thin film transistor is turned off without increasing the area occupied by the circuit.SOLUTION: A semiconductor device includes a plurality of inverter circuits and a plurality of switches, each inverter circuit including a first thin film transistor having a first oxide semiconductor film and a second transistor having a second oxide semiconductor film, the first thin film transistor and the second thin film transistor are of an enhancement type, a silicon oxide film having an OH group is provided on and in contact with the first oxide semiconductor film and the second oxide semiconductor film, and a silicon nitride film is provided on and in contact with the silicon oxide film.SELECTED DRAWING: Figure 9

Description

[Technical Field]

[0001] The present invention relates to a driver circuit using an oxide semiconductor, a manufacturing method thereof, and a display device including the driver circuit. The present invention relates to a display device and an electronic device equipped with the display device. [Background technology]

[0002] As typified by liquid crystal display devices, thin film transistors formed on flat plates such as glass substrates are , amorphous silicon, and polycrystalline silicon. Thin film transistors using silicon have low field effect mobility, but are suitable for enlarging the area of ​​glass substrates. On the other hand, thin film transistors using polycrystalline silicon have a field effect mobility of Although it is expensive, it requires a crystallization process such as laser annealing, which is necessary for enlarging the area of ​​glass substrates. It has the characteristic that it does not necessarily adapt.

[0003] In response to this, thin film transistors are being fabricated using oxide semiconductors, and they are being used in electronic devices and optical devices. For example, zinc oxide and In-Ga as oxide semiconductors. - Thin film transistors are fabricated using Zn-O oxide semiconductors, and used as switches in image display devices. Patent Documents 1 and 2 disclose techniques used in coupling elements and the like. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-123861 [Patent Document 2] Japanese Patent Application Laid-Open No. 2007-96055 Summary of the Invention [Problem to be solved by the invention]

[0005] Thin film transistors with a channel formation region in an oxide semiconductor are made of amorphous silicon. The oxide semiconductor film has a higher field effect mobility than the thin film transistors used in the previous study. Film formation is possible at temperatures below 300°C using sputtering methods, and oxide semiconductors are used. Thin-film transistors are easier to manufacture than thin-film transistors that use polycrystalline silicon. be.

[0006] Using such oxide semiconductors, thin film transistors can be fabricated on glass substrates, plastic substrates, etc. and forming a liquid crystal display, electroluminescence display or electronic paper. It is expected to be applied to the following areas:

[0007] As the resolution of display devices increases, the number of pixels increases, and the number of gate lines and source lines also increase. As the number of gate lines and source lines increases, the number of drive circuits required to drive them increases. It becomes difficult to mount the C chip by bonding, etc., and manufacturing costs increase. Therefore, the drive circuit is mounted on a glass substrate, a plastic substrate, or the like, using a thin film of one polarity. However, it is preferable to use amorphous silicon to form the transistor. In a unipolar drive circuit configured with this, the threshold voltage shift due to the degradation of the thin film transistor occurs. Also, in a unipolar drive circuit made of polysilicon, there is a problem of threshold voltage. Therefore, amorphous silicon is used. In the unipolar drive circuit using polysilicon and the unipolar drive circuit using polysilicon, the threshold voltage By constructing a compensation circuit for the shift or variation in threshold voltage, The area increases.

[0008] On the other hand, when a unipolar driver circuit is configured using thin film transistors using oxide semiconductors, , the threshold voltage is higher for thin film transistors using amorphous silicon and polysilicon. Although the problem of threshold voltage shift or variation is not significant, the oxide semiconductor The problem of threshold voltage variation due to temporal degradation remains. The solution is to improve the quality of images on the display device or to improve the stability of the operation of the driver circuit. On the other hand, thin film transistors using oxide semiconductors In order to reduce power consumption, the current that flows when the thin film transistor is turned off is reduced. It is hoped that this will happen.

[0009] In view of the above, one embodiment of the present invention is a thin film transistor in which a channel formation region is formed in an oxide semiconductor. In a display device having a driving circuit configured as above, the area occupied by the circuit can be reduced without increasing the area. Shift in the threshold voltage of thin film transistors due to degradation of oxide semiconductors over time and the current ( Hereinafter, it is an object to reduce an off-state current. [Means for solving the problem]

[0010] As one aspect of the present invention, a power supply circuit includes a plurality of inverter circuits and a plurality of switches, The data circuit includes a first oxide semiconductor film, and a gate terminal and a first terminal are connected to a high power supply potential. a first thin film transistor connected to a wiring, and a second oxide semiconductor film; The second terminal of the first thin film transistor is connected to the first terminal, and the second terminal supplies a low power supply potential. a second transistor connected to the wiring and having a gate terminal to which an input signal is supplied, The first thin film transistor and the second thin film transistor are enhancement type. a first oxide semiconductor film and a second oxide semiconductor film, the first oxide semiconductor film and the second oxide semiconductor film being in contact with each other and having an OH group; a silicon oxide film is provided on the display device, and a silicon nitride film is provided on the silicon oxide film in contact with the silicon nitride film; This is the drive circuit for the device. [Effects of the Invention]

[0011] According to one embodiment of the present invention, it is possible to reduce the size of a thin film transistor without increasing the area occupied by a circuit. The shift in threshold voltage can be reduced, and the off-current can be reduced. [Brief explanation of the drawings]

[0012] [Figure 1] FIG. 1 is a diagram illustrating a first embodiment. [Figure 2] FIG. 1 is a diagram illustrating a first embodiment. [Figure 3] FIG. 1 is a diagram illustrating a first embodiment. [Figure 4] FIG. 1 is a diagram illustrating a first embodiment. [Figure 5] FIG. 1 is a diagram illustrating a first embodiment. [Figure 6] FIG. 1 is a diagram illustrating a first embodiment. [Figure 7] FIG. 1 is a diagram illustrating a first embodiment. [Figure 8] FIG. 1 is a diagram illustrating a first embodiment. [Figure 9] FIG. 1 is a diagram illustrating a first embodiment. [Figure 10] FIG. 1 is a diagram illustrating a first embodiment. [Figure 11] FIG. 1 is a diagram illustrating a first embodiment. [Figure 12] FIG. 1 is a diagram illustrating a first embodiment. [Figure 13] FIG. 1 is a diagram illustrating a first embodiment. [Figure 14] FIG. 10 is a diagram illustrating a second embodiment. [Figure 15] FIG. 10 is a diagram illustrating a second embodiment. [Figure 16] FIG. 10 is a diagram illustrating embodiment 3. [Figure 17] FIG. 10 is a diagram illustrating embodiment 3. [Figure 18] FIG. 10 is a diagram illustrating embodiment 3. [Figure 19] FIG. 10 is a diagram illustrating embodiment 3. [Figure 20] FIG. 10 is a diagram illustrating embodiment 3. [Figure 21] FIG. 10 is a diagram illustrating embodiment 3. [Figure 22] FIG. 10 is a diagram illustrating embodiment 3. [Figure 23] FIG. 10 is a diagram illustrating embodiment 3. [Figure 24] FIG. 10 is a diagram illustrating a fourth embodiment. [Figure 25] FIG. 10 is a diagram illustrating a fourth embodiment. [Figure 26] FIG. 10 is a diagram illustrating a fourth embodiment. [Figure 27] FIG. 13 is a diagram illustrating a sixth embodiment. [Figure 28] FIG. 13 is a diagram illustrating a sixth embodiment. [Figure 29] FIG. 10 is a diagram illustrating embodiment 5. DETAILED DESCRIPTION OF THE INVENTION

[0013] The present invention will be described in detail with reference to the accompanying drawings. The present invention is not limited to the above, and various modifications and variations in form and detail are possible without departing from the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that the present invention can be modified in the following manner. It should be noted that the present invention is not limited to the following description. In the structure, the same parts or parts having similar functions are designated by the same reference numerals in different drawings. and the repeated explanation will be omitted.

[0014] (Embodiment 1) In this embodiment, a thin film transistor made of an oxide semiconductor that constitutes a unipolar driver circuit is used. An n-channel thin film transistor is used as the pixel. As a driving circuit, an example of a source line driving circuit and / or a gate line driving circuit will be given. The following will describe and describe the advantages of one embodiment of the present invention.

[0015] 1 shows a schematic diagram of the entire display device. A driving circuit 101, a gate line driving circuit 102, and a pixel section 103 are integrally formed. In the element part 103, the part surrounded by the dotted line frame 110 is one pixel. Although the line driver circuit 102 is provided at one end in the above embodiment, it may be provided in a plurality of positions. In addition, the pixels of the display device may include thin film transistors (hereinafter referred to as TFTs). The display elements are controlled by the source line driving circuit 101 and the gate line driving circuit 10. The signals that drive 2 (clock signal, start pulse, etc.) are transmitted through a flexible printed circuit board ( External input is made via Flexible Print Circuit (FPC) 104. In addition, circuits 105 such as a logic circuit, a power supply circuit, and an oscillation circuit are provided on the substrate, and a driving A signal for controlling the driving circuit is generated on the substrate, and the source line driving circuit 101 and the gate line driving circuit The signal may be supplied to the circuit 102.

[0016] The source line driver circuit 101 and the gate line driver circuit 102 for driving the pixel section are inverters. It is composed of a capacitor circuit, a capacitance element, a switch using elements such as a TFT, a resistance element, etc. As a driving circuit with a unipolar TFT, two n-channel TFTs are combined to form an in- When forming a converter circuit, enhancement type transistors and depletion type transistors are used. When it is formed by combining with an enhancement metal oxide semiconductor (hereinafter referred to as EDMOS circuit), When it is formed by two enhanced transistors (hereinafter referred to as EEMOS circuit), When a MOSFET is formed by combining a MOSFET and a resistor (hereinafter referred to as an ERMOS circuit), On the other hand, thin-film transistors are provided in the pixel area formed on the same substrate as the driver circuit. It is preferable to use an enhancement type transistor as the transistor. Since the threshold voltage of a gate-type transistor is positive, the voltage applied between the gate and source Therefore, the current flowing through the transistor can be made smaller than that of a depletion type transistor, resulting in low power consumption. This is because it allows for electrification.

[0017] Therefore, the inverter circuit of the driver circuit for driving the pixel section is It is preferable to use an EEMOS circuit that is configured with a dispersion type TFT. By using an EEMOS circuit as the inverter circuit, the pixel section and the drive To shorten the manufacturing process by using only one type of transistor when manufacturing an operating circuit Note that the enhancement type transistor described in this embodiment can be formed by using an oxide The semiconductor is used, and its electrical characteristics are that the on-off ratio is 10 at a gate voltage of ±20V. 9 Therefore, the leakage current between the source and drain is small, and low power consumption operation is possible. It can be realized.

[0018] If the threshold voltage of the n-channel TFT is positive, it is called an enhancement type transistor. When the threshold voltage of the n-channel TFT is negative, it is called a depletion-type transistor. This definition will be followed throughout the specification.

[0019] The oxide semiconductor used in this specification is InMO3(ZnO) m (m>0) A thin film is formed on the substrate, and a thin film transistor is fabricated using the thin film as a semiconductor layer. , M is gallium (Ga), iron (Fe), nickel (Ni), manganese (Mn) and copper It represents one or more metal elements selected from the group consisting of Co, Fe, and Ni. In addition to the case of a, there are cases where Ga and the above metal elements are contained, such as Ga and Ni or Ga and Fe. In addition, in the oxide semiconductor, in addition to the metal element contained as M, impurity elements and Some contain Fe, Ni or other transition metal elements, or oxides of these transition metals. In this specification, this thin film is also referred to as an In-Ga-Zn-O based non-single crystal film.

[0020] The crystalline structure of the In-Ga-Zn-O non-single crystal film is formed by sputtering and then heated at 200°C Even if heat treatment is carried out at 500°C, typically 300 to 400°C for 10 to 100 minutes, the amorphous The structure of the TFT can be observed by XRD (X-ray diffraction) analysis. At a gate voltage of ±20V, the on / off ratio was 10 9 Above, create a mobility of 10 or more. A thin film formed using an oxide semiconductor film having such electrical properties can be manufactured. The transistor has a higher transfer rate than thin-film transistors made using amorphous silicon. and a driving circuit configured with a shift register having the thin film transistor. It can be driven quickly.

[0021] In this specification, "A and B are connected" does not mean that A and B are directly connected. In addition to those that are connected electrically, those that are connected electrically are also included. Electrically connected means that there is an object between A and B that has some electrical effect. This represents the case where A and B are roughly the same node via the object.

[0022] Specifically, A and B are connected to each other through a switching element such as a transistor. A and B are connected via the switching element, and A and B are approximately at the same voltage when the switching element is turned on. When A and B are connected via a resistor element, the voltage generated across the resistor element When the potential difference is small enough that it does not affect the operation of the circuit including A and B, This represents a situation where A and B can be regarded as the same node.

[0023] Note that the display device refers to a device having a display element such as a light-emitting element or a liquid crystal element. The display device may include a peripheral driving circuit for driving a plurality of pixels. The peripheral driving circuit for driving the plurality of pixels is formed on the same substrate as the plurality of pixels. The display device may include a flexible printed circuit board (FPC). It is connected via a flexible printed circuit board (FPC) and contains IC chips, resistor elements, and capacitors. It includes a printed wiring board (PWB) on which elements, inductors, transistors, etc. are mounted. The display device may include an optical sheet such as a polarizing plate or a retardation plate. The display device may include a lighting device, a housing, an audio input / output device, an optical sensor, etc. It's okay to be there.

[0024] Note that one pixel refers to one element whose brightness can be controlled. In this case, one pixel refers to one color element, and the brightness is expressed by one color element. Therefore, in the case of a color display device consisting of RGB color elements, the minimum unit of the image is The pixel is assumed to be composed of three pixels: an R pixel, a G pixel, and a B pixel.

[0025] The terms "first," "second," "third," and "Nth" (N is a natural number) used in this specification refer to the configurations. It is added to avoid confusion of elements and is not intended to limit the number. do.

[0026] Next, the gate line driver circuit and the source line driver circuit using EEMOS circuits as inverter circuits An example of a circuit diagram, a top view, and a cross-sectional view of the circuit will be shown and explained.

[0027] Next, we will explain the configuration of a source line driver circuit that uses an EEMOS circuit as an inverter circuit. Make it clear.

[0028] FIG. 2 is a diagram showing the configuration of the source line driving circuit 101 in the display device shown in FIG. The source line driver circuit includes a clock signal level shifter 201, a start pulse level shifter 202, and a Shifter 202, pulse output circuit 203 constituting shift register 251, NAND circuit 2 04, a buffer 205, and a sampling switch 206. The signals are the first clock signal (CLK1), the second clock signal (CLK2), the start The first is a clock signal. A first clock signal (CLK1), a second clock signal (CLK2), and a start pulse (SP, or The input signal is a low-voltage signal input to the driver circuit from the outside. Immediately after that, the clock signal level shifter 201 or the start pulse level shifter 202 Therefore, the signal undergoes amplitude conversion and becomes a signal with a high voltage amplitude. The source line driver circuit is, for example, a pulse output circuit in one stage of a shift register. The sampling pulses drive the sampling switch 206 to The analog video signals of the source lines Sout1 to Sout(N) are sampled simultaneously. In addition, there are other signals such as a scanning direction switching signal for switching the scanning direction. In this embodiment, the first clock signal (CLK1) may be input. , and the second clock signal (CLK2) are used as clock signals. The drive circuit may be driven by inputting a clock signal other than the phase.

[0029] 3A and 3B show the pulse output circuit 20 included in the shift register 251 shown in FIG. 3. In this embodiment, the shift register of the static circuit is The pulse output circuit 300 outputs a start pulse A first switch 301 connected to a terminal to which SP is input, and a second switch 302 connected to a terminal to which SP is input via the first switch 301 a first inverter circuit 302 that inverts and outputs a signal input thereto; a second inverter circuit 303 that inverts and outputs the signal inverted by the second inverter circuit 302; The second switch connected to the terminal to which the signal inverted by the inverter circuit 303 is input It consists of 304 and the third inverter circuit 305. In the circuit diagram shown in Fig. 3(A) The block indicated by the dotted line 350 is a pulse output circuit that outputs a one-stage sampling pulse circuit. The shift register in Fig. 3(A) is composed of N-stage (n is a natural number, 1 < N) pulse output circuits. From the N-stage pulse output circuits, output signals out1 to outN are output from the output terminals of the respective third inverter circuits 305. In the pulse output circuit of the second stage (even stage), which is the next stage after the first stage (odd stage) described above The wiring for inputting the first clock signal and the second clock signal is switched and connected between the first switch 301 and the second switch 304 Hereinafter, in the third stage and subsequent stages, the wirings for alternately inputting the first clock signal and the second clock signal are alternately switched and connected between the first switch 30 1 and the second switch 304

[0030] Fig. 3(B) shows the circuit configuration of the pulse output circuit in detail. The pulse output circuit itself has TFT351, TFT352, TFT353, TFT354, TFT355, TF T356, TFT357, TFT358. The pulse output circuit 331 of the odd stage and the pulse output circuit 332 of the even stage are connected to the wiring 359 for supplying the first clock signal CLK1 and the wiring 360 for supplying the second clock signal CLK2 In the pulse output circuit 331 of the first stage, the first terminal of TFT351 is connected to the terminal to which the start pulse SP is input, the gate terminal is connected to the wiring 359, and the second terminal is T ​The first terminal of the TFT 352 is connected to the gate terminal of the TFT 353 and the second terminal of the TFT 356. The first terminal and the gate terminal are connected to a wiring to which a high power supply potential VDD is supplied, and the second terminal is connected to a TFT 353, the gate terminal of TFT 355, and the gate terminal of TFT 358. The second terminal of the TFT353 is connected to the wiring that supplies the low power supply potential VSS (also called GND). The first terminal and gate terminal of the TFT 354 are connected to a wiring to which a high power supply potential VDD is supplied. The second terminal is connected to the first terminal of the TFT 355 and the first terminal of the TFT 356. The second terminal of the TFT 355 is connected to a wiring to which a low power supply potential VSS is supplied. The gate terminal of the TFT 356 is connected to a wiring 360. The first terminal and the gate terminal of the TFT 357 is connected to the wiring that supplies the high power supply potential VDD, and the second terminal is connected to the first terminal of the TFT358. The second terminal of the TFT 357 in the first-stage pulse output circuit 331 is connected to It is connected to the first terminal of the TFT 351 in the second-stage pulse output circuit 332. The second terminal of the TFT in the pulse output circuit is connected to the pulse output circuit of the next stage. do.

[0031] In FIG. 3B, the TFT 352 and the TFT 353 are the first inverters shown in FIG. The TFT 354 corresponds to the inverter circuit 302 and constitutes an EEMOS circuit. 355 corresponds to the second inverter circuit 303 shown in FIG. 3(A), and The TFT 351 corresponds to the first switch 301 shown in FIG. The TFT 356 corresponds to the second switch 304 shown in FIG. The TFT 356 is an enhancement type transistor, similar to the TFT 352 to the TFT 355. It is preferable to use an enhancement type transistor as a switch. This reduces the off-state current of the transistor, leading to lower power consumption. This can also simplify the manufacturing process.

[0032] In addition, transistors such as n-channel transistors or p-channel transistors A transistor is a device having at least three terminals including a gate, a drain, and a source. The semiconductor device has a channel forming region between the drain region and the source region. A current can be passed through the channel forming region and the source region. The type of transistor varies depending on the structure and operating conditions of the transistor, so it is difficult to determine which is the source or drain. In some cases, it may be difficult to determine whether the item is rain or not. The regions that function as the source and drain are referred to as the first terminal and the second terminal, respectively. The terminal that functions as a gate is referred to as the gate terminal. .

[0033] Here, the circuit operation of the circuit shown in Figures 3(A) and 3(B) will be explained. For the sake of explanation, in Figure 4, the timing chart is shown for the circuit shown in Figure 3(B). In the first stage pulse output circuit, the second terminal of the TFT351 is connected to node A (see Figure 4). , A), the second terminal of the TFT 352 is a node B (indicated as B in FIG. 4), and the second terminal of the TFT 354 is a node The second terminal of the TFT357 is connected to node C (shown as C in FIG. 4), and the second terminal of the TFT357 is connected to node out1. (shown as out1 in Fig. 4). Also, as a node in the circuit shown in Fig. 3(B), In the pulse output circuit, the second terminal of the TFT 351 is connected to a node D (shown as D in FIG. 4), The second terminal of the TFT 352 is a node E (shown as E in FIG. 4), and the second terminal of the TFT 354 is a node The second terminal of the TFT 357 is connected to the node F (shown as F in FIG. 4), and the second terminal of the TFT 357 is connected to the node out2 (shown as ou t2) and the third stage pulse output circuit as a node in the circuit shown in Figure 3(B). In the circuit, the second terminal of the TFT 351 is a node G (denoted as G in FIG. 4).

[0034] In FIG. 4, during a period T1, the start pulse SP is at a high level, and the first clock signal CLK1 is at a high level. The operation when the first clock signal is at the L level and the second clock signal is at the L level will be explained. When the signal CLK1 goes high, the TFT351 in the first stage pulse output circuit is turned on. Then, the voltage level of the start pulse, which is the H level, is the voltage level of node A. Then, the voltage level of node A rises to the H level. As a result, the TFT 353 of the first-stage pulse output circuit is turned on. The voltage level at node B drops to L level. When the voltage level of the first stage pulse output circuit falls to the L level, the TFT 355 is turned off. Then, the H level, which is the voltage level of the high power supply potential, is applied to the node C The voltage level of node B rises to the H level. As a result, the TFT 358 of the first stage pulse output circuit is turned off. The voltage level of the power supply potential, which is H level, raises the voltage level of the node out1 to H level. Since the second clock signal CLK2 is at the L level, the first stage pulse output The TFT 356 of the first stage pulse output circuit and the TFT 351 of the second stage pulse output circuit are turned off.

[0035] Next, in the period T2 in FIG. 4, the start pulse SP is at the L level, and the first clock signal CLK1 The operation when the first clock signal is at L level and the second clock signal is at H level will be explained. When the clock signal goes low, TFT351 in the first stage pulse output circuit goes into the off state. On the other hand, since the second clock signal CLK2 is at H level, the first stage pulse output circuit Therefore, the TFT 356 of the circuit is turned on. The voltage level at node A is maintained at the H level. In the second stage pulse output circuit, the same operation as in the period T1 is performed. When the clock signal CLK2 goes high, the TFT35 of the second stage pulse output circuit 1 is turned on. Then, the voltage level of the node out1 becomes H level, and the voltage level of the node D The voltage level of node D rises to the H level. By this, the TFT353 of the second stage pulse output circuit is turned on. The L level, which is the voltage level of the power supply potential, causes the voltage level of node E to drop to the L level. Then, the voltage level of node E drops to L level, and the second stage pulse output The TFT355 of the circuit is turned off. Then, the voltage level of the high power supply potential is H level. The voltage level of node F rises to the H level. Also, the voltage level of node E rises to the L level. As a result, the TFT 358 of the second stage pulse output circuit is turned off. Then, the voltage level of the high power supply potential, that is, the H level, changes the voltage level of the node out2 to the H level. Since the first clock signal CLK1 is at the L level, the second stage TFT356 of the first pulse output circuit and TFT351 of the third pulse output circuit are in the off state. This becomes:

[0036] Next, in the period T3 in FIG. 4, the start pulse SP is at the L level, and the first clock signal CLK1 The operation when the first clock signal is at H level and the second clock signal is at L level will be explained. When the clock signal goes high, TFT351 in the first stage pulse output circuit turns on. On the other hand, since the second clock signal CLK2 is at the L level, the first-stage pulse output circuit Therefore, the voltage level of the node A drops to the L level. Then, the voltage level of node A drops to the L level, and The TFT 353 of the second pulse output circuit is turned off. The H level at node B raises the voltage level at node B to the H level. When the voltage level rises to H level, TFT355 in the first stage pulse output circuit Then, the voltage level of the low power supply potential becomes L level, and the voltage level of the node C becomes The voltage level of node B rises to the H level. As a result, the TFT 358 of the first stage pulse output circuit is turned on. The voltage level L level causes the voltage level of the node out1 to drop to L level. Since the second clock signal CLK2 is at the L level, the T The TFT 356 and the TFT 351 of the second-stage pulse output circuit are turned off. As with the first stage pulse output circuit in 2, TFT356 in the second stage pulse output circuit is turned on. The voltage level of node F, which was at H level during period T2, The voltage level of the second stage pulse output circuit is maintained at the H level. The same operation as in the period T2 is performed. In the period T3, the first clock signal CLK1 is H. When this level is reached, the TFT 351 in the third-stage pulse output circuit is turned on. The voltage level of the node out2, which is H level, raises the voltage level of the node G to H level. Then, the voltage level of node G rises to the H level, and the third stage power The TFT353 in the pulse output circuit is turned on. By controlling the output, the pulse output circuit is combined into multiple stages as a shift register. It can be driven.

[0037] In the pulse output circuits described in Figs. 3(A), 3(B), and 4, The figure shows a configuration in which a second switch 304 is provided between the first and second nodes. The voltage level of the node C controlled by the TFT 354 connected to the high power supply potential VDD is This is because the voltage is equal to or less than (VDD-VthN) (VthN is the threshold voltage of the TFT 354). The second switch 304 disconnects the node A from the node C and drives the This is preferable because it is possible to increase the driving ability of the TFT 353 by the potential of the node A. The present invention can be applied to a configuration in which the second switch 304 is not provided. It can be achieved.

[0038] In addition, in the configuration of the source line driving circuit, the NAND logic of the signals output from each pulse output circuit is The product (NAND) is taken to generate a signal to drive each source line. In the final stage pulse output circuit, the number of pulse output circuits is set to be greater than the number of source lines. It is preferable to use a configuration in which a signal to be output to the source line is generated by the above-mentioned method.

[0039] FIG. 5A shows the configuration of the clock signal level shifter 201 shown in FIG. This is a clock signal with opposite polarity (CLK1 and CLK2) input to a single input register. The bell shifter circuits are arranged in parallel to perform amplitude conversion (Stage 1), and the subsequent buffer The first stage (Stage 2 to Stage 4) uses each other's output as its inverted input signal. The configuration is as follows.

[0040] The operation of the circuit shown in Figure 5(A) will be explained. are the three potentials of VSS, VDD0, and VDD, and VSS <VDD0<VDDとする。クロ The amplitude of the clock signal is level-shifted at the input of the source line driver circuit, resulting in low power consumption. It is possible to reduce power consumption and noise. The TFT603, TFT606, and TFT608 have a double gate structure. They may be single gate or multi-gate structures with three or more gate electrodes. For other TFTs, there is no particular restriction on the number of gate electrodes.

[0041] From the signal input section (CLK in1), the amplitude of L level / H level = VSS / VDD0 A first input clock signal (CLK in1) having a first input clock signal (CLK in1) is input. When the signal is at H level, the TFTs 602 and 604 are turned on, and the gate voltage of the TFT 603 is The voltage level of the electrode becomes L level and turns off. Here, the on-resistance of the TFT 602 is Therefore, the node α is set to the L level. When the first input clock signal is at L level, the TFTs 602 and 604 are in the OFF state. Therefore, the voltage level of the gate terminal of the TFT 603 is increased through the TFT 601 that is in saturated operation. The voltage level rises to VDD, and when the voltage reaches (VDD-VthN), the TFT601 The gate electrode of the TFT 603 is in a floating state. 3 is turned on, and the potential of the node α rises to VDD. As the potential of the node α rises, the potential of the gate terminal of the TFT 603, which is in a floating state, The potential rises and becomes higher than VDD, exceeding (VDD+VthN). Therefore, the H level that appears at node α is equal to VDD. Therefore, the L level of the output signal The signal goes to VSS, and the H level goes to VDD, completing the amplitude conversion.

[0042] On the other hand, the signal input section (CLK in2) outputs the third signal, which also has an amplitude of VSS / VDD0. The input clock signal (CLK in2) of T A one-input level shifter circuit configured with TFT606 to TFT609 and a capacitor 610 The amplitude is converted by the , and a signal with an amplitude of VSS / VDD is output to node β. The signal appearing at node α has a polarity different from that of the first input clock signal. The signal appearing at node β is inverted and polarized relative to the second input clock signal. The genders are reversed.

[0043] The level shifter described in FIG. 5(A) takes into consideration the load on the pulse after amplitude conversion, A buffer stage (Stage 2 to Stage 5) is provided after the level shifter circuit (Stage 1). The inverter circuit that constitutes this buffer stage is a two-input type, and The reason for using the two-input type is to reduce power consumption. In the shifter circuit, when the TFT 602 is in the on state, the TFTs 601 to 606 Through 02, a through current flows between VSS and VDD. By using a two-input type, This prevents through current from flowing during operation.

[0044] In Figure 5(A), in the inverter circuit of Stage 2, the gate terminal of TFT611 The signal input to the gate terminal of the TFT612 has the opposite polarity. Therefore, the first input clock signal and the second input clock signal are By utilizing the fact that the polarities of the signals are inverted, the output signal appearing at node α and the output signal appearing at node β The output signal appearing at the input terminal is used as an inverted input signal of the other signal.

[0045] The operation of the inverter circuit will be explained. Here, we will look at the TF The operation of the inverter circuit consisting of T611 to 614 and the capacitor 615 will be described. . The other part of Stage 2 is an inverter consisting of TFTs 616 to 619 and a capacitor 620. a capacitor circuit, an inverter consisting of TFTs 621 to 624 and a capacitor 625 in Stage 3; The inverter circuit is composed of the TFTs 626 to 629 and the capacitor 630 in Stage 3. Path, an inverter circuit consisting of TFTs 631 to 634 and a capacitor 635 in Stage 4 , an inverter circuit consisting of TFTs 636 to 639 and a capacitor 640 in Stage 4. The operation is similar for any other inverter circuit.

[0046] When the signal input to the gate terminal of the TFT611 is at H level, the TFT611 is in the ON state. The potential of the gate electrode of the TFT613 rises to VDD, and the potential (VDD-V thN), TFT611 turns off and the gate terminal of TFT613 On the other hand, the signal input to the gate electrodes of the TFTs 612 and 614 is at L level. Therefore, the TFTs 612 and 614 are turned off. The potential of the gate electrode of the TFT 613 is Since the voltage rises to (VDD-VthN), the TFT613 is turned on, and the node γ The potential of the capacitor 615 rises to VDD. As a result, the potential of node γ rises and the gate of TFT613, which is in a floating state, The potential of the output electrode is raised to a level higher than VDD (VDD + Vt hN), the H level appearing at node γ becomes equal to VDD.

[0047] On the other hand, when the signal input to the gate terminal of the TFT611 is at L level, the TFT611 is turned on. The gate terminals of the TFTs 612 and 614 are turned on by inputting a high level. Therefore, the potential of the gate electrode of the TFT 613 becomes L level, and the node γ The level appears.

[0048] A pulse is also output to node δ by a similar operation. A pulse with the opposite polarity to the pulse appearing at γ is output.

[0049] After that, the same operation is performed in Stage 3 and Stage 4. At node ζ, A pulse with the opposite polarity to the pulse appearing at node ε is output. Finally, the signal output section (C A pulse is output to the signal output section (CLK out1) and the signal output section (CLK out2).

[0050] Figure 5(B) shows how the amplitude of the clock signal is converted. The amplitude of the input signal is , L level / H level = VSS / VDD0, and the amplitude of the output signal is The voltage is VSS / VDD.

[0051] FIG. 5C shows the level shifter 202 for the start pulse (SP) shown in FIG. In the case of a start pulse, since it does not have an inverted signal, it is a one-input type level shifter. The output of the inverter circuit (Stage 1) is input to a one-input inverter circuit (Stage 2). Furthermore, the outputs of Stage 1 and Stage 2 are used to form a two-input inverter. The circuit operation is as follows: the one-input level shifter circuit is The same applies to the single-input inverter circuit. Compared to the shifter circuit, the amplitude of the input signal is L level / H level = VSS / VDD However, the operation within the circuit is the same except that there is no amplitude conversion between the input and output pulses. Therefore, the explanation will be omitted here. In addition, in FIG. 5(C), a one-input inverter circuit ( Stage 1) has TFTs 641 to 644 and a capacitor 645, and is a one-input inverter The circuit (Stage 2) has TFTs 646 to 649 and a capacitor 650, and is a two-input type inverter. The converter circuit (Stage 3) has TFTs 651 to 654 and a capacitor 655.

[0052] Figure 5(D) shows how the amplitude of the start pulse (SP) is converted. The amplitude of the output signal is the same as the clock signal, L level / H level = VSS / VDD0. The width is L level / H level = VSS / VDD.

[0053] 6A shows the two-input NAND circuit 204 shown in FIG. is similar to a one-input inverter circuit, and the signal input part in a one-input inverter circuit The TFT702 and 703 are connected in series with the TFT705 and 706. The only difference is that the TFT 701 in FIG. 6(A) has a double gate structure. This shows an example of

[0054] When a high level is input to both the signal input section (In1) and the signal input section (In2), TFT702, 703, 705, and 706 are turned on, and the voltage level of the gate terminal of TFT704 The signal output (Out) goes to L level and is turned off. Either or both of the signal input section (In1) and signal input section (In2) are at L level. When this is input, there is no conduction between the gate terminal of the TFT 704 and the low power supply potential VSS, so T The voltage level of the gate terminal of the FT704 rises to VDD and turns on. By the action of 07, the potential is higher than (VDD+VthN), and the signal output section (Out ) appears at the H level of the potential VDD.

[0055] FIG. 6B shows the configuration of the buffer 205 shown in FIG. 2, which is a one-input inverter. Circuit (Stage 1) and two-input inverter circuit (Stage 2 to Stage 4) Both the one-input inverter circuit and the two-input inverter circuit are configured as follows: The operation has been explained in the level shifter section, so the explanation will be omitted here. In (B), the one-input inverter circuit (Stage 1) includes TFTs 711 to 714. and a capacitor 715, and a two-input inverter circuit (Stage 2) includes TFTs 716 to 719 and a capacitor 720, and the two-input inverter circuit (Stage 3) is a TFT 72 1 to 724 and a capacitance 725, and a two-input inverter circuit (Stage 4) is TF T726 to 729 and capacity 730.

[0056] FIG. 6C shows the configuration of the sampling switch 206 shown in FIG. A sampling pulse is input from the output unit (25), and the 12 TFTs 73 arranged in parallel are 1 are controlled simultaneously. The input electrodes (1) to (12) of the 12 TFT731 are connected to the analog When a video signal is input and a sampling pulse is input, the potential of the video signal is called the source voltage. It acts to write on the lines.

[0057] The display device shown in this embodiment mode includes a transistor of a driver circuit for driving a pixel portion. The TFT is a unipolar enhancement type TFT having the same polarity as the pixel TFT. This makes it possible to omit the process for forming a complementary circuit configuration, This can contribute to reducing manufacturing costs and improving yields.

[0058] Next, FIG. 7 shows the circuit configuration of the gate line driving circuit 102 in the display device shown in FIG. The clock signal level shifter 751 and the start pulse level shifter 752 are , a pulse output circuit 753, a NAND circuit 754, and a buffer It has a 755.

[0059] The gate line driving circuit receives a first clock signal (CLK1) and a second clock signal (CL These input signals are input from the outside with low voltage amplitude. Immediately after being input as a signal of width, the level shifter 751 for the clock signal and the level shifter 752 for the start pulse The amplitude is converted by the level shifter 752 and input to the drive circuit as a signal with a high voltage amplitude. can be.

[0060] The pulse output circuit 753, the buffer 755, the clock signal level shifter 751, Regarding the configuration and operation of the start pulse level shifter 752 and the NAND circuit 754 Since the circuit configuration is similar to that used in the source line driver circuit, the description thereof will be omitted here.

[0061] Next, a layout diagram (top view) of the pulse output circuit shown in FIG. 3(B) is shown in FIG. In FIG. 8, the first stage of the pulse output circuit is This shows the following.

[0062] The pulse output circuit of FIG. 8 includes a power supply line 801 to which a power supply potential VDD is supplied, a power supply line 802 to which a power supply potential GND is supplied, and a A power supply line 802, a control signal line 803, a control signal line 804, a control signal line 805, and T FT351, TFT352, TFT353, TFT354, TFT355, TFT356 , TFT357, and TFT358.

[0063] In FIG. 8, an oxide semiconductor film 806, a first wiring layer 807, a second wiring layer 808, a contact The first wiring layer 807 is a layer on which a gate electrode is formed. The second wiring layer 808 is a wiring for connecting a source electrode or a drain electrode of a transistor. This is the layer to be formed.

[0064] The connection relationships of the circuit elements in FIG. 8 are the same as those in FIG. 3(B). Among them, the control signal line 803 is a line through which a start pulse SP is supplied, and the control signal line 804 is a wiring to which a first clock signal is supplied, and a control signal line 805 is a wiring to which a second clock signal is supplied. The power supply line 801 is a wiring to which a high power supply potential VDD is supplied, and the power supply line 802 is a wiring to which a high power supply potential VDD is supplied. The power supply line 802 is a wiring to which the low power supply potential VSS is supplied.

[0065] In the layout diagram of the pulse output circuit in FIG. 8, in this embodiment, TFTs 351 to 352 are The FT358 is configured with EEMOS. Therefore, the off current flowing through the TFT is In addition, a TFT using an oxide semiconductor film in the channel formation region can be Compared to TFTs that use amorphous silicon in the channel formation region, the mobility and other electrical characteristics are This allows the area occupied by TFTs in a circuit to be reduced without compromising performance. can.

[0066] In the layout diagram of the pulse output circuit in FIG. 8, the TFTs 351 to 358 The shape of the channel forming region may be U-shaped. Although the size is shown as the same, the size of the TFT is changed appropriately depending on the size of the load in the subsequent stage. That's fine.

[0067] Next, the manufacturing process of the TFT in the layout diagram explained in FIG. 8 will be explained with reference to FIG. 9. In Figure 9, two n-channel thin film transistors are used to configure the driver circuit. 8. The cross section of the inverter circuit, for example, TFT 354 and TFT 355 in FIG. The cross section of the TFT 354 and the TFT 355 is taken along the dotted line AB in FIG. , and CD.

[0068] The pixel portion and the driver circuit are formed on the same substrate, and the pixel portion is arranged in a matrix. The voltage applied to the pixel electrode is switched on and off using an enhancement type transistor placed in the pixel electrode. The enhancement type transistor disposed in this pixel section uses an oxide semiconductor. The electrical characteristics are as follows: the on / off ratio is 10 at a gate voltage of ±20V. 9 That's all Therefore, the leakage current is small, and low power consumption driving can be achieved.

[0069] The cross-sectional structure of the inverter circuit of the drive circuit is shown in Figure 9(A). T354 and TFT355 have a gate electrode provided under the semiconductor layer via a gate insulating film. This is an example of a thin film transistor in which wiring is provided on a semiconductor layer.

[0070] In FIG. 9A, a first gate electrode 901 and a second gate electrode 902 are formed on a substrate 900. The first gate electrode 901 and the second gate electrode 902 are made of aluminum. It is desirable to form it from a low-resistance conductive material such as aluminum (Al) or copper (Cu), but aluminum alone is also suitable. However, since it has poor heat resistance and is prone to corrosion, it is necessary to combine it with a heat-resistant conductive material. The heat-resistant conductive material is titanium (Ti), tantalum (Ta), tungsten (Tb) and tantalum (Tc). Stainless steel (W), molybdenum (Mo), chromium (Cr), neodymium (Nd), scandium (Sc), or an alloy containing the above elements, or a combination of the above elements The film is formed of an alloy film containing a combination of the above elements or a nitride film containing the above elements as components.

[0071] For example, the two-layer laminate structure of the first gate electrode 901 and the second gate electrode 902 is as follows: , a two-layer laminate structure in which a molybdenum layer is laminated on an aluminum layer, or a molybdenum layer on a copper layer Two-layer structure with a copper layer and a titanium nitride layer or a tantalum nitride layer on a copper layer a two-layer structure in which a titanium nitride layer and a molybdenum layer are laminated; or a two-layer structure in which a titanium nitride layer and a molybdenum layer are laminated. The three-layer structure is a tungsten layer or tungsten nitride layer and an aluminum layer. and silicon alloy or aluminum and titanium alloy, and titanium nitride or titanium layer are laminated. It is preferable to use a laminate in this manner.

[0072] Also, on the gate insulating layer 903 covering the first gate electrode 901 and the second gate electrode 902 A first oxide semiconductor film 905 and a second oxide semiconductor film 907 are provided.

[0073] The first oxide semiconductor film 905 is provided with a contact hole formed in the gate insulating layer 903. A first wiring 909 directly connected to the first gate electrode 901 via 904, and a second oxide A second wiring 910 is provided extending over the second oxide semiconductor film 907. A third wiring 911 is provided on the substrate 07.

[0074] The TFT 354 has a first gate electrode 901 and a gate insulating layer 903 interposed therebetween. The first oxide semiconductor film 905 overlaps with the electrode 901. Connected to 10.

[0075] The TFT 355 is connected to a second gate electrode 902 via a gate insulating layer 903. a second oxide semiconductor film 907 overlapping the gate electrode 902; a second wiring 910; It is connected to wiring 911.

[0076] In addition, between the first oxide semiconductor film 905 and the first wiring 909, + providing a layer 906a; Between the first oxide semiconductor film 905 and the second wiring 910, n + A layer 906b is provided. , and n is formed between the second oxide semiconductor film 907 and the second wiring 910. + layer 908a, and a second Between the oxide semiconductor film 907 and the third wiring 911, n + A layer 908b is provided.

[0077] The n-type semiconductor layer described in this embodiment can function as a source region or a drain region. + layer 906a , 906b, 908a, 908b are In-Ga-Zn-O based non-single crystal films, and the first The oxide semiconductor film 905 and the second oxide semiconductor film 907 were formed under different film formation conditions. In this embodiment, the n + layer 906a , 906b, 908a, and 908b are In-Ga-Zn-O based non-single crystal films, and at least Both contain amorphous components. + layers 906a, 906b, 908a, 908b may contain crystalline grains (nanocrystals) in its amorphous structure. + layer 9 The crystal grains (nanocrystals) in 906a, 906b, 908a, and 908b have a diameter of 1 nm to 1 0 nm, typically about 2 nm to 4 nm.

[0078] n + By providing layers 906a, 906b, 908a, and 908b, the first metal layer The wiring 909, the second wiring 910, the third wiring 911, the first oxide semiconductor film 905, the second The oxide semiconductor film 907 has a good junction and is thermally stable compared to a Schottky junction. It can also supply carriers to the channel (source side), or stably absorbs the carriers in the channel (drain side), or reduces the resistance component to the wiring. In order to avoid this, we actively + It is effective to provide a layer. Good mobility can be maintained even at high drain voltages.

[0079] As shown in FIG. 9A, a first wiring 901 electrically connected to a first oxide semiconductor film 905 9. 09 is connected to the TFT 354 through a contact hole 904 formed in the gate insulating layer 903. The first gate electrode 901 is directly connected to the first gate electrode 902. By directly connecting the first gate electrode 902 to the first gate electrode 901, good contact can be achieved. The first gate electrode 901 and the first Compared with the case where the wiring 909 is connected via another conductive film, for example, a transparent conductive film, The number of holes and contact holes can be reduced, thereby reducing the occupied area. do.

[0080] As shown in FIG. 9A, a first wiring 909, a second wiring 910, a third wiring 911, a third wiring 912, a A silicon oxide film containing an OH group was formed on the first oxide semiconductor film 905 and the second oxide semiconductor film 907. In this embodiment, a silicon nitride film 912 and a silicon nitride film 913 are formed. A compound having an OH group, such as C2H5)4)), is used to form a film on the wiring layer and the oxide semiconductor film. It is preferable to form a silicon oxide film on the silicon substrate, and the silicon oxide film contains OH groups. The silicon oxide film containing the group was prepared by mixing TEOS and O2 using the plasma CVD method at a reaction pressure of 40 P. a, substrate temperature 300-400°C, high frequency (13.56MHz) power density 0.5-0. 8W / cm 2It can be formed by discharging at 1000 kJ / cm. The silicon nitride film 913 can also be produced by plasma CVD using SiH4 and NH3. As disclosed in this embodiment, the first oxide semiconductor film 905 and the second oxide semiconductor film On the compound semiconductor film 907, a silicon oxide film 912 containing OH groups and a silicon nitride film 913 are successively formed. By forming the oxide semiconductor film, dangling bonds in the oxide semiconductor film are terminated by OH groups, and Furthermore, it is possible to prevent a decrease in resistance due to oxygen vacancies in the oxide semiconductor film. As a result, the shift in the threshold voltage of the TFT is reduced, and the transistor is an enhancement type. The effect of reducing the off-state current due to this can be maintained.

[0081] As disclosed in this embodiment, the first oxide semiconductor film 905 and the second oxide semiconductor film A silicon oxide film 912 containing OH groups and a silicon nitride film 913 are successively formed on the semiconductor film 907. By forming a silicon nitride film on the oxide semiconductor, the silicon nitride film functions as a passivation film. In other words, the oxide semiconductor film is not in direct contact with the silicon nitride film. The resistance reduction caused by nitridation with nitrogen can be reduced. By disposing a silicon oxide film containing silicon nitride between the silicon nitride film and the oxide semiconductor film, The stress caused by film formation is alleviated, and the stress caused by the stress is reduced on the oxide semiconductor. This can reduce hydrogenation (or reduction) of the oxide semiconductor that occurs in the above-described manner.

[0082] Note that in FIG. 9A, the first oxide semiconductor film 905 and the second oxide semiconductor film 907 are in + Although the configuration in which layers 906a, 906b, 908a, and 908b are provided is shown in FIG. As shown in (B), it is not necessarily required to provide the wiring through the contact hole 904. The connection between the line layer and the gate electrode can be selected to be connected or not connected depending on the circuit configuration. That's fine.

[0083] 9A and 9B, the first oxide semiconductor film 905 and the second oxide semiconductor film 90 On the substrate 7, a silicon oxide film 912 containing OH groups and a silicon nitride film 913 were successively formed. For example, when separating the source region and the drain region, a so-called channel A silicon oxide film containing OH groups is formed as a stop film, and a silicon nitride film is formed on top of it. An example is shown and explained in Fig. 10(A) and (B). In the cross-sectional structure of the TFT shown in Fig. 9(A) and (B), are given the same symbols.

[0084] In FIG. 10A, the first oxide semiconductor film 905 and the second oxide semiconductor film 907 On the top, a silicon oxide film 912 containing OH groups as shown in FIGS. 9(A) and 9(B) is formed in the same manner. The first channel protection layer 1001 and the second channel protection layer 1002 are also shown in FIG. ) covers the first channel protection layer 1001 and the second channel protection layer 1002, and + The layers 906a, 906b, 908a, and 908b are formed and etched to form the source region. The n + Layers 906a, 906b, 908a, and 908b After the formation, as shown in FIG. 10(A), a first wiring 909, a second wiring 910, and a third wiring 911 are formed. and forming a first channel protection layer 1001, a second channel protection layer 1002, and a second channel protection layer 1003 on the first channel protection layer 1001, the second channel protection layer 1002, and a second channel protection layer 1003 on the second channel protection layer 1002. A silicon nitride film is formed on the first wiring 909 to the third wiring 911. 10A, the oxide semiconductor film 905 and the second oxide semiconductor film 907 are formed on the oxide semiconductor film 905. By forming a silicon oxide film and a silicon nitride film, it functions as a passivation film. The silicon nitride film is not in direct contact with the oxide semiconductor film. The nitride semiconductor film is nitrided by the nitrogen in the silicon nitride film, and the decrease in resistance is reduced. As a result, the shift in the threshold voltage of the TFT can be reduced, and the enhancement The effect of reducing the off-state current due to the use of a gate-type transistor can be maintained.

[0085] The cross-sectional structure of the TFT shown in FIG. 10(A) is formed by forming a silicon oxide film as a channel stop film. A silicon nitride film is disposed on top of the silicon nitride film. As in (A), + The structure in which a layer is provided is shown, but as in FIG. 9(B), + Layer Alternatively, the configuration shown in FIG. 10(B) may be used.

[0086] In Fig. 9(A), (B), Fig. 10(A), (B), the inverse staggered TFT is explained. However, the structure of the TFT of this embodiment is not limited to the inverted staggered type TFT. The same effect can be achieved in a lens-type TFT. An example of the surface structure will be described below. Note that the cross section of the TFT shown in FIGS. 11(A) and 11(B) is In terms of structure, the same components as those in Figures 9(A) and (B) are designated by the same reference numerals. do.

[0087] In FIG. 11A, a first wiring 909, a second wiring 910, The third wiring 911 is + Layers 906a, 906b, 908a, and 908b are laminated together to form The first oxide semiconductor film 905 and the second oxide semiconductor film 907 are n + Layers 906a, 906b, 908a, and 908b are stacked to form a first wiring 909 to a third wiring 11(A), the opening of the n + layer 906a, 906b, 908a, and 908b, and the first oxide semiconductor film 905 and the second oxide semiconductor film A silicon oxide film 1101 containing OH groups is formed on the semiconductor film 907. On the film 1101, a silicon nitride film 1102 is formed, which functions as a passivation film. On the first oxide semiconductor film 905 and the second oxide semiconductor film 907, As shown in Fig. 1, by forming a silicon oxide film and a silicon nitride film containing OH groups, a passive The silicon nitride film, which functions as a dielectric film, is not in direct contact with the oxide semiconductor film. That is, the oxide semiconductor film is nitrided by the nitrogen in the silicon nitride film. Furthermore, the silicon oxide film containing OH groups can be made into a silicon nitride film. By disposing the silicon nitride film between the silicon nitride film and the oxide semiconductor film, the stresses associated with the formation of the silicon nitride film can be reduced. The stress applied to the oxide semiconductor is released by the stress. As a result, the threshold voltage of the TFT is shifted. This reduces the off-state current due to the enhancement type transistor. It can be sustained.

[0088] The cross-sectional structure of the TFT shown in FIG. 11(A) is a silicon oxide film formed on a coplanar TFT. A silicon nitride film is disposed on top of the silicon nitride film. (A), as in Figure 10(A), + 9(B) and 1 0(B) and n + A structure shown in FIG. 11B in which no layer is provided may also be used.

[0089] 9A and 9B to 11A and 11B, the oxide semiconductor film is a silicon nitride film. The resistance reduction caused by nitridation due to the nitrogen in the oxide semiconductor is reduced, and the hydrogen in the oxide semiconductor is also reduced. This reduces the oxidation (or reduction) of the TFT, resulting in a shift in the threshold voltage. This reduces the off-state current due to the enhancement type transistor. The pixels of the display device are made up of enhancement-type TFTs. When manufacturing the TFTs that form the driver circuit and the TFTs that form the gate electrodes, gate electrodes are formed above and below the oxide semiconductor film. The threshold voltage is controlled by providing a gate electrode, and the enhancement is achieved by controlling the voltage applied to the two gate electrodes. Compared to the structure of an enhancement-type TFT, an enhancement-type TFT can be formed with a simpler structure. It is possible.

[0090] Next, the two n-channel thin films shown in FIGS. 9(A), (B) to 11(A), (B) were The cross section of the inverter circuit that uses the membrane transistor to configure the drive circuit is shown in Figure 9(A ) as an example, the manufacturing process will be explained below with reference to Figures 12(A), 12(B), and 12(C). The cross sections of the TFT 354 and the TFT 355 are shown along the dotted lines AB and C in FIG. This shows D.

[0091] A first conductive film is formed on a substrate 900 by sputtering, and a first photomask is used. The first conductive film is selectively etched to form the first gate electrode 901 and the second gate electrode 902. Next, the first gate electrode 901 and the second gate electrode 902 are formed. A gate insulating layer 903 is formed by plasma CVD or sputtering. The edge layer 903 is formed by depositing a silicon oxide layer, a silicon nitride layer, or an oxynitride layer using a CVD method, a sputtering method, or the like. The silicon layer or silicon nitride oxide layer can be formed as a single layer or a stacked layer. The insulating layer 903 may be formed by a CVD method using organic silane gas. It is possible. Organosilane gases include ethyl silicate (TEOS: chemical formula Si(OC2H5 )4), tetramethylsilane (TMS: chemical formula Si(CH3)4), tetramethylcyclo Tetrasiloxane (TMCTS), Octamethylcyclotetrasiloxane (OMCTS) , hexamethyldisilazane (HMDS), triethoxysilane (SiH(OC2H5)3 ), trisdimethylaminosilane (SiH(N(CH3)2)3), and other silicon-containing compounds. It can be used.

[0092] Next, the gate insulating layer 903 is selectively etched using a second photomask to form the first A contact hole 904 is formed that reaches the gate electrode 901. The plan view corresponds to FIG. 12(A).

[0093] Next, an oxide semiconductor film is formed by sputtering, and then an n + A layer is deposited. Before forming the oxide semiconductor film by a sputtering method, argon gas was introduced to form a plasma. A reverse sputtering process is performed to generate a ferrite layer, and the surface of the gate insulating layer 903 and the contact hole 90 It is preferable to remove any dust adhering to the bottom surface of the target 4. The substrate was heated by applying a voltage to the substrate side using an RF power supply in an argon atmosphere without applying a voltage to the substrate. This is a method of forming plasma in the surface to modify it. Alternatively, an atmosphere containing oxygen, hydrogen, N2O, etc., may be used. Alternatively, it may be carried out in an argon atmosphere to which Cl2, CF4, etc. have been added. good.

[0094] Then, the oxide semiconductor film and the n + Etching of layers Next, a second conductive film is formed by sputtering, and a fourth photomask is used. The second conductive film is selectively etched to form a first wiring 909, a second wiring 910, and a third wiring 911. The first wiring 909 is connected to the first gate electrode 911 through the contact hole 904. Before forming the second conductive film by sputtering, Reverse sputtering is performed by introducing a gon gas to generate plasma, and the surface of the gate insulating layer 903 is , n + Remove any dust adhering to the surface of the layer and the bottom of the contact hole 904. Reverse sputtering is a method of sputtering a substrate in an argon atmosphere without applying a voltage to the target side. This method involves applying voltage to the plate using an RF power source to form plasma on the substrate and modify the surface. In place of argon, nitrogen, helium, etc. may be used. It may be carried out in an atmosphere containing oxygen, hydrogen, N2O, etc. It may be carried out in an atmosphere containing I2, CF4, etc.

[0095] When etching the second conductive film, n+ The oxide semiconductor film is partially Switch and + Layers 906a, 906b, 908a, and 908b: first oxide semiconductor film 905, and a second oxide semiconductor film 907 is formed. and the first oxide semiconductor film 905 and the second oxide semiconductor film 906 overlapping with the second gate electrode. The thickness of 907 becomes thinner. When this etching is completed, TFT354 and TFT355 The cross section at this stage is shown in Figure 12(B).

[0096] Next, a heat treatment is carried out at 200°C to 600°C in an air atmosphere or a nitrogen atmosphere. The timing of this heat treatment is not limited, and it can be performed at any time after the formation of the oxide semiconductor film. That's fine.

[0097] Next, a silicon oxide film 912 containing OH groups is formed by a CVD method using organic silane gas. The organic silane gas is ethyl silicate (TEOS: chemical formula Si(OC2H5)4). , tetramethylsilane (TMS: chemical formula Si(CH3)4), tetramethylcyclotetra Siloxane (TMCTS), Octamethylcyclotetrasiloxane (OMCTS), Hexamethylcyclotetrasiloxane dimethyldisilazane (HMDS), triethoxysilane (SiH(OC2H5)3), Use silicon-containing compounds such as dimethylaminosilane (SiH(N(CH3)2)3) A silicon nitride film 913 is formed on the silicon oxide film 912 containing OH groups. The silicon oxide film 912 containing H groups and the silicon nitride film 913 act as a passivation film. A silicon nitride film having a function can be configured not to be in direct contact with the oxide semiconductor film. a silicon oxide film containing an OH group and a silicon nitride film are successively formed on an oxide semiconductor film; This leads to the termination of dangling bonds in the oxide semiconductor film by OH groups and the formation of oxide semiconductor films. This prevents the decrease in resistance due to oxygen deficiency in the film, and as a result, The shift in the threshold voltage of the enhancement transistor is reduced. The cross section at this stage is shown in Figure 12(C). is equivalent to

[0098] The silicon oxide film 912 and the silicon nitride film 913 containing OH groups are provided with a fifth After selectively etching the contact holes using a photomask, A third conductive film is formed using the same material as the electrode. Then, a sixth photomask is used to The third conductive film is selectively etched to electrically connect it to the same layer as the first to third wirings. A connection wiring for this purpose is formed.

[0099] In a light-emitting display device using a light-emitting element, a plurality of thin film transistors are provided in a pixel portion, and a pixel Even in the element part, the gate terminal of one TFT and the source or drain of another transistor It has a contact hole for direct connection to the electrode. The contact holes are formed when forming contact holes in the gate insulating film using the second photomask. The same mask can be used to form the two layers.

[0100] In addition, in LCD displays and electronic paper, the wiring board is used to connect to external terminals such as FPCs. When forming a contact hole that reaches the gate wiring in the terminal portion, a second photomask When forming contact holes in the gate insulating film using a mask, the same mask is used. It is possible.

[0101] The above-described process sequence is an example and is not particularly limited. Although the number of sheets increases, the photomask for etching the second conductive film and the + Layer and oxide semiconductor film Alternatively, etching may be performed using separate photomasks that etch a portion of the film.

[0102] 13A to 13C illustrate an example of a manufacturing process different from that shown in FIG.

[0103] A first conductive film is formed on a substrate 900 by sputtering, and a first photomask is used. The first conductive film is selectively etched to form the first gate electrode 901 and the second gate electrode 902. Next, the first gate electrode 901 and the second gate electrode 902 are formed. A gate insulating layer 903 is formed by plasma CVD or sputtering.

[0104] Next, an oxide semiconductor film is formed by sputtering, and then an n + A layer is deposited.

[0105] Then, a second photomask is used to selectively remove the oxide semiconductor film and the n + Etching of layers In this way, the oxide film overlapping the first gate electrode 901 and the gate insulating layer 903 is formed. Semiconductor film 905, and n + A layer 906 is formed, covering the second gate electrode 902 and the gate insulating layer The oxide semiconductor film 907 overlaps with the oxide semiconductor film 903 interposed therebetween. + Layer 908 is formed. The cross section at the floor level corresponds to Figure 13(A).

[0106] Next, the gate insulating layer 903 is selectively etched using a third photomask to form a second A contact hole 904 is formed that reaches the gate electrode 902. The plan view corresponds to FIG. 13(B).

[0107] Next, a second conductive film is formed by sputtering, and a fourth photomask is used to selectively The second conductive film is etched to form a first wiring 909, a second wiring 910, and a third wiring 911. Before forming the second conductive film by sputtering, argon gas is introduced. The surface of the gate insulating layer 903, n + layer 90 6, 908 and the bottom of the contact hole 904. It is preferable to use nitrogen or helium instead of argon. It may be performed in an argon atmosphere to which oxygen, hydrogen, N2O, etc. have been added. The treatment may be carried out in an atmosphere containing Cl2, CF4, etc.

[0108] In the steps described with reference to FIGS. 13(A) to 13(D), the contact hole 904 is formed. After that, the second conductive film can be formed without performing any other film formation. The number of processes in which the bottom surface of the contact hole is exposed can be reduced, and the material of the gate electrode can be In the process described in FIGS. 13(A) to 13(D), In this case, the oxide semiconductor film is in contact with the gate electrode surface exposed through the contact hole 904. Therefore, the gate electrode material is etched during the oxide semiconductor film etching process. Therefore, it is necessary to select etching conditions or gate electrode materials that do not cause such damage.

[0109] When etching the second conductive film, n + The oxide semiconductor film is partially Switch and +Layers 906a, 906b, 908a, and 908b: first oxide semiconductor film 905, and a second oxide semiconductor film 907 is formed. and the first oxide semiconductor film 905 and the second oxide semiconductor film 906 overlapping with the second gate electrode. The thickness of 907 becomes thinner. When this etching is completed, TFT354 and TFT355 is completed.

[0110] The cross section at this stage corresponds to FIG. 13(C).

[0111] Next, a heat treatment is carried out at 200°C to 600°C in an air atmosphere or a nitrogen atmosphere. The timing of this heat treatment is not limited, and it can be performed at any time after the formation of the oxide semiconductor film. That's fine.

[0112] Next, a silicon oxide film 912 containing OH groups is formed by a CVD method using organic silane gas. The organic silane gas is ethyl silicate (TEOS: chemical formula Si(OC2H5)4). , tetramethylsilane (TMS: chemical formula Si(CH3)4), tetramethylcyclotetra Siloxane (TMCTS), Octamethylcyclotetrasiloxane (OMCTS), Hexamethylcyclotetrasiloxane dimethyldisilazane (HMDS), triethoxysilane (SiH(OC2H5)3), Use silicon-containing compounds such as dimethylaminosilane (SiH(N(CH3)2)3) A silicon nitride film 913 is formed on the silicon oxide film 912 containing OH groups. The silicon oxide film 912 containing H groups and the silicon nitride film 913 act as a passivation film. A silicon nitride film having a function can be configured not to be in direct contact with the oxide semiconductor film. a silicon oxide film containing an OH group and a silicon nitride film are successively formed on an oxide semiconductor film; This leads to the termination of dangling bonds in the oxide semiconductor film by OH groups and the formation of oxide semiconductor films. This prevents the decrease in resistance due to oxygen deficiency in the film, and as a result, The shift in the threshold voltage of the enhancement transistor is reduced. The effect of reducing the leakage current can be maintained. The cross section at this stage is shown in FIG. 13(D). is equivalent to

[0113] The silicon oxide film 912 and the silicon nitride film 913 containing OH groups are provided with a fifth After selectively etching the contact holes using a photomask, A third conductive film is formed using the same material as the electrode. Then, a sixth photomask is used to The third conductive film is selectively etched to electrically connect it to the same layer as the first to third wirings. A connection wiring for this purpose is formed.

[0114] In a light-emitting display device using a light-emitting element, a plurality of thin film transistors are provided in a pixel portion, and a pixel Even in the element part, the gate terminal of one TFT and the source or drain of another transistor It has a contact hole for direct connection to the electrode. The contact holes are formed when forming contact holes in the gate insulating film using the second photomask. The same mask can be used to form the two layers.

[0115] In addition, in LCD displays and electronic paper, the wiring board is used to connect to external terminals such as FPCs. When forming a contact hole that reaches the gate wiring in the terminal portion, a second photomask When forming contact holes in the gate insulating film using a mask, the same mask is used. It is possible.

[0116] The above-described process sequence is an example and is not particularly limited. Although the number of sheets increases, the photomask for etching the second conductive film and the + Layer and oxide semiconductor film Alternatively, etching may be performed using separate photomasks that etch a portion of the film.

[0117] In this embodiment, the contents described in each drawing may be the same as those described in another embodiment. However, they can be freely combined or replaced as appropriate.

[0118] (Embodiment 2) In the above embodiment, a shift register in a drive circuit of a display device is In this embodiment, an example of a shift register using a digital tick circuit is shown. An example of a driver circuit using a dynamic shift register will be described. .

[0119] 14(A) to 14(D), the pulses of the shift register using the dynamic circuit are The configuration of the pulse output circuit will be described. A pulse output circuit 1400 shown in FIG. 14(A) is an example. The inverter circuit 1401 receives a start pulse SP from an input terminal, and the inverter A switch 1402 having one terminal connected to the output terminal of the inverter circuit 1401, and a switch 1402 having one terminal connected to the output terminal of the inverter circuit 1401. The capacitor 1402 is connected to the other terminal of the odd-numbered stage. The switch 1402 of the pulse output circuit is turned on or off by the first clock signal (CLK1). The switches 1402 of the pulse output circuits of the even stages are controlled to be on or off. The on / off state is controlled by the clock signal (CLK2).

[0120] FIG. 14(B) shows the detailed circuit configuration of the pulse output circuit. 1400 includes a TFT 1411, a TFT 1412, a TFT 1413, and a capacitance element 1414. The odd-numbered pulse output circuits are used to supply the first clock signal CLK1. Wiring 1415, the pulse output circuits in the even stages supply the second clock signal CLK2. In the pulse output circuit 1400, the TFT 1411 and The TFT 1412 corresponds to the inverter circuit 1401 shown in FIG. 14(A), and The TFT 1413 is configured as a switch 1402 shown in FIG. The capacitor 1414 corresponds to the capacitor 1403 shown in FIG. The TFT1413, like the TFT1411 and TFT1412, is an enhancement It is preferable to use an enhancement type transistor as a switch. By using a transistor, the off-state current of the transistor can be reduced, resulting in low power consumption. This allows for increased power consumption and simplifies the manufacturing process.

[0121] Here, the timing of the circuit operation shown in Figure 14(A) and (B) is shown in Figure 14(C). In FIG. 14(C), for the sake of explanation, the circuit in FIG. 14(B) is shown. The codes will be explained using the symbols A to E. First, the start pulse SP The inverted signal of the start pulse SP appears at node A. The signal at node A is transferred to node B when the first clock signal CLK1 is at H level, and The signal at node A is reflected at node B. The signal at node B is then reflected at the inverter circuit. The signal at node C is inverted by the second Since the clock signal CLK2 is at the L level and the switch is closed, the current is applied to node D. Next, when the first clock signal CLK1 is at the L level and the second clock signal CLK When 2 becomes H level, the signal at node C moves to node D, and the signal at node C is transferred to node D. The signal at node D is then inverted by the inverter circuit, and appears as a The inverted signal of node D appears at node E. The first clock signal CLK1 and the second clock signal CLK2 appear at node E. By alternately setting the clock signal CLK2 to the H level, the circuits shown in FIGS. 14(A) and 14(B) are realized. The path can be made to function as a shift register.

[0122] Note that, in the example of the circuit configuration of the pulse output circuit described in FIG. 14B, The potential of the output signal may decrease by the threshold voltage. By configuring a pulse output circuit using an inverter circuit that uses the bootstrap method shown in Therefore, it is possible to make the transistor function as a shift register without causing a drop in the potential of the signal.

[0123] A circuit configuration different from that shown in FIG. 14(B) is shown in FIG. 15(A). The pulse output circuit 1500 includes a TFT 1501, a TFT 1502, a TFT 1503, a capacitor, and a The odd-numbered pulse output circuits have a first clock signal CLK1. The even-numbered pulse output circuits are connected to a wiring 1505 for supplying the second clock signal CLK. 2. In the pulse output circuit 1500, The TFT 1501 and the TFT 1502 are connected to the inverter circuit 1401 shown in FIG. The TFT 1503 corresponds to the EEMOS circuit shown in FIG. The capacitor 1504 corresponds to the switch 1402. 03. Note that the TFT1503, like the TFT1501 and TFT1502, It is preferable to use an enhancement type transistor as a switch. By using a ment type transistor, the off-state current of the transistor can be reduced. Therefore, power consumption can be reduced and the manufacturing process can be simplified.

[0124] The pulse output circuit shown in FIG. 15(A) differs from that shown in FIG. 14(B) in that the gate of the TFT 1502 A wiring 1505 is connected to the output terminal to supply the first clock signal CLK1. The pulse output circuit 1500 shown in FIG. 15(A) is a timing diagram shown in FIG. When the first clock signal CLK1 is at a high level, the If the start pulse SP is at H level, both node A and node B are at L level. If the first crosstalk SP is at L level, both the node A and the node B are at H level. When the clock signal CLK1 is at the L level, the potential of the node B can be maintained. That is, the TFT 1502 is turned on or off by the first clock signal CLK1. This allows for control in synchronization with the on / off of the TFT1503. Wiring that supplies high power supply potential when the TFTs that make up the inverter circuit are both in a conductive state This reduces the current that flows between the wiring to which the low power supply potential is supplied, resulting in low power consumption. This will enable us to strengthen our capabilities.

[0125] The shift register having the pulse output circuit shown in this embodiment mode is a source line driver. The circuit can be used for the gate line driver circuit. A desired signal may be obtained by outputting the signal via a logic circuit or the like. .

[0126] In addition, the inverter circuit constituting the dynamic circuit described in this embodiment also As in the first embodiment, on the first oxide semiconductor film and the second oxide semiconductor film of the TFT, By successively forming a silicon oxide film containing OH groups and a silicon nitride film, the oxidation caused by the OH groups can be prevented. Termination of dangling bonds in the oxide semiconductor film and oxygen vacancies in the oxide semiconductor film As a result, the shift in the threshold voltage of the TFT can be prevented. This reduces the off-state current due to the enhancement type transistor. It can be sustained.

[0127] As disclosed in the first embodiment, the first inverter circuit of the pulse output circuit a silicon oxide film containing an OH group and a silicon nitride film over the first oxide semiconductor film and the second oxide semiconductor film; By successively depositing the base film, a silicon nitride film that functions as a passivation film is obtained. The oxide semiconductor film may be in direct contact with the oxide semiconductor film. It is possible to reduce the decrease in resistance caused by nitridation by nitrogen in the silicon nitride film. In addition, by disposing a silicon oxide film containing an OH group between the silicon nitride film and the oxide semiconductor film, This reduces the stress caused by forming the silicon nitride film, and prevents the oxide semiconductor from being damaged by the stress. This can reduce the hydrogenation (or reduction) of the oxide semiconductor that occurs when the oxide semiconductor is subjected to stress. In addition, the TFT using an oxide semiconductor film in the channel formation region is Compared to TFTs that use SiO2 in the channel formation region, this TFT has superior electrical properties such as mobility, and therefore This allows the area occupied by the TFT in the circuit to be reduced without reducing the display area.

[0128] In this embodiment, the contents described in each drawing may be the same as those described in another embodiment. However, they can be freely combined or replaced as appropriate.

[0129] (Embodiment 3) In this embodiment mode, a manufacturing process of a display device including a driver circuit will be described with reference to FIGS. and explain.

[0130] In FIG. 16(A), a light-transmitting substrate 1600 is made of barium borosilicate glass or aluminum. A glass substrate such as lumino-borosilicate glass can be used.

[0131] Next, a conductive layer is formed on the entire surface of the substrate 1600, and then a first photolithography process is performed. Then, a resist mask is formed and unnecessary parts are removed by etching to form wiring and electrodes ( Gate wiring including a gate electrode layer 1601 of the thin film transistor portion, capacitance wiring 16 of the capacitance portion 08, and the first terminal 1621 of the terminal portion. Etching is performed to form a tapered shape at the end of 1601. Cross section at this stage This is shown in Figure 16(A). The top view at this stage corresponds to Figure 18.

[0132] The gate wiring including the gate electrode layer 1601, the capacitance wiring 1608, and the first terminal 162 of the terminal portion It is desirable that 1 be made of a low-resistance conductive material such as aluminum (Al) or copper (Cu). Aluminum alone has problems such as poor heat resistance and susceptibility to corrosion, so a heat-resistant conductive material is required. The heat-resistant conductive material is titanium (Ti), tantalum, etc. (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd ), scandium (Sc), or an alloy containing the above elements; The film is formed from an alloy film of a combination of the above elements, or a nitride film containing the above elements as components. .

[0133] Next, a gate insulating layer 1602 is formed over the entire surface of the gate electrode layer 1601. The layer 1602 is formed by sputtering or the like to a thickness of 50 to 250 nm.

[0134] For example, a silicon oxide film having a thickness of 100 nm is formed as the gate insulating layer 1602 by sputtering. Of course, the gate insulating layer 1602 is not limited to such a silicon oxide film. Other insulating films such as silicon oxynitride film, silicon nitride film, aluminum oxide film, and tantalum oxide film are also used. Films may be used and may be formed as single layer or laminate structures made of these materials.

[0135] Before the oxide semiconductor film is formed, a reverse process in which argon gas is introduced to generate plasma is performed. It is preferable to perform sputtering to remove dust adhering to the surface of the gate insulating layer 1602. It is also possible to use nitrogen, helium, etc. instead of argon. It may be carried out in an atmosphere containing oxygen, hydrogen, N2O, etc. It may be carried out in an atmosphere containing I2, CF4, etc.

[0136] Next, a first oxide semiconductor film (a first In After the plasma treatment, the first The formation of the In-Ga-Zn-O based non-single crystal film is performed by forming the gate insulating layer 1602 and the first It is useful in that it prevents dust and moisture from adhering to the interface of the oxide semiconductor film. The oxide semiconductor target containing In, Ga, and Zn (In2O3:Ga2O3: ZnO = 1:1:1), the distance between the substrate and the target was 170 mm, and the pressure was 0. The film is formed under 4 Pa, a direct current (DC) power supply of 0.5 kW, and an argon or oxygen atmosphere. Using a direct current (DC) power supply is preferable because it reduces dust and makes the film thickness distribution uniform. The thickness of the first In—Ga—Zn—O based non-single crystal film is set to 5 nm to 200 nm. In this embodiment, the thickness of the first In—Ga—Zn—O based non-single-crystal film is 100 nm.

[0137] Next, a second oxide semiconductor film (a second In-G In this example, a Zn-O based non-single crystal film (In2O3:Ga2O) is formed by sputtering. 3: A target of ZnO = 1:1:1 was used, and the film formation conditions were a pressure of 0.4 Pa, The power was set to 500 W, the film formation temperature was set to room temperature, and argon gas was introduced at a flow rate of 40 sccm. The film was formed by sputtering. The thickness was In2O3:Ga2O3:ZnO=1:1:1. Although the target was intentionally used, crystals of 1 nm to 10 nm in size were formed immediately after film formation. In-Ga-Zn-O based non-single crystal film containing crystal grains may be formed. The composition ratio of the film, the deposition pressure (0.1 Pa to 2.0 Pa), the power (250 W to 3000 W: 8 in) The thickness (inch φ), temperature (room temperature to 100°C), and reactive sputtering film formation conditions should be adjusted appropriately. The presence or absence of crystal grains, the density of crystal grains, and the diameter size are adjusted in the range of 1 nm to 10 nm. The thickness of the second In-Ga-Zn-O based non-single crystal film is 5 nm to 20 nm. Of course, if crystal grains are contained in the film, the size of the contained crystal grains may exceed the film thickness. In this embodiment, the thickness of the second In-Ga-Zn-O based non-single-crystal film is 5 Let nm.

[0138] The first In-Ga-Zn-O based non-single-crystal film is For example, the film formation conditions for the second In-Ga-Zn-O based non-single crystal film are different from those for the first In-Ga-Zn-O based non-single crystal film. The ratio of the oxygen gas flow rate to the argon gas flow rate in the first In-Ga-Zn-O system non- The single crystal film is formed under the conditions where the ratio of the oxygen gas flow rate to the argon gas flow rate is large. Specifically, the deposition conditions for the second In-Ga-Zn-O based non-single crystal film are: , or helium) atmosphere (or oxygen gas 10% or less, argon gas 90% or more) The first In—Ga—Zn—O based non-single-crystal film is formed under an oxygen atmosphere.

[0139] The second In-Ga-Zn-O non-single crystal film was deposited in the chamber where the reverse sputtering was performed previously. The reverse sputtering may be performed in the same chamber as the previous reverse sputtering, or in a chamber different from the previous reverse sputtering. It may be carried out in a chamber.

[0140] There are two types of sputtering methods: RF sputtering, which uses a high frequency power supply for the sputtering power source, and DC sputtering. There is also the pulsed DC sputtering method, which applies a pulsed bias. The DC sputtering method is mainly used to deposit insulating films, while the DC sputtering method is mainly used to deposit metal films. It is used for.

[0141] There are also multi-target sputtering devices that can accommodate multiple targets of different materials. The equipment can deposit layers of different materials in the same chamber, or multiple types of materials in the same chamber. It is also possible to simultaneously discharge and deposit the same materials.

[0142] Also, a sputtering apparatus using a magnetron sputtering method equipped with a magnet mechanism inside the chamber and ECR sputtering using plasma generated by microwaves without glow discharge. There are sputtering devices that use this method.

[0143] In addition, in the film formation method using the sputtering method, the target material and the sputtering gas component are mixed during film formation. Reactive sputtering is used to form thin films of these compounds by chemically reacting them with each other. There is also a bias sputtering method in which a voltage is also applied to the substrate.

[0144] Next, a second photolithography step is performed to form a resist mask, and the first In- Etching of the Ga-Zn-O non-single crystal film and the second In-Ga-Zn-O non-single crystal film Here, the unnecessary layer is removed by wet etching using ITO07N (manufactured by Kanto Chemical Co., Ltd.). The oxide semiconductor film 160 is a first In—Ga—Zn—O-based non-single-crystal film. 9. Forming the oxide semiconductor film 1611, which is a second In-Ga-Zn-O based non-single-crystal film The etching here is not limited to wet etching, but may be dry etching. The cross-sectional view at this stage is shown in FIG. 16(B). Corresponds to Figure 19.

[0145] Next, a third photolithography step is performed to form a resist mask and etch the By removing unnecessary parts, wiring made of the same material as the gate electrode layer and contacts that reach the electrode layer can be formed. This contact hole is designed to be directly connected to the conductive film that will be formed later. For example, in the drive circuit section, the gate electrode layer and the source electrode layer or the drain electrode layer The thin film transistors that come into direct contact with the gate wiring of the terminal area are formed. In this case, a contact hole is formed.

[0146] Next, a conductive film made of a metal material is formed over the oxide semiconductor film 1609 and the oxide semiconductor film 1611. The cross section at this stage is shown in Figure 16(C). did.

[0147] The material of the conductive film 1632 is an element selected from Al, Cr, Ta, Ti, Mo, and W, Alternatively, an alloy containing the above elements or an alloy film of a combination of the above elements may be used. In addition, when heat treatment is performed at 200 to 600°C, the heat resistance that can withstand this heat treatment is required. It is preferable to have a conductive film with Al as the only material. Since there are problems, it is formed by combining it with a heat-resistant conductive material. Conductive materials include titanium (Ti), tantalum (Ta), tungsten (W), and molybdenum (Mo). Elements selected from Mo, chromium (Cr), neodymium (Nd), and scandium (Sc) or an alloy film containing the above elements as components, or an alloy film of a combination of the above elements, is formed of a nitride containing the above-mentioned elements as components.

[0148] Here, the conductive film 1632 has a single-layer structure of a titanium film. A two-layer structure may be used, and a titanium film may be laminated on an aluminum film. 632 is a Ti film and an aluminum film containing Nd (Al-Nd) on top of the Ti film. The conductive film 1632 may have a three-layer structure in which a Ti film is formed on top of the conductive film 1632. A single layer structure of an aluminum film containing silicon may also be used.

[0149] Next, a fourth photolithography step is performed to form a resist mask 1631, and Unnecessary portions are removed by etching to form the source electrode layer or the drain electrode layer 1605a, 160 5b, n serving as a source region or a drain region + Layers 1604a, 1604b, and A connection electrode 1620 is formed. The etching method used here is wet etching or Dry etching is used. For example, the conductive film 1632 is an aluminum film or When using an aluminum alloy film, wet etching is performed using a solution that is a mixture of phosphoric acid, acetic acid, and nitric acid. Here, ammonia hydrogen peroxide (hydrogen peroxide: ammonia: water = 5:2) :2) by wet etching the conductive film 1632 of the Ti film, The source and drain electrode layers 1605a and 1605b are formed by etching the oxide semiconductor film 1611. Switching + In this etching step, layers 1604a and 1604b are formed. The exposed region of the oxide semiconductor film 1609 is also partly etched to form the semiconductor layer 1603. That's n + The channel forming region of the semiconductor layer 1603 between the layers 1604a and 1604b has a thickness of In FIG. 17A, the source or drain electrode layer 1605a , 1605b, n + The layers 1604a and 1604b are etched using ammonia hydrogen peroxide. Since the source electrode layer or the drain electrode layer 160 is used as a blocking agent, the process is performed at once. 5a, 1605b and n + The edges of layers 1604a and 1604b meet, forming a continuous structure. In addition, because wet etching is used, etching is performed isotropically, and the soak The edges of the source and drain electrode layers 1605a and 1605b are covered with a resist mask 1631. Through the above steps, a thin film transistor is formed using the semiconductor layer 1603 as a channel forming region. The cross section at this stage is shown in Figure 17(A). The top view at the floor level corresponds to Figure 20.

[0150] Next, it is preferable to carry out a heat treatment at 200°C to 600°C, typically 300°C to 500°C. Here, the material is placed in a furnace and heat treated at 350°C for 1 hour in a nitrogen atmosphere. This heat treatment causes rearrangement at the atomic level in the In-Ga-Zn-O non-single crystal film. This releases the strain that inhibits carrier movement, so the heat treatment (including optical annealing) The timing of the heat treatment is important. There are no particular limitations as long as it is after the formation of the single crystal film, and it may be performed, for example, after the formation of the pixel electrode.

[0151] Furthermore, oxygen radical treatment was performed on the exposed channel formation region of the semiconductor layer 1603. The thin film transistor may be made normally off by oxygen radical treatment. In addition, by performing radical treatment, the semiconductor layer 1603 can be etched. The radical treatment can repair the damage caused by O2, N2O, preferably oxygen. It is preferable to carry out the process in an atmosphere containing N2, He, or Ar. The radical treatment may be carried out in an atmosphere containing 4. The radical treatment is preferably carried out without bias. Desirable.

[0152] In the fourth photolithography step, the source electrode layer or the drain electrode layer The second terminal 1622 made of the same material as 1605a and 1605b remains at the terminal portion. The second terminal 1622 is a source wiring (a source electrode layer or a drain electrode layer 1605a, 1605b). b) and the source wiring.

[0153] In addition, in the terminal portion, the connection electrode 1620 is connected to a contact hole formed in the gate insulating film. It is directly connected to the first terminal 1621 of the terminal section through a cable. The source wiring or drain of the thin film transistor of the driving circuit is formed through the same process as described above. The in-line and the gate electrode are directly connected.

[0154] Also, a resist having regions of multiple thicknesses (typically two types) formed by a multi-tone mask is used. By using a resist mask, the number of resist masks can be reduced, which simplifies the process and reduces Cost reduction is possible.

[0155] Next, the resist mask 1631 is removed, and the thin film transistor 1670 is covered with a thin film containing an OH group. The silicon oxide film 1607a containing OH groups is formed by using an organic silane. The organic silane gas is ethyl silicate (TEOS : Chemical formula Si(OC2H5)4), tetramethylsilane (TMS: Chemical formula Si(CH3) 4), Tetramethylcyclotetrasiloxane (TMCTS), Octamethylcyclotetra Siloxane (OMCTS), hexamethyldisilazane (HMDS), triethoxysilane (SiH(OC2H5)3), trisdimethylaminosilane (SiH(N(CH3)2) 3) and other silicon-containing compounds can be used. The silicon oxide film 1607a containing OH groups and the silicon nitride film 1607b are formed. The silicon nitride film having a function as a passivation film is formed by the film 1607b. In other words, the oxide semiconductor film is not in direct contact with the silicon nitride film. The decrease in resistance due to nitridation caused by the nitrogen in the OH group can be reduced. By disposing a silicon oxide film containing The stress caused by the formation of the oxide semiconductor is alleviated, and the stress caused by the stress is reduced. As a result, hydrogenation (or reduction) of the oxide semiconductor can be reduced. The shift in the threshold voltage of the TFT is reduced, and the transistor is an enhancement type. Therefore, the effect of reducing the off-state current can be maintained.

[0156] Next, a fifth photolithography step is performed to form a resist mask, and a film containing an OH group is formed. The silicon oxide film 1607a and the silicon nitride film 1607b (hereinafter referred to as the silicon oxide film 1607 containing OH groups) The source electrode 1607 is formed by etching the silicon nitride film 1607a and the silicon nitride film 1607b together, which are also called the protective insulating film. A contact hole 1625 reaching the electrode layer or drain electrode layer 1605b is formed. By etching here, a contact hole 1627 reaching the second terminal 1622, A contact hole 1626 reaching the contact electrode 1620 is also formed. 17(B).

[0157] Next, the resist mask is removed, and then a transparent conductive film is formed. are indium oxide (In2O3) and indium oxide tin oxide alloy (In2O3-SnO 2, abbreviated as ITO) is formed using a sputtering method or a vacuum deposition method. Etching of such materials is done with a hydrochloric acid solution. However, etching of ITO in particular Residues tend to be generated, so indium oxide zinc oxide alloy is used to improve etching processability. Gold (In2O3-ZnO) may also be used.

[0158] Next, a sixth photolithography step is performed to form a resist mask and then to perform etching. The unnecessary portions are removed to form the pixel electrode layer 1610 .

[0159] In this sixth photolithography step, the gate insulating layer 16 in the capacitance section is A silicon oxide film 1607a containing O2 and OH groups and a silicon nitride film 1607b are used as dielectrics. The capacitor wiring 1608 and the pixel electrode layer 1610 form a storage capacitor.

[0160] In the sixth photolithography step, the first terminal and the second terminal are formed by resist. The transparent conductive films 1628 and 1629 formed on the terminals are left behind by covering with a mask. 1628 and 1629 are electrodes or wiring used for connection with the FPC. The transparent conductive film 1628 formed on the connection electrode 1620 directly connected to the gate electrode 621 The second terminal 1622 is a terminal electrode for connection that functions as an input terminal of the wiring. The transparent conductive film 1629 is a terminal electrode for connection that functions as an input terminal of the source wiring. do.

[0161] Next, the resist mask is removed, and the cross-sectional view at this stage is shown in FIG. The top view at this stage corresponds to Figure 21.

[0162] 22(A1) and 22(A2) show the terminal portion where the gate wiring is provided at this stage. 22(A1) shows a top view and a cross-sectional view of C1 in FIG. 22(A2). 22(A1) corresponds to a cross-sectional view taken along line -C2. The formed transparent conductive film 1655 is a terminal electrode for connection that functions as an input terminal. In addition, in FIG. 22(A1), the terminal portion has a first terminal formed of the same material as the gate wiring. The electrode 1651 and the connection electrode 1653 made of the same material as the source wiring are connected to the gate insulating layer 1 652 and is directly connected to the gate insulating layer 1652 through a contact hole formed in the gate insulating layer 1652. The connection electrode 1653 and the transparent conductive film 1655 are in contact with each other to provide electrical continuity. The electrodes are directly connected to each other through contact holes provided in 654 for electrical continuity.

[0163] 22(B1) and 22(B2) are top views of a terminal portion where a source wiring is provided. 22(B1) shows a cross-sectional view of the D1-D2 in FIG. 22(B2). 22(B1) corresponds to a cross section taken along line D2. The transparent conductive film 1655 is a terminal electrode for connection that functions as an input terminal. In FIG. 22(B1), the terminal portion has an electrode 165 formed of the same material as the gate wiring. 6 is a gate insulating layer 165 below a second terminal 1650 electrically connected to the source wiring. The electrode 1656 is not electrically connected to the second terminal 1650. The terminal 1656 is connected to a potential different from that of the second terminal 1650, such as floating, GND, or 0V. By setting the capacitance as a countermeasure against noise or static electricity, The second terminal 1650 is formed by a contact hole provided in the protective insulating film 1654. It is electrically connected to the transparent conductive film 1655 via a wire.

[0164] A plurality of gate wirings, source wirings, and capacitance wirings are provided depending on the pixel density. In addition, in the terminal section, a first terminal has the same potential as the gate wiring, a second terminal has the same potential as the source wiring, and The second terminal, the third terminal with the same potential as the capacitance wiring, and so on are arranged in a row. The number of terminals may be any number and may be determined appropriately by the implementer.

[0165] In this way, six photolithography processes were carried out using six photomasks to create the bottom A pixel having a thin film transistor 1670, which is a gate-type n-channel thin film transistor. A thin film transistor section and a capacitor section having a storage capacitor can be completed. These are arranged in a matrix corresponding to each pixel to form a pixel section, The present invention can be used as one of the substrates for manufacturing a display device of a passive matrix type. For convenience, such a substrate is called an active matrix substrate.

[0166] When manufacturing an active matrix liquid crystal display device, an active matrix substrate a liquid crystal layer is provided between the active matrix substrate and an opposing substrate on which an opposing electrode is provided; The common electrode is electrically connected to the counter electrode provided on the counter substrate. A fourth terminal electrically connected to the common electrode is provided on the active matrix substrate. This fourth terminal is used to set the common electrode to a fixed potential, such as GND or 0V. This is a terminal for connecting the

[0167] Furthermore, the pixel configuration is not limited to that shown in FIG. 21, and an example of a top view different from that shown in FIG. 21 is shown in FIG. In the case of 23, no capacitance wiring is provided, and the pixel electrode is connected to the gate wiring of the adjacent pixel, the protective insulating film, and the gate In this example, a storage capacitor is formed by stacking the capacitor wiring and the capacitor wiring The third terminal connected to the terminal 3 can be omitted. The same reference numerals will be used for the explanation.

[0168] In an active matrix liquid crystal display device, pixel electrodes arranged in a matrix form By driving the display using the When a voltage is applied between the pixel electrode and the counter electrode corresponding to the pixel electrode, The liquid crystal layer disposed between the pixel electrode and the counter electrode is optically modulated, and this optical modulation is applied to the display panel. It is perceived by the observer as a turn.

[0169] When displaying moving images on a liquid crystal display device, the response of the liquid crystal molecules themselves is slow, which can cause afterimages. In order to improve the moving image characteristics of the LCD device, There is a driving technique called black insertion, which displays black every other frame.

[0170] In addition, video characteristics can be improved by increasing the normal vertical synchronization frequency by 1.5 or 2 times or more. There is also a driving technology called double speed driving, in which the speed is increased by 100 ps.

[0171] In addition, in order to improve the video characteristics of the LCD display, multiple LEDs (light emitting diodes) are used as backlights. A surface light source is formed by using a diode) light source or multiple EL light sources, etc., and a surface light source is formed. There is also a driving technology that drives each light source to light intermittently within one frame period. Therefore, three or more types of LEDs may be used, or white-emitting LEDs may be used. Since multiple LEDs can be controlled, the LE can be switched in accordance with the timing of the optical modulation of the liquid crystal layer. This driving technology can also synchronize the timing of the LEDs to be turned off. This is especially useful when displaying images with a large proportion of black areas occupying the entire screen. This can reduce power consumption.

[0172] By combining these driving technologies, the display characteristics such as the video characteristics of the LCD device can be improved. can be improved compared to the past.

[0173] The n-channel transistor forming the pixel of the display device obtained in this embodiment is Similarly to the transistors in the inverter circuits that make up the output line driver circuit or source line driver circuit, In-Ga-Zn-O based non-single crystal film is used in the channel formation region, and it has good dynamic characteristics. The driving techniques described above can be combined. In this way, a silicon oxide film containing OH groups and a silicon nitride film are successively formed on an oxide semiconductor film. By forming a film, dangling bonds in the oxide semiconductor film are terminated by OH groups, and It is possible to prevent a decrease in resistance due to oxygen vacancies in the oxide semiconductor. As a result, the shift in the threshold voltage of the TFT is reduced, and the transistor is an enhancement type. The effect of reducing the off-state current due to the above can be maintained. The TFTs used in the channel formation region are amorphous silicon TFTs. Compared to TF, it has superior electrical properties such as mobility, so it can be used in circuits without sacrificing performance. The area occupied by T can be reduced.

[0174] In addition, when a light-emitting display device is manufactured, one electrode (also called a cathode) of the organic light-emitting element is In order to set the low power supply potential, for example, GND or 0V, the cathode is connected to the terminal. A fifth terminal is provided for setting the voltage level, for example, GND, 0V, etc. When manufacturing a device, a power supply line is provided in addition to a source line and a gate line. Therefore, the terminal section is provided with a sixth terminal that is electrically connected to the power supply line.

[0175] In this embodiment, the contents described in each drawing may be the same as those described in another embodiment. However, they can be freely combined or replaced as appropriate.

[0176] (Fourth embodiment) In this embodiment mode, an example of a light-emitting display device will be described. Here we will demonstrate this using a light-emitting element that uses electroluminescence. The light-emitting element that uses the luminescence is classified into two types depending on whether the luminescent material is an organic compound or an inorganic compound. Generally, the former is called an organic EL element and the latter an inorganic EL element.

[0177] In an organic EL element, electrons and holes are released from a pair of electrodes by applying a voltage to the light-emitting element. are injected into the layers containing the light-emitting organic compounds, causing a current to flow. The recombination of the electrons and holes creates an excited state in the light-emitting organic compound. The excited state is then converted to the ground state, at which point light is emitted. Such a light-emitting element is called a current-excited light-emitting element.

[0178] Inorganic EL elements are divided into dispersion-type inorganic EL elements and thin-film-type inorganic EL elements depending on the element structure. Dispersion-type inorganic EL elements have a light-emitting layer in which particles of a light-emitting material are dispersed in a binder. The emission mechanism is a donor-acceptor interaction that utilizes the donor and acceptor levels. Thin-film inorganic EL devices sandwich the light-emitting layer between dielectric layers. Furthermore, this structure is sandwiched between electrodes, and the light emission mechanism utilizes the inner-shell electron transition of metal ions. In this example, the light-emitting element is an organic EL element. do.

[0179] FIG. 24 is a diagram showing an example of a pixel configuration.

[0180] The structure and operation of applicable pixels will be described. The n-channel TFT uses a Ga-Zn-O non-single crystal film as the channel formation region. Here is an example:

[0181] The pixel 6400 in FIG. 24 includes a TFT 6401, a TFT 6402, and a light emitting element 6403. The TFT 6401 has a gate terminal connected to a gate line 6406 and a first terminal connected to a The first terminal is connected to the source line 6405 and the second terminal is connected to the gate terminal of the TFT 6402 . The TFT 6402 has a first terminal connected to a power supply line 6407 and a second terminal connected to a light emitting element 6403. The second electrode of the light emitting element 6403 is connected to the first electrode (pixel electrode) of the common electrode 64. The common electrode 6408 is electrically connected to a common potential line formed on the same substrate. To be continued.

[0182] A low power supply potential is set to the second electrode (common electrode 6408) of the light emitting element 6403. The low power supply potential is a low power supply potential with respect to the high power supply potential set to the power supply line 6407. Potential < High power supply potential. For example, GND, 0V, etc. are set as low power supply potential. The potential difference between the high power supply potential and the low power supply potential is applied to the light emitting element 6403. Then, in order to make the light emitting element 6403 emit light by passing a current through the light emitting element 6403, a high power supply potential and the low power supply potential is set to be equal to or higher than the forward threshold voltage of the light emitting element 6403. Each potential is set.

[0183] Next, the configuration of the light-emitting element will be described with reference to FIG. 25. FT7001, 7011, and 7021 are the same as the thin film transistors described in the above embodiment modes. It is possible to fabricate a highly reliable thin film containing an In-Ga-Zn-O system non-single crystal film as a semiconductor layer. It is a transistor.

[0184] The light emitting element only needs to have at least one of the anode and cathode transparent in order to extract light. Then, a thin film transistor and a light emitting element are formed on the substrate, and light is emitted from the surface opposite to the substrate side. The top surface emission takes out the light emitted from the surface on the substrate side, the bottom surface emission takes out the light emitted from the surface on the substrate side, There are light emitting devices with a double-sided emission structure that emit light from the opposite side of the light emitting side. The pixel configuration can be applied to any light-emitting element of any emission structure.

[0185] A light emitting element with a top emission structure will be described with reference to FIG.

[0186] In FIG. 25(A), a TFT 7001 is an n-type, and light emitted from a light emitting element 7002 is incident on an anode 7003. The cross-sectional view of the pixel when light is emitted to the 005 side (through the anode 7005) is shown in FIG. In FIG. 5(A), the cathode 7003 of the light emitting element 7002 and the TFT 7001 are electrically connected. A light-emitting layer 7004 and an anode 7005 are stacked in this order on the cathode 7003. 03: Various conductive materials with low work function and light reflection can be used. For example, Ca, Al, CaF, MgAg, AlLi, etc. are preferable. The light-emitting layer 7004 may be composed of a single layer or a plurality of layers stacked together. When it is composed of multiple layers, the electron injection layer is formed on the cathode 7003. The electron transport layer, the light emitting layer, the hole transport layer, and the hole injection layer are laminated in this order. It is not necessary to provide all of the anodes. The anode 7005 is made of a conductive material that transmits light. For example, indium oxide containing tungsten oxide, indium oxide containing tungsten oxide Indium zinc oxide, indium oxide with titanium oxide, indium tin oxide with titanium oxide oxide, indium tin oxide (hereinafter referred to as ITO), indium zinc oxide, oxidized silicon dioxide, A light-transmitting conductive film such as indium tin oxide to which indium is added may also be used.

[0187] The region where the light-emitting layer 7004 is sandwiched between the cathode 7003 and the anode 7005 is the light-emitting element 7002. In the case of the pixel shown in FIG. 25(A), the light emitted from the light emitting element 7002 is The light is emitted toward the anode 7005 as shown by the mark.

[0188] Next, a light-emitting element with a bottom emission structure will be described with reference to FIG. The light emitted from the light emitting element 7012 is emitted to the cathode 7013 side (cathode 701 25(B) shows a cross-sectional view of a pixel in the case where the TFT 7011 and the The cathode 701 of the light-emitting element 7012 is formed on the electrically connected conductive film 7017 having light-transmitting properties. 3 is formed, and a light-emitting layer 7014 and an anode 7015 are laminated in this order on the cathode 7013. In addition, when the anode 7015 has a light-transmitting property, a light-reflecting or A shielding film 7016 for shielding may be formed. The cathode 7013 is As in the case of (1), various conductive materials with small work functions can be used. However, the film thickness is set to a level that allows light to pass through (preferably, about 5 nm to 30 nm). For example, an aluminum film having a thickness of 20 nm can be used as the cathode 7013. The light-emitting layer 7014 may be composed of a single layer or multiple layers, as in FIG. The anode 7015 is a light-transmitting layer. Although it is not necessary to form the insulating film 111 using a conductive material having light-transmitting properties, it may be formed using a conductive material having light-transmitting properties as in FIG. The shielding film 7016 can be made of, for example, a metal that reflects light. However, the material is not limited to a metal film, and for example, a resin to which a black pigment is added can also be used.

[0189] The region where the light-emitting layer 7014 is sandwiched between the cathode 7013 and the anode 7015 is the light-emitting element 7012. In the case of the pixel shown in FIG. 25(B), the light emitted from the light emitting element 7012 is As shown by the mark, the light is emitted toward the cathode 7013 side.

[0190] Next, a light emitting element with a dual emission structure will be described with reference to FIG. In this example, a light-emitting element is formed on a light-transmitting conductive film 7027 electrically connected to a TFT 7021. A cathode 7023 of the electrode 7022 is formed as a film, and a light-emitting layer 7024 and an anode 7 25(A), the cathode 7023 has a work function However, the thickness of the material must be such that it can absorb light. For example, an aluminum film having a thickness of 20 nm is used as the cathode 7023. The light-emitting layer 7024 can be a single layer, as in FIG. The anode may be formed of a single layer or a plurality of layers stacked together. 7025 is formed using a conductive material that transmits light, similar to FIG. 25(A). It can be achieved.

[0191] The overlapping portion of the cathode 7023, the light-emitting layer 7024, and the anode 7025 is the light-emitting element 70. In the case of the pixel shown in FIG. 25(C), the light emitted from the light emitting element 7022 is is emitted to both the anode 7025 side and the cathode 7023 side as shown by the arrows.

[0192] Although organic EL elements have been described as light-emitting elements here, inorganic EL elements can also be used as light-emitting elements. It is also possible to provide an L element.

[0193] Next, the appearance and cross section of a light-emitting display panel (also called a light-emitting panel) which corresponds to one form of a display device will be described. The surface will be explained using Figures 26(A) and 26(B). Figure 26(A) shows the first substrate The thin film transistor and the light emitting element formed on the first substrate are sandwiched between the first substrate and the second substrate by a sealing material. 26(B) is a cross-section taken along line HI in FIG. 26(A). Corresponding to the figure.

[0194] A pixel portion 4502, a source line driver circuit 4503a, and a A sealant 45 is applied to surround the gate driver circuits 4503a and 4504b. 05 is provided. Also, a pixel portion 4502, source line driver circuits 4503a and 4503b A second substrate 4506 is provided on the gate line driver circuits 4504a and 4504b. Therefore, the pixel portion 4502, the source line driver circuits 4503a and 4503b, and the gate line The driver circuits 4504a and 4504b are formed on the first substrate 4501, the sealant 4505, and the second substrate 4502. The plate 4506 seals the filler 4507 together. Highly airtight and low outgassing protective film (lamination film, UV hardening) It is preferable to package (enclose) the product in a protective film (e.g., a synthetic resin film) or a cover material.

[0195] A pixel portion 4502, a source line driver circuit 4503a, 4503b and the gate line driver circuits 4504a and 4504b are each provided with a plurality of thin film transistors. In FIG. 26B, a thin film transistor 4510 included in a pixel portion 4502 , and a thin film transistor 4509 included in a source line driver circuit 4503a are illustrated.

[0196] The thin film transistors 4509 and 4510 are made of In-Ga-Zn-O based non-single crystal films as semiconductor layers. The thin film transistor having the structure described in the above embodiment can be applied.

[0197] Further, 4511 corresponds to a light-emitting element, and a first electrode which is a pixel electrode of the light-emitting element 4511 The layer 4517 is electrically connected to the source electrode layer or the drain electrode layer of the thin film transistor 4510. The light-emitting element 4511 is configured by a first electrode layer 4517, an electroluminescent layer The second electrode layer 4512 and the second electrode layer 4513 are stacked in a stacked structure. The direction of the light emitting element 4511 is adjusted according to the direction of the light extracted from the light emitting element 4511. The configuration can be changed as appropriate.

[0198] The partition wall 4520 is formed using an organic resin film, an inorganic insulating film, or organic polysiloxane. In particular, a photosensitive material is used to form an opening on the first electrode layer 4517, and the sidewall of the opening It is preferable to form the inclined surface so that the inclined surface has a continuous curvature.

[0199] The electroluminescent layer 4512 may be composed of a single layer or a plurality of layers stacked. It doesn't matter whether it's done or not.

[0200] The second electrode layer is formed to prevent oxygen, hydrogen, moisture, carbon dioxide, and the like from entering the light-emitting element 4511. A protective film may be formed on the partition wall 4513 and the partition wall 4520. The protective film may be a silicon nitride film, A silicon nitride oxide film, a DLC film, or the like can be formed.

[0201] In addition, source line driver circuits 4503a and 4503b, gate line driver circuits 4504a and 450 4b or the pixel portion 4502, various signals and potentials are applied to the FPC 4518a, 45 It is supplied by 18b.

[0202] In this embodiment, the connection terminal electrode 4515 is connected to the first electrode layer 4 The terminal electrode 4516 is formed from the same conductive film as the thin film transistors 4509 and 517. The source electrode layer and the drain electrode layer 510 are formed from the same conductive film.

[0203] The connection terminal electrode 4515 is connected to the terminal of the FPC 4518a via the anisotropic conductive film 4519. are electrically connected to each other.

[0204] The second substrate 4506 located in the direction of light extraction from the light emitting element 4511 must be light-transmitting. In this case, glass plates, plastic plates, polyester films or A light-transmitting material such as an acrylic film is used.

[0205] In addition to inert gases such as nitrogen and argon, filler 4507 can also be used as UV-curable resin. It can be made of oil or thermosetting resin, and PVC (polyvinyl chloride), acrylic, Polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral) or EV In this embodiment, nitrogen is used as the filler. Use the element.

[0206] If necessary, a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate) may be provided on the light-emitting surface of the light-emitting element. Optical films such as retardation plates (λ / 4 plates, λ / 2 plates) and color filters may be provided as appropriate. In addition, an anti-reflection film may be provided on the polarizing plate or the circular polarizing plate. Anti-glare treatment can be applied to diffuse reflected light and reduce glare.

[0207] Source line driver circuits 4503a and 4503b, and gate line driver circuits 4504a and 4504 b is formed by a single crystal semiconductor film or a polycrystalline semiconductor film on a separately prepared substrate. In addition, only the source line driver circuit, or a part of the source line driver circuit, or the gate driver circuit may be mounted. Only the port line driving circuit or only a part of the circuit may be separately formed and mounted. It is not limited to 26 configurations.

[0208] Through the above steps, a light-emitting display device (display panel) can be manufactured. The n-channel transistors constituting the pixels of the display device obtained in this form are gate line drivers. In- A Ga-Zn-O based non-single crystal film is used in the channel formation region, and it has good dynamic characteristics. As described in the above embodiment, a silicon oxide film containing an OH group and a By successively forming a silicon nitride film and an oxide semiconductor film, dangling in the oxide semiconductor film due to OH groups can be prevented. Termination of bonding and prevention of low resistance due to oxygen vacancies in the oxide semiconductor film As a result, the shift in the threshold voltage of the TFT can be reduced, and the enhancement The effect of reducing the off-state current due to the use of a gate-type transistor can be maintained. In addition, TFTs that use an oxide semiconductor film in the channel formation region have amorphous silicon as the channel. Compared to the TFT used in the panel formation area, it has superior electrical properties such as mobility, so performance is reduced. This allows the area occupied by the TFT in the circuit to be reduced without increasing the number of TFTs.

[0209] In this embodiment, the contents described in each drawing may be the same as those described in another embodiment. However, they can be freely combined or replaced as appropriate.

[0210] (Embodiment 5) In this embodiment, an example of an electronic paper display device to which the configuration of the above embodiment can be applied is used. Shows.

[0211] Figure 29 shows an active matrix type electronic paper as an example of a display device. The thin film transistor 81 can be manufactured in the same manner as in the thin film transistor shown in the embodiment 4. The thin film transistor is highly reliable and contains an nO-based non-single crystal film as a semiconductor layer. On the oxide semiconductor film of the TFT that constitutes the driver circuit, a silicon oxide film 583 containing an OH group and a nitrogen By successively forming the silicon dioxide film 584, the dangling in the oxide semiconductor film due to the OH group can be prevented. Termination of ring bonds and prevention of low resistance due to oxygen vacancies in the oxide semiconductor film We are trying to stop this.

[0212] The electronic paper in Figure 29 is an example of a display device that uses the twisting ball display method. The spherical display method uses black and white spherical particles on the electrode layer of the display element. A first electrode layer and a second electrode layer are disposed between the first electrode layer and the second electrode layer, and a potential is applied to the first electrode layer and the second electrode layer. This is a method of displaying by creating a difference and controlling the orientation of spherical particles.

[0213] The TFT581 is a thin film transistor with a bottom gate structure, and the source electrode layer or the drain electrode layer The electrode layer is in contact with the first electrode layer 587 through an opening formed in the insulating layer 585, and the TFT 5 81 and the first electrode layer 587 are electrically connected. Between the layers 588 are black regions 590a and white regions 590b, and between the black regions 590a and white regions 590b. a sphere having a region 590b and a cavity 594 surrounding the region 590b that is filled with a liquid; The spherical particles 589 are provided, and the periphery of the spherical particles 589 is filled with a filler 595 such as a resin. In this embodiment, the first electrode layer 587 corresponds to the pixel electrode. The second electrode layer 588 corresponds to a common electrode. The second electrode layer is electrically connected to a common potential line provided on the same substrate 580 as the first electrode layer. Above 588, a substrate 596 is provided.

[0214] Also, instead of the twist ball, an electrophoretic element can be used. and a diameter of 10 μm to 20 μm that contains positively charged white particles and negatively charged black particles. Microcapsules of about 0 μm in size are used. When an electric field is applied by the first and second electrode layers, the microcapsules turn white. White particles and black particles move in opposite directions, allowing the display to be white or black. The display element that applies this principle is an electrophoretic display element, which is generally called electronic paper. Electrophoretic display elements have a higher reflectivity than liquid crystal display elements, so auxiliary lights are not required. It also consumes little power and the display can be seen even in dimly lit places. Even if power is not supplied to the display unit, the image that has been displayed can be retained. Therefore, the semiconductor device with a display function (simply a display device, or a device equipped with a display device) is The ability to preserve the displayed image even when the device (also known as a semiconductor device) is moved away This becomes possible.

[0215] Through the above steps, highly reliable electronic paper can be produced.

[0216] In this embodiment, the contents described in each drawing may be the same as those described in another embodiment. However, they can be freely combined or replaced as appropriate.

[0217] (Sixth embodiment) In this embodiment, an example of an electronic device including the display device described in the above embodiment is We will explain about this.

[0218] FIG. 27(A) shows a portable gaming machine, which includes a housing 9630, a display unit 9631, and a speaker 9633. , operation keys 9635, connection terminals 9636, recording medium reading unit 9672, etc. The portable gaming machine shown in FIG. 27(A) can be used to play a program or data recorded on a recording medium. It also has the function of reading out data and displaying it on the display, and of sharing information with other portable gaming machines via wireless communication. The portable gaming machine shown in FIG. 27(A) has the following functions. The functions are not limited to these, and various functions can be provided.

[0219] FIG. 27B shows a digital camera, which includes a housing 9630, a display portion 9631, and a speaker 963 3, operation keys 9635, connection terminal 9636, shutter button 9676, image receiving unit 9677 , etc. The digital camera with a television receiving function shown in FIG. 27(B) can have: Functions for taking still images, shooting videos, and automatically or manually correcting captured images Function, function to acquire various information from the antenna, image taken or acquired from the antenna It has the function of saving the captured information, displaying the captured image or the information obtained from the antenna on the display. It is possible to have a function to receive television images, etc. The functions of the mobile camera are not limited to these, and the mobile camera may have a variety of functions.

[0220] FIG. 27C shows a television receiver, which includes a housing 9630, a display portion 9631, and a speaker 9633. , operation keys 9635, connection terminals 9636, etc. A television receiver has the functions of processing television radio waves and converting them into image signals, It has functions such as converting signals suitable for display and converting the frame frequency of image signals. The functions of the television receiver shown in FIG. 27(C) are not limited to these. It can have a variety of functions.

[0221] FIG. 28A shows a computer, which includes a housing 9630, a display portion 9631, and a speaker 9633. , operation keys 9635, connection terminals 9636, pointing devices 9681, external connection points The computer shown in FIG. 28(A) can store various information. (still images, videos, text images, etc.) on the display, Functions for controlling processing by means of wireless or wired communication, the ability to connect to various computer networks using the communication function, It can have a function to transmit or receive data, etc. The functions possessed by the computer are not limited to these, and the computer may have a variety of functions.

[0222] Next, FIG. 28(B) shows a mobile phone, which includes a housing 9630, a display portion 9631, and a speaker 963 3, operation keys 9635, microphone 9638, etc. The mobile phone shown in Figure 1 displays various information (still images, videos, text images, etc.) on the display. Functions for displaying calendars, dates, or times on the display, and functions for displaying information on the display Functions for operating or editing software, and for controlling processing using various software (programs) The functions of the mobile phone shown in Figure 28(B) are as follows: The function is not limited to the above, and may have various functions.

[0223] The electronic device described in this embodiment has the display device according to the above embodiment on a display unit for displaying information. That is, the display device includes the gate line driving circuit or the source line The transistors in the inverter circuit that constitutes the drive circuit are In-Ga-Zn-O based non-single-layer A crystalline film is used in the channel forming region, and the device has good dynamic characteristics. As will be described, a silicon oxide film containing OH groups and a silicon nitride film are successively formed on an oxide semiconductor film. By forming the oxide semiconductor film, dangling bonds in the oxide semiconductor film are terminated by OH groups. Furthermore, a decrease in resistance due to oxygen vacancies in the oxide semiconductor film can be prevented. As a result, the shift in the threshold voltage of the TFT is reduced, and the enhancement type transistor The effect of reducing the off-state current due to the presence of the oxide semiconductor film can be maintained. The TFT used amorphous silicon for the channel formation region. Compared to TFTs, it has superior electrical properties such as mobility, allowing for efficient use in circuits without compromising performance. This allows the area occupied by the TFT to be reduced.

[0224] In this embodiment, the contents described in each drawing may be the same as those described in another embodiment. However, they can be freely combined or replaced as appropriate. [Explanation of symbols]

[0225] 100 boards 101 Source line driver circuit 102 Gate line driving circuit 103 Pixel section 104 Flexible Printed Circuit Board 105 circuits 110 dotted frame 170 Thin-Film Transistor 201 Clock signal level shifter 202 Start pulse level shifter 203 Pulse output circuit 204 NAND circuit 205 buffers 206 Sampling Switch 251 Shift Register 300 Pulse output circuit 301 Switch 302 Inverter circuit 303 Inverter Circuit 304 Switch 305 Inverter Circuit 331 Pulse output circuit 332 Pulse output circuit 350 dotted line 351 TFT 352 TFT 353 TFT 354 TFT 355 TFT 356 TFT 357 TFT 358 TFT 359 Wiring 360 Wiring 581 TFT 585 Insulation Layer 587 Electrode layer 588 Electrode layer 589 Spherical particles 594 Cavity 595 Filling material 601 TFT 602 TFT 603 TFT 605 capacity 606 TFT 608 TFT 609 TFT 610 capacity 611 TFT 612 TFT 613 TFT 615 capacity 702 TFT 704 TFT 705 TFT 707 capacity 731 TFT 751 Clock signal level shifter 752 Start pulse level shifter 753 Pulse Output Circuit 754 NAND circuit 755 buffers 781 Shift Register 801 Power line 802 Power line 803 control signal line 804 control signal line 805 control signal line 806 Oxide semiconductor film 807 Wiring layer 808 wiring layer 809 Contact hole 900 boards 901 Gate electrode 902 Gate electrode 903 Gate insulating layer 904 Contact Hole 905 Oxide semiconductor film 906 n+ layer 907 Oxide semiconductor film 908 n+ layer 909 Wiring 910 Wiring 911 Wiring 912 Silicon oxide film 913 Silicon nitride film 1001 Channel protection layer 1002 Channel protection layer 1101 Silicon oxide film 1102 Silicon nitride film 1400 Pulse output circuit 1401 Inverter circuit 1402 Switch 1403 Capacitor element 1411 TFT 1412 TFT 1413 TFT 1414 Capacitor element 1415 Wiring 1416 Wiring 1500 Pulse Output Circuit 1501 TFT 1502 TFT 1503 TFT 1504 Capacitive element 1505 Wiring 1506 Wiring 1600 board 1601 gate electrode layer 1602 Gate insulating layer 1603 Semiconductor layer 1608 Capacitance wiring 1609 Oxide semiconductor film 1610 Pixel electrode layer 1611 Oxide semiconductor film 1620 Connecting electrode 1621 terminal 1622 terminal 1625 Contact Hole 1626 Contact Hole 1627 Contact Hole 1628 Transparent conductive film 1629 Transparent conductive film 1631 Resist mask 1632 Conductive film 1650 terminal 1651 terminal 1652 Gate insulating layer 1653 Connecting electrode 1654 Protective insulating film 1655 Transparent conductive film 1656 Electrode 1670 Thin-Film Transistor 4501 Circuit Board 4502 Pixel section 4505 Sealing material 4506 board 4507 Filling material 4509 Thin-film transistor 4510 Thin-film transistor 4511 Light-emitting element 4512 Electroluminescent layer 4513 Electrode layer 4515 Connection terminal electrode 4516 Terminal electrode 4517 Electrode layer 4519 Anisotropic conductive film 4520 Bulkhead 6400 pixels 6401 TFT 6402 TFT 6403 Light-emitting elements 6405 source line 6406 Gate line 6407 Power line 6408 Common electrode 7001 TFT 7002 Light-emitting element 7003 Cathode 7004 Light-emitting layer 7005 Anode 7011 TFT 7012 Light-emitting element 7013 Cathode 7014 Light-emitting layer 7015 Anode 7016 Shielding membrane 7017 Conductive film 7021 TFT 7022 Light-emitting element 7023 Cathode 7024 Light-emitting layer 7025 Anode 7027 Conductive film 9630 chassis 9631 Display section 9633 Speaker 9635 Operation Key 9636 Connection terminal 9638 Microphone 9672 Recording medium reading unit 9676 Shutter button 9677 Image receiving unit 9680 External connection port 9681 Pointing Device 4503a Source line driver circuit 4504a Gate line driver circuit 4518a FPC

Claims

1. a first conductive film; a second conductive film; a third conductive film; an insulating film above the first to third conductive films; a first oxide semiconductor film above the insulating film; a second oxide semiconductor film above the insulating film; a third oxide semiconductor film above the insulating film; a fourth oxide semiconductor film above the insulating film; a fourth conductive film above the insulating film; a fifth conductive film above the insulating film; a sixth conductive film above the insulating film; a seventh conductive film above the insulating film, the first conductive film functions as a gate electrode of a first transistor; the second conductive film functions as a gate electrode of a second transistor and also functions as a gate electrode of a third transistor; the third conductive film functions as a gate electrode of a fourth transistor; the first oxide semiconductor film has a channel formation region of the first transistor, the second oxide semiconductor film has a channel formation region of the second transistor, the third oxide semiconductor film has a channel formation region of the third transistor, the fourth oxide semiconductor film has a channel formation region of the fourth transistor, the fourth conductive film has a region in contact with an upper surface of the first oxide semiconductor film, the fifth conductive film has a region in contact with an upper surface of the first oxide semiconductor film and a region in contact with an upper surface of the second oxide semiconductor film; the sixth conductive film has a region in contact with an upper surface of the third oxide semiconductor film and a region in contact with an upper surface of the fourth oxide semiconductor film; the seventh conductive film has a region in contact with an upper surface of the fourth oxide semiconductor film, the fourth conductive film functions as one of a source electrode and a drain electrode of the first transistor, the fifth conductive film functions as the other of the source electrode and the drain electrode of the first transistor, and also functions as one of the source electrode and the drain electrode of the second transistor; the sixth conductive film functions as one of a source electrode or a drain electrode of the third transistor and also functions as one of a source electrode or a drain electrode of the fourth transistor; the seventh conductive film functions as the other of the source electrode and the drain electrode of the fourth transistor, the other of the source electrode and the drain electrode of the second transistor has a region in contact with an upper surface of the second oxide semiconductor film; the other of the source electrode and the drain electrode of the third transistor has a region in contact with an upper surface of the third oxide semiconductor film; the insulating film has a first opening and a second opening; the fourth conductive film has a region provided in the first opening of the insulating film, the fourth conductive film has a region in contact with an upper surface of the first conductive film, the seventh conductive film has a region provided in the second opening of the insulating film, the seventh conductive film has a region in contact with an upper surface of the third conductive film.

2. a first conductive film; a second conductive film; a third conductive film; an insulating film above the first to third conductive films; a first oxide semiconductor film above the insulating film; a second oxide semiconductor film above the insulating film; a third oxide semiconductor film above the insulating film; a fourth oxide semiconductor film above the insulating film; a fourth conductive film above the insulating film; a fifth conductive film above the insulating film; a sixth conductive film above the insulating film; a seventh conductive film above the insulating film, the first conductive film functions as a gate electrode of a first transistor; the second conductive film functions as a gate electrode of a second transistor and also functions as a gate electrode of a third transistor; the third conductive film functions as a gate electrode of a fourth transistor; the first oxide semiconductor film has a channel formation region of the first transistor, the second oxide semiconductor film has a channel formation region of the second transistor, the third oxide semiconductor film has a channel formation region of the third transistor, the fourth oxide semiconductor film has a channel formation region of the fourth transistor, the fourth conductive film has a region in contact with an upper surface of the first oxide semiconductor film, the fifth conductive film has a region in contact with an upper surface of the first oxide semiconductor film and a region in contact with an upper surface of the second oxide semiconductor film; the sixth conductive film has a region in contact with an upper surface of the third oxide semiconductor film and a region in contact with an upper surface of the fourth oxide semiconductor film; the seventh conductive film has a region in contact with an upper surface of the fourth oxide semiconductor film, the fourth conductive film functions as one of a source electrode and a drain electrode of the first transistor, the fifth conductive film functions as the other of the source electrode and the drain electrode of the first transistor, and also functions as one of the source electrode and the drain electrode of the second transistor; the sixth conductive film functions as one of a source electrode or a drain electrode of the third transistor and also functions as one of a source electrode or a drain electrode of the fourth transistor; the seventh conductive film functions as the other of the source electrode and the drain electrode of the fourth transistor, the other of the source electrode and the drain electrode of the second transistor has a region in contact with an upper surface of the second oxide semiconductor film; the other of the source electrode and the drain electrode of the third transistor has a region in contact with an upper surface of the third oxide semiconductor film; the insulating film has a first opening and a second opening; the fourth conductive film has a region provided in the first opening of the insulating film and a region in contact with an upper surface of the first conductive film, the seventh conductive film has a region provided in the second opening of the insulating film and a region in contact with an upper surface of the third conductive film, a silicon oxide film and a silicon nitride film in contact with an upper surface of the silicon oxide film; the silicon oxide film has a region in contact with an upper surface of the first oxide semiconductor film, a region in contact with an upper surface of the second oxide semiconductor film, a region in contact with an upper surface of the third oxide semiconductor film, and a region in contact with an upper surface of the fourth oxide semiconductor film.

3. In claim 1 or 2, the first oxide semiconductor film contains indium, gallium, and zinc; the second oxide semiconductor film contains indium, gallium, and zinc, the third oxide semiconductor film contains indium, gallium, and zinc, the fourth oxide semiconductor film contains indium, gallium, and zinc.

Images