Wireless power supply system and control method of inverter executed on power supply side of wireless power supply system

Abstract

To provide a technique capable of suppressing the generation of a large current when a PT symmetry breaks during power supply in a wireless power supply system using the PT symmetry.SOLUTION: A wireless power supply system is configured such that a PT symmetry is preserved between a power supply unit and a power reception unit. The power supply unit includes an inverter, a current detection unit that outputs a detection signal representing an input current input from the inverter to a power supply side resonant circuit, and a drive control unit. The drive control unit (i) drives the inverter by outputting a drive signal generated so as to switch an opening / closing state of a switching element of the inverter in accordance with a timing at which the input current appearing in the detection signal switches from negative to positive, and (ii) stops driving of the inverter when the detection signal indicating that an event indicating a break of the PT symmetry has occurred is input from the current detection unit during driving of the inverter.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present application relates to a wireless power supply system and a control method for an inverter executed on the power supply side of the wireless power supply system. [Background technology]

[0002] One example of wireless power transfer is a coupled (non-radiative) type that uses electromagnetic action to enable wireless power transfer between a receiving coil and a feeding coil. Among coupled wireless power transfer methods, the magnetic resonance method is known to be able to achieve high power transfer efficiency compared to the electromagnetic induction method, even when the distance or positional deviation between the receiving coil and the feeding coil is large.

[0003] However, even in the magnetic resonance system, the transmitted power is usually significantly affected by the transmission distance, which is the distance between the coils on the receiving and transmitting sides. This is because the resonance frequency changes depending on the transmission distance. Therefore, in conventional wireless power transfer systems that use the magnetic resonance system, the receiving side and the transmitting side sometimes communicate with each other and cooperate to maintain a resonant state so that the transmitted power remains constant even when the transmission distance changes. However, such a configuration causes the system or device that performs wireless power transfer to become larger and more complex.

[0004] To address these issues, a magnetic resonance type wireless power transfer technology that utilizes PT (Parity-Time) symmetry has been proposed. PT symmetry refers to a symmetry that combines parity symmetry and time-reversal symmetry. An example of a wireless power transfer technology that utilizes PT symmetry is disclosed in, for example, Patent Document 1 listed below.

[0005] According to the wireless power transfer technology using PT symmetry, even if the distance between the receiver coil and the transmitter coil varies, the resonance state between the receiver and transmitter coils is naturally adjusted according to the principle of PT symmetry so that the transmitted power and the power transfer efficiency of the entire system are kept constant. Therefore, it is possible to omit the device configuration that performs control to maintain the resonance state as described above. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Publication No. 2022-121324 Summary of the Invention [Problem to be solved by the invention]

[0007] In wireless power transfer systems that utilize PT symmetry, when PT symmetry is broken, the power transmission current on the power source side can become significantly large. However, conventional wireless power transfer systems that utilize PT symmetry are primarily intended to operate within the range in which PT symmetry is maintained, and no consideration has been given to counteracting situations in which PT symmetry is broken to the point where such a large current occurs.

[0008] An object of the present application is to provide a technology that can suppress the generation of a large current when PT symmetry is broken during power supply in a wireless power supply system. [Means for solving the problem]

[0009] The present invention can be realized, for example, in the following forms.

[0010] One embodiment of the present invention is provided as a wireless power supply system. This form of wireless power supply system includes: a receiving unit having a receiving-side resonant circuit including a receiving-side coil and connected to a load; and a power supply unit having a feeding-side resonant circuit including a feeding-side coil and supplying power to the receiving unit by magnetic resonance with the receiving unit, wherein the power supply unit and the power receiving unit are configured to preserve PT symmetry. The power supply unit includes an inverter having a plurality of switching elements and controlling the resonant frequency of the power supply unit by switching the open / close states of the plurality of switching elements in accordance with an input drive signal; a current detection unit that detects an input current input from the inverter to the feeding-side resonant circuit and outputs a detection signal representing the input current; and a drive control unit connected to the inverter and the current detection unit, (i) driving the inverter by outputting the drive signal that is generated so that the open / close states of the switching elements switch in accordance with the timing when the input current appearing in the detection signal switches from negative to positive, and (ii) stopping the drive of the inverter when the detection signal representing the occurrence of an event indicating a breaking of the PT symmetry is input from the current detection unit while the inverter is being driven. In this wireless power supply system, when a detection signal indicating that PT symmetry has been broken during wireless power supply from the power supply unit to the power receiving unit is detected, the drive control unit of the power supply unit that controls the drive of the inverter automatically stops the drive of the inverter, thereby preventing a large current from being generated in the power supply unit due to a PT symmetry breaking that occurs during power supply.

[0011] The present invention can be realized in various forms other than a wireless power supply system or a method for controlling an inverter executed on the power supply side of a wireless power supply system. For example, the present invention can be realized in the form of a device constituting a power supply unit or a power receiving unit constituting a wireless power supply system, a wireless power supply method executed in a wireless power supply system, a control circuit for controlling the drive of an inverter on the power supply side, etc. The present invention can also be realized in the form of, for example, a power supply method of a wireless power supply system, a program for causing a computer to execute inverter drive control, a recording medium on which the program is recorded, etc. [Brief explanation of the drawings]

[0012] [Figure 1] 1 is a schematic diagram showing the configuration of a wireless power supply system according to a first embodiment. [Figure 2] FIG. 2 is a schematic diagram showing the configuration of an inverter in a power supply unit. [Figure 3A] FIG. 10 is an explanatory diagram for explaining a resonant state due to PT symmetry. [Figure 3B] An explanatory diagram for explaining PT symmetry breaking. [Figure 4] FIG. 4 is a flowchart illustrating the operation of the wireless power supply system. [Figure 5A] FIG. 10 is an explanatory diagram illustrating an example of a current change in a normal state after power supply is started. [Figure 5B] FIG. 10 is an explanatory diagram illustrating a change in current when PT symmetry is broken. [Figure 6] FIG. 10 is a schematic diagram showing the configuration of a wireless power supply system according to a second embodiment. [Figure 7] FIG. 1 is a schematic diagram illustrating an example of a phase delay circuit. [Figure 8] FIG. 4 is an explanatory diagram showing the relationship between the phase of the output voltage of the inverter and the phase of the drive signal. [Figure 9] FIG. 10 is a schematic diagram showing the configuration of a drive control unit according to a third embodiment. [Figure 10] FIG. 10 is a schematic diagram showing the configuration of a drive control unit according to a fourth embodiment. [Figure 11] FIG. 10 is a schematic diagram showing the configuration of a wireless power supply system according to a fifth embodiment. [Figure 12] FIG. 10 is a schematic diagram showing the configuration of a wireless power supply system according to a fifth embodiment. [Figure 13] FIG. 10 is a schematic diagram showing the configuration of an inverter according to a fifth embodiment. [Figure 14] FIG. 13 is a schematic diagram showing the configuration of a drive control unit according to a sixth embodiment. [Figure 15] FIG. 20 is an explanatory diagram showing an example of a method for detecting an abnormality in the drive frequency by a stop command unit according to the seventh embodiment. [Figure 16] FIG. 13 is an explanatory diagram for explaining a drive signal output by a phase detection unit according to the eighth embodiment. [Figure 17] FIG. 13 is a schematic diagram showing the configuration of a wireless power supply system according to a ninth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0013] Hereinafter, an example of an embodiment of a wireless power supply system and an inverter control method executed on the power supply side of the wireless power supply system will be described with reference to the drawings.

[0014] 1. First embodiment: 1 is a schematic diagram showing the configuration of a wireless power supply system 100 according to a first embodiment. The wireless power supply system 100 of this embodiment performs wireless power supply using a magnetic resonance method that utilizes the principle of PT symmetry. Hereinafter, the wireless power supply system 100 will also be simply referred to as the "power supply system 100."

[0015] The power supply system 100 includes a power receiving unit 10 connected to an external load LD, and a power supply unit 20 connected to an external DC power supply. In the power supply system 100, magnetic field resonance occurs between resonant circuits included in the power supply unit 20 and the power receiving unit 10, thereby wirelessly transmitting power from the power supply unit 20 to the power receiving unit 10. As will be described later, in the power supply system 100, the power supply unit 20 and the power receiving unit 10 are configured to maintain PT symmetry.

[0016] The power receiving unit 10 includes a power receiving side resonant circuit 10c. The power receiving side resonant circuit 10c is configured with a power receiving side coil 11 and a power receiving side capacitor 12. In this embodiment, the power receiving side coil 11 and the power receiving side capacitor 12 are connected in series to a load LD.

[0017] The power supply unit 20 includes a power supply side resonant circuit 20c. The power supply side resonant circuit 20c is configured with a power supply side coil 21 and a power supply side capacitor 22. In this embodiment, the power supply side coil 21 and the power supply side capacitor 22 are connected in series. During wireless power supply, the power supply side coil 21 of the power supply unit 20 is arranged adjacent to the power receiving side coil 11 of the power receiving unit 10 without being in direct contact with each other, which would result in electrical conduction.

[0018] Power supply unit 20 further includes inverter 23, current detection unit 29, and drive control unit 30. As will be described later, inverter 23, current detection unit 29, and phase detection unit 32 of power supply unit 20 are configured to maintain PT symmetry with power receiving unit 10. Below, inverter 23, current detection unit 29, and drive control unit 30 will be described in order. PT symmetry will also be described along the way.

[0019] First, the configuration of inverter 23 included in power supply unit 20 will be described with reference to Fig. 2. Inverter 23 has multiple switching elements 25f, 25s. Inverter 23 controls the resonant frequency of power supply unit 20 by switching the open / closed states of switching elements 25f, 25s in response to drive signals Sd, rSd input from drive control unit 30. Switching elements 25f, 25s are configured by, for example, MOSFETs.

[0020] The inverter 23 of this embodiment includes a first switch circuit 24a and a second switch circuit 24b. The first switch circuit 24a includes a pair of switching elements 25f and 25s and a gate drive circuit .

[0021] The pair of switching elements 25f, 25s are connected in series to a DC power supply of voltage VPP. Each of the pair of switching elements 25f, 25s is connected in parallel to one terminal of power supply side resonant circuit 20c. In this embodiment, the pair of switching elements 25f, 25s of first switch circuit 24a is connected to power supply side coil 21 via power supply side capacitor 22.

[0022] An input terminal of the gate drive circuit 26 is connected to the signal output unit 45 of the drive control unit 30 shown in Fig. 1. A drive signal Sd is input to the gate drive circuit 26 from the drive control unit 30 via the input terminal. The gate drive circuit 26 has two output terminals, and a corresponding one of the pair of switching elements 25f, 25s is connected to each output terminal.

[0023] The gate drive circuit 26 outputs signals in parallel, with phases opposite to each other, to each of the pair of switching elements 25. The gate drive circuit 26 outputs a first drive signal Sdf to the first switching element 25f, and outputs a second drive signal Sds to the second switching element 25s. As will be described in detail in the second embodiment, an appropriate dead time is provided between the first drive signal Sdf and the second drive signal Sds.

[0024] Similar to the first switch circuit 24a, the second switch circuit 24b includes a pair of switching elements 25f, 25s and a gate drive circuit 26. The circuit configuration of the second switch circuit 24b is similar to that of the first switch circuit 24a, and therefore detailed description thereof will be omitted.

[0025] The pair of switching elements 25f, 25s of the second switch circuit 24b are connected in parallel to the other terminal of the power supply side resonant circuit 20c, opposite to the terminals to which the pair of switching elements 25f, 25s of the first switch circuit 24a are connected. Also, drive signals rSdf, rSds, which are inverted versions of the drive signals Sdf, Sds input to the switching elements 25f, 25s of the first switch circuit 24a, are input from the gate drive circuit 26 to the switching elements 25f, 25s of the second switch circuit 24b.

[0026] In both the first switch circuit 24a and the second switch circuit 24b, the open / closed states of the pair of switching elements 25f, 25s are switched according to the phases of the drive signals Sdf, Sds, rSdf, rSds output from the gate drive circuit 26. The open / closed states of the pair of switching elements 25f, 25s are basically controlled so that when one is in an open state, the other is in a closed state.

[0027] 1, the current detection unit 29 detects the input current It input from the inverter 23 to the power supply side resonant circuit 20c, and outputs a detection signal DS representing the input current It to the drive control unit 30. The current detection unit 29 is formed by, for example, a current sensor.

[0028] In this embodiment, the current detection unit 29 is installed between the first switch circuit 24a of the inverter 23 and the power supply-side capacitor 22. In this embodiment, the current detection unit 29 is configured to output a detection signal DS whose positive and negative directions match those of the input current It and which indicates the magnitude and frequency of the input current It.

[0029] The drive control unit 30 is connected to the inverter 23 and the current detection unit 29. The drive control unit 30 controls the drive of the inverter 23 using the detection signal DS input from the current detection unit 29. The drive control unit 30 includes a phase detection unit 32, a break detection unit 35, a drive state switching unit 40, and a signal output unit 45.

[0030] The input terminals of the phase detection unit 32 and the break detection unit 35 are connected in parallel to the current detection unit 29. The output terminals of the phase detection unit 32 and the break detection unit 35 are connected to two input terminals of the drive state switching unit 40. The output terminal of the drive state switching unit 40 is connected to an input terminal of the signal output unit 45, and the two output terminals of the signal output unit 45 are connected to the inverter 23.

[0031] The phase detection unit 32 is a component that contributes to establishing PT symmetry between the power receiving unit 10 and the power supply unit 20. The breakdown detection unit 35 is a component that functions to detect an abnormality in which the PT symmetry is broken. The drive state switching unit 40 switches the drive state of the inverter 23 by switching the signal input to the inverter 23. The signal output unit 45 inputs the signal input from the drive state switching unit 40 to the inverter 23. Below, the phase detection unit 32, the breakdown detection unit 35, the drive state switching unit 40, and the signal output unit 45 will be described in detail in this order.

[0032] The phase detection unit 32 includes a first comparator 33. A non-inverting input terminal of the first comparator 33 is connected to the current detection unit 29. Although not shown, an inverting input terminal of the first comparator 33 is connected to the ground or a fixed potential. An output terminal of the first comparator 33 is connected to a first input terminal A of a NAND gate 41 of the drive state switching unit 40.

[0033] The first comparator 33 converts the periodic waveform input from the current detection unit 29 into a square wave to generate a drive signal Sd, which is input to the drive state switching unit 40. As will be described later, the drive signal Sd is input to the inverter 23 via the drive state switching unit 40 to drive the inverter 23. The drive signal Sd corresponds to a signal generated to switch the open / closed state of each of the switching elements 25f, 25s of the inverter 23 in accordance with the timing at which the input current It appearing in the detection signal DS switches from negative to positive.

[0034] In power supply system 100, the circuit of power supply unit 20, which is composed of inverter 23, current detection unit 29, and phase detection unit 32, is configured to function as a negative resistance circuit that behaves as a negative resistance corresponding to load LD connected to power receiving unit 10. This preserves PT symmetry between power receiving unit 10 and power supply unit 20. Therefore, even if the distance between power receiving side coil 11 and power supply side coil 21 fluctuates, the resonant frequencies of power receiving unit 10 and power supply unit 20 are naturally adjusted in accordance with the principle of PT symmetry, and the transmitted power is maintained constant.

[0035] However, the PT symmetry may be broken due to changes in the conditions of the power receiving unit 10 and the power supply unit 20. Breaking of PT symmetry occurs, for example, when the power receiving unit 10 is separated from the power supply unit 20 and the distance between the power receiving coil 11 and the power supply coil 21 becomes significantly large, or when the power supply is cut off because the battery included in the load LD of the power receiving unit 10 has finished charging. In addition, breaking of PT symmetry may also occur when an abnormal decrease or increase in the resistance value of the load LD of the power receiving unit 10 occurs, or due to a fault such as a short circuit inside the power receiving unit 10 or the power supply unit 20.

[0036] Breaking of PT symmetry will be described with reference to Figures 3A and 3B. Figure 3A is a schematic diagram illustrating a resonant state between the power receiving unit 10 and the power supply unit 20 when PT symmetry is preserved. Figure 3B is a schematic diagram illustrating a state when PT symmetry is broken and the resonant state between the power receiving unit 10 and the power supply unit 20 is broken.

[0037] 3A and 3B show, in the upper part, a pendulum 10a representing the oscillating power receiving unit 10 and a pendulum 20a representing the oscillating power supply unit 20. In addition, in the lower part of each of Figs. 3A and 3B, the changes over time in the power supply current Ia on the power supply unit 20 side and the power receiving current Ib on the power receiving unit 10 side are illustrated in the states shown by the pendulums 10a and 20a in the upper part.

[0038] In Figures 3A and 3B, pendulum 10a oscillates upon receiving force from power source PS, and pendulum 20a transmits the force generated by the oscillation to load LD. When PT symmetry is maintained between power receiving unit 10 and power supply unit 20, as shown by pendulums 10a and 20a in the upper part of Figure 3A, power receiving unit 10 and power supply unit 20 are in a resonant state. In this state, as shown in the lower part of Figure 3A, power supply current Ia and power receiving current Ib are nearly equal, achieving extremely high transmission efficiency. Note that in Figure 3A, the lengths of the arrows indicating the reciprocating motion of pendulums 10a and 20a are equal. This means that the magnitude and frequency of the current on the power supply side and the power receiving side are equal due to the establishment of PT symmetry.

[0039] When the PT symmetry is broken for the reasons described above, the power supply unit 20, which is released from the load of the power receiving unit 10, oscillates more strongly, as shown by the increased amplitude of pendulum 20a in the upper part of Figure 3B. Meanwhile, the power supply unit 20 decays, as shown by the decreased amplitude of pendulum 10a, which is not in resonance with pendulum 20a, in the upper part of Figure 3B. Therefore, as shown in the lower part of Figure 3B, the power supply current Ia becomes significantly larger than normal, while the power receiving current Ib becomes significantly smaller. Note that in Figure 3B, the difference in the lengths of the arrows indicating the reciprocating motion of pendulums 10a and 20a indicates that the current on the power receiving side is attenuated more than the current on the power supply side due to the broken PT symmetry.

[0040] 1, the break detection unit 35 is configured to output a stop signal SS for stopping the operation of the inverter 23 when the detection signal DS indicates an event indicating a break in PT symmetry as described above. In this embodiment, the break detection unit 35 is configured to output the stop signal SS when the detection signal DS indicates that the input current It is an overcurrent equal to or greater than a predetermined threshold, indicating that a break in PT symmetry has occurred.

[0041] The breakdown detection unit 35 includes a second comparator 36 and a timer circuit 37. The inverting input terminal of the second comparator 36 is connected to the current detection unit 29. Although not shown, a detection diode is provided between the inverting input terminal of the second comparator 36 and the current detection unit 29. Furthermore, although not shown, the non-inverting input terminal of the second comparator 36 is connected to a fixed potential. This fixed potential corresponds to a threshold voltage that is a boundary value between the potential of the detection signal DS in a normal state where PT symmetry is maintained and the potential of the detection signal DS in an abnormal state where PT symmetry is broken.

[0042] The second comparator 36 functions as a current determination unit that detects the occurrence of a break in PT symmetry due to current. The second comparator 36 continues to output a normal signal NS while PT symmetry between the power receiving unit 10 and the power supply unit 20 is maintained, wireless power supply is being performed, and a detection signal DS within the normal range is being input. On the other hand, when the voltage of the detection signal DS exceeds a threshold voltage and the detection signal DS indicates the occurrence of an overcurrent that occurs when PT symmetry is broken, as described below, the second comparator 36 outputs a stop signal SS to stop the inverter 23. The signals NS and SS output by the second comparator 36 are input to a timer circuit 37.

[0043] In this embodiment, the normal signal NS output by the second comparator 36 is a high signal, and the stop signal SS is a low signal. In other embodiments, the second comparator 36 may be configured to output a low signal as the normal signal NS and a high signal as the stop signal SS.

[0044] The timer circuit 37 can be formed, for example, by a combination of a CR circuit and a diode. The timer circuit 37 is configured to input the normal signal NS input from the second comparator 36 to the drive state switching unit 40 as is, except during a standby period described below. Furthermore, when a stop signal SS is input from the second comparator 36, the timer circuit 37 is configured to input the stop signal SS to the drive state switching unit 40 and continue inputting the stop signal SS to the drive state switching unit 40 for a predetermined standby period.

[0045] With the above configuration, the break detection unit 35 inputs a normal signal NS to the drive state switching unit 40 while the detection signal DS indicating a normal state in which PT symmetry is maintained is being input. Furthermore, once the detection signal DS indicating the occurrence of an event indicating a break in PT symmetry is input, the break detection unit 35 continues to input a stop signal SS to the drive state switching unit 40 for a predetermined time. Note that in another embodiment, instead of providing the timer circuit 37 in the break detection unit 35, a timer function equivalent to that of the timer circuit 37 may be realized by a hysteresis provided in the second comparator 36.

[0046] The drive state switching unit 40 includes a NAND gate 41, a capacitor C1, and a resistor R1. A first input terminal A of the NAND gate 41 is connected to the output terminal of the first comparator 33 of the phase detection unit 32 via the capacitor C1. A drive signal Sd is input to the first input terminal A of the NAND gate 41 from the phase detection unit 32.

[0047] A second input terminal B of the NAND gate 41 is connected to the output terminal of the break detection unit 35. In this embodiment, the second input terminal B of the NAND gate 41 is connected to the output terminal of the timer circuit 37 of the break detection unit 35. A normal signal NS or a stop signal SS is input from the break detection unit 35 to the second input terminal B of the NAND gate 41.

[0048] The output terminal of the NAND gate 41 is connected to the input terminal of the signal output unit 45. The resistor R1 connects the first input terminal A of the NAND gate 41 and the output terminal of the NAND gate 41 together.

[0049] The drive state switching unit 40 receives the drive signal Sd from the phase detection unit 32 at a first input terminal A of the NAND gate 41 and outputs an inverted drive signal rSd while the normal signal NS from the break detection unit 35 is input to a second input terminal B of the NAND gate 41. The inverted drive signal rSd is an inverted signal of the drive signal Sd. The inverted drive signal rSd is input to a signal output unit 45.

[0050] While the stop signal SS is being input from the tear detection unit 35 to the second input terminal B of the NAND gate 41, the drive state switching unit 40 does not output the drive signal Sd, and the input of the signal to the signal output unit 45 is interrupted. As a result, the input of the drive signal Sd from the signal output unit 45 to the inverter 23 is stopped, and the drive of the inverter 23 is stopped.

[0051] When the input of the stop signal SS from the break detector 35 ends, the drive state switching unit 40 oscillates at a predetermined frequency. The predetermined frequency is, for example, 1 Hz. A signal generated by this oscillation is input to the inverter 23 via the signal output unit 45, thereby restarting the operation of the inverter 23, which had been stopped. After the operation of the inverter 23 is restarted, the input current It flows through the power supply coil 21, and a drive signal Sd corresponding to the detection signal DS is input to the inverter 23.

[0052] In this way, the drive state switching unit 40 has a function of stopping the inverter 23 that is in operation in response to the stop signal SS input from the tear detection unit 35. The drive state switching unit 40 also has a function of automatically restarting the stopped inverter 23 when the stop signal SS is no longer input.

[0053] The signal output unit 45 includes three signal inverting elements 46a, 46b, and 46c. The first signal inverting element 46a is provided between the drive state switching unit 40 and the gate drive circuit 26 of the first switch circuit 24a. The first signal inverting element 46a inverts the positive and negative of the signal input from the drive state switching unit 40 and inputs the signal to the gate drive circuit 26 of the first switch circuit 24a.

[0054] The second signal inverting element 46b and the third signal inverting element 46c are provided between the drive state switching unit 40 and the gate drive circuit 26 of the second switch circuit 24b. The second signal inverting element 46b and the third signal inverting element 46c are connected in series. The second signal inverting element 46b and the third signal inverting element 46c input a signal whose polarity matches that of the signal input from the drive state switching unit 40 to the gate drive circuit 26 of the second switch circuit 24b.

[0055] The signal output unit 45 inputs the drive signal Sd input from the phase detection unit 32 via the drive state switching unit 40 to the gate drive circuit 26 of the first switch circuit 24a. At the same time, the signal output unit 45 inputs the drive signal rSd, which is an inverted version of the drive signal Sd, to the gate drive circuit 26 of the second switch circuit 24b. This drives the inverter 23, causing the input current It to flow through the power supply side coil 21 of the power supply side resonant circuit 20c, and magnetic field resonance occurs between the resonant circuits 10c, 20c, thereby transmitting power wirelessly from the power supply unit 20 to the power receiving unit 10.

[0056] The operation of the power supply system 100 will be described with reference to Fig. 4. In the power supply system 100, it can be understood that the control process of the inverter 23 shown in the flowchart of Fig. 4 is executed.

[0057] In step S10, the power receiving coil 11 of the power receiving unit 10 and the power supply coil 21 of the power supply unit 20 are arranged adjacent to each other, and wireless power supply is performed between the power receiving unit 10 and the power supply unit 20. As described above, this wireless power supply is performed in a state where the PT symmetry between the power receiving unit 10 and the power supply unit 20 is maintained.

[0058] Step S20 corresponds to a step of detecting the occurrence of PT symmetry breaking. In step S20, the breaking detection unit 35 outputs a normal signal NS when the detection signal DS does not indicate the occurrence of PT symmetry breaking, and outputs a stop signal SS for stopping the inverter 23 when the detection signal DS indicates the occurrence of PT symmetry breaking. In this embodiment, as described above, the normal signal NS is output when the input current It flowing through the power supply side coil 21 is equal to or less than the threshold, and the stop signal SS is output when the input current It is greater than the threshold.

[0059] When no breaking of PT symmetry is detected from the detection signal DS, the breaking detection unit 35 outputs a normal signal NS, and the execution of wireless power feeding in step S10 continues (arrow NO in step S20). When a breaking of PT symmetry is detected from the detection signal DS, the breaking detection unit 35 outputs a stop signal SS, and the process of step S30 is executed (arrow YES in step S20).

[0060] In step S30, the inverter 23 is stopped. As described above, the drive state switching unit 40, to which the stop signal SS is input from the tear detection unit 35, stops inputting the drive signals Sd and rSd to the signal output unit 45, thereby stopping the inverter 23.

[0061] In step S40, the inverter 23 is kept stopped and on standby for a predetermined time. As described above, the timer circuit 37 of the tear detection unit 35 continues to input the stop signal SS to the drive state switching unit 40 for a predetermined time, thereby maintaining the standby state in which the inverter 23 is stopped.

[0062] In step S50, the driving of the inverter 23 is resumed. As described above, when the timer circuit 37 of the tear detection unit 35 finishes inputting the stop signal SS to the driving state switching unit 40, a signal for starting the driving of the inverter 23 is input from the driving state switching unit 40 to the inverter 23. This causes the driving of the inverter 23 to be resumed.

[0063] Thereafter, if the cause of the PT symmetry breaking is resolved while inverter 23 is stopped in step S40, wireless power feeding is performed between power receiving unit 10 and power feeding unit 20 in step S10. If the cause of the PT symmetry breaking is still not resolved when inverter 23 is restarted in step S50, inverter 23 goes through step S20 and is again stopped in step S30.

[0064] 5A and 5B, an example of the change over time of the input current It in the power supply system 100 during wireless power supply will be described. Fig. 5A shows an example of the change over time of the input current It when the inverter 23 starts driving from a stopped state and transitions to a normal power supply state.

[0065] As shown in Figure 5A, at time t i In the initial state immediately after the inverter 23 starts to operate, the amplitude of the input current It gradually increases. In a normal state where the PT symmetry is maintained, the input current It reaches the target current IT at time t s Thereafter, while wireless power supply continues, the target current IT oscillates at a constant cycle with the target current IT as the maximum value.

[0066] FIG. 5B shows an example of the time variation of the input current It when the PT symmetry is broken after the inverter 23 starts to operate. When the PT symmetry is broken, the amplitude of the input current It gradually increases, and the maximum value exceeds the target current IT. When the maximum value of the input current It is equal to or exceeds the threshold current I th The time t e At time t, the stop signal SS is input from the break detection unit 35 to the drive state switching unit 40. e After that, the inverter 23 stops driving, so the input current It gradually attenuates and becomes 0. Therefore, even if the PT symmetry is broken during power supply, the input current It does not exceed the threshold current I th Therefore, the current is prevented from exceeding the limit.

[0067] As described above, the power supply system 100 of this embodiment is configured to use the detection signal DS to preserve the PT symmetry between the power receiving unit 10 and the power supply unit 20. Therefore, for example, even if the distance between the power receiving side coil 11 and the power supply side coil 21 increases to some extent or a certain degree of positional deviation occurs during power supply, fluctuations in the power transmission efficiency are suppressed.

[0068] Furthermore, according to the power supply system 100 of this embodiment, when the detection signal DS for realizing PT symmetry indicates that PT symmetry is broken during power supply, the driving of the inverter 23 of the power supply unit 20 is stopped. This prevents a large current from being generated in the power supply unit 20 due to the breaking of PT symmetry during power supply.

[0069] Furthermore, according to the power supply system 100 of this embodiment, when a certain waiting time has elapsed after the driving of the inverter 23 has been stopped, the driving state switching unit 40 automatically resumes driving the inverter 23. This prevents the inverter 23 from remaining in a stopped state even though the cause of the temporary breaking of PT symmetry has been resolved, and the availability of the power supply system 100 is improved.

[0070] 2. Second embodiment: 6 is a schematic diagram showing the configuration of a power supply system 100A according to the second embodiment. The configuration of the power supply system 100A according to the second embodiment is substantially the same as that of the power supply system 100 according to the first embodiment, except that the configuration of the power supply unit 20A is different. The configuration of the power supply unit 20A according to the second embodiment is substantially the same as that of the power supply unit 20 according to the first embodiment, except that a drive control unit 30A includes a phase detection unit 32A to which a phase delay unit 34 is added.

[0071] The phase detection unit 32A of the second embodiment has almost the same configuration as the phase detection unit 32 described in the first embodiment, except that a phase delay unit 34 is added before the first comparator 33. The phase delay unit 34 delays the phase of the input signal by a predetermined period. In this embodiment, the phase delay unit 34 delays the phase of the detection signal DS output by the current detection unit 29. The input side of the phase delay unit 34 is connected to the current detection unit 29, and the output side is connected to the first comparator 33.

[0072] The phase delay unit 34 will be described in detail with reference to Figures 7 and 8. Figure 7 is a schematic diagram showing an example of a phase delay circuit 34c that constitutes the phase delay unit 34.

[0073] In this embodiment, the phase delay unit 34 is configured with a plurality of phase delay circuits 34c. Each phase delay circuit 34c is configured with a CR circuit including a capacitor C2 and a resistor R2. In this embodiment, the phase delay unit 34 has a configuration in which a plurality of phase delay circuits 34c are connected in series. The phase delay unit 34 may be configured, for example, by connecting two phase delay circuits 34c in series, each of which delays the phase by π / 2 or more.

[0074] 8 shows a timing chart of the input current It of the power supply-side resonant circuit 20c, the drive signals Sd, Sdf, and Sds, the voltage Vf of the first switching element 25f of the first switch circuit 24a, and the input voltage Vt of the power supply-side resonant circuit 20c. Also shown in FIG. 8 are an ideal drive signal Sdi and a comparative drive signal Sdc between the input current It and the drive signal Sd. The comparative drive signal Sdc corresponds to a signal generated when the phase of the detection signal DS is not delayed by the phase delay unit 34. In FIG. 8, the drive signal Sdf indicates the open / closed state of the first switching element 25f of the first switch circuit 24a, and the drive signal Sds indicates the open / closed state of the second switching element 25s of the first switch circuit 24a.

[0075] In the power supply unit 20, it is preferable that the drive signal Sd output by the phase detector 32 has a zero phase difference with respect to the input current It, as indicated by the ideal drive signal Sdi. However, if the phase detector 32 does not include the phase delay unit 34, a phase delay DL occurs between the input current It and the drive signal Sdc, as indicated by the drive signal Sdc of the comparative example. When this phase delay DL occurs, current flows into the switching element 25s before the switching element 25f is closed, resulting in hard switching. The occurrence of hard switching can cause significant power loss and reduced transmission efficiency in wireless power transmission. This phase delay DL is unavoidable in real electronic circuits.

[0076] Therefore, in power supply unit 20, phase detector 32 generates a drive signal Sd based on a phase of input current It prior to the current cycle, rather than a drive signal based on the phase of input current It in the current cycle, and outputs the drive signal Sd to inverter 23. Phase detector 32 generates drive signal Sd so that the open / closed states of switching elements 25f, 25s are switched in accordance with the timing at which input current It switches from negative to positive, as shown in detection signal DS delayed a predetermined cycle from the current cycle. This drive signal Sd enables the open / closed states of switching elements 25r, 25s to be switched immediately before the timing at which input current It switches from negative to positive in the current cycle.

[0077] To generate such a drive signal Sd, in this embodiment, the phase detector 32 uses the phase delay unit 34 to delay the phase of the detection signal DS by a larger amount than the phase delay DL, and generates the drive signal Sd using the phase of the detection signal DS in a period prior to the current period. The phase delay unit 34 delays the phase of the detection signal DS by a period determined in advance through experiments or the like. The period delayed by the phase delay unit 34 is set so that the timing at which the open / closed states of the switching elements 25f, 25s switch is immediately before the timing at which the input current It represented by the detection signal DS switches from negative to positive.

[0078] Expressed in specific numerical ranges, the phase delay unit 34 may be configured to delay the phase of the detection signal DS by at least ¾ of a cycle but less than one cycle. The phase delay unit 34 may be configured to delay the phase of the detection signal DS by at least 5 / 6 of a cycle but less than one cycle. As a result, the phase detection unit 32 generates the drive signal Sd such that the timing at which the open / closed states of the switching elements 25f, 25s change is immediately before the timing at which the input current It changes from negative to positive.

[0079] In the phase delay unit 34, the gate drive circuit 26 generates a predetermined dead time DT between the drive signals Sdf and rSdf input to the first switching element 25f and the drive signals Sds and rSds input to the second switching element 25s. The dead time DT is a small time lag between the timing at which the first switching element 25f is closed and the timing at which the second switching element 25s is opened. The dead time DT corresponds to a transition period during which the input voltage Vt of the inverter 23 changes from an upper limit to a lower limit or from the lower limit to the upper limit.

[0080] According to this configuration, it is possible to precisely match the opening and closing cycle of switching elements 25f, 25s of inverter 23 with the cycle of resonance in power supply unit 20. Therefore, even when transmitting large amounts of power, for example, 1 kW or more, between power receiving unit 10 and power supply unit 20, it is possible to prevent a decrease in the transmission power or the power transmission efficiency of the entire system due to insufficient accuracy in the drive control of inverter 23.

[0081] Furthermore, with the above-described configuration in which the phase of the detection signal DS is delayed by the phase delay unit 34, the open / closed states of the switching elements 25f and 25s of the inverter 23 are switched in synchronization with the timing at which the input current It switches from negative to positive. This allows the charge accumulated in the parasitic capacitance of the switching elements 25f and 25s due to the negative current before the switching elements 25f and 25s are closed to be eliminated, thereby achieving zero-volt switching (ZVS). This suppresses the occurrence of transient crossings between voltage and current, reducing power loss due to driving the switching elements 25 in the inverter 23. The effect of reducing power loss in the inverter 23 becomes greater as the inverter 23 operates in a higher frequency range.

[0082] As described above, the phase delay circuit 34c constituting the phase delay unit 34 of this embodiment has a configuration in which multiple phase delay circuits 34c are connected in series. By combining multiple phase delay circuits 34c, it is possible to achieve a phase delay sufficient to generate the drive signal Sd using the phase of a period prior to the current period of the detection signal, as described above, with a simple circuit configuration such as that shown in Fig. 7.

[0083] As described above, the phase delay circuit 34c of this embodiment is configured by a CR circuit, which can further suppress signal attenuation and noise generation in the phase delay circuit 34c.

[0084] As described above, according to the power supply system 100A of the second embodiment, the phase detection unit 32 of the power supply unit 20 has a phase delay unit 34, which makes it possible to suppress the occurrence of hard switching and realize ZVS. This makes it possible to transmit large amounts of power more efficiently and reduce power loss caused by the opening and closing of the switching elements 25 of the inverter 23. In addition, according to the power supply system 100A of the second embodiment, it is possible to achieve various effects similar to those described in the first embodiment.

[0085] 3. Third embodiment: 9 is a schematic diagram showing the configuration of a drive control unit 30B included in a power supply unit 20B of a power supply system 100B of the third embodiment. The configuration of the power supply system 100B of the third embodiment is substantially the same as the power supply system 100A of the second embodiment, except for the configuration of the drive control unit 30B. The configuration of the drive control unit 30B of the third embodiment is substantially the same as the configuration of the drive control unit 30 of the second embodiment, except for the configuration of the tear detection unit 35B.

[0086] The break detection unit 35B of the third embodiment includes a waiting time control unit 38 instead of the timer circuit 37. The break detection unit 35B further includes a diode D1, a first resistor R3, and a second resistor R4.

[0087] The output terminal of the second comparator 36 of the break detection unit 35B is connected to the second input terminal B of the NAND gate 41 of the drive state switching unit 40. The diode D1 is provided between the second comparator 36 and the NAND gate 41. The diode D1 is provided between the second comparator 36 and the NAND gate 41. The diode D1 passes only the normal signal NS output from the second comparator 36 and does not pass the stop signal SS.

[0088] The standby time control unit 38 is configured by a microcomputer having a central processing unit (CPU) and a main memory device (RAM), and controls the standby time during which the drive of the inverter 23 is stopped. The standby time control unit 38 is connected in parallel with the second comparator 36 of the break detection unit 35B to the current detection unit 29, and receives an input of the detection signal DS from the current detection unit 29. The standby time control unit 38 reads the voltage of the detection signal DS by AD conversion.

[0089] The standby time control unit 38 is connected to the output terminal of the second comparator 36 so as to be able to detect the signals NS and SS output by the second comparator 36. The standby time control unit 38 is also connected in parallel with the second comparator 36 and the diode D1 to the second input terminal B of the NAND gate 41 of the drive state switching unit 40 so as to be able to input a signal to the second input terminal B of the NAND gate 41. A first resistor R3 is provided between the second input terminal B of the NAND gate 41 and the standby time control unit 38. The second input terminal B of the NAND gate 41 is grounded via a second resistor R4.

[0090] When the second comparator 36 outputs the stop signal SS, the standby time control unit 38 inputs the stop signal SS to the second input terminal B of the NAND gate 41 of the drive state switching unit 40, thereby stopping the drive of the inverter 23. Based on the detection signal DS, the standby time control unit 38 continues to input the stop signal SS to the second input terminal B of the NAND gate 41, at least until the input current It becomes 0 A, thereby causing the inverter 23 to wait with the drive stopped.

[0091] The standby time control unit 38 keeps the inverter 23 in standby mode for a predetermined time after the input current It becomes 0 A. When the predetermined time has elapsed, the standby time control unit 38 stops inputting the stop signal SS to the second input terminal B of the NAND gate 41. This restarts the operation of the inverter 23. The standby time control unit 38 may have a function to change the time for which the inverter 23 is kept in standby mode depending on the situation.

[0092] As described above, according to the power supply system 100B of the third embodiment, the standby time control unit 38 configured by a microcomputer can appropriately adjust the standby time of the inverter 23 after the PT symmetry is broken. In addition, according to the power supply system 100B of the third embodiment, it is possible to achieve the various effects described in the above embodiments.

[0093] 4. Fourth embodiment: The configuration of a power supply system 100C of the fourth embodiment will be described with reference to Fig. 10 and Fig. 11. Fig. 10 is a schematic diagram showing the configuration of the power supply system 100C of the fourth embodiment. Fig. 11 is a schematic diagram showing the configuration of an inverter 23C included in the power supply system 100C of the fourth embodiment.

[0094] The configuration of a power supply system 100C of the fourth embodiment is substantially the same as that of the power supply system 100A of the second embodiment, except for the configuration of the power supply unit 20C. The power supply unit 20C of the fourth embodiment is substantially the same as the power supply unit 20A of the second embodiment, except for the fact that it includes an inverter 23C, a drive state switching unit 40C, and a tear detection unit 35C, each of which has a different configuration. The configurations of the inverter 23C, the drive state switching unit 40C, and the tear detection unit 35C of the fourth embodiment are substantially the same as those described in the second embodiment, except for the points described below.

[0095] 10, a drive state switching unit 40C included in a drive control unit 30C of the fourth embodiment has an inverting signal element 42 instead of a NAND gate 41. In the fourth embodiment, the drive state switching unit 40C does not receive a signal from the break detection unit 35. While a detection signal DS is being input to the phase detection unit 32, the drive state switching unit 40C inputs a drive signal rSd corresponding to the detection signal DS to the signal output unit 45. When the drive of the inverter 23C is stopped and the output of the current detection unit 29 becomes silent, the drive state switching unit 40C inputs a signal generated by self-oscillation to the inverter 23C via the signal output unit 45.

[0096] The break detection unit 35C included in the drive control unit 30C of the fourth embodiment is configured with an electronic circuit. The circuit configuration of the break detection unit 35C will not be illustrated or described in detail. The break detection unit 35C is configured to be able to detect the magnitude of the input current It based on the detection signal DS input from the current detection unit 29. Furthermore, the break detection unit 35C is configured to start inputting a stop signal SS to the inverter 23C when the input current It becomes larger than a threshold current, and to continue inputting the stop signal SS for a predetermined time.

[0097] 11, an inverter 23C according to the fourth embodiment includes a gate unit 26C configured by a MOSFET gate driver IC instead of the gate drive circuit 26. The gate unit 26C includes an input terminal IN to which drive signals Sd and rSd are input from a signal output unit 45, and an enable terminal EN to which a stop signal SS is input from a break detection unit 35C.

[0098] In the inverter 23C, while the stop signal SS is not input to the enable terminal EN, the switching elements 25f and 25s open and close in accordance with the drive signals Sd and rSd input from the signal output unit 45. Furthermore, while the stop signal SS is input to the enable terminal EN, the inverter 23C is in a standby state in which driving is stopped regardless of the signal input to the input terminal IN. Note that when the stop signal SS is no longer input to the enable terminal EN, the inverter 23C resumes driving in response to a signal generated by self-excited oscillation of the driving state switching unit 40C, which is input via the signal output unit 45.

[0099] As described above, according to the power supply system 100C of the fourth embodiment, the inverter 23C can be stopped by the stop signal SS output by the break detection unit 35C having a configuration different from that of the above embodiments. In addition, according to the power supply system 100C of the fourth embodiment, various effects similar to those described in the above embodiments can be achieved.

[0100] 5. Fifth embodiment: The configuration of a power supply system 100D of the fifth embodiment will be described with reference to Fig. 12 and Fig. 13. Fig. 12 is a schematic diagram showing the configuration of the power supply system 100D of the fifth embodiment. Fig. 13 is a schematic diagram showing the configuration of an inverter 23D included in the power supply system 100D of the fifth embodiment.

[0101] The configuration of a power supply system 100D of the fifth embodiment is substantially the same as that of the power supply system 100C of the third embodiment, except for the configuration of the power supply unit 20D. The power supply unit 20D of the fifth embodiment is substantially the same as the power supply unit 20C of the fourth embodiment, except for the configuration of the inverter 23D, the absence of the drive state switching unit 40C, and the inclusion of only a single signal inverting element 47 instead of the signal output unit 45.

[0102] 12, a drive control unit 30D of the fifth embodiment is configured to input to an inverter 23D a drive signal Sd output by a phase detection unit 32 and a drive signal rSd obtained by inverting the drive signal Sd output by the phase detection unit 32 by a signal inversion element 47. The drive control unit 30D also includes a break detection unit 35C described in the fourth embodiment.

[0103] Referring to FIG. 13, the inverter 23D further includes a capacitor C3 and a resistor R5 connected to the gate unit 26C of the first switch circuit 24a. The capacitor C3 is provided before the input terminal of the gate unit 26C. One end of the resistor R5 is connected between the capacitor C3 and the input terminal of the gate unit 26C. The other end of the resistor R5 is connected to the inverting output terminal of the gate unit 26C, which is connected to the second switching element 25s. In the inverter 23D, the capacitor C3 and the resistor R5 generate a signal for resuming driving from a stopped state.

[0104] As described above, according to the power supply system 100D of the fifth embodiment, the drive control unit 30D does not need to be provided with a component for restarting the inverter 23D from a stopped state. This allows for a simplification of the configuration of the drive control unit 30D. In addition, according to the power supply system 100D of the fifth embodiment, various operational effects similar to those described in the above embodiments can be achieved.

[0105] 6. Sixth embodiment: 14 is a schematic diagram showing the configuration of a drive control unit 30E included in a power supply system 100E of the sixth embodiment. The configuration of the power supply system 100E of the sixth embodiment is almost the same as the power supply system 100A of the second embodiment, except for the configuration of the drive control unit 30E. The configuration of the drive control unit 30E of the sixth embodiment is almost the same as the drive control unit 30A of the second embodiment, except for the addition of an OR gate 50 and the inclusion of a stop command unit 52.

[0106] In the power supply unit 20E of the sixth embodiment, an OR gate 50 is provided between the break detection unit 35 and the drive state switching unit 40. The timer circuit 37 of the break detection unit 35 is connected to a first input terminal of the OR gate 50. The break detection unit 35 inputs a normal signal NS or a stop signal SS to the OR gate 50.

[0107] A stop command unit 52 is connected to a second input terminal of the OR gate 50. When the stop command unit 52 detects an event that requires stopping the inverter 23, the stop command unit 52 inputs a stop signal SS to the OR gate 50 to stop the inverter 23. In this embodiment, the stop command unit 52 is configured by a human body detection sensor that detects a person approaching the power supply unit 20E. The stop command unit 52 inputs the stop signal SS to the OR gate 50 when a person is near the power supply unit 20E.

[0108] In other embodiments, the stop command unit 52 is not limited to a human body sensor. The stop command unit 52 may be configured, for example, by a seismic sensor that detects the occurrence of abnormal vibrations such as earthquakes. The stop command unit 52 may also be configured by a metallic foreign object detection sensor that detects the presence of a metallic foreign object between the power receiving coil 11 and the power supplying coil 21.

[0109] The output terminal of the OR gate 50 is connected to the second input terminal of the NAND gate 41 of the drive state switching unit 40. When a stop signal SS is input from either the break detection unit 35 or the stop command unit 52, the OR gate 50 inputs the stop signal SS to the second input terminal of the NAND gate 41. The OR gate 50 inputs the normal signal NS to the second input terminal of the NAND gate 41 only when a normal signal NS is input from the break detection unit 35 and a stop signal SS is not input from the stop command unit 52.

[0110] According to the power supply system 100E of the sixth embodiment, the inverter 23 is stopped not only when the break detection unit 35 detects that the PT symmetry has been broken, but also when the stop command unit 52 detects an event that should stop the drive of the inverter 23. Therefore, it is possible to prevent problems from occurring due to the inverter 23 continuing to be driven despite the occurrence of an event that should stop the inverter 23. In addition, according to the power supply system 100E of the sixth embodiment, it is possible to achieve various effects similar to those described in the above embodiments.

[0111] 7. Seventh embodiment: The power supply system of the seventh embodiment has almost the same configuration as the power supply system 100E of the sixth embodiment shown in FIG. 14, except that the stop command unit 52 detects an abnormality in the drive frequency by the detection signal DS as an event that requires stopping the inverter 23.

[0112] The stop command unit 52 of the seventh embodiment is configured by a frequency measurement FPGA (Field Programmable Gate Array) that detects the frequency of the detection signal DS. When the frequency of the detection signal DS is outside a predetermined normal range, the stop command unit 52 inputs a stop signal SS to the OR gate 50. Note that an abnormality in the drive frequency occurs, for example, when the coupling coefficient is significantly high in a state where PT symmetry is established.

[0113] 15 is an explanatory diagram showing an example of a method for detecting an abnormality in the drive frequency by the stop command unit 52 of the seventh embodiment. The stop command unit 52 has a circuit that outputs timer signals TS1 and T2 that serve as judgment criteria, and a circuit that compares the period of the detection signal DS representing the input current It with the period of the timer signals TS1 and T2. The first timer signal TS1 indicates the upper limit value t1 of the normal range of the period of the detection signal DS. The second timer signal TS2 indicates the lower limit value t2 of the normal range of the period of the detection signal DS. The timer signals TS1 and TS2 are counted, for example, by an FPGA included in the stop command unit 52.

[0114] The stop command unit 52 outputs a normal signal NS when the half period T / 2 of the input current It is equal to or less than the upper limit t1 indicated by the first timer signal TS1 and equal to or greater than the lower limit t2 indicated by the second timer signal TS2. The stop command unit 52 also outputs a stop signal SS when the half period T / 2 of the input current It is greater than the upper limit t1 indicated by the first timer signal TS1 or smaller than the lower limit t2 indicated by the second timer signal TS2.

[0115] As described above, according to the power supply system of the seventh embodiment, the stop command unit 52 can automatically stop the inverter 23 when an abnormal state in which the drive frequency is outside the normal range is detected. This makes it possible to prevent problems from occurring due to the inverter 23 continuing to be driven despite the occurrence of an event that should stop the inverter 23. In addition, according to the power supply system of the seventh embodiment, it is possible to achieve the various effects described in the above embodiments.

[0116] 8. Eighth embodiment: The drive signal Sd of the inverter 23 output by the phase detector 32 in the power supply system of the eighth embodiment will be described with reference to Fig. 16. Fig. 16 shows a timing chart of the input current It, the detection signal DS, and the drive signal Sd.

[0117] The configuration of the power supply system of the eighth embodiment is almost the same as the configuration of the power supply system 100A of the second embodiment, except for the different way of connecting the current detection unit 29. In the power supply system of the eighth embodiment, the current detection unit 29 is connected with the polarity reversed from that of the second embodiment so as to output a detection signal DS whose positive and negative directions are reversed from those of the input current It.

[0118] In the power supply system of the eighth embodiment, the detection signal DS output by the current detection unit 29 represents the input current It with its phase delayed by 1 / 2 cycle. With this configuration, the drive signal Sd can be generated based on the timing at which the input current It, which appears in the detection signal DS at a phase 1 / 2 cycle earlier, switches from positive to negative, as compared to the second embodiment. Therefore, the cycle to be delayed by the phase delay unit 34 can be set shorter than in the second embodiment. For example, in the eighth embodiment, the phase delay unit 34 may delay the phase by 3 / 8 cycle or more and less than 1 / 2 cycle.

[0119] According to the power supply system of the eighth embodiment, it is possible to achieve the various effects described in each of the above embodiments. Furthermore, the configuration of the power supply system of the eighth embodiment is applicable to the configurations of each of the above embodiments.

[0120] 9. Ninth embodiment: 17 is a schematic diagram showing the configuration of a power supply system 100G of the ninth embodiment. The power supply system 100G of the ninth embodiment is substantially the same as the power supply system 100A of the second embodiment, except for the configuration of the power supply unit 20G. The configuration of the power supply unit 20G of the ninth embodiment is substantially the same as the power supply unit 20A of the second embodiment, except for the configuration of the drive control unit 30G. In the drive control unit 30G of the ninth embodiment, the positions of the first comparator 33 and the phase delay unit 34 in the phase detection unit 32G are swapped, and the first comparator 33 is provided before the phase delay unit 34.

[0121] The phase detector 32G of the ninth embodiment generates a drive signal Sd whose phase is delayed relative to the input current It, without directly delaying the phase of the detection signal DS using the phase delay unit 34. As in the second embodiment, this drive signal Sd corresponds to a signal generated so that the open / closed state of the switching element 25 switches in synchronization with the timing of a change in the positive / negative state of the input current It appearing in the detection signal DS when the detection signal DS is delayed a predetermined period from the current period. Therefore, the power supply system 100G of the ninth embodiment can achieve various advantageous effects, including the realization of ZVS in driving the inverter 23, similar to those described in the second embodiment.

[0122] In addition, the power supply system 100G of the ninth embodiment can achieve the various effects described in the above embodiments. Also, the configuration of the phase detector 32G of the ninth embodiment can be applied to the configurations of the above embodiments.

[0123] 10. Other embodiments: The present invention is not limited to the configurations of the above-described embodiments. For example, the circuit configuration of each component of the wireless power supply system is not limited to the configurations described in the above-described embodiments. The circuit configuration of each component may be modified as appropriate within the scope of achieving substantially the same functions as those described in the above-described embodiments. Furthermore, the present invention can also be realized in the following forms, for example. In the following, all configurations described as other embodiments are positioned as examples of embodiments for carrying out the present invention, similar to the above-described embodiments.

[0124] 10-1. Other embodiment 1: In each of the above-described embodiments, the resonant circuits 10c and 20c of the power receiving unit 10 and the power feeding unit 20 may each have a configuration in which a coil and a capacitor are connected in parallel.

[0125] 10-2. Alternative embodiment 2: In each of the above embodiments, it may be omitted to provide a configuration for restarting inverter 23 that has been stopped after a break in PT symmetry has been detected by break detection unit 35. In each of the above embodiments, inverter 23 that has been stopped after a break in PT symmetry has been detected may remain stopped without being restarted.

[0126] 10-3. Other embodiment 3: In each of the above embodiments, the delay of the signal phase by the phase delay unit 34 may be realized by other circuit configurations instead of the multi-stage circuit configuration illustrated in Fig. 7. Furthermore, the phase delay circuit 34c constituting the phase delay unit 34 may be realized by, for example, an RC circuit instead of a CR circuit.

[0127] 10-4. Alternative embodiment 4: The configuration of the phase detector 32G described in the ninth embodiment may be applied to the power supply system of the eighth embodiment. That is, in the power supply system of the eighth embodiment, the current detector 29 may be connected to output a detection signal DS whose positive and negative directions are opposite to those of the input current It. This makes it possible to generate the drive signal Sd based on the timing at which the input current It, which appears in the detection signal DS in the phase 1 / 2 cycle earlier, switches from positive to negative, as described in the eighth embodiment.

[0128] 11. Example of morphology: The present invention can be realized in the following aspects.

[0129] [First embodiment] The first embodiment is provided as a wireless power supply system. A wireless power supply system of a first aspect includes: a receiving unit having a receiving-side resonant circuit including a receiving-side coil and connected to a load; and a power supply unit having a feeding-side resonant circuit including a feeding-side coil and feeding power to the receiving unit by magnetic resonance with the receiving unit, wherein the power supply unit and the receiving unit are configured to preserve PT symmetry; an inverter having a plurality of switching elements and controlling a resonant frequency of the power supply unit by switching the open / close states of the plurality of switching elements in accordance with an input drive signal; a current detection unit that detects an input current input from the inverter to the feeding-side resonant circuit and outputs a detection signal representing the input current; and a drive control unit connected to the inverter and the current detection unit, (i) driving the inverter by outputting the drive signal generated so that the open / close states of the switching elements switch in accordance with the timing when the input current appearing in the detection signal switches from negative to positive, and (ii) stopping driving of the inverter when the detection signal representing the occurrence of an event indicating breaking of the PT symmetry is input from the current detection unit while the inverter is being driven. According to the wireless power supply system of the first embodiment, when a detection signal indicating that PT symmetry has been broken is detected during wireless power supply from the power supply unit to the power receiving unit, the drive control unit of the power supply unit that controls the drive of the inverter automatically stops the drive of the inverter, thereby preventing a large current from being generated in the power supply unit due to the breaking of PT symmetry during power supply.

[0130] [Second Mode] In the wireless power supply system of the first mode, the drive control unit may stop driving the inverter when the detection signal indicating that the input current is greater than a predetermined threshold is input. According to the wireless power supply system of the second embodiment, the occurrence of PT symmetry breaking can be detected more easily and efficiently based on the magnitude and frequency of the input current indicated by the detection signal, and measures can be taken.

[0131] [Third Mode] In the wireless power supply system described in the first or second mode, the drive control unit may automatically resume driving of the inverter when a predetermined time has elapsed after stopping the operation of the inverter. According to the wireless power supply system of the third embodiment, if the PT symmetry breaking is resolved while the inverter is stopped, power supply is automatically resumed, thereby improving the operating rate of the wireless power supply system.

[0132] [Fourth Mode] In the wireless power supply system according to any one of the first, second, and third modes, the drive control unit may stop the inverter not only when it detects an event indicating a breaking of the PT symmetry, but also when it detects a predetermined event that should stop the drive of the inverter during wireless power supply. According to the wireless power supply system of the fourth embodiment, when an event that requires stopping the inverter is detected during wireless power supply, the inverter is stopped from operating, thereby preventing problems from occurring due to the inverter continuing to operate.

[0133] [Fifth Mode] In the wireless power supply system according to any one of the first, second, third, and fourth modes, the drive control unit may include a phase delay unit that delays the detection signal by a predetermined period, and may generate the drive signal using the detection signal whose phase is delayed from the current period by the phase delay unit, and output the drive signal to the inverter. According to the wireless power transfer system of the fifth aspect, the switching period of the inverter's switching element can be precisely matched to the resonance period of the power supply unit. Therefore, even when transmitting large amounts of power, it is possible to prevent a decrease in power transfer efficiency due to insufficient precision in inverter drive control. Furthermore, when driving the inverter in the power supply unit, zero-volt switching (ZVS), which is soft switching, can be achieved, significantly reducing power loss due to the inverter's switching operation.

[0134] [Sixth Mode] The sixth mode is provided as a control method for an inverter in a wireless power transfer system including: a power receiving unit having a power receiving-side resonant circuit including a power receiving coil and connected to a load; and a power feeding unit having a power feeding-side resonant circuit including a power feeding coil and feeding power to the power receiving unit through magnetic resonance with the power receiving unit, the power feeding unit having a plurality of switching elements and an inverter that controls the resonant frequency of the power feeding unit by switching the open / closed states of the plurality of switching elements, the power feeding unit and the power receiving unit being configured to preserve PT symmetry. The control method of the fifth mode includes the steps of: acquiring a detection signal representing an input current input from the inverter to the power feeding-side coil while the inverter is operating; inputting to the inverter a drive signal generated so that the open / closed states of the switching elements switch in synchronization with a timing when the input current appearing in the detection signal switches from negative to positive, thereby driving the inverter; and stopping the operation of the inverter when the detection signal indicates the occurrence of an event indicating breaking of the PT symmetry. According to the control method of the sixth aspect, when a detection signal indicating that PT symmetry has been broken is detected during wireless power transfer from the power supply unit to the power receiving unit, the inverter is automatically stopped, thereby preventing a large current from being generated in the power supply unit due to a PT symmetry breaking that occurs during power transfer.

[0135] [7th Mode] The control method of the 6th mode may further include a step of automatically restarting the driving of the inverter when a predetermined time has elapsed after the driving of the inverter has been stopped. According to the control method of the seventh embodiment, if the PT symmetry breaking is resolved while the inverter is stopped, power supply is automatically resumed, thereby improving the operating rate of the wireless power supply system. [Explanation of symbols]

[0136] 10... power receiving unit, 10a... pendulum, 10c... power receiving side resonant circuit, 11... power receiving side coil, 12... power receiving side capacitor, 20... power supply unit, 20A, 20B, 20C, 20D, 20E, 20F, 20G... power supply unit, 20a... pendulum, 20c... power supply side resonant circuit, 21... power supply side coil, 22... power supply side capacitor, 23, 23C, 23D... inverter, 24a... first switch circuit, 24b... second switch circuit, 25f... first switch switching element, 25s...second switching element, 26...gate drive circuit, 26C...gate unit, 29...current detection unit, 30, 30A, 30B, 30C, 30D, 30E, 30F, 30G...drive control unit, 32, 32A, 32G...phase detection unit, 33...first comparator, 34...phase delay unit, 34c...phase delay circuit, 35, 35B, 35C, 35F...break detection unit, 36...second comparator, 37...timer circuit, 38...standby time Control unit, 40, 40C... drive state switching unit, 42... inversion signal element, 45... signal output unit, 46a... first signal inversion element, 46b... second signal inversion element, 46c... third signal inversion element, 47... signal inversion element, 52... stop command unit, 54... frequency determination unit, 100, 100B, 100C, 100D, 100E, 100F, 100G... wireless power supply system, rSdf... drive signal, D1... diode, C1, C2, C3... capacitor R1, R2, R3, R4, R5...resistor, LD...load, IN...input terminal, EN...enable terminal, DS...detection signal, PS...power source, SS...stop signal, NS...normal signal, IT...target current, DT...dead time, Ia...supply current, Ib...received current, Sd...drive signal, Vt...input voltage, It...input current, TS1...first timer signal, TS2...second timer signal, Sd, rSd, Sdf, Sdi, Sds...drive signals

Claims

1. A wireless power supply system, a power receiving unit having a power receiving side resonant circuit including a power receiving side coil and connected to a load; a power supply unit having a power supply side resonant circuit including a power supply side coil, and supplying power to the power receiving unit by magnetic resonance with the power receiving unit; Equipped with The power supply unit and the power receiving unit are configured to preserve PT symmetry, The power supply unit is an inverter having a plurality of switching elements, the inverter controlling the resonance frequency of the power supply unit by switching the open / closed states of the plurality of switching elements in response to an input drive signal; a current detection unit that detects an input current input from the inverter to the power supply side resonant circuit and outputs a detection signal representing the input current; a drive control unit connected to the inverter and the current detection unit, (i) outputting the drive signal generated so that the open / closed state of the switching element is switched in synchronization with the timing at which the input current appearing in the detection signal switches from negative to positive, thereby driving the inverter, and (ii) stopping the driving of the inverter when the detection signal indicating the occurrence of an event that indicates the breaking of the PT symmetry is input from the current detection unit while the inverter is being driven; A wireless power supply system comprising:

2. The wireless power supply system according to claim 1, The drive control unit stops driving the inverter when the detection signal indicating that the input current is greater than a predetermined threshold is input.

3. The wireless power supply system according to claim 1, The drive control unit automatically restarts driving of the inverter when a predetermined time has elapsed since the inverter stopped operating.

4. The wireless power supply system according to claim 1, the drive control unit stops the inverter not only when it detects an event indicating a breaking of the PT symmetry but also when it detects a predetermined event that should stop driving of the inverter during wireless power supply.

5. The wireless power supply system according to any one of claims 1 to 4, the drive control unit includes a phase delay unit that delays the detection signal by a predetermined period, and generates the drive signal using the detection signal whose phase is delayed from the current period by the phase delay unit, and outputs the drive signal to the inverter.

6. a power receiving unit having a power receiving-side resonant circuit including a power receiving-side coil and connected to a load; and a power feeding unit having a power feeding-side resonant circuit including a power feeding-side coil and feeding power to the power receiving unit by magnetic resonance with the power receiving unit, wherein the power feeding unit has a plurality of switching elements and an inverter that controls a resonant frequency of the power feeding unit by switching the open / closed states of the plurality of switching elements, and wherein the power feeding unit and the power receiving unit are configured so that PT symmetry is preserved, the method being executed by the power feeding unit in a wireless power feeding system comprising: acquiring a detection signal representing an input current input from the inverter to the power supply coil while the inverter is operating; a step of inputting a drive signal to the inverter, the drive signal being generated so that the open / closed state of the switching element is switched in synchronization with the timing at which the input current appearing in the detection signal switches from negative to positive, thereby driving the inverter; stopping the inverter when the detection signal indicates that an event indicating breaking of the PT symmetry has occurred; A control method comprising:

7. 7. The control method according to claim 6, further comprising: a step of automatically restarting the driving of the inverter when a predetermined time has elapsed since the driving of the inverter was stopped.

Images