Display device

Abstract

To provide a display device capable of preventing visibility of an image displayed in a display area from being lowered by external light or reducing the lowering of the visibility.SOLUTION: A display device comprises a display panel including a plurality of light-emitting portions arranged in a display area for displaying an image, and an inorganic area arranged in a non-display area around the display area. Each of the plurality of light-emitting portions includes a pixel electrode, a light-emitting layer, and a common electrode that are stacked sequentially. The display panel includes a first side, a second side opposite to the first side, and a third side connected to the first side and the second side. In the non-display area on the first side of the display panel, the common electrode overlaps with the inorganic area, and in the non-display area on the third side of the display panel, the common electrode is spaced from the inorganic area.SELECTED DRAWING: Figure 8

Description

[Technical Field]

[0001] The present invention relates to a display device. [Background technology]

[0002] With the development of an information society, the requirements for display devices for displaying images are becoming increasingly diverse. Display devices can be flat panel display devices such as liquid crystal displays (LCDs), field emission displays (FEDs), light emitting displays (LEMs), etc. Light emitting displays can include organic light emitting displays including organic light emitting elements, inorganic light emitting displays including inorganic light emitting elements such as inorganic semiconductors, and micro-light emitting displays including micro-light emitting elements.

[0003] In recent display devices, the area of ​​the display area where pixels that display images are arranged has been increasing, while the area of ​​the bezel area or dead space area, which corresponds to the non-display area excluding the display area, has been decreasing. As a result, some structures arranged in the non-display area may be exposed without being covered by the light-shielding layer of the cover substrate. In this case, external light may be diffused by some structures arranged in the non-display area, which may reduce the visibility of the image displayed in the display area. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Korean Patent Publication No. 10-2023-0000487 [Patent Document 2] Korean Patent Publication No. 10-2019-0093228 [Patent Document 3] Korean Patent Publication No. 10-2021-0025145 Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the present invention is to provide a display device that can prevent or reduce a decrease in visibility of an image displayed in a display area due to external light.

[0006] The objectives of the present invention are not limited to the technical objectives mentioned above, and other technical objectives not mentioned will be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0007] According to one embodiment of the present invention, a display device includes a display panel including a plurality of light-emitting units arranged in a display area for displaying an image, and an inorganic region arranged in a non-display area around the display area. Each of the plurality of light-emitting units includes a pixel electrode, a light-emitting layer, and a common electrode, which are sequentially stacked. The display panel includes a first side, a second side opposite the first side, and a third side connecting the first side and the second side. In the non-display area of ​​the first side of the display panel, the common electrode overlaps with the inorganic region, and in the non-display area of ​​the third side of the display panel, the common electrode is spaced apart from the inorganic region.

[0008] The display panel may further include a cover substrate disposed on the display panel and including a light-shielding layer, wherein the light-shielding layer overlaps the inorganic region in a non-display region on a first side of the display panel, and the light-shielding layer does not overlap the inorganic region in a non-display region on a third side of the display panel.

[0009] The common electrode may overlap the light-shielding layer in a non-display area on a first side of the display panel, and the common electrode may not overlap the light-shielding layer in a non-display area on a third side of the display panel.

[0010] The display panel may further include a first corner contacting the first side and the third side, and an edge of the common electrode and the inorganic region may intersect with each other in a non-display region of the first corner of the display panel.

[0011] The display panel may further include a first corner contacting the first side and the third side, and an edge of the common electrode may intersect with an edge of the light-shielding layer in a non-display area of ​​the first corner of the display panel.

[0012] The display panel may further include a first corner contacting the first side and the third side, and an edge of the light-blocking layer may intersect with an edge of the inorganic region in a non-display region of the first corner of the display panel.

[0013] The display panel may further include first scan lines extending in a first direction, second scan lines extending in the first direction, a first scan driving circuit disposed in a non-display area on a first side of the display panel and outputting first scan signals to the first scan lines, and a second scan driving circuit disposed in the non-display area on the first side of the display panel and outputting second scan signals to the second scan lines. In the non-display area on the first side of the display panel, the inorganic region may be disposed between the first scan driving circuit and the second scan driving circuit.

[0014] In a non-display area on a first side of the display panel, the common electrode may overlap the first scan driving circuit and the second scan driving circuit.

[0015] In a non-display area on a first side of the display panel, the light-shielding layer may overlap the first scan driving circuit and the second scan driving circuit.

[0016] In the non-display area on the first side of the display panel, the light-shielding layer may overlap the second scan driving circuit but not the first scan driving circuit.

[0017] The display panel may further include third scan lines extending in the first direction, and a third scan driving circuit disposed in a non-display area on a first side of the display panel and outputting third scan signals to the third scan lines. In the non-display area on the first side of the display panel, the third scan driving circuit may be disposed between the first scan driving circuit and the inorganic area.

[0018] In a non-display area on a first side of the display panel, the common electrode may overlap the first scan driving circuit, the second scan driving circuit, and the third scan driving circuit.

[0019] In a non-display area on a first side of the display panel, the light-shielding layer may overlap the first scan driving circuit, the second scan driving circuit, and the third scan driving circuit.

[0020] In the non-display area on the first side of the display panel, the light-shielding layer may overlap the second scan driving circuit and the third scan driving circuit, but may not overlap the first scan driving circuit.

[0021] In the non-display area on the first side of the display panel, the light-shielding layer may overlap the second scan driving circuit but may not overlap the first scan driving circuit and the third scan driving circuit.

[0022] The display panel may further include a first sealing inorganic film disposed on the plurality of light emitting portions, a sealing organic film disposed on the first sealing inorganic film, and a second sealing inorganic film disposed on the sealing organic film.

[0023] The non-display area may further include an inorganic sealing area where the first sealing inorganic film and the second sealing inorganic film are in contact with each other, and the inorganic sealing area may be disposed closer to an edge of the display panel than the inorganic area.

[0024] The display panel may further include a dam disposed in the non-display area for confining the sealing organic film, and the inorganic sealing area may be disposed closer to the dam than the inorganic area.

[0025] According to one embodiment of the present invention, a display device includes a display panel including a plurality of light-emitting units arranged in a display area that displays an image and inorganic regions arranged in a non-display area around the display area, and a cover substrate arranged on the display panel and including a light-shielding layer. Each of the plurality of light-emitting units includes a pixel electrode, a light-emitting layer, and a common electrode, which are sequentially stacked. The display panel includes a first side, a second side opposite the first side, and a third side connecting the first side and the second side. In the non-display area on the first side of the display panel, the common electrode overlaps with the light-shielding layer, and in the non-display area on the third side of the display panel, the common electrode does not overlap with the light-shielding layer.

[0026] In a non-display area on a first side of the display panel, the common electrode may overlap the inorganic area, and in a non-display area on a third side of the display panel, the common electrode may be spaced apart from the inorganic area.

[0027] In a non-display area on a first side of the display panel, the light-shielding layer may overlap with the inorganic area, and in a non-display area on a third side of the display panel, the light-shielding layer may not overlap with the inorganic area.

[0028] According to one embodiment, a display device includes a substrate including a display area and a non-display area disposed around the display area, at least one inorganic film disposed on the substrate, a first organic film disposed on the at least one inorganic film, a second organic film disposed on the first organic film, a pixel electrode disposed on the second organic film in the display area, an emitting layer disposed on the pixel electrode, and a common electrode disposed on the emitting layer, wherein the non-display area includes an inorganic region including a groove penetrating the first organic film and the second organic film, and the common electrode is disposed on the inorganic region of the non-display area on a first side of the substrate, and the common electrode is disposed apart from the inorganic region of the non-display area on a third side adjacent to the first side of the substrate.

[0029] The display device may further include a first sub-power line disposed on the first organic film in the non-display area, and a second sub-power line disposed on the second organic film in the non-display area.

[0030] The first sub-power line and the second sub-power line may be disposed in the groove of the inorganic region, the first sub-power line and the second sub-power line disposed in the groove of the inorganic region of the non-display region on the first side of the substrate may be connected to the common electrode, and the first sub-power line and the second sub-power line disposed in the groove of the inorganic region of the non-display region on the third side of the substrate may be disposed spaced apart from the common electrode.

[0031] The display panel may further include a first power supply connecting electrode disposed on the at least one inorganic film and connected to the first sub-power supply line in the groove of the inorganic region.

[0032] The display device may further include a second power connecting electrode disposed on the at least one inorganic film and connected to the first sub-power line, a first sealing inorganic film disposed on the common electrode, a sealing organic film disposed on the first sealing inorganic film, a second sealing inorganic film disposed on the sealing organic film, and a dam disposed in the non-display area to confine the sealing organic film. The dam may be disposed on the second power connecting electrode.

[0033] The semiconductor device may further include a scan transistor disposed on the substrate and covered by the at least one inorganic film, and the first sub-power line and the second sub-power line may overlap the scan transistor.

[0034] Specific details of other embodiments are included in the detailed description and drawings. [Effects of the Invention]

[0035] In a display device according to an embodiment, in the non-display region on the first side of the display panel, a light-blocking layer disposed on one surface of the cover substrate may overlap with the grooves in the inorganic region, thereby preventing external light from entering the grooves in the inorganic region. This prevents the external light from being unpredictably diffused by the common electrode disposed on the sidewalls of the grooves in the inorganic region, thereby preventing or reducing a decrease in the visibility of images displayed in the display region.

[0036] In addition, in the non-display area on the third side of the display panel, the inorganic area is exposed without being hidden by the light-shielding layer of the cover substrate, but the common electrode is spaced apart from the inorganic area and is not disposed in the groove of the inorganic area. Therefore, even if external light enters the inorganic area, diffused reflection can be reduced or prevented. Therefore, a decrease in visibility of the image displayed in the display area can be prevented or reduced.

[0037] The effects of the embodiments are not limited to the above-mentioned examples, and a wider variety of effects are included in this specification. [Brief explanation of the drawings]

[0038] [Figure 1] 1 is a perspective view illustrating a display device according to an embodiment. [Figure 2] FIG. 2 is a layout diagram illustrating a display panel according to an embodiment. [Figure 3] 1 is a block diagram illustrating a display device according to an embodiment. [Figure 4] FIG. 1 is an equivalent circuit diagram illustrating a sub-pixel according to an embodiment. [Figure 5] FIG. 3 is a layout diagram showing an example of the display area of ​​FIG. 2 in detail. [Figure 6] FIG. 3 is a layout diagram showing an example of the A1 area in FIG. 2 in detail. [Figure 7] FIG. 3 is a layout diagram showing an example of the A1 area in FIG. 2 in detail. [Figure 8] FIG. 3 is a layout diagram showing an example of the A1 area in FIG. 2 in detail. [Figure 9] FIG. 3 is a layout diagram showing an example of the A2 area in FIG. 2 in detail. [Figure 10] FIG. 3 is a layout diagram showing an example of the A2 area in FIG. 2 in detail. [Figure 11] FIG. 3 is a layout diagram showing an example of the A3 area in FIG. 2 in detail. [Figure 12] FIG. 3 is a layout diagram showing an example of the A3 area in FIG. 2 in detail. [Figure 13] FIG. 3 is a layout diagram showing an example of the A3 area in FIG. 2 in detail. [Figure 14] 6 is a cross-sectional view showing an example of a cross section of the display panel corresponding to line I1-I1' in FIG. 5. [Figure 15] 9 is a cross-sectional view showing an example of a cross section of the display panel corresponding to the line I2-I2' in FIGS. 6 to 8. FIG. [Figure 16] 11 is a cross-sectional view showing an example of a cross section of the display panel corresponding to the line I3-I3' in FIGS. 9 and 10. FIG. [Figure 17] 1 is a perspective view illustrating an electronic device to which a display device according to an embodiment is applied; DETAILED DESCRIPTION OF THE INVENTION

[0039] The advantages and features of the present invention, as well as methods for achieving them, will become clearer with reference to the following detailed embodiments in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, and can be realized in various different forms. The present embodiments are provided merely to complete the disclosure of the present invention and to fully convey the scope of the invention to those skilled in the art to which the present invention pertains. The present invention is defined solely by the scope of the claims.

[0040] When elements or layers are referred to as "on" other elements or layers, this includes all cases where other layers or elements are directly on or between the other elements. The same reference numerals refer to the same components throughout the specification. The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments are merely examples, and the present invention is not limited to the details shown.

[0041] The features of the various embodiments of the present invention may be partially or fully combined or combined with each other, and various technical interlocking and driving mechanisms may be possible. Each embodiment may be implemented independently of each other, or may be implemented in conjunction with each other.

[0042] Hereinafter, specific embodiments will be described with reference to the accompanying drawings.

[0043] FIG. 1 is a perspective view showing a display device according to an embodiment.

[0044] Referring to FIG. 1, a display device 10 is a device for displaying moving or still images, and can be used as a display screen for a variety of products, including portable electronic devices such as mobile phones, smartphones, tablet personal computers (PCs), smart watches, watch phones, mobile communication terminals, electronic organizers, e-books, portable multimedia players (PMPs), navigation systems, and ultra-mobile PCs (UMPCs), as well as televisions, notebook computers, monitors, billboards, and Internet of Things (IoT).

[0045] The display device 10 may be an emissive display device such as an organic light emitting display device using organic light emitting diodes, a quantum dot light emitting display device including a quantum dot light emitting layer, an inorganic light emitting display device including an inorganic semiconductor, or a micro- or nano-light emitting display device using a micro- or nano-light emitting diode (micro LED or nano LED). Although the following description focuses on the case where the display device 10 is an organic light emitting display device, the present invention is not limited thereto.

[0046] The display device 10 includes a display panel 110 , a plurality of source driving circuits 200 , a plurality of flexible circuit boards 300 , a timing control circuit 400 , a power supply circuit 500 , and a circuit board 600 .

[0047] The display panel 110 may be formed as a rectangular plane having a long side in a first direction DR1 and a short side in a second direction DR2 intersecting the first direction DR1. The corners where the long side in the first direction DR1 and the short side in the second direction DR2 intersect may be rounded or formed at a right angle to have a predetermined curvature. The planar shape of the display panel 110 is not limited to a rectangle and may be formed as other polygons, circles, or ellipses. The display panel 110 may be formed flat, but is not limited thereto. For example, the display panel 110 may include curved portions formed at the left and right ends, having a constant or variable curvature. In addition, the display panel 110 may be formed to be flexible so that it can be bent, warped, bent, folded, or rolled.

[0048] The display panel 110 may include a display area DA for displaying an image and a non-display area NDA disposed around the display area DA. A substrate (SUB in FIGS. 14 to 17) of the display panel 110 may include the display area DA and the non-display area NDA.

[0049] The display area DA occupies most of the area of ​​the display panel 110. The display area DA may be disposed in the center of the display panel 110. A plurality of pixels (PX in FIG. 5) may be disposed in the display area DA to display an image.

[0050] The non-display area NDA may be an area that does not display an image. The non-display area NDA may be an edge area of ​​the display panel 110. The non-display area NDA may be an area outside the display area DA. The non-display area NDA may be arranged to surround the display area DA.

[0051] Display pads (PD in FIG. 2) may be arranged in the non-display area NDA for connection with a plurality of flexible circuit boards 300. The display pads (PD in FIG. 2) may be arranged on one edge of the display panel 110.

[0052] Each of the source driving circuits 200 may be formed as an integrated circuit (IC) and attached to a corresponding flexible circuit board 300, but the embodiment of the present specification is not limited thereto. Each of the source driving circuits 200 may be attached to the display panel 110 by a chip on glass (COG) method, a chip on plastic (COP) method, or an ultrasonic bonding method.

[0053] Each of the flexible circuit boards 300 may be disposed on a display pad (PD in FIG. 2) disposed on one edge of the display panel 110. Each of the flexible circuit boards 300 may be attached to the display pad (PD in FIG. 2) using a conductive adhesive member such as an anisotropic conductive film. This allows the flexible circuit boards 300 to be electrically connected to signal lines of the display panel 110. The flexible circuit boards 300 may be flexible printed circuit boards or flexible films such as chip-on-film.

[0054] The timing control circuit 400 generates timing control signals for controlling the timing of the scan driving circuits (GDC1 and GDC2 in FIG. 2), the emission driving circuits (EDC1 and EDC2 in FIG. 2), and the source driving circuit 200. The power supply circuit 500 can generate a plurality of power supply voltages for driving the display panel 110 in response to an externally input power source. The timing control circuit 400 and the power supply circuit 500 can each be formed as an integrated circuit (IC) and attached to a circuit board 600.

[0055] The circuit board 600 may be coupled to one side of each of the flexible circuit boards 300. The circuit board 600 may be a rigid printed circuit board.

[0056] FIG. 2 is a layout diagram showing a display panel according to an embodiment.

[0057] Referring to FIG. 2, the display panel 110 includes a display pad PD, a first-side scan driving circuit GDC1, a first-side light-emitting driving circuit EDC1, a second-side scan driving circuit GDC2, a second-side light-emitting driving circuit EDC2, and a dam area DAMA.

[0058] The display pads PD may be arranged on one edge of the display panel 110. The display pads PD may be divided into a plurality of groups. If the display device 10 includes five flexible circuit boards 300 as shown in FIG. 1, the display pads PD may be divided into five groups. The display pads PD in each of the plurality of groups correspond one-to-one to the bumps of the corresponding flexible circuit board 300. Therefore, the display pads PD in each of the plurality of groups may be electrically connected to the corresponding flexible circuit board 300.

[0059] Some of the display pads PD may be electrically connected to data lines (DL in FIG. 3) arranged in the display area DA. Other of the display pads PD may be electrically connected to the first-side scan driving circuit GDC1, the second-side scan driving circuit GDC2, the first-side light-emitting driving circuit EDC1, and the second-side light-emitting driving circuit EDC2. Other of the display pads PD may be connected to a first power line (VSL1 in FIG. 15) to which a first power supply voltage is applied.

[0060] The first power line (VSL1 in FIG. 15) may be arranged to surround at least three sides of the display area DA. For example, the first power line (VSL1 in FIG. 15) may be arranged to surround the left, top, and right sides of the display area DA. Alternatively, the first power line (VSL1 in FIG. 15) may be arranged to surround the left, top, right, and bottom sides of the display area DA.

[0061] The first-side scan driving circuit GDC1 and the second-side scan driving circuit GDC2 may be electrically connected to the scan lines (SL in FIG. 3) of the display area DA. The first-side scan driving circuit GDC1 may be arranged in the non-display area NDA on the first side (e.g., the left side) of the display panel 110. The second-side scan driving circuit GDC2 may be arranged in the non-display area NDA on the second side (e.g., the right side) of the display panel 110.

[0062] The first-side light-emitting drive circuit EDC1 and the second-side light-emitting drive circuit EDC2 may be electrically connected to the light-emitting control lines (EML in FIG. 3) of the display area DA. The first-side light-emitting drive circuit EDC1 may be disposed in the non-display area NDA on a first side (e.g., the left side) of the display panel 110. The second-side light-emitting drive circuit EDC2 may be disposed in the non-display area NDA on a second side (e.g., the right side) of the display panel 110.

[0063] The first-side scan driving circuit GDC1 may be disposed between the display area DA and the first-side light-emitting driving circuit EDC1. The first-side scan driving circuit GDC1 may be disposed closer to the display area DA than the first-side light-emitting driving circuit EDC1. In addition, the first-side light-emitting driving circuit EDC1 may be disposed closer to the edge of the first side of the display panel 110 than the first-side scan driving circuit GDC1.

[0064] The second-side scan driving circuit GDC2 may be disposed between the display area DA and the second-side light-emitting driving circuit EDC2. The second-side scan driving circuit GDC2 may be disposed closer to the display area DA than the second-side light-emitting driving circuit EDC2. In addition, the second-side light-emitting driving circuit EDC2 may be disposed closer to the edge of the second side of the display panel 110 than the second-side scan driving circuit GDC2.

[0065] The dam region DAMA includes at least one dam (DAM1, DAM2 in FIG. 15) for preventing the sealing organic film (TFE2 in FIG. 15) from overflowing onto the display pad PD. The dam region DAMA may be arranged to surround the display region DA.

[0066] The dam area DAMA may be disposed outside the first-side light-emitting drive circuit EDC1 and outside the second-side light-emitting drive circuit EDC2. The dam area DAMA may be disposed closer to the edge of the first side of the display panel 110 than the first-side light-emitting drive circuit EDC1. Also, the dam area DAMA may be disposed closer to the edge of the second side of the display panel 110 than the second-side light-emitting drive circuit EDC2.

[0067] FIG. 3 is a block diagram showing a display device according to an embodiment.

[0068] Referring to FIG. 3, the display area DA includes a plurality of sub-pixels SPX, a plurality of scan lines SL, a plurality of light emitting control lines EML, and a plurality of data lines DL.

[0069] The pixels PX may be arranged in a matrix in a first direction DR1 and a second direction DR2. The scan lines SL and the emission control lines EML may extend in the first direction DR1 and be arranged in the second direction DR2. The data lines DL may extend in the second direction DR2 and be arranged in the first direction DR1. The scan lines SL include write scan lines GWL, control scan lines GCL, initialization scan lines GIL, and bias scan lines GBL.

[0070] Each of the plurality of sub-pixels SPX may be connected to one of the plurality of write scan lines GWL, one of the plurality of control scan lines GCL, one of the plurality of initialization scan lines GIL, one of the plurality of bias scan lines GBL, one of the plurality of emission control lines EML, and one of the plurality of data lines DL. Each of the plurality of sub-pixels SPX receives a data voltage on the data line DL in response to a write scan signal on the write scan line GWL, and can emit light emitting elements in response to the data voltage.

[0071] The non-display area NDA includes a first-side scan driving circuit GDC1, a second-side scan driving circuit GDC2, a first-side light-emitting driving circuit EDC1, and a second-side light-emitting driving circuit EDC2.

[0072] Each of the first-side scan drive circuit GDC1 and the second-side scan drive circuit GDC2 may include a write scan drive circuit GWC, a control scan drive circuit GCC, an initialization scan drive circuit GIC, and a bias scan drive circuit GBC. While Fig. 3 illustrates an example in which the write scan drive circuit GWC, the control scan drive circuit GCC, the initialization scan drive circuit GIC, and the bias scan drive circuit GBC are arranged in this order from the display area DA to the edge of the display panel 110, the embodiment of the present specification is not limited to this. That is, for example, the order in which the write scan drive circuit GWC, the control scan drive circuit GCC, the initialization scan drive circuit GIC, and the bias scan drive circuit GBC are arranged in the non-display area NDA does not matter as long as they are arranged in the non-display area NDA.

[0073] The write scan drive circuit GWC can receive a write timing signal GWTS as an input from the timing control circuit 400. The write scan drive circuit GWC can generate write scan signals in response to the write timing signal GWTS and sequentially output them to the write scan lines GWL.

[0074] The control scan driver circuit GCC can receive a control timing signal GCTS as an input from the timing control circuit 400. The control scan driver circuit GCC can generate control scan signals in response to the control timing signal GCTS and sequentially output them to the control scan lines GCL.

[0075] The initialization scan driving circuit GIC may receive an initialization timing signal GITS from the timing control circuit 400. The initialization scan driving circuit GIC may generate initialization scan signals in response to the initialization timing signal GITS and sequentially output the generated initialization scan signals to the initialization scan lines GIL.

[0076] The bias scan drive circuit GBC can receive a bias timing signal GBTS as an input from the timing control circuit 400. The bias scan drive circuit GBC can generate a bias scan signal in response to the bias timing signal GBTS and sequentially output it to the bias scan lines GBL.

[0077] The first-side light-emitting drive circuit EDC1 and the second-side light-emitting drive circuit EDC2 can each receive a light-emitting timing signal EMTS from the timing control circuit 400. The first-side light-emitting drive circuit EDC1 and the second-side light-emitting drive circuit EDC2 can each generate a light-emitting control signal in response to the light-emitting timing signal EMTS and sequentially output the signal to the light-emitting control line EML.

[0078] The data driving circuit 200G includes a plurality of source driving circuits 200. Each of the plurality of source driving circuits 200 receives digital video data DATA and a data timing signal DCS from the timing control circuit 400. Each of the plurality of source driving circuits 200 converts the digital video data DATA into an analog data voltage in response to the data timing signal DCS and outputs the analog data voltage to a data line DL. In this case, a desired subpixel SPX can be selected from the plurality of subpixels SPX by a write scan signal, and a data voltage can be supplied to the selected subpixel SPX.

[0079] The timing control circuit 400 may receive digital video data DATA and a timing signal TS (not shown) from an external device. The timing control circuit 400 generates a write timing signal GWTS, a control timing signal GCTS, an initialization timing signal GITS, a bias timing signal GBTS, and an emission timing signal EMTS in response to the timing signal TS. The timing control circuit 400 may output the write timing signal GWTS to the write scan driving circuit GWC and the control timing signal GCTS to the control scan driving circuit GCC. The timing control circuit 400 may also output the initialization timing signal GITS to the initialization scan driving circuit GIC and the bias timing signal GBTS to the bias scan driving circuit GBC. The timing control circuit 400 may also output the emission timing signal EMTS to the first light-emitting driving circuit EDC1 and the second light-emitting driving circuit EDC2. The timing control circuit 400 may also output the digital video data DATA and a data timing signal DCS to the source driving circuit 200. The data timing signal DCS may be generated in response to the timing signal TS.

[0080] The power supply circuit 500 generates a plurality of panel driving voltages in response to an external power supply voltage. For example, the power supply circuit 500 may generate a first power supply voltage VSS, a second power supply voltage VDD, a third power supply voltage VINT, a fourth power supply voltage VAINT, and a fifth power supply voltage VOB and supply them to the display panel 110. The first power supply voltage VSS may be a low potential voltage, and the second power supply voltage VDD may be a high potential voltage. The third power supply voltage VINT may be a first initialization voltage, the fourth power supply voltage VAINT may be a second initialization voltage, and the fifth power supply voltage VOB may be a third initialization voltage. The third power supply voltage VINT, the fourth power supply voltage VAINT, and the fifth power supply voltage VOB may be higher than the first power supply voltage VSS and lower than the second power supply voltage VDD.

[0081] FIG. 4 is an equivalent circuit diagram showing a sub-pixel according to an embodiment.

[0082] Referring to FIG. 4, the sub-pixel SPX according to an embodiment may be connected to a write scan line GWL, an initialization scan line GIL, a control scan line GCL, a bias scan line GBL, an emission control line EML, and a data line DL.

[0083] The sub-pixel SPX according to an embodiment includes a driving transistor DT, a switching element, a capacitor Cst, and a light-emitting element LE. The switching element includes first to seventh transistors T1, T2, T3, T4, T5, T6, and T7.

[0084] The driving transistor DT controls a current between its source and drain (hereinafter referred to as a "driving current") in response to a data voltage applied to its first electrode. A first gate electrode of the driving transistor DT may be connected to a second power line VDL to which a second power voltage (VDD in FIG. 3) is applied via a capacitor Cst. A second gate electrode (a back gate electrode in the example of FIG. 4) of the driving transistor DT may be connected to the second power line VDL to which a second power voltage (VDD in FIG. 3) is applied.

[0085] The light emitting element LE may be an organic light emitting diode. The light emitting element LE emits light in response to a driving current. The amount of light emitted by the light emitting element LE is proportional to the driving current. A first electrode of the light emitting element LE may be connected to a second electrode of the fifth transistor T5 and a first electrode of the sixth transistor T6. A second electrode of the light emitting element LE may be connected to a first power line VSL1 to which a first power voltage is applied. The first electrode of the light emitting element LE may be an anode electrode or a pixel electrode, and the second electrode may be a cathode electrode or a common electrode.

[0086] The first transistor T1 is turned on by a write scan signal of a gate-on voltage applied to the write scan line GWL to connect the data line DL to the first electrode of the drive transistor DT. Thus, a data voltage can be applied to the first electrode of the drive transistor DT during the period when the first transistor T1 is turned on. The gate electrode of the first transistor T1 may be connected to the write scan line GWL, the first electrode may be connected to the data line DL, and the second electrode may be connected to the first electrode of the drive transistor DT.

[0087] The second transistor T2 is turned on by a control scan signal of a gate-on voltage applied to the control scan line GCL to connect the first gate electrode and the second electrode of the drive transistor DT. During the period when the second transistor T2 is turned on, the drive transistor DT can operate like a diode. The gate electrode of the second transistor T2 can be connected to the control scan line GCL, the first electrode can be connected to the second electrode of the drive transistor DT, and the second electrode can be connected to the first gate electrode of the drive transistor DT.

[0088] The third transistor T3 is turned on by an initialization scan signal of a gate-on voltage applied to the initialization scan line GIL to connect the first gate electrode of the driving transistor DT to the third power line VIL. During the period in which the third transistor T3 is turned on, the first gate electrode of the driving transistor DT may be initialized to the third power supply voltage (VINT in FIG. 3) of the third power line VIL. The gate electrode of the third transistor T3 may be connected to the initialization scan line GIL, the first electrode may be connected to the first gate electrode of the driving transistor DT, and the second electrode may be connected to the third power line VIL.

[0089] The fourth transistor T4 is turned on by an emission control signal of a gate-on voltage applied to the emission control line EML to connect the second power line VDL to the first electrode of the drive transistor DT. While the fourth transistor T4 is turned on, the second power supply voltage (VDD in FIG. 3) of the second power line VDL may be applied to the first electrode of the drive transistor DT. The gate electrode of the fourth transistor T4 may be connected to the emission control line EML, the first electrode may be connected to the second power line VDL, and the second electrode may be connected to the first electrode of the drive transistor DT.

[0090] The fifth transistor T5 is turned on by an emission control signal of a gate-on voltage applied to the emission control line EML to connect the second electrode of the driving transistor DT to the first electrode of the light-emitting element LE. During the period when the fifth transistor T5 is turned on, the driving current of the driving transistor DT can be supplied to the light-emitting element LE. The gate electrode of the fifth transistor T5 can be connected to the emission control line EML, the first electrode can be connected to the second electrode of the driving transistor DT, and the second electrode can be connected to the first electrode of the light-emitting element LE.

[0091] The sixth transistor T6 is turned on by a bias scan signal of a gate-on voltage applied to the bias scan line GBL to connect the first electrode of the light emitting element LE to the fourth power line VAIL. During the period when the sixth transistor T6 is turned on, the first electrode of the light emitting element LE may be initialized to the fourth power supply voltage (VAINT in FIG. 3) of the fourth power line VAIL. The gate electrode of the sixth transistor T6 may be connected to the bias scan line GBL, the first electrode may be connected to the first electrode of the light emitting element LE, and the second electrode may be connected to the fourth power line VAIL.

[0092] The seventh transistor T7 is turned on by a bias scan signal of a gate-on voltage applied to the bias scan line GBL to connect the first electrode of the driving transistor DT to the fifth power line VOBL. While the seventh transistor T7 is turned on, the first electrode of the driving transistor DT may be initialized to the fifth power voltage (VOB in FIG. 3) of the fifth power line VOBL. The gate electrode of the seventh transistor T7 may be connected to the bias scan line GBL, the first electrode may be connected to the first electrode of the driving transistor DT, and the second electrode may be connected to the fifth power line VOBL.

[0093] The capacitor Cst is formed between the first gate electrode of the driving transistor DT and the second power supply line VDL, and one electrode of the capacitor Cst may be connected to the first gate electrode of the driving transistor DT and the other electrode may be connected to the second power supply line VDL.

[0094] The drive transistor DT, the first transistor T1, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be formed as p-type metal oxide semiconductor field effect transistors (MOSFETs). In this case, the active layers of the drive transistor DT, the first transistor T1, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be formed of polysilicon. The drive transistor DT, the first transistor T1, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be turned on by a gate low voltage signal.

[0095] The second transistor T2 and the third transistor T3 may be formed as n-type metal oxide semiconductor field effect transistors. In this case, the active layers of the second transistor T2 and the third transistor T3 may be formed of oxide semiconductors. The second transistor T2 and the third transistor T3 may be turned on by a gate high voltage signal. Whether the transistors T1 to T7 and DT are formed as n-type or p-type transistors is not necessarily limited to the above. For example, the transistors may be formed as n-type or p-type transistors depending on the voltage applied to the transistors, the driving method, etc.

[0096] FIG. 5 is a layout diagram showing an example of the display area of ​​FIG. 2 in detail.

[0097] 5, the pixels PX may be arranged in a matrix, and each of the pixels PX may include a first light-emitting portion ELU1 of a first sub-pixel SPX1, a second light-emitting portion ELU2 of a second sub-pixel SPX2, and a third light-emitting portion ELU3 of a third sub-pixel SPX3.

[0098] In each of the plurality of pixels PX, the first light-emitting unit ELU1, the second light-emitting unit ELU2, and the third light-emitting unit ELU3 may be arranged in a stripe pattern. For example, in each of the plurality of pixels PX, the first light-emitting unit ELU1, the second light-emitting unit ELU2, and the third light-emitting unit ELU3 may be arranged in a first direction DR1. In the example of Fig. 5, each of the light-emitting units ELU1, ELU2, and ELU3 has a rectangular shape with long sides along the second direction DR2 and short sides along the first direction DR1, and is arranged in a matrix pattern along the first direction DR1 and the second direction DR2.

[0099] The first light-emitting unit ELU1 emits a first light, the second light-emitting unit ELU2 emits a second light, and the third light-emitting unit ELU3 emits a third light. Here, the first light may be light in the blue wavelength band, the second light may be light in the green wavelength band, and the third light may be light in the red wavelength band. For example, the blue wavelength band refers to light whose main peak wavelength is in the wavelength band of approximately 370 nm to 460 nm, the green wavelength band refers to light whose main peak wavelength is in the wavelength band of approximately 480 nm to 560 nm, and the red wavelength band refers to light whose main peak wavelength is in the wavelength band of approximately 600 nm to 750 nm.

[0100] Although FIG. 5 illustrates an example in which each of the plurality of pixels PX includes three light-emitting units ELU1, ELU2, and ELU3, embodiments of the present specification are not limited thereto. For example, each of the plurality of pixels PX may include four light-emitting units. In this case, the first light-emitting unit may emit a first light, the second and fourth light-emitting units may emit a second light, and the third light-emitting unit may emit a third light. Alternatively, the first light-emitting unit may emit a first light, the second light-emitting unit may emit a second light, the third light-emitting unit may emit a third light, and the fourth light-emitting unit may emit a fourth light. The fourth light may be white light. Furthermore, in each of the plurality of pixels PX, the first, second, third, and fourth light-emitting units may be arranged in a stripe pattern or a Pentile (registered trademark) pattern.

[0101] 6 to 8 are layout diagrams showing an example of the A1 area in FIG. 2 in detail.

[0102] 6 to 8 are layout diagrams showing in detail the non-display area NDA arranged on the left side of the display panel 110, which corresponds to the first side of the display panel 110. Fig. 7 is a diagram showing Fig. 6 in addition to the common electrode CE, and Fig. 8 is a diagram showing Fig. 7 in addition to the light-shielding layer BM.

[0103] 6 to 8, the first-side scan driving circuit GDC1, the first-side light-emitting driving circuit EDC1, the inorganic area VAL, and the dam area DAMA may be disposed in the non-display area NDA on the first side of the display panel 110.

[0104] The first-side scan drive circuit GDC1 may include a write scan drive circuit GWC, a control scan drive circuit GCC, an initialization scan drive circuit GIC, and a bias scan drive circuit GBC. The write scan drive circuit GWC, the control scan drive circuit GCC, the initialization scan drive circuit GIC, and the bias scan drive circuit GBC may be arranged in this order from the display area DA along the edge EG1 of the first side of the display panel 110. For example, in the example of FIG. 7 etc., the write scan drive circuit GWC may be arranged closest to the display area DA, and the bias scan drive circuit GBC may be arranged closest to the edge EG1 of the first side of the display panel 110. Furthermore, the control scan drive circuit GCC may be arranged closer to the write scan drive circuit GWC than the initialization scan drive circuit GIC. Furthermore, the initialization scan drive circuit GIC may be arranged closer to the bias scan drive circuit GBC than the control scan drive circuit GCC.

[0105] The write scan drive circuit GWC includes a plurality of write scan stages (GWST in FIGS. 6 to 8). In the non-display area NDA on the first side of the display panel 110, the plurality of write scan stages GWST may be arranged in the second direction DR2. The plurality of write scan stages GWST are connected in a cascade manner and driven sequentially along the second direction DR2, thereby sequentially outputting write scan signals to write scan lines (GWL in FIG. 3). Each of the plurality of write scan stages GWST may output a write scan signal to the write scan line (GWL in FIG. 3) connected thereto. For this purpose, the plurality of write scan stages GWST may include a plurality of write scan transistors (GWT in FIG. 15).

[0106] The control scan drive circuit GCC includes a plurality of control scan stages GCST. The control scan stages GCST may be arranged in a second direction DR2 in the non-display area NDA on the first side of the display panel 110. The control scan stages GCST are connected in a cascade manner and driven sequentially in the second direction DR2, thereby sequentially outputting control scan signals to control scan lines (GCL in FIG. 3). Each of the control scan stages GCST may output a control scan signal to the control scan line (GCL in FIG. 3) connected thereto. For this purpose, the control scan drive circuit GCC may include a plurality of control scan transistors (GCT in FIG. 15).

[0107] The initialization scan driving circuit GIC includes a plurality of initialization scan stages GIST. The plurality of initialization scan stages GIST may be arranged in the second direction DR2 in the non-display area NDA on the first side of the display panel 110. The plurality of initialization scan stages GIST are connected in a cascade manner and driven sequentially along the second direction DR2, thereby sequentially outputting initialization scan signals to initialization scan lines (GIL in FIG. 3). Each of the plurality of initialization scan stages GIST may output an initialization scan signal to the initialization scan line (GIL in FIG. 3) connected thereto. For this purpose, the initialization scan driving circuit GIC may include a plurality of initialization scan transistors (GIT in FIG. 15).

[0108] The bias scan driving circuit GBC includes a plurality of bias scan stages GBST. The plurality of bias scan stages GBST may be arranged in a second direction DR2 in the non-display area NDA on the first side of the display panel 110. The plurality of bias scan stages GBST are connected in a cascade manner and driven sequentially in the second direction DR2, thereby sequentially outputting bias scan signals to bias scan lines (GBL in FIG. 3). Each of the plurality of bias scan stages GBST may output a bias scan signal to the bias scan line (GBL in FIG. 3) connected thereto. For this purpose, the bias scan driving circuit GBC may include a plurality of bias scan transistors (GBT in FIG. 15).

[0109] The first-side light-emitting drive circuit EDC1 includes a plurality of light-emitting stages EST. The plurality of light-emitting stages EST may be arranged in a second direction DR2 in the non-display area NDA on the first side of the display panel 110. The plurality of light-emitting stages EST are connected in a cascade manner and driven sequentially in the second direction DR2, thereby sequentially outputting light-emitting control signals to light-emitting control lines (EML in FIG. 3). Each of the plurality of light-emitting stages EST may output a light-emitting control signal to the light-emitting control line (EML in FIG. 3) connected thereto. For this purpose, the light-emitting stages EST may include a plurality of light-emitting control transistors (ECT in FIG. 15).

[0110] The dam area DAMA may be disposed outside the first side light-emitting driving circuit EDC1 and may be disposed closer to the edge EG1 of the first side of the display panel 110 than the first side light-emitting driving circuit EDC1.

[0111] The dam area DAMA includes a first dam DAM1 and a second dam DAM2. In the non-display area NDA on the first side of the display panel 110, the first dam DAM1 and the second dam DAM2 may each extend in a second direction DR2.

[0112] The first dam DAM1 may be disposed outside the first side light-emitting drive circuit EDC1, and the second dam DAM2 may be disposed outside the first dam DAM1. The first dam DAM1 may be disposed between the first side light-emitting drive circuit EDC1 and the second dam DAM2. The second dam DAM2 may be disposed closer to the edge EG1 of the first side of the display panel 110 than the first dam DAM1.

[0113] 6 to 8 illustrate an example in which the dam region DAMA includes two dams DAM1 and DAM2, but the number of dams in the dam region DAMA is not limited to that in the embodiments of this specification. For example, the dam region DAMA may include one dam DAM or three or more dams DAM as long as it can confine the sealing organic film TFE2 and prevent the sealing organic film TFE2 from overflowing to the outer edge (e.g., the edge EG1 on the first side) of the display panel 110.

[0114] The inorganic region VAL may be a region where an organic film (160, 180 in FIGS. 14 to 16) adjacent to an edge EG1 of the first side of the display panel 110 is removed and an inorganic film is disposed therein to prevent oxygen or moisture from penetrating into the display area DA through the organic film (160, 180 in FIGS. 14 to 16). The inorganic region VAL may extend along the second direction DR2 in the non-display area NDA of the first side of the display panel 110.

[0115] The inorganic region VAL may be disposed between any two adjacent drive circuits among the write scan drive circuit GWC, the control scan drive circuit GCC, the initialization scan drive circuit GIC, and the bias scan drive circuit GBC of the first-side scan drive circuit GDC1. For example, in the example of Figure 6, the inorganic region VAL may be disposed between the adjacent control scan drive circuit GCC and initialization scan drive circuit GIC. In this case, the inorganic region VAL may be disposed between the control scan stage GCST and the initialization scan stage GIST.

[0116] However, the arrangement position of the inorganic region VAL in the embodiments of this specification is not limited to that shown in Figure 6. For example, the inorganic region VAL may be arranged between the adjacent write scan drive circuit GWC and control scan drive circuit GCC. In this case, the inorganic region VAL may be arranged between the write scan stage GWST and the control scan stage GCST.

[0117] Alternatively, the inorganic region VAL may be disposed between the initialization scan drive circuit GIC and the bias scan drive circuit GBC, which are adjacent to each other. In this case, the inorganic region VAL may be disposed between the initialization scan stage GIST and the bias scan stage GBST.

[0118] Alternatively, the inorganic region VAL may be disposed between the bias scan driving circuit GBC and the first side light emission driving circuit EDC1, in which case it may be disposed between the bias scan stage GBST and the light emission stage EST.

[0119] The inorganic region VAL may include a groove (Gval in FIGS. 15 and 16) where an organic film (160, 180 in FIGS. 14 to 16) has been removed. The groove (Gval in FIGS. 15 and 16) of the inorganic region VAL may have a cross-sectional shape that is dug in a V-shape like a valley in the example of FIG. 15 etc.

[0120] 7, the common electrode CE may be disposed over the entire display area DA. In the non-display area NDA on the first side of the display panel 110, the common electrode CE may overlap the write scan drive circuit GWC, the control scan drive circuit GCC, and the initialization scan drive circuit GIC of the first-side scan drive circuit GDC1. In the non-display area NDA on the first side of the display panel 110, the common electrode CE may overlap the inorganic area VAL.

[0121] In the non-display area NDA on the first side of the display panel 110, the common electrode CE may not overlap the bias scan drive circuit GBC of the first-side scan drive circuit GDC1 and the first-side light-emitting drive circuit EDC1, as shown in FIG. 7 , but the embodiments of this specification are not limited to this. That is, as long as the common electrode CE overlaps the inorganic region VAL in the non-display area NDA on the first side of the display panel 110, it does not matter whether the common electrode CE overlaps any of the drive circuits, including the scan drive circuit GWC, the control scan drive circuit GCC, the initialization scan drive circuit GIC, the bias scan drive circuit GBC, and the first-side light-emitting drive circuit EDC1. For example, in the non-display area NDA on the first side of the display panel 110, the common electrode CE may overlap the bias scan drive circuit GBC of the first-side scan drive circuit GDC1 in a continuous manner from the display area DA. Also, in the non-display area NDA on the first side of the display panel 110, the common electrode CE may overlap the first-side light-emitting drive circuit EDC1 in a continuous manner from the display area DA.

[0122] 8, in the non-display area NDA on the first side of the display panel 110, the light-shielding layer BM of the cover substrate (CSUB in FIGS. 14 to 16) may overlap the dam area DAMA, the first-side emission drive circuit EDC1, the bias scan drive circuit GBC of the first-side scan drive circuit GDC1, and the initialization scan drive circuit GIC. In the non-display area NDA on the first side of the display panel 110, the light-shielding layer BM of the cover substrate (CSUB in FIGS. 14 to 16) may overlap the inorganic area VAL.

[0123] In the non-display area NDA on the first side of the display panel 110, the light-shielding layer BM of the cover substrate (CSUB in FIGS. 14 to 16) may overlap with the control scan drive circuit GCC of the first-side scan drive circuit GDC1 as shown in FIG. 8, but the embodiments of this specification are not limited to this. In other words, as long as the light-shielding layer BM overlaps with the inorganic region VAL in the non-display area NDA on the first side of the display panel 110, it does not matter whether the light-shielding layer BM overlaps with any of the drive circuits, including the scan drive circuit GWC, the control scan drive circuit GCC, the initialization scan drive circuit GIC, the bias scan drive circuit GBC, and the first-side emission drive circuit EDC1. For example, in the non-display area NDA on the first side of the display panel 110, the light-shielding layer BM of the cover substrate (CSUB in FIGS. 14 to 16) is arranged from the edge of the non-display area NDA toward the display area DA as shown in FIG. 8, but does not have to overlap with the control scan drive circuit GCC of the first-side scan drive circuit GDC1. In the example of FIG. 8, the light-shielding layer BM overlaps a part of the control scan drive circuit GCC, but does not overlap the remaining part.

[0124] Furthermore, in the non-display area NDA on the first side of the display panel 110, the light-shielding layer BM of the cover substrate (CSUB in FIGS. 14 to 16) may not overlap with the write scan drive circuit GWC of the first-side scan drive circuit GDC1 as in FIG. 8, but the embodiments of the present specification are not limited to this. For example, in the non-display area NDA on the first side of the display panel 110, the light-shielding layer BM of the cover substrate (CSUB in FIGS. 14 to 16) may overlap with the write scan drive circuit GWC of the first-side scan drive circuit GDC1.

[0125] In the non-display area NDA on the first side of the display panel 110, the common electrode CE overlaps with the inorganic region VAL, and therefore may be disposed in a groove (Gval in FIGS. 15 and 16) where an organic film (160, 180 in FIGS. 14 to 16) has been removed. The groove (Gval in FIGS. 15 and 16) in the organic film (160, 180 in FIGS. 14 to 16) has a cross-sectional shape that is, for example, V-shaped, like a valley. Therefore, when external light is incident on the common electrode CE disposed in the groove (Gval in FIGS. 15 and 16), it may be diffusely reflected in an unpredictable manner. In other words, the groove (Gval in FIGS. 15 and 16) in the organic film (160, 180 in FIGS. 14 to 16) is shaped to diffusely reflect light when it is incident on the common electrode CE disposed in the groove.

[0126] In the embodiment of the present specification, in the non-display area NDA on the first side of the display panel 110, the light-shielding layer BM of the cover substrate (CSUB in FIGS. 14 to 16) overlaps with the inorganic area VAL, thereby blocking external light from entering the common electrode CE arranged in the groove (Gval in FIGS. 15 and 16) of the inorganic area VAL. Therefore, it is possible to prevent or reduce a decrease in the visibility of the image displayed in the display area due to unpredictable diffuse reflection of external light incident on the common electrode CE arranged in the groove (Gval in FIGS. 15 and 16) of the inorganic area VAL.

[0127] The A4 area shown in Figure 2 is substantially the same as the description of the A1 area shown in Figures 6 to 8, except that the first-side scan driving circuit GDC1 and the first-side light-emitting driving circuit EDC1 are replaced with the second-side scan driving circuit GDC2 and the second-side light-emitting driving circuit EDC2, and is bilaterally symmetrical with the A1 area shown in Figures 6 to 8. Therefore, the description of the A4 area shown in Figure 2 will be omitted.

[0128] 9 and 10 are layout diagrams showing an example of the A2 area in FIG. 2 in detail.

[0129] 9 and 10 are layout diagrams showing in detail the non-display area NDA arranged on the upper side (third side) of the display panel 110, which corresponds to the second side of the display panel 110. FIG. 10 is a diagram further showing the light-shielding layer BM in FIG. 9.

[0130] 9 and 10 , the inorganic area VAL and the dam area DAMA may be disposed in the non-display area NDA on the third side of the display panel 110. The first-side scan driving circuit GDC1 and the first-side light-emitting driving circuit EDC1 do not have to be disposed in the non-display area NDA on the third side of the display panel 110.

[0131] The dam region DAMA may be disposed outside the inorganic region VAL. The distance between the dam region DAMA and the inorganic region VAL may be greater than the distance between the dam region DAMA and the edge EG2 on the third side of the display panel 110. More specifically, the distance between the end of the dam region DAMA on the display region DA side in the second direction DR2 and the end of the inorganic region VAL away from the display region DA in the second direction DR2 may be greater than the distance between the end of the dam region DAMA on the side away from the display region DA in the second direction DR2 and the edge EG2 on the third side of the display panel 110.

[0132] In the non-display area NDA on the third side of the display panel 110, the first dam DAM1 and the second dam DAM2 of the dam area DAMA may each extend in the first direction DR1.

[0133] The first dam DAM1 may be disposed outside the inorganic region VAL, and the second dam DAM2 may be disposed outside the first dam DAM1. The first dam DAM1 may be disposed between the inorganic region VAL and the second dam DAM2. The second dam DAM2 may be disposed closer to the edge EG2 of the second side of the display panel 110 than the first dam DAM1. The dam region DAMA may overlap the light-shielding layer BM of the cover substrate (CSUB in FIGS. 14 to 16) as shown in FIG. 10.

[0134] Although the dam area DAMA includes two dams DAM1 and DAM2 in the examples shown in FIGS. 9 and 10, the number of dams in the dam area DAMA is not limited to the number in the embodiments of this specification, as described above.

[0135] In the non-display area NDA on the third side of the display panel 110, the inorganic area VAL may extend in the first direction DR1. The inorganic area VAL may be disposed between the dam area DAMA and the display area DA. In the non-display area NDA on the third side of the display panel 110, the inorganic area VAL may not overlap with the common electrode CE as shown in FIG. 9. In the non-display area NDA on the third side of the display panel 110, the inorganic area VAL may be disposed spaced apart from the common electrode CE as shown in FIG. 9.

[0136] In the non-display area NDA on the third side of the display panel 110, the inorganic area VAL does not need to overlap the light-shielding layer BM of the cover substrate (CSUB in FIGS. 14 to 16) as shown in FIG.

[0137] A distance DIS1 (FIG. 8) between the display area DA and the light-shielding layer BM of the cover substrate (CSUB in FIGS. 14 to 16) in the non-display area NDA on the first side of the display panel 110 may be substantially the same as a distance DIS3 (FIG. 10) between the display area DA and the light-shielding layer BM of the cover substrate (CSUB in FIGS. 14 to 16) in the non-display area NDA on the third side of the display panel 110. In comparison, a distance DIS2 (FIG. 8) between the inorganic area VAL in the non-display area NDA on the first side of the display panel 110 and the edge EG1 of the display panel 110 may be greater than a distance DIS4 (FIG. 10) between the inorganic area VAL in the non-display area NDA on the third side of the display panel 110 and the edge EG2 of the display panel 110.

[0138] In summary, the distance from the light-shielding layer BM to the display area DA is designed to be the same in both the non-display area NDA on the first side of the display panel 110 and the non-display area NDA on the third side of the display panel 110. However, because the scan driving circuit and the light-emitting driving circuit are not disposed in the non-display area NDA on the third side of the display panel 110, the width of the non-display area NDA on the third side of the display panel 110 is narrower than the width of the non-display area NDA on the first side of the display panel 110. As a result, in the non-display area NDA on the third side of the display panel 110, the inorganic area VAL is disposed adjacent to the edge EG2 of the display panel 110, so that the inorganic area VAL can be exposed without overlapping with the light-shielding layer BM of the cover substrate (CSUB in FIGS. 14 to 16). However, because the common electrode CE does not overlap with the inorganic area VAL, it is not disposed in the groove (Gval in FIGS. 15 and 16) of the inorganic area VAL. Therefore, diffuse reflection can be reduced or prevented even when external light is incident on the inorganic area VAL. This can prevent or mitigate degradation in the visibility of the image displayed in the display area DA.

[0139] The A5 area shown in Fig. 2 is substantially the same as the A2 area shown in Fig. 9 and Fig. 10. Therefore, a description of the A5 area shown in Fig. 2 will be omitted.

[0140] 11 to 13 are layout diagrams showing an example of the A3 area in FIG. 2 in detail.

[0141] 11 to 13 are layout diagrams showing in detail the non-display area NDA arranged in the first corner of the display panel 110 where the first side and the third side of the display panel 110 meet. Fig. 12 is a diagram showing Fig. 11 in addition to the common electrode CE, and Fig. 13 is a diagram showing Fig. 12 in addition to the light-shielding layer BM.

[0142] 11 to 13, the first side scan driving circuit GDC1, the first side light emission driving circuit EDC1, the inorganic area VAL, and the dam area DAMA may be disposed in the non-display area NDA at the first corner of the display panel 110.

[0143] The first corner of the display panel 110 may have a rounded planar shape with a predetermined curvature. The write scan drive circuit GWC, control scan drive circuit GCC, initialization scan drive circuit GIC, and bias scan drive circuit GBC of the first-side scan drive circuit GDC1 are arranged along the curvature of the first corner and are, for example, bent at least once. That is, these drive circuits include at least one bent portion along the curvature of the first corner. Although FIGS. 11 to 13 illustrate the write scan drive circuit GWC, control scan drive circuit GCC, initialization scan drive circuit GIC, and bias scan drive circuit GBC of the first-side scan drive circuit GDC1 being bent twice (including two bent portions) along the curvature of the first corner, the embodiment of the present specification is not limited thereto. For example, these drive circuits may include three or more bent portions along the curvature of the first corner. Furthermore, these drive circuits may be curved along the curvature of the first corner.

[0144] Since the first corner of the display panel 110 has a rounded planar shape with a predetermined curvature, the outer length of each of the write scan drive circuit GWC, the control scan drive circuit GCC, the initialization scan drive circuit GIC, and the bias scan drive circuit GBC of the first-side scan drive circuit GDC1 is longer than the inner length. As a result, a first space SPC1 may be disposed between adjacent write scan stages GWST in the bending section CARA of the write scan drive circuit GWC. Signal lines connecting adjacent write scan stages GWST in the bending section CARA of the write scan drive circuit GWC may be disposed in the first space SPC1.

[0145] A second space SPC2 may be disposed between adjacent control scan stages GCST in the bending section CARA of the control scan drive circuit GCC, and signal lines connecting adjacent control scan stages GCST in the bending section CARA of the control scan drive circuit GCC may be disposed in the second space SPC2.

[0146] A third space SPC3 may be disposed between adjacent initialization scan stages GIST in the bending section CARA of the initialization scan driving circuit GIC, and signal lines connecting adjacent initialization scan stages GIST in the bending section CARA of the initialization scan driving circuit GIC may be disposed in the third space SPC3.

[0147] A fourth space SPC4 may be disposed between adjacent bias scan stages GBST in the bending section CARA of the bias scan driving circuit GBC, and signal lines connecting adjacent bias scan stages GBST in the bending section CARA of the bias scan driving circuit GBC may be disposed in the fourth space SPC4.

[0148] The first side light-emitting drive circuit EDC1 is also bent at least once along the curvature of the first corner. That is, the first side light-emitting drive circuit EDC1 also includes at least one bent portion along the curvature of the first corner. Although FIGS. 11 to 13 illustrate an example in which the first side light-emitting drive circuit EDC1 is bent twice along the curvature of the first corner (including two bent portions), the embodiments of the present specification are not limited thereto. For example, the first side light-emitting drive circuit EDC1 may include three or more bent portions along the curvature of the first corner. Furthermore, the first side light-emitting drive circuit EDC1 may be curved along the curvature of the first corner.

[0149] Since the first corner of the display panel 110 has a rounded planar shape with a predetermined curvature, the outer length of the first side light-emitting driving circuit EDC1 is longer than the inner length. Therefore, a fifth space SPC5 may be disposed between adjacent light-emitting stages EST in the bending section CARA of the first side light-emitting driving circuit EDC1. Signal lines connecting adjacent light-emitting stages EST in the bending section CARA of the first side light-emitting driving circuit EDC1 may be disposed in the fifth space SPC5.

[0150] The area of ​​the second space SPC2 may be larger than the area of ​​the first space SPC1, and the area of ​​the third space SPC3 may be larger than the area of ​​the second space SPC2. Also, the area of ​​the fourth space SPC4 may be larger than the area of ​​the third space SPC3, and the area of ​​the fifth space SPC5 may be larger than the area of ​​the fourth space SPC4.

[0151] 12 , in the non-display area NDA at the first corner of the display panel 110, the common electrode CE may overlap the write scan drive circuit GWC, the control scan drive circuit GCC, and the initialization scan drive circuit GIC of the first-side scan drive circuit GDC1. In the non-display area NDA at the first corner of the display panel 110, the common electrode CE may overlap a first portion of the inorganic area VAL. In the non-display area NDA at the first corner of the display panel 110, the common electrode CE may not overlap a second portion of the inorganic area VAL. In the non-display area NDA at the first corner of the display panel 110, the first portion of the inorganic area VAL may include a portion disposed between the control scan drive circuit GCC and the initialization scan drive circuit GIC. The second portion of the inorganic area VAL may include a portion not disposed between the control scan drive circuit GCC and the initialization scan drive circuit GIC. The first portion of the inorganic area VAL may include a portion disposed in the non-display area NDA on the first side of the display panel 110. The second portion of the inorganic area VAL may include a portion disposed in the non-display area NDA on the third side of the display panel 110.

[0152] 13, in the non-display area NDA at the first corner of the display panel 110, the light-shielding layer BM of the cover substrate (CSUB in FIGS. 14 to 16) may overlap the dam area DAMA, the first-side emission drive circuit EDC1, the bias scan drive circuit GBC of the first-side scan drive circuit GDC1, and the initialization scan drive circuit GIC. In the non-display area NDA at the first corner of the display panel 110, the light-shielding layer BM of the cover substrate (CSUB in FIGS. 14 to 16) may overlap the inorganic area VAL. Note that as long as the light-shielding layer BM overlaps the inorganic area VAL in the non-display area NDA at the first corner of the display panel 110, it does not matter whether the light-shielding layer BM overlaps any of the drive circuits, including the scan drive circuit GWC, the control scan drive circuit GCC, the initialization scan drive circuit GIC, the bias scan drive circuit GBC, and the first-side emission drive circuit EDC1.

[0153] The edge EGCE of the common electrode CE and the inorganic region VAL may intersect with each other in the non-display region NDA at a first corner of the display panel 110. For example, a first portion of the edge EGCE of the common electrode CE (a portion corresponding to the first portion of the inorganic region VAL) may be disposed outside the first portion of the inorganic region VAL (the side from the display region DA toward the edge of the non-display region NDA), and a second portion of the inorganic region VAL may be disposed outside the second portion of the edge EGCE of the common electrode CE (a portion corresponding to the second portion of the inorganic region VAL).

[0154] An edge EGCE of the common electrode CE and an edge EGBM of the light-shielding layer BM of the cover substrate (CSUB in FIGS. 14 to 16) may intersect with each other in the non-display area NDA at a first corner of the display panel 110. For example, a first portion of the edge EGCE of the common electrode CE may be disposed outside a first portion of the edge EGBM of the light-shielding layer BM of the cover substrate (CSUB in FIGS. 14 to 16) (a portion corresponding to the first portion of the edge EGCE of the common electrode CE and / or a portion corresponding to the first portion of the inorganic region VAL), and a second portion of the edge EGBM of the light-shielding layer BM of the cover substrate (CSUB in FIGS. 14 to 16) may be disposed outside a second portion of the edge EGCE of the common electrode CE (a portion corresponding to the second portion of the edge EGCE of the common electrode CE and / or a portion corresponding to the second portion of the inorganic region VAL).

[0155] The edge EGBM of the light-shielding layer BM of the cover substrate (CSUB in FIGS. 14 to 16) and the inorganic region VAL may intersect with each other in the non-display area NDA at the first corner of the display panel 110. For example, a first portion of the edge EGBM of the light-shielding layer BM of the cover substrate (CSUB in FIGS. 14 to 16) may be located more inward than the first portion of the inorganic region VAL, and a second portion of the inorganic region VAL may be located more inward than the second portion of the edge EGBM of the light-shielding layer BM of the cover substrate (CSUB in FIGS. 14 to 16).

[0156] In the embodiment of the present specification, in the non-display area NDA at the first corner of the display panel 110, the light-shielding layer BM of the cover substrate (CSUB in FIGS. 14 to 16) overlaps with the inorganic area VAL, thereby blocking external light from entering the common electrode CE disposed in the groove (Gval in FIGS. 15 and 16) of the inorganic area VAL. Therefore, it is possible to prevent or reduce a decrease in the visibility of the image displayed in the display area due to unpredictable diffuse reflection of external light incident on the common electrode CE disposed in the groove (Gval in FIGS. 15 and 16) of the inorganic area VAL.

[0157] The area A6 shown in Figure 2 is substantially the same as the description of the area A3 shown in Figures 11 to 13, except that the first-side scan drive circuit GDC1 and the first-side light-emitting drive circuit EDC1 are replaced with a second-side scan drive circuit GDC2 and a second-side light-emitting drive circuit EDC2, and is bilaterally symmetrical with the area A3 shown in Figures 11 to 13. Therefore, a description of the area A6 shown in Figure 2 will be omitted.

[0158] Fig. 14 is a cross-sectional view showing an example of a cross section of a display panel corresponding to line I1-I1' in Fig. 5. Fig. 14 shows a cross section of the display panel 110 showing the first light-emitting unit ELU1, the second light-emitting unit ELU2, and the third light-emitting unit ELU3 of the display area DA.

[0159] Referring to FIG. 14, the substrate SUB is made of an insulating material such as glass or polymer resin.

[0160] A barrier film BR may be disposed on the substrate SUB. The barrier film BR is a film that mainly protects the thin film transistors TFT1 and TFT2 and the light-emitting layer EL from moisture that penetrates through the substrate SUB, which is susceptible to moisture permeation. The barrier film BR is made of multiple inorganic films stacked alternately.

[0161] A first thin film transistor TFT1 may be disposed on the barrier film BR. The first thin film transistor TFT1 may be either the fifth transistor T5 or the sixth transistor T6 shown in FIG. 4. The first thin film transistor TFT1 may include a first active layer ACT1 and a first gate electrode G1.

[0162] A first active layer ACT1 of the first thin film transistor TFT1 may be disposed on the barrier film BR. The first active layer ACT1 of the first thin film transistor TFT1 may include polycrystalline silicon, single crystal silicon, low temperature polycrystalline silicon, or amorphous silicon.

[0163] The first active layer ACT1 may include a first channel region CHA1, a first source region S1, and a first drain region D1. The first channel region CHA1 may be a region overlapping with the first gate electrode G1 in a third direction DR3, which is a thickness direction of the substrate SUB. The third direction DR3 may be defined as the thickness direction of the substrate SUB or the thickness direction of the display panel 110. The first source region S1 may be disposed on one side of the first channel region CHA1, and the first drain region D1 may be disposed on the other side of the first channel region CHA1. The first source region S1 and the first drain region D1 may be regions that do not overlap with the first gate electrode G1 in the third direction DR3. The first source region S1 and the first drain region D1 may be regions having conductivity formed by doping ions into a semiconductor material.

[0164] A first gate insulating film 131 may be disposed on the first channel region CHA1, the first source region S1, and the first drain region D1 of the first thin film transistor TFT1.

[0165] A first gate metal layer may be disposed on the first gate insulating layer 131. The first gate metal layer may include a first gate electrode G1 of the first thin film transistor TFT1 and a first capacitor electrode CAE1. The first gate electrode G1 may overlap the first active layer ACT1 in the third direction DR3.

[0166] A second gate insulating film 132 may be disposed on the first gate electrode G1 of the first thin film transistor TFT1 and the first capacitor electrode CAE1.

[0167] A second gate metal layer may be disposed on the second gate insulating layer 132. The second gate metal layer may include a second capacitor electrode CAE2. The second capacitor electrode CAE2 may overlap the first capacitor electrode CAE1 of the first thin film transistor TFT1 in the third direction DR3. Because the second gate insulating layer 132 has a predetermined dielectric constant, a capacitor (Cst in FIG. 4) may be formed by the first capacitor electrode CAE1, the second capacitor electrode CAE2, and the second gate insulating layer 132 disposed therebetween.

[0168] A first interlayer insulating film 141 may be disposed on the second capacitor electrode CAE2.

[0169] A second thin film transistor TFT2 may be disposed on the first interlayer insulating film 141. The second thin film transistor TFT2 may be either the second transistor T2 or the third transistor T3 shown in FIG. 4. The second thin film transistor TFT2 may include a second active layer ACT2 and a second gate electrode G2.

[0170] A second active layer ACT2 of the second thin film transistor TFT2 may be disposed on the first interlayer insulating film 141. The second active layer ACT2 may include an oxide semiconductor. For example, the second active layer ACT2 may include IGZO (indium (In), gallium (Ga), zinc (Zn), and oxygen (O)), IGZTO (indium (In), gallium (Ga), zinc (Zn), tin (Sn), and oxygen (O)), or IGTO (indium (In), gallium (Ga), tin (Sn), and oxygen (O)).

[0171] The second active layer ACT2 may include a second channel region CHA2, a second source region S2, and a second drain region D2. The second channel region CHA2 may be a region overlapping with the second gate electrode G2 in the third direction DR3. The second source region S2 may be disposed on one side of the second channel region CHA2, and the second drain region D2 may be disposed on the other side of the second channel region CHA2. The second source region S2 and the second drain region D2 may be regions that do not overlap with the second gate electrode G2 in the third direction DR3. The second source region S2 and the second drain region D2 may be regions that are formed by doping ions into an oxide semiconductor to have conductivity.

[0172] A third gate insulating film 133 may be disposed on the second active layer ACT2 of the second thin film transistor TFT2.

[0173] A third gate metal layer may be disposed on the third gate insulating layer 133. The third gate metal layer may include a second gate electrode G2 of the second thin film transistor TFT2. The second gate electrode G2 may overlap the second active layer ACT2 in the third direction DR3.

[0174] A second interlayer insulating film 142 may be disposed on the second gate electrode G2 of the second thin film transistor TFT2.

[0175] A first data metal layer may be disposed on the second interlayer insulating layer 142. The first data metal layer may include a first connecting electrode BE1, a second connecting electrode BE2, and a third connecting electrode BE3. The first connecting electrode BE1 may be connected to the first drain region D1 of the first active layer ACT1 through a first connecting hole BCT1 that penetrates the first gate insulating layer 131, the second gate insulating layer 132, the first interlayer insulating layer 141, the third gate insulating layer 133, and the second interlayer insulating layer 142. The second connecting electrode BE2 may be connected to the second source region S2 of the second active layer ACT2 through a second connecting hole BCT2 that penetrates the third gate insulating layer 133 and the second interlayer insulating layer 142. The third connecting electrode BE3 may be connected to the second drain region D2 of the second active layer ACT2 through a third connecting hole BCT3 that penetrates the third gate insulating layer 133 and the second interlayer insulating layer 142.

[0176] A first organic film 160 for planarizing steps caused by the first thin film transistor TFT1 and the second thin film transistor TFT2 may be disposed on the first connecting electrode BE1, the second connecting electrode BE2, and the third connecting electrode BE3.

[0177] A second data metal layer may be disposed on the first organic layer 160. The second data metal layer may include a fourth connecting electrode BE4. The fourth connecting electrode BE4 may be connected to the first connecting electrode BE1 through a fourth connecting hole BCT4 that penetrates the first organic layer 160.

[0178] A second organic film 180 may be disposed on the fourth connecting electrode BE4.

[0179] The barrier film BR, the first gate insulating film 131, the second gate insulating film 132, the third gate insulating film 133, the first interlayer insulating film 141, and the second interlayer insulating film 142 are inorganic films, for example, silicon nitride (SiN x ), silicon oxynitride (SiON), silicon oxide (SiO x ), titanium oxide (TiO x ), or aluminum oxide (AlO x ) can be formed.

[0180] The first gate metal layer, the second gate metal layer, the third gate metal layer, the first data metal layer, and the second data metal layer may be formed of a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0181] The first organic film 160 and the second organic film 180 may be formed of an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0182] A plurality of light emitting elements LE and a bank 190 may be disposed on the second organic film 180. Each of the plurality of light emitting elements LE may include a pixel electrode PXE, an emission layer EL, and a common electrode CE. Each of the plurality of light emitting elements LE is an element that emits light when holes from the pixel electrode PXE and electrons from the common electrode CE recombine in the emission layer EL. Each of the plurality of light emitting elements LE may be an organic light emitting diode whose emission layer EL is made of an organic emission layer, but the embodiment of the present specification is not limited thereto.

[0183] A pixel electrode layer may be disposed on the second organic film 180. The pixel electrode layer may include a pixel electrode PXE. Each pixel electrode PXE may be connected to a fourth connecting electrode BE4 via a pixel connecting hole PCT penetrating the second organic film 180. Each pixel electrode PXE may be connected to a first source region S1 or a first drain region D1 of the first thin film transistor TFT1 via a first connecting electrode BE1 and a fourth connecting electrode BE4. In the example of FIG. 14, the pixel electrode PXE is connected to the first drain region D1 as an example. Therefore, a voltage controlled by the first thin film transistor TFT1 can be applied to each pixel electrode PXE. The pixel electrode layer may be formed of a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0184] The bank 190 serves to define the first to third light emitting units ELU1, ELU2, and ELU3 of the display pixel. To this end, the bank 190 may be formed on the second organic film 180 to expose a portion of the pixel electrode PXE. The bank 190 may cover the edge of the pixel electrode PXE.

[0185] A spacer 191 may be disposed on the bank 190 to stably support a mask during the process of depositing the light-emitting layer EL.

[0186] The bank 190 and the spacer 191 may be formed of an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0187] Each of the light-emitting layers EL may be exposed and not covered by the bank 190, and disposed on the corresponding pixel electrode PXE. Each of the light-emitting layers EL includes an organic material and can emit a predetermined light. For example, the light-emitting layer EL of the first light-emitting unit ELU1 may emit a first light, the light-emitting layer EL of the second light-emitting unit ELU2 may emit a second light, and the light-emitting layer EL of the third light-emitting unit ELU3 may emit a third light. Each of the light-emitting layers EL may include a hole transporting layer, an organic material layer, and an electron transporting layer.

[0188] The common electrode CE may be disposed on the light-emitting layer EL and the bank 190. The common electrode CE may be formed to cover the upper surface of each light-emitting layer EL and the upper surface of the bank 190. The common electrode CE may be commonly disposed throughout the display area DA. The common electrode CE may also be disposed in a portion of the non-display area NDA.

[0189] The common electrode CE may be formed of a transparent metal material (TCO, Transparent Conductive Material) such as ITO or IZO that transmits light in the upper light emitting structure, or a semi-transmissive metal material (Semi-transmissive Conductive Material) such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag). When the common electrode CE is formed of a semi-transmissive metal material, the light output efficiency of each light emitting element LE is increased due to the microcavities.

[0190] An encapsulation layer TFE may be formed on the common electrode CE. The encapsulation layer TFE may include at least one inorganic film to prevent oxygen or moisture from penetrating into the light-emitting layer EL. The encapsulation layer TFE may also include at least one organic film to prevent voids from being generated in the at least one inorganic film due to foreign matter such as dust.

[0191] The sealing layer TFE may include a first sealing inorganic film TFE1, a sealing organic film TFE2, and a second sealing inorganic film TFE3, which are sequentially stacked. The first sealing inorganic film TFE1 may be disposed on the common electrode CE, the sealing organic film TFE2 may be disposed on the first sealing inorganic film TFE1, and the second sealing inorganic film TFE3 may be disposed on the sealing organic film TFE2.

[0192] The first sealing inorganic film TFE1 and the second sealing inorganic film TFE3 are made of silicon nitride (SiN x ), silicon oxynitride (SiON), silicon oxide (SiO x ), titanium oxide (TiO x ), or aluminum oxide (AlO x The encapsulating organic film TFE2 may be formed of an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0193] A polarizing film POL may be disposed on the encapsulation layer TFE to prevent a decrease in visibility due to external light. The polarizing film POL may include a first base member, a linear polarizing plate, a phase retardation film such as a quarter-wave plate, and a second base member. The polarizing film POL may be substituted for other anti-reflection layers, such as a color filter layer including multiple color filters.

[0194] A sensor electrode layer including a sensor electrode for sensing a touch may be disposed between the encapsulation layer TFE and the polarizing film POL.

[0195] A cover substrate CSUB may be disposed on the polarizing film POL. The cover substrate CSUB may be attached to the polarizing film POL by a transparent adhesive member ADL such as an optically clear adhesive (OCA) film or an optically clear resin (OCR).

[0196] Figure 15 is a cross-sectional view showing an example of a cross section of a display panel corresponding to line I2-I2' in Figures 6 to 8. Figure 15 shows a cross section of display panel 110 showing non-display area NDA on the first side of display panel 110.

[0197] Referring to Figure 15, the write scan transistor GWT of the write scan stage (GWST in Figure 6), the control scan transistor GCT of the control scan stage (GCST in Figure 6), the initialization scan transistor GIT of the initialization scan stage (GIST in Figure 6), the bias scan transistor GBT of the bias scan stage (GBST in Figure 6), and the emission control transistor ECT of the emission stage (EST in Figure 6) may be arranged on the barrier film BR.

[0198] The write scan transistor GWT may include a write active layer ACTGW and a write gate electrode GGW. The write active layer ACTGW may include a write channel region CHGW, a write source region SGW, and a write drain region DGW. The write active layer ACTGW may be disposed on the barrier film BR. The write gate electrode GGW may overlap the write channel region CHGW in the third direction DR3 and be disposed on the first gate insulating film 131.

[0199] The control scan transistor GCT may include a control active layer ACTGC and a control gate electrode GGC. The control active layer ACTGC may include a control channel region CHGC, a control source region SGC, and a control drain region DGC. The control active layer ACTGC may be disposed on the barrier film BR. The control gate electrode GGC may overlap the control channel region CHGC in the third direction DR3 and be disposed on the first gate insulating film 131.

[0200] The initialization scan transistor GIT may include an initialization active layer ACTGI and an initialization gate electrode GGI. The initialization active layer ACTGI may include an initialization channel region CHGI, an initialization source region SGI, and an initialization drain region DGI. The initialization active layer ACTGI may be disposed on the barrier film BR. The initialization gate electrode GGI may overlap the initialization channel region CHGI in the third direction DR3 and be disposed on the first gate insulating film 131.

[0201] The bias scan transistor GBT may include a bias active layer ACTGB and a bias gate electrode GGB. The bias active layer ACTGB may include a bias channel region CHGB, a bias source region SGB, and a bias drain region DGB. The bias active layer ACTGB may be disposed on the barrier film BR. The bias gate electrode GGB may overlap the bias channel region CHGB in the third direction DR3 and be disposed on the first gate insulating film 131.

[0202] The light-emitting control transistor ECT may include a light-emitting active layer ACTE and a light-emitting gate electrode GE. The light-emitting active layer ACTE may include a light-emitting channel region CHE, a light-emitting source region SE, and a light-emitting drain region DE. The light-emitting active layer ACTE may be disposed on the barrier film BR. The light-emitting gate electrode GE may overlap the light-emitting channel region CHE in the third direction DR3 and be disposed on the first gate insulating film 131.

[0203] The write active layer ACTGW, the control active layer ACTGC, the initialization active layer ACTGI, the bias active layer ACTGB, and the light-emitting active layer ACTE can comprise polycrystalline silicon, single-crystal silicon, low-temperature polycrystalline silicon, or amorphous silicon. The first gate metal layer can comprise a write gate electrode GGW, a control gate electrode GGC, an initialization gate electrode GGI, a bias gate electrode GGB, and a light-emitting gate electrode GE.

[0204] A groove Gval penetrating the first organic film 160 and the second organic film 180 may be disposed in the inorganic region VAL. The inorganic region VAL may separate the first organic film 160 and the second organic film 180 adjacent to the edge EG1 of the first side of the display panel 110 from the first organic film 160 and the second organic film 180 adjacent to the display area DA. The inorganic region VAL may separate the first organic film 160 and the second organic film 180. Therefore, even if oxygen or moisture penetrates through the first organic film 160 and the second organic film 180 at the edge EG1 of the first side of the display panel 110, it is possible to prevent the oxygen or moisture from being transferred to the first organic film 160 and the second organic film 180 adjacent to the display area DA and affecting the light-emitting layer EL.

[0205] The first data metal layer may include a first power supply connecting electrode VSCE1 and a second power supply connecting electrode VSCE2. The first power supply connecting electrode VSCE1 and the second power supply connecting electrode VSCE2 may be disposed on the second interlayer insulating film 142.

[0206] The first power connecting electrode VSCE1 may be disposed at a position corresponding to a groove Gval penetrating the first organic layer 160 and the second organic layer 180. The groove Gval may have a V-shaped cross section.

[0207] The second power supply connecting electrode VSCE2 may be disposed on the second interlayer insulating film 142 that is not covered by the first organic film 160 and is exposed in the dam region DAMA.

[0208] The first power supply line VSL1 includes a first sub-power supply line SVSL1 and a second sub-power supply line SVSL2.

[0209] The first sub-power line SVSL1 may be disposed on the first organic film 160. The first sub-power line SVSL1 may be disposed along a sidewall of the groove Gval in the inorganic region VAL. The first sub-power line SVSL1 may be connected to the first power connecting electrode VSCE1 exposed in the groove Gval in the inorganic region VAL. The first sub-power line SVSL1 may be disposed on the second power connecting electrode VSCE2 in the dam region DAMA.

[0210] The second sub-power line SVSL2 may be disposed on the second organic film 180. The second sub-power line SVSL2 may be disposed on the first sub-power line SVSL1 in the groove Gval of the inorganic region VAL, following the shape of the sidewall of the groove Gval. The second sub-power line SVSL2 may be disposed on the first sub-power line SVSL1 in the groove Gval of the inorganic region VAL. The second sub-power line SVSL2 may be disposed on the first sub-power line SVSL1 in the dam region DAMA.

[0211] For example, the second power supply connecting electrode VSCE2, the first sub-power supply line SVSL1, and the second sub-power supply line SVSL2 may be sequentially stacked in the dam region DAMA.

[0212] As shown in Figures 6 to 8, 15, etc., the first sub-power line SVSL1 and the second sub-power line SVSL2 may overlap with the initialization scan drive circuit GIC (including the initialization scan transistor GIT), the bias scan drive circuit GBC (including the bias scan transistor GBT), and the first side light-emitting drive circuit EDC1 (including the light-emitting control transistor ECT) arranged between the inorganic region VAL and the dam region DAMA.

[0213] The common electrode CE may be disposed on the exposed second organic film 180 and the bank 190 without being covered by the bank 190. The common electrode CE may be connected to the second sub-power line SVSL2 in the groove Gval of the inorganic region VAL. The common electrode CE may be disposed on the sidewall of the groove Gval of the inorganic region VAL. In an example such as FIG. 15 , the common electrode CE is disposed on the second sub-power line SVSL2 in the groove Gval of the inorganic region VAL, following the shape of the sidewall of the groove Gval. As a result, when external light enters the groove Gval of the inorganic region VAL, it may be diffusely reflected unpredictably by the common electrode CE disposed on the sidewall of the groove Gval of the inorganic region VAL.

[0214] The first dam DAM1 and the second dam DAM2 may be disposed on the first power line VSL1.

[0215] The first dam DAM1 and the second dam DAM2 may be structures for preventing the encapsulation organic film TFE2 from overflowing onto the edge EG1 of the first side of the display panel 110. The first dam DAM1 and the second dam DAM2 may be structures for confining the encapsulation organic film TFE2.

[0216] The first dam DAM1 may include a first sub-dam SDAM1_1, a second sub-dam SDAM2_1, and a third sub-dam SDAM3_1 stacked in sequence on the first power line VSL1. The first dam DAM1 has no dams DAM in the region adjacent to the display area DA side and the region adjacent to the opposite side of the display area DA, forming a groove. As a result, the first dam DAM1 is formed convexly in the third direction DR3. The groove in the region adjacent to the display area DA side of the first dam DAM1 is formed between the first dam DAM1 and the first organic film 160 and the second organic film 180. The groove in the region adjacent to the opposite side of the display area DA of the first dam DAM1 is formed between the first dam DAM1 and the second dam DAM2. In the example of FIG. 15, the first dam DAM1 is formed to protrude in the third direction DR3, for example, with respect to the second interlayer insulating film 142. The first sub-dam SDAM1_1 may be formed of the same material as the second organic film 180, the second sub-dam SDAM2_1 may be formed of the same material as the bank 190, and the third sub-dam SDAM3_1 may be formed of the same material as the spacer 191.

[0217] The second sub-power line SVSL2 may be arranged on the first sub-dam SDAM1_1 of the first dam DAM1. The second sub-power line SVSL2 may be arranged to cover the first sub-dam SDAM1_1 of the first dam DAM1. For example, the second sub-power line SVSL2 may be arranged on the top and side surfaces of the first sub-dam SDAM1_1 of the first dam DAM1. The second sub-dam SDAM2_1 of the first dam DAM1 may be arranged on the second sub-power line SVSL2.

[0218] The second dam DAM2 may include a first sub-dam SDAM1_2, a second sub-dam SDAM2_2, a third sub-dam SDAM3_2, and a fourth sub-dam SDAM4_2 sequentially stacked on the second interlayer insulating film 142. The first sub-dam SDAM1_2 may be formed of the same material as the first organic film 160, and the second sub-dam SDAM2_2 may be formed of the same material as the second organic film 180. The third sub-dam SDAM3_2 may be formed of the same material as the bank 190, and the fourth sub-dam SDAM4_2 may be formed of the same material as the spacer 191.

[0219] The first sub-dam SDAM1_2 of the second dam DAM2 may be disposed on the second power connecting electrode VSCE2. The first sub-power line SVSL1 may be disposed on the first sub-dam SDAM1_2 of the second dam DAM2, and the second sub-dam SDAM2_2 of the second dam DAM2 may be disposed on the first sub-power line SVSL1. The second sub-power line SVSL2 may be disposed on the second sub-dam SDAM2_2 of the second dam DAM2, and the third sub-dam SDAM3_2 of the second dam DAM2 may be disposed on the second sub-power line SVSL2.

[0220] An inorganic sealing area IEA including only an inorganic film may be disposed outside the second dam DAM2 (toward the edge of the display panel 110). The inorganic film of the inorganic sealing area IEA may be formed by disposing a first sealing inorganic film TFE1 and a second sealing inorganic film TFE3 in contact with each other. No organic film is disposed in the inorganic sealing area IEA. The display area DA is surrounded by the inorganic sealing area IEA, thereby preventing external oxygen or moisture from penetrating into the light-emitting layer EL of the display area DA. The inorganic sealing area IEA may be disposed adjacent to the edge of the first side of the display panel 110 (EG1 in Figures 6 to 8). The inorganic sealing area IEA may be disposed closer to the dam area DAMA than the inorganic area VAL. As described above, the dam area DAMA may include one dam DAM or three or more dams DAM. When one dam DAM is included in the dam area DAMA, an inorganic film can be formed on the side of the one dam DAM facing the outer edge (e.g., the edge EG1 on the first side) of the display panel 110 by arranging the first sealing inorganic film TFE1 and the second sealing inorganic film TFE3 in contact with each other. When three dams DAM are included in the dam area DAMA, an inorganic film can be formed on the dam DAM that is closest to the outer edge (e.g., the edge EG1 on the first side) of the display panel 110 by arranging the first sealing inorganic film TFE1 and the second sealing inorganic film TFE3 in contact with each other on the side facing the outer edge (e.g., the edge EG1 on the first side) of the display panel 110.

[0221] A light-shielding layer BM may be disposed on one surface of the cover substrate CSUB. The light-shielding layer BM may overlap the grooves Gval of the inorganic region VAL in the third direction DR3. This may prevent external light from entering the grooves Gval of the inorganic region VAL. This may prevent external light from being unpredictably diffused by the common electrode CE disposed on the sidewalls of the grooves Gval of the inorganic region VAL, thereby preventing or reducing degradation in visibility of images displayed in the display area DA.

[0222] 11 to 13 is substantially the same as the cross section of the display panel 110 corresponding to the line I4-I4' shown in Fig. 15, and therefore a description of the cross section of the display panel 110 corresponding to the line I4-I4' shown in Fig. 11 to 13 will be omitted. Note that the portion along the line I4-I4' is included in the first corner of the display panel 110.

[0223] FIG. 16 is a cross-sectional view showing an example of a cross section of the display panel corresponding to the line I3-I3' in FIGS.

[0224] 16 shows a cross section of the display panel 110 showing the non-display area NDA on the third side of the display panel 110. In the embodiment of FIG. 16, explanations that overlap with the embodiment of FIG. 15 will be omitted, and the explanation will focus on the differences from the embodiment of FIG. 15.

[0225] 16, the common electrode CE may be disposed on the exposed second organic film 180 and the bank 190 without being covered by the bank 190. The common electrode CE is not disposed in the groove Gval of the inorganic region VAL. The common electrode CE may be connected to the second sub-power line SVSL2.

[0226] A light-shielding layer BM may be disposed on one surface of the cover substrate CSUB. The light-shielding layer BM does not overlap the grooves Gval of the inorganic region VAL in the third direction DR3.

[0227] In the non-display area NDA on the third side of the display panel 110, the inorganic area VAL is exposed without being blocked by the light-shielding layer BM of the cover substrate CSUB, so external light can be incident on the inorganic area VAL. However, the common electrode CE is disposed apart from the inorganic area VAL and is not disposed in the groove Gval of the inorganic area VAL. Therefore, even if external light is incident on the inorganic area VAL, diffused reflection can be reduced or prevented. Therefore, a decrease in visibility of the image displayed in the display area can be prevented or reduced.

[0228] 11 to 13 is substantially the same as the cross section of the display panel 110 corresponding to the line I5-I5' shown in Fig. 16, and therefore a description of the cross section of the display panel 110 corresponding to the line I5-I5' shown in Fig. 11 to 13 will be omitted. Note that the portion along the line I5-I5' is included in the first corner of the display panel 110.

[0229] FIG. 17 is a perspective view showing an electronic device to which a display device according to an embodiment is applied.

[0230] 17 , a tablet 1 to which the display device 10 according to an embodiment is applied is shown as an example of an electronic device. However, the display device 10 according to an embodiment may be applied to electronic devices other than the tablet 1. For example, the display device 10 according to an embodiment may be applied to electronic devices that display moving images or still images. For example, the display device 10 according to an embodiment may be applied to portable electronic devices such as mobile phones, smartphones, smart watches, watch phones, mobile communication terminals, electronic organizers, electronic books, portable multimedia players (PMPs), navigation systems, and ultra-mobile PCs (UMPCs). Alternatively, the display device 10 according to an embodiment may be used as a display screen for various electronic devices such as televisions, notebook computers, monitors, billboards, and Internet of Things (IoT) devices.

[0231] Although the present invention has been described above with reference to the accompanying drawings, those skilled in the art will understand that the present invention can be embodied in other specific forms without changing the technical spirit or essential features of the present invention. Therefore, it should be understood that the above-described embodiment is illustrative in all respects and is not limiting. [Explanation of symbols]

[0232] 10 Display device 110 Display panel SUB board PXE 1st pixel electrode LE light-emitting element CE common electrode

Claims

1. a display panel including a plurality of light-emitting units arranged in a display area that displays an image, and an inorganic area arranged in a non-display area around the display area; Each of the plurality of light-emitting portions includes a pixel electrode, a light-emitting layer, and a common electrode, which are sequentially stacked, the display panel includes a first side, a second side opposite to the first side, and a third side connecting the first side and the second side; In a non-display area on the first side of the display panel, the common electrode overlaps the inorganic area; In a non-display area on a third side of the display panel, the common electrode is disposed apart from the inorganic area.

2. a cover substrate disposed on the display panel and including a light-shielding layer; In a non-display region on the first side of the display panel, the light-shielding layer overlaps the inorganic region; The display device according to claim 1 , wherein the light-shielding layer does not overlap the inorganic region in the non-display region on the third side of the display panel.

3. In a non-display region on the first side of the display panel, the common electrode overlaps the light-shielding layer; The display device according to claim 2 , wherein the common electrode does not overlap the light-shielding layer in a non-display area on the third side of the display panel.

4. the display panel further includes a first corner bordering the first side and the third side; The display device of claim 1 , wherein an edge of the common electrode and the inorganic region intersect with each other in a non-display region at a first corner of the display panel.

5. the display panel further includes a first corner bordering the first side and the third side; The display device according to claim 2 , wherein an edge of the common electrode intersects with an edge of the light-shielding layer in a non-display area at a first corner of the display panel.

6. the display panel further includes a first corner bordering the first side and the third side; The display device according to claim 2 , wherein an edge of the light-shielding layer intersects with an edge of the inorganic region in a non-display region at a first corner of the display panel.

7. The display panel includes: a first scan line extending in a first direction; a second scan line extending in the first direction; a first scan driving circuit disposed in a non-display area on the first side of the display panel, the first scan driving circuit outputting a first scan signal to the first scan line; and a second scan driving circuit disposed in a non-display area on the first side of the display panel and configured to output a second scan signal to the second scan line; The display device according to claim 2 , wherein the inorganic region is disposed between the first scan driving circuit and the second scan driving circuit in the non-display region on the first side of the display panel.

8. The display device according to claim 7 , wherein the common electrode overlaps with the first scan driving circuit and the second scan driving circuit in a non-display area on the first side of the display panel.

9. The display device according to claim 7 , wherein the light-shielding layer overlaps the first scan driving circuit and the second scan driving circuit in a non-display area on the first side of the display panel.

10. The display device according to claim 7 , wherein in the non-display area on the first side of the display panel, the light-shielding layer overlaps the second scan driving circuit but does not overlap the first scan driving circuit.

11. The display panel includes: a third scan line extending in the first direction; and a third scan driving circuit disposed in a non-display area on the first side of the display panel and configured to output a third scan signal to the third scan line; The display device according to claim 7 , wherein in the non-display area on the first side of the display panel, a third scan driving circuit is disposed between the first scan driving circuit and the inorganic area.

12. The display device of claim 11 , wherein the common electrode overlaps with the first scan driving circuit, the second scan driving circuit, and the third scan driving circuit in a non-display area on the first side of the display panel.

13. The display device according to claim 11 , wherein the light-shielding layer overlaps the first scan driving circuit, the second scan driving circuit, and the third scan driving circuit in a non-display area on the first side of the display panel.

14. The display device according to claim 11 , wherein in a non-display area on the first side of the display panel, the light-shielding layer overlaps the second scan driving circuit and the third scan driving circuit but does not overlap the first scan driving circuit.

15. The display device according to claim 11 , wherein in the non-display area on the first side of the display panel, the light-shielding layer overlaps the second scan driving circuit but does not overlap the first scan driving circuit and the third scan driving circuit.

16. The display panel includes: a first sealing inorganic film disposed on the plurality of light emitting units; a sealing organic film disposed on the first sealing inorganic film; and The insulating film further includes a second sealing inorganic film disposed on the sealing organic film, the non-display area further includes an inorganic sealing area where the first sealing inorganic film and the second sealing inorganic film are in contact with each other, The display device according to claim 1 , wherein the inorganic sealing region is disposed closer to an edge of the display panel than the inorganic region.

17. The display panel includes: a dam disposed in the non-display area for confining the sealing organic film; The display device according to claim 16 , wherein the inorganic sealing region is disposed closer to the dam than the inorganic region.

18. A display panel including a plurality of light-emitting units arranged in a display area that displays an image, and an inorganic area arranged in a non-display area around the display area; and a cover substrate disposed on the display panel and including a light-shielding layer; Each of the plurality of light-emitting portions includes a pixel electrode, a light-emitting layer, and a common electrode, which are sequentially stacked, the display panel includes a first side, a second side opposite to the first side, and a third side connecting the first side and the second side; In a non-display region on the first side of the display panel, the common electrode overlaps with a light-shielding layer; In a non-display area on a third side of the display panel, the common electrode does not overlap with the light-shielding layer.

19. In a non-display area on the first side of the display panel, the common electrode overlaps the inorganic area; The display device of claim 18 , wherein the common electrode is disposed apart from the inorganic region in a non-display region on a third side of the display panel.

20. In a non-display region on the first side of the display panel, the light-shielding layer overlaps the inorganic region; The display device of claim 18 , wherein the light-shielding layer does not overlap the inorganic region in a non-display region on the third side of the display panel.

21. a substrate including a display area and a non-display area disposed around the display area; at least one inorganic film disposed on the substrate; a first organic film disposed on the at least one inorganic film; a second organic film disposed on the first organic film; a pixel electrode disposed on the second organic film in the display region; a light-emitting layer disposed on the pixel electrode; and a common electrode disposed on the light-emitting layer; the non-display area includes an inorganic area including a groove penetrating the first organic film and the second organic film, the common electrode is disposed on an inorganic region in a non-display region on a first side of the substrate; The display device, wherein the common electrode is disposed apart from the inorganic region of the non-display region on a third side adjacent to the first side of the substrate.

22. a first sub-power line disposed on the first organic film in the non-display area; and The display device of claim 21 , further comprising a second sub-power line disposed on the second organic film in the non-display area.

23. the first sub-power line and the second sub-power line are disposed in the groove of the inorganic region; the first sub-power line and the second sub-power line disposed in the groove in the inorganic region of the non-display region on the first side of the substrate are connected to the common electrode; The display device of claim 22 , wherein the first and second sub-power lines disposed in the grooves of the inorganic region in the non-display region on the third side of the substrate are spaced apart from the common electrode.

24. The display device of claim 22 , further comprising a first power supply connecting electrode disposed on the at least one inorganic film and connected to the first sub-power supply line in the groove of the inorganic region.

25. a second power supply connecting electrode disposed on the at least one inorganic film and connected to the first sub-power supply line; a first sealing inorganic film disposed on the common electrode; a sealing organic film disposed on the first sealing inorganic film; a second sealing inorganic film disposed on the sealing organic film; and a dam disposed in the non-display area for confining the sealing organic film; The display device of claim 22 , wherein the dam is disposed on the second power supply connecting electrode.

26. a scan transistor disposed on the substrate and covered by the at least one inorganic film; The display device of claim 22 , wherein the first sub-power line and the second sub-power line overlap the scan transistor.

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