Display device and electronic apparatus

Abstract

To provide a display device capable of improving corrosion defects of lines in a non-display area.SOLUTION: A display device comprises: a display panel; a plurality of pixels arranged in a display area of the display panel; an inspection circuit portion and a pad area arranged in a non-display area of the display panel; a data routing line extending from the display area to the inspection circuit portion and the pad area; a first planarization layer extending from the display area to the inspection circuit portion, and arranged on the data routing line; and a second planarization layer extending from the display area to the inspection circuit portion and the pad area, and arranged on the first planarization layer. The inspection circuit portion is arranged adjacent to the pad area and includes an inspection signal supply line for supplying an inspection signal to the data routing line, and the second planarization layer includes a first area overlapping the inspection signal supply line and a second area overlapping the pad area.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] The present invention relates to a display device and an electronic device. [Background technology]

[0002] With the development of an information society, the demands for display devices for displaying images are becoming increasingly diverse. For example, display devices are applied to a variety of electronic devices such as smartphones, digital cameras, notebook computers, navigation systems, and smart TVs.

[0003] Recently, display devices have been minimizing the bezel area or non-display area outside the display area in order to expand the display area where pixels that display images are arranged. Various signal lines are arranged in the bezel area or non-display area, and if the thickness of the protective film on the signal lines is thin, the signal lines may be corroded by moisture or air that penetrates from the outside, causing defects. Summary of the Invention [Problem to be solved by the invention]

[0004] One of the problems to be solved by the present invention is to provide a display device capable of improving corrosion defects of wiring in the non-display area.

[0005] The objectives of the present invention are not limited to the above-mentioned objectives, and other technical objectives will be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0006] A display device according to one embodiment of the present invention may include a display panel, a plurality of pixels arranged in a display area of ​​the display panel, a test circuit unit and a pad area arranged in a non-display area of ​​the display panel, data routing wiring extending from the display area to the test circuit unit and the pad area, a first planarization layer extending from the display area to the test circuit unit and arranged on the data routing wiring, and a second planarization layer extending from the display area to the test circuit unit and the pad area and arranged on the first planarization layer, the test circuit unit including test signal supply wiring arranged adjacent to the pad area and supplying test signals to the data routing wiring, and the second planarization layer including a first region overlapping the test signal supply wiring and a second region overlapping the pad area.

[0007] The first region of the second planarization layer may cover the inspection signal supply wiring, and a side of the first region may be spaced apart from the inspection signal supply wiring on a plane.

[0008] A side of the first region of the second planarization layer may be disposed between the inspection signal supply wiring and the pad region on a plane.

[0009] The pad region may include a data pad connected to the data routing wiring, and the first region of the second planarization layer may not overlap the data pad.

[0010] The second region of the second planarization layer may overlap the data pad.

[0011] The second region of the second planarization layer may include a pad opening overlapping the data pad.

[0012] The height of the first region of the second planarization layer may be greater than the height of the second region.

[0013] The first planarization layer may not overlap the pad region and may overlap the first region and the second region of the second planarization layer.

[0014] The test circuit unit may include a test transistor including a test active layer, the data routing wiring may be electrically connected to one end of the test active layer, and the test signal supply wiring may be electrically connected to the other end of the test active layer.

[0015] The test circuitry may be disposed between the display area and the pad area, and the data routing wiring may extend from the display area to the pad area, passing through the test circuitry.

[0016] Furthermore, a display device according to an embodiment of the present invention may include a substrate including a display area and a non-display area including a pad area, data routing wiring disposed on the non-display area, at least two insulating layers disposed on the data routing wiring, data pads disposed on the pad area and connected to the data routing wiring via contact holes penetrating the insulating layers, test signal supply wiring disposed in the non-display area not overlapping the pad area and intersecting the data routing wiring, a first planarization layer disposed on the test signal supply wiring, and a second planarization layer disposed on the first planarization layer and the data pad, the second planarization layer including a first region overlapping the test signal supply wiring and a second region overlapping the data pad.

[0017] The first region of the second planarization layer may cover the inspection signal supply wiring, and a side of the first region may be spaced apart from the inspection signal supply wiring on a plane.

[0018] A side of the first region of the second planarization layer may be disposed between the inspection signal supply wiring and the pad region on a plane.

[0019] The first region of the second planarization layer and the first planarization layer may not overlap the data pad.

[0020] The second region of the second planarization layer may overlap the data pad.

[0021] The second region of the second planarization layer may include a pad opening overlapping the data pad.

[0022] The first region of the second planarization layer may have a thickness measured from the top surface of the substrate that is greater than a thickness of the second region.

[0023] The first planarization layer may overlap the first region and the second region of the second planarization layer.

[0024] Furthermore, a display device according to one embodiment of the present invention includes a substrate having a display area and a non-display area, a pad area disposed in the non-display area of ​​the substrate and including pads, an inspection circuit unit disposed between the display area and the pad area of ​​the substrate, routing wiring disposed on the substrate and passing through the inspection circuit unit and extending to the pads, and a first planarization layer extending from the display area to the inspection circuit unit and the pad area, wherein the inspection circuit unit is adjacent to the pad area and includes signal wiring electrically connected to the routing wiring, and the first planarization layer includes a first area covering the signal wiring and a second area covering the pad area, and a side of the first area may be disposed between the signal wiring and the pads on a plane.

[0025] The test circuit unit may include a test transistor including a test active layer, the routing wiring may be electrically connected to one end of the test active layer, and the signal wiring may be electrically connected to the other end of the test active layer.

[0026] The first region of the first planarization layer may not overlap the pad, and the second region of the first planarization layer may overlap the pad.

[0027] The first region of the first planarization layer may have a thickness measured from the top surface of the substrate that is greater than a thickness of the second region.

[0028] The semiconductor device may further include a second planarization layer disposed between the signal wiring and the first planarization layer, the second planarization layer covering the signal wiring.

[0029] The second planarization layer may not overlap the pad.

[0030] Furthermore, an electronic device according to an embodiment of the present invention may include a display device for providing an image, a processor for providing an image data signal to the display device, a memory for storing data information for driving the display device, and a power supply module for generating power, wherein the display device may include a display panel, a plurality of pixels arranged in a display area of ​​the display panel, a test circuit unit and a pad area arranged in a non-display area of ​​the display panel, data routing wiring extending from the display area to the test circuit unit and the pad area, a first planarization layer extending from the display area to the test circuit unit and arranged on the data routing wiring, and a second planarization layer extending from the display area to the test circuit unit and the pad area and arranged on the first planarization layer, the test circuit unit including test signal supply wiring arranged adjacent to the pad area and supplying a test signal to the data routing wiring, and the second planarization layer may include a first region overlapping the test signal supply wiring and a second region overlapping the pad area.

[0031] Specific details of other embodiments are included in the detailed description and drawings. [Effects of the Invention]

[0032] In a display device according to an exemplary embodiment of the present invention, the first region of the second planarization layer may be formed to cover the inspection signal supply wiring that is closest to the pad region in the inspection circuit unit, thereby protecting the inspection signal supply wiring from external moisture and air and preventing corrosion of the inspection signal supply wiring.

[0033] The effects of the embodiments of the present invention are not limited to the above examples, and more diverse effects are included within this specification. [Brief explanation of the drawings]

[0034] [Figure 1] 1 is a perspective view illustrating a display device according to an embodiment. [Figure 2] 1 is a plan view showing a display device according to an embodiment. [Figure 3] FIG. 3 is a plan view showing the display panel of FIG. 2. [Figure 4] 1 is a circuit diagram of a pixel of a display device according to an embodiment; [Figure 5] 1 is a cross-sectional view showing a display device according to an embodiment. [Figure 6] FIG. 2 is a plan view showing a non-display area of ​​a display device according to an embodiment. [Figure 7] FIG. 7 is an enlarged plan view of region A in FIG. 6. [Figure 8] FIG. 2 is a plan view showing an inspection circuit unit according to an embodiment. [Figure 9] FIG. 8 is a cross-sectional view taken along the line Q1-Q1′ in FIG. 7. [Figure 10] 1 is a plan view showing a test circuit unit and a part of a pad region of a display device according to an embodiment; [Figure 11] FIG. 11 is a cross-sectional view taken along the line Q2-Q2′ in FIG. [Figure 12] 1A to 1C are diagrams illustrating steps in a method for manufacturing a display device according to an embodiment. [Figure 13] 1A to 1C are diagrams illustrating steps in a method for manufacturing a display device according to an embodiment. [Figure 14] 1A to 1C are diagrams illustrating steps in a method for manufacturing a display device according to an embodiment. [Figure 15] FIG. 1 is a block diagram of an electronic device according to one embodiment. [Figure 16] 1 is a schematic diagram of an electronic device according to various embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0035] The advantages and features of the present invention, as well as methods for achieving them, will become clearer with reference to the following detailed description of the embodiments in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, and can be realized in various different forms. The present embodiments are provided merely to complete the disclosure of the present invention and to fully convey the scope of the invention to those skilled in the art to which the present invention pertains. The present invention is defined solely by the scope of the claims.

[0036] When an element or layer is referred to as being "on" another element or layer, this includes being immediately on top of or between other layers or elements. Similarly, when references are made to "below," "left," and "right," this includes being immediately adjacent to or between other layers or materials. Like reference numerals throughout the specification refer to like elements.

[0037] Although terms such as "first" and "second" are used to describe various components, it is understood that these components are not limited by these terms. These terms are used merely to distinguish one component from another. Therefore, it is understood that a "first" component referred to below may be a "second" component within the technical concept of the present invention.

[0038] Each embodiment will be described below with reference to the drawings.

[0039] FIG. 1 is a perspective view showing a display device according to an embodiment.

[0040] Referring to FIG. 1, the display device 100 is a device for displaying moving or still images, and can be used as a display screen for a variety of products, including portable electronic devices such as mobile phones, smartphones, tablet personal computers (PCs), smart watches, watch phones, mobile communication terminals, electronic organizers, electronic books, portable multimedia players (PMPs), navigation systems, and Ultra Mobile PCs (UMPCs), as well as televisions, notebook computers, monitors, billboards, and Internet of Things (IoT).

[0041] The display device 100 may be an emissive display device such as an organic light emitting display device using an organic light emitting diode, a quantum dot light emitting display device including a quantum dot light emitting layer, an inorganic light emitting display device including an inorganic semiconductor, and a micro- or nano-light emitting display device using a micro- or nano-light emitting diode (micro LED or nano LED). Hereinafter, the display device 100 will be described mainly as an organic light emitting display device, but the present invention is not limited thereto.

[0042] The display device 100 may include a display panel 110 and a circuit board 200 .

[0043] The display panel 110 may be formed as a rectangular plane having a long side in a first direction DR1 and a short side in a second direction DR2 intersecting the first direction DR1. The corner where the long side in the first direction DR1 and the short side in the second direction DR2 intersect may be rounded to have a predetermined curvature or may be formed at a right angle.

[0044] The planar shape of the display panel 110 is not limited to a rectangle, but may be other polygonal, circular, or elliptical shapes. The display panel 110 may be formed flat, but is not limited thereto. For example, the display panel 110 may include curved portions formed at the left and right ends, having a constant curvature or a variable curvature. The display panel 110 may also be formed flexible so that it can be bent, warped, bent, folded, or rolled.

[0045] The display panel 110 may include a display area DA that displays an image and a non-display area NDA that is arranged around the display area DA. Alternatively, the substrate of the display panel 110 ("SUB" in FIG. 5) may include the display area DA and the non-display area NDA.

[0046] The display area DA occupies most of the area of ​​the display panel 110. The display area DA may be disposed in the center of the display panel 110. Pixels may be disposed in the display area DA to display an image.

[0047] The non-display area NDA may be disposed adjacent to the display area DA, may be an outer area of ​​the display area DA, may be disposed so as to surround the display area DA, or may be an edge area of ​​the display panel 110.

[0048] Pads ("PD" in FIG. 3) may be arranged in the non-display area NDA to connect to the circuit board 200. The pads may be arranged on one side edge of the display panel 110. For example, the pads may be arranged on the bottom edge of the display panel 110.

[0049] The circuit board 200 may be disposed on a display pad area PA disposed on one side edge of the display panel 110. The circuit board 200 may be attached to the display pad DP using a low-resistance, highly reliable material such as anisotropic conductive film or SAP (Self Assembly Anisotropic Conductive Paste). This allows the circuit board 200 to be electrically connected to the signal wiring of the display panel 110.

[0050] The display panel 110 receives a data voltage, a power supply voltage, a scan timing signal, etc. through a circuit board 200. The circuit board 200 may be a flexible printed circuit board, a printed circuit board, or a flexible film such as a chip on film.

[0051] The circuit board 200 may include a data driver DD. The data driver DD may generate a data voltage, a power supply voltage, a scan timing signal, etc. The data driver DD may supply the data voltage, the power supply voltage, the scan timing signal, etc. to the display panel 110 via the circuit board 200.

[0052] The data driver DD may be formed as an integrated circuit (IC) and attached to the circuit board 200. Alternatively, the data driver DD may be attached to the display panel 110 using a chip on glass (COG) method, a chip on plastic (COP) method, or an ultrasonic bonding method.

[0053] Fig. 2 is a plan view of a display device according to an embodiment, Fig. 3 is a plan view of a display panel of Fig. 2, Fig. 3 is a diagram showing the remaining components of Fig. 2 except for a data driver.

[0054] 2 and 3, the display device 100 may include a plurality of pixels PX arranged on a display panel 110, a gate driver that supplies driving signals to the pixels PX, an emission driver, and a data driver. Here, the pixels PX may be arranged in a display area DA of the display panel 110, the gate driver and the emission driver may be arranged in a non-display area NDA of the display panel 110, and the data driver may be connected to the non-display area NDA of the display panel 110 via a circuit board 200.

[0055] The display device 100 may further include a power supply and a timing control unit. The power supply may supply power voltages to the pixels PX, the gate drivers, the light emitting drivers, and the data drivers. The timing control unit may control the operations of the first gate driver GD1, the second gate driver GD2, the first light emitting driver ED1, the second light emitting driver ED2, and the data driver.

[0056] A plurality of pixels PX may be arranged in a display area DA. The plurality of pixels PX may display an image. The plurality of pixels PX may be connected to gate lines GL, emission control lines EML, data lines DL, and power lines. The gate lines GL and emission control lines EML may extend along a first direction DR1, and the data lines DL may extend along a second direction DR2.

[0057] 3, the non-display area NDA may include a pad area PA in which a plurality of pads PD are arranged. For example, the pad area PA may be arranged in a non-display area (NDA; e.g., a lower non-display area) located below the display area. The plurality of pads PD may be arranged along a first direction DR1.

[0058] A gate driver GD and a light-emitting driver ED may be arranged in the non-display area NDA. For example, the gate driver GD may include a first gate driver GD1 and a second gate driver GD2. The light-emitting driver ED may include a first light-emitting driver ED1 and a second light-emitting driver ED2. Here, the first gate driver GD1 and the first light-emitting driver ED1 may be arranged in the non-display area (NDA; e.g., the left non-display area) located on the left side of the display area DA, and the second gate driver GD2 and the second light-emitting driver ED2 may be arranged in the non-display area (NDA; e.g., the right non-display area) located on the right side of the display area DA.

[0059] The gate driver GD may drive the gate lines GL. For example, the first gate driver GD1 and the second gate driver GD2 may respectively supply gate signals to the gate lines GL. The gate lines GL may be connected to the first gate driver GD1 and the second gate driver GD2. For example, one side of each gate line GL may be electrically connected to the first gate driver GD1, and the other side of each gate line GL may be electrically connected to the second gate driver GD2.

[0060] The light-emitting driver ED may drive the light-emitting control line EML. For example, the first light-emitting driver ED1 and the second light-emitting driver ED2 may each supply a light-emitting control signal to the light-emitting control line EML, and the light-emitting control line EML may be connected to the first light-emitting driver ED1 and the second light-emitting driver ED2. For example, one side of each light-emitting control line EML may be electrically connected to the first light-emitting driver ED1, and the other side of each light-emitting control line EML may be electrically connected to the second light-emitting driver ED2.

[0061] The circuit board 200 may be electrically connected to the display panel 110 via pads PD. The circuit board 200 may include a first circuit board CB1, a second circuit board CB2, a third circuit board CB3, a fourth circuit board CB4, and a fifth circuit board CB5. In one embodiment, the first to fifth circuit boards CB1-CB5 may be connected to at least one of a timing control unit and a power supply unit via other circuit boards, connectors, etc.

[0062] Each circuit board CB1-CB5 may include a cluster terminal (or cluster bump). For example, the first circuit board CB1 may include a first cluster terminal BP1, the second circuit board CB2 may include a second cluster terminal BP2, the third circuit board CB3 may include a third cluster terminal BP3, the fourth circuit board CB4 may include a fourth cluster terminal BP4, and the fifth circuit board CB5 may include a fifth cluster terminal BP5.

[0063] The first cluster terminal BP1 may include a plurality of first terminals (or bumps; C1, P1, D1) arranged adjacently on the first circuit board CB1, the second cluster terminal BP2 may include a plurality of second terminals P2, D2 arranged adjacently on the second circuit board CB2, the third cluster terminal BP3 may include a plurality of third terminals P3, D3 arranged adjacently on the third circuit board CB3, the fourth cluster terminal BP4 may include a plurality of fourth terminals P4, D4 arranged adjacently on the fourth circuit board CB4, and the fifth cluster terminal BP5 may include a plurality of fifth terminals C2, P5, D5 arranged adjacently on the fifth circuit board CB5.

[0064] The data driver DD may include a plurality of driver circuits (DDC1, DDC2, DDC3, DDC4, DDC5; hereinafter, referred to as data driver circuits) arranged along a first direction DR1. For example, the data driver DD may include a first data driver circuit DDC1 mounted on a first circuit board CB1, a second data driver circuit DDC2 mounted on a second circuit board CB2, a third data driver circuit DDC3 mounted on a third circuit board CB3, a fourth data driver circuit DDC4 mounted on a fourth circuit board CB4, and a fifth data driver circuit DDC5 mounted on a fifth circuit board CB5.

[0065] Each of the data driving circuits DDC1-DDC5 can be electrically connected to the pads PD of the display panel 110 via each of the circuit boards CB1-CB5. For example, the first data driving circuit DDC1 may be electrically connected to the first pads C11, P11, and D11 of the display panel 110 via the first terminals C1, P1, and D1 of the first circuit board CB1, the second data driving circuit DDC2 may be electrically connected to the second pads P22 and D22 of the display panel 110 via the second terminals P2 and D2 of the second circuit board CB2, the third data driving circuit DDC3 may be electrically connected to the third pads P33 and D33 of the display panel 110 via the third terminals P3 and D3 of the third circuit board CB3, the fourth data driving circuit DDC4 may be electrically connected to the fourth pads P44 and D44 of the display panel 110 via the fourth terminals P4 and D4 of the fourth circuit board CB4, and the fifth data driving circuit DDC5 may be electrically connected to the fifth pads C22, P55, and D55 of the display panel 110 via the fifth terminals C2, P5, and D5 of the fifth circuit board CB5.

[0066] The plurality of data lines DL may be connected to the data driver DD. For example, the plurality of data lines DL may be divided and connected to a plurality of data driving circuits DDC1-DDC5. Specifically, the plurality of data lines DL may include a plurality of first data lines connected to the first data driving circuit DDC1, a plurality of second data lines connected to the second data driving circuit DDC2, a plurality of third data lines connected to the third data driving circuit DDC3, a plurality of fourth data lines connected to the fourth data driving circuit DDC4, and a plurality of fifth data lines connected to the fifth data driving circuit DDC5.

[0067] The first terminals (C1, P1, D1; for example, the first cluster terminals BP1) may include a plurality of first control terminals C1, a plurality of first power supply terminals P1, and a plurality of first data terminals D1 arranged along a first direction DR1 on the first circuit board CB1. The first control terminal C1 may be connected to a timing control unit arranged on another circuit board (hereinafter, an external circuit board). The first power supply terminal P1 may be connected to a power supply unit arranged on the external circuit board. The first data terminal D1 may be connected to a first data driving circuit DDC1.

[0068] The second terminals (P2, D2; for example, the second cluster terminals BP2) may include a plurality of second power terminals P2 and a plurality of second data terminals D2 arranged along the first direction DR1 on the second circuit board CB2. The second power terminals P2 may be connected to a power supply disposed on an external circuit board. The second data terminals D2 may be connected to the second data driving circuit DDC2.

[0069] The third terminals (P3, D3; for example, the third cluster terminals BP3) may include a plurality of third power supply terminals P3 and a plurality of third data terminals D3 arranged along the first direction DR1 on the third circuit board CB3. The third power supply terminals P3 may be connected to a power supply disposed on an external circuit board. The third data terminals D3 may be connected to the third data driving circuit DDC3.

[0070] The fourth terminals (P4, D4; for example, the fourth cluster terminals BP4) may include a plurality of fourth power supply terminals P4 and a plurality of fourth data terminals D4 arranged along the first direction DR1 on the fourth circuit board CB4. The fourth power supply terminals P4 may be connected to a power supply disposed on an external circuit board. The fourth data terminals D4 may be connected to a fourth data driving circuit DDC4.

[0071] The fifth terminals (C2, P5, D5; for example, the fifth cluster terminal BP5) may include a plurality of second control terminals C2, a plurality of fifth power supply terminals P5, and a plurality of fifth data terminals D5 arranged along the first direction DR1 on the fifth circuit board CB5. The second control terminal C2 may be connected to a timing control unit arranged on the external circuit board. The fifth power supply terminal P5 may be connected to a power supply unit arranged on the external circuit board. The fifth data terminal D5 may be connected to a fifth data driving circuit DDC5.

[0072] The first terminals C1, P1, D1 of the first circuit board CB1, the second terminals P2, D2 of the second circuit board CB2, the third terminals P3, D3 of the third circuit board CB3, the fourth terminals P4, D4 of the fourth circuit board CB4, and the fifth terminals C2, P5, D5 of the fifth circuit board CB5 can be connected to the first pads C11, P11, D11 of the first cluster pad PD1, the second pads P22, D22 of the second cluster pad PD2, the third pads P33, D33 of the third cluster pad PD3, the fourth pads P44, D44 of the fourth cluster pad PD4, and the fifth pads C22, P55, D55 of the fifth cluster pad PD5 of the display panel 110, respectively.

[0073] The first terminals C1, P1, D1 can be arranged to correspond to (or overlap with) the first pads C11, P11, D11, respectively, the second terminals P2, D2 can be arranged to correspond to (or overlap with) the second pads P22, D22, respectively, the third terminals P3, D3 can be arranged to correspond to (or overlap with) the third pads P33, D33, respectively, the fourth terminals P4, D4 can be arranged to correspond to (or overlap with) the fourth pads P44, D44, respectively, and the fifth terminals C2, P5, D5 can be arranged to correspond to (or overlap with) the fifth pads C22, P55, D55, respectively.

[0074] The first pads C11, P11, and D11 may include a plurality of first control pads C11, a plurality of first power pads P11, and a plurality of first data pads D11 arranged along a first direction DR1 on the pad area PA of the display panel 110. The first control pads C11 may be connected to the first control terminals C1. The first control pads C11 may be connected to the first gate driver GD1 and the second gate driver GD2. The first power pads P11 may be connected to the first power terminals P1. The first power pads P11 may be connected to the first gate driver GD1, the first light-emitting driver ED1, and the pixels PX. The first data pads D11 may be connected to the first data terminals D1. The first data pads D11 may be connected to the first data lines.

[0075] The second pads P22, D22 may include a plurality of second power supply pads P22 and a plurality of second data pads D22 arranged along the first direction DR1 on the pad area PA of the display panel 110. The second power supply pads P22 may be connected to the second power supply terminals P2, respectively. The second power supply pads P22 may be connected to the pixels PX. The second data pads D22 may be connected to the second data terminals D2, respectively. The second data pads D22 may be connected to the second data lines, respectively. The third pads P33, D33 may include a plurality of third power supply pads P33 and a plurality of third data pads D33 arranged along the first direction DR1 on the pad area PA of the display panel 110. The third power supply pads P33 may be connected to the third power supply terminals P3, respectively. The third power supply pads P33 may be connected to the pixels PX, the third data pads D33 may be connected to the third data terminals D3, respectively. The third data pads D33 may be connected to the third data lines, respectively.

[0076] The fourth pads P44, D44 may include a plurality of fourth power supply pads P44 and a plurality of fourth data pads D44 arranged along the first direction DR1 on the pad region PA of the display panel 110. The fourth power supply pads P44 may be connected to the fourth power supply terminals P4, respectively. The fourth power supply pads P44 may be connected to the pixels PX, respectively. The fourth data pads D44 may be connected to the fourth data terminals D4, respectively. The fourth data pads D44 may be connected to the fourth data lines, respectively.

[0077] The fifth pads C22, P55, and D55 may include a plurality of second control pads C22, a plurality of fifth power supply pads P55, and a plurality of fifth data pads D55 arranged along the first direction DR1 on the pad area PA of the display panel 110. The second control pads C22 may be connected to the second control terminals C2, the fifth power supply pads P55 may be connected to the fifth power supply terminals P5, and the fifth power supply pads P55 may be connected to the pixels PX. The fifth data pads D55 may be connected to the fifth data terminals D5, and the fifth data pads D55 may be connected to the fifth data lines.

[0078] The first control pad C11 and the first gate driver GD1 may be electrically connected to each other via a corresponding fanout line FL, and the other first control pad C11 and the first light-emitting driver ED1 may be electrically connected to each other via a corresponding fanout line FL.

[0079] The second control pad C22 and the second gate driver GD2 may be electrically connected to each other via a corresponding fanout line FL, and another second control pad C22 and the second light-emitting driver ED2 may be electrically connected to each other via a corresponding fanout line FL.

[0080] The first to fifth data pads D11, D22, D33, D44, and D55 may be electrically connected to the first to fifth data lines through corresponding fanout lines FL.

[0081] A gate timing control signal, a light-emitting timing control signal, a gate clock signal, and a light-emitting clock signal from the timing controller may be supplied to the first gate driver GD1 and the first light-emitting driver ED1 via the first control terminal C1 of the first circuit board CB1 and the first control pad C11 of the display panel 110. For example, the gate timing control signal and the gate clock signal may be supplied to the first gate driver GD1, and the light-emitting timing control signal and the light-emitting clock signal may be supplied to the first light-emitting driver ED1. A power signal from the power supply may be supplied to the first gate driver GD1, the first light-emitting driver ED1, and the pixel PX via the first power terminal P1 of the first circuit board CB1 and the first power pad P11 of the display panel 110. The power signal may include, for example, a driving voltage, a common voltage, a first initialization voltage, a second initialization voltage, and a bias voltage. A data signal from the first data driver circuit DDC1 may be supplied to the first data line via the first data terminal D1 of the first circuit board CB1 and the first data pad D11 of the display panel 110.

[0082] A power signal from the power supply unit can be supplied to the pixel PX via the second power terminal P2 of the second circuit board CB2 and the second power pad P22 of the display panel 110. A data signal from the second data driving circuit DDC2 can be supplied to the second data line via the second data terminal D2 of the second circuit board CB2 and the second data pad D22 of the display panel 110.

[0083] A power signal from the power supply unit may be supplied to the pixel PX via the third power terminal P3 of the third circuit board CB3 and the third power pad P33 of the display panel 110. A data signal from the third data driving circuit DDC3 may be supplied to the third data line via the third data terminal D3 of the third circuit board CB3 and the third data pad D33 of the display panel 110.

[0084] A power signal from the power supply unit may be supplied to the pixel PX via a fourth power terminal P4 of the fourth circuit board CB4 and a fourth power pad P44 of the display panel 110. A data signal from the fourth data driving circuit DDC4 may be supplied to the fourth data line via a fourth data terminal D4 of the fourth circuit board CB4 and a fourth data pad D44 of the display panel 110.

[0085] A gate timing control signal, a light-emitting timing control signal, a gate clock signal, and a light-emitting clock signal from the timing controller may be supplied to the second gate driver GD2 and the second light-emitting driver ED2 via the second control terminal C2 of the fifth circuit board CB5 and the second control pad C22 of the display panel 110. For example, the gate timing control signal and the gate clock signal may be supplied to the second gate driver GD2, and the light-emitting timing control signal and the light-emitting clock signal may be supplied to the second light-emitting driver ED2. A power signal from the power supply may be supplied to the second gate driver GD2, the second light-emitting driver ED2, and the pixel PX via the fifth power terminal P5 of the fifth circuit board CB5 and the fifth power pad P55 of the display panel 110. A data signal from the fifth data driver circuit DDC5 may be supplied to the fifth data line via the fifth data terminal D5 of the fifth circuit board CB5 and the fifth data pad D55 of the display panel 110.

[0086] At least one first alignment key AK1 may be arranged in the non-display area NDA. For example, the first alignment key AK1 may be arranged between adjacent circuit boards in the non-display area NDA. The first alignment key AK1 may be a mark for aligning the circuit boards. The first alignment key AK1 may be used to align the circuit boards. The first alignment key AK1 may also be used to check whether the circuit boards are accurately aligned with each other. The first alignment key AK1 may have, for example, a cross shape.

[0087] 4 is a circuit diagram for a pixel of a display device according to an embodiment, for example, the pixel PX of FIG.

[0088] As shown in FIG. 4, the pixel PX may be connected to a first gate line GWL, a second gate line GCL, a third gate line GIL, a fourth gate line EBL, an emission control line EML, a data line DL, a driving voltage line VDL, a common voltage line VSL, a first initialization voltage line VIL1, a second initialization voltage line VIL2, and a bias voltage line VBL.

[0089] The pixel PX may include a pixel circuit PC and a light-emitting element LEL. The pixel circuit PC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a capacitor Cst.

[0090] The first transistor T1 may include a gate electrode, a source electrode, and a drain electrode. The first transistor T1 can control a source-drain current (hereinafter, referred to as a drive current) in response to a data voltage applied to the gate electrode. The drive current (e.g., Isd) flowing through the channel region of the first transistor T1 is proportional to the square of the difference between the voltage (Vsg) between the source electrode and gate electrode of the first transistor T1 and the threshold voltage (Vth) of the first transistor T1 (Isd=k×(Vsg-Vth)). 2) where k is a proportionality coefficient determined by the structure and physical characteristics of the first transistor T1, Vsg is the source-gate voltage of the first transistor T1, and Vth is the threshold voltage of the first transistor T1.

[0091] The light emitting element LEL receives the driving current Isd and emits light, and the amount of light emitted or the brightness of the light emitting element LEL may be proportional to the magnitude of the driving current Isd.

[0092] The light-emitting element LEL may be an organic light-emitting diode including a first electrode, a second electrode, and an organic light-emitting layer disposed between the first and second electrodes. As another example, the light-emitting element LEL may be an inorganic light-emitting element including a first electrode, a second electrode, and an inorganic semiconductor disposed between the first and second electrodes. As yet another example, the light-emitting element LEL may be a quantum dot light-emitting element including a first electrode, a second electrode, and a quantum dot light-emitting layer disposed between the first and second electrodes. As yet another example, the light-emitting element LEL may be a micro light-emitting diode.

[0093] A first electrode of the light-emitting element LEL may be electrically connected to a fourth node N4. The first electrode of the light-emitting element LEL may be connected to the drain electrode of the sixth transistor T6 and the source electrode of the seventh transistor T7 via the fourth node N4. A second electrode of the light-emitting element LEL may be connected to a common voltage line VSL. The second electrode of the light-emitting element LEL may receive a second driving voltage (VS; for example, a low-potential voltage) from the common voltage line VSL.

[0094] The second transistor T2 may be turned on by a first gate signal GW of the first gate line GWL to electrically connect the data line DL to a first node N1, which is a source electrode of the first transistor T1. The second transistor T2 may be turned on based on the first gate signal GW to supply a data voltage to the first node N1. The gate electrode of the second transistor T2 may be electrically connected to the first gate line GWL, the source electrode may be electrically connected to the data line DL, and the drain electrode may be electrically connected to the first node N1.

[0095] The third transistor T3 may be turned on by a second gate signal GC on the second gate line GCL to electrically connect the second node N2, which is the drain electrode of the first transistor T1, to the third node N3, which is the gate electrode of the first transistor T1. The third transistor T3 may be connected between the third node N3 and the second node N2. For example, the gate electrode of the third transistor T3 may be electrically connected to the second gate line GCL, the source electrode may be electrically connected to the third node N3, and the drain electrode may be electrically connected to the second node. The third transistor T3 may be turned on by a second gate signal on the second gate line GCL to electrically connect the second node N2, which is the drain electrode of the first transistor T1, to the third node N3, which is the gate electrode of the first transistor T1. The third transistor T3 may be a double-gate transistor having two gate electrodes (e.g., a gate electrode and an opposing gate electrode). The gate electrode and the opposing gate electrode may be arranged to face each other on different layers.

[0096] The fourth transistor T4 may be turned on by a third gate signal GI on the third gate line GIL to electrically connect the third node N3, which is the gate electrode of the first transistor T1, to the first initialization voltage line VIL1. The fourth transistor T4 may be connected in series between the third node N3 and the first initialization voltage line VIL1. For example, the gate electrode of the fourth transistor T4 may be electrically connected to the third gate line GIL, the source electrode may be electrically connected to the third node N3, and the drain electrode may be electrically connected to the first initialization voltage line VIL1. The fourth transistor T4 may be a double-gate transistor. The first initialization voltage line VIL1 may transmit a first initialization voltage VI1.

[0097] The fifth transistor T5 may be turned on by an emission control signal EM of the emission control line EML to electrically connect the driving voltage line VDL to a first node N1, which is the source electrode of the first transistor T1. The fifth transistor T5 may have a gate electrode electrically connected to the emission control line EML, a source electrode electrically connected to the driving voltage line VDL, and a drain electrode electrically connected to the first node N1.

[0098] The sixth transistor T6 is turned on by an emission control signal EM of the emission control line EML to electrically connect the second node N2, which is the drain electrode of the first transistor T1, to the fourth node N4, which is the first electrode of the light emitting element LEL. The sixth transistor T6 has a gate electrode electrically connected to the emission control line EML, a source electrode electrically connected to the second node N2, and a drain electrode electrically connected to the fourth node N4.

[0099] When the fifth transistor T5, the first transistor T1 and the sixth transistor T6 are all turned on, a driving current can be supplied to the light emitting element LEL.

[0100] The seventh transistor T7 may be turned on by a fourth gate signal EB of the fourth gate line EBL to electrically connect a fourth node N4, which is a first electrode of the light-emitting element LEL, to a second initialization voltage line VIL2. The seventh transistor T7 may be turned on based on the fourth gate signal to discharge the voltage supplied to the first electrode of the light-emitting element LEL to a second initialization voltage VI2. The gate electrode of the seventh transistor T7 may be electrically connected to the fourth gate line EBL, the source electrode may be electrically connected to the fourth node N4, and the drain electrode may be electrically connected to the second initialization voltage line VIL2. The second initialization voltage line VIL2 may supply the second initialization voltage VI2.

[0101] The eighth transistor T8 may be turned on by a fourth gate signal EB of the fourth gate line EBL to electrically connect the bias voltage line VBL to a first node N1, which is the source electrode of the first transistor T1. The eighth transistor T8 may be turned on based on the fourth gate signal EB to supply a bias voltage VB to the first node N1. The eighth transistor T8 may improve hysteresis of the first transistor T1 by supplying the bias voltage VB to the source electrode of the first transistor T1. The gate electrode of the eighth transistor T8 may be electrically connected to the fourth gate line EBL, the source electrode may be electrically connected to the bias voltage line VBL, and the drain electrode may be electrically connected to the first node N1.

[0102] The first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 may each include a silicon-based active layer. For example, the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 may each be a p-type transistor including an active layer made of low-temperature polycrystalline silicon (LTPS). An active layer made of low-temperature polycrystalline silicon has high electron mobility and excellent turn-on characteristics. Therefore, by including transistors with excellent turn-on characteristics, the display device 100 can stably and efficiently drive the plurality of pixels PX. The first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 may each output a current flowing into their source electrode to their drain electrode based on a gate low voltage applied to their gate electrode.

[0103] The third transistor T3 and the fourth transistor T4 may be n-type transistors including an oxide-based active layer. The transistor including the oxide-based active layer may have a coplanar structure with a gate electrode disposed thereon. The transistor including the oxide-based active layer may output a current flowing into the drain electrode to the source electrode based on a gate high voltage applied to the gate electrode.

[0104] The capacitor Cst may be electrically connected between a third node N3, which is the gate electrode of the first transistor T1, and the driving voltage line VDL. For example, a first electrode of the capacitor Cst is electrically connected to the third node N3, and a second electrode of the capacitor Cst is electrically connected to the driving voltage line VDL, thereby maintaining a potential difference between the driving voltage line VDL and the gate electrode of the first transistor T1.

[0105] FIG. 5 is a cross-sectional view showing a display device according to an embodiment.

[0106] 5, the display device 100 may include a substrate SUB, a barrier layer BR, a thin film transistor layer TFTL, a light-emitting element layer EMTL, and an encapsulation layer ENC. The barrier layer BR, the thin film transistor layer TFTL, the light-emitting element layer EMTL, and the encapsulation layer ENC may be sequentially disposed on the substrate SUB along a third direction DR3.

[0107] The substrate SUB may be a rigid substrate or a flexible substrate that allows bending, folding, rolling, etc. The substrate SUB is made of an insulating material such as glass, quartz, or polymer resin. Examples of polymer materials include polyethersulfone (PES), polyacrylate (PA), polyarylate (PAR), polyetherimide (PEI), polyethylene napthalate (PEN), polyethylene terepthalate (PET), polyphenylene sulfide (PPS), polyallylate, polyimide (PI), polycarbonate (PC), cellulose triacetate (CAT), cellulose acetate propionate (CAP), or a combination thereof. Alternatively, the substrate SUB may include a metallic material.

[0108] 5, a barrier layer BR may be disposed on the substrate SUB. The barrier layer BR may be disposed on the entire surface of the substrate SUB. The barrier layer BR may be a film for protecting the transistors T1-T8 of the thin film transistor layer TFTL and the light-emitting layer EL of the light-emitting element layer EMTL from moisture that may penetrate through the substrate SUB, which is susceptible to moisture permeation.

[0109] The barrier layer BR is made of a plurality of inorganic layers stacked alternately. For example, the barrier layer BR may be formed of a multilayer structure (e.g., a first barrier layer BR1 and a second barrier layer BR2) in which one or more inorganic layers selected from the group consisting of silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, and aluminum oxide are stacked alternately.

[0110] A first pattern layer may be disposed on the barrier layer BR. For example, a light-shielding layer BML may be disposed on the barrier layer BR. The light-shielding layer BML may be disposed on the barrier layer BR so as to cover an overlapping region (e.g., a first channel region CH1) between the first gate electrode GE1 and the first active layer ACT1. For example, the light-shielding layer BML may be disposed on the barrier layer BR so as to overlap with the channel region CH1 of the first transistor T1, which is a drive transistor.

[0111] The light-shielding layer BML is made of a metal material such as chromium (Cr) or molybdenum (Mo), or black ink or black dye. If the light-shielding layer BML is made of a metal material, the light-shielding layer BML may be supplied with a positive power source. This prevents the light-shielding layer BML from floating electrically, allowing the transistor (e.g., first transistor T1) on the light-shielding layer BML to stabilize its electrical characteristics.

[0112] A buffer layer BF may be disposed on the light-shielding layer BML. The buffer layer BF may be disposed on the entire surface of the substrate SUB including the barrier layer BR. The buffer layer BF may be a film for protecting the transistors T1-T8 of the thin film transistor layer TFTL and the light-emitting layer EL of the light-emitting element layer EMTL from moisture that may penetrate through the substrate SUB, which is susceptible to moisture permeation.

[0113] The buffer layer BF may be formed of a multi-layer structure (e.g., a first buffer layer BR1 and a second buffer layer BR2) in which one or more inorganic layers selected from the group consisting of silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, and aluminum oxide are alternately stacked.

[0114] A second pattern layer may be disposed on the buffer layer BF. For example, a first active layer ACT1 may be disposed on the barrier layer BR. The first active layer ACT1 may include a first channel region CH1 of the first transistor T1, a second electrode E12 of the first transistor T1, a first electrode E61 of the sixth transistor T6, a second electrode E62 of the sixth transistor T6, and a sixth channel region CH6 of the sixth transistor T6.

[0115] The first active layer ACT1 may be an active layer made of low temperature polycrystalline silicon (LTPS).

[0116] A first gate insulating layer GTI1 may be disposed on the second pattern layer. For example, the first gate insulating layer GTI1 may be disposed on the first active layer ACT1. In this case, the first gate insulating layer GTI1 may be disposed over the entire surface of the substrate SUB including the first active layer ACT1.

[0117] The first gate insulating layer GTI1 may include at least one of tetraethoxysilane (tetraethylorthosilicate, TEOS), silicon nitride (SiNx), and silicon oxide (SiO2). For example, the first gate insulating layer GTI1 may have a double-layer structure in which a silicon nitride layer having a thickness of 40 nm and a tetraethoxysilane layer having a thickness of 80 nm are stacked in order.

[0118] A third pattern layer may be disposed on the first gate insulating layer GTI1. For example, the second gate electrode GE2, the first gate electrode GE1, the eighth gate electrode GE8, the emission control line EML, the fifth gate electrode GE5, and the sixth gate electrode GE6 may be disposed on the first gate insulating layer GTI1.

[0119] 5 shows an example in which the first gate electrode GE1, the sixth gate electrode GE6, and the emission control line EML are arranged on the first gate insulating layer GTI1. The first gate electrode GE1 can be arranged on the first gate insulating layer GTI1 so as to overlap with the first channel region CH1 of the first active layer ACT1. The sixth gate electrode GE6 of the emission control line EML can be arranged on the first gate insulating layer GTI1 so as to overlap with the sixth channel region CH6 of the first active layer ACT1.

[0120] The third pattern layer includes at least one of molybdenum (Mo), copper (Cu), aluminum, and titanium (Ti) and is formed as a single layer or multiple layers. For example, the first gate electrode GE1 includes a triple layer including a titanium layer, an aluminum layer, and a titanium layer sequentially disposed on the first gate insulating layer GTI1 along the third direction DR3.

[0121] A second gate insulating layer GTI2 may be disposed on the third pattern layer. For example, the second gate insulating layer GTI2 may be disposed on the first gate electrode GE1, the sixth gate electrode GE6, and the emission control line EML. The second gate insulating layer GTI2 may be disposed over the entire surface of the substrate SUB, including the first gate electrode GE1, the sixth gate electrode GE6, and the emission control line EML.

[0122] The second gate insulating layer GTI2 may include the same material and structure as the first gate insulating layer GTI1.

[0123] A fourth pattern layer may be disposed on the second gate insulating layer GTI2. For example, a fourth opposing gate electrode GEb4, a third opposing gate electrode GEb3, and a capacitor electrode CPE may be disposed on the second gate insulating layer GTI2. FIG. 5 shows an example in which the capacitor electrode CPE and the third opposing gate electrode GEb3 are disposed on the second gate insulating layer GTI2. The capacitor electrode CPE may be disposed on the second gate insulating layer GTI2 so as to overlap with the first gate electrode GE1. A capacitor Cst may be formed between the capacitor electrode CPE and the first gate electrode GE1.

[0124] The fourth pattern layer can have the same material or structure as the third pattern layer.

[0125] A first interlayer insulating layer ITL1 may be disposed on the fourth pattern layer. For example, the first interlayer insulating layer ITL1 may be disposed on the capacitor electrode CPE and the third opposing gate electrode GEb3. In this case, the first interlayer insulating layer ITL1 may be disposed over the entire surface of the substrate SUB including the capacitor electrode CPE and the third opposing gate electrode GEb3.

[0126] The first interlayer insulating layer ITL1 may include an inorganic film such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. Note that the first interlayer insulating layer ITL1 may include a plurality of inorganic films.

[0127] A fifth pattern layer may be disposed on the first interlayer insulating layer ITL1. For example, a second active layer ACT2 may be disposed on the first interlayer insulating layer ITL1. The second active layer ACT2 may be disposed on the first interlayer insulating layer ITL1 to overlap with the third opposing gate electrode GEb3. The second active layer ACT2 may include a first electrode E31 of the third transistor T3, a second electrode E32 of the third transistor T3, and a third channel region CH3 of the third transistor T3. The third channel region CH3 of the second active layer ACT2 may overlap with the third opposing gate electrode GEb3.

[0128] The second active layer ACT2 may be an oxide-based active layer, for example, an oxide semiconductor including indium-gallium-zinc-oxide (IGZO) or indium-gallium-zinc-tin-oxide (IGZTO).

[0129] A third gate insulating layer GTI3 may be disposed on the fifth pattern layer. For example, the third gate insulating layer GTI3 may be disposed on the second active layer ACT2. The third gate insulating layer GTI3 may be disposed over the entire surface of the substrate SUB including the second active layer ACT2.

[0130] The third gate insulating layer GTI3 may have the same material and structure as the first gate insulating layer GTI1.

[0131] A sixth pattern layer may be disposed on the third gate insulating layer GTI3. For example, a fourth gate electrode GE4 and a third gate electrode GE3 may be disposed on the third gate insulating layer GTI3.

[0132] 5 shows an example in which the third gate electrode GE3 is arranged on the third gate insulating layer GTI3. The third gate electrode GE3 can be arranged to overlap with the third channel region CH3 of the second active layer ACT2.

[0133] The sixth pattern layer can have the same material or structure as the third pattern layer.

[0134] A second interlayer insulating layer ITL2 may be disposed on the sixth pattern layer. For example, the second interlayer insulating layer ITL2 may be disposed on the third gate electrode GE3. The second interlayer insulating layer ITL2 may be disposed over the entire surface of the substrate SUB including the third gate electrode GE3.

[0135] The second interlayer insulating layer ITL2 may have the same material and structure as the first interlayer insulating layer ITL1.

[0136] A seventh pattern layer may be disposed on the second interlayer insulating layer ITL2. For example, the first initialization voltage line VIL1, the third gate line GIL, the data connecting electrode DCE, the first gate line GWL, the second gate line GCL, the gate connecting electrode GCE, the active connecting electrode ACE, the bias voltage line VBL, the capacitor connecting electrode CCE, the lower pixel connecting electrode PCEa, the fourth gate line EBL, and the second initialization voltage line VIL2 may be disposed on the second interlayer insulating layer ITL2.

[0137] 5 illustrates an example in which the gate connecting electrode GCE, the active connecting electrode ACE, the bias voltage line VBL, and the lower pixel connecting electrode PCEa are disposed on the second interlayer insulating layer ITL2. The lower pixel connecting electrode PCEa may be connected to the second electrode E62 of the sixth transistor T6 via a first contact hole CT1 that penetrates the second interlayer insulating layer ITL2, the third gate insulating layer GTI3, the first interlayer insulating layer ITL1, the second gate insulating layer GTI2, and the first gate insulating layer GTI1. The active connecting electrode ACE may be connected to the second electrode E12 of the first transistor T1 and the first electrode E61 of the sixth transistor T6 via a second contact hole CT2 that penetrates the second interlayer insulating layer ITL2, the third gate insulating layer GTI3, the first interlayer insulating layer ITL1, the second gate insulating layer GTI2, and the first gate insulating layer GTI1. The active connecting electrode ACE may be connected to the second electrode E32 of the third transistor T3 via a fifth contact hole CT5 that penetrates the second interlayer insulating layer ITL2 and the third gate insulating layer GTI3. The gate connecting electrode GCE may be connected to the first gate electrode GE1 via a third contact hole CT3 that penetrates the second interlayer insulating layer ITL2, the third gate insulating layer GTI3, the first interlayer insulating layer ITL1, the hole 40 of the capacitor electrode CPE, and the second gate insulating layer GTI2. The gate connecting electrode GCE may be connected to the first electrode E31 of the third transistor T3 via a fourth contact hole CT4 that penetrates the second interlayer insulating layer ITL2 and the third gate insulating layer GTI3.

[0138] The seventh pattern layer can have the same material or structure as the third pattern layer.

[0139] A first planarization layer VA1 may be disposed on the seventh pattern layer. For example, the first planarization layer VA1 may be disposed on the gate connecting electrode GCE, the active connecting electrode ACE, the bias voltage line VBL, and the lower pixel connecting electrode PCEa. The first planarization layer VA1 may be disposed over the entire surface of the substrate SUB, including the gate connecting electrode GCE, the active connecting electrode ACE, the bias voltage line VBL, and the lower pixel connecting electrode PCEa.

[0140] The first planarization layer VA1 may include an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0141] An eighth pattern layer may be disposed on the first planarization layer VA1. For example, the first data line DL1, the driving voltage line VDL, and the upper pixel connecting electrode PCEb may be disposed on the second interlayer insulating layer ITL2. FIG. 5 shows an example in which the driving voltage line VDL and the upper pixel connecting electrode PCEb are disposed on the first planarization layer VA1.

[0142] The upper pixel connecting electrode PCEb may be connected to the lower pixel connecting electrode PCEa through a sixth contact hole CT6 that penetrates the first planarization layer VA1.

[0143] The eighth pattern layer can have the same material or structure as the third pattern layer.

[0144] A second planarization layer VA2 may be disposed on the eighth pattern layer. For example, the second planarization layer VA2 may be disposed on the driving voltage line VDL and the upper pixel connecting electrode PCEb. The second planarization layer VA2 may be disposed over the entire surface of the substrate SUB, including the driving voltage line VDL and the upper pixel connecting electrode PCEb.

[0145] The second planarization layer VA2 may have the same material and structure as the first planarization layer VA1.

[0146] A ninth pattern layer may be disposed on the second planarization layer VA2. For example, a light emitting element layer EMTL including the ninth pattern layer may be disposed on the second planarization layer VA2. For example, a pixel electrode PE may be disposed as the ninth pattern layer on the third planarization layer VA3. The pixel electrode PE may be connected to the upper pixel connecting electrode PCEb via a seventh contact hole CT7 penetrating the second planarization layer VA2.

[0147] The light emitting element layer EMTL may further include a light emitting element LEL and a bank (PDL; or pixel defining layer) in addition to the ninth pattern layer.

[0148] The light-emitting element LEL may include a pixel electrode PE, an emitting layer EL, and a common electrode CM. The emitting area EA refers to the area where the pixel electrode PE, the emitting layer EL, and the common electrode CM are sequentially stacked, and where holes from the pixel electrode PE and electrons from the common electrode CM are combined in the emitting layer to emit light. In this case, the pixel electrode PE may be the anode electrode of the light-emitting element LEL, and the common electrode CM may be the cathode electrode of the light-emitting element LEL.

[0149] In a top emission structure that emits light from the light-emitting layer EL toward the common electrode CM, the pixel electrode PE can be formed of a single layer of molybdenum (Mo), titanium (Ti), copper (Cu), or aluminum (Al), or to increase reflectivity, it can be formed of a laminated structure of aluminum and titanium (Ti / Al / Ti), a laminated structure of aluminum and ITO (ITO / Al / ITO), APC alloy, or a laminated structure of APC alloy and ITO (ITO / APC / ITO). APC alloy is an alloy of silver (Ag), palladium (Pd), and copper (Cu).

[0150] The bank PDL may serve to define the light-emitting area EA of the pixel PX. To this end, the bank PDL may be disposed on the third planarization layer VA3 to expose a portion of the pixel electrode PE. The bank PDL may cover the edge of the pixel electrode PE. The bank PDL may also be disposed in a seventh contact hole CT7 penetrating the third planarization layer VA3. This allows the seventh contact hole CT7 penetrating the third planarization layer VA3 to be filled with the bank PDL. The bank PDL may be formed of an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0151] A spacer SPC may be disposed on the bank PDL. The spacer SPC can serve to support a mask during the process of manufacturing the light-emitting layer EL. The spacer SPC may be formed of an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0152] An emitting layer EL may be formed on the pixel electrode PE. The emitting layer EL may include an organic material and emit a predetermined color. For example, the emitting layer EL may include a hole transporting layer, an organic material layer, and an electron transporting layer. The organic material layer may include a host and a dopant. The organic material layer may include a material that emits a predetermined light, and may be formed using a phosphorescent material or a fluorescent material.

[0153] The light-emitting element LEL is provided for each pixel PX. For example, the first pixel may include a first light-emitting element, the second pixel may include a second light-emitting element, and the third pixel may include a third light-emitting element. The first light-emitting element, the second light-emitting element, and the third light-emitting element may provide light of different colors. For example, the first light-emitting element may emit light of a first color, the second light-emitting element may emit light of a second color, and the third light-emitting element may emit light of a third color.

[0154] For example, the light-emitting layer of the first light-emitting element emitting light of the first color may be a phosphorescent material including a host material including CBP (carbazole biphenyl) or mCP (1,3-bis(carbazol-9-yl)) and a dopant including at least one selected from PIQIr(acac) (bis(1-phenylisoquinoline)acetylacetonate iridium), PQIr(acac) (bis(1-phenylquinoline)acetylacetonate iridium), PQIr (tris(1-phenylquinoline)iridium), and PtOEP (octaethylporphyrin platinum). Alternatively, the light-emitting layer of the first light-emitting element emitting light of the first color may be a fluorescent material including, but not limited to, PBD:Eu(DBM)3(Phen) or Perylene.

[0155] The light-emitting layer of the second light-emitting element emitting light of the second color may be a phosphorescent material containing a host material including CBP or mCP and a dopant material including Ir(ppy)3 (fac tris(2-phenylpyridine)iridium), or may be a fluorescent material containing Alq3 (tris(8-hydroxyquinolino)aluminum), but is not limited thereto.

[0156] The light-emitting layer of the third light-emitting element emitting light of a third color may be a phosphorescent material including a host material including CBP or mCP and a dopant material including (4,6-F2ppy)2Irpic or L2BD111, but is not limited thereto.

[0157] A common electrode CM may be disposed on each light-emitting layer (e.g., EL). The common electrode CM may be disposed so as to cover each light-emitting layer EL. The common electrode CM may be a common layer disposed in common to each pixel PX. A capping layer may also be formed on the common electrode CM.

[0158] In the top emission structure, the common electrode CM can be made of a transparent conductive material (TCO) such as ITO or IZO, which transmits light, or a semi-transmissive metallic material such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag).When the common electrode CM is made of a semi-transmissive metallic material, the light output efficiency increases due to the microcavities.

[0159] The encapsulation layer ENC may be disposed on the light-emitting element layer EMTL. The encapsulation layer ENC may include at least one inorganic film TFE1, TFE3 to prevent oxygen or moisture from penetrating into the light-emitting element layer EMTL. The encapsulation layer ENC may also include at least one organic film TFE2 to protect the light-emitting element layer EMTL from foreign matter such as dust. For example, the encapsulation layer ENC may include a first encapsulation inorganic film TFE1, an encapsulation organic film TFE2, and a second encapsulation inorganic film TFE3.

[0160] The first sealing inorganic film TFE1 may be disposed on the common electrode CM, the sealing organic film TFE2 may be disposed on the first sealing inorganic film TFE1, and the second sealing inorganic film TFE3 may be disposed on the sealing organic film TFE2. The first sealing inorganic film TFE1 and the second sealing inorganic film TFE3 may be formed of a multi-layer structure in which one or more inorganic films selected from the group consisting of silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, and aluminum oxide are alternately stacked. The sealing organic film TFE2 may be an organic film such as an acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0161] 6 is a plan view showing a non-display area of ​​a display device according to an embodiment, illustrating a portion between the pad area PA where the second cluster pads PD2 of FIG. 3 are arranged and the display area DA.

[0162] Referring to FIG. 6, the non-display area NDA may include a first voltage line VDD1, a second voltage line VDD2, a common line VSS, a data routing line DRL, and a test circuit unit IPA.

[0163] The first voltage wiring VDD1 may transmit a driving voltage applied from the circuit board ("200" in FIG. 1) via the second voltage wiring VDD2. The driving voltage of the first voltage wiring VDD1 may be transmitted to the driving voltage line VDL in the display area DA. The first voltage wiring VDD1 may extend in a first direction DR1 below the display area DA.

[0164] The second voltage wiring VDD2 may be disposed between the pad area PA and the first voltage wiring VDD1. The second voltage wiring VDD2 may extend in the second direction DR2 to connect the pad area PA and the first voltage wiring VDD1. A plurality of second voltage wirings VDD2 may be provided. For example, the second voltage wirings VDD2 may be disposed on both sides of the inspection circuit unit IPA, but are not limited to this. The second voltage wiring VDD2 may transmit a driving voltage applied from the circuit board ("200" in FIG. 1) to the first voltage wiring VDD1.

[0165] The common line VSS may be disposed between the pad area PA and the first voltage line VDD1. The common line VSS may extend in the second direction DR2 to connect the pad area PA and the display area DA. A plurality of common lines VSS may be provided. For example, two common lines VSS may be disposed on each side of the testing circuit unit IPA, but this is not limiting. For example, the common lines VSS may be disposed adjacent to each other with the second voltage line VDD2 interposed therebetween. The common line VSS may supply a low potential voltage applied from the circuit board to the common voltage line VSL of the display area DA.

[0166] The data routing wiring DRL may extend from the display area DA to the testing circuit section IPA. The data routing wiring DRL may be connected to the data lines ("DL" in FIG. 4) of the display area DA and extend to the testing circuit section IPA. The data routing wiring DRL may pass through the testing circuit section IPA and extend to the pad area PA. For example, the data routing wiring DRL may pass through the testing circuit section IPA. The data routing wiring DRL may supply a data voltage applied from the circuit board to the data lines DL of the display area DA.

[0167] The inspection circuit unit IPA may be a circuit unit for detecting whether the pixels PX are normal. The inspection circuit unit IPA may apply an inspection signal to the data routing lines DRL extending from the display area DA to inspect whether the pixels PX of the display area DA emit light normally. The inspection circuit unit IPA may be disposed between the display area DA and the pad area PA.

[0168] Fig. 7 is an enlarged plan view of region A in Fig. 6. Fig. 8 is a plan view showing an inspection circuit unit according to one embodiment.

[0169] 7 and 8, the inspection circuit unit IPA may include data routing lines DRL that supply data signals.

[0170] The data routing lines DRL may include a first routing line DRL1, a second routing line DRL2, and a third routing line DRL3. Each of the routing lines DRL1, DRL2, and DRL3 may be connected to a data line DL of a corresponding pixel PX to supply a data signal.

[0171] The test circuit unit IPA may supply a test signal to the data routing line DRL. For example, the test circuit unit IPA may include a first test transistor TT1 electrically connected between a first test signal supply line TSL1 that supplies a first test signal and the first routing line DRL1, a second test transistor TT2 electrically connected between the first test signal supply line TSL1 and the second routing line DRL2, and a third test transistor TT3 electrically connected between the second test signal supply line TSL2 and a third routing line DRL3.

[0172] The first inspection transistor TT1 may include a first inspection active layer T1A, a first inspection gate T1G, and first, second, and third connection patterns CE1, CE2, and CE3. The first inspection gate T1G may be electrically connected to a first inspection control line TSCL1. One end of the first inspection active layer T1A may be electrically connected to a first routing line DRL1 via a first connection pattern CE1. The other end of the first inspection active layer T1A may be connected to a third connection pattern CE3 via a second connection pattern CE2, and the third connection pattern CE3 may be electrically connected to a first inspection signal supply line TSL1.

[0173] The second inspection transistor TT2 may include a second inspection active layer T2A, a first inspection gate T1G, and fourth to sixth connecting patterns CE4, CE5, and CE6. One end of the second inspection active layer T2A may be electrically connected to the second routing line DRL2 via the fourth connecting pattern CE4. The other end of the second inspection active layer T2A may be connected to the sixth connecting pattern CE6 via the fifth connecting pattern CE5, and the sixth connecting pattern CE6 may be electrically connected to the first inspection signal supply line TSL1.

[0174] The third inspection transistor TT3 may include a third inspection active layer T3A, a second inspection gate T2G, and seventh to ninth connecting patterns CE7, CE8, and CE9. The second inspection gate T2G may be electrically connected to the first inspection control line TSCL1. One end of the third inspection active layer T3A may be electrically connected to the third routing line DRL3 via the seventh connecting pattern CE7. The other end of the third inspection active layer T3A may be connected to the ninth connecting pattern CE9 via the eighth connecting pattern CE8, and the ninth connecting pattern CE9 may be electrically connected to the second inspection signal supply line TSL2.

[0175] The first inspection transistor TT1, the second inspection transistor TT2, and the third inspection transistor TT3 can be turned on by a first inspection control signal on a first inspection control line TSCL1. For example, the inspection circuit unit IPA of the display device 100 turns on the first inspection transistor TT1, the second inspection transistor TT2, and the third inspection transistor TT3 by a first inspection control signal supplied via the same first inspection control line TSCL1. In addition, the first inspection transistor TT1 and the second inspection transistor TT2 can be supplied with the same first inspection signal via the same first inspection signal supply line TSL1. Therefore, a lighting inspection can be performed to detect whether the pixels PX electrically connected to the data routing lines DRL1, DRL2, and DRL3, respectively, are emitting light normally.

[0176] The inspection circuit unit IPA may also include a fourth inspection transistor TT4 electrically connected between a third inspection signal supply wiring TSL3 that supplies a third inspection signal and the first routing wiring DRL1, a fifth inspection transistor TT5 electrically connected between the fourth inspection signal supply wiring TSL4 and the second routing wiring DRL2, and a sixth inspection transistor TT6 electrically connected between the fifth inspection signal supply wiring TSL5 and the third routing wiring DRL3.

[0177] The fourth inspection transistor TT4 may include a fourth inspection active layer T4A, a third inspection gate T3G, and a tenth connecting pattern CE10. The third inspection gate T4G may be electrically connected to the second inspection control line TSCL2. One end of the fourth inspection active layer T4A may be electrically connected to the first routing line DRL1 via the tenth connecting pattern CE10. The other end of the fourth inspection active layer T4A may be electrically connected to the third inspection signal supply line TSL3.

[0178] The fifth inspection transistor TT5 may include a fifth inspection active layer T5A, a third inspection gate T3G, and an eleventh connecting pattern CE11. The third inspection gate T3G may be electrically connected to the second inspection control line TSCL2. One end of the fifth inspection active layer T5A may be electrically connected to the second routing line DRL2 via the eleventh connecting pattern CE11. The other end of the fifth inspection active layer T5A may be electrically connected to the fourth inspection signal supply line TSL4.

[0179] The sixth inspection transistor TT6 may include a sixth inspection active layer T6A, a third inspection gate T3G, and a twelfth connecting pattern CE12. The third inspection gate T4G may be electrically connected to the second inspection control line TSCL2. One end of the sixth inspection active layer T6A may be electrically connected to the third routing line DRL3 via the twelfth connecting pattern CE12. The other end of the sixth inspection active layer T6A may be electrically connected to the fifth inspection signal supply line TSL5.

[0180] The fourth inspection transistor TT4, the fifth inspection transistor TT5, and the sixth inspection transistor TT6 can be turned on by a second inspection control signal on the second inspection control line TSCL2. For example, the inspection circuit unit IPA of the display device 100 turns on the fourth inspection transistor TT4, the fifth inspection transistor TT5, and the sixth inspection transistor TT6 by a first inspection control signal supplied via the same second inspection control line TSCL2.

[0181] The fourth, fifth, and sixth inspection transistors TT4, TT5, and TT6 may be supplied with different inspection signals via a third inspection signal supply line TSL3, a fourth inspection signal supply line TSL4, and a fifth inspection signal supply line TSL5, respectively.

[0182] Therefore, it is possible to perform a lighting test to detect whether the pixels PX electrically connected to the respective routing lines DRL1, DRL2, and DRL3 are emitting light normally.

[0183] The data routing lines DRL1, DRL2, and DRL3 can be connected to the second data pad D22 in the pad area PA.

[0184] FIG. 9 is a cross-sectional view taken along the line Q1-Q1' in FIG.

[0185] Referring to FIG. 9, the non-display area NDA may include a first routing line DRL1, a fifth inspection signal supply line TSL5, a first connecting electrode CNE1, and a second data pad D22.

[0186] Specifically, a barrier layer BR, a buffer layer BF, and a thin film transistor layer TFTL may be sequentially disposed on a substrate SUB in the third direction DR3. For example, a first barrier layer BR1, a second barrier layer BR2, a first buffer layer BF1, a second buffer layer BF2, and a first gate insulating layer GTI1 may be disposed on the substrate SUB.

[0187] A first routing line DRL1 may be arranged on the first gate insulating layer GTI1, and a second gate insulating layer GTI2, a first interlayer insulating layer ITL1, a third gate insulating layer GTI3, and a second interlayer insulating layer ITL2 may be arranged on the first routing line DRL1.

[0188] The first connecting electrode CNE1, the second data pad D22, and the fifth inspection signal supply line TSL5 may be disposed on the second interlayer insulating layer ITL2.

[0189] The first connecting electrode CNE1 may be in direct contact with the first routing line DRL1 through a first contact hole CT1 that penetrates the second gate insulating layer GTI2, the first interlayer insulating layer ITL1, the third gate insulating layer GTI3, and the second interlayer insulating layer ITL2.

[0190] The second data pad D22 may be disposed on the first connecting electrode CNE1 through the first contact hole CT1. The second data pad D22 may be disposed on the first connecting electrode CNE1 in direct contact therewith, and thus may be electrically connected to the first routing line DRL1.

[0191] The fifth inspection signal supply wiring TSL5 may be disposed directly on the second interlayer insulating layer ITL2. The fifth inspection signal supply wiring TSL5 may be the wiring closest to the pad area PA in the inspection circuit unit IPA. The fifth inspection signal supply wiring TSL5 may cross the data routing wiring DRL on a plane.

[0192] A first planarization layer VA1 may be disposed on the fifth inspection signal supply wiring TSL5. The first planarization layer VA1 may extend from the display area DA to the non-display area NDA. For example, the first planarization layer VA1 may extend to the inspection circuit unit IPA in the non-display area NDA. The first planarization layer VA1 may be disposed on the fifth inspection signal supply wiring TSL5 and directly cover the fifth inspection signal supply wiring TSL5. The first planarization layer VA1 may be disposed in the non-display area NDA and may not overlap with the pad area PA. For example, the first planarization layer VA1 may be disposed such that its side edges do not overlap with the pad area PA. The side edges of the first planarization layer VA1 may be disposed spaced apart from the pad area PA on a plane.

[0193] A second planarization layer VA2 may be disposed on the first planarization layer VA1 and the second data pad D22. The second planarization layer VA2 may extend from the display area DA to the non-display area NDA. For example, the second planarization layer VA2 may extend to the test circuit area IPA and the pad area PA. The second planarization layer VA2 may directly cover the second data pad D22.

[0194] The second planarization layer VA2 may include a first region FTL and a second region HTL. For example, in a plan view, the first region FTL may not overlap the pad region PA and may overlap the fifth inspection signal supply wiring TSL5. For example, in a plan view, the first region FTL may cover the fifth inspection signal supply wiring TSL5. In a plan view, the first region FTL may not overlap the second data pad D22, and the second region HTL may overlap the pad region PA and may overlap the second data pad D22.

[0195] The thickness of the first region FTL may be greater than the thickness of the second region HTL. Here, the thickness may be measured in the third direction DR3 from the top surface of the substrate SUB. In other words, the height of the top surface of the first region FTL measured in the third direction DR3 from the top surface of the substrate SUB may be greater than the height of the top surface of the second region HTL. The first region FTL may be a region formed in full tone in the process of forming the second planarization layer VA2, and the second region HTL may be a region formed in half tone.

[0196] In a plan view, the side of the first region FTL may be spaced apart from the pad region PA. The first region FTL is thick and may prevent the pad region PA from connecting to the circuit board. Therefore, in this embodiment, the side of the first region FTL is spaced apart from the pad region PA, which facilitates connection between the pad and the circuit board.

[0197] A side edge of the first region FTL may be disposed between the fifth inspection signal supply line TSL5 and the pad region PA in a plan view. For example, a side edge of the first region FTL may be disposed spaced apart from the fifth inspection signal supply line TSL5 in a direction adjacent to the pad region PA. The fifth inspection signal supply line TSL5 is made of a metal material and is easily corroded by moisture and air. In this embodiment, the first region FTL of the second planarization layer VA2 is formed to cover the fifth inspection signal supply line TSL5 in a plan view, and the side edge of the first region FTL is disposed spaced apart from the fifth inspection signal supply line TSL5 in a direction adjacent to the pad region PA, thereby preventing the fifth inspection signal supply line TSL5 from being corroded by external moisture and air.

[0198] In addition, the side of the first region FTL may be disposed between the side of the first planarization layer VA1 and the fifth inspection signal supply wiring TSL5. For example, the side of the first region FTL may be disposed between the side of the fifth inspection signal supply wiring TSL5 and the side of the first planarization layer VA1.

[0199] In a plan view, the second region HTL may overlap a portion of the first planarization layer VA1. For example, in a plan view, a side edge of the first planarization layer VA1 may overlap the second region HTL. The second region HTL may be thinner than the first region FTL. The second region HTL may be disposed in the pad region PA to facilitate electrical connection between the pad and the circuit board.

[0200] Fig. 10 is a plan view showing a part of a test circuit unit and a pad area of ​​a display device according to an embodiment. Fig. 11 is a cross-sectional view taken along line Q2-Q2' in Fig. 10. Figs. 10 and 11 show the pad area PA in more detail than that shown in Fig. 9.

[0201] 10 and 11, the first planarization layer VA1 may be disposed in the non-display area NDA such that its side does not overlap with the pad area PA. The first planarization layer VA1 may be disposed apart from the pad contact hole PCH formed in the pad area PA.

[0202] In a plan view, the second planarization layer VA2 may include a pad contact hole PCH overlapping the second data pad D22. The pad contact hole PCH may be an opening disposed in the pad area PA and exposing the top surface of the second data pad D22. The pad contact hole PCH may be an area that was not exposed during the formation of the second planarization layer VA2 and was removed by a developer.

[0203] In a plan view, the pad contact hole PCH may be arranged so as not to overlap with the first connecting electrode CNE1 and the first routing line DRL1. In a plan view, the pad contact hole PCH may be arranged so as to overlap with the second region HTL of the second planarization layer VA2, but not to overlap with the first region FTL.

[0204] As described above, in the display device 100 according to an embodiment, the first region FTL of the second planarization layer VA2 may be formed to cover the inspection signal supply wiring (e.g., the fifth inspection signal supply wiring) that is closest to the pad region PA in the inspection circuit unit IPA, thereby protecting the inspection signal supply wiring from external moisture and air and preventing corrosion of the inspection signal supply wiring.

[0205] 12 to 14 are views illustrating a method for manufacturing a display device according to an embodiment of the present invention, each showing a process for manufacturing the second planarization layer VA2 in the structure corresponding to FIG.

[0206] 12, a substrate SUB is prepared. The substrate SUB may be formed by sequentially forming the barrier layer BR, the buffer layer BF, and the first planarization layer VA1 of the thin film transistor layer TFTL described above in FIG. 11. For example, the fifth inspection signal supply line TSL5, the first connecting electrode CNE1, and the second data pad D22 may be formed on the second interlayer insulating layer ITL2, and the first planarization layer VA1 may be formed on the fifth inspection signal supply line TSL5.

[0207] A planarization material layer VAL is formed on the substrate SUB. The planarization material layer VAL is a layer for forming a second planarization layer VA2 and may be formed to cover the first planarization layer VA1 and the second data pad D22. The planarization material layer VAL may be photosensitive.

[0208] 13, a mask MS is aligned on the substrate SUB. The mask MS may include a first portion FT, a second portion HT, and a third portion OT. The first portion FT may be a transmissive portion that completely transmits UV light. The second portion HT may be a semi-transmissive portion that controls the amount of UV light transmitted. The third portion OT may be a blocking portion that blocks UV light.

[0209] In this embodiment, the first portion FT of the mask is formed to overlap the fifth inspection signal supply wiring TSL5, and the first region FTL of the second planarization layer VA2 is formed to cover the fifth inspection signal supply wiring TSL5, as will be described later.

[0210] Next, UV exposure is performed on the top of the mask MS. The area of ​​the planarizing material layer VAL corresponding to the first portion FT of the mask MS is fully exposed to UV light. The area of ​​the planarizing material layer VAL corresponding to the second portion HT of the mask MS is partially exposed to UV light. The area of ​​the planarizing material layer VAL corresponding to the third portion OT of the mask MS is blocked from UV light and is not exposed.

[0211] Next, referring to FIG. 14, the substrate SUB is heat-treated, and then the planarizing material layer VAL is developed to form a second planarizing layer VA2.

[0212] Specifically, the area of ​​the planarization material layer VAL corresponding to the first portion FT of the mask MS has its chemical properties changed by UV light and remains undissolved in the developer. This is therefore formed as the first region FTL of the second planarization layer VA2. The area of ​​the planarization material layer VAL corresponding to the second portion HT of the mask MS has its chemical properties changed only partially by UV light and remains only partially dissolved in the developer, leaving a relatively thin layer. This is therefore formed as the second region HTL of the second planarization layer VA2. The area of ​​the planarization material layer VAL corresponding to the third portion OT of the mask MS is not exposed to UV light and is completely dissolved and removed by the developer. This is therefore formed as the pad contact hole PCH of the second planarization layer VA2.

[0213] Therefore, a second planarization layer VA2 including the first region FTL, the second region HTL, and the pad contact hole PCH can be formed. The first region FTL of the second planarization layer VA2 is formed to cover the fifth inspection signal supply line TSL5, thereby preventing the fifth inspection signal supply line TSL5 from being corroded by external moisture or air.

[0214] Although a negative type planarization material layer is disclosed in one embodiment of the present invention, the present invention is not limited thereto, and a positive type planarization material layer may also be used.

[0215] The display device according to an embodiment of the present invention may be applied to various electronic devices. The electronic device according to an embodiment of the present invention may include the display device described above, and may further include a module or device having additional functions other than the display device.

[0216] FIG. 15 is a block diagram of an electronic device according to one embodiment of the present invention.

[0217] Referring to FIG. 15, an electronic device 1 according to one embodiment of the present invention may include a display module 11, a processor 12, a memory 13, and a power module 14.

[0218] The processor 12 may include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0219] The memory 13 stores data information required for the operation of the processor 12 and the display module 11. When the processor 12 executes an application stored in the memory 13, video data signals and / or input control signals are transmitted to the display module 11, and the display module 11 processes the provided signals to output video information via a display screen.

[0220] The power supply module 14 may include a power supply module such as a power adapter or a battery device, and a power conversion module that converts the power supplied by the power supply module to generate the power required for operation of the electronic device 1.

[0221] At least one of the components of the electronic device 1 described above may be included in the display device according to the above-described embodiment. Furthermore, some of the individual modules functionally included in one module may be included in the display device, while other modules may be provided separately from the display device. For example, the display device may include the display module 11, and the processor 12, memory 13, and power supply module 14 may be provided as other devices within the electronic device 1 rather than as part of the display device.

[0222] FIG. 16 is a schematic diagram of an electronic device according to various embodiments.

[0223] Referring to FIG. 16, various electronic devices to which a display device according to one embodiment of the present invention is applied include not only electronic devices for displaying images such as a smartphone 10_1a, a tablet PC 10_1b, a laptop 10_1c, a TV 10_1d, and a desk monitor 10_1e, but also wearable electronic devices including a display module such as smart glasses 10_2a, a head-mounted display 10_2b, and a smart watch 10_2c, and vehicular electronic devices 10_3 including a display module such as a CID (Center Information Display) arranged on the dashboard, center fascia, or dashboard of a car, and a room mirror display.

[0224] Although the embodiments of the present invention have been described above with reference to the drawings, those skilled in the art will understand that the present invention can be embodied in other specific forms without changing the technical idea or essential features of the present invention. Therefore, it should be understood that the above-described embodiments are illustrative in all respects and are not limiting. [Explanation of symbols]

[0225] 10 Display device DA display area NDA Hidden Area PA Pad Area IPA inspection circuit section DRL Data Routing Wiring TSL5 5th inspection signal supply wiring D22 Datapad VA1,2 First and second planarization layers FTL 1st area HTL 2nd area PCH pad opening SUB board

Claims

1. A display panel; a plurality of pixels arranged in a display area of ​​the display panel; an inspection circuit section and a pad area disposed in a non-display area of ​​the display panel; data routing wiring extending from the display area to the inspection circuit unit and the pad area; a first planarization layer extending from the display area to the test circuitry and disposed on the data routing lines; a second planarization layer extending from the display area to the inspection circuit area and the pad area and disposed on the first planarization layer; the test circuit unit is disposed adjacent to the pad region and includes test signal supply wiring that supplies a test signal to the data routing wiring; the second planarization layer includes a first region overlapping the inspection signal supply wiring and a second region overlapping the pad region.

2. The display device of claim 1 , wherein the first region of the second planarization layer covers the inspection signal supply wiring, and a side of the first region is spaced apart from the inspection signal supply wiring in a plane.

3. The display device according to claim 2 , wherein a side of the first region of the second planarization layer is disposed between the inspection signal supply wiring and the pad region on a plane.

4. the pad area includes a data pad connected to the data routing wiring; The display device of claim 1 , wherein the first region of the second planarization layer does not overlap the data pad.

5. The display device of claim 4 , wherein the second region of the second planarization layer overlaps the data pad.

6. The display device of claim 5 , wherein the second region of the second planarization layer includes a pad opening overlapping the data pad.

7. The display device according to claim 1 , wherein the height of the first region of the second planarization layer is greater than the height of the second region.

8. The display device according to claim 1 , wherein the first planarization layer does not overlap the pad region, but overlaps the first region and the second region of the second planarization layer.

9. the test circuit unit includes a test transistor including a test active layer; The display device of claim 1 , wherein the data routing wiring is electrically connected to one end of the test active layer, and the test signal supply wiring is electrically connected to the other end of the test active layer.

10. the inspection circuit unit is disposed between the display area and the pad area, 2. The display device according to claim 1, wherein the data routing wiring extends from the display area to the pad area, passing through the test circuit section.

11. a substrate including a non-display area including a pad area and a display area; data routing wiring disposed on the non-display area; at least two insulating layers disposed on the data routing wiring; a data pad disposed on the pad region and connected to the data routing wiring via a contact hole passing through the insulating layer; test signal supply wiring arranged in the non-display area not overlapping the pad area and intersecting the data routing wiring; a first planarization layer disposed on the inspection signal supply wiring; a second planarization layer disposed on the first planarization layer and the data pad, the second planarization layer including a first region overlapping the inspection signal supply wiring and a second region overlapping the data pad.

12. The display device of claim 11 , wherein the first region of the second planarization layer covers the inspection signal supply wiring, and a side of the first region is spaced apart from the inspection signal supply wiring in a plane.

13. The display device of claim 11 , wherein a side of the first region of the second planarization layer is disposed between the inspection signal supply wiring and the pad region on a plane.

14. The display device of claim 11 , wherein the first region of the second planarization layer and the first planarization layer do not overlap the data pad.

15. The display device of claim 11 , wherein the second region of the second planarization layer overlaps the data pad.

16. The display device of claim 11 , wherein the second region of the second planarization layer includes a pad opening overlapping the data pad.

17. The display device of claim 11 , wherein the thickness of the first region of the second planarization layer measured from the top surface of the substrate is greater than the thickness of the second region.

18. The display device according to claim 1 , wherein the first planarization layer overlaps the first region and the second region of the second planarization layer.

19. a substrate including a display area and a non-display area; a pad area including pads, the pad area being disposed in a non-display area of ​​the substrate; an inspection circuit unit disposed between the display area and the pad area of ​​the substrate; a routing wiring disposed on the substrate, passing through the inspection circuit unit and extending to the pad; a first planarization layer extending from the display area to the testing circuit area and the pad area; the test circuit unit is adjacent to the pad region and includes signal wiring electrically connected to the routing wiring; the first planarization layer includes a first region covering the signal wiring and a second region covering the pad region; A display device, wherein the side of the first region is disposed between the signal wiring and the pad on a plane.

20. the test circuit unit includes a test transistor including a test active layer; The display device of claim 19 , wherein the routing wiring is electrically connected to one end of the test active layer, and the signal wiring is electrically connected to the other end of the test active layer.

21. The display device of claim 19 , wherein the first region of the first planarization layer does not overlap the pad, and the second region of the first planarization layer overlaps the pad.

22. The display device of claim 19 , wherein the first region of the first planarization layer has a thickness measured from the top surface of the substrate that is greater than the thickness of the second region.

23. further comprising a second planarization layer disposed between the signal wiring and the first planarization layer; The display device according to claim 19 , wherein the second planarization layer covers the signal wiring.

24. 24. The display device of claim 23, wherein the second planarization layer does not overlap the pads.

25. a display device that provides an image; a processor for providing a video data signal to said display device; a memory for storing data information for driving; a power supply module for generating power; The display device includes: A display panel; a plurality of pixels arranged in a display area of ​​the display panel; an inspection circuit unit disposed in a non-display area of ​​the display panel; data routing wiring extending from the display area to the inspection circuit section and the pad area; a first planarization layer extending from the display area to the test circuitry and disposed on the data routing lines; a second planarization layer extending from the display area to the inspection circuit area and the pad area and disposed on the first planarization layer; the test circuit unit is disposed adjacent to the pad region and includes test signal supply wiring that supplies a test signal to the data routing wiring; the second planarization layer includes a first region overlapping the inspection signal supply wiring and a second region overlapping the pad region.

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