Display panel and display device

Abstract

To provide a display panel and a display device.SOLUTION: In the same subpixel, a capacitor conductive part and a data line pattern corresponding to the subpixel and / or a power signal line pattern corresponding to the subpixel have an overlapping region. The capacitor conductive part is coupled to at least the power signal line pattern corresponding to the subpixel or the data line pattern corresponding to the subpixel. A pixel defining layer includes a plurality of opening regions. The subpixel includes a corresponding opening region. An orthogonal projection of at least a part of a touch electrode on a base substrate forms a grid. A transistor array layer further includes a first conductive layer. The capacitor conductive part is formed in the first conductive layer. A pixel circuit further includes a plurality of transistors. Sources and drains of at least some transistors are formed on the first conductive layer.SELECTED DRAWING: Figure 8b

Description

[Technical Field]

[0001] [CROSS-REFERENCE TO RELATED APPLICATIONS] This application claims priority from a Chinese patent application filed with the China Patent Office on August 17, 2020, bearing application number 202010822808.3 and entitled "Display Panel and Display Device," the entire disclosure of which is incorporated herein by reference.

[0002] The present invention relates to the field of display technology, and more particularly to a display panel and a display device. [Background technology]

[0003] Organic light-emitting diodes (OLEDs), quantum dot light-emitting diodes (QLEDs) and other electroluminescent diodes have advantages such as self-luminescence and low energy consumption, making them one of the most important hot spots in the application research field of electroluminescent display devices. Summary of the Invention [Means for solving the problem]

[0004] An embodiment of the present application provides a display panel comprising: A base substrate; a transistor array layer located on the base substrate; a pixel definition layer located on a side of the transistor array layer away from the base substrate; and a touch electrode located on a side of the pixel defining layer away from the base substrate; the base substrate has a display area, the display area includes a plurality of sub-pixels, each sub-pixel includes a pixel circuit and a light-emitting element, the pixel circuit includes a gate line pattern, a data line pattern, and a power signal line pattern; the transistor array layer includes a plurality of capacitor conductive portions, and the sub-pixels include corresponding capacitor conductive portions, wherein in the same sub-pixel, the capacitor conductive portion and the data line pattern corresponding to the sub-pixel and / or the power signal line pattern corresponding to the sub-pixel have an overlapping region, and the capacitor conductive portion is coupled to at least the power signal line pattern corresponding to the sub-pixel or the data line pattern corresponding to the sub-pixel; the pixel defining layer includes a plurality of aperture regions, the sub-pixels including corresponding aperture regions; an orthogonal projection of at least a portion of the touch electrodes on the base substrate is a grid; wherein the plurality of subpixels further include first color subpixels, second color subpixels, and third color subpixels, an area of ​​an aperture region of the first color subpixels being smaller than an area of ​​an aperture region of the third color subpixels, an area of ​​an aperture region of the second color subpixels being smaller than an area of ​​an aperture region of the third color subpixels, an orthogonal projection of the capacitor conductive portion of the first color subpixel on the base substrate and an orthogonal projection of the touch electrode on the base substrate have a first auxiliary overlapping area; an orthogonal projection of the capacitor conductive portion of the second-color subpixel on the base substrate and an orthogonal projection of the touch electrode on the base substrate have a second auxiliary overlapping area; an orthogonal projection of the capacitor conductive portion of the third-color subpixel on the base substrate and an orthogonal projection of the touch electrode on the base substrate have a third auxiliary overlapping area; At least one of the first auxiliary overlapping area and the second auxiliary overlapping area is larger than the third auxiliary overlapping area.

[0005] In some examples, the first auxiliary overlapping area is greater than the second auxiliary overlapping area; or The first auxiliary overlapping area is approximately equal to the second auxiliary overlapping area, or the third auxiliary overlapping area is approximately equal to the second auxiliary overlapping area.

[0006] In some examples, the transistor array layer comprises a first conductive layer, a first insulating layer, and a second conductive layer; the first conductive layer is located between the base substrate and the pixel definition layer, where the first conductive layer includes a plurality of data line patterns and a plurality of power signal line patterns; the first insulating layer is located between the base substrate and the first conductive layer; the second conductive layer is located between the base substrate and the first insulating layer, the second conductive layer includes a plurality of auxiliary conductive portions, and the capacitor conductive portion in the subpixel includes the auxiliary conductive portion, wherein, in the same subpixel, an orthogonal projection of a first end of the auxiliary conductive portion on the base substrate and an orthogonal projection of the power signal line pattern on the base substrate have an overlapping region, and an orthogonal projection of a second end of the auxiliary conductive portion on the base substrate and an orthogonal projection of the data line pattern on the base substrate have an overlapping region, and the auxiliary conductive portion is coupled to the power signal line pattern; the first auxiliary overlapping area includes an overlapping area between an orthogonal projection of an auxiliary conductive portion of the first color subpixel on the base substrate and an orthogonal projection of the touch electrode on the base substrate; the second auxiliary overlapping area includes an overlapping area between an orthogonal projection of an auxiliary conductive portion of the second-color subpixel on the base substrate and an orthogonal projection of the touch electrode on the base substrate; The third auxiliary overlapping area includes an overlapping area between an orthogonal projection of an auxiliary conductive portion in the third color subpixel on the base substrate and an orthogonal projection of the touch electrode on the base substrate.

[0007] In some examples, the auxiliary conductive portion in the first color subpixel includes a first auxiliary exposed portion, and an orthogonal projection of the first auxiliary exposed portion on the base substrate does not overlap with an orthogonal projection of the data line pattern on the base substrate and an orthogonal projection of the power signal line pattern on the base substrate, respectively, and the first auxiliary overlapping area includes a first auxiliary sub-overlapping area, and an overlapping area between the orthogonal projection of the first auxiliary exposed portion on the base substrate and the orthogonal projection of the touch electrode on the base substrate has a first auxiliary sub-overlapping area; the auxiliary conductive portion in the second color subpixel includes a second auxiliary exposed portion, and an orthogonal projection of the second auxiliary exposed portion on the base substrate does not overlap with an orthogonal projection of the data line pattern on the base substrate and an orthogonal projection of the power signal line pattern on the base substrate, respectively; the second auxiliary overlapping area includes a second auxiliary sub-overlapping area; and an overlapping area between the orthogonal projection of the second auxiliary exposed portion on the base substrate and an orthogonal projection of the touch electrode on the base substrate has a second auxiliary sub-overlapping area; the auxiliary conductive portion in the third color subpixel includes a third auxiliary exposed portion, and an orthogonal projection of the third auxiliary exposed portion on the base substrate does not overlap with an orthogonal projection of the data line pattern on the base substrate and an orthogonal projection of the power signal line pattern on the base substrate, respectively; the third auxiliary overlapping area includes a third auxiliary sub-overlapping area; and an overlapping area between the orthogonal projection of the third auxiliary exposed portion on the base substrate and an orthogonal projection of the touch electrode on the base substrate has a third auxiliary sub-overlapping area; The first auxiliary sub-overlapping area is larger than at least one of the second auxiliary sub-overlapping area and the third auxiliary sub-overlapping area.

[0008] In some examples, the second auxiliary sub-overlapping area is greater than the third auxiliary sub-overlapping area, or the third auxiliary sub-overlapping area is approximately equal to the second auxiliary sub-overlapping area.

[0009] In some examples, in the first color subpixel, a positive projection of the first auxiliary exposed portion on the base substrate is located between a positive projection of the data line pattern on the base substrate and a positive projection of the power signal line pattern on the base substrate; and / or In the second-color subpixel, the orthogonal projection of the second auxiliary exposed portion on the base substrate is located between the orthogonal projection of the data line pattern on the base substrate and the orthogonal projection of the power signal line pattern on the base substrate; and / or In the third color subpixel, the orthogonal projection of the third auxiliary exposed portion on the base substrate is located between the orthogonal projection of the data line pattern on the base substrate and the orthogonal projection of the power signal line pattern on the base substrate.

[0010] In some examples, an orthogonal projection of the auxiliary conductive portion on the base substrate has a total area of: The ratio of the first auxiliary overlapping area to the total area is in the range of 1 / 3 to 2 / 3; and / or The ratio of the second auxiliary sub-overlap area to the total area is in the range of 0 to 1 / 4; and / or The ratio of the third auxiliary sub-overlap area to the total area ranges from 0 to 1 / 16.

[0011] In some examples, in the first color subpixel, an orthogonal projection of the touch electrode on the base substrate covers an orthogonal projection of the first auxiliary exposed portion on the base substrate; and / or In the second color subpixel, the orthogonal projection of the touch electrode on the base substrate covers the orthogonal projection of the second auxiliary exposed portion on the base substrate; and / or In the third color subpixel, the orthogonal projection of the touch electrode on the base substrate covers the orthogonal projection of the third auxiliary exposed portion on the base substrate.

[0012] In some examples, the auxiliary conductive portion in the first-color subpixel further includes a first auxiliary shield portion, and an orthogonal projection of the first auxiliary shield portion on the base substrate overlaps with an orthogonal projection of at least one of the data line pattern and the power signal line pattern on the base substrate, wherein a width of the first auxiliary exposed portion in a column direction is smaller than a width of the first auxiliary shield portion in the column direction; and / or the auxiliary conductive portion in the second-color subpixel further includes a second auxiliary shield portion, and an orthogonal projection of the second auxiliary shield portion on the base substrate overlaps with an orthogonal projection of at least one of the data line pattern and the power signal line pattern on the base substrate, wherein a width of the second auxiliary exposed portion in the column direction is smaller than a width of the second auxiliary shield portion in the column direction; and / or The auxiliary conductive portion in the third color subpixel further includes a third auxiliary shield portion, and the orthogonal projection of the third auxiliary shield portion on the base substrate overlaps with the orthogonal projection of at least one of the data line pattern and the power signal line pattern on the base substrate, and the width of the third auxiliary exposed portion in the column direction is smaller than the width of the third auxiliary shield portion in the column direction.

[0013] In some examples, the pixel circuit further includes a first capacitor; an orthogonal projection of a first capacitor in the first color subpixel on the base substrate and an orthogonal projection of the touch electrode on the base substrate have a first storage overlap area; an orthogonal projection of a first capacitor in the second color subpixel on the base substrate and an orthogonal projection of the touch electrode on the base substrate have a second storage overlap area; an orthogonal projection of the first capacitor in the third color subpixel on the base substrate and an orthogonal projection of the touch electrode on the base substrate have a third storage overlap area; At least one of the first storage overlapping area and the second storage overlapping area is larger than the third storage overlapping area.

[0014] In some examples, the first storage overlap area is greater than the second storage overlap area.

[0015] In some examples, the second conductive layer further includes a plurality of storage conductive portions spaced apart from the auxiliary conductive portions, and the subpixel includes the storage conductive portions, the storage conductive portions functioning as second plates of the first capacitors; the first storage overlap area includes an overlap area between an orthogonal projection of a storage conductive portion of the first color subpixel on the base substrate and an orthogonal projection of the touch electrode on the base substrate; the second storage overlap area includes an overlap area between an orthogonal projection of a storage conductive portion of the second color subpixel on the base substrate and an orthogonal projection of the touch electrode on the base substrate; The third storage overlap area includes an overlap area between a positive projection of a storage conductive portion of the third color subpixel on the base substrate and a positive projection of the touch electrode on the base substrate.

[0016] In some examples, the orthogonal projection of the touch electrodes on the base substrate has a grid-like shape, and the orthogonal projection of the touch electrodes on the base substrate does not overlap with the orthogonal projection of the opening area on the base substrate.

[0017] In some examples, the touch electrode includes a first electrode portion and a second electrode portion, wherein an orthogonal projection of the first electrode portion on the base substrate and an orthogonal projection of the auxiliary conductive portion on the base substrate have an overlapping region, and an orthogonal projection of the second electrode portion on the base substrate does not overlap with an orthogonal projection of the auxiliary conductive portion on the base substrate; The width of the first electrode portion is greater than the width of the second electrode portion.

[0018] In some examples, the display panel further includes a light-emitting functional layer, the light-emitting functional layer is located between the pixel definition layer and the touch electrode, and the light-emitting functional layer includes a plurality of first color light-emitting layers, a plurality of second color light-emitting layers, and a plurality of third color light-emitting layers; wherein an orthogonal projection of the first-color light-emitting layer on the base substrate covers an orthogonal projection of an aperture region of the first-color subpixel on the base substrate; an orthogonal projection of the second-color light-emitting layer on the base substrate covers an orthogonal projection of an aperture area of ​​the second-color subpixel on the base substrate; The orthogonal projection of the third-color light-emitting layer on the base substrate covers the orthogonal projection of the aperture area of ​​the third-color subpixel on the base substrate.

[0019] In some examples, orthogonal projections of touch electrodes located between adjacent opening regions on the base substrate overlap with orthogonal projections of at least two different color light-emitting layers on the base substrate.

[0020] In some examples, an orthogonal projection of a touch electrode surrounding an aperture region of the third color subpixel on the base substrate is located within an orthogonal projection of the third color light-emitting layer on the base substrate; and / or an orthogonal projection of a touch electrode surrounding an aperture region of the second-color subpixel on the base substrate is located within an orthogonal projection of the second-color light-emitting layer on the base substrate; and / or The orthogonal projection of the touch electrode surrounding the aperture region of the first-color subpixel on the base substrate is located within the orthogonal projection of the first-color light-emitting layer on the base substrate.

[0021] In some examples, the third color light-emitting layer and the second color light-emitting layer are adjacent, and there is a first minimum distance between a boundary of an orthogonal projection of the third color light-emitting layer on the base substrate and a boundary of an orthogonal projection of the touch electrode on the base substrate, and there is a second minimum distance between a boundary of an orthogonal projection of the second color light-emitting layer on the base substrate and a boundary of an orthogonal projection of the touch electrode on the base substrate; The first minimum distance is greater than the second minimum distance.

[0022] In some examples, an area enclosed by an orthogonal projection of a touch electrode surrounding an aperture area of ​​the first color subpixel on the base substrate is a first grid area; an area surrounded by an orthogonal projection of a touch electrode surrounding an aperture region of the second color subpixel on the base substrate is a second grid area; an area surrounded by an orthogonal projection of a touch electrode surrounding an aperture region of the third color subpixel on the base substrate is a third grid area; The third grid area is larger than the second grid area and larger than the first grid area.

[0023] In some examples, the display panel includes a plurality of overlapping units, each including the first color subpixel, the second color subpixel, and the third color subpixel.

[0024] In some examples, the overlap unit further includes a fourth color subpixel, and an area enclosed by an orthogonal projection of a touch electrode surrounding an aperture region of the fourth color subpixel on the base substrate is a fourth grid area; and The first grid area corresponding to the first color subpixel is greater than or approximately equal to the fourth grid area corresponding to the fourth color subpixel.

[0025] In some examples, in the same overlapping unit, the aperture regions of the third color subpixels and the aperture regions of the first color subpixels are arranged along a first direction; an area surrounded by an inner boundary of the touch electrode surrounding the aperture area of ​​the third color subpixel has a first width perpendicular to the first direction; an area surrounded by an inner boundary of the touch electrode surrounding the aperture area of ​​the first color subpixel has a second width perpendicular to the first direction; The first width is greater than the second width.

[0026] In some examples, in the same overlapping unit, the aperture regions of the second color subpixels and the aperture regions of the fourth color subpixels are arranged along a first direction; an area surrounded by an inner boundary of the touch electrode surrounding the aperture area of ​​the second color subpixel has a third width perpendicular to the first direction; an area surrounded by an inner boundary of the touch electrode surrounding the aperture area of ​​the fourth color subpixel has a fourth width perpendicular to the first direction; The third width is greater than the fourth width.

[0027] In some examples, the extension direction of the grid lines of the touch electrode having an overlapping area with the orthogonal projection of the auxiliary conductive portion has an angle β with a third direction, where 15°≦β≦60°, and the third direction is approximately perpendicular to the extension direction of the data line pattern.

[0028] In some examples, tanβ=A1 / A2, where A1 represents the width of the auxiliary conductive portion perpendicular to the third direction and A2 represents the width of the auxiliary conductive portion in the third direction.

[0029] In some examples, an extension direction of a grid line of a touch electrode having an overlapping area with an orthogonal projection of an auxiliary conductive portion in a first color subpixel has a first angle with respect to the third direction; an extension direction of a grid line of a touch electrode having an overlapping area with an orthogonal projection of an auxiliary conductive portion in a second color subpixel has a second angle with respect to the third direction; an extending direction of a grid line of a touch electrode having an overlapping area with an orthogonal projection of an auxiliary conductive portion in a third color subpixel has a third angle with respect to the third direction; The first angle is smaller than the second angle and smaller than the third angle.

[0030] In some examples, an aperture group is an aperture region of four adjacent subpixels, and an orthogonal projection of a grid intersection of the touch electrode on the base substrate is located in an area surrounded by an orthogonal projection of the aperture group on the base substrate.

[0031] In some examples, an orthogonal projection of a grid intersection of the touch electrodes on the base substrate is approximately at the center of an area enclosed by an orthogonal projection of the openings on the base substrate.

[0032] In some examples, the fourth color subpixel and the first color subpixel have the same emitting color.

[0033] In some examples, each of the subpixels further includes a first electrode; an overlap region between an orthogonal projection of a first electrode in the first color subpixel on the base substrate and an orthogonal projection of the touch electrode on the base substrate has a first anode overlap area; an overlapping region between an orthogonal projection of a first electrode in the second color subpixel on the base substrate and an orthogonal projection of the touch electrode on the base substrate has a second anode overlapping area; an overlapping region between an orthogonal projection of a first electrode in the third color subpixel on the base substrate and an orthogonal projection of the touch electrode on the base substrate has a third anode overlapping area; At least one of the first anode overlapping area and the second anode overlapping area is larger than the third anode overlapping area.

[0034] In some examples, the first anode overlapping area is greater than the second anode overlapping area; or The first anode overlapping area is approximately equal to the second anode overlapping area.

[0035] Another display panel provided by an embodiment of the present application includes a base substrate, a transistor array layer located on the base substrate; a pixel-defining layer located on a side of the transistor array layer away from the base substrate; a touch electrode located on a side of the pixel defining layer away from the base substrate; The base substrate has a display area, the sub-pixel includes a plurality of sub-pixels, each sub-pixel includes a pixel circuit and a light-emitting element, the pixel circuit includes a gate line pattern, a data line pattern, and a power signal line pattern; the transistor array layer includes a plurality of capacitor conductive portions, and the sub-pixels include corresponding capacitor conductive portions, wherein in the same sub-pixel, the capacitor conductive portion and the data line pattern corresponding to the sub-pixel and / or the power signal line pattern corresponding to the sub-pixel have an overlapping region, and the capacitor conductive portion is coupled to at least the power signal line pattern corresponding to the sub-pixel or the data line pattern corresponding to the sub-pixel; the pixel defining layer includes a plurality of aperture regions, the sub-pixels including corresponding aperture regions; an orthogonal projection of at least a portion of the touch electrodes on the base substrate is a grid; the transistor array layer further includes a first conductive layer, and the capacitor conductive portion is formed in the first conductive layer; The pixel circuit further includes a plurality of transistors, at least some of which have sources and drains formed on the first conductive layer.

[0036] In some examples, the capacitor conductive portions have an arcuate or irregular pattern.

[0037] In some examples, the capacitor conductive portion includes an auxiliary conductive portion, and the auxiliary conductive portion at least partially overlaps the power signal line pattern, the data line pattern, and the touch electrode.

[0038] In some examples, the power supply signal line patterns of two adjacent columns of the subpixels are electrically coupled via a power input line, or the power supply signal line patterns corresponding to two adjacent columns of the subpixels of the same color are electrically coupled via a power input line.

[0039] In some examples, the power input line and the power signal line pattern are arranged on different layers.

[0040] In some examples, the width of the power signal line pattern is greater than the width of the data line pattern.

[0041] In some examples, the data line pattern is not disposed on the same conductive layer as the power signal line pattern, or the data line pattern and the power input line are not disposed on the same conductive layer.

[0042] In some examples, the first conductive layer includes a first sub-conductive layer and a second sub-conductive layer stacked together, and a first sub-insulating layer is provided between the first sub-conductive layer and the second sub-conductive layer.

[0043] In some examples, the overlapping area between the capacitor conductive portion and the power signal line pattern is larger than the overlapping area between the capacitor conductive portion and the data line pattern.

[0044] In some examples, the pixel circuit includes a seventh transistor and a second transistor, a gate of the seventh transistor is coupled to a second reset signal line pattern, and a gate of the second transistor is coupled to a first reset signal line pattern, and the first reset signal line pattern and the second reset signal line pattern carry different signals.

[0045] In some examples, the pixel circuit includes a data-writing transistor and a first transistor, and the gate line pattern coupled to a gate of the data-writing transistor and the gate line pattern coupled to a gate of the first transistor transmit different timing signals.

[0046] The display device provided by the present application embodiment includes the above-mentioned display panel. [Brief explanation of the drawings]

[0047] [Figure 1] 1A and 1B are schematic diagrams of the structure of some display panels in embodiments of the present application; [Figure 2] 2 is a partial cross-sectional view of the display panel shown in FIG. 1 taken along the line AA'. [Figure 3] 1A and 1B are schematic diagrams of the structure of some pixel circuits in embodiments of the present application; [Figure 4] 3A and 3B are timing diagrams of some signals in an embodiment of the present application; [Figure 5a] 1 is a schematic diagram of the layout structure of several display panels in an embodiment of the present application; [Figure 5b] FIG. 10 is a schematic diagram of a layout structure of yet another display panel in an embodiment of the present application. [Figure 5c] 5b is a schematic cross-sectional view of the structure of the display panel shown in FIG. 5a taken along the AA' direction. [Figure 5d] 5b is a schematic cross-sectional view of the structure of the display panel shown in FIG. 5a along the BB' direction. [Figure 5e] 5b is a schematic cross-sectional view of the structure of the display panel shown in FIG. 5a taken along the CC' direction. [Figure 5f] 5b is a schematic cross-sectional view of the structure of the display panel shown in FIG. 5a taken along the DD' direction. [Figure 5g] FIG. 2 is a schematic diagram of a layout structure of a first-color subpixel in an embodiment of the present application. [Figure 5h] FIG. 2 is a schematic diagram of a layout structure of a second-color subpixel in an embodiment of the present application. [Figure 5i] FIG. 2 is a schematic diagram of a layout structure of a third-color subpixel in an embodiment of the present application. [Figure 6a] 1 is a schematic diagram of the structure of some semiconductor layers in an embodiment of the present application. [Figure 6b] 3A to 3C are schematic diagrams of the structure of some third conductive layers in embodiments of the present application. [Figure 6c] 3A to 3C are schematic diagrams of the structure of some second conductive layers in embodiments of the present application. [Figure 6d]2A to 2C are schematic diagrams of the structure of some first conductive layers in embodiments of the present application. [Figure 6e] 2A to 2C are schematic diagrams of the structure of some first electrode layers in embodiments of the present application. [Figure 6f] 1 is a schematic diagram of the structure of some light-emitting functional layers in an embodiment of the present application. FIG. [Figure 6g] 3A to 3C are schematic diagrams of the structures of some second touch electrodes in embodiments of the present application. [Figure 7a] FIG. 10 is a schematic diagram of a structure of still another semiconductor layer in an embodiment of the present application. [Figure 7b] FIG. 10 is a schematic diagram of a structure of yet another third conductive layer in an embodiment of the present application. [Figure 7c] FIG. 10 is a schematic diagram of a structure of yet another second conductive layer in an embodiment of the present application. [Figure 7d] FIG. 10 is a schematic diagram of a structure of yet another first conductive layer in an embodiment of the present application. [Figure 7e] FIG. 10 is a schematic diagram of a structure of still another first electrode layer in an embodiment of the present application. [Figure 7f] FIG. 10 is a schematic diagram of a structure of still another light-emitting functional layer in an embodiment of the present application. [Figure 7g] FIG. 10 is a schematic diagram of a structure of yet another first sub-conductive layer in an embodiment of the present application. [Figure 7h] FIG. 10 is a schematic diagram of a structure of yet another second sub-conductive layer in an embodiment of the present application. [Figure 8a] 1A and 1B are schematic diagrams of the structures of some touch electrodes in embodiments of the present application; [Figure 8b] FIG. 10 is a schematic diagram of yet another touch electrode structure in an embodiment of the present application. [Figure 8c] FIG. 10 is a schematic diagram of yet another touch electrode structure in an embodiment of the present application. [Figure 8d] 8C is a schematic diagram of the structure of the touch electrode shown in FIG. 8C along the AA' direction. [Figure 9a] FIG. 10 is a schematic diagram of a layout structure of yet another display panel in an embodiment of the present application. [Figure 9b] FIG. 10 is a schematic diagram of a layout structure of yet another display panel in an embodiment of the present application. [Figure 9c] FIG. 10 is a schematic diagram of a layout structure of yet another display panel in an embodiment of the present application. [Figure 10a] FIG. 10 is a schematic diagram of a layout structure of yet another display panel in an embodiment of the present application. [Figure 10b] FIG. 10 is a schematic diagram of a layout structure of yet another display panel in an embodiment of the present application. [Figure 11] FIG. 10 is a schematic diagram of a layout structure of yet another display panel in an embodiment of the present application. [Figure 12] FIG. 10 is a schematic diagram of a layout structure of yet another display panel in an embodiment of the present application. [Figure 13a] FIG. 10 is a schematic diagram of a layout structure of yet another display panel in an embodiment of the present application. [Figure 13b] FIG. 10 is a schematic diagram of a layout structure of yet another display panel in an embodiment of the present application. [Figure 14a] FIG. 10 is a schematic diagram of a layout structure of yet another display panel in an embodiment of the present application. [Figure 14b] FIG. 10 is a schematic diagram of a layout structure of yet another display panel in an embodiment of the present application. [Figure 15] FIG. 10 is a schematic diagram of a layout structure of still another display panel according to an embodiment of the present application. DETAILED DESCRIPTION OF THE INVENTION

[0048] In order to make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the technical solutions of the embodiments of the present application are clearly and completely described in conjunction with the accompanying drawings of the embodiments of the present application. Obviously, the described embodiments are not all of the embodiments, but are only a part of the embodiments of the present application. And, if there is no contradiction, the embodiments and the features of the embodiments of the present application can be combined with each other. Based on the described embodiments of the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0049] Unless otherwise defined, technical or scientific terms used in this application shall have their ordinary meaning as understood by a person of ordinary skill in the art to which this application pertains. The terms "first," "second," and similar terms used in this application do not denote order, quantity, or importance, but are used only to distinguish between different components. The terms "comprise" or "comprises" and other similar terms mean that the elements or items appearing before the word cover the elements or items listed after the word and their equivalents, but do not exclude other elements or items. The terms "coupled" or "connected," and similar terms, are not limited to physical or mechanical coupling, but may include direct or indirect electrical coupling.

[0050] The size and shape of each figure in the drawings do not reflect actual proportions and are intended only for the purpose of explaining the present application. In addition, the same or similar reference numerals indicate the same or similar elements or elements having the same or similar functions.

[0051] 1 and 2 , the display panel provided by the embodiment of the present application includes a base substrate 1000, a transistor array layer ZA located on the base substrate 1000 and located on a side of the base substrate 1000, a first electrode layer 500 located on the transistor array layer ZA away from the base substrate 1000, a pixel definition layer 950 located on the first electrode layer 500 side away from the base substrate 1000, an light-emitting function layer 600 located on the light-emitting function layer 600 side away from the base substrate 1000, a second electrode 700 located on the light-emitting function layer 600 away from the base substrate 1000, a sealing layer FB located on the second electrode 700 away from the base substrate 1000, and a touch electrode 800 located on the sealing layer FB away from the base substrate 1000.

[0052] In some embodiments of the present application, as shown in FIG. 1 , a base substrate 1000 has a display area AA and a non-display area surrounding the display area. The display area includes a plurality of sub-pixels spx. The non-display area has a barrier BK surrounding the display area AA. The non-display area may also include a circuit configuration such as a drive circuit, for example, a gate driver on array (GOA), but this will not be described here.

[0053] Exemplarily, the subpixel spx may include a pixel circuit and a light-emitting element. Here, the pixel circuit includes a transistor and a capacitor for driving the light-emitting element to emit light. It should be noted that one or more embodiments described herein correspond to a display panel having a 7T2C (i.e., seven thin-film transistors and two capacitors) pixel circuit. In other embodiments, the display panel may include a different pixel circuit, for example, more or less than seven thin-film transistors and one or more capacitors.

[0054] As shown in FIG. 3, in a display panel provided by one embodiment of the present application, a subpixel may include a gate line pattern GATE (abbreviated as GA), a first reset signal line pattern RST1, a first initialization signal line pattern VINT1, a data line pattern DATA (abbreviated as DA), a light emitting control signal line pattern EM, a power supply signal line pattern VDD, a second reset signal line pattern RST2, and a second initialization signal line pattern VINT2.

[0055] Exemplarily, the first reset signal line pattern RST1 and the second reset signal line pattern RST2 may transmit different signals.

[0056] For example, the first reset signal line pattern RST1 and the second reset signal line pattern RST2 may be located on different layers, for example, the first reset signal line pattern RST1 and the gate line pattern GA may be located on the same layer, and the second reset signal line pattern RST2 and the data line pattern DA or the power supply signal line pattern VDD may be located on the same layer.

[0057] Exemplarily, the first initialization signal line pattern VINT1 and the second initialization signal line pattern VINT2 transmit the same signal.

[0058] For example, the first initialization signal line pattern VINT1 and the second initialization signal line pattern VINT2 may transmit different signals, for example, VINT1 is V1 and VINT2 is V1±5V.

[0059] For example, the first initialization signal line pattern VINT1 and the second initialization signal line pattern VINT2 may be located on different layers, for example, the first initialization signal line pattern VINT1 and the gate line pattern GA may be located on the same layer, and the second initialization signal line pattern VINT2 and the data line pattern DA or the first reset signal line pattern RST1 may be located on the same layer.

[0060] As shown in FIG. 3, the pixel circuit in the subpixel may include a first transistor T1, a second transistor T2, a third transistor T3, a data write transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a first capacitor Cst, and a second capacitor C1.

[0061] Taking the pixel circuit as an example, all the transistors included in the pixel circuit are P-type transistors. The first transistor T1 has a double-gate structure, where the gate 201g of the first transistor T1 is coupled to the gate line pattern GA, the source S1 of the first transistor T1 is coupled to the drain D3 of the third transistor T3, and the drain D1 of the first transistor T1 is coupled to the gate 203g of the third transistor T3. Of course, the first transistor T1 can have a single-gate structure or a multi-gate structure, but is not limited thereto.

[0062] The second transistor T2 may have a double-gate structure, in which the gate 202g of the second transistor T2 is coupled to the first reset signal line pattern RST1, the source S2 of the second transistor T2 is coupled to the first initialization signal line pattern VINT1, and the drain D2 of the second transistor T2 is coupled to the gate 203g of the third transistor T3. Of course, the second transistor T2 may have a single-gate structure or a multi-gate structure, but is not limited thereto.

[0063] The gate 204g of the data write transistor T4 is coupled to the gate line pattern GA, the source S4 of the data write transistor T4 is coupled to the data line pattern DA, and the drain D4 of the data write transistor T4 is coupled to the source S3 of the first transistor T3. By way of example, but not limitation, the gate line pattern GA coupled to the gate 204g of the data write transistor T4 and the gate line pattern GA coupled to the gate 201g of the first transistor T1 may transmit different timing signals.

[0064] The gate 205g of the fifth transistor T5 is coupled to the light emission control signal line pattern EM, the source S5 of the fifth transistor T5 is coupled to the power supply signal line pattern VDD, and the drain D5 of the fifth transistor T5 is coupled to the source S3 of the third transistor T3.

[0065] The gate 206g of the sixth transistor T6 is coupled to the light emitting control signal line pattern EM, the source S6 of the sixth transistor T6 is coupled to the drain D3 of the third transistor T3, and the drain D6 of the sixth transistor T6 is coupled to the anode of the light emitting element L. Exemplarily, the light emitting control signal line pattern EM coupled to the gate 205g of the fifth transistor T5 and the light emitting control signal line pattern EM coupled to the gate 206g of the sixth transistor T6 are restricted to transmit different timing signals.

[0066] The gate 207g of the seventh transistor T7 is coupled to the second reset signal line pattern RST2, the drain D7 of the seventh transistor T7 is coupled to the anode of the light-emitting element L, and the source S7 of the seventh transistor T7 is coupled to the second initialization signal line pattern VINT2.

[0067] A first plate Cst1 of the first capacitor Cst is coupled to the gate 203g of the third transistor T3, and a second plate Cst2 of the first capacitor Cst is coupled to the power supply signal line pattern VDD.

[0068] A first end (i.e., a first plate C11) of the second capacitor C1 is coupled to a first end (e.g., a data line pattern DA) of the data write transistor, and a second end (e.g., a second plate C12) of the second capacitor C1 is coupled to a power supply signal line pattern VDD. For example, the first plate C11 of the second capacitor C1 is coupled to the data line pattern DA and / or the data write transistor T4, and the second plate C12 of the second capacitor C1 is coupled to the power supply signal line pattern VDD.

[0069] Optionally, the second plate C12 of the second capacitor C1 is electrically coupled to the power supply signal line pattern VDD, and the first plate C11 of the second capacitor C1 extends below or above the data line pattern DA, such that the first plate C12 overlaps with the orthogonal projection of the data line pattern DA on the base substrate.

[0070] Optionally, the first terminal of the data write transistor T4 may be the source (or source region, e.g., S4 in FIG. 3) or drain (or drain region, e.g., D4 in FIG. 3) of the data write transistor, or the gate (e.g., 204g in FIG. 3). Note that S and D in FIG. 3 are merely drawing symbols for distinguishing the description.

[0071] If necessary, the first end of the data write transistor T4 may be a connection structure between the source of the data write transistor T4 and the data line pattern DA.

[0072] As shown in FIG. 4, exemplarily, when the pixel circuit having the above configuration operates, one operation cycle includes a first reset period P1, a write compensation period P2, a second reset period P3, and a light emitting period P4.

[0073] During the first reset period P1, the first reset signal input via the first reset signal line pattern RST1 is at an active level, turning on the second transistor T2, and the initialization signal transmitted via the first initialization signal line pattern VINT1 is input to the gate 203g of the third transistor T3 to reset the gate 203g of the third transistor T3, for example, clearing the gate-source voltage Vgs held in the third transistor T3 in the previous frame.

[0074] During the write compensation period P2, the first reset signal is inactive, the second transistor T2 is off, the gate scanning signal input by the gate line pattern GA is active, and the first transistor T1 and the data write transistor T4 are turned on. The data line pattern DA writes a data signal and transmits it to the source S3 of the third transistor T3 via the data write transistor T4. At the same time, the first transistor T1 and the data write transistor T4 are turned on, and the third transistor T3 is in a diode structure. The first transistor T1, the third transistor T3, and the data write transistor T4 work together to compensate the threshold voltage of the third transistor T3. If the compensation time is long enough, the potential of the gate 203g of the third transistor T3 can be controlled to eventually reach Vdata+Vth, where Vdata is the voltage of the data signal and Vth is the threshold voltage of the third transistor T3.

[0075] During the second reset period P3, the gate scanning signal is at an inactive level, the first transistor T1 and the data write transistor T4 are both off, and the second reset signal input from the second reset signal line RST2 is at an active level, so that the seventh transistor T7 is controlled to be turned on and the initialization signal transmitted through the second initialization signal line pattern VINT2 is input to the anode of the light-emitting element L, thereby controlling the light-emitting element L to be non-emitting.

[0076] During the light-emitting period P4, the light-emitting control signal written in the light-emitting control signal line pattern EM is at an active level, turning on the fifth transistor T5 and the sixth transistor T6, and turning on the power supply signal. This causes the power supply signal VDD transmitted to the source S3 of the third transistor T3, and the gate 203g of the third transistor T3 is maintained at Vdata+Vth, turning on the third transistor T3. The source voltage of the third transistor T3 is Vdata+Vth-VDD, where VDD is the voltage value corresponding to the power supply signal. A leakage current generated by the gate-source voltage flows to the anode of the corresponding light-emitting element L, causing the corresponding light-emitting element L to emit light.

[0077] If the transistors are P-type transistors, the enable level can be low and the disable level can be high. If the transistors are N-type transistors, the enable level can be high and the disable level can be low. The transistors in the pixel circuit can be both P-type and N-type transistors, or can include both P-type and N-type transistors. For example, transistor T3 is a P-type transistor and transistor T1 is an N-type transistor. Figure 4 is merely an example of the operation timing of the pixel circuit. It should be understood that signals such as RST1, RST2, Ga, EM, and Da can be adaptively adjusted depending on the transistor type and circuit of the pixel and the actual state.

[0078] As shown in FIGS. 5a to 5i, when manufacturing the above-mentioned transistor array layer ZA, the layout of each film layer is as follows: the semiconductor layer 400, the gate insulating layer 910, the third conductive layer 300, the interlayer dielectric layer 920, the second conductive layer 200, the first interlayer insulating layer 930, the first conductive layer 100, and the second interlayer insulating layer 940 are sequentially stacked in a direction away from the base substrate 1000. Note that other metal layers or insulating layers may be included between the base substrate 1000 and the semiconductor layer 400. For example, at least one buffer layer or organic insulating layer may be further included between the base substrate 1000 and the semiconductor layer 400. For example, the buffer layer may be made of silicon oxide or silicon nitride, and the organic insulating layer may be made of polyimide or the like.

[0079] As shown in FIGS. 5a to 5i, 6a, and 7a, the semiconductor layer 400 is used to form the channel region (e.g., 101pg to 107pg), source formation region (e.g., 101ps to 107pg), drain formation region (e.g., 101pd to 107pd), connection formation region (e.g., 101px, 102px), etc. in each transistor in the pixel circuit. Of course, other structures can be formed as needed. A lightly doped drain (LDD) region doped with a lightly doped impurity is formed between the drain formation region (e.g., 101pd to 107pd) and the channel region (e.g., 101pg to 107pg) of at least one transistor, and between the source formation region (e.g., 101ps to 107ps) and the channel region (e.g., 101pg to 107pg) of the transistor. Here, the semiconductor layer 400 corresponding to the source formation region and the drain formation region has better conductivity than the semiconductor layer 400 corresponding to the channel region due to a doping effect. Optionally, the semiconductor layer 400 is low temperature polysilicon (LTPS). The semiconductor layer 400 includes an oxide semiconductor material (e.g., indium gallium zinc oxide (IGZO)). The semiconductor layer 400 includes a low temperature polycrystalline oxide material (LTPO). For example, as shown in FIG. 3, the semiconductor layer 400 of T3 is low temperature polysilicon LTPS, and the semiconductor layer 400 of T1 includes an oxide semiconductor material LTPO.

[0080] The source formation region, drain formation region, and connection formation region may be conductive regions in which a semiconductor layer is doped with n-type or p-type impurities, and the source formation region, drain formation region, and connection formation region may form a connection structure of the semiconductor layer for electrical connection. For example, the semiconductor layer corresponding to the source formation region and drain formation region may directly function as the source or drain of the corresponding transistor. Alternatively, the source electrode may be formed using a conductive material (e.g., a metal material) so as to be in contact with the source electrode formation region, and the drain electrode may be formed using a conductive material (e.g., a metal material) so as to be in contact with the drain electrode formation region.

[0081] As shown in Figures 5a to 5i, 6b, and 7b, the third conductive layer 300 is used to form the gates of transistors (e.g., 201g-207g) in the pixel circuit and at least one structure of the gate line pattern GA, the light-emitting control signal line pattern EM, the first reset signal line pattern RST1, and the second reset signal line pattern RST2 included in the display panel. Optionally, the gate 203g of the third transistor T3 of the pixel circuit is multiplexed as the first plate Cst1 of the first capacitor Cst of the pixel circuit. Of course, the gate 203g of the third transistor T3 of the pixel circuit can also be multiplexed as the second plate Cst2 of the first capacitor Cst of the pixel circuit.

[0082] As shown in FIGS. 5a to 5i, 6c, and 7c, the second conductive layer 200 includes a plurality of auxiliary conductive portions WD, a plurality of storage conductive portions WCst2 spaced apart from the auxiliary conductive portions WD, and a first initialization signal line pattern VINT1 and a second initialization signal line pattern VINT2 included in the display panel. Here, each subpixel includes the auxiliary conductive portions. In the same subpixel, the orthogonal projection of the auxiliary conductive portion WD on the base substrate 1000 at a first end thereof and the orthogonal projection of the power signal line pattern on the base substrate 1000 have an overlapping region, and the orthogonal projection of the auxiliary conductive portion WD on the base substrate 1000 at a second end thereof and the orthogonal projection of the data line pattern on the base substrate 1000 have an overlapping region. Optionally, the auxiliary conductive portion WD at least partially overlaps the power signal line pattern, the data line pattern, and the touch electrode.

[0083] The subpixel also includes a storage conductive portion Cst2 for forming the second plate Cst2 of the first capacitor Cst. That is, the storage conductive portion Cst2 functions as the second plate Cst2 of the first capacitor Cst. Of course, the storage conductive portion Cst2 can also serve as the first plate Cst1 of the first capacitor Cst. The shape and structure of the auxiliary conductive portion WD are not limited and may be a rectangular shape with a regular pattern or an irregular pattern with at least one side arc. Exemplarily, one end of the auxiliary conductive portion WD extends to the other end of the auxiliary conductive portion in the row direction F4.

[0084] As shown in Figures 3, 5a to 5i, 6d, and 7d, the first conductive layer 100 is used to form the sources (e.g., S1 to S7) and drains (e.g., D1 to D7) of each transistor in the pixel circuit, as well as the data line patterns (e.g., DA1, DA2, DA3, DA4, and DA5) and power signal line pattern VDD included in the display panel. Optionally, the width of the power signal line pattern VDD is greater than the width of the data line patterns (e.g., DA1, DA2, DA3, DA4, and DA5). Note that the connecting lines 401, 402, 403, and 404 in Figures 6d and 7d can be formed using the first conductive layer, and specific layouts are shown in Figures 5a to 5i, 6d, and 7d.

[0085] Of course, in actual applications, the data line pattern DA and the power signal line pattern VDD do not necessarily need to be formed on the same conductive layer. For example, as shown in FIGS. 7g and 7h, the first conductive layer 100 may include a stacked first sub-conductive layer 111 and a second sub-conductive layer 112. A first sub-insulating layer (not shown) is provided between the first sub-conductive layer 111 and the second sub-conductive layer 112. Exemplarily, at least one of the connecting lines 401, 402, 403, and 404 may be disposed on the same layer as the data line patterns (DA1, DA2, etc.) or the power signal line pattern VDD. For example, the data line patterns (DA1, DA2, etc.) and the connecting lines 401, 402, and 403 may be disposed on the first sub-conductive layer 111, and the power signal line pattern VDD may be disposed on the second sub-conductive layer 112. That is, the data line patterns (DA1, DA2, etc.) and the power signal line pattern VDD may not be disposed on the same conductive layer.

[0086] For example, the first sub-conductive layer 111 on which the data line patterns (DA1, DA2, etc.) are located is closer to the base substrate 1000 than the second sub-conductive layer on which the power signal line patterns VDD are located.

[0087] For example, the connecting line 404 as a connecting structure between adjacent initialization signal line patterns may be located in a sub-pixel or non-display area, for example, connecting the first initialization signal line pattern VINT1 and the second initialization signal line pattern VINT2.

[0088] 3, 5a to 5i to 7d for more details, the gate 201g of the first transistor T1 overlaps the first channel region 101pg, the source S1 of the first transistor T1 is located in the first source forming region 101ps, and the drain D1 of the first transistor T1 is located in the first drain forming region 101pd.

[0089] The gate 202g of the second transistor T2 overlaps the second channel region 102pg, the source S2 of the second transistor T2 is located in the second source forming region 102ps, and the drain D2 of the second transistor T2 is located in the second drain forming region 102pd.

[0090] The gate 203g of the third transistor T3 overlaps with the third channel region 103pg, the source S3 of the third transistor T3 is located in the third source forming region 103ps, and the drain D3 of the third transistor T3 is located in the third drain forming region 103pd.

[0091] The gate 204g of the data write transistor T4 overlaps with the fourth channel region 104pg, the source S4 of the data write transistor T4 is located in the fourth source forming region 104ps, and the drain D4 of the data write transistor T4 is located in the fourth drain forming region 104pd.

[0092] The gate 205g of the fifth transistor T5 overlaps the fifth channel region 105pg, the source S5 of the fifth transistor T5 is located in the fifth source forming region 105ps, and the drain D5 of the fifth transistor T5 is located in the fifth drain forming region 105pd.

[0093] The gate 206g of the sixth transistor T6 overlaps the sixth channel region 106pg, the source S6 of the sixth transistor T6 is located in the sixth source forming region 106ps, and the drain D6 of the sixth transistor T6 is located in the sixth drain forming region 106pd.

[0094] The gate 207g of the seventh transistor T7 overlaps the seventh channel region 107pg, the source S7 of the seventh transistor T7 is located in the seventh source forming region 107ps, and the drain D7 of the seventh transistor T7 is located in the seventh drain forming region 107pd.

[0095] The gate 203g of the third transistor T3 is multiplexed as a first plate Cst1 of the first capacitor Cst, and a second plate Cst2 of the first capacitor Cst is coupled to the power signal line pattern VDD.

[0096] Optionally, the conductive portion of the capacitor may include an auxiliary conductive portion WD, which may include the second plate C12 of the second capacitor C1. That is, the auxiliary conductive portion may partially or completely function as the second plate C12 of the second capacitor C1. For example, in the same subpixel, the auxiliary conductive portion WD may be used as the second plate C12 of the second capacitor C1, and the data line pattern DA may be used as the first plate C11 of the second capacitor C1. Alternatively, the data line pattern DA, which has an overlapping area with the first electrode plate C11 of the second capacitor C1, may be used as the first plate C11 of the second capacitor C1.

[0097] As shown in FIGS. 5a to 5i, 6e, and 7e, the first electrode layer 500 is used to form first electrodes (e.g., 510, 520, 530, 540) of the light-emitting element L. Illustratively, the first electrodes are anodes (e.g., 510, 520, 530, 540) of the light-emitting element L. Note that the pixel-defining layer 950 includes multiple aperture areas (e.g., KK1, KK2, KK3, and KK4). Here, one first electrode corresponds to one aperture area, and the orthogonal projection of the aperture area on the base substrate 1000 is located within the orthogonal projection of the corresponding first electrode on the base substrate 1000. For example, the aperture area KK1 corresponds to the first electrode 510, the aperture area KK2 corresponds to the first electrode 520, the aperture area KK3 corresponds to the first electrode 530, and the aperture area KK4 corresponds to the first electrode 540. Illustratively, the first electrode may be electrically connected directly to the semiconductor layer, or may be electrically connected to the semiconductor layer via another conductive layer, such as the first conductive layer 100.

[0098] As shown in FIGS. 5a to 5i, 6f, and 7f, the light-emitting functional layer 600 is used to form the light-emitting layers of the light-emitting element L. For example, the light-emitting functional layer 600 includes a first-color light-emitting layer 610, a second-color light-emitting layer 620, a third-color light-emitting layer 630, and a fourth-color light-emitting layer 640. The light-emitting functional layer 600 may also include film layers such as a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer. The boundaries of the first-color light-emitting layer 610, the second-color light-emitting layer 620, the third-color light-emitting layer 630, and the fourth-color light-emitting layer 640 may or may not overlap. For example, at least two of the first-color light-emitting layer 610, the second-color light-emitting layer 620, the third-color light-emitting layer 630, and the fourth-color light-emitting layer 640 have overlapping regions. For example, the boundary of the first-color light-emitting layer 610 extends to the second-color light-emitting layer 620.

[0099] As shown in FIG. 2, the sealing layer FB may include at least one layer of FB1, FB2, and FB3, where at least one of FB1, FB2, and FB3 is an inorganic, organic, or organic-inorganic composite material. The inorganic material may be at least one of silicon nitride (SiNx), silicon oxide (SiOx), and silicon oxynitride (SiON), and the organic material may be polyimide (PI). For example, the sealing layer FB may include a first inorganic sealing layer FB1, an organic sealing layer FB2, and a second inorganic sealing layer FB3, which are stacked together. Here, the organic sealing layer FB2 is located on the inner periphery of the barrier 110 and covers the display area AA, the barrier 110, and the peripheral area of ​​the barrier 110. Here, the orthogonal projections of the first inorganic sealing layer FB1 on the base substrate 1000 and the second inorganic sealing layer FB3 on the base substrate 1000 overlap. In this way, by extending the first inorganic sealing layer FB1 and the second inorganic sealing layer FB3 to the peripheral region of the barrier 110, the organic sealing layer FB and the display region can better block moisture and oxygen.

[0100] As shown in FIGS. 2, 6g, 8a, and 8b, the touch electrode 800 includes a plurality of first touch electrodes 810 and a plurality of second touch electrodes 820 arranged in a cross pattern. The shape of the orthogonal projection of the touch electrode 800 on the base substrate 1000 is a grid. Illustratively, the orthogonal projection of the touch electrode 800 on the base substrate 1000 does not overlap with the orthogonal projection of the opening regions (e.g., KK1, KK2, KK3, and KK4) on the base substrate 1000. It can be understood that in a display panel, the touch electrode 800 may be at least one of the plurality of first touch electrodes 810 and the plurality of second touch electrodes 820 in a partial display region of the display panel. For example, the touch electrode 800 may be located in a partial subpixel region of the display panel. For example, the first color, the second color, the third color, and the fourth color may at least partially correspond to the subpixel regions, and the touch electrode may include only the plurality of first touch electrodes 810 or the plurality of second touch electrodes 820.

[0101] Exemplarily, the plurality of first touch electrodes 810 are disposed on the same conductive film layer, and the plurality of second touch electrodes 820 are disposed on the same conductive film layer. The layer on which the first touch electrodes 810 are disposed is on the encapsulation layer FB side away from the base substrate 1000, and the layer on which the second touch electrodes 820 are disposed is on the package layer FB side. The layer on which the first touch electrodes 810 are disposed is on the second touch electrode 820 side away from the base substrate 1000. An electrode insulating layer 830 is provided between the layer on which the first touch electrodes 810 are disposed and the layer on which the second touch electrodes 820 are disposed. Exemplarily, the electrode insulating layer 830 may be disposed in the display area and cover the display area. The electrode insulating layer 830 may also cover not only the display area but also the non-display area. Alternatively, an end of the electrode insulating layer 830 may be disposed between two barriers BK. Of course, in actual applications, the configuration may be designed according to the actual application, and is not limited thereto.

[0102] Exemplarily, one or more insulating layers (not shown) may be provided between the first touch electrode 810 and the encapsulation layer FB. At least one insulating layer may be an inorganic, organic, or organic-inorganic composite material, and the inorganic material may be at least one of silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), etc. The organic material may be polyamide (PI), etc. For example, at least one touch electrode substrate may be provided between the first touch electrode 810 and the encapsulation layer FB3, and the material may be silicon nitride (SiNx), silicon oxide (SiOx), or polyimide (PI).

[0103] For example, the touch electrode substrate may be located in the display area and cover the display area. The electrode insulating layer 830 may cover not only the display area but also the non-display area. Alternatively, the edge of the touch electrode substrate may be located between two barriers BK. Of course, in practical applications, the touch electrode substrate may be designed according to the practical application, and is not limited thereto.

[0104] 8a, the orthogonal projections of the first touch electrodes 810 on the base substrate 1000 and the orthogonal projections of the second touch electrodes 820 on the base substrate 1000 may have a strip-like shape. Because the first touch electrodes 810 and the second touch electrodes 820 are arranged crosswise, the orthogonal projections of the first touch electrodes 810 on the base substrate 1000 and the orthogonal projections of the second touch electrodes 820 on the base substrate 1000 may have a grid-like shape. Alternatively, as shown in FIG. 8b, the orthogonal projections of the first touch electrodes 810 on the base substrate 1000 and the orthogonal projections of at least a portion of the second touch electrodes 820 on the base substrate 1000 may have a grid-like shape.

[0105] Exemplarily, the first touch electrodes 810 and the second touch electrodes 820 are arranged in a cross-like manner, and the orthogonal projections of the first touch electrodes 810 on the base substrate 1000 and the orthogonal projections of the second touch electrodes 820 on the base substrate 1000 are formed in a grid shape. Alternatively, the first touch electrodes 810 and the second touch electrodes 820 are at least partially overlapped, and the orthogonal projections of the first touch electrodes 810 on the base substrate 1000 and the orthogonal projections of the second touch electrodes 820 on the base substrate 1000 overlap.

[0106] Of course, the present application includes, but is not limited to, this. In practical applications, it can be designed according to the requirements of the practical application, but is not limited to this. The second touch electrode 820 shown in Figure 8b is taken as an example for explanation.

[0107] 8c and 8d, first touch electrodes 810 are electrically connected by a first bridge portion 811. Here, a first end of the first bridge portion 811 is electrically connected to the first touch electrode 810 through a via 831 that penetrates the electrode insulating layer 830, and a second end of the first bridge portion 811 is electrically connected to another first touch electrode 810 through a via 832 that penetrates the electrode insulating layer 830. Similarly, as shown in FIGS. 8c and 8d, second touch electrodes 820 are electrically connected by a second bridge portion 821. Here, a first end of the second bridge portion 821 is electrically connected to the second touch electrode 820 through a via that penetrates the electrode insulating layer 830, and a second end of the second bridge portion 821 is electrically connected to another second touch electrode 820 through a via that penetrates the electrode insulating layer 830.

[0108] It should be noted that the light-emitting element can be configured as an electroluminescent diode, such as at least one of an organic light-emitting diode (OLED) and a quantum dot light-emitting diode (QLED). The light-emitting element may include a stacked first electrode 500 (e.g., an anode of the light-emitting element), a light-emitting functional layer 600, and a second electrode 700 (e.g., a cathode of the light-emitting element). Of course, the present application is not limited thereto, but includes this. In practical applications, it can be designed according to the requirements of the practical application, but is not limited thereto.

[0109] In practical applications, the materials of the third conductive layer 300, the second conductive layer 200, the first conductive layer 100, the second touch electrode 820, and the first touch electrode 810 may be the same or different. At least one of the third conductive layer 300, the second conductive layer 200, the first conductive layer 100, the second touch electrode 820, and the first touch electrode 810 includes a metallic material, an alloy material, or another conductive material such as a metal. The metal may be, for example, at least one of aluminum (Al), titanium (Ti), molybdenum (Mo), a molybdenum-niobium alloy, an aluminum-neodymium alloy, graphene, etc.

[0110] Optionally, at least one of third conductive layer 300, second conductive layer 200, first conductive layer 100, second touch electrode 820, and first touch electrode 810 forms a single layer structure or a laminate structure with sub-layers of molybdenum / aluminum / molybdenum, titanium / aluminum / titanium material.

[0111] Optionally, the thickness of at least one of the third conductive layer 300, the second conductive layer 200, the first conductive layer 100, the second touch electrode 820, and the first touch electrode 810 is in the range of 100 nm to 500 nm.

[0112] For example, the third conductive layer 300, the second conductive layer 200, and the first conductive layer 100 may be selected from at least one of metal aluminum (Al), titanium (Ti), molybdenum (Mo), etc. Alternatively, at least one of the second touch electrode 820 and the first touch electrode 810 may have a laminated structure obtained by forming sublayers of titanium / aluminum / titanium. Alternatively, at least one of the materials of the second touch electrode 820 and the first touch electrode 810 may include graphene. Because the surface reflectivity of the conductive layer is high, for example, the surface reflectivity of the metal molybdenum material is high, which tends to reflect external light and light emitted by the light-emitting functional layer to the second capacitor C1. This may cause a problem of 600° reflection into adjacent opening regions, resulting in crosstalk of light emission and reduced light mixing efficiency.

[0113] Taking this into consideration, embodiments of the present application provide several display panels. As shown in Figures 5a to 5i to 7f, the display panel includes an overlapping unit, and the overlapping unit may include multiple subpixels. For example, the multiple subpixels may include a first-color subpixel, a second-color subpixel, and a third-color subpixel. In other words, the overlapping unit may include a first-color subpixel, a second-color subpixel, and a third-color subpixel. In this way, the display panel can achieve color display by using the first-color subpixel, the second-color subpixel, and the third-color subpixel for light mixing. In some examples, the first color, the second color, and the third color may be selected from red, green, and blue. For example, the second color is red, the first color is green, and the third color is blue. Of course, embodiments of the present application include, but are not limited to, this. The above first color, second color, and third color may also be other colors.

[0114] Optionally, the overlapping unit may also include a fourth color subpixel. In this manner, the display panel may achieve color display by using the first color subpixel, the second color subpixel, the third color subpixel, and the fourth color subpixel for light mixing. In some examples, the fourth color subpixel may be a green subpixel, a white subpixel, a yellow subpixel, or other colors not limited to this specification.

[0115] Hereinafter, the overlapping unit includes a first color subpixel, a second color subpixel, a third color subpixel, and a fourth color subpixel, where the first color and the fourth color are green, the second color is red, and the third color is blue. Take blue as an example.

[0116] 5a to 5i to 7f, a first-color subpixel includes a pixel circuit of any of the previous embodiments, a first electrode 510, a first-color light-emitting layer 610, and an opening KK1. Here, the orthogonal projection of the first-color light-emitting layer 610 on the base substrate 1000 covers the orthogonal projection of the opening region KK1 of the first-color subpixel on the base substrate 1000, and the first-color subpixel includes the opening region KK1. As an example, the opening region KK1 may be used as the light-emitting region of the first-color subpixel.

[0117] Also, the second-color subpixel has a pixel circuit of any of the above-described embodiments, a first electrode 520, a second-color light-emitting layer 620, and an aperture region KK2, where the orthogonal projection of the second-color light-emitting layer 620 on the base substrate 1000 covers the orthogonal projection of the aperture region KK2 on the aperture region KK2 of the second-color subpixel on the base substrate 1000. As an example, the aperture region KK2 may be used as the light-emitting region of the second-color subpixel.

[0118] The third-color subpixel also includes a pixel circuit according to any of the above embodiments, a first electrode 530, a third-color light-emitting layer 630, and an aperture region KK3. Here, the orthogonal projection of the third-color light-emitting layer 630 on the base substrate 1000 covers the orthogonal projection of the aperture region KK3 of the third-color subpixel on the base substrate 1000, and the light-emitting region of the third-color subpixel includes the aperture region KK3. As an example, the aperture region KK3 may be used as the light-emitting region of the third-color subpixel.

[0119] The fourth-color subpixel also includes a pixel circuit according to any of the above embodiments, a first electrode 540, a fourth-color light-emitting layer 640, and an aperture region KK4. Here, the orthogonal projection of the fourth-color light-emitting layer 640 on the base substrate 1000 covers the orthogonal projection of the aperture region KK4 of the fourth-color subpixel on the base substrate 1000, and the light-emitting region of the fourth-color subpixel includes the aperture region KK4. Exemplarily, the aperture region KK4 can be used as the light-emitting region of the fourth-color subpixel.

[0120] Here, the area of ​​the aperture region KK1 in the first color subpixel is smaller than the area of ​​the aperture region KK3 in the third color subpixel, the area of ​​the aperture region KK2 in the second color subpixel is smaller than the area of ​​the aperture region KK3 in the third color subpixel, and the area of ​​the aperture region KK4 in the fourth color subpixel is smaller than the area of ​​the aperture region KK3 in the third color subpixel.

[0121] For example, if the luminous efficiency of the green and red light-emitting elements is higher than that of the blue light-emitting element, the effect on adjacent subpixels will be greater. Therefore, the area of ​​the aperture region of the green subpixel is made smaller than that of the blue subpixel. The area of ​​the aperture region of the red subpixel is smaller than that of the blue subpixel, thereby improving the emission of blue light. Furthermore, this also results in a larger portion of the second capacitor C1 of the green and red subpixels being unobstructed by the aperture region, increasing the exposure of the second capacitor C1, resulting in luminous interference and reduced light mixing efficiency.

[0122] Specifically, in an embodiment of the present application, as shown in FIGS. 3 to 6g, the transistor array layer includes a plurality of capacitor conductive portions R, and at least a portion of the subpixels include the capacitor conductive portion R. Here, there is an overlapping area between the capacitor conductive portion R and the power supply signal line pattern VDD and / or the data line pattern in the same subpixel. For example, there is an overlapping area between the capacitor conductive portion R, the power supply signal line pattern VDD, and the data line pattern in the same subpixel. Alternatively, there is an overlapping area between the capacitor conductive portion R and the power supply signal line pattern VDD in the same subpixel. Alternatively, there is an overlapping area between the capacitor conductive portion R and the data line pattern in the same subpixel. Optionally, the overlapping area between the capacitor conductive portion R and the power supply signal line pattern VDD is larger than the overlapping area between the capacitor conductive portion R and the data line pattern DA.

[0123] 3 to 6g, the orthogonal projection of the capacitor conductive portion R in the first color subpixel on the base substrate 1000 and the orthogonal projection of the touch electrode (e.g., the second touch control electrode 820) on the base substrate 1000 has a first auxiliary overlapping area S1. The orthogonal projection of the capacitor conductive portion R in the second color subpixel on the base substrate 1000 and the orthogonal projection of the touch electrode (e.g., the second touch electrode 820) on the base substrate 1000 has a second auxiliary overlapping area S2. The orthogonal projection of the capacitor conductive portion R in the third color subpixel on the base substrate 1000 and the orthogonal projection of the touch electrode (e.g., the second touch electrode 820) on the base substrate 1000 has a third auxiliary overlapping area S3. The orthogonal projection of the capacitor conductive portion R in the fourth-color subpixel on the base substrate 1000 and the orthogonal projection of the touch electrode (e.g., the second touch electrode 820) on the base substrate 1000 has a fourth auxiliary overlapping area S4. Here, at least one of the first auxiliary overlapping area S1, the second auxiliary overlapping area S2, and the fourth auxiliary overlapping area S4 is larger than the third auxiliary overlapping area S3. For example, the first auxiliary overlapping area S1 is larger than the second auxiliary overlapping area S2, and the second auxiliary overlapping area S2 is larger than the third auxiliary overlapping area S3, or the first auxiliary overlapping area S1 is larger than the second auxiliary overlapping area S2 and the second auxiliary overlapping area S2 is equal to the third auxiliary overlapping area S3. Alternatively, the first auxiliary overlapping area S1 is approximately equal to the second auxiliary overlapping area S2, and the second auxiliary overlapping area S2 is larger than the third auxiliary overlapping area S3. In this way, the second capacitor C1 can be shielded by the touch electrode 800, thereby improving the problems of light emission interference and poor light mixing effect caused by the second capacitor C1.

[0124] 3 to 6g, the transistor array layer ZA includes a plurality of data line patterns (DA1, DA2, etc.) and a plurality of power signal line patterns (VDD, etc.), and the transistor array layer ZA includes a plurality of capacitor conductive portions R. The subpixel includes the capacitor conductive portion R, and the capacitor conductive portion R overlaps with the power signal line pattern VDD and / or the data line pattern DA. For example, the capacitor conductive portions R are formed on the second conductive layer 200. Of course, they may also be formed on other conductive layers, such as the first conductive layer.

[0125] Optionally, at least a portion of the capacitor conductive portion R and the power supply signal line pattern VDD or the data line pattern DA form a capacitor. That is, there is at least one insulating layer between the capacitor conductive portion R and the power supply signal line pattern VDD or the data line pattern DA. For example, the conductive portion R of the capacitor forms a capacitor plate of a second capacitor C1. Specifically, some or all of the conductive portions of the capacitor constitute the first plate C11 or the second plate C12 of the second capacitor.

[0126] Optionally, the capacitor conductive portions R may be arcuate or have an irregular pattern.

[0127] Optionally, the capacitor conductive portion R includes an auxiliary conductive portion WD formed on the second conductive layer 200, the auxiliary conductive portion WD being located under the data line pattern (e.g., DA1, DA2), and a first end of the auxiliary conductive portion connected to the power signal line pattern VDD. For example, the first end of the auxiliary conductive portion WD is connected to the power signal line pattern VDD through a via in the first interlayer insulating layer 930. The second end of the auxiliary conductive portion WD extends to under the data line pattern. The auxiliary conductive portion WD and the power signal line pattern and / or the data line pattern have an overlapping area. That is, in this case, the second plate C12 of the second capacitor C1 is formed on the auxiliary conductive portion WD, and the first plate of the second capacitor C1 is formed on the data line pattern DA (e.g., DA1, DA2) corresponding to the subpixel. Or, the first plate of the second capacitor C1 is formed on the data line pattern DA (e.g., DA1, DA2) corresponding to the subpixel having an overlapping area with the auxiliary conductive portion WD.

[0128] Optionally, the capacitor conductive portion R may further include a second auxiliary conductive portion WN2 (not shown), which is formed on the second conductive layer 200 and is formed under a data line pattern (e.g., DA1, DA2) corresponding to a subpixel. A first end of the second auxiliary conductive portion WD2 is connected to a data line pattern (e.g., data line pattern DA1) corresponding to each subpixel. For example, the first end of the second auxiliary conductive portion WD2 is connected to a data line pattern (e.g., data line pattern DA1) corresponding to each subpixel through a via in the first interlayer insulating layer 930. A second end of the second auxiliary conductive portion WN2 extends under the power signal line pattern, and there is an overlapping region between the second auxiliary conductive portion WN2 and the power signal line pattern and / or the data line pattern. That is, in this case, the first plate of the second capacitor C1 is formed on the second auxiliary conductive portion WD2, and the second plate of the second capacitor C1 is the power signal line pattern VDD, or the second plate of the second capacitor C1 is formed on the power signal line pattern VDD corresponding to the subpixel having an overlapping area with the second auxiliary conductive portion WD2.

[0129] For ease of understanding, at least some of the following embodiments will be described by taking the capacitor conductive portion R as the auxiliary conductive portion WD. For example, the area of ​​the opening region KK1 in the first color subpixel is smaller than the area of ​​the opening region KK3 in the third color subpixel. Therefore, the capacitor conductive portion R in the first color subpixel is less blocked by the opening region, while the capacitor conductive portion R in the third color subpixel is more blocked by the opening region. This enhances the light-emitting effect of the capacitor conductive portion R in the first color subpixel. In the embodiment of the present application, the first auxiliary overlapping area S1 is larger than the third auxiliary overlapping area S3. This increases the portion of the capacitor conductive portion R in the first color subpixel that is blocked by the touch electrode 800, thereby solving the problems of light-emitting interference and poor light-mixing effect caused by the capacitor conductive portion R in the first color subpixel.

[0130] For example, because the area of ​​the aperture region KK2 in the second color subpixel is smaller than the area of ​​the aperture region KK3 in the third color subpixel, the capacitor conductive portion R in the second color subpixel is less blocked by the aperture region, but the capacitor conductive portion R in the third color subpixel is more blocked by the aperture region, resulting in a stronger luminous effect for the capacitor conductive portion R in the second color subpixel. In the embodiment of the present application, the second auxiliary overlapping area S2 is larger than the third auxiliary overlapping area S3, so that the capacitor conductive portion R in the second color subpixel is more blocked by the touch electrode 800, thereby improving the luminous interference and poor light mixing effect caused by the capacitor conductive portion R in the second color subpixel.

[0131] For example, because the area of ​​the opening region KK4 in the fourth color subpixel is smaller than the area of ​​the opening region KK3 in the third color subpixel, the capacitor conductive portion R in the fourth color subpixel is less blocked by the opening region, but the capacitor conductive portion R in the third color subpixel is more blocked by the opening region, resulting in a stronger luminous effect for the capacitor conductive portion R in the fourth color subpixel. In an embodiment of the present application, the fourth auxiliary overlapping area S4 is made larger than the third auxiliary overlapping area S3, so that the capacitor conductive portion R in the fourth color subpixel can be more blocked by the touch electrode 800, thereby alleviating the problems of luminous interference and reduced light mixing effect caused by the capacitor conductive portion R in the four-color subpixel.

[0132] Specifically, in the embodiment of the present application, as shown in FIG. 6e, the area of ​​the opening region KK1 in the first color subpixel may be smaller than the area of ​​the opening region KK2 in the second color subpixel. For example, the area of ​​the opening region of the green subpixel may be smaller than the area of ​​the opening region of the red subpixel. Thus, compared with the second color subpixel, the first color subpixel has a smaller portion of the capacitor conductive portion R blocked by the opening region. However, in the embodiment of the present application, the first auxiliary overlapping area S1 is approximately equal to or larger than the second auxiliary overlapping area S2. Therefore, compared with the second color subpixel, the capacitor conductive portion R can be blocked by the touch electrode 800 to a greater extent. As a result, the light emission interference and insufficient light mixing caused by the capacitor conductive portion R in the first color subpixel are further reduced.

[0133] Specifically, in the embodiment of the present application, the area of ​​the opening region KK1 of the first color subpixel is 100 μm 2 ~130μm 2The shape of the aperture region KK1 is not limited. It may be a polygon, rectangle, square, rhombus, ellipse, circle, or the like. Of course, other irregular patterns are also possible, such as a closed shape consisting of at least two arc segments and one straight line segment. For example, the aperture region KK1 of the first color subpixel is rectangular, with a first side length of 12 μm to 13 μm and a second side length of 9 μm to 10 μm.

[0134] Optionally, the aperture area of ​​the first color subpixel KK1 is 10*10 μm 2 ~12*10μm 2 or 11*10μm 2 ~12*10μm 2 Optionally, the aperture area of ​​the aperture area KK1 of the first color subpixel is 13*9 μm 2 ~12*10μm 2 For example, the area of ​​the opening region KK1 of the first color subpixel is 13*9 μm 2 (length × width), or the area of ​​the aperture area KK1 of the first color subpixel is 12*10 μm 2 (length * width). Of course, in practical applications, the design can be determined according to the requirements of the practical application environment, and is not limited thereto.

[0135] Specifically, in the embodiment of the present application, the area of ​​the opening region KK2 of the second color subpixel is 120 μm 2 ~200μm 2 The shape of the aperture region KK2 is not limited. For example, it may be a polygon, a rectangle, a square, a rhombus, an ellipse, a circle, etc. Of course, it may be other irregular patterns, such as a closed figure consisting of at least two arc segments and one straight line segment. For example, the aperture region KK2 of the second color subpixel is a square with a side length of 13 μm to 15 μm. Optionally, the aperture area of ​​the aperture region KK2 of the second color subpixel may be 13*10 μm. 2 ~19*10μm 2 or 13*15μm 2 ~18*11μm2 Optionally, the aperture area of ​​the aperture region KK1 of the first color subpixel is 13*13 μm 2 ~14*14μm 2 For example, the area of ​​the opening region KK2 of the second color subpixel may be 13*13 μm 2 The area of ​​the opening region KK2 of the second color subpixel may be 14*14 μm 2 Of course, in practical applications, the design can be determined according to the requirements of the practical application environment, and is not limited thereto.

[0136] Specifically, in the embodiment of the present application, the area of ​​the opening region KK3 of the third color subpixel is 180 μm 2 ~230μm 2 The shape of the aperture region KK3 is not limited. It may be a polygon, rectangle, square, rhombus, ellipse, circle, etc. Of course, other irregular patterns may be used, such as a closed figure consisting of at least two arc segments and one straight line segment. For example, the aperture region KK3 of the third color subpixel is rectangular, with the length of the first side being 15 μm-16 μm, and the length of the second side of the aperture region KK1 of the first color subpixel being 13 μm-14 μm. Optionally, the aperture area of ​​the aperture region KK3 of the third color subpixel may be 18*10 μm. 2 ~23*10μm 2 or 20*10μm 2 ~22*10μm 2 Optionally, the aperture area of ​​the aperture region KK1 of the first color subpixel is 15*13 μm 2 ~16*14μm 2 For example, the area of ​​the opening region KK3 of the third color subpixel may be 15*13 μm 2 Alternatively, the area of ​​the opening region KK3 of the third color subpixel may be 16*13 μm 2 Alternatively, the area of ​​the opening region KK3 of the third color subpixel may be 16*14 μm 2(length x width). Of course, in actual applications, the design can be determined according to the requirements of the actual application environment, and is not limited thereto.

[0137] Specifically, in the embodiment of the present application, the area of ​​the opening region KK4 of the fourth color subpixel is 100 μm 2 ~230μm 2 The shape of the opening region KK4 is not limited. For example, it may be a polygon, a rectangle, a square, a diamond, an ellipse, a circle, etc. Of course, it may be other irregular patterns, such as a closed figure consisting of at least two arc segments and one straight line segment. For example, the opening region of the fourth color subpixel is elliptical and has an area of ​​100 μm. 2 ~130μm 2 Alternatively, the aperture region KK4 of the fourth color subpixel has a rectangular shape, the length of a first side of which is 12 μm-13 μm, and the length of a second side of which is 9 μm-10 μm. Optionally, the aperture area of ​​the aperture region KK1 of the first color subpixel is 13*9 μm. 2 ~12*10μm 2 For example, the area of ​​the aperture region KK4 of the fourth color subpixel is 13*9 μm 2 (length × width), and the area of ​​the opening region KK4 of the fourth color subpixel may be 12*10 μm 2 (length * width). Of course, in actual applications, the design can be determined according to the requirements of the actual application environment, and is not limited thereto.

[0138] Specifically, in the embodiment of the present application, the first auxiliary overlap region S1 is 3 μm 2 ~40μm 2 Optionally, the first auxiliary overlap area S1 may be 6 μm 2 ~20μm 2 For example, the first auxiliary overlap region S1 may be 3 μm 2 Alternatively, the first auxiliary overlapping area S1 may be 6 μm 2 Alternatively, the first auxiliary overlapping area S1 may be 10 μm 2Alternatively, the first auxiliary overlapping area S1 may be 20 μm 2 Alternatively, the first auxiliary overlapping area S1 may be 30 μm 2 Of course, in practical applications, the design can be determined according to the requirements of the practical application environment, and is not limited thereto.

[0139] In a specific implementation, in the embodiment of the present application, the second auxiliary overlap area S2 is 0 to 10 μm 2 Optionally, the second auxiliary overlap area S2 may be 0 to 5 μm 2 For example, the second auxiliary overlapping area S2 may be 0 μm 2 Alternatively, the second auxiliary overlapping area S2 may be 5 μm 2 Alternatively, the second auxiliary overlapping area S2 may be 10 μm 2 Of course, in practical applications, the design can be determined according to the requirements of the practical application environment, and is not limited thereto.

[0140] In a specific implementation, in the embodiment of the present application, the third auxiliary overlap area S3 is 0 to 6 μm 2 Optionally, the third auxiliary overlap area S3 may be 0 to 3 μm 2 For example, the third auxiliary overlapping area S3 may be 0 μm 2 Alternatively, the third auxiliary overlapping area S3 may be 3 μm 2 Alternatively, the third auxiliary overlapping area S3 may be 6 μm 2 Of course, in practical applications, the design can be determined according to the requirements of the practical application environment, and is not limited thereto.

[0141] In a specific implementation, in the embodiment of the present application, the fourth auxiliary overlapping area S4 is 0 to 40 μm 2 Optionally, the fourth auxiliary overlap area S4 may be 0 to 15 μm 2 For example, the fourth auxiliary overlapping area S4 may be 0 μm 2Alternatively, the fourth auxiliary overlapping area S4 may be 5 μm 2 Alternatively, the fourth auxiliary overlapping area S4 may be 15 μm 2 Alternatively, the fourth auxiliary overlapping area S4 may be approximately equal to at least one of the first auxiliary overlapping area S3, the second auxiliary overlapping area S2, and the third auxiliary overlapping area S3, or the fourth auxiliary overlapping area S4 may be equal to at least one of the first auxiliary overlapping area S3, the second auxiliary overlapping area S2, and the third auxiliary overlapping area S3. Of course, in actual applications, the design can be determined according to the requirements of the actual application environment, and is not limited thereto.

[0142] In a specific implementation, in the embodiment of the present application, as shown in Figures 5a to 5i to 6g, the area of ​​the opening region KK1 in the first color subpixel can be larger than the area of ​​the opening region KK4 in the fourth color subpixel. The areas of the opening region KK1 in the first color subpixel and the opening region KK4 in the fourth color subpixel can also be approximately equal. These can be designed and determined according to actual application requirements and are not limited thereto.

[0143] 5a to 5i to 6g, in the embodiment of the present application, the second conductive layer 200 may include a capacitor conductive portion R(WD) (the auxiliary conductive portion WD is taken as the capacitor conductive portion R as an example). For example, the first auxiliary overlapping area S1 may include an overlapping area between an orthogonal projection of an auxiliary conductive portion in a first-color subpixel on the base substrate 1000 and an orthogonal projection of a touch electrode (e.g., the second touch electrode 820) on the base substrate 1000. The second auxiliary overlapping area S2 may include an overlapping area between an orthogonal projection of an auxiliary conductive portion in a second-color subpixel on the base substrate 1000 and an orthogonal projection of a touch electrode (e.g., the second touch electrode 820) on the base substrate 1000. The third auxiliary overlapping area S3 may include an overlapping area between an orthogonal projection of an auxiliary conductive portion in a third-color subpixel on the base substrate 1000 and an orthogonal projection of a touch electrode (e.g., the second touch electrode 820) on the base substrate 1000. The fourth auxiliary overlapping area S4 may include an overlapping area between the orthogonal projection of the auxiliary conductive portion in the fourth color subpixel on the base substrate 1000 and the orthogonal projection of the touch electrode (e.g., the second touch electrode 820) on the base substrate 1000. In this way, the auxiliary conductive portion can be shielded by the touch electrode (e.g., the second touch electrode 820), thereby solving the problems of light interference and insufficient light mixing effect caused by the light reflected by the auxiliary conductive portion.

[0144] 5a to 5i to 9c, in one embodiment of the present application, the auxiliary conductive portion WD in the first-color subpixel includes a first auxiliary exposed portion WD1. The orthogonal projection of the first auxiliary exposed portion WD1 on the base substrate 1000 does not overlap with the orthogonal projections of the data line pattern DA2 and the power signal line pattern VDD on the base substrate 1000. The first auxiliary overlapping area S1 may include a first auxiliary sub-overlapping area S11 between the orthogonal projection of the first auxiliary exposed portion WD1 on the base substrate 1000 and the orthogonal projection of a touch electrode (e.g., the second touch electrode 820) on the base substrate 1000.

[0145] For example, in the first color sub-pixel, the orthogonal projection of the first auxiliary exposure portion WD1 on the base substrate 1000 is located between the orthogonal projections of the data line pattern DA2 and the power signal line pattern VDD on the base substrate 1000.

[0146] Optionally, the orthogonal projection of the first auxiliary exposure portion WD1 on the base substrate 1000 can be located on the orthogonal projection of the data line pattern DA2 on the base substrate 1000, away from the orthogonal projection side of the power supply signal line pattern VDD on the base substrate 1000. Alternatively, the orthogonal projection of the first auxiliary exposure portion WD1 on the base substrate 1000 may be located on the orthogonal projection side of the power supply signal line pattern VDD on the base substrate 1000, away from the data line pattern DA2 on the base substrate 1000.

[0147] The first auxiliary exposure portion WD1 may include a first region WD11 (not shown) of the first auxiliary exposure portion, a second region WD12 (not shown) of the first auxiliary exposure portion, and a third region WD13 of the first auxiliary exposure portion. The first region WD11 of the first auxiliary exposure portion is a first region between the data line pattern DA2 and the orthogonal projection of the power supply signal line pattern VDD on the base substrate 1000, where the orthogonal projection of the auxiliary conductive portion WD on the base substrate 1000 is located. The second region WD12 of the first auxiliary exposure portion is a second region on the orthogonal projection side of the data line pattern DA2 on the base substrate 1000, away from the orthogonal projection of the power supply signal line pattern VDD on the base substrate 1000, where the orthogonal projection of the auxiliary conductive portion WD on the base substrate 1000 is located. The third region WD13 of the first auxiliary exposed portion is a third region on the normal projection side of the power signal line pattern VDD on the base substrate 1000, away from the data line pattern DA2 on the base substrate 1000, where the normal projection of the auxiliary conductive portion WD on the base substrate 1000 is located.

[0148] In a specific implementation, in the embodiment of the present application, the first auxiliary sub-overlap region S11 is 2 μm 2 ~10μm 2 Optionally, the first auxiliary sub-overlap area S11 may be 3 μm 2 ~6 μm 2As an example, the first auxiliary sub-overlap area S11 may be 2 μm 2 Alternatively, the first auxiliary sub-overlap area S11 may be 3 μm 2 Alternatively, the first auxiliary sub-overlapping area S11 may be 5 μm 2 Alternatively, the first auxiliary sub-overlapping area S11 may be 6 μm 2 The first auxiliary sub-overlap area S11 may be 10 μm 2 Of course, in practical applications, the design can be determined according to the requirements of the practical application environment, and is not limited thereto.

[0149] Specifically, in an embodiment of the present application, as shown in Figures 5a to 5i to 6d, in the same subpixel, the orthogonal projection of the auxiliary conductive portion WD on the base substrate 1000 has a total area Sm. Here, the ratio of the first auxiliary overlapping area S1 to the total area Sm may be in the range of 1 / 6 to 3 / 4. Optionally, the ratio of the first auxiliary overlapping area S1 to the total area Sm may be in the range of 1 / 3 to 2 / 3, i.e., 1 / 3≦S1 / Sm≦2 / 3. For example, S1 / Sm=1 / 3, S1 / Sm=2 / 3, or S1 / Sm=1 / 2. Of course, in actual applications, the specific value of S1 / Sm can be set according to the requirements of the actual application and is not limited thereto.

[0150] Specifically, in an embodiment of the present application, as shown in FIGS. 5a to 5i to 6d, in the same subpixel, the orthogonal projections of the auxiliary conductive portions WD on the base substrate 1000 have a total area Sm. Here, the ratio of the first auxiliary sub-overlapping area S11 to the total area Sm may be in the range of 1 / 8 to 2 / 3. Optionally, the ratio of the first auxiliary sub-overlapping area S11 to the total area Sm may be in the range of 1 / 6 to 1 / 3, i.e., 1 / 6≦S11 / Sm≦1 / 3. For example, S11 / Sm=1 / 6, S11 / Sm=1 / 4, or S11 / Sm=1 / 3. Of course, in practical applications, the specific value of S11 / Sm can be set according to the requirements of the practical application and is not limited thereto.

[0151] 9a to 9c, in the first color subpixel, the orthogonal projection of the touch electrode (e.g., the second touch electrode 820) on the base substrate 1000 may be disposed to cover the orthogonal projection of the first auxiliary exposed portion WD1 on the base substrate 1000. This can maximize the coverage of the first auxiliary exposed portion WD1 that may reflect light.

[0152] Specifically, in an embodiment of the present application, as shown in FIGS. 9b and 9c, the auxiliary conductive portion WD in the first-color subpixel may further include a first auxiliary shield portion WZ1. The portion WZ1 overlaps the orthogonal projection of at least one of the data line pattern DA2 and the power signal line pattern VDD on the base substrate 1000 with the orthogonal projection of the first auxiliary shield portion WZ1 on the base substrate 1000. Here, the first auxiliary shield portion WZ1 and the first auxiliary exposed portion WD1 of the same auxiliary conductive portion are integrated to form an auxiliary conductive portion. For example, as shown in FIG. 9b, the width of the first auxiliary exposed portion WD1 in the column direction F3 is approximately equal to the width of the first auxiliary shield portion WZ1 in the column direction F3. This reduces the difficulty of preparing the auxiliary conductive portion in the first-color subpixel. As shown in FIG. 9c, the width of the first auxiliary exposed portion WD1 in the column direction F3 may be smaller than the width of at least a portion of the first auxiliary shield portion WZ1 in the column direction F3. This allows the first auxiliary exposed portion WD1 to be further shielded. For example, the width of the first auxiliary exposed portion WD1 in the row direction F4 can be made smaller than the width of at least a part of the first auxiliary shield portion WZ1 in the row direction F4, which is advantageous in reducing reflected light generated at the exposed auxiliary conductive portions WD.

[0153] Specifically, in one embodiment of the present application, as shown in Figures 5a to 5i to 9c, the auxiliary conductive portion WD in the second-color subpixel includes a second auxiliary exposed portion WD2. The orthogonal projection of the second auxiliary exposed portion WD2 on the base substrate 1000 does not overlap with the orthogonal projections of the data line pattern DA3 and the power signal line pattern VDD on the base substrate 1000. The second auxiliary overlapping area S2 includes a second auxiliary sub-overlapping area S12. The second auxiliary sub-overlapping area S12 is located between the orthogonal projection of the base substrate 1000, the orthogonal projection of the second auxiliary exposed portion WD2 on the base substrate 1000, and the touch electrode (e.g., the second touch electrode 820) on the base substrate 1000. Exemplarily, in the second-color subpixel, the orthogonal projection of the second auxiliary exposed portion WD2 on the base substrate 1000 is located between the orthogonal projections of the data line pattern DA3 and the power signal line pattern VDD on the base substrate 1000. Alternatively, the orthogonal projection of the second auxiliary exposure unit WD2 on the base substrate 1000 is located on the orthogonal projection side of the data line pattern DA3 on the base substrate 1000, away from the orthogonal projection of the power supply signal line pattern VDD on the base substrate 1000. Alternatively, the orthogonal projection of the second auxiliary exposure unit WD2 on the base substrate 1000 is located on the orthogonal projection side of the power supply signal line pattern VDD on the base substrate 1000, away from the data line pattern DA3 on the base substrate 1000.

[0154] In a specific implementation, in the embodiment of the present application, the second auxiliary sub-overlap area S12 is 0 to 4.5 μm 2 Optionally, the second auxiliary sub-overlap area S12 may be 0 to 2.2 μm 2 For example, the second auxiliary sub-overlap area S12 can be 0 μm 2 Alternatively, the second auxiliary sub-overlap area S12 may be 1.5 μm 2 Alternatively, the second auxiliary sub-overlap area S12 may be 2.2 μm 2 Alternatively, the second auxiliary sub-overlapping area S12 may be 3.5 μm 2 Alternatively, the second auxiliary sub-overlap area S12 may be 4.5 μm 2Of course, in practical applications, the design can be determined according to the requirements of the practical application environment, and is not limited thereto.

[0155] In a specific implementation, in an embodiment of the present application, as shown in FIGS. 5a to 5i to 6d, in the same subpixel, for example, the second-color subpixel, the auxiliary conductive portion WD on the base substrate 1000 has a total area Sm. Here, in the same subpixel, the ratio of the second auxiliary overlapping area S2 to the total area Sm (second-color subpixel) may be within a range of 1 / 20 to 3 / 4. Optionally, the ratio of the second auxiliary overlapping area S2 to the total area Sm (second-color subpixel) may be within a range of 1 / 10 to 7 / 20, i.e., 1 / 10≦S2 / Sm≦7 / 20. For example, S2 / Sm=1 / 10, S2 / Sm=1 / 5, or S2 / Sm=7 / 20. Of course, in actual applications, the specific value of S2 / Sm can be set according to the requirements of the actual application and is not limited thereto.

[0156] In a specific implementation, in an embodiment of the present application, as shown in Figures 5a to 5i to 6d, in the same subpixel, for example, a second-color subpixel, the orthogonal projection of the auxiliary conductive portion WD on the base substrate 1000 has a total area Sm. Here, the ratio of the second auxiliary sub overlap area S12 to the total area Sm may range from 1 / 10 to 1 / 2. The ratio of the second auxiliary sub overlap area S12 to the total area Sm may range from 1 / 5 to 1 / 4, i.e., 1 / 5≦S12 / Sm≦1 / 4. For example, S12 / Sm=1 / 4, S12 / Sm=1 / 5, or S12 / Sm=9 / 40. Of course, in actual applications, the specific value of S12 / Sm can be set according to the requirements of the actual application and is not limited thereto.

[0157] During specific implementation, in an embodiment of the present application, as shown in Figures 9a to 9c, in a subpixel of a second color, the orthogonal projection of a touch electrode (e.g., the second touch electrode 820) on the base substrate 1000 covers the orthogonal projection of the second auxiliary exposure portion WD2 on the base substrate 1000. This makes it possible to cover the second auxiliary exposure portion WD2, which may reflect light, as much as possible.

[0158] Specifically, in an embodiment of the present application, as shown in FIGS. 9b and 9c, the auxiliary conductive portion WD in the second-color subpixel may further include a second auxiliary shield portion WZ2. The orthogonal projection of the second auxiliary shield portion WZ2 on the base substrate 1000 overlaps with the orthogonal projection of at least one of the data line pattern and the power signal line pattern VDD on the base substrate 1000. Here, the second auxiliary shield portion WZ2 and the second auxiliary exposed portion WD2 of the same auxiliary conductive portion are integrated to form an auxiliary conductive portion. For example, as shown in FIG. 9b, the width of the second auxiliary exposed portion WD2 in the column direction F3 is approximately equal to the width of the auxiliary shield portion WZ2 in the column direction F3. This reduces the difficulty of preparing the auxiliary conductive portion in the second-color subpixel. As shown in FIG. 9c, the width of the second auxiliary exposed portion WD2 in the column direction F3 may be smaller than the width of at least a portion of the auxiliary shield portion WZ2 in the column direction F3. This allows for further shielding of the second auxiliary exposed portion WD2. For example, the width of the second auxiliary exposed portion WD2 in the row direction F4 is smaller than the width of at least a portion of the second auxiliary shield portion WZ2 in the row direction F4.

[0159] In a specific implementation, in the embodiment of the present application, as shown in Figures 5a to 5i to 6g, the auxiliary conductive portion WD in the third-color subpixel includes a third auxiliary exposed portion WD3. The orthogonal projection of the third auxiliary exposed portion WD3 on the base substrate 1000 does not overlap with the orthogonal projections of the data line pattern DA1 and the power signal line pattern VDD on the base substrate 1000, respectively. The third auxiliary overlapping area S3 includes a third auxiliary sub-overlapping area S13. The third auxiliary sub-overlapping area S13 is located between the orthogonal projection of the third auxiliary exposed portion WD3 on the base substrate 1000 and the orthogonal projection of the touch electrode (e.g., the second touch electrode 820) on the base substrate 1000. Exemplarily, in the third-color subpixel, the orthogonal projection of the third auxiliary exposed portion WD3 on the base substrate 1000 is located between the orthogonal projections of the data line pattern DA1 and the power signal line pattern VDD on the base substrate 1000.

[0160] In a specific implementation, in the embodiment of the present application, the third auxiliary sub-overlap area S13 is 0 to 2.5 μm 2 Optionally, the third auxiliary sub-overlap area S13 may be 0 to 1.2 μm 2 For example, the third auxiliary sub-overlap area S13 can be 0 μm 2 Or, the third auxiliary sub-overlap area S13 can be 0.5 μm 2 Alternatively, the third auxiliary sub-overlap area S13 may be 1.0 μm 2 Alternatively, the third auxiliary sub-overlap area S13 may be 1.2 μm 2 Alternatively, the third auxiliary sub-overlap area S13 may be 2.5 μm 2 Of course, in practical applications, the design can be determined according to the requirements of the practical application environment, and the details are not limited here.

[0161] In a specific implementation, in an embodiment of the present application, as shown in Figures 5a to 5i to 6d, in the same subpixel, for example, in the third-color subpixel, the orthogonal projection of the auxiliary conductive portion WD on the base substrate 1000 has a total area Sm. Here, the ratio of the third auxiliary overlapping area S3 to the total area Sm ranges from 0 to 1 / 2, and optionally, the ratio of the third auxiliary overlapping area S3 to the total area Sm ranges from 0 to 1 / 4, that is, 0≦S3 / Sm≦1 / 4. For example, S3 / Sm=0, S3 / Sm=1 / 16, or S3 / Sm=1 / 4. Of course, in actual applications, the specific value of S3 / Sm can be set according to the requirements of the actual application and is not limited thereto.

[0162] In a specific implementation, in an embodiment of the present application, as shown in FIGS. 5a to 5i to 6d, the orthogonal projection of the auxiliary conductive portion WD on the base substrate 1000 in the same subpixel, for example, in the third-color subpixel, has a total area Sm. Here, the ratio of the third auxiliary sub overlap area S13 to the total area Sm ranges from 0 to 1 / 8. Optionally, the ratio of the third auxiliary sub overlap area S13 to the total area Sm ranges from 0 to 1 / 16, that is, 0≦S13 / Sm≦1 / 16. For example, S13 / Sm=0, S13 / Sm=1 / 16, or S13 / Sm=1 / 32. Of course, in actual applications, the specific value of S13 / Sm can be set according to the requirements of the actual application and is not limited thereto.

[0163] Specifically, in an embodiment of the present application, as shown in Figures 9a to 9c, in a third-color subpixel, a touch electrode (e.g., a second touch electrode 820) may be disposed on the base substrate 1000. The orthogonal projection covers the orthogonal projection of the third auxiliary exposure portion WD3 on the base substrate 1000. This can maximize coverage of the third auxiliary exposure portion WD3 that may reflect light.

[0164] In a specific implementation, in the embodiment of the present application, as shown in FIGS. 9b and 9c, the auxiliary conductive portion WD in the third-color subpixel may further include a third auxiliary shield portion WZ3. The orthogonal projection of the third auxiliary shield portion WZ3 on the base substrate 1000 overlaps with the orthogonal projection of at least one of the data line pattern and the power signal line pattern VDD onto the base substrate 1000. Here, the third auxiliary shield portion WZ3 and the third auxiliary exposed portion WD3 of the same auxiliary conductive portion together form an auxiliary conductive portion. For example, as shown in FIG. 9b, the width of the third auxiliary exposed portion WD3 in the column direction F3 is approximately equal to the width of the third auxiliary shield portion WZ3 in the column direction F3. This reduces the difficulty of preparing the auxiliary conductive portion in the third-color subpixel. As shown in FIG. 9c, the width of the third auxiliary exposed portion WD3 in the column direction F3 may be smaller than the width of at least a portion of the third auxiliary shield portion WZ3 in the column direction F3. This allows for further shielding of the third auxiliary exposed portion WD3. For example, the width of the third auxiliary exposed portion WD3 in the row direction F4 is smaller than the width of at least a part of the third auxiliary shield portion WZ3 in the row direction F4.

[0165] In a specific implementation, in the embodiment of the present application, as shown in FIGS. 5a to 5i to 6g, the auxiliary conductive portion WD in the fourth-color subpixel includes a fourth auxiliary exposed portion WD4. The orthogonal projection of the fourth auxiliary exposed portion WD4 on the base substrate 1000 does not overlap with the orthogonal projections of the data line pattern DA4 and the power signal line pattern VDD on the base substrate 1000. The fourth auxiliary overlapping area S4 includes a fourth auxiliary sub-overlapping area S14. The fourth auxiliary sub-overlapping area S14 is located between the orthogonal projection of the fourth auxiliary exposed portion WD4 on the base substrate 1000 and the orthogonal projection of the touch electrode (e.g., the second touch electrode 820) on the base substrate 1000. Exemplarily, in the fourth-color subpixel, the orthogonal projection of the fourth auxiliary exposed portion WD4 on the base substrate 1000 is located between the orthogonal projections of the data line pattern DA4 and the power signal line pattern VDD on the base substrate 1000.

[0166] In a specific implementation, in an embodiment of the present application, as shown in Figures 5a to 5i to 6d, in the same subpixel, for example, in the fourth-color subpixel, the orthogonal projection of the auxiliary conductive portion WD on the base substrate 1000 has a total area Sm. Here, the ratio range of the fourth auxiliary overlap area S4 to the total area Sm is 1 / 6 to 5 / 6, i.e., 1 / 6≦S4 / Sm≦5 / 6. For example, S4 / Sm=1 / 6, S4 / Sm=2 / 3, or S4 / Sm=5 / 6. Of course, in actual applications, the specific value of S4 / Sm can be set according to the requirements of the actual application and is not limited thereto.

[0167] In a specific implementation, in an embodiment of the present application, as shown in FIGS. 5a to 5i to 6d, in the same subpixel, for example, the fourth-color subpixel, the orthogonal projection of the auxiliary conductive portion WD on the base substrate 1000 has a total area Sm. Here, the ratio range of the overlapping area S14 of the fourth auxiliary subpixel to the total area Sm may be 1 / 3 to 2 / 3, i.e., 1 / 3≦S14 / Sm≦2 / 3. For example, S14 / Sm=1 / 3, S14 / Sm=2 / 3, or S14 / Sm=1 / 2. Of course, in actual applications, the specific value of S14 / Sm can be set according to the requirements of the actual application and is not limited thereto.

[0168] In a specific implementation, in the embodiment of the present application, the fourth auxiliary sub-overlap area S14 is 2 μm 2 ~10μm 2 Optionally, the fourth auxiliary sub-overlap area S14 is 3 μm 2 ~6 μm 2 Illustratively, the fourth auxiliary sub-overlap area S14 is 2 μm 2 Or, the fourth auxiliary sub-overlap area S14 is 3 μm 2 Or, the fourth auxiliary sub-overlap area S14 is 5 μm 2 Or, the fourth auxiliary sub-overlap area S14 is 6 μm 2 Or, the fourth auxiliary sub-overlap area S14 is 10 μm 2Of course, in practical applications, the design can be determined according to the requirements of the practical application environment, and is not limited thereto.

[0169] 9a to 9c, in a fourth-color subpixel, the orthogonal projection of the touch electrode (e.g., the second touch electrode 820) on the base substrate 1000 covers the orthogonal projection of the fourth auxiliary exposed portion WD4 on the base substrate 1000. This maximizes the coverage of the fourth auxiliary exposed portion WD4 that may reflect light.

[0170] In a specific implementation, in the embodiment of the present application, as shown in FIGS. 9b and 9c, the auxiliary conductive portion in the fourth-color subpixel may further include a fourth auxiliary shield portion WZ4. The orthogonal projection of the fourth auxiliary shield portion WZ4 on the base substrate 1000 overlaps with the orthogonal projection of at least one of the data line pattern and the power signal line pattern VDD onto the base substrate 1000. The fourth auxiliary shield portion WZ4 and the fourth auxiliary exposed portion WD4 of the same auxiliary conductive portion are integrally disposed to form the auxiliary conductive portion. For example, as shown in FIG. 9b, the width of the fourth auxiliary shield portion WZ4 in the column direction F3 is approximately equal to the width of the fourth auxiliary shield portion WZ4 in the column direction F3. This reduces the difficulty of preparing the auxiliary conductive portion in the fourth-color subpixel. As shown in FIG. 9c, the width of the fourth auxiliary exposed portion WD4 in the column direction F3 may be smaller than at least a portion of the width of the fourth auxiliary shield portion WZ4 in the column direction F3. This allows the fourth auxiliary exposed portion WD4 to be further shielded. For example, the width of the fourth auxiliary exposed portion WD4 in the row direction F4 may be smaller than at least a portion of the width of the fourth auxiliary shield portion WZ4 in the direction F4.

[0171] In a specific implementation, in an embodiment of the present application, the first auxiliary sub-overlapping area S11 can be larger than the second auxiliary sub-overlapping area S12, as shown in Figures 5a to 5i to 6d. In this way, compared with the first color sub-pixel and the second color sub-pixel, the first color sub-pixel shielded by the touch electrode (e.g., the second touch electrode 820) can have more auxiliary conductive portions, thereby improving the problem of the first auxiliary exposed portion WD1 reflecting light and reducing the light emitting interference and light mixing effect.

[0172] 5a to 5i to 6d, in an embodiment of the present application, the first auxiliary sub-overlapping area S11 can be larger than the third auxiliary sub-overlapping area S13. In this way, compared with the first color sub-pixel and the third color sub-pixel, the first color sub-pixel can have more auxiliary conductive portions shielded by the touch electrode (e.g., the second touch electrode 820), thereby improving the problem of the first auxiliary exposed portion WD1 reflecting light and reducing the luminous interference and light mixing effect.

[0173] In a specific implementation, in an embodiment of the present application, as shown in Figures 5a to 5i to 6d, the fourth auxiliary sub-overlapping area S14 can be larger than the second auxiliary sub-overlapping area S12. In this way, compared with the second color sub-pixel, the fourth color sub-pixel can have more auxiliary conductive portions shielded by the touch electrode (e.g., the second touch electrode 820), thereby improving the problem of the fourth auxiliary exposed portion WD4 reflecting light and reducing luminous interference and light mixing effects.

[0174] 5a to 5i to 6d, in the embodiment of the present application, the fourth auxiliary sub-overlapping area S14 can be larger than the third auxiliary sub-overlapping area S13. In this way, the fourth color sub-pixel shielded by the touch electrode (e.g., the second touch electrode 820) can have more auxiliary conductive portions than the third color sub-pixel, thereby improving the problem of the fourth auxiliary exposed portion WD4 reflecting light and reducing the light emitting interference and light mixing effect.

[0175] In a specific implementation, in the embodiment of the present application, as shown in Figures 5a to 5i to 6d, the second auxiliary sub-overlapping area S12 can be larger than the third auxiliary sub-overlapping area S13. The first auxiliary sub-overlapping area S11 can be larger than the second auxiliary sub-overlapping area S12. The second auxiliary sub-overlapping area S12 can be larger than the third auxiliary sub-overlapping area S13. In this way, the areas of the first auxiliary exposed portion WD1, the second auxiliary exposed portion WD2, and the third auxiliary exposed portion WD3 shielding the touch electrode (e.g., the second touch electrode 820) can be sequentially increased, thereby improving the problem of reduced light interference and light mixing effect due to the first auxiliary exposed portion WD1, the second auxiliary exposed portion WD2, and the third auxiliary exposed portion WD3 reflecting light. Of course, it is also possible for the second auxiliary sub-overlapping area S12 to be approximately equal to the third auxiliary sub-overlapping area S13. For example, the second auxiliary sub-overlapping area S12 is equal to the third auxiliary sub-overlapping area S13, both of which are equal to 0. Alternatively, the fourth auxiliary sub-overlapping area S14 is equal to at least one of the first auxiliary sub-overlapping area S11, the second auxiliary sub-overlapping area S12, and the third auxiliary sub-overlapping area S13. Alternatively, the fourth auxiliary sub-overlapping area S14 is greater than at least one of the first auxiliary sub-overlapping area S11, the second auxiliary sub-overlapping area S12, and the third auxiliary sub-overlapping area S13.

[0176] In a specific implementation, in an embodiment of the present application, as shown in Figures 5a to 5i to 6d, the fourth auxiliary sub-overlapping area S14 can be larger than the first auxiliary sub-overlapping area S11. In this way, the fourth auxiliary exposed portion WD4 of the touch electrode (e.g., the second touch electrode 820) shielding can be larger than the first auxiliary exposed portion WD1, thereby alleviating the problem of the fourth auxiliary exposed portion WD4 reflecting light and reducing the light interference and light mixing effect. Of course, the fourth auxiliary sub-overlapping area S14 can also be approximately equal to the first auxiliary sub-overlapping area S111.

[0177] 5a to 5i to 7f and 10a and 10b, the orthogonal projection of the first capacitor (e.g., the second plate Cst2 of the first capacitor) in the first-color subpixel on the base substrate 1000 and the orthogonal projection of the touch electrode (e.g., the second touch electrode 820) on the base substrate 1000 has a first storage overlapping area SC1. Illustratively, the first storage overlapping area SC1 includes the overlapping area between the orthogonal projection of the storage conductive portion Cst2 in the first-color subpixel on the base substrate 1000 and the orthogonal projection of the touch electrode (e.g., the second touch electrode 820) on the base substrate 1000.

[0178] Illustratively, as shown in Figures 5a-5i-7f and 10a-10b, the grid structure formed by the touch electrodes in at least one subpixel includes at least five interior angles, of which at least two are obtuse and two are acute, such as five to ten interior angles, of which at least two are obtuse and two are acute.

[0179] Optionally, the grid structure formed by the touch electrodes in at least one subpixel has at least four unequal interior angles. For example, in a first-color subpixel, the second touch electrodes 820 form interior angles A1 to A5, where A1 is equal to 90°, A2 and A5 are acute angles with angles between 30° and 80°, and A3 and A4 are successive obtuse angles with angles between 95° and 150°.

[0180] Of course, the above situation is not limiting. For example, optionally, A2 and A5 are equal acute angles, and A3 and A4 are equal obtuse angles. Or, the interior angles forming the grid are all equal, forming, for example, a regular pentagon or hexagon.

[0181] Illustratively, as shown in Figures 5a to 5i to 7f and 10a and 10b, the grid structure formed by the touch electrodes in at least one subpixel includes at least five sides, at least two of which have different lengths. For example, in a first-color subpixel, the second touch electrode 820 forms five sides with interior angles A1 to A5. For example, the lengths of a1 to a5 are unequal.

[0182] For example, as shown in FIGS. 5a to 5i to 7f and 10a and 10b, the structure formed by the touch electrode in at least one subpixel includes at least four sides, at least two of which have unequal widths. Optionally, the width of at least one of the sides of the touch electrode corresponding to one subpixel gradually decreases. For example, the width of an A4 side decreases from the beginning of the A4 corner to the end of the A5 corner. Optionally, at least one of the sides of the touch electrode corresponding to one subpixel includes three portions with unequal widths. For example, as shown in FIG. 9b, one side of the touch electrode includes at least three portions with different widths, where DC1 is larger than DC2, and DC1 is larger than DC4. Here, DC4 has a narrow width, which reduces overlap with the power signal line and reduces the impact on the touch signal.

[0183] Of course, the above situation is not limited to this. For example, the touch electrodes can optionally form a polygonal structure with the same side length or width, such as a regular pentagon or a regular hexagon.

[0184] 5a to 5i to 7f and 10a and 10b, the orthogonal projection of the first capacitor in the second-color subpixel on the base substrate 1000 and the orthogonal projection of the touch electrode (e.g., the second touch electrode 820) on the base substrate 1000 has a second storage overlap area SC2. Illustratively, the second storage overlap area SC2 includes the overlap area between the orthogonal projection of the storage conductive portion Cst2 in the second-color subpixel on the base substrate 1000 and the orthogonal projection of the touch electrode (e.g., the second touch electrode 820) on the base substrate 1000.

[0185] 5a to 5i to 7f and 10a and 10b, the orthogonal projection of the first capacitor in the third-color subpixel on the base substrate 1000 and the orthogonal projection of the touch electrode (e.g., the second touch electrode 820) on the base substrate 1000 has a third storage overlapping area SC3. Illustratively, the third storage overlapping area SC3 includes the overlapping area between the orthogonal projection of the storage conductive portion Cst2 in the third-color subpixel on the base substrate 1000 and the orthogonal projection of the touch electrode (e.g., the second touch electrode 820) on the base substrate 1000.

[0186] 5a to 5i to 7f and 10a and 10b, the orthogonal projection of the first capacitor in the fourth-color subpixel on the base substrate 1000 and the orthogonal projection of the touch electrode (e.g., the second touch electrode 820) on the base substrate 1000 has a fourth storage overlapping area SC4. Illustratively, the fourth storage overlapping area SC4 includes the overlapping area between the orthogonal projection of the storage conductive portion Cst2 in the fourth-color subpixel on the base substrate 1000 and the orthogonal projection of the touch electrode (e.g., the second touch electrode 820) on the base substrate 1000.

[0187] In a specific implementation, in an embodiment of the present application, as shown in Figures 5a to 5i to 7f and 10a and 10b, at least one of the first storage overlap area SC1, the second storage overlap area SC2, and the fourth storage overlap area SC4 is larger than the third storage overlap area SC3. For example, all of the first storage overlap area SC1, the second storage overlap area SC2, and the fourth storage overlap area SC4 may be larger than the third storage overlap area SC3. Alternatively, at least one of the first storage overlap area SC1 and the fourth storage overlap area SC4 may be larger than the second storage overlap area SC2. The second storage overlap area SC2 is equal to the third storage overlap area SC3.

[0188] In a specific implementation, in the embodiment of the present application, as shown in Figures 5a to 5i to 7f and 10a and 10b, the first storage overlap area SC1 may be larger than the second storage overlap area SC2. In this way, the first capacitor in the first color subpixel can be shielded as much as possible by the touch electrode (e.g., the second touch electrode 820).

[0189] In a specific implementation, in an embodiment of the present application, as shown in FIGS. 5a to 5i to 9b, a touch electrode (e.g., a second touch electrode 820) includes a first electrode portion DC1 and a second electrode portion DC2. Here, the orthogonal projection of the first electrode portion DC1 on the base substrate 1000 and the orthogonal projection of the auxiliary conductive portion on the base substrate 1000 have an overlapping area. The orthogonal projection of the second electrode portion DC2 on the base substrate 1000 and the orthogonal projection of the auxiliary conductive portion on the base substrate 1000 do not overlap. Here, the width of the first electrode portion DC1 may be greater than the width of the second electrode portion DC2. In this way, the touch electrode can better shield the auxiliary conductive portion.

[0190] Optionally, as shown in FIGS. 5a to 5i to 9b, the touch electrode (e.g., the second touch electrode 820) includes at least three portions with different widths, and the touch electrode includes a first electrode portion DC1, a second electrode portion DC2, and a third electrode portion DC3 (not shown). For example, the orthogonal projection of the first electrode portion DC1 on the base substrate 1000 and the orthogonal projection of the auxiliary conductive portion on the base substrate 1000 have an overlapping region. The orthogonal projection of the second electrode portion DC2 on the base substrate 1000 and the orthogonal projection of the auxiliary conductive portion on the base substrate 1000 do not overlap. The orthogonal projection of the third electrode portion DC3 on the base substrate 1000 and the orthogonal projection of the storage conductive portion on the base substrate 1000 have an overlapping region. Optionally, the width of the first electrode portion DC1 is smaller than the width of the second electrode portion DC2, and the width of the second electrode portion DC2 is smaller than the width of the third electrode portion DC3.

[0191] Optionally, as shown in Figures 5a to 5i to 9b, the touch electrode has a protrusion in at least one corresponding subpixel region, for example DC1, and the touch electrode has protrusions in at least two corresponding subpixel regions, where the protrusions have different directions or widths.

[0192] 5a to 5i, 6f, and 6g, in an embodiment of the present application, an orthogonal projection of a touch electrode (e.g., second touch electrode 820) located between adjacent opening areas on base substrate 1000 overlaps with an orthogonal projection of at least two different color light-emitting layers on base substrate 1000. Optionally, an orthogonal projection of a touch electrode (e.g., second touch electrode 820) on base substrate 1000 located between adjacent opening areas is covered with an orthogonal projection of at least two different color light-emitting layers on base substrate 1000.

[0193] Illustratively, the orthogonal projection of a touch electrode (e.g., second touch electrode 820) located between adjacent opening areas on base substrate 1000 is covered with the orthogonal projection of two different color light-emitting layers on base substrate 1000. Also, the orthogonal projection of a touch electrode (e.g., second touch electrode 820) located between adjacent opening areas on base substrate 1000 is covered with the orthogonal projection of three different color light-emitting layers on base substrate 1000.

[0194] Illustratively, in the same subpixel, the touch electrode (e.g., 820) and the storage conductive portion WCst2 have an overlapping area (e.g., SC1), and the touch electrode (e.g., 820) is covered with the orthogonal projections of three different color light-emitting layers on the base substrate 1000. The area of ​​the orthogonal projection of the storage conductive portion WCst2 on the base substrate 1000 is Sn, where SC1 / Sn is approximately 1 / 5 to 4 / 5.

[0195] Optionally, in the same subpixel, the ratio of the area of ​​the touch electrode covered by the orthogonal projection of the three different color light-emitting layers on the base substrate 1000 to the area of ​​the orthogonal projection of the corresponding storage conductive portion WCst2 on the base substrate 1000 is approximately 3 / 10 to 2 / 5. For example, the ratio of the area of ​​the touch electrode covered by the orthogonal projection of the three different color light-emitting layers on the base substrate 1000 to the area of ​​the orthogonal projection of the corresponding storage conductive portion WCst2 on the base substrate 1000 is approximately 1 / 5. Alternatively, the ratio of the area of ​​the touch electrode covered by the orthogonal projection of the three different color light-emitting layers on the base substrate 1000 to the area of ​​the orthogonal projection of the corresponding storage conductive portion WCst2 on the base substrate 1000 is approximately 3 / 10. Alternatively, the ratio of the area of ​​the touch electrode covered by the orthogonal projection of the three different color light-emitting layers on the base substrate 1000 to the area of ​​the orthogonal projection of the corresponding storage conductive portion WCst2 on the base substrate 1000 is approximately 2 / 5. Alternatively, the ratio of the area of ​​the touch electrode covered by the orthogonal projection of the three different color light-emitting layers on the base substrate 1000 to the area of ​​the orthogonal projection of the corresponding storage conductive portion WCst2 on the base substrate 1000 is approximately 1 / 2. Of course, in actual applications, this may be designed according to the requirements of the actual application environment and is not limited thereto.

[0196] In a specific implementation, in the embodiment of the present application, as shown in Figures 5a to 5i, 6f, 6g, and 11, the orthogonal projection of the touch electrode (e.g., the second touch electrode 820) on the base substrate 1000 surrounding the opening region KK1 in the first-color subpixel is located within the orthogonal projection of the first-color light-emitting layer 610 on the base substrate 1000. This can increase the area of ​​the first-color light-emitting layer 610 and ensure the light-emitting effect.

[0197] Optionally, at least a portion of the boundary ES1 of the first color light-emitting layer 610 covers the auxiliary conductive portion, thereby further shielding the auxiliary conductive portion.

[0198] In a specific implementation, in the embodiment of the present application, as shown in Figures 5a to 5i, 6f, 6g, and 11, the orthogonal projection of the touch electrode (e.g., second touch electrode 820) on the base substrate 1000 surrounding the opening region KK2 in the second-color subpixel is located within the orthogonal projection of the second-color light-emitting layer 620 on the base substrate 1000. This allows the area of ​​the second-color light-emitting layer 620 to be increased and ensures a good light-emitting effect.

[0199] Optionally, at least a portion of the boundary ES2 of the second color light-emitting layer 620 covers the auxiliary conductive portion, thereby further shielding the auxiliary conductive portion.

[0200] In a specific implementation, in the embodiment of the present application, as shown in Figures 5a to 5i, 6f, 6g, and 11, the orthogonal projection of the touch electrode (e.g., the second touch electrode 820) on the base substrate 1000 surrounding the opening region KK3 in the third-color subpixel is located within the orthogonal projection of the third-color light-emitting layer 630 on the base substrate 1000. This allows the area of ​​the third-color light-emitting layer 630 to be increased and ensures a good light-emitting effect.

[0201] Optionally, at least a portion of the boundary ES3 of the third color light-emitting layer 630 covers the auxiliary conductive portion, thereby further shielding the auxiliary conductive portion.

[0202] In a specific implementation, in the embodiment of the present application, as shown in Figures 5a to 5i, 6f, 6g, and 11, the orthogonal projection of the touch electrode (e.g., the second touch electrode 820) on the base substrate 1000 surrounding the opening region KK4 in the fourth-color subpixel is located within the orthogonal projection of the fourth-color light-emitting layer 640 on the base substrate 1000. This can increase the area of ​​the fourth-color light-emitting layer 640 and ensure the light-emitting effect.

[0203] Optionally, at least a portion of the boundary ES4 of the fourth color light-emitting layer 640 covers the auxiliary conductive portion, thereby further shielding the auxiliary conductive portion.

[0204] In the region where at least two color light-emitting layers overlap, the stacking positions of the light-emitting layers are not limited to those described in this embodiment and can be adjusted according to actual circumstances or process conditions. For example, light-emitting layers of different colors can be fabricated in the same step or in different steps. For example, the stacking positions of the light-emitting layers are not limited to those shown in FIG. 5e. Starting from the pixel-defining layer 950, the stacking order can be 610, 620, 630. Of course, the stacking order can also be 630, 620, 610, or 610, 630, 620, or 630, 610, 620, etc.

[0205] In a specific implementation, in the embodiment of the present application, as shown in Figures 5a to 5i, 6f, 6g, and 11, for adjacent third-color light-emitting layers 630 and second-color light-emitting layers 620, there is a first minimum distance W0S1 between a boundary ES3 of the orthogonal projection of the third-color light-emitting layer 630 on the base substrate 1000 and a boundary CK3 of the orthogonal projection of the touch electrode (e.g., second touch electrode 820) on the base substrate 1000 surrounding the third-color subpixel. There is a second minimum distance W0S2 between a boundary ES2 of the orthogonal projection of the second-color light-emitting layer 620 on the base substrate 1000 and a boundary CK1 of the orthogonal projection of the touch electrode (e.g., second touch electrode 820) on the base substrate 1000 surrounding the second-color subpixel. Here, the first minimum distance W0S1 is greater than the second minimum distance W0S2. In this way, on the one hand, the area of ​​the third-color light-emitting layer 630 can be further increased to ensure a good light-emitting effect. Meanwhile, the auxiliary conductive portion can be further shielded by covering at least a portion of the boundary ES3 of the third-color light-emitting layer 630 with the auxiliary conductive portion. Furthermore, because the light-emitting area of ​​the second-color subpixel is small, if the third-color light-emitting layer 630 extends to the second-color light-emitting layer 620, it will have less impact on the light-emitting effect of the second-color subpixel.

[0206] In a specific implementation, in the embodiment of the present application, as shown in Figures 5a to 5i, 6f, 6g, and 11, the area surrounded by the orthogonal projection of the touch electrode (e.g., second touch electrode 820) on the base substrate 1000 surrounding the opening region KK1 in the first color subpixel is the first grid area WG1. The area surrounded by the orthogonal projection of the touch electrode (e.g., second touch electrode 820) on the base substrate 1000 surrounding the opening region KK2 in the second color subpixel is the second grid area WG2. The area surrounded by the orthogonal projection of the touch electrode (e.g., second touch electrode 820) on the base substrate 1000 surrounding the opening region KK3 in the third color subpixel is the third grid area WG3. Here, the third grid area WG3 is larger than the second grid area WG2 and larger than the first grid area WG1. In this way, the third grid area WG3, the second grid area WG2, and the first grid area WG1 are proportional to the opening area KK3 in the third color subpixel, the opening area KK2 in the second color subpixel, and the opening area KK1 in the first color subpixel, respectively, thereby improving the light transmittance.

[0207] It is understood that the first touch electrodes 810 and / or the second touch electrodes in the embodiments of the present application do not all need to be a closed grid, and touch electrodes corresponding to local areas or individual subpixels may have gaps or be disconnected. For example, in combination with Figures 1-2, 5a to 5i, 6f, and 6g-11, touch electrodes corresponding to the edge of the display area AA near the non-display area, or the non-display area, or individual subpixels may have gaps or be disconnected.

[0208] In a specific implementation, in the embodiment of the present application, as shown in Figures 5a to 5i, 6f, 6g, and 11, the area surrounded by the orthogonal projection of the touch electrode (e.g., second touch electrode 820) on base substrate 1000 surrounding the opening region KK4 of the fourth color subpixel is the fourth grid area WG4. The first grid area WG1 corresponding to the first color subpixel can be larger than the fourth grid area WG4 corresponding to the fourth color subpixel. Alternatively, the first grid area WG1 corresponding to the first color subpixel can be approximately equal to the fourth grid area WG4 corresponding to the fourth color subpixel, but is not limited thereto.

[0209] In a specific implementation, in the embodiment of the present application, the first grid area WG1 is 850 to 920 μm 2 Optionally, the first grid area WG1 can be 860 μm 2 ~910μm 2 For example, the first grid area WG1 can be 850 μm 2 Alternatively, the first grid area WG1 can be 860 μm 2 Alternatively, the first grid area WG1 can be 900 μm 2 Alternatively, the first grid area WG1 can be 910 μm 2 Alternatively, the first grid area WG1 can be 920 μm 2 Of course, in practical applications, the design can be determined according to the requirements of the practical application environment, and the details are not limited here.

[0210] Or, in a specific implementation, in the embodiment of the present application, the first grid area WG1 is 30.5*28.5 μm 2 ~35.5*30.5μm 2 Optionally, the first grid area WG1 can be 30.5*28.5 μm 2 For example, the first grid area WG1 can be 31.5*29.5 μm 2 Or, the first grid area WG1 can be 32.5*29.1 μm 2Of course, in practical applications, the design can be determined according to the requirements of the practical application environment, and the details are not limited here.

[0211] In a specific implementation, in the embodiment of the present application, the second grid area WG2 is 950 to 1050 μm 2 Optionally, the second grid area WG2 can be 960 to 1040 μm 2 For example, the second grid area WG2 can be 950 μm 2 Alternatively, the second grid area WG2 can be 960 μm 2 Alternatively, the second grid area WG2 can be 980 μm 2 Alternatively, the second grid area WG2 can be 1000 μm 2 Alternatively, the second grid area WG2 can be 1040 μm 2 Alternatively, the second grid area WG21050 μm 2 Of course, in actual applications, the design can be determined according to the requirements of the actual application environment, and the details are not limited here.

[0212] Or, in a specific implementation, in the embodiment of the present application, the second grid area WG2 is 30.1*30.1 μm 2 ~32.1*32.1μm 2 Optionally, the second grid area WG2 can be 30.5*30.5 μm 2 ~32.0*32.0μm 2 For example, the second grid area WG2 can be 30.1*30.1 μm 2 Or the second grid area WG2 can be 30.5*30.5 μm 2 Or the second grid area WG2 can be 31.6*31.6 μm 2 Or, the second grid area WG2 can be 32.0*32.0 μm 2 Or the second grid area WG2 can be 32.1*32.1 μm 2Of course, in practical applications, the design can be determined according to the requirements of the practical application environment, and the details are not limited here.

[0213] In a specific implementation, in the embodiment of the present application, the third grid area WG3 is 1100 μm 2 ~1300μm 2 Optionally, the third grid area WG3 can be 1150 μm 2 ~1250μm 2 For example, the third grid area WG3 can be 1100 μm 2 Alternatively, the third grid area WG3 can be 1150 μm 2 Alternatively, the third grid area WG3 can be 1200 μm 2 Alternatively, the third grid area WG3 can be 1225 μm 2 Alternatively, the third grid area WG3 can be 1300 μm 2 Of course, in practical applications, the design can be determined according to the requirements of the practical application environment, and the details are not limited here.

[0214] Or, in a specific implementation, in the embodiment of the present application, the third grid area WG3 is 32*32 μm 2 ~37*37μm 2 Optionally, the third grid area WG3 can be 33*33 μm 2 ~36*36μm 2 For example, the third grid area WG3 can be 32*32 μm 2 Or the third grid area WG3 can be 33*33 μm 2 Or the third grid area WG3 can be 34*34 μm 2. Or, the third grid area WG335*35 μm 2 Or the third grid area WG3 is 36*36μm 2 Or the third grid area WG3 can be 37*37 μm 2Of course, in practical applications, the design can be determined according to the requirements of the practical application environment, and the details are not limited here.

[0215] In a specific implementation, in the embodiment of the present application, the fourth grid area WG4 is 850 to 920 μm 2 Optionally, the fourth grid area WG4 can be 860 μm 2 ~910μm 2 For example, the fourth grid area WG4 can be 850 μm 2 Or, the fourth grid area WG4 can be 860 μm 2 Alternatively, the fourth grid area WG4 can be 900 μm 2 Or, the fourth grid area WG4910 μm 2 Or the fourth grid area WG4 is 920 μm 2 Of course, in practical applications, the design can be determined according to the requirements of the practical application environment, and the details are not limited here.

[0216] Or, in a specific implementation, in the embodiment of the present application, the fourth grid area WG4 is 30.5*28.5 μm 2 ~35.5*30.5μm 2 Optionally, the fourth grid area WG4 can be 30.5*28.5 μm 2 For example, the fourth grid area WG4 can be 31.5*29.5 μm 2 Or the fourth grid area WG4 can be 32.5*29.1 μm 2 Of course, in practical applications, the design can be determined according to the requirements of the practical application environment, and the details are not limited here.

[0217] In a specific implementation, in the embodiment of the present application, as shown in Figures 5a to 5i and 11, in the same overlapping unit, the aperture region KK3 in the third color subpixel and the aperture region KK1 in the first color subpixel may be arranged along the first direction F1. The aperture region KK2 in the second color subpixel and the aperture region KK4 in the fourth color subpixel may also be arranged along the first direction F1. Here, the area surrounded by the inner boundary NS3 of the touch electrode (e.g., the second touch electrode 820) surrounding the aperture region KK3 in the third color subpixel has a first width WK1 perpendicular to the first direction F1. The area surrounded by the inner boundary NS1 of the touch electrode (e.g., the second touch electrode 820) surrounding the aperture region KK1 in the first color subpixel has a second width WK2 perpendicular to the first direction F1. The area enclosed by the inner boundary NS2 of the touch electrode (e.g., the second touch electrode 820) surrounding the aperture region KK2 in the second color subpixel has a third width WK3 perpendicular to the first direction F1. The area enclosed by the inner boundary NS4 of the touch electrode (e.g., the second touch electrode 820) surrounding the aperture region KK4 in the fourth color subpixel has a fourth width WK4 perpendicular to the first direction F1.

[0218] Optionally, the first direction F1 and the row direction F3 may form a specific angle, for example, the angle may be greater than 0 degrees and less than 90 degrees. Optionally, the first direction F1 and the row direction F3 may form an angle between 25 degrees and 75 degrees. Optionally, the first direction F1 and the row direction F3 may form an angle between 30 degrees and 60 degrees. For example, the first direction F1 and the row direction F3 may form an angle of 25 degrees. Alternatively, the first direction F1 and the row direction F3 may form an angle of 30 degrees. Alternatively, the first direction F1 and the row direction F3 may form an angle of 45 degrees. Alternatively, the first direction F1 and the row direction F3 may form an angle of 60 degrees. Alternatively, the first direction F1 and the row direction F3 may form an angle of 75 degrees. Of course, in actual applications, the design may be determined according to the requirements of the actual application environment, and the present invention is not limited thereto.

[0219] Specifically, in one embodiment of the present application, the first width WK1 may be 34.0 μm to 35.0 μm. Optionally, the first width WK1 may be 34.1 μm to 34.9 μm. For example, the first width WK1 may be 34.0 μm. Alternatively, the first width WK1 may be 34.1 μm. Alternatively, the first width WK1 may be 34.4 μm. Alternatively, the first width WK1 may be 34.8 μm. Alternatively, the first width WK1 may be 34.9 μm. Alternatively, the first width WK1 may be 35.0 μm. Of course, in actual applications, the design can be determined according to the requirements of the actual application environment, and the present invention is not limited thereto.

[0220] Specifically, in one embodiment of the present application, the second width WK2 may be 30.5 μm to 31.5 μm. Optionally, the second width WK2 may be 30.7 μm to 31.4 μm. For example, the second width WK2 may be 30.5 μm. Alternatively, the second width WK2 may be 30.7 μm. Alternatively, the second width WK2 may be 31.2 μm. Alternatively, the second width WK2 may be 31.4 μm. Alternatively, the second width WK2 may be 31.5 μm. Of course, in actual applications, the design can be determined according to the requirements of the actual application environment, and the present invention is not limited thereto.

[0221] Specifically, in one embodiment of the present application, the third width WK3 may be 30.8 μm to 32.5 μm. Optionally, the third width WK3 may be 31.0 μm to 32.0 μm. For example, the third width WK3 may be 30.8 μm. Alternatively, the third width WK3 may be 31.0 μm. Alternatively, the third width WK3 may be 31.6 μm. Alternatively, the third width WK3 may be 31.8 μm. Alternatively, the third width WK3 may be 32.0 μm. Alternatively, the third width WK3 may be 32.5 μm. Of course, in actual applications, the design can be determined according to the requirements of the actual application environment, and the present invention is not limited thereto.

[0222] In a specific embodiment, in the embodiment of the present application, the fourth width WK4 may be 28.8 to 31.5 μm. Optionally, the fourth width WK4 may be 29.2 to 30.5 μm. For example, the fourth width WK4 may be 28.8 μm. Alternatively, the fourth width WK4 may be 29.2 μm. Alternatively, the fourth width WK4 may be 29.9 μm. Alternatively, the fourth width WK4 may be 30.5 μm. Alternatively, the fourth width WK4 may be 31.5 μm. Of course, in actual applications, the design can be determined according to the requirements of the actual application environment, and is not limited thereto.

[0223] For example, as shown in FIG. 11 , the first width WK1 may be larger than the second width WK2. This ensures that the aperture region KK3 in the third color subpixel and the aperture region KK1 in the first color subpixel are provided, thereby improving light transmittance. For example, the difference between the first width WK1 and the second width WK2 may be 3.0 μm to 4.0 μm. Optionally, the difference between the first width WK1 and the second width WK2 may be 3.1 μm to 3.9 μm. For example, the difference between the first width WK1 and the second width WK2 may be 3.0 μm. Alternatively, the difference between the first width WK1 and the second width WK2 may be 3.3 μm. Alternatively, the difference between the first width WK1 and the second width WK2 may be 3.6 μm. Alternatively, the difference between the first width WK1 and the second width WK2 may be 3.8 μm. Alternatively, the difference between the first width WK1 and the second width WK2 may be 3.9 μm. Alternatively, the difference between the first width WK1 and the second width WK2 may be 4.0 μm. Of course, in actual applications, the design can be determined according to the requirements of the actual application environment, and the present invention is not limited to this.

[0224] For example, as shown in FIG. 11 , the third width WK3 may be greater than the fourth width WK4. This allows the opening region KK2 in the second color subpixel and the opening region KK4 in the fourth color subpixel to be secured, thereby improving light transmittance. For example, the difference between the third width WK3 and the fourth width WK4 may be 1.0 μm to 2.0 μm. Optionally, the difference between the third width WK3 and the fourth width WK4 may be 1.2 μm to 1.8 μm. For example, the difference between the third width WK3 and the fourth width WK4 may be 1.0 μm. Alternatively, the difference between the third width WK3 and the fourth width WK4 may be 1.2 μm. Alternatively, the difference between the third width WK3 and the fourth width WK4 may be 1.5 μm. Alternatively, the difference between the third width WK3 and the fourth width WK4 may be 1.7 μm. Alternatively, the difference between the third width WK3 and the fourth width WK4 may be 1.8 μm. Alternatively, the difference between the third width WK3 and the fourth width WK4 may be 2.0 μm. Of course, in actual applications, the design can be determined according to the requirements of the actual application environment, and the present invention is not limited to this.

[0225] Specifically, in an embodiment of the present application, as shown in FIGS. 5a to 5i and 12, the angle formed by the extension direction F0 of the grid line of the touch electrode (e.g., the second touch electrode 820) having an overlap area with the orthogonal projection of the auxiliary conductive portion and the third direction is angle β, which is 15°≦β≦60°. Optionally, the angle β is 20°≦β≦50°. The third direction is approximately perpendicular to the extension direction of the data line pattern, for example, the row direction F4. Exemplarily, tan β=A1 / A2, where A1 represents the width of the auxiliary conductive portion in the third direction perpendicular to the third direction, and A2 represents the width of the auxiliary conductive portion in the third direction. For example, β=15°, β=25°, β=35°, β=45°, β=50°, β=60°, etc. Of course, in practical applications, the specific value of β can be determined according to the requirements of practical applications and is not limited thereto.

[0226] In a specific implementation, in an embodiment of the present application, as shown in FIGS. 5A to 5I and 12 , a first angle formed between the extension direction of the grid lines of a touch electrode (e.g., second touch electrode 820) having an overlapping area with the orthogonal projection of the auxiliary conductive portion in a first color subpixel and the third direction is β1. A second angle formed between the extension direction of the grid lines of a touch electrode (e.g., second touch electrode 820) having an overlapping area with the orthogonal projection of the auxiliary conductive portion in a second color subpixel and the third direction is β2. A third angle formed between the extension direction of the grid lines of a touch electrode (e.g., second touch electrode 820) having an overlapping area with the orthogonal projection of the auxiliary conductive portion in a third color subpixel and the third direction is β3. Here, the first angle and the second angle can be smaller than the third angle so that the touch electrode (e.g., second touch electrode 820) can cover as much of the auxiliary conductive layer as possible. Of course, depending on the actual situation, at least two of the angles β1, β2, and β3 may be the same.

[0227] In a specific implementation, in an embodiment of the present application, as shown in Figures 5a to 5i, 9a, and 10a, the aperture regions of four adjacent subpixels are defined as an aperture group, and the orthogonal projection of the grid intersection of the touch electrode (e.g., the second touch electrode 820) on the base substrate 1000 is located in the area surrounded by the orthogonal projection of the aperture group on the base substrate 1000. In addition, the orthogonal projection of the grid intersection of the touch electrode (e.g., the second touch electrode 820) on the base substrate 1000 is located approximately in the center of the area surrounded by the orthogonal projection of the aperture group on the base substrate 1000. This allows the grid intersections to be uniformly distributed within the display area, further improving the display uniformity.

[0228] 13a and 13b, in an embodiment of the present application, the overlapping area between the orthogonal projection of the first electrode 510 (e.g., an anode) in a first-color subpixel on the base substrate 1000 and the orthogonal projection of the touch electrode (e.g., the overlapping area of ​​the second touch electrode 820) on the base substrate 1000 has a first anode overlapping area BS1. The overlapping area between the orthogonal projection of the first electrode 520 in a second-color subpixel on the base substrate 1000 and the orthogonal projection of the touch electrode (e.g., the second touch electrode 820) on the base substrate 1000 has a second anode overlapping area BS2. The overlapping area between the orthogonal projection of the first electrode 530 in a third-color subpixel on the base substrate 1000 and the orthogonal projection of the touch electrode (e.g., the second touch electrode 820) on the base substrate 1000 has a third anode overlapping area BS3. The overlap region between the orthogonal projection of the first electrode 540 in the fourth color subpixel on the base substrate 1000 and the orthogonal projection of the touch electrode (e.g., the second touch electrode 820) on the base substrate 1000 has a fourth anode overlap area BS4, where at least one of the first anode overlap area BS1, the second anode overlap area BS2, and the fourth anode overlap area BS4 is larger than the third anode overlap area BS3.

[0229] Exemplarily, the first anode overlapping area BS1 is larger than the third anode overlapping area BS3, the second anode overlapping area BS2 is larger than the third anode overlapping area BS3, and the fourth anode overlapping area BS4 is larger than the third anode overlapping area BS3.

[0230] In a specific implementation, in the embodiment of the present application, the first anode overlapping area BS1 can be larger than the second anode overlapping area BS2, as shown in Figures 13a and 13b, or the first anode overlapping area BS1 can be approximately the same as the second anode overlapping area BS2.

[0231] In a specific implementation, in the embodiment of the present application, as shown in Figures 13a and 13b, the first anode overlapping area BS1 can be larger than the fourth anode overlapping area BS4, or the first anode overlapping area BS1 can be approximately the same as the fourth anode overlapping area BS4.

[0232] In a specific implementation, in the embodiment of the present application, the fourth anode overlapping area BS4 can be larger than the second anode overlapping area BS2, as shown in Figures 13a and 13b, or the fourth anode overlapping area BS4 can be approximately the same as the second anode overlapping area BS2.

[0233] Optionally, the first anode overlap area BS1 is 2.5 μm 2 -35μm 2 Optionally, the first anode overlap area BS1 is 3 μm 2 -25μm 2 Or, the first anode overlap area BS1 is 6 μm 2 -20μm 2 Optionally, a second anode overlap area BS of 20 μm 2 -30μm 2 Optionally, the second anode overlap area BS2 is 1.5 μm 2 -25μm 2 Or, the second anode overlap area BS2 is 6 μm 2 -20μm 2 is.

[0234] Optionally, the third anode overlap area BS3 is 0 μm 2 -25μm 2 Optionally, the third anode overlap area BS3 is 1.5 μm 2 -25μm 2 Or, the third anode overlap area BS3 is 5 μm 2 -20μm 2 is.

[0235] Optionally, the fourth anode overlap area BS4 is 0 μm 2 -30μm 2 Optionally, the fourth anode overlap area BS4 is 1.5 μm 2 -25μm 2 Or, the first anode overlap area BS4 is 6 μm 2 -20μm 2 is.

[0236] In a specific implementation, in an embodiment of the present application, as shown in FIGS. 14a and 14b in conjunction with FIGS. 8a to 8d, an auxiliary insulating layer may be further provided on the second touch electrode 820 side away from the base substrate 1000. An auxiliary electrode 840 may also be provided on the auxiliary insulating layer side away from the base substrate 1000. Illustratively, the auxiliary electrode 840 is in a floating state and does not transmit a signal. Of course, the auxiliary electrode 840 may be made of the same layer and / or the same material as the first touch electrode 810.

[0237] As shown in Figures 14a and 14b and 8a to 8d, it can be seen that an insulating layer 830 is provided on the side of the first touch electrode 810 remote from the base substrate 1000. An auxiliary electrode 840 is also provided on the side of 830 remote from the base substrate 1000. The auxiliary electrode 840 is floating and does not transmit signals. The auxiliary electrode 840 can be formed in the same layer and / or made of the same material as the second touch electrode 820 (or 811).

[0238] In a specific implementation, in an embodiment of the present application, as shown in FIG. 15 , the display panel further includes a power input line VDDIN located in the non-display area. The power signal line patterns VDD in the subpixels are electrically connected to the power input line VDDIN. Exemplarily, the power signal line patterns VDD of two adjacent columns of subpixels are electrically connected via the power input line VDDIN, or the power signal line patterns VDD corresponding to two adjacent columns of subpixels of the same color are electrically connected via the power input line VDDIN. Exemplarily, the power input line VDDIN is provided on the same layer as the power signal line pattern VDD. Alternatively, the power input line VDDIN and the power signal line pattern VDD can be arranged on different layers, so the power signal line pattern VDD and the power input line VDDIN need to be electrically connected via via holes. Also, the data line pattern DA and the power input line VDDIN do not need to be provided on the same conductive layer.

[0239] It should be understood that the above embodiments can be combined as appropriate, and that the ranges of the respective values ​​can be adjusted as appropriate.

[0240] The embodiments of the present application further provide a display device including the above-mentioned display panel provided by the embodiments of the present application, for example, an organic light emitting diode (OLED). The principle of solving the problem of the display device is similar to that of the above-mentioned display panel, so the implementation of the display device can refer to the implementation of the above-mentioned display panel, and the details will not be repeated here.

[0241] In specific implementations, in the embodiments of the present application, the display device is a mobile phone, a tablet computer, a television, a monitor, a laptop, a digital photo frame, a navigation system, a watch, a bracelet, etc. Other essential components of the display device are components that should be understood by those skilled in the art, and will not be repeated here and should not be used as limitations on the present application.

[0242] Although the preferred embodiments of the present application have been described, those skilled in the art can make additional changes and modifications to these embodiments after learning the basic creative concept. Therefore, it is intended that the appended claims be interpreted to include all changes and modifications that fall within the scope of the preferred embodiments and the present application.

[0243] Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present application without departing from the spirit and scope of the embodiments of the present application. Thus, if these changes and modifications of the embodiments of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application also intends to include these changes and modifications.

Claims

1. a base substrate, a transistor array layer, a pixel definition layer, and a touch electrode; the transistor array layer is located on the base substrate; the pixel-defining layer is located on a side of the transistor array layer away from the base substrate; the touch electrode is located on a side of the pixel defining layer away from the base substrate; the base substrate has a display area, the display area includes a plurality of sub-pixels, each sub-pixel includes a pixel circuit and a light-emitting element, the pixel circuit includes a gate line pattern, a data line pattern, and a power signal line pattern; the transistor array layer includes a plurality of capacitor conductive portions, and the sub-pixels include corresponding capacitor conductive portions, wherein in the same sub-pixel, the capacitor conductive portion and the data line pattern corresponding to the sub-pixel and / or the power signal line pattern corresponding to the sub-pixel have an overlapping region, and the capacitor conductive portion is coupled to at least the power signal line pattern corresponding to the sub-pixel or the data line pattern corresponding to the sub-pixel; the pixel defining layer includes a plurality of aperture regions, the sub-pixels including corresponding aperture regions; an orthogonal projection of at least a portion of the touch electrodes on the base substrate is a grid; the transistor array layer further includes a first conductive layer, and the capacitor conductive portion is formed in the first conductive layer; The pixel circuit further includes a plurality of transistors, and sources and drains of at least some of the transistors are formed on the first conductive layer.

2. The display panel according to claim 1 , wherein the capacitor conductive portion has an arc-shaped or irregular pattern.

3. The display panel according to claim 1 , wherein the capacitor conductive portion includes an auxiliary conductive portion, and the auxiliary conductive portion at least partially overlaps the power signal line pattern, the data line pattern, and the touch electrode.

4. 2. The display panel according to claim 1, wherein the power supply signal line patterns of the subpixels in two adjacent columns are electrically coupled via a power supply input line, or the power supply signal line patterns corresponding to the subpixels in two adjacent columns of the same color are electrically coupled via a power supply input line.

5. 5. The display panel according to claim 4, wherein the power input line and the power signal line pattern are arranged on different layers.

6. 2. The display panel according to claim 1, wherein the width of the power supply signal line pattern is larger than the width of the data line pattern.

7. 5. The display panel according to claim 4, wherein the data line pattern is not disposed on the same conductive layer as the power signal line pattern, or the data line pattern and the power input line are not disposed on the same conductive layer.

8. 2. The display panel according to claim 1, wherein the first conductive layer includes a first sub-conductive layer and a second sub-conductive layer stacked together, and a first sub-insulating layer is provided between the first sub-conductive layer and the second sub-conductive layer.

9. 2. The display panel according to claim 1, wherein an overlapping area between the capacitor conductive portion and the power supply signal line pattern is larger than an overlapping area between the capacitor conductive portion and the data line pattern.

10. 2. The display panel of claim 1, wherein the pixel circuit includes a seventh transistor and a second transistor, a gate of the seventh transistor is coupled to a second reset signal line pattern, and a gate of the second transistor is coupled to a first reset signal line pattern, and the reset signal line pattern and the second reset signal line pattern transmit different signals.

11. 2. The display panel of claim 1, wherein the pixel circuit includes a data writing transistor and a first transistor, and the gate line pattern coupled to the gate of the data writing transistor and the gate line pattern coupled to the gate of the first transistor transmit different timing signals.

12. A display device comprising the display panel according to any one of claims 1 to 11.

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