Display device

Abstract

To provide a display device in which the decrease in display quality due to charge redistribution of a holding capacitor at gate-off time can be suppressed.SOLUTION: A display device includes a plurality of first pixels arranged in a first direction, a plurality of second pixels arranged in the first direction adjacent to the first pixels in a second direction that intersects with the first direction, a first gate line connected to a gate of a pixel transistor of the first pixel, a second gate line connected to a gate of a pixel transistor of the second pixel, a driving circuit that drives the pixel transistor of the first pixel through the first gate line and drives the pixel transistor of the second pixel through the second gate line, and a display region in which the first gate line, the pixel transistor of the first pixel, the second gate line, and the pixel transistor of the second pixel are arranged in this order in the second direction. The driving circuit is controlled to turn on the pixel transistor of the first pixel and the pixel transistor of the second pixel at the same time and then, controlled to turn off the pixel transistor of the second pixel and the pixel transistor of the first pixel in this order.SELECTED DRAWING: Figure 9

Description

[Technical Field]

[0001] The present invention relates to a display device. [Background technology]

[0002] In recent years, there has been a demand for even higher resolution display panels in configurations where displayed images are enlarged using lenses, such as virtual reality (VR), augmented reality (AR), and mixed reality (MR). Conventionally, a display device capable of simultaneously driving multiple sets of adjacent gate lines has been disclosed as a configuration for achieving a high frame rate with such a high-resolution panel (for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2010-271366 Summary of the Invention [Problem to be solved by the invention]

[0004] In display devices, in addition to the storage capacitance formed between the pixel electrode and the common electrode, parasitic capacitance occurs between the pixel electrode and other conductive members. This causes a drop in the pixel electrode potential due to charge redistribution of the storage capacitance when the gate is off, which impairs the accuracy of the displayed image. In particular, as the resolution of displays increases, the storage capacitance decreases, and the influence of the gate-source parasitic capacitance of the pixel transistor increases relatively.

[0005] For example, in the configuration of the above-mentioned conventional technology, in a pixel adjacent to both of the simultaneously driven gate lines, the parasitic capacitance generated between each of the two adjacent gate lines affects the pixel electrode potential, and in a pixel adjacent to one of the simultaneously driven gate lines, the parasitic capacitance generated between the pixel adjacent to the one adjacent gate line affects the pixel electrode potential. As a result, a potential difference occurs between the pixel electrode potential provided between the two simultaneously driven gate lines and the pixel electrode potential between the pixel adjacent to both of the simultaneously driven gate lines and the pixel adjacent to one of the simultaneously driven gate lines, which may result in a deterioration of display quality.

[0006] An object of the present invention is to provide a display device that can suppress a deterioration in display quality caused by charge redistribution in a storage capacitor when the gate is turned off. [Means for solving the problem]

[0007] a first gate line connected to a gate of a pixel transistor of the first pixel; a second gate line connected to a gate of a pixel transistor of the second pixel; a drive circuit that drives the pixel transistor of the first pixel via the first gate line and drives the pixel transistor of the second pixel via the second gate line; and a display area in which the first gate line, the pixel transistor of the first pixel, the second gate line, and the pixel transistor of the second pixel are arranged in this order in the second direction, and the drive circuit simultaneously turns on the pixel transistor of the first pixel and the pixel transistor of the second pixel, and then turns off the pixel transistor of the second pixel and the pixel transistor of the first pixel, in that order.

[0008] A display device according to one aspect of the present disclosure includes a plurality of first pixels arranged in a first direction, a plurality of second pixels arranged in the first direction and adjacent to each of the first pixels in a second direction intersecting the first direction, a plurality of third pixels arranged in the first direction and adjacent to each of the second pixels in the second direction, a first gate line connected to a gate of a pixel transistor of the first pixels, a second gate line connected to a gate of a pixel transistor of the second pixels, and a third gate line connected to a gate of a pixel transistor of the third pixels, and drives the pixel transistor of the first pixel via the first gate line and the pixel transistor of the second pixel via the second gate line. a display area in which the first gate line, the pixel transistor of the first pixel, the second gate line, the pixel transistor of the second pixel, the third gate line, and the pixel transistor of the third pixel are arranged in this order in the second direction, and the drive circuit simultaneously turns on the pixel transistor of the first pixel, the pixel transistor of the second pixel, and the pixel transistor of the third pixel, and then turns off the pixel transistor of the third pixel, the pixel transistor of the second pixel, and the pixel transistor of the first pixel, in that order. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a diagram showing an example of a schematic configuration of a display device according to an embodiment. [Figure 2] FIG. 2 is a diagram showing an example of a pixel arrangement in a display area. [Figure 3] FIG. 3 is a cross-sectional view showing a schematic cross-sectional structure of the display device. [Figure 4] FIG. 4 is a block diagram showing an example of the configuration of a gate driver. [Figure 5] FIG. 5 is a circuit diagram showing an example of a circuit configuration of a shift register circuit. [Figure 6] FIG. 6 is a circuit diagram showing an example of the circuit configuration of the gate line driving circuit. [Figure 7]FIG. 7 is a timing chart showing a first example of gate line driving according to the first comparative example. [Figure 8] FIG. 8 is a timing chart showing a second example of gate line driving according to the first comparative example. [Figure 9] FIG. 9 is a timing chart showing an example of gate line driving according to the first embodiment. [Figure 10] FIG. 10 is a timing chart showing a third example of gate line driving according to the first comparative example. [Figure 11] FIG. 11 is a timing chart showing an example of gate line driving according to a modification of the first embodiment. [Figure 12] FIG. 12 is a timing chart showing a first example of gate line driving according to the second comparative example. [Figure 13] FIG. 13 is a timing chart showing a second example of gate line driving according to the second comparative example. [Figure 14] FIG. 14 is a timing chart showing an example of gate line driving according to the second embodiment. [Figure 15] FIG. 15 is a timing chart showing a third example of gate line driving according to the second comparative example. [Figure 16] FIG. 16 is a timing chart showing an example of gate line driving according to a modification of the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] Modes for carrying out the invention (embodiments) will be described in detail with reference to the drawings. The present invention is not limited to the contents described in the following embodiments. Furthermore, the components described below include those that can be easily imagined by a person skilled in the art and those that are substantially identical. Furthermore, the components described below can be combined as appropriate. Note that the disclosure is merely an example, and any appropriate modifications that a person skilled in the art can easily conceive while maintaining the gist of the invention are naturally included within the scope of the present invention. Furthermore, for clarity of explanation, the drawings may show the width, thickness, shape, etc. of each part schematically compared to the actual embodiment. However, these are merely examples and are not intended to limit the interpretation of the present invention. Furthermore, in this specification and each figure, elements similar to those previously described with reference to the preceding figures are designated by the same reference numerals, and detailed descriptions may be omitted as appropriate.

[0011] Fig. 1 is a diagram showing an example of a schematic configuration of a display device according to an embodiment, Fig. 2 is a diagram showing an example of a pixel arrangement in a display region.

[0012] The display device 1 according to this embodiment is, for example, a liquid crystal display device using a liquid crystal display element as a display element. In addition, in the present disclosure, the display device 1 can employ, for example, a column inversion driving method or a frame inversion method as a driving method. The driving method of the display device 1 is not limited to the column inversion driving method or the frame inversion method.

[0013] The display device 1 has a display area AA provided on a display panel 11, and a drive circuit 40 provided in the peripheral area of ​​the display area AA. The display device 1 is supplied with power from a power supply device 12.

[0014] The drive circuit 40 includes a gate driver 42, a signal line selection circuit 43, and a display control circuit 44. The gate driver 42 and the signal line selection circuit 43 are thin film transistor (TFT) circuits formed in the peripheral region of the display area AA. The display control circuit 44 is included in a driver IC 4 mounted in the peripheral region of the display area AA. The driver IC 4 is connected to the control device 13 via a relay board formed, for example, by a flexible printed circuit (FPC) or the like.

[0015] The control device 13 controls the power supply from the power supply device 12 to the display device 1. The control device 13 also controls power-on and power-off of the display device 1. The power supply device 12 and the control device 13 are mounted, for example, in a device (not shown) in which the display device 1 is mounted.

[0016] The display area AA is provided with a plurality of pixels Pix aligned in the Dx direction (first direction) and the Dy direction (second direction). The display area AA is also provided with gate lines SCL that supply gate signals GATE to the pixels Pix, signal lines DTL that supply pixel signals SIG to the pixels Pix, and a common electrode COML that supplies a common potential VCOM to the pixels Pix. In this embodiment, the gate lines SCL extend in the Dx direction. In this embodiment, the signal lines DTL extend in the Dy direction.

[0017] As shown in Fig. 2, each pixel Pix includes a pixel transistor Tr and a pixel electrode PX. The pixel transistor Tr is configured by a thin film transistor (TFT), for example, an n-channel MOS (Metal Oxide Semiconductor) TFT (hereinafter also referred to as "n-type TFT"). The source of the pixel transistor Tr is connected to a signal line DTL, the gate is connected to a gate line SCL, and the drain is connected to the pixel electrode PX. A storage capacitor Cs is formed between the pixel electrode PX and a common electrode COML.

[0018] A gate signal GATE is supplied to the gates of the pixel transistors Tr of the pixels Pix aligned in the Dx direction (first direction) via a gate line SCL, and a pixel signal SIG is supplied to the sources of the pixel transistors Tr of the pixels Pix aligned in the Dy direction (second direction) via a signal line DTL.

[0019] In FIG. 2, the total number of pixels Pix arranged in the Dx direction (first direction) is M, and the total number of pixels Pix arranged in the Dy direction (second direction) is N. A gate signal GATE is applied to the gate of the pixel transistor Tr of the n-th pixel Pix (n is a natural number from 1 to N) arranged in the Dy direction (second direction). <n>is supplied to the gate of the pixel transistor Tr of the pixel Pix arranged at the (n+1)th position in the Dy direction (second direction), and a gate signal GATE<n+1> is supplied to the gate of the pixel transistor Tr of the pixel Pix arranged at the (n+2)th position in the Dy direction (second direction), and a gate signal GATE<n+2> is supplied to the gate of the pixel transistor Tr of the pixel Pix arranged at the (n+3)th position in the Dy direction (second direction), and a gate signal GATE<n+3> is supplied.

[0020] In addition, a pixel signal SIG is applied to the source of the pixel transistor Tr of the pixel Pix arranged at the m-th position (m is a natural number from 1 to M) in the Dx direction (first direction). <m>is supplied.

[0021] In the present disclosure, the pixel Pix includes, for example, a red pixel for displaying red (R), a green pixel for displaying green (G), and a blue pixel for displaying blue (B). Alternatively, the pixel Pix may further include a white pixel for displaying white (W). An example of the pixel arrangement is a stripe arrangement in which RGB (W) pixels are arranged in the Dx direction (first direction), but in the present disclosure, the pixel arrangement is not limited to an RGB (W) stripe arrangement as long as the display colors of the pixels arranged in the Dy direction (second direction) are the same.

[0022] The power supply device 12 generates a negative first potential VGL and a positive second potential VGH and supplies them to the display device 1. The first potential VGL is, for example, −8 V. The second potential VGH is, for example, +8 V. The first potential VGL and the second potential VGH are supplied to the gate driver 42. Note that the first potential VGL supplied to the gate driver 42 is not limited to −8 V. Also, the second potential VGH supplied to the gate driver 42 is not limited to +8 V.

[0023] The power supply device 12 also generates a negative third potential VL and a positive fourth potential VH and supplies them to the display device 1. The third potential VL is, for example, −5 V. The fourth potential VH is, for example, +5 V. The third potential VL and the fourth potential VH are supplied to the driver IC4. Note that the third potential VL supplied to the driver IC4 is not limited to −5 V. Note that the fourth potential VH supplied to the driver IC4 is not limited to +5 V.

[0024] The control device 13 transmits to the display device 1 a video signal Source, which is the original signal of the video to be displayed on the display device 1.

[0025] The control device 13 includes, for example, a central processing unit (CPU) and storage devices such as memory. The control device 13 executes a program using these hardware resources such as the CPU and storage devices, thereby realizing the display function of the display device 1. Depending on the execution result of the program, the control device 13 controls the driver IC 4 to treat the image to be displayed on the display device 1 as image input gradation information.

[0026] The display control circuit 44 controls the display operation in the display area AA by controlling the gate driver 42 and the signal line selection circuit 43. The display control circuit 44 receives a video signal Source and various control signals from the control device 13. The display control circuit 44 also converts the video signal Source from the control device 13 into an image signal Vsig and outputs it. The image signal Vsig is, for example, a signal obtained by time-division multiplexing pixel signals Sig corresponding to an RGB (W) pixel arrangement. The display control circuit 44 also supplies a common potential VCOM to the common electrode COML.

[0027] The display control circuit 44 also functions as an interface (I / F) between the signal line selection circuit 43 and the control device 13 and as a timing generator. The driver IC 4 including the display control circuit 44 may be mounted on a relay board connected to the display panel 11, rather than being mounted on the display panel 11. The gate driver 42 and the signal line selection circuit 43 may also be included in the driver IC 4.

[0028] Next, a schematic structure of the display device 1 according to the embodiment will be described below. Fig. 3 is a cross-sectional view showing a schematic cross-sectional structure of the display device.

[0029] The array substrate 2 includes a first substrate 21 made of glass or transparent resin, a plurality of pixel electrodes PX, a common electrode COML, and an insulating layer 24 that insulates the pixel electrodes PX from the common electrode COML. The plurality of pixel electrodes PX are arranged, for example, in a matrix above the first substrate 21. The common electrode COML is provided between the first substrate 21 and the pixel electrodes PX.

[0030] A pixel electrode PX is provided corresponding to each pixel Pix. A pixel signal SIG for display operation is supplied to the pixel electrode PX from a signal line selection circuit 43 via a signal line DTL and a pixel transistor Tr. During display operation, a common potential VCOM for display, which is a voltage signal, is supplied from a driver IC 4 to the common electrode COML. The common potential VCOM is preferably a potential different from the GND potential, for example, approximately −0.08 V. The set value of the common potential VCOM is set to an optimal value that does not cause flicker in driving methods such as a column inversion driving method or a frame inversion driving method. The common potential VCOM is preferably a fixed potential, but may also be configured to have a waveform consisting of an AC rectangular wave.

[0031] The pixel electrodes PX and the common electrode COML are made of a light-transmitting conductive material such as ITO (Indium Tin Oxide). A polarizing plate 35B is provided on the lower side of the first substrate 21 via an adhesive layer (not shown).

[0032] The counter substrate 3 includes a second substrate 31 made of glass or transparent resin, and a color filter 32 and a light-shielding layer (not shown) formed on one surface of the second substrate 31. A polarizing plate 35A is provided on the upper side of the second substrate 31 via an adhesive layer (not shown).

[0033] The array substrate 2 and the counter substrate 3 are disposed opposite each other with a predetermined gap (cell gap) between them. A liquid crystal layer 6 is provided as a display function layer in the space between the first substrate 21 and the second substrate 31. The liquid crystal layer 6 modulates light passing through the liquid crystal layer 6 by changing the alignment state of the liquid crystal molecules for each pixel Pix according to the state of the electric field between each pixel electrode PX and the common electrode COML. In this embodiment, for example, a liquid crystal suitable for a lateral electric field mode such as IPS (in-plane switching) including FFS (fringe field switching) is used.

[0034] The array substrate 2 includes wiring such as pixel transistors Tr of each pixel Pix, gate lines SCL that supply gate signals GATE that drive each pixel transistor Tr, and signal lines DTL that supply pixel signals SIG to each pixel electrode PX. The gate lines SCL extend in the Dx direction (first direction) on a plane parallel to the surface of the first substrate 21. The signal lines DTL extend in the Dy direction (second direction) on a plane parallel to the surface of the first substrate 21.

[0035] 4 is a block diagram showing an example of the configuration of a gate driver 42. As shown in FIG. 4, the gate driver 42 includes a shift register circuit 421 and a gate line driving circuit 422.

[0036] The gate line driving circuit 422 is a circuit that generates a scanning signal GATE to be supplied to the gate of the pixel transistor Tr based on the output signal SRout output from the shift register circuit 421 and the enable signal ENB output from the display control circuit 44. The gate line driving circuit 422 includes gate line driving circuits 422_1, . . . , 422_p, . . . , 422_P. The shift register circuit 421 includes shift register circuits 421_1, . . . , 421_p, . . . , 421_P.

[0037] In the configuration example shown in FIG. 4, the total number P of gate line driving circuits 422 corresponds to 1 / 4 of the total number N of pixels Pix aligned in the Dy direction (second direction) (P×4=N). Gate line driving circuits 422_p (p is a natural number from 1 to P) are circuits that drive four gate lines SCL aligned consecutively in the Dy direction (second direction). Specifically, the gate line driving circuit 422_1 drives the gate signal GATE <1> ,GATE <2> ,GATE <3> ,GATE <4> The gate line driving circuit 422_p supplies the gate signal GATE <n>,GATE<n+1> ,GATE<n+2> ,GATE<n+3> The gate line driving circuit 422_P supplies the gate signal GATE <n-3>,GATE <n-2>,GATE <n-1>,GATE <n>The number of gate lines SCL to which the gate line driving circuit 422_p supplies the gate signal GATE is not limited to four. When the gate line driving circuit 422_p supplies the gate signal GATE to Q gate lines SCL, the total number P of the gate line driving circuits 422 corresponds to 1 / Q of the total number N of pixels Pix arranged in the Dy direction (second direction) (P×Q=N).

[0038] 4, the shift register circuits 421_1, . . . , 421_p, . . . , 421_P are provided corresponding to the gate line driving circuits 422_1, . . . , 422_p, . . . , 422_P, respectively. Specifically, the output signal SRout(1) of the shift register circuit 421_1 is supplied to the gate line driving circuit 422_1, the output signal SRout(p) of the shift register circuit 421_p is supplied to the gate line driving circuit 422_p, and the output signal SRout(P) of the shift register circuit 421_P is supplied to the gate line driving circuit 422_P.

[0039] 5 is a circuit diagram showing an example of the circuit configuration of the shift register circuit 421. The shift register circuit 421 receives a start pulse signal STV and a shift clock signal CKV from the display control circuit 44.

[0040] The start pulse signal STV and the shift clock signal CKV are binary logic signals of high potential and low potential.

[0041] The start pulse signal STV is a signal that defines one frame period 1F of the display device 1. Specifically, one frame period 1F of the display device 1 according to the embodiment is defined starting from the rising edge of the start pulse signal STV. In other words, one frame period 1F is a period during which one frame's worth of image signal Vsig is displayed.

[0042] The shift clock signal CKV is a signal that undergoes logic inversion at a predetermined cycle. More specifically, the shift clock signal CKV is a signal that transitions from a low potential to a high potential, with the high potential period of the start pulse signal STV being one cycle.

[0043] A start pulse signal STV and a shift clock signal CKV are input to the shift register circuit 421_1. An output signal SROUT(p-1) of a preceding shift register circuit 421_p-1 (not shown) is input to the shift register circuit 421_p instead of the start pulse signal STV. An output signal SROUT(P-1) of a preceding shift register circuit 421_P-1 (not shown) is input to the shift register circuit 421_P instead of the start pulse signal STV.

[0044] The shift register circuits 421_1, ···, 421_p, ···, 421_P respectively include clocked inverters 51, 53, 54, 56 and inverters 52, 55. The shift register circuits 421_1, ···, 421_p, ···, 421_P generate an inverted shift clock signal xCKV obtained by logically inverting the shift clock signal CKV.

[0045] When the shift clock signal CKV is at a high potential and the inverted shift clock signal xCKV is at a low potential, the clocked inverters 51 and 56 are on and the clocked inverters 53 and 54 are off. At this time, when the start pulse signal STV (or the output signal SROUT(p-1) of the preceding shift register circuit 421_p-1 (not shown)) becomes a high potential, the output potential of the inverter 52 is held at a high potential.

[0046] In this state, when the shift clock signal CKV goes low and the inverted shift clock signal xCKV goes high, the clocked inverters 51 and 56 turn off and the clocked inverters 53 and 54 turn on. As a result, the high potential held as the output potential of the inverter 52 becomes the output potential of the output signal SRout(p).

[0047] When the shift clock signal CKV is at a high potential and the inverted shift clock signal xCKV is at a low potential, the clocked inverters 51 and 56 are on and the clocked inverters 53 and 54 are off. At this time, when the start pulse signal STV (or the output signal SROUT(p-1) of the preceding shift register circuit 421_p-1 (not shown)) becomes a low potential, the low potential is held as the output potential of the inverter 52.

[0048] In this state, when the shift clock signal CKV goes low and the inverted shift clock signal xCKV goes high, the clocked inverters 51 and 56 turn off and the clocked inverters 53 and 54 turn on. As a result, the low potential held as the output potential of the inverter 52 becomes the output potential of the output signal SRout(p).

[0049] 6 is a circuit diagram showing an example of the circuit configuration of the gate line driving circuit 422. The gate line driving circuit 422 receives a first enable signal ENB1, a second enable signal ENB2, a third enable signal ENB3, and a fourth enable signal ENB4 from the display control circuit 44.

[0050] The gate line driving circuit 422_1 receives an output signal SRout(1) from the shift register circuit 421_1. The gate line driving circuit 422_p receives an output signal SRout(p) from the shift register circuit 421_p. The gate line driving circuit 422_P receives an output signal SRout(P) from the shift register circuit 421_P.

[0051] The configuration of the gate line driving circuit 422_p will be described below: The gate line driving circuit 422_p generates an inverted output signal xSRout(p) by logically inverting the output signal SRout(p) output from the shift register circuit 421_p.

[0052] The gate line driving circuit 422_p supplies a gate signal GATE to the n-th pixel Pix arranged in the Dx direction (first direction) in the Dy direction (second direction). <n>a gate signal GATE supplied to the pixel Pix arranged in the Dx direction (first direction) that is the n+1th pixel in the Dy direction (second direction);<n+1> a gate signal GATE supplied to the pixel Pix arranged in the Dx direction (first direction) at the n+2th position in the Dy direction (second direction);<n+2> and a gate signal GATE supplied to the pixel Pix arranged in the Dx direction (first direction) at the n+3th position in the Dy direction (second direction).<n+3> The fourth buffer circuit 61_4 generates the following:

[0053] When the output signal SRout(p) output from the shift register circuit 421_p is at a low potential (first potential VGL), the first transistor Tr1 and the second transistor Tr2 of the first buffer circuit 61_1 are controlled to be off and the third transistor Tr3 is controlled to be on, so that the output potential of the first buffer circuit 61_1 becomes the first potential VGL, and the pixel transistor Tr of the n-th pixel Pix aligned in the Dx direction (first direction) in the Dy direction (second direction) is controlled to be off.

[0054] Furthermore, in the first buffer circuit 61_1, when the output signal SRout(p) output from the shift register circuit 421_p is at a high potential (the second potential VGH), the first transistor Tr1 and the second transistor Tr2 are controlled to be on and the third transistor Tr3 is controlled to be off, so that the output potential of the first buffer circuit 61_1 becomes a potential (for example, the second potential VGH) that depends on the potential of the first enable signal ENB1, and the pixel transistor Tr of the n-th pixel Pix aligned in the Dx direction (first direction) in the Dy direction (second direction) is controlled to be on.

[0055] When the output signal SRout(p) output from the shift register circuit 421_p is at a low potential (first potential VGL), the first transistor Tr1 and the second transistor Tr2 of the second buffer circuit 61_2 are controlled to be off and the third transistor Tr3 is controlled to be on, so that the output potential of the second buffer circuit 61_2 becomes the first potential VGL, and the pixel transistor Tr of the pixel Pix that is the (n+1)th in the Dy direction (second direction) and aligned in the Dx direction (first direction) is controlled to be off.

[0056] Furthermore, in the second buffer circuit 61_2, when the output signal SRout(p) output from the shift register circuit 421_p is at a high potential (the second potential VGH), the first transistor Tr1 and the second transistor Tr2 are controlled to be on and the third transistor Tr3 is controlled to be off, so that the output potential of the second buffer circuit 61_2 becomes a potential (for example, the second potential VGH) that depends on the potential of the second enable signal ENB2, and the pixel transistor Tr of the pixel Pix that is the (n+1)th in the Dy direction (second direction) and aligned in the Dx direction (first direction) is controlled to be on.

[0057] When the output signal SRout(p) output from the shift register circuit 421_p is at a low potential (first potential VGL), the first transistor Tr1 and the second transistor Tr2 of the third buffer circuit 61_3 are controlled to be off and the third transistor Tr3 is controlled to be on, so that the output potential of the third buffer circuit 61_3 becomes the first potential VGL and the pixel transistor Tr of the pixel Pix that is the (n+2)th in the Dy direction (second direction) and aligned in the Dx direction (first direction) is controlled to be off.

[0058] Furthermore, in the third buffer circuit 61_3, when the output signal SRout(p) output from the shift register circuit 421_p is at a high potential (the second potential VGH), the first transistor Tr1 and the second transistor Tr2 are controlled to be on and the third transistor Tr3 is controlled to be off, so that the output potential of the third buffer circuit 61_3 becomes a potential (for example, the second potential VGH) that depends on the potential of the third enable signal ENB3, and the pixel transistor Tr of the pixel Pix that is the (n+2)th in the Dy direction (second direction) and aligned in the Dx direction (first direction) is controlled to be on.

[0059] When the output signal SRout(p) output from the shift register circuit 421_p is at a low potential (first potential VGL), the first transistor Tr1 and the second transistor Tr2 of the fourth buffer circuit 61_4 are controlled to be off and the third transistor Tr3 is controlled to be on, so that the output potential of the fourth buffer circuit 61_4 becomes the first potential VGL, and the pixel transistor Tr of the pixel Pix that is the (n+3)th in the Dy direction (second direction) and aligned in the Dx direction (first direction) is controlled to be off.

[0060] Furthermore, in the fourth buffer circuit 61_4, when the output signal SRout(p) output from the shift register circuit 421_p is at a high potential (the second potential VGH), the first transistor Tr1 and the second transistor Tr2 are controlled to be on and the third transistor Tr3 is controlled to be off, so that the output potential of the fourth buffer circuit 61_4 becomes a potential (for example, the second potential VGH) that depends on the potential of the fourth enable signal ENB4, and the pixel transistor Tr of the pixel Pix that is the (n+3)th in the Dy direction (second direction) and aligned in the Dx direction (first direction) is controlled to be on.

[0061] (Embodiment 1) Fig. 7 is a timing chart showing a first example of gate line driving according to Comparative Example 1. Fig. 8 is a timing chart showing a second example of gate line driving according to Comparative Example 1.

[0062] A first example of gate line driving according to the first comparative example shown in Fig. 7 illustrates a mode in which pixels Pix connected to gate lines SCL aligned in the Dy direction (second direction) are sequentially driven every horizontal period 1H. A second example of gate line driving according to the first comparative example shown in Fig. 8 illustrates a mode in which pixels Pix connected to two gate lines SCL aligned in the Dy direction (second direction) are simultaneously driven every horizontal period 1H.

[0063] More specifically, in FIG. 8, in the first half of two horizontal periods in which the output signal SRout(p) output from the shift register circuit 421_p is at a high potential (second potential VGH), the gate signal GATE <n>and the gate signal GATE<n+1> and simultaneously change from a low potential (first potential VGL) to a high potential (second potential VGH). As a result, the pixel transistor Tr of the n-th pixel Pix aligned in the Dx direction (first direction) in the Dy direction (second direction) and the pixel transistor Tr of the n+1-th pixel Pix aligned in the Dx direction (first direction) in the Dy direction (second direction) are simultaneously controlled to be on.

[0064] 8, in the first half of two horizontal periods in which the output signal SRout(p) output from the shift register circuit 421_p is at a high potential (second potential VGH), the gate signal GATE <n>and the gate signal GATE<n+1> and simultaneously change from high potential (second potential VGH) to low potential (first potential VGL). As a result, the pixel transistor Tr of the n-th pixel Pix aligned in the Dx direction (first direction) in the Dy direction (second direction) and the pixel transistor Tr of the n+1-th pixel Pix aligned in the Dx direction (first direction) in the Dy direction (second direction) are simultaneously controlled to be off.

[0065] In addition, in the latter half of the two horizontal periods in which the output signal SRout(p) output from the shift register circuit 421_p is at a high potential (second potential VGH), the gate signal GATE<n+2> and the gate signal GATE<n+3> and simultaneously change from a low potential (first potential VGL) to a high potential (second potential VGH). As a result, the pixel transistor Tr of the pixel Pix that is the (n+2)th pixel in the Dy direction (second direction) aligned in the Dx direction (first direction) and the pixel transistor Tr of the pixel Pix that is the (n+3)th pixel in the Dy direction (second direction) aligned in the Dx direction (first direction) are simultaneously controlled to be on.

[0066] 8, in the latter half of the two horizontal periods in which the output signal SRout(p) output from the shift register circuit 421_p is at a high potential (second potential VGH), the gate signal GATE<n+2> and the gate signal GATE<n+3> and simultaneously change from a high potential (second potential VGH) to a low potential (first potential VGL), and the pixel transistor Tr of the pixel Pix that is the n+2th in the Dy direction (second direction) and aligned in the Dx direction (first direction) and the pixel transistor Tr of the pixel Pix that is the n+3th in the Dy direction (second direction) and aligned in the Dx direction (first direction) are simultaneously controlled to be off.

[0067] This makes it possible to achieve a higher frame rate than in the first example shown in Fig. 7. Specifically, in the driving mode of the second example shown in Fig. 8, the frame rate can be approximately doubled compared to the first example shown in Fig. 7.

[0068] In the display device 1 having the above-described schematic structure, in addition to the storage capacitance Cs formed between the pixel electrode PX and the common electrode COML, parasitic capacitances are generated between the pixel electrode PX and other conductive members. Specifically, as shown in Fig. 2, parasitic capacitances Cgs1 and Cgs2 are generated between the pixel electrode PX and two gate lines SCL that sandwich the pixel transistor Tr in the Dy direction (second direction). Therefore, a potential drop occurs in the pixel electrode PX due to the so-called feed-through phenomenon caused by charge redistribution of the storage capacitance Cs when the gate is off.

[0069] In the following description, the n-th pixel Pix aligned in the Dx direction (first direction) in the Dy direction (second direction) is also referred to as the “first pixel.” In addition, in this disclosure, the gate line connected to the gate of the pixel transistor Tr of the first pixel corresponds to the “first gate line.”

[0070] In addition, the pixel Pix that is the (n+1)th pixel in the Dy direction (second direction) and aligned in the Dx direction (first direction) is also referred to as the “second pixel.” In addition, in the present disclosure, the gate line connected to the gate of the pixel transistor Tr of the second pixel corresponds to the “second gate line.”

[0071] Furthermore, the parasitic capacitance Cgs1 generated between each pixel Pix and the gate line SCL above it shown in Fig. 2 is also referred to as the "first parasitic capacitance Cgs1." Furthermore, the parasitic capacitance Cgs2 generated between each pixel Pix and the gate line SCL below it shown in Fig. 2 is also referred to as the "second parasitic capacitance Cgs2."

[0072] In the driving mode of the first example of gate line driving according to the first comparative example shown in FIG. 7, the feedthrough voltage ΔV is a first potential VGL, a pixel signal SIG <m>Using the potential Vd, the storage capacitance Cs, the first parasitic capacitance Cgs1, and the second parasitic capacitance Cgs2, the potential Vd is expressed by the following equation (1).

[0073] ΔV=(Vd-VGL)×Cgs1 / (Cgs1+Cgs2+Cs)...(1)

[0074] The capacitance values ​​of the first parasitic capacitance Cgs1 and the second parasitic capacitance Cgs2 are set to about 1 / 100 of the storage capacitance Cs. The relationship between the capacitance value Cgs1 of the first parasitic capacitance and the capacitance value Cgs2 of the second parasitic capacitance is generally Cgs1>Cgs2.

[0075] In the driving mode of the first example of gate line driving according to the first comparative example shown in FIG. 7, the feedthrough voltages generated in the first pixel and the second pixel can both be expressed by the above formula (1).

[0076] In contrast, in the driving mode of the second example of gate line driving according to the first comparative example shown in Fig. 8, a difference occurs in the feedthrough voltage between the first pixel and the second pixel. Specifically, the feedthrough voltage ΔV generated in the second pixel is expressed by the above formula (1), which is the same as the driving mode of the first example of gate line driving according to the first comparative example shown in Fig. 7. On the other hand, the feedthrough voltage ΔV generated in the first pixel is expressed by the following formula (2).

[0077] ΔV=(Vd-VGL)×(Cgs1+Cgs2) / (Cgs1+Cgs2+Cs) ···(2)

[0078] This causes a difference in pixel electrode potential between the first pixel and the second pixel that are driven simultaneously, which may result in a deterioration in display quality.

[0079] In the gate line driving example according to the first embodiment, when a first pixel and a second pixel aligned in the Dy direction (second direction) are simultaneously driven, the pixel transistor of the second pixel is turned off before the pixel transistor of the first pixel is turned off, thereby suppressing the potential difference in pixel electrode potential occurring between the first pixel and the second pixel that are simultaneously driven.

[0080] 9 is a timing chart showing an example of gate line driving according to the first embodiment. Specifically, in the first embodiment, as shown in FIG. 9, the gate driver 42 drives the gate signal GATE <n>and the gate signal GATE<n+1> and are simultaneously controlled from a low potential (first potential VGL) to a high potential (second potential VGH), and then the gate signal GATE<n+1> , gate signal GATE <n>The potentials are controlled in this order from a high potential (second potential VGH) to a low potential (first potential VGL).

[0081] In Figure 9, the gate signal GATE<n+1> is controlled from a high potential (second potential VGH) to a low potential (first potential VGL), and then after a delay time td has elapsed, the gate signal GATE <n>is controlled from a high potential (second potential VGH) to a low potential (first potential VGL).

[0082] Furthermore, the gate driver 42 outputs the gate signal GATE during the second half horizontal period 1H of the two horizontal periods in which the output signal SRout(p) output from the shift register circuit 421_p is at a high potential (the second potential VGH).<n+2> and the gate signal GATE<n+3> and are simultaneously controlled from a low potential (first potential VGL) to a high potential (second potential VGH), and then the gate signal GATE<n+3> , gate signal GATE<n+2> The potentials are controlled in this order from a high potential (second potential VGH) to a low potential (first potential VGL).

[0083] In Figure 9, the gate signal GATE<n+3> is controlled from a high potential (second potential VGH) to a low potential (first potential VGL), and then after a delay time td has elapsed, the gate signal GATE<n+2> is controlled from a high potential (second potential VGH) to a low potential (first potential VGL).

[0084] As a result, the gate signal GATE <n>The feedthrough voltage generated in the pixel Pix to which the gate signal GATE<n+1> The feedthrough voltage generated in the pixel Pix to which the gate signal GATE<n+2> The feedthrough voltage generated in the pixel Pix to which the gate signal GATE<n+3> All of the feedthrough voltages generated in the pixels Pix to which the voltage V is supplied are expressed by the above formula (1), which is the same as the driving mode of the first example of gate line driving according to the first comparative example shown in Fig. 7. This makes it possible to suppress degradation of display quality caused by charge redistribution of the storage capacitor when the gate is off.

[0085] Fig. 10 is a timing chart showing a third example of gate line driving according to Comparative Example 1. The third example of gate line driving according to Comparative Example 1 shown in Fig. 10 illustrates an example in which pixels Pix connected to four gate lines SCL arranged in the Dy direction (second direction) are simultaneously driven in one horizontal period 1H.

[0086] More specifically, in FIG. 10, in one horizontal period in which the output signal SRout(p) output from the shift register circuit 421_p is at a high potential (second potential VGH), the gate signal GATE <n>, gate signal GATE<n+1> , gate signal GATE<n+2> , and the gate signal GATE<n+3> are simultaneously set to a high potential (second potential VGH). As a result, the pixel transistor Tr of the n-th pixel Pix in the Dy direction (second direction) aligned in the Dx direction (first direction), the pixel transistor Tr of the n+1-th pixel Pix in the Dy direction (second direction) aligned in the Dx direction (first direction), the pixel transistor Tr of the n+2-th pixel Pix in the Dy direction (second direction) aligned in the Dx direction (first direction), and the pixel transistor Tr of the n+3-th pixel Pix in the Dy direction (second direction) aligned in the Dx direction (first direction) are simultaneously controlled to be on.

[0087] In addition, in FIG. 10, in one horizontal period in which the output signal SRout(p) output from the shift register circuit 421_p is at a high potential (second potential VGH), the gate signal GATE <n>, gate signal GATE<n+1> , gate signal GATE<n+2> , and the gate signal GATE<n+3> are simultaneously changed from a high potential (second potential VGH) to a low potential (first potential VGL), and the pixel transistor Tr of the pixel Pix that is the nth pixel in the Dy direction (second direction) aligned in the Dx direction (first direction), the pixel transistor Tr of the pixel Pix that is the n+1th pixel in the Dy direction (second direction) aligned in the Dx direction (first direction), the pixel transistor Tr of the pixel Pix that is the n+2th pixel in the Dy direction (second direction) aligned in the Dx direction (first direction), and the pixel transistor Tr of the pixel Pix that is the n+3rd pixel in the Dy direction (second direction) aligned in the Dx direction (first direction) are simultaneously controlled to be turned off.

[0088] This makes it possible to achieve an even higher frame rate than the second example of gate line driving according to the first comparative example shown in Fig. 7. Specifically, in the driving mode of the third example of gate line driving according to the first comparative example shown in Fig. 10, the frame rate can be approximately four times that of the first example of gate line driving according to the first comparative example shown in Fig. 7, and the frame rate can be approximately twice that of the second example of gate line driving according to the first comparative example shown in Fig. 8.

[0089] In the following description, the n-th pixel Pix aligned in the Dx direction (first direction) in the Dy direction (second direction) is also referred to as the “first pixel.” In addition, in this disclosure, the gate line connected to the gate of the pixel transistor Tr of the first pixel corresponds to the “first gate line.”

[0090] In addition, the pixel Pix that is the (n+1)th pixel in the Dy direction (second direction) and aligned in the Dx direction (first direction) is also referred to as the “second pixel.” In addition, in the present disclosure, the gate line connected to the gate of the pixel transistor Tr of the second pixel corresponds to the “second gate line.”

[0091] In addition, the pixel Pix that is the (n+2)th pixel in the Dy direction (second direction) and aligned in the Dx direction (first direction) is also referred to as the “third pixel.” In addition, in the present disclosure, the gate line connected to the gate of the pixel transistor Tr of the third pixel corresponds to the “third gate line.”

[0092] In addition, the pixel Pix that is the (n+3)th pixel in the Dy direction (second direction) and aligned in the Dx direction (first direction) is also referred to as the “fourth pixel.” In addition, in the present disclosure, the gate line connected to the gate of the pixel transistor Tr of the fourth pixel corresponds to the “fourth gate line.”

[0093] In a gate line driving example according to a modification of the first embodiment, when a first pixel, a second pixel, a third pixel, and a fourth pixel arranged in the Dy direction (second direction) are simultaneously driven, the pixel transistor of the second pixel is turned off before the pixel transistor of the first pixel, the pixel transistor of the third pixel is turned off before the pixel transistor of the second pixel, and the pixel transistor of the fourth pixel is turned off before the pixel transistor of the third pixel, thereby making it possible to suppress a potential difference in pixel electrode potential occurring among the simultaneously driven first pixel, second pixel, third pixel, and fourth pixel.

[0094] 11 is a timing chart showing an example of gate line driving according to a modification of embodiment 1. Specifically, in the modification of embodiment 1, as shown in FIG. 11, the gate driver 42 drives the gate signal GATE <n>, gate signal GATE<n+1> , gate signal GATE<n+2> , and the gate signal GATE<n+3> are simultaneously controlled from a low potential (first potential VGL) to a high potential (second potential VGH), and then the gate signal GATE<n+3> , gate signal GATE<n+2> , gate signal GATE<n+1> , gate signal GATE <n>The potentials are controlled in this order from a high potential (second potential VGH) to a low potential (first potential VGL).

[0095] In FIG. 11, the gate signal GATE<n+3> is controlled from a high potential (second potential VGH) to a low potential (first potential VGL), and then after a delay time td1 has elapsed, the gate signal GATE<n+2> is controlled from a high potential (second potential VGH) to a low potential (first potential VGL), and the gate signal GATE<n+2> is controlled from a high potential (second potential VGH) to a low potential (first potential VGL), and then after a delay time td2 has elapsed, the gate signal GATE<n+1> is controlled from a high potential (second potential VGH) to a low potential (first potential VGL), and the gate signal GATE<n+1> is controlled from a high potential (second potential VGH) to a low potential (first potential VGL), and then after a delay time td3 has elapsed, the gate signal GATE <n>is controlled from a high potential (second potential VGH) to a low potential (first potential VGL).

[0096] As a result, as in the first embodiment, the gate signal GATE <n>The feedthrough voltage generated in the pixel Pix to which the gate signal GATE<n+1> The feedthrough voltage generated in the pixel Pix to which the gate signal GATE<n+2> The feedthrough voltage generated in the pixel Pix to which the gate signal GATE<n+3> All of the feedthrough voltages generated in the pixels Pix to which the voltage V is supplied are expressed by the above formula (1), which is the same as the driving mode of the first example of gate line driving according to the first comparative example shown in Fig. 7. This makes it possible to suppress degradation of display quality caused by charge redistribution of the storage capacitor when the gate is off.

[0097] (Embodiment 2) Fig. 12 is a timing chart showing a first example of gate line driving according to Comparative Example 2. Fig. 13 is a timing chart showing a second example of gate line driving according to Comparative Example 2.

[0098] A first example of gate line driving according to the second comparative example shown in Fig. 12 illustrates an example in which pixels Pix connected to gate lines SCL aligned in the Dy direction (second direction) are sequentially driven every horizontal period 1H, similar to the first example of gate line driving according to the first comparative example shown in Fig. 7. A second example of gate line driving according to the second comparative example shown in Fig. 13 illustrates an example in which pixels Pix connected to two gate lines SCL aligned in the Dy direction (second direction) are simultaneously driven every horizontal period 1H, similar to the second example of gate line driving according to the first comparative example shown in Fig. 8.

[0099] In a first example of gate line driving according to the second comparative example shown in FIG. 12 and a second example of gate line driving according to the second comparative example shown in FIG. 13, the gate signal GATE is first controlled from a low potential (first potential VGL) to a high potential (second potential VGH), and then the gate signal GATE is controlled to an intermediate potential (third potential VGM) between the low potential (first potential VGL) and the high potential (second potential VGH) (period tc shown in FIGS. 12 and 13), and then the gate signal GATE is controlled from the intermediate potential (third potential VGM) to the low potential (first potential VGL). The intermediate potential (third potential VGM) is set to, for example, the GND potential. This makes it possible to suppress transient potential fluctuations caused by charge redistribution in the storage capacitance Cs when the gate is turned off.

[0100] 14 is a timing chart showing an example of gate line driving according to the second embodiment. Specifically, in the second embodiment, as shown in FIG. 14, the gate driver 42 drives the gate signal GATE <n>and the gate signal GATE<n+1> and are simultaneously controlled from a low potential (first potential VGL) to a high potential (second potential VGH), and then the gate signal GATE <n>and the gate signal GATE<n+1> and are simultaneously controlled from a high potential (second potential VGH) to an intermediate potential (third potential VGM) (periods tc1 and tc2 shown in FIG. 14), and further, the gate signal GATE<n+1> , gate signal GATE <n>The potentials are controlled in this order from the intermediate potential (third potential VGM) to the low potential (first potential VGL).

[0101] In FIG. 14, the gate signal GATE<n+1> is controlled from the intermediate potential (third potential VGM) to the low potential (first potential VGL), and then after the delay time td has elapsed, the gate signal GATE <n>is controlled from an intermediate potential (third potential VGM) to a low potential (first potential VGL).

[0102] Furthermore, the gate driver 42 outputs the gate signal GATE during the second half horizontal period 1H of the two horizontal periods in which the output signal SRout(p) output from the shift register circuit 421_p is at a high potential (the second potential VGH).<n+2> and the gate signal GATE<n+3> and are simultaneously controlled from a low potential (first potential VGL) to a high potential (second potential VGH), and then the gate signal GATE<n+2> and the gate signal GATE<n+3> and are simultaneously controlled from a high potential (second potential VGH) to an intermediate potential (third potential VGM), and further, the gate signal GATE<n+3> , gate signal GATE<n+2> The potentials are controlled in this order from the intermediate potential (third potential VGM) to the low potential (first potential VGL).

[0103] In FIG. 14, the gate signal GATE<n+3> is controlled from the intermediate potential (third potential VGM) to the low potential (first potential VGL), and then after the delay time td has elapsed, the gate signal GATE<n+2> is controlled from an intermediate potential (third potential VGM) to a low potential (first potential VGL).

[0104] As a result, as in the first embodiment, the gate signal GATE <n>The feedthrough voltage generated in the pixel Pix to which the gate signal GATE<n+1> The feedthrough voltage generated in the pixel Pix to which the gate signal GATE<n+2> The feedthrough voltage generated in the pixel Pix to which the gate signal GATE<n+3> All of the feedthrough voltages generated in the pixels Pix to which the voltage V is supplied are expressed by the above formula (1), which is the same as the driving mode of the first example of gate line driving according to the first comparative example shown in Fig. 7. This makes it possible to suppress degradation of display quality caused by charge redistribution of the storage capacitor when the gate is off.

[0105] Fig. 15 is a timing chart showing a third example of gate line driving according to Comparative Example 2. The third example of gate line driving according to Comparative Example 2 shown in Fig. 15 illustrates an example in which, similar to the third example of gate line driving according to Comparative Example 1 shown in Fig. 10, pixels Pix connected to four gate lines SCL arranged in the Dy direction (second direction) are simultaneously driven in one horizontal period 1H.

[0106] In the third example of gate line driving according to the second comparative example shown in FIG. 15, similarly to the first example of gate line driving according to the second comparative example shown in FIG. 12 and the second example of gate line driving according to the second comparative example shown in FIG. 13, the gate signal GATE is first controlled from a low potential (first potential VGL) to a high potential (second potential VGH), and then the gate signal GATE is controlled to an intermediate potential (third potential VGM) between the low potential (first potential VGL) and the high potential (second potential VGH) (period tc shown in FIG. 15), and then the gate signal GATE is controlled from the intermediate potential (third potential VGM) to the low potential (first potential VGL). The intermediate potential (third potential VGM) is set to, for example, the GND potential. This makes it possible to suppress transient potential fluctuations caused by charge redistribution of the storage capacitance Cs when the gate is turned off.

[0107] More specifically, in FIG. 15, in one horizontal period in which the output signal SRout(p) output from the shift register circuit 421_p is at a high potential (second potential VGH), the gate signal GATE <n>, gate signal GATE<n+1> , gate signal GATE<n+2> , and the gate signal GATE<n+3> are simultaneously set to a high potential (second potential VGH). As a result, the pixel transistor Tr of the n-th pixel Pix in the Dy direction (second direction) aligned in the Dx direction (first direction), the pixel transistor Tr of the n+1-th pixel Pix in the Dy direction (second direction) aligned in the Dx direction (first direction), the pixel transistor Tr of the n+2-th pixel Pix in the Dy direction (second direction) aligned in the Dx direction (first direction), and the pixel transistor Tr of the n+3-th pixel Pix in the Dy direction (second direction) aligned in the Dx direction (first direction) are simultaneously controlled to be on.

[0108] In addition, in FIG. 15, in one horizontal period in which the output signal SRout(p) output from the shift register circuit 421_p is at a high potential (second potential VGH), the gate signal GATE <n>, gate signal GATE<n+1> , gate signal GATE<n+2> , and the gate signal GATE<n+3> are simultaneously changed from the intermediate potential (third potential VGM) to the low potential (first potential VGL), and the pixel transistor Tr of the pixel Pix that is the nth pixel in the Dy direction (second direction) aligned in the Dx direction (first direction), the pixel transistor Tr of the pixel Pix that is the n+1th pixel in the Dy direction (second direction) aligned in the Dx direction (first direction), the pixel transistor Tr of the pixel Pix that is the n+2th pixel in the Dy direction (second direction) aligned in the Dx direction (first direction), and the pixel transistor Tr of the pixel Pix that is the n+3rd pixel in the Dy direction (second direction) aligned in the Dx direction (first direction) are simultaneously controlled to be turned off.

[0109] This makes it possible to achieve a frame rate that is even higher than that of the second example of gate line driving according to the second comparative example shown in Fig. 12. Specifically, in the driving mode of the third example of gate line driving according to the second comparative example shown in Fig. 15, the frame rate can be about four times that of the first example of gate line driving according to the second comparative example shown in Fig. 12, and about twice that of the second example of gate line driving according to the second comparative example shown in Fig. 13.

[0110] 16 is a timing chart showing an example of gate line driving according to a modification of the second embodiment. Specifically, in the modification of the second embodiment, as shown in FIG. 16, the gate driver 42 drives the gate signal GATE <n>, gate signal GATE<n+1> , gate signal GATE<n+2> , and the gate signal GATE<n+3> are simultaneously controlled from a low potential (first potential VGL) to a high potential (second potential VGH), and then the gate signal GATE <n>, gate signal GATE<n+1> , gate signal GATE<n+2> , and the gate signal GATE<n+3> are simultaneously controlled from a high potential (second potential VGH) to an intermediate potential (third potential VGM) (periods tc1, tc2, tc3, and tc4 shown in FIG. 16), and further, the gate signal GATE<n+3> , gate signal GATE<n+2> , gate signal GATE<n+1> , gate signal GATE <n>The potentials are controlled in this order from the intermediate potential (third potential VGM) to the low potential (first potential VGL).

[0111] In FIG. 16, the gate signal GATE<n+3> is controlled from the intermediate potential (third potential VGM) to the low potential (first potential VGL), and then after the delay time td1 has elapsed, the gate signal GATE<n+2> is controlled from the intermediate potential (third potential VGM) to the low potential (first potential VGL), and the gate signal GATE<n+2> is controlled from the intermediate potential (third potential VGM) to the low potential (first potential VGL), and then after the delay time td2 has elapsed, the gate signal GATE<n+1> is controlled from the intermediate potential (third potential VGM) to the low potential (first potential VGL), and the gate signal GATE<n+1> is controlled from the intermediate potential (third potential VGM) to the low potential (first potential VGL), and then after the delay time td3 has elapsed, the gate signal GATE <n>is controlled from an intermediate potential (third potential VGM) to a low potential (first potential VGL).

[0112] As a result, as in the modification of the first embodiment, the gate signal GATE <n>The feedthrough voltage generated in the pixel Pix to which the gate signal GATE<n+1> The feedthrough voltage generated in the pixel Pix to which the gate signal GATE<n+2> The feedthrough voltage generated in the pixel Pix to which the gate signal GATE<n+3> All of the feedthrough voltages generated in the pixels Pix to which the voltage V is supplied are expressed by the above formula (1), which is the same as the driving mode of the first example of gate line driving according to the first comparative example shown in Fig. 7. This makes it possible to suppress degradation of display quality caused by charge redistribution of the storage capacitor when the gate is off.

[0113] The display device 1 is not limited to a liquid crystal display device, and may be, for example, an organic EL display using organic light emitting diodes (OLEDs) as display elements. The display device 1 may also be an inorganic EL display using inorganic light emitting diodes (micro LEDs) as display elements. The display device 1 may also be an electrophoretic display (EPD), or may even be a transparent display that displays an image on a transparent display surface.

[0114] Furthermore, in the above embodiment, an example has been given in which two or four gate lines SCL arranged in the Dy direction (second direction) are driven simultaneously, but the number of gate lines driven simultaneously is not limited to 2 or 4. Furthermore, an example may be one in which the number of gate lines SCL driven simultaneously is changed depending on the position in the Dy direction (second direction).

[0115] Although preferred embodiments of the present disclosure have been described above, the present disclosure is not limited to such embodiments. The contents disclosed in the embodiments are merely examples, and various modifications are possible within the scope of the present disclosure. Appropriate modifications made within the scope of the present disclosure also naturally fall within the technical scope of the present disclosure. [Explanation of symbols]

[0116] 1 Display device 4 Driver IC 11 Display panel 12 Power supply 13 Control device 40 Drive circuit 42 Gate Driver 43 Signal line selection circuit 44 Display control circuit 421,421_1,421_p,421_P Shift register circuit 422, 422_1, 422_p, 422_P Gate line driving circuit AA display area Cgs1 1st parasitic capacitance Cgs2 2nd parasitic capacitance CKV Shift clock signal COML Common electrode Cs retention capacity DTL signal line ENB Enable signal ENB1 First enable signal ENB2 Second enable signal ENB3 Third enable signal ENB4 4th enable signal GATE Gate signal Pix PX pixel electrode Source video signal SCL gate line SIG pixel signal STV Start pulse signal Tr Pixel transistor VCOM common potential VGH Second potential VGL 1st potential Vsig Image signal< / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / m> < / n> < / n> < / n> < / n> < / n> < / m> < / n>

Claims

1. a plurality of first pixels arranged in a first direction; a plurality of second pixels adjacent to the plurality of first pixels in a second direction intersecting the first direction and arranged in the first direction; a first gate line connected to the gate of the pixel transistor of the first pixel; a second gate line connected to the gate of the pixel transistor of the second pixel; a driving circuit that drives a pixel transistor of the first pixel via the first gate line and drives a pixel transistor of the second pixel via the second gate line; a display area in which the first gate line, the pixel transistor of the first pixel, the second gate line, and the pixel transistor of the second pixel are arranged in this order in the second direction; Equipped with The drive circuit the pixel transistor of the first pixel and the pixel transistor of the second pixel are simultaneously turned on, and then the pixel transistor of the second pixel and the pixel transistor of the first pixel are sequentially turned off; Display device.

2. The drive circuit the first gate line and the second gate line are simultaneously controlled from a first potential to a second potential higher than the first potential, and then the second gate line and the first gate line are controlled from the second potential to the first potential in this order; The display device according to claim 1 .

3. The drive circuit the first gate line and the second gate line are simultaneously controlled from a first potential to a second potential higher than the first potential, and then the first gate line and the second gate line are simultaneously controlled from the second potential to a third potential lower than the second potential and higher than the first potential, and further controlled from the third potential to the first potential in the order of the second gate line and the first gate line; The display device according to claim 1 .

4. a plurality of first pixels arranged in a first direction; a plurality of second pixels adjacent to the plurality of first pixels in a second direction intersecting the first direction and arranged in the first direction; a plurality of third pixels adjacent to the plurality of second pixels in the second direction and aligned in the first direction; a first gate line connected to the gate of the pixel transistor of the first pixel; a second gate line connected to the gate of the pixel transistor of the second pixel; a third gate line connected to the gate of the pixel transistor of the third pixel; a driving circuit that drives a pixel transistor of the first pixel via the first gate line, drives a pixel transistor of the second pixel via the second gate line, and drives a pixel transistor of the third pixel via the third gate line; a display area in which the first gate line, the pixel transistor of the first pixel, the second gate line, the pixel transistor of the second pixel, the third gate line, and the pixel transistor of the third pixel are arranged in this order in the second direction; Equipped with The drive circuit the pixel transistor of the first pixel, the pixel transistor of the second pixel, and the pixel transistor of the third pixel are simultaneously turned on, and then the pixel transistor of the third pixel, the pixel transistor of the second pixel, and the pixel transistor of the first pixel are sequentially turned off. Display device.

5. The drive circuit the first gate line, the second gate line, and the third gate line are simultaneously controlled from a first potential to a second potential higher than the first potential, and then controlled from the second potential to the first potential in the order of the third gate line, the second gate line, and the first gate line; The display device according to claim 4 .

6. The drive circuit the first gate line, the second gate line, and the third gate line are simultaneously controlled from a first potential to a second potential higher than the first potential, and then the first gate line, the second gate line, and the third gate line are simultaneously controlled from the second potential to a third potential lower than the second potential and higher than the first potential, and further controlled from the third potential to the first potential in the order of the third gate line, the second gate line, and the first gate line; The display device according to claim 4 .

Images