Semiconductor device

Abstract

To provide a semiconductor device capable of suppressing heat conducted through a lead.SOLUTION: The semiconductor device includes: a base part 21 having a first surface facing in a first direction and connected to a heat-dissipating member; a first lead 22 electrically connected to the base part and supplied with a reference potential from a second surface facing in a second direction opposite to the first direction; and a first semiconductor chip 10 mounted on a third surface of the base part facing in the second direction and having an active element for handling a high-frequency signal. The base part is provided with a hole 50 penetrating through the base part between a first location where the first lead is connected to the base part and the first semiconductor chip.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] It is known to provide grooves between the amplifiers on a substrate on which the amplifiers are mounted (for example, Patent Document 1).It is also known to mount the amplifiers on different substrates (for example, Patent Document 2). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2019-176282 [Patent Document 2] Japanese Patent Application Laid-Open No. 2009-272679 Summary of the Invention [Problem to be solved by the invention]

[0004] In Patent Documents 1 and 2, it is possible to suppress heat conduction between multiple amplifiers. However, when leads are connected to a base portion on which a semiconductor chip is mounted, heat generated in the semiconductor chip may be transmitted through the leads, which may adversely affect the circuit board or solder to which the leads are connected.

[0005] An object of the present disclosure is to provide a semiconductor device that can suppress heat transfer through leads. [Means for solving the problem]

[0006] An embodiment of the present disclosure is a semiconductor device comprising: a base portion having a first surface facing a first direction connected to a heat dissipation member; a first lead electrically connected to the base portion and supplied with a reference potential from a second surface facing a second direction opposite to the first direction; and a first semiconductor chip mounted on a third surface facing the second direction of the base portion and having an active element that handles high-frequency signals, wherein the base portion has a hole penetrating the base portion between the first location where the first lead is connected to the base portion and the first semiconductor chip.

[0007] An embodiment of the present disclosure is a semiconductor device comprising: a base portion having a first surface facing a first direction connected to a heat dissipation member; a first lead electrically connected to the base portion and supplied with a reference potential from a second surface facing a second direction opposite to the first direction; and a first semiconductor chip mounted on a third surface facing the second direction of the base portion and having an active element that handles high-frequency signals, wherein a hole is provided through the first lead. [Effects of the Invention]

[0008] According to the present disclosure, it is possible to provide a semiconductor device that suppresses heat transfer through leads. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a cross-sectional view of a module on which a semiconductor device according to the first embodiment is mounted. [Figure 2] FIG. 2 is a plan view of the semiconductor device according to the first embodiment. [Figure 3] FIG. 3 is a cross-sectional view of a module on which a semiconductor device according to a first comparative example is mounted. [Figure 4] FIG. 4 is a plan view of a semiconductor device according to a first comparative example. [Figure 5] FIG. 5 is a cross-sectional view of a module on which a semiconductor device according to a second comparative example is mounted. [Figure 6] FIG. 6 is a plan view of a semiconductor device according to a second comparative example. [Figure 7]FIG. 7 is a plan view of the semiconductor device in Simulation 1. As shown in FIG. [Figure 8] FIG. 8 is a diagram showing S11 versus frequency in Simulation 2. [Figure 9] FIG. 9 is a diagram showing S21 versus frequency in Simulation 2. [Figure 10] FIG. 10 is a plan view of a semiconductor device according to a first modification of the first embodiment. [Figure 11] FIG. 11 is a plan view of a semiconductor device according to the second modification of the first embodiment. [Figure 12] FIG. 12 is a plan view of a semiconductor device according to a third modification of the first embodiment. [Figure 13] FIG. 13 is a plan view of a semiconductor device according to the fourth modification of the first embodiment. [Figure 14] FIG. 14 is a plan view of the semiconductor device according to the second embodiment. [Figure 15] FIG. 15 is a plan view of a semiconductor device according to a first modification of the second embodiment. [Figure 16] FIG. 16 is a plan view of a semiconductor device according to Modification 2 of the second embodiment. [Figure 17] FIG. 17 is a plan view of a semiconductor device according to a third modification of the second embodiment. [Figure 18] FIG. 18 is a block diagram of a semiconductor device according to the third embodiment. [Figure 19] FIG. 19 is a plan view of the semiconductor device according to the third embodiment. [Figure 20] FIG. 20 is a plan view of a semiconductor device according to a first modification of the third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] [Description of the embodiments of the present disclosure] First, embodiments of the present disclosure will be listed and described.

[0011] (1) An embodiment of the present disclosure is a semiconductor device comprising: a base portion having a first surface facing a first direction connected to a heat dissipation member; a first lead to which a reference potential is supplied from a second surface facing a second direction opposite to the first direction and electrically connected to the base portion; and a first semiconductor chip mounted on a third surface facing the second direction of the base portion and having an active element for handling high-frequency signals, wherein the base portion has a hole penetrating the base portion between the first semiconductor chip and a first location where the first lead is connected to the base portion. This makes it possible to suppress heat transfer through the leads and to suppress deterioration of high-frequency characteristics. (2) In the above (1), the holes may be provided in plurality, and the plurality of holes may block at least half of the range of the first location as seen from the first semiconductor chip. This makes it possible to suppress heat transfer through the leads and to suppress deterioration of high-frequency characteristics. (3) In the above (1) or (2), the reference potential may be supplied from the surface facing the second direction, the reference potential may be electrically connected to the base, and a plurality of leads including the first lead may be provided, and the first lead may have the shortest distance between a portion of the plurality of leads connected to the base and the first semiconductor chip. This can suppress heat conduction through the first lead, which is the most susceptible to heat conduction. (4) In the above (3), the leads may include a second lead, and a distance between the first semiconductor chip and a second location where the second lead is connected to the base portion may be longer than a distance between the first location and the first semiconductor chip, and no hole penetrating the base portion may be provided between the second location and the first semiconductor chip. This can suppress deterioration of high-frequency characteristics. (5) In the above (3) or (4), a passive element chip having a passive element but no active element is mounted on the third surface, the leads include a third lead, at least a part of the passive element chip is located between a third location where the third lead is connected to the base and the first semiconductor chip, and no hole penetrating the base is provided between the third location and the first semiconductor chip, thereby suppressing degradation of high frequency characteristics. (6) In any of (3) to (5) above, a second semiconductor chip is mounted on the third surface and has an active element that handles high-frequency signals, and a fourth lead, the part of the plurality of leads connected to the base being closest to the second semiconductor chip, may not have a hole penetrating the base between the second semiconductor chip and a fourth point where the fourth lead is connected to the base, thereby suppressing degradation of high-frequency characteristics. (7) In the above (6), the first semiconductor chip may include a main amplifier of a Doherty amplifier, and the second semiconductor chip may include a peak amplifier of the Doherty amplifier, thereby suppressing degradation of high-frequency characteristics. (8) An embodiment of the present disclosure is a semiconductor device including: a base portion having a first surface facing a first direction connected to a heat dissipation member; a first lead to which a reference potential is supplied from a second surface facing a second direction opposite to the first direction and which is electrically connected to the base portion; and a first semiconductor chip mounted on a third surface facing the second direction of the base portion and having an active element that handles high-frequency signals, the first lead having a hole penetrating the first lead. This makes it possible to suppress heat transfer through the leads and to suppress deterioration of high-frequency characteristics. (9) In the above (8), the reference potential may be supplied from the surface facing the second direction, the reference potential may be electrically connected to the base, and the first lead may include a plurality of leads including the first lead, the first lead having the shortest distance between a portion of the plurality of leads connected to the base and the first semiconductor chip. This makes it possible to suppress heat conduction through the first lead, which is the most susceptible to heat conduction. (10) In the above (9), the leads may include a second lead, and a distance between a second location where the second lead is connected to the base and the first semiconductor chip may be longer than a distance between a first location where the first lead is connected to the base and the first semiconductor chip, and no hole may be provided through the second lead. This can suppress deterioration of high-frequency characteristics. (11) In the above (9) or (10), a passive element chip having a passive element but no active element is mounted on the third surface, the leads include a third lead, at least a part of the passive element chip is located between the first semiconductor chip and a third location where the third lead is connected to the base portion, and no hole penetrating the third lead may be provided, thereby suppressing deterioration of high frequency characteristics. (12) In any of the above (9) to (11), a second semiconductor chip is mounted on the third surface and has an active element that handles high-frequency signals, and a hole may not be provided through a fourth lead of the plurality of leads whose portion connected to the base is closest to the second semiconductor chip, thereby suppressing deterioration of high-frequency characteristics. (13) In the above (12), the first semiconductor chip may include a main amplifier of a Doherty amplifier, and the second semiconductor chip may include a peak amplifier of the Doherty amplifier, thereby suppressing degradation of high-frequency characteristics. (14) In any one of the above (1) to (13), the second surface may be mounted on a circuit board via solder, thereby suppressing deterioration of the solder. (15) In any of (1) to (14) above, a signal lead for inputting or outputting a high-frequency signal from the surface facing the second direction and a bonding wire for electrically connecting the signal lead to the first semiconductor chip may be provided, thereby enabling the supply of a reference potential and the input and output of a high-frequency signal to be performed from the same direction.

[0012] [Details of the embodiments of the present disclosure] Specific examples of semiconductor devices according to embodiments of the present disclosure will be described below with reference to the drawings. Note that the present disclosure is not limited to these examples, but is defined by the claims, and is intended to include all modifications within the meaning and scope of the claims.

[0013] (First embodiment) Fig. 1 is a cross-sectional view of a module on which a semiconductor device according to the first embodiment is mounted. Fig. 2 is a plan view of the semiconductor device according to the first embodiment. Fig. 1 corresponds to the AA cross section of Fig. 2. Fig. 2 is a perspective view of sealing portion 28. The thickness direction of base portion 21 is defined as the Z direction, the direction from leads 23a to 23b as the X direction, and the direction perpendicular to the X and Z directions as the Y direction.

[0014] As shown in FIGS. 1 and 2 , the semiconductor device 100 according to the first embodiment includes a semiconductor chip 10, a lead frame 20, bonding wires 18a and 18b, and a sealing portion 28. The semiconductor chip 10 includes a substrate 11 and electrodes 12 to 14. The substrate 11 includes, for example, a substrate and a semiconductor layer disposed on the substrate. The electrodes 12 and 13 are disposed on the upper surface of the substrate 11 and are, for example, an input electrode and an output electrode, respectively. The electrode 14 is disposed on the lower surface of the substrate 11 and is supplied with a reference potential such as a ground potential. The substrate 11 includes an active element 15 that handles high-frequency signals. The active element 15 is, for example, a transistor. If the active element 15 is a FET (field effect transistor), the electrodes 12, 13, and 14 are a gate electrode, a drain electrode, and a source electrode, respectively. If the active element 15 is a GaN HEMT (gallium nitride high electron mobility transistor), the substrate 11 is, for example, a silicon carbide (SiC) substrate. When the active element 15 is a laterally diffused metal oxide semiconductor (LDMOS), the substrate 11 is, for example, a silicon (Si) substrate.

[0015] The lead frame 20 includes a base portion 21 and leads 22, 23a, and 23b. The semiconductor chip 10 is bonded to the upper surface of the base portion 21 with a bonding member 16 sandwiched therebetween. The base portion 21 is provided with holes 50 penetrating the base portion 21. A plurality of holes 50 are provided corresponding to the plurality of leads 22. Two leads 22 are connected to each of two sides of the base portion 21 facing each other in the X direction. Leads 23a and 23b are provided between the two leads 22 in the Y direction. The lead 22 is mechanically and electrically connected to the base portion 21. The lead 22 and the base portion 21 are at the same potential. The lead 23 is separated from the base portion 21. The lead 22 includes a terminal portion 24 and a connecting portion 25. The connecting portion 25 mechanically and electrically connects the terminal portion 24 to the base portion 21. Each of the leads 23a and 23b includes a terminal portion 24, a connecting portion 25, and a pad 26. The connection portions 25 mechanically and electrically connect the terminal portions 24 to the pads 26. The lead frame 20 is a metal plate such as a copper plate.

[0016] Bonding wire 18a electrically connects electrode 12 to pad 26 of lead 23a. Bonding wire 18b electrically connects electrode 12 to pad 26 of lead 23b. Bonding wires 18a and 18b are thin metal wires such as gold or aluminum wires. Bonding member 16 is a brazing material such as gold-tin.

[0017] Sealing portion 28 seals semiconductor chip 10, lead frame 20, and bonding wires 18a and 18b. The lower surface of base portion 21 is exposed from the lower surface of sealing portion 28, and the upper surfaces of terminal portions 24 are exposed from the upper surface of sealing portion 28. Sealing portion 28 is, for example, a resin layer such as an epoxy resin layer.

[0018] The module 100A includes a heat dissipation member 30 and a circuit board 40. The heat dissipation member 30 is made of a material with high thermal conductivity, such as copper. The semiconductor device 100 is joined onto the heat dissipation member 30 with a joining member 32 sandwiched therebetween. The joining member 32 is made of a material with high thermal conductivity, such as a thermally conductive sheet, and is an insulator.

[0019] The circuit board 40 includes a substrate 41, conductive layers 42, 42a, and 43, and a via wiring 45. The conductive layers 42 and 42a are provided on the lower surface of the substrate 41, and the conductive layer 43 is provided on the upper surface of the substrate 41. The via wiring 45 penetrates the substrate 41 and electrically connects the conductive layers 42 and 43. The conductive layers 42 and 43 are at the same potential. The conductive layer 42a is electrically isolated from the conductive layer 43. The conductive layers 42 and 42a are joined to the terminal portion 24 via a joining member 46. The circuit board 40 is, for example, a PCB (Printed Circuit Board). The substrate 41 is a dielectric substrate, and is, for example, a resin layer such as FR-4 (Flame Retrdant Type 4) or a ceramic layer. The conductive layers 42, 42a, and 43 and the via wiring 45 are, for example, metal layers such as copper layers. The joining member 46 is electrically conductive and is, for example, a brazing material such as solder.

[0020] An example in which the module 100A is an amplifier circuit will be described. For example, when the module 100A is used in a mobile communication base station, the module 100A amplifies a high-frequency signal between 0.5 GHz and 20 GHz. The high-frequency signal passes through the conductor layer 42a, the lead 23a, and the bonding wire 18a and is input to the electrode 12. The high-frequency signal amplified by the active element 15 passes through the bonding wire 18b and the lead 23b from the electrode 13 and is output to the circuit board 40. A reference potential such as a ground potential is supplied to the conductor layer 43. The reference potential is supplied to the electrode 14 via the via wiring 45, the conductor layer 42, the lead 22, and the base portion 21.

[0021] In the semiconductor device 100 of the first embodiment, heat generated in the semiconductor chip 10 passes through the base portion 21 and the bonding member 32 and is dissipated from the heat dissipation member 30. Meanwhile, electrical signals input to or output from the semiconductor chip 10 are input to or output from the leads 23a and 23b to the circuit board 40. In this way, heat dissipation from the semiconductor chip 10 occurs from the negative direction in the Z direction, and electrical connection with the semiconductor chip 10 occurs from the positive direction in the Z direction.

[0022] (First Comparative Example) Fig. 3 is a cross-sectional view of a module on which a semiconductor device according to Comparative Example 1 is mounted. Fig. 4 is a plan view of the semiconductor device according to Comparative Example 1. Fig. 3 corresponds to the AA cross section of Fig. 4.

[0023] 3 and 4, in the semiconductor device 110 and module 110A according to the first comparative example, the base portion 21, the leads 22, and the leads 23a and 23b are exposed from the lower surface of the sealing portion 28. The base portion 21 and the leads 22 are joined to the conductive layer 42 of the circuit board 40 with the bonding member 46 sandwiched therebetween. The leads 23a and 23b are joined to the conductive layer 42a of the circuit board 40 with the bonding member 46 sandwiched therebetween.

[0024] In module 110A, heat is dissipated from the semiconductor chip 10 in the negative Z direction, and electrical connection with the semiconductor chip 10 is also made in the negative Z direction. Heat generated in the semiconductor chip 10 is dissipated through the base portion 21, the bonding member 46, and the circuit board 40, as indicated by arrow 60. The circuit board 40 is provided with a substrate 41, which is a dielectric substrate, and has high thermal resistance. This results in poor heat dissipation.

[0025] On the other hand, in the module 100A of the first embodiment, as shown in FIG. 1, electrical connection and heat dissipation are performed in opposite directions. That is, the lower surface 21a (first surface) of the base portion 21 facing the negative direction (first direction) in the Z direction is thermally connected to the heat dissipation member 30. The upper surface 24a (second surface) of the terminal portion 24 of the lead 22 facing the positive direction (second direction opposite to the first direction) in the Z direction is connected to the reference potential. The semiconductor chip 10 is mounted on the upper surface 21b (third surface) of the base portion 21 facing the positive direction in the Z direction. This allows the lower surface 21a of the base portion 21 to be thermally connected to the heat dissipation member 30 via the bonding member 32. As a result, heat generated in the semiconductor chip 10 is dissipated from the base portion 21 to the heat dissipation member 30 as indicated by arrow 61. This improves heat dissipation compared to the module 110A of the first comparative example.

[0026] (Second Comparative Example) Fig. 5 is a cross-sectional view of a module on which a semiconductor device according to Comparative Example 2 is mounted. Fig. 6 is a plan view of the semiconductor device according to Comparative Example 2. Fig. 5 corresponds to the AA cross section of Fig. 6.

[0027] 5 and 6, in the semiconductor device 112 and module 112A according to the second comparative example, no hole 50 is provided in the base portion 21. The other structures are the same as those in the first embodiment shown in FIGS.

[0028] In the second comparative example, similar to the first embodiment, the use of the heat dissipation member 30 improves heat dissipation from the semiconductor chip 10. However, the reference potential is supplied to the base portion 21 through the leads 22. Therefore, if the number of leads 22 is small or the leads 22 are thin, electrical impedance such as parasitic inductance between the electrodes 14 of the semiconductor chip 10 and ground increases. In this case, the electrodes 14 of the semiconductor chip 10 cannot be sufficiently grounded. Because the semiconductor chip 10 handles high-frequency signals, oscillation or degradation of high-frequency characteristics occurs. Therefore, the number of leads 22 is increased or the leads 22 are thickened. This reduces the electrical impedance of the leads 22 and therefore the electrical impedance between the electrodes 14 and ground.

[0029] Heat generated in the semiconductor chip 10 is released from the base 21 to the heat dissipation member 30 as indicated by arrow 61. Some of the heat is conducted through the base 21 and leads 22 as indicated by arrow 62 and released from the circuit board 40. If a large amount of heat is conducted through the leads 22, the temperatures of the bonding members 46 and the circuit board 40 rise. If the bonding members 46 are solder, an increase in the temperature of the bonding members 46 will cause deterioration of the bonding members 46. Furthermore, an increase in the temperature of the circuit board 40 may cause deterioration of the circuit board 40. In this way, if the thermal impedance between the electrodes 14 and the circuit board 40 decreases, the bonding members 46 or the circuit board 40 may deteriorate.

[0030] As described above, it is necessary to reduce the electrical impedance of the lead 22 and increase the thermal impedance of the lead 22. However, there is a positive correlation between electrical impedance and thermal impedance, and it is difficult to achieve both low electrical impedance and high thermal impedance.

[0031] (Simulation 1) A simulation was performed to determine whether the holes 50 affect heat conduction. FIG. 7 is a plan view of the semiconductor device in Simulation 1. As shown in FIG. 7, a lead 22 connected to a base portion 21 and a lead 23 not connected to the base portion 21 are provided. Semiconductor chips 10a to 10c and passive element chips 35a to 35c are mounted on the base portion 21. The underside of the base portion 21 is joined to a copper heat dissipation member 30 using a thermally conductive sheet as a joining member 32. The terminal portions 24 of the leads 22 are joined to a PCT substrate as a circuit board 40 using tin-silver-copper solder. The lead frame 20 is a copper plate, the semiconductor chips 10a to 10c are silicon carbide substrates, and the passive element chips 35a to 35c are gallium arsenide substrates.

[0032] The lead 22a is the lead closest to the semiconductor chip 10a. A plurality of holes 50 were provided between the lead 22a and the semiconductor chip 10a. The width of the holes 50 in the X direction was 0.2 mm, and the width in the Y direction was 0.4 mm. Simulations were performed on a sample without holes 50, a sample with five holes 50 arranged in the X direction, and a sample with seven holes 50 arranged in the X direction. In Figure 7, seven holes 50 are provided.

[0033] A constant amount of heat was supplied from the top surface of the semiconductor chip 10a as a heat source, and the temperature of the top surface of the semiconductor chip 10a and the temperature of the top surface of the pad 26 were simulated with the ambient temperature set to 100°C.

[0034] Table 1 shows the simulation results.

[0035] [Table 1]

[0036] As shown in Table 1, the temperature of the top surface of the semiconductor chip 10a is 1°C higher and the temperature of the top surface of the terminal portion 24 is 2°C lower in the samples with five and seven holes 50 compared to the sample without holes 50. A joining member 46 such as solder is joined to the top surface of the terminal portion 24. Therefore, the temperature of the joining member 46 can be lower in the samples with five and seven holes 50 compared to the sample without holes 50. This is thought to be because the holes 50 increase the thermal impedance from the base portion 21 to the terminal portion 24 of the lead 22a.

[0037] (Simulation 2) A simulation was conducted to determine whether the holes 50 affect high-frequency characteristics. In Simulation 2, four holes 50 were provided in the center of a 1 mm wide line in the longitudinal direction of the line. The holes 50 were 0.4 mm long and 0.2 mm wide. The longitudinal direction of the holes 50 was set to the longitudinal direction of the line. The four holes 50 were arranged in the width direction of the line. The reflection characteristics S11 and transmission characteristics S21 of the line with and without holes were simulated.

[0038] Fig. 8 is a diagram showing S11 versus frequency in Simulation 2. Fig. 9 is a diagram showing S21 versus frequency in Simulation 2. The vertical axis of Fig. 8 represents the absolute value of S11 in dB, and the vertical axis of Fig. 9 represents the absolute value of S21 in dB. As shown in Figs. 8 and 9, even when a hole 50 is provided in the line, the high-frequency characteristics of S11 and S21 do not change by 1 dB or more.

[0039] The reason why the holes 50 do not affect the high-frequency characteristics is explained below. Due to the skin effect, high-frequency current is concentrated on the surface of the line. Therefore, even if holes 50 are not provided, high-frequency current mainly flows near the surface of the line, with almost no current flowing in the center of the line. Therefore, even if holes 50 are provided in the line, the high-frequency current flows on the surface of the line and near the holes 50, and it is thought that the effect on the high-frequency characteristics is small. The skin effect is a phenomenon that occurs in high-frequency signals, and when the dimensions of the holes 50 are set to a realistic dimension of 0.1 mm or more and 1 mm or less, the fluctuation in the high-frequency characteristics is small at frequencies above 0.5 GHz and below 10 GHz, as shown in Figures 8 and 9.

[0040] (Description of the First Embodiment) As shown in FIG. 2 , in the semiconductor device 100 of the first embodiment, a hole 50 is provided penetrating the base portion 21 between a portion 65 (first portion) where the lead 22 (first lead) is connected to the base portion 21 and the semiconductor chip 10 (first semiconductor chip). As indicated by arrow 63a, heat reaching the hole 50 from the semiconductor chip 10 is blocked by the hole 50. Therefore, as indicated by arrow 63b, the amount of heat conducted through the lead 22 is smaller than the amount of heat conducted through the lead 22 in the second comparative example. Therefore, as shown in Simulation 1, the increase in temperature of the bonding member 46 and the circuit board 40 can be suppressed. Therefore, deterioration of the bonding member 46 and the circuit board 40 can be suppressed. Furthermore, as shown in Simulation 2, the hole 50 does not significantly affect the high-frequency characteristics. Therefore, deterioration of the high-frequency characteristics can be suppressed.

[0041] The upper surface (second surface) of the lead 22 is mounted on the circuit board 40 with solder sandwiched between them as the joining member 46. When the temperature of the solder rises, the joining member 46 is likely to deteriorate. Therefore, when solder is used as the joining member 46, holes 50 can be provided.

[0042] High-frequency signals are input to and output from the top surface of lead 23 (signal lead) facing the positive Z direction. Bonding wires 18a and 18b electrically connect lead 23 to semiconductor chip 10. This allows the supply of a reference potential and the input and output of high-frequency signals to be performed from the same direction, as shown in FIG.

[0043] (Modification 1 of the first embodiment) Fig. 10 is a plan view of a semiconductor device according to Modification 1 of the first embodiment. In Fig. 10, in order to explain the shapes and arrangements of the different holes 50a to 50d, different types of holes 50a to 50d are illustrated in one base portion 21. One base portion 21 may be provided with any one type of hole among the holes 50a to 50d, or may be provided with different types of holes.

[0044] In the semiconductor device 101 according to the first modification of the first embodiment, a plurality of holes 50a are provided between the leads 22a and the semiconductor chip 10, penetrating the base portion 21. The planar shape of the holes 50a is rectangular. The plurality of holes 50a cover the entire range 64a of the point 65a as seen from the semiconductor chip 10.

[0045] A plurality of holes 50b are provided between the leads 22b and the semiconductor chip 10, penetrating the base portion 21. The planar shape of the holes 50b is circular. The plurality of holes 50b completely cover an area 64b of the semiconductor chip 10 when the portion 65b is viewed from the semiconductor chip 10.

[0046] A single hole 50c is provided between the lead 22c and the semiconductor chip 10, penetrating the base portion 21. The planar shape of the hole 50c is a slit. The multiple holes 50c block the entire range 64c of the portion 65c when viewed from the semiconductor chip 10.

[0047] A hole 50d penetrating the base portion 21 is provided between the lead 22d and the semiconductor chip 10. The planar shape of the hole 50c is a slit. The multiple holes 50c do not block most of the range 64d when viewing the point 65d from the semiconductor chip 10.

[0048] When hole 50c blocks the entire area 64c, as in hole 50c, the thermal impedance can be increased. However, because hole 50c blocks high-frequency signals, high-frequency characteristics are likely to deteriorate. When hole 50d blocks only a small area of ​​area 64c, as in hole 50d, hole 50d is less likely to block high-frequency signals, but it is difficult to increase the thermal impedance.

[0049] Like the hole 50 in FIG. 2, multiple holes 50 are provided, and the multiple holes 50 block at least half of the range 64 when viewing the point 65 from the semiconductor chip 10. By providing multiple holes 50, high-frequency signals propagate through the holes 50, thereby suppressing degradation of high-frequency characteristics. On the other hand, the multiple holes 50 block at least half of the range 64. This increases the thermal impedance, thereby suppressing heat transfer through the leads 22. The multiple holes 50 may block at least three-quarters of the range 64.

[0050] Like the holes 50a and 50b in Figure 10, the holes 50a or 50b block all of the areas 64a and 64b, thereby providing a higher thermal impedance.

[0051] (Modification 2 of the first embodiment) FIG. 11 is a plan view of a semiconductor device according to Modification 2 of the first embodiment. As shown in FIG. 11, a semiconductor device 102 according to Modification 2 of the first embodiment has leads 22a and 22e. The leads 22a and 22e are connected to the base portion 21 at points 65a and 65e, respectively. The shortest distance La between the semiconductor chip 10 and point 65a is shorter than the shortest distance Le between the semiconductor chip 10 and point 65e. That is, the lead 22a (first lead) has the shortest distances La and Le between the semiconductor chip 10 and points 65a and 65e, respectively, among the multiple leads 22a and 22e. No hole 50 is provided between point 65e and the semiconductor chip 10. The other configurations are the same as those of the first embodiment, and therefore description thereof will be omitted.

[0052] Heat generated in the semiconductor chip 10 is mainly conducted through the base portion 21 and leads 22a between the portion 65a and the semiconductor chip 10. For this reason, the temperature of the bonding member 46 that is bonded to the lead 22a is likely to rise the most, and the bonding member 46 is most likely to deteriorate. Therefore, holes 50 are provided between the portion 65a of the lead 22a and the semiconductor chip 10. This makes it possible to suppress the heat conducted through the lead 22a, which is the most susceptible to heat conduction, and therefore to suppress the temperature rise of the bonding member 46 that is bonded to the lead 22a.

[0053] The distance Le between the semiconductor chip 10 and a point 65e (second point) where the lead 22e (second lead) is connected to the base portion 21 is longer than the distance La between the point 65a (first point) and the semiconductor chip 10. Therefore, the temperature of the bonding member 46 that bonds to the lead 22e is less likely to rise. Therefore, it is not necessary to provide a hole 50 between the point 65e and the semiconductor chip 10. This makes it possible to reduce the electrical impedance between the lead 22e and the semiconductor chip 10. Therefore, it is possible to improve the high-frequency characteristics. The distance Le is, for example, 1.2 times or more, or even 2 times or more, the distance La.

[0054] (Modification 3 of the first embodiment) FIG. 12 is a plan view of a semiconductor device according to Modification 3 of the first embodiment. As shown in FIG. 12, in a semiconductor device 103 according to Modification 3 of the first embodiment, a passive element chip 35 is mounted on the upper surface of a base portion 21. The passive element chip 35 has passive elements such as capacitors, inductors, and transmission lines, but does not have active elements such as transistors. Bonding wires 18c and 18a are connected to the passive element chip 35. At least a portion of the passive element chip 35 is located between the semiconductor chip 10 and a portion 65f (third portion) where the lead 22f (third lead) is connected to the base portion 21. The other configurations are the same as those of the first embodiment, and therefore description thereof will be omitted.

[0055] In the region of the base portion 21 where the passive element chip 35, which generates a small amount of heat, is provided, heat flows to the passive element chip 35. As a result, the amount of heat that reaches the leads 22f from the semiconductor chip 10 is reduced. Therefore, the temperature of the bonding member 46 that bonds to the leads 22f is unlikely to rise. Therefore, it is not necessary to provide a hole 50 between the portion 65f and the semiconductor chip 10. This makes it possible to reduce the electrical impedance between the leads 22f and the semiconductor chip 10. Therefore, it is possible to improve high-frequency characteristics.

[0056] The shortest distance Lf between the point 65f and the semiconductor chip 10 may be equal to or less than the shortest distance La between the point 65a and the semiconductor chip 10. In this case, if the passive element chip 35 is not provided, the temperature of the bonding member 46 bonded to the lead 22f becomes high. When the passive element chip 35 is provided as in the third modification of the first embodiment, the temperature of the bonding member 46 bonded to the lead 22f is unlikely to become high even if the distance Lf is equal to or less than the distance La.

[0057] The passive element chip 35 may block the imaginary line connecting the point 65f and the semiconductor chip 10 at the shortest distance Lf. This reduces the heat that reaches the lead 22f from the semiconductor chip 10, making it unnecessary to provide the hole 50.

[0058] (Fourth modification of the first embodiment) FIG. 13 is a plan view of a semiconductor device according to Modification 4 of the first embodiment. As shown in FIG. 13, in a semiconductor device 104 according to Modification 4 of the first embodiment, a semiconductor chip 10a (second semiconductor chip) is mounted on the upper surface of a base portion 21. The semiconductor chip 10a includes a substrate 11, electrodes 12 and 13, and an active element 15 that handles high-frequency signals. A portion 65g (fourth portion) of the lead 22g (fourth lead) that is connected to the base portion 21 is closest to the semiconductor chip 10a. No hole 50 is provided between the portion 65g where the lead 22g is connected to the base portion 21 and the semiconductor chip 10a. The other configurations are the same as those of Modification 2 of the first embodiment, and therefore description thereof will be omitted.

[0059] The semiconductor chip 10a generates a small amount of heat. Therefore, the temperature of the bonding member 46 bonded to the lead 22g is unlikely to rise. Therefore, it is not necessary to provide the hole 50 between the portion 65g and the semiconductor chip 10a. This reduces the electrical impedance between the lead 22g and the semiconductor chip 10. This improves the high-frequency characteristics. The shortest distance Lg between the portion 65g and the semiconductor chip 10 may be equal to or less than the shortest distance La between the portion 65a and the semiconductor chip 10. Even in this case, the temperature of the bonding member 46 bonded to the lead 22g is unlikely to rise.

[0060] (Second embodiment) Fig. 14 is a plan view of the semiconductor device according to the second embodiment. As shown in Fig. 14, in the semiconductor device 105 according to the second embodiment, the base portion 21 does not have a hole 50, but the connection portion 25 of the lead 22 has a hole 50. The other configuration is the same as that of the first embodiment, and therefore a description thereof will be omitted.

[0061] According to the second embodiment, as indicated by arrow 63a, heat that passes from the semiconductor chip 10 through the base portion 21 and leads 22 to the hole 50 is blocked by the hole 50. Therefore, as indicated by arrow 63b, the amount of heat conducted through the leads 22 after the hole 50 is smaller than the amount of heat conducted through the leads 22 in the second comparative example. Therefore, as in Simulation 1, the increase in temperature of the bonding member 46 and the circuit board 40 can be suppressed, and deterioration of the bonding member 46 and the circuit board 40 can be suppressed. Furthermore, as indicated by Simulation 2, the hole 50 does not have much effect on high-frequency characteristics. Therefore, deterioration of high-frequency characteristics can be suppressed.

[0062] A plurality of holes 50 are arranged in the width direction (Y direction) of the lead 22. High-frequency signals propagate through the holes 50, thereby suppressing degradation of high-frequency characteristics. The total width of the holes 50 in the Y direction can be set to ½ or more of the width W of the lead 22 in the Y direction. This increases thermal impedance. The total width of the plurality of holes 50 in the Y direction may be ¾ or more of the width W1.

[0063] (Modification 1 of the second embodiment) Fig. 15 is a plan view of a semiconductor device according to Modification 2 of the first embodiment. As shown in Fig. 15, in a semiconductor device 106 according to Modification 1 of the first embodiment, holes 50 are not provided in the base portion 21 and the leads 22e, but holes are provided in the leads 22a. The other configurations are the same as those of Modification 2 of the first embodiment, and therefore description thereof will be omitted.

[0064] Heat generated in the semiconductor chip 10 is mainly conducted through the lead 22a, which has a short distance La. Therefore, a hole 50 is provided in the lead 22a (first lead). This makes it possible to suppress a rise in temperature of the bonding member 46, which is bonded to the lead 22a, through which heat is most easily conducted.

[0065] The distance Le is longer than the distance La. Therefore, the temperature of the joining member 46 that joins the lead 22e is less likely to become high. Therefore, it is not necessary to provide the hole 50 in the lead 22e (second lead). This makes it possible to lower the electrical impedance of the lead 22e. Therefore, it is possible to improve the high-frequency characteristics.

[0066] (Modification 2 of the second embodiment) Fig. 16 is a plan view of a semiconductor device according to Modification 2 of the second embodiment. As shown in Fig. 16, in a semiconductor device 107 according to Modification 2 of the second embodiment, holes 50 are not provided in the base portion 21 and the leads 22f, but holes are provided in the leads 22a. The other configurations are the same as those of Modification 3 of the first embodiment, and therefore description thereof will be omitted.

[0067] Since the passive element chip 35 is provided between the portion 65f and the semiconductor chip 10, the temperature of the bonding member 46 that bonds to the lead 22f is unlikely to become high. Therefore, it is not necessary to provide the hole 50 in the lead 22f (third lead). This makes it possible to reduce the electrical impedance of the lead 22f. As a result, it is possible to improve the high-frequency characteristics.

[0068] (Modification 3 of the second embodiment) Fig. 17 is a plan view of a semiconductor device according to Modification 3 of the second embodiment. As shown in Fig. 17, in a semiconductor device 108 according to Modification 3 of the second embodiment, holes 55 are not provided in the base portion 21 and leads 22f and 22g, but a hole is provided in the lead 22a. The other configurations are the same as those in Modification 4 of the first embodiment, and therefore description thereof will be omitted.

[0069] In the semiconductor chip 10a with a small amount of heat generation, the temperature of the bonding member 46 that bonds to the lead 22g is unlikely to rise because the amount of heat generated is small. Therefore, the hole 50 does not need to be provided in the lead 22g (fourth lead). This makes it possible to lower the electrical impedance of the lead 22g. This improves the high-frequency characteristics.

[0070] (Third embodiment) The third embodiment is an example of an amplifier device having a Doherty amplifier used in a mobile communication base station. FIG. 18 is a block diagram of a semiconductor device according to the third embodiment. As shown in FIG. 18, a semiconductor device 109 includes amplifiers 71, 75a, and 75b, matching circuits 70, 72, 74a, 74b, 76a, and 76b, a divider 73, and a combiner 77. The semiconductor device 109 is a two-stage amplifier device. A high-frequency signal input from an input terminal Tin is amplified by the amplifier 71, further amplified by amplifiers 75a and 75b, and output from an output terminal Tout.

[0071] The matching circuit 70 is mounted on the passive element chip 35c, the matching circuits 72, 74a, and 74b and the divider 73 are mounted on the passive element chip 35a, and the matching circuits 76a and 76b and the combiner 77 are mounted on the passive element chip 35b. The amplifiers 75a, 75b, and 71 are, for example, transistors, such as FETs, and are mounted on the semiconductor chips 10a to 10c, respectively. The amplifier 71 is a driver amplifier. The amplifiers 75a and 75b are power amplifiers and Doherty amplifiers. The amplifier 75a is a main amplifier, and the amplifier 75b is a peak amplifier.

[0072] A signal Sin input to input terminal Tin is input to amplifier 71 via matching circuit 70. Matching circuit 70 matches the impedance seen from input terminal Tin at matching circuit 70 with the impedance seen from matching circuit 70 at amplifier 71. Matching circuit 70 supplies a gate bias to amplifier 71 from bias terminal Tg1. Amplifier 71 amplifies signal Sin and outputs the amplified signal to distributor 73 via matching circuit 72. Matching circuit 72 matches the impedance seen from amplifier 71 at matching circuit 72 with the impedance seen from matching circuit 72 at distributor 73. Matching circuit 72 supplies a drain bias to amplifier 71 from bias terminal Td1. Distributor 73 distributes the signal amplified by amplifier 71 into signals S1 and S2.

[0073] Signal S1 is input to amplifier 75a via matching circuit 74a. Matching circuit 74a matches the impedance seen from distributor 73 at matching circuit 74a with the impedance seen from matching circuit 74a at amplifier 75a. Matching circuit 74a supplies a gate bias to amplifier 75a from bias terminal Tg2a. Amplifier 75a amplifies signal S1 and outputs the amplified signal S3 to combiner 77 via matching circuit 76a. Matching circuit 76a matches the impedance seen from amplifier 75a at matching circuit 76a with the impedance seen from matching circuit 76a at combiner 77. Matching circuit 76a supplies drain bias to amplifiers 75a and 75b from bias terminal Td2.

[0074] Signal S2 is input to amplifier 75b via matching circuit 74b. Matching circuit 74b matches the impedance seen from distributor 73 at matching circuit 74b with the impedance seen from matching circuit 74b at amplifier 75b. Matching circuit 73a supplies a gate bias to amplifier 75b from bias terminal Tg2b. Amplifier 75b amplifies signal S2 and outputs the amplified signal S4 to combiner 77 via matching circuit 76b. Matching circuit 76b matches the impedance seen from amplifier 75b at matching circuit 76b with the impedance seen from matching circuit 76b at combiner 77. Combiner 77 combines signals S3 and S4 and outputs the combined signal as output signal Sout to output terminal Tout.

[0075] In the Doherty amplifier, when the input power of the input signal Sin is low, amplifier 75a, which is the main amplifier, mainly amplifies the signal. When the input power of the input signal Sin is high, amplifier 75a and amplifier 75b, which is the peak amplifier, amplify the signal. Therefore, the amount of heat generated by amplifier 75a is greater than that of amplifier 75b.

[0076] 19 is a plan view of a semiconductor device according to the third embodiment. In FIG. 19, the sealing portion 28 is shown in a see-through manner. As shown in FIG. 19, in a semiconductor device 109, semiconductor chips 10a to 10c and passive element chips 35a to 35c are mounted on a base portion 21. Leads 22 and 23 are provided on the sealing portion 28. Lead 23 corresponds to the input terminal Tin, output terminal Tout, and bias terminals Tg1, Td1, Tg2a, Tg2b, and Td2 in FIG. 18.

[0077] The bonding wire 18d electrically connects the input terminal Tin to the passive element chip 35c. The bonding wire 18e electrically connects the passive element chip 35c to the semiconductor chip 10c. The bonding wire 18f electrically connects the semiconductor chip 10c to the passive element chip 35a. The bonding wire 18g electrically connects the passive element chip 35a to the semiconductor chip 10a. The bonding wire 18h electrically connects the semiconductor chip 10a to the passive element chip 35b. The bonding wire 18i electrically connects the passive element chip 35a to the semiconductor chip 10b. The bonding wire 18j electrically connects the semiconductor chip 10b to the passive element chip 35b. The bonding wire 18k electrically connects the passive element chip 35b to the output terminal Tout. The bonding wire 18l electrically connects the bias terminal Tg1 to the passive element chip 35c. Bonding wires 18m, 18n, and 18o electrically connect the bias terminals Td1, Tg2a, and Tg2b to the passive element chip 35a, and bonding wire 18p electrically connects the bias terminal Td2 to the passive element chip 35b.

[0078] Of the semiconductor chips 10a to 10c, the chip that generates the most heat is the semiconductor chip 10a that has the main amplifier. Therefore, a hole 50 is provided between the semiconductor chip 10a and a portion 65a of the lead 22a that is closest to the semiconductor chip 10a. This makes it possible to suppress the temperature rise at the terminal portion 24 of the lead 22a. The semiconductor chip 10b that has the peak amplifier does not generate as much heat as the semiconductor chip 10a. Therefore, a hole 50 is not provided between the semiconductor chip 10b and a portion 65g of the lead 22g that is closest to the semiconductor chip 10b. This makes it possible to suppress the deterioration of high-frequency characteristics.

[0079] (Modification 1 of the third embodiment)

[0080] Fig. 20 is a plan view of a semiconductor device according to Modification 1 of the third embodiment. Fig. 20 shows the sealing portion 28 in a see-through manner. As shown in Fig. 20, in a semiconductor device 109A according to Modification 1 of the third embodiment, holes 50 are not provided in the base portion 21, but holes 50 are provided in the leads 22a. The other configurations are the same as those of the third embodiment, and therefore description thereof will be omitted.

[0081] A hole 50 is provided in the lead 22a that is closest to the semiconductor chip 10a that has the main amplifier that generates the most heat. This makes it possible to suppress the temperature rise at the terminal portion 24 of the lead 22a. No hole is provided in the lead 22g that is closest to the semiconductor chip 10b that has the peak amplifier that generates the least heat. This makes it possible to suppress the deterioration of high-frequency characteristics.

[0082] In the first embodiment, its modifications, and the third embodiment, an example has been described in which the hole 50 is provided between the portion 65a of the base portion 21 and the semiconductor chip 10a, and in the second embodiment, its modifications, and Modification 1 of the third embodiment, an example has been described in which the hole 50 is provided in the lead 22a. The hole 50 may be provided both between the portion 65a of the base portion 21 and the semiconductor chip 10a and in the lead 22a.

[0083] The embodiments disclosed herein should be considered to be illustrative and not restrictive in all respects. The scope of the present disclosure is defined by the claims, not by the meaning described above, and is intended to include all modifications within the meaning and scope equivalent to the claims. [Explanation of symbols]

[0084] 10 (first semiconductor chip), 10a (first semiconductor chip), 10b (second semiconductor chip), 10c: semiconductor chip 11, 41: Substrate 12, 13, 14: Electrode 15: Active element 16: Joint material 18a, 18b, 18c, 18d, 18e, 18f, 18g, 18h, 18i, 18k, 18l, 18m, 18n, 18o, 18p: Bonding wire 20: Lead frame 21: Base section 21a (first surface): bottom surface of base 21b (third surface): top surface of base 22 (1st lead), 22a (1st lead), 22b, 22c, 22d, 22e (2nd lead), 22f (3rd lead), 22g (4th lead), 23, 23a, 23b 24:Terminal section 24a (2nd surface): Top surface of terminal 25: Connection 26: Pad 28: Sealing part 30: Heat dissipation material 32: Joint material 35, 35a, 35b, 35c: passive element chip 40: Circuit board 42, 42a, 43: Conductor layer 45: Via wiring 46: Joint material 50, 50a, 50b, 50c, 50d: Hole 60, 61, 62, 63a, 63b: Arrows 64, 64a, 64b, 64c, 64d: Range 65 (1st place), 65a (1st place), 65b, 65c, 65d, 65e (2nd place), 65f (3rd place), 65g (4th place): place 70, 72, 74a, 74b, 76a, 76b: matching circuit 71, 75a, 75b: Amplifiers 73:Distributor 77: Synthesizer 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 109A, 110, 112: semiconductor device 100A, 112A, 114A: Module

Claims

1. a base portion having a first surface facing a first direction and connected to a heat dissipation member; a first lead to which a reference potential is supplied from a second surface facing a second direction opposite to the first direction and which is electrically connected to the base portion; a first semiconductor chip mounted on a third surface of the base portion facing the second direction and having an active element for handling high frequency signals; Equipped with The semiconductor device has a hole formed in the base portion between the first semiconductor chip and a first location where the first lead is connected to the base portion.

2. The semiconductor device according to claim 1 , wherein a plurality of the holes are provided, and the plurality of holes cover at least half of the range of the first location as seen from the first semiconductor chip.

3. the reference potential is supplied from the surface facing the second direction, the reference potential is electrically connected to the base portion, and the reference potential is supplied from the surface facing the second direction; and the reference potential is supplied from the surface facing the second direction. The ...

3. The semiconductor device according to claim 1, wherein the first lead has a shortest distance between a portion of the plurality of leads connected to the base portion and the first semiconductor chip.

4. the plurality of leads includes a second lead; a distance between a second location where the second lead is connected to the base portion and the first semiconductor chip is longer than a distance between the first location and the first semiconductor chip; 4. The semiconductor device according to claim 3, wherein no hole is provided between the second location and the first semiconductor chip, the hole penetrating the base portion.

5. a passive element chip mounted on the third surface, the passive element chip having a passive element but no active element; the plurality of leads includes a third lead; at least a portion of the passive element chip is located between the first semiconductor chip and a third location where the third lead is connected to the base portion; 4. The semiconductor device according to claim 3, wherein no hole penetrating the base portion is provided between the third location and the first semiconductor chip.

6. a second semiconductor chip mounted on the third surface and having an active element for handling high frequency signals; 4. The semiconductor device according to claim 3, wherein a fourth lead, the part of the plurality of leads whose connection to the base portion is closest to the second semiconductor chip, has no hole penetrating the base portion between the fourth point where the fourth lead is connected to the base portion and the second semiconductor chip.

7. the first semiconductor chip has a main amplifier of a Doherty amplifier; The semiconductor device according to claim 6 , wherein the second semiconductor chip includes a peak amplifier of the Doherty amplifier.

8. a base portion having a first surface facing a first direction and connected to a heat dissipation member; a first lead to which a reference potential is supplied from a second surface facing a second direction opposite to the first direction and which is electrically connected to the base portion; a first semiconductor chip mounted on a third surface of the base portion facing the second direction and having an active element for handling high frequency signals; Equipped with The semiconductor device has a hole penetrating the first lead.

9. the reference potential is supplied from the surface facing the second direction, the reference potential is electrically connected to the base portion, and the reference potential is supplied from the surface facing the second direction; and the reference potential is supplied from the surface facing the second direction. The ... The semiconductor device according to claim 8 , wherein the first lead has a shortest distance between a portion of the plurality of leads connected to the base portion and the first semiconductor chip.

10. the plurality of leads includes a second lead; a distance between a second location where the second lead is connected to the base portion and the first semiconductor chip is longer than a distance between a first location where the first lead is connected to the base portion and the first semiconductor chip; The semiconductor device according to claim 9 , wherein no hole is provided through the second lead.

11. a passive element chip mounted on the third surface, the passive element chip having a passive element but no active element; the plurality of leads includes a third lead; at least a portion of the passive element chip is located between the first semiconductor chip and a third location where the third lead is connected to the base portion; 11. The semiconductor device according to claim 9, wherein no hole is provided through the third lead.

12. a second semiconductor chip mounted on the third surface and having an active element for handling high frequency signals; 11. The semiconductor device according to claim 9, wherein a hole is not provided through a fourth lead, of the plurality of leads, whose portion connected to the base portion is closest to the second semiconductor chip.

13. the first semiconductor chip has a main amplifier of a Doherty amplifier; The semiconductor device according to claim 12 , wherein the second semiconductor chip includes a peak amplifier of the Doherty amplifier.

14. 11. The semiconductor device according to claim 1, wherein the second surface is mounted on a circuit board via solder.

15. a signal lead through which a high frequency signal is input or output from the surface facing the second direction; a bonding wire that electrically connects the signal lead and the first semiconductor chip; The semiconductor device according to claim 1 , 2 , or 8 to 10 , comprising:

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