Voltage-current conversion circuit and semiconductor integrated circuit

Abstract

To provide a voltage-current conversion circuit with the accuracy improved while the increase in area and consumption current is suppressed.SOLUTION: A V / I conversion circuit 200 converts an input voltage VIN input to an input terminal IN into an output current IOUT. An NMOS transistor MN1 is a native element and a first resistor R1 is connected between the ground and a source of the NMOS transistor MN1. A voltage dividing circuit 210 includes a second resistor R2 and a third resistor R3 connected in series between the input terminal IN and the ground. A voltage Vg resulting from the division of the input voltage VIN is supplied to a gate of the NMOS transistor.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a voltage-to-current (V / I) conversion circuit. [Background technology]

[0002] A V / I conversion circuit is used to convert a voltage signal into a current signal. V / I conversion circuits are divided into open-loop types that use a source follower circuit and closed-loop types that use an operational amplifier.

[0003] The open-loop type does not require an operational amplifier, so the circuit area can be made smaller, but it is easily affected by variations in the gate-source voltage of the transistor.

[0004] The closed-loop type has high accuracy, but requires an operational amplifier, which increases the circuit area and current consumption. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2008-26082

[0006] [overview] The present disclosure has been made in light of such a situation, and one exemplary purpose of an embodiment thereof is to provide a voltage-to-current conversion circuit with improved accuracy.

[0007] A semiconductor integrated circuit according to an embodiment of the present disclosure includes a voltage-to-current converter circuit including an input terminal for receiving an input voltage, an NMOS transistor as a native element, a first resistor connected between a source of the NMOS transistor and ground, and a voltage divider circuit including second and third resistors connected in series between the input terminal and ground, and for dividing the input voltage and supplying a voltage to the gate of the NMOS transistor.

[0008] Any combination of the above components, or mutual substitution of the components or expressions of the present disclosure between methods, devices, systems, etc., are also valid aspects of the present disclosure. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a circuit diagram of a semiconductor integrated circuit including a V / I conversion circuit according to an embodiment. [Figure 2] FIG. 2 is a circuit diagram of a V / I conversion circuit according to a comparative technique.

[0010] [Detailed explanation] (Outline of the embodiment) A summary of some exemplary embodiments of the present disclosure will be provided. This summary is intended to provide a basic understanding of one or more embodiments as a prelude to the detailed description that follows, and is not intended to limit the scope of the invention or disclosure. For convenience, the term "one embodiment" may refer to one embodiment (example or variant) or multiple embodiments (examples or variants) disclosed herein.

[0011] This summary is not an exhaustive overview of all possible embodiments, nor is it intended to identify key elements of all embodiments or delineate the scope of some or all aspects. Its sole purpose is to present some concepts of one or more embodiments in a simplified form as a prelude to the more detailed description that is presented later.

[0012] A voltage-to-current conversion circuit according to one embodiment includes an input terminal for receiving an input voltage, an NMOS transistor as a native element, a first resistor connected between a source of the NMOS transistor and ground, and a voltage divider circuit including second and third resistors connected in series between the input terminal and ground, which divides the input voltage and supplies the divided voltage to the gate of the NMOS transistor.

[0013] This configuration reduces the effect of process variations on the output current by using native elements, and also allows the temperature characteristics of the output current to be controlled according to the voltage division ratio of the voltage divider circuit.

[0014] In one embodiment, the temperature characteristic of the resistance value of the first resistor is X [ppm / °C], and the typical value of the threshold voltage (gate-source voltage) of the NMOS transistor is V gs(TYP) When the temperature coefficient of the threshold voltage is -Y [mV / ℃], the gate voltage Vg of the NMOS transistor is 0.9×Y / X+V gs(TYP) <Vg<1.1×Y / X+V gs(TYP) The voltage division ratio of the voltage divider circuit may be specified so as to satisfy the following equation: This makes it possible to significantly reduce the temperature dependency of the output current.

[0015] (Embodiment) Preferred embodiments will be described below with reference to the drawings. The same or equivalent components, parts, and processes shown in each drawing will be designated by the same reference numerals, and redundant descriptions will be omitted where appropriate. Furthermore, the embodiments are merely examples and do not limit the invention, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

[0016] In this specification, "a state in which component A is connected to component B" includes not only a case in which component A and component B are directly physically connected to each other, but also a case in which component A and component B are indirectly connected to each other via other components that do not substantially affect the electrical connection between them or that do not impair the function or effect achieved by their connection.

[0017] Similarly, "a state in which component C is provided between component A and component B" includes not only cases in which components A and C, or components B and C, are directly connected, but also cases in which they are indirectly connected via other components that do not substantially affect the electrical connection state between them or impair the functions or effects achieved by their combination.

[0018] 1 is a circuit diagram of a semiconductor integrated circuit 100 including a V / I conversion circuit 200 according to an embodiment. The semiconductor integrated circuit 100 includes a reference voltage source 110 and the V / I conversion circuit 200.

[0019] The V / I conversion circuit 200 converts the input voltage V supplied to the input terminal IN into IN , the output current I OUT and outputs it from the output terminal OUT. IN may be a reference voltage generated by the reference voltage source 110, or may be a variable voltage generated by a D / A converter or the like.

[0020] The V / I conversion circuit 200 includes a voltage divider circuit 210, a first resistor R1, an NMOS transistor MN1, and a current mirror circuit 220.

[0021] NMOS transistor MN1 is a native device. A native device is a transistor that is intermediate between enhancement mode and depletion mode and has a threshold voltage near zero. A native device is a transistor that is fabricated without doping in the channel region to adjust the threshold voltage, and is fabricated on a silicon substrate that is originally doped p-type without additional doping. A first resistor R1 is connected between the source of NMOS transistor MN1 and ground.

[0022] The voltage divider circuit 210 includes a second resistor R2 and a third resistor R3 connected in series between the input terminal IN and ground. IN The voltage Vg obtained by dividing the voltage V is supplied to the gate of the NMOS transistor MN1.

[0023] The current mirror circuit 220 includes PMOS transistors MP1 and MP2 whose gates and sources are connected in common. The current mirror circuit 220 controls a current I flowing through a first resistor R1 and an NMOS transistor MN1. R1 and the output current I OUT Source the.

[0024] The above is the configuration of the V / I conversion circuit 200. Next, the operation thereof will be described.

[0025] The gate voltage Vg of the NMOS transistor MN1 is expressed by the formula (1). Vg=R3 / (R2+R3)×V IN …(1) As will be described later, the voltage division ratio R3 / (R2+R3) of the voltage divider circuit 210 can be used as a parameter that defines the temperature characteristics of the V / I conversion circuit 200.

[0026] The source voltage Vs of the NMOS transistor MN1 is expressed by the formula (2). Vs=Vg-V gs =R3 / (R2+R3)×V IN -V gs …(2) V gs is the gate-source voltage of the NMOS transistor MN1.

[0027] The current flowing through the first resistor R1 and the NMOS transistor MN1 is expressed by equation (3). I R1 =Vs / R1=(R3 / (R2+R3)×V IN -V gs ) / R1 …(3)

[0028] When the current mirror ratio of the current mirror circuit 220 is α, the output current I OUT is expressed by equation (4). I OUT = α × I R1 =α×(R3 / (R2+R3)×V IN -V gs ) / R1 …(4)

[0029] The advantages of the V / I conversion circuit 200 become clear when compared with a comparative technique, which will now be described.

[0030] 2 is a circuit diagram of a V / I conversion circuit 200R according to a comparative technique. This V / I conversion circuit 200R is an open-loop type, similar to the V / I conversion circuit 200 of FIG. 1. The V / I conversion circuit 200R includes an NMOS transistor MN2, which is a normal non-native element, instead of the NMOS transistor MN1, which is a native element. The threshold voltage of the NMOS transistor MN2 is higher than the threshold voltage of the native element.

[0031] In addition, the V / I conversion circuit 200R does not include the voltage divider circuit 210, and the input voltage V IN is directly input to the gate of the NMOS transistor MN2.

[0032] The output current I of the V / I conversion circuit 200R OUT ' is expressed by equation (5). I OUT '=α×I R1 =α×(V IN -V gs ') / R1 …(5) V gs ' is the gate-source voltage of the NMOS transistor MN2.

[0033] The output current I in the V / I conversion circuit 200R of FIG. OUT The variation and temperature dependence of

[0034] Input voltage V IN The ideal 1.5V reference voltage V is temperature-dependent and has no variations. REF The gate-source voltage V of the NMOS transistor MN2 at room temperature is gs ' is set to 0.7V. If α=1, the output current I OUT(TYP) 'teeth, I OUT(TYP) '=(V REF -V gs ') / R1 =(1.5-0.7)V / 800kΩ=1μA is.

[0035] V gs The process variation of ' is ±0.1V, and the process variation of resistor R1 is ±10%. When the process variation is taken into account, the output current I OUT I OUT(TYP) The range will be between 79.5% and 125%.

[0036] Gate-source voltage V gs The temperature dependence of ' is -1.6mV / °. The source voltage Vs of NMOS transistor MN2 is V REF -V gs The temperature dependence of ' is V gs When =0.7V, -(-1.6mV / Vs)=1.6mV / (V REF -V gs )=1.6mV / 0.8V=+2000ppm / ℃.

[0037] Therefore, the output current I OUT The temperature dependence of ' is +1500ppm / ℃ for the temperature characteristic of resistor R1. (1+0.002) / (1+0.0015)-1=-0.000499=+499 ppm / ℃.

[0038] V gs Considering the variation of ±0.1V, V gs 785 ppm when V = 0.8 V - 0.1 V, gs When '=0.8V+0.1V, it becomes 0.785ppm. In other words, the fluctuation range is 277ppm to 785ppm.

[0039] Next, the output current I in the V / I conversion circuit 200 of FIG. OUT The variation and temperature dependence of

[0040] The gate-source voltage V of the native NMOS transistor MN1 gs is 0.15V at room temperature. The voltage division ratio of resistors R2 and R3 is gsThe output current I when the variation of OUT It is used as a parameter to define the temperature characteristics of V gs The output current I when the variation of OUT In order to make the temperature characteristics of R2=0.189MΩ R3=0.811MΩ The gate voltage Vg at room temperature without any variation is Vg=1.5V×0.811 / (0.189+0.811)=1.217V In addition, the source voltage Vs is Vg-V gs =1.217-0.15=1.067V. The output current I OUT To obtain (=1μA), set R1=1.067MΩ.

[0041] Native devices are not affected by variations in doping of the channel region during the manufacturing process, so the gate-source voltage V gs The variation of is smaller than that of non-native devices. Now, the gate-source voltage V gs The variation in the voltage is ±0.025V and the variation in the resistance value is ±10%. Because the pairing of resistors R2 and R3 can suppress the relative variation to a negligible level, R3 / (R2+R3) can be treated as a constant, and only the variation in resistor R1 needs to be considered.

[0042] Considering process variations, the output current I OUT I OUT(TYP) The variation ranges from 88.8% to 113.7% of the reference value. Comparing this with the comparison technology's 79.5% to 125%, it can be seen that the range of variation has been reduced to about half.

[0043] Gate-source voltage V gs The temperature dependency of the source voltage Vs of the NMOS transistor MN1 is set to -1.6 mV / °C. -(-1.6mV / Vs)=1.6mV / 1.067V=+1500ppm / ℃ This becomes:

[0044] Therefore, the output current I OUT The temperature dependence of resistor R1 is +1500 ppm / ℃. (1 + 0.0015) / (1 + 0.0015) - 1 = 0 ppm / °C. In other words, by optimizing the voltage division ratio of resistors R2 and R3, a flat temperature characteristic can be achieved.

[0045] Gate-source voltage V gs Considering the variation of ±0.025V, the output current I OUT It can be seen that the temperature characteristics of are within the range of ±40 ppm when process variations are taken into account, which is significantly smaller than the variation range of 277 ppm to 785 ppm in the comparison technology.

[0046] In this way, according to the V / I conversion circuit 200 of the embodiment, the output current I OUT Furthermore, by optimizing the voltage division ratio of the voltage divider circuit 210, the temperature dependency can be made extremely small.

[0047] In general, the temperature characteristic of the resistance value of the first resistor R1 is X [ppm / ℃], and the threshold voltage V of the NMOS transistor MN1, which is the native element, is gs A typical value of is V gs(TYP) , threshold voltage V gs When the temperature coefficient is -Y [mV / ℃], the gate voltage Vg of the NMOS transistor is Y / (Vg-V gs(TYP) )≒X …(6) It is enough to satisfy Vg=V REF ×R3 / (R2+R3), the voltage division ratio of the voltage divider circuit 210 is determined so as to satisfy the formula (6), and the output current I OUT The temperature characteristics can be suppressed.

[0048] Transforming equation (4) gives: Vg ≒ Y / X + Vgs(TYP) In practice, it is sufficient to satisfy a certain output current I OUT Since temperature fluctuations of 0.9×Y / X+V gs(TYP) <Vg<1.1×Y / X+V gs(TYP) The voltage division ratio may be determined so as to satisfy the following.

[0049] (Variation 1) In the embodiment, the voltage division ratio of the voltage divider circuit 210, i.e., the gate voltage Vg, is optimized to reduce temperature fluctuations, but the present disclosure is not limited to this. By adjusting the position of the gate voltage Vg, the output current I OUT can have any temperature dependence.

[0050] (Variation 2) In the embodiment, the output current I OUT Although the V / I conversion circuit 200 has been described as a source type, the present disclosure is also applicable to a sink type V / I conversion circuit. Specifically, the current mirror circuit 220 may be omitted, and the drain of the NMOS transistor MN1 may be used as the output terminal of the V / I conversion circuit 200. Alternatively, a current mirror circuit that folds back the output current of the current mirror circuit 220 may be added.

[0051] The embodiments described using specific terms merely illustrate the principles and applications of the present invention, and many modifications and changes in arrangement are permitted in the embodiments as long as they do not deviate from the spirit of the present invention as defined in the claims.

[0052] (Addendum) One aspect of the technology disclosed in this specification can be understood as follows.

[0053] (Item 1) an input terminal for receiving an input voltage; A native element NMOS transistor, a first resistor connected between the source of the NMOS transistor and ground; a voltage divider circuit including a second resistor and a third resistor connected in series between the input terminal and ground, which divides the input voltage and supplies the resulting voltage to the gate of the NMOS transistor; A voltage-to-current conversion circuit comprising:

[0054] (Item 2) The temperature characteristic of the resistance value of the first resistor is X [ppm / °C], and the typical value of the threshold voltage of the NMOS transistor is V gs(TYP) When the temperature coefficient of the threshold voltage is -Y [mV / °C], the gate voltage Vg of the NMOS transistor is 0.9×Y / X+V gs(TYP) <Vg<1.1×Y / X+V gs(TYP) 2. The voltage-current conversion circuit according to item 1, wherein a voltage division ratio of the voltage divider circuit is defined so as to satisfy the following.

[0055] (Item 3) 3. A semiconductor integrated circuit comprising the voltage-current conversion circuit according to item 1 or 2. [Explanation of symbols]

[0056] 100 Semiconductor Integrated Circuit 110 Reference voltage source 200 V / I conversion circuit MN1 NMOS transistor R1 First resistor R2 2nd resistor R3 3rd resistor 210 Voltage divider circuit 220 Current mirror circuit MP1, MP2 PMOS transistors

Claims

1. an input terminal for receiving an input voltage; a native element NMOS transistor; a first resistor connected between the source of the NMOS transistor and ground; a voltage divider circuit including a second resistor and a third resistor connected in series between the input terminal and ground, which divides the input voltage and supplies the resulting voltage to the gate of the NMOS transistor; A voltage-to-current conversion circuit comprising:

2. The temperature characteristic of the resistance value of the first resistor is X [ppm / °C], and the typical value of the threshold voltage of the NMOS transistor is V ｇｓ（ＴＹＰ） When the temperature coefficient of the threshold voltage is −Y [mV / ° C.], the gate voltage Vg of the NMOS transistor is 0.9×Y / X+V ｇｓ（ＴＹＰ） <Vg<1.1×Y / X+V ｇｓ（ＴＹＰ） 2. The voltage-to-current converter circuit according to claim 1, wherein a voltage division ratio of said voltage divider circuit is defined so as to satisfy the following:

3. A semiconductor integrated circuit comprising the voltage-current conversion circuit according to claim 1 or 2.

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