shunt regulator

Abstract

A shunt regulator is provided which can reduce a consumption current at the time of normal operation even if a circuit including a large current flowing at the time of operation is included. The shunt regulator includes a capacitor connected between an output terminal and a ground terminal, a voltage dividing circuit and an output transistor connected between the output terminal and the ground terminal, an error amplifier which controls the output transistor based on a voltage of an output terminal of the voltage dividing circuit and a reference voltage, a nonvolatile memory, a memory control circuit which outputs a read signal of data to the nonvolatile memory, and a voltage detection circuit which detects that the voltage of the output terminal reaches a prescribed voltage which allows a data read operation of the nonvolatile memory, outputs a detection signal to the memory control circuit, and an operation current of the nonvolatile memory is supplied from the capacitor.

Description

Technical Field

[0001] This invention relates to a shunt regulator. Background Technology

[0002] Figure 5 This is a circuit diagram representing a conventional shunt regulator.

[0003] Figure 5 The shunt regulator includes a reference voltage circuit 101, an error amplifier 102, an N-channel metal-oxide-semiconductor (NMOS) transistor 103, and voltage divider resistors R1 and R2.

[0004] If the shunt regulator has a power supply voltage Vin at input, a current flows through the external resistor 110, and the resulting output voltage Vout drives the load 111. If the current flowing through the external resistor 110 with resistance value R is set as Ir, the current flowing through the load 111 is set as Io, and the current flowing through the shunt regulator IC is set as Ic, then the output voltage Vout is expressed by the following formula.

[0005] Vout=Vin-Ir / R=Vin-(Io+Ic) / R

[0006] In the shunt regulator, the NMOS transistor 103 adjusts the current Ic to obtain the required output voltage Vout. That is, regarding the shunt regulator, since Ir = Io + Ic, it is necessary to estimate the current Ic flowing in the shunt regulator IC to determine the current Ir (see, for example, Patent Document 1).

[0007] [Existing Technical Documents]

[0008] [Patent Literature]

[0009] [Patent Document 1] US Patent No. 8085006 Specification Summary of the Invention

[0010] [The problem the invention aims to solve]

[0011] However, when the shunt regulator includes circuits that flow large currents during operation (e.g., non-volatile memory), it is necessary to estimate the operating current of the circuit to determine the current Ir. Therefore, when the circuit is not operating, the NMOS transistor 103 needs to flow that level of current. Thus, conventional shunt regulators have the problem of wasting large currents during normal operation when the circuit is not running.

[0012] The present invention was made in view of the aforementioned problems, and its object is to provide a shunt regulator that can reduce the current consumption during normal operation, even in circuits that include circuits with large current flow during operation.

[0013] [Technical means to solve the problem]

[0014] An embodiment of the shunt regulator of the present invention includes: an output terminal connected to a power supply terminal via an external resistor; a capacitor connected between the output terminal and a ground terminal; a voltage divider circuit connected in series between the output terminal and the ground terminal; an output transistor connected between the output terminal and the ground terminal; a first reference voltage circuit outputting a first reference voltage; an error amplifier controlling the output transistor based on the voltage at the output terminal of the voltage divider circuit and the first reference voltage; a non-volatile memory; a memory control circuit outputting a data read signal to the non-volatile memory; and a voltage detection circuit detecting that the voltage at the output terminal reaches a predetermined voltage that allows the data read operation of the non-volatile memory, outputting a detection signal to the memory control circuit, wherein the operating current of the non-volatile memory is supplied from the capacitor.

[0015] [The effects of the invention]

[0016] According to the shunt regulator of the present invention, a capacitor is provided at the output terminal and a voltage detection circuit for detecting the output voltage is included, so that even if a circuit with a large current flowing during operation is included, the current consumption during normal operation can be reduced. Attached Figure Description

[0017] Figure 1 This is a block diagram illustrating the shunt regulator of this embodiment.

[0018] Figure 2 This is a circuit diagram illustrating an example of the voltage detection circuit of this embodiment.

[0019] Figure 3 This is a circuit diagram illustrating another example of the voltage detection circuit in this embodiment.

[0020] Figure 4 This is a circuit diagram illustrating another example of the voltage detection circuit in this embodiment.

[0021] Figure 5 This is a block diagram illustrating a conventional shunt regulator.

[0022] [Explanation of Symbols]

[0023] 11, 23, 25: Reference Voltage Circuit

[0024] 12: Error Amplifier

[0025] 13, 14, 21, 22: Resistors

[0026] 15, 29: NMOS transistors

[0027] 16: Non-volatile memory

[0028] 17: Memory control circuit

[0029] 20: Voltage detection circuit

[0030] 24, 26: Comparators

[0031] 27: SR latch circuit

[0032] 28: Constant Current Circuit

[0033] 100: Shunt voltage regulator

[0034] 110: External resistor

[0035] 111: Load

[0036] 112: Capacitor Detailed Implementation

[0037] The shunt regulator of the present invention will now be described with reference to the accompanying drawings.

[0038] Figure 1 This is a block diagram illustrating the shunt regulator 100 of this embodiment.

[0039] As an example, the shunt regulator 100 includes a non-volatile memory that flows a large current during data readout. Furthermore, the current flowing through the external resistor is set to an amount that does not take into account the operating current of the non-volatile memory.

[0040] Figure 1 The shunt regulator 100 includes a reference voltage circuit 11, an error amplifier 12, resistors 13 and 14 forming a voltage divider circuit, an NMOS transistor 15 serving as an output transistor, a non-volatile memory 16, a memory control circuit 17, a voltage detection circuit 20, an external resistor 110, and a capacitor 112.

[0041] Resistors 13 and 14 are connected in series between the output terminal and the ground terminal. Error amplifier 12 has its output terminal of reference voltage circuit 11 connected to its inverting input terminal -, and its output terminal FB (the junction of resistors 13 and 14) of voltage divider circuit connected to its non-inverting input terminal +. Its output terminal is connected to the gate of NMOS transistor 15. The input terminal of voltage detection circuit 20 is connected to the output terminal of shunt regulator 100, and its output terminal is connected to the input terminal of memory control circuit 17. The output terminal of memory control circuit 17 is connected to the input terminal of non-volatile memory 16. The output terminal of non-volatile memory 16 is connected, for example, to the control terminal of voltage divider circuit or the control terminal of reference voltage circuit 11. Capacitor 112 is connected between the output terminal of shunt regulator 100 and the ground terminal. External resistor 110 is connected between the power supply terminal with input power supply voltage Vin and the output terminal of shunt regulator 100. Load 111 is connected between the output terminal of shunt regulator 100 and the ground terminal.

[0042] The non-volatile memory 16 stores circuit parameter data of the shunt regulator 100, such as adjustment data for the reference voltage circuit 11 or the voltage divider circuit. The non-volatile memory 16 has a voltage range from which data can be read; if the voltage is below the minimum read voltage, data read is not guaranteed. The memory control circuit 17 outputs a control signal Vcnt for reading data from the non-volatile memory 16 based on the detection signal Vdet from the voltage detection circuit 20. The voltage detection circuit 20 detects that the output voltage Vout of the shunt regulator 100 has reached a predetermined voltage that allows the non-volatile memory 16 to operate, and outputs the detection signal Vdet.

[0043] Figure 2 This is a circuit diagram illustrating an example of the voltage detection circuit 20 of this embodiment.

[0044] The voltage detection circuit 20 includes resistors 21 and 22 that form a voltage divider circuit, a reference voltage circuit 23, and a comparator 24.

[0045] Resistors 21 and 22 are connected between the output terminal and the ground terminal. Comparator 24 has an output terminal FB2 (the connection point of resistors 21 and 22) connected to the voltage divider circuit at the non-inverting input terminal +, and an output terminal of the reference voltage circuit 23 connected to the inverting input terminal -. The comparator outputs a detection signal Vdet from the output terminal.

[0046] The shunt regulator 100 configured as described herein operates as follows.

[0047] If there is a power supply voltage Vin at the input, current flows through the external resistor 110 and outputs an output voltage Vout at the output terminal. The output voltage Vout rises slowly by charging the capacitor 112 connected to the output terminal. Therefore, the voltage at the output terminal FB2 of the voltage divider circuit of the voltage detection circuit 20 also rises slowly. If the voltage at the output terminal FB2 of the non-inverting input terminal + input becomes higher than the reference voltage Vref1 of the reference voltage circuit 23, the comparator 24 outputs a high-level detection signal Vdet.

[0048] If the memory control circuit 17 receives a detection signal Vdet of level Hi from the output terminal of the voltage detection circuit 20 at its input terminal, it latches the signal and outputs a control signal Vcnt of level Hi from its output terminal to the input terminal of the non-volatile memory 16. If the non-volatile memory 16 receives the control signal Vcnt of level Hi, it begins reading data.

[0049] The data read operation of the non-volatile memory 16 requires a large current, but this current is supplied by the charge stored in the capacitor 112. Therefore, the voltage of the capacitor 112, that is, the output voltage Vout of the output terminal, gradually decreases due to the data read operation of the non-volatile memory 16. Here, the reference voltage Vref1 is set so that the output voltage Vout is not lower than the minimum read voltage before the data read operation of the non-volatile memory 16 ends. In addition, when the data read operation of the non-volatile memory 16 ends, the output voltage Vout of the output terminal rises gradually together with the voltage of the capacitor 112, entering the normal operating state. Moreover, the memory control circuit 17 is configured to release the latch of the detection signal Vdet of the voltage detection circuit 20, and even if the detection signal Vdet is received again, the control signal Vcnt is not output.

[0050] As explained above, the shunt regulator 100 of this embodiment is configured such that the voltage detection circuit 20 detects that the output voltage Vout of the output terminal reaches the voltage required for the data read operation of the non-volatile memory 16, and the capacitor 112 supplies the current required for the data read operation, thereby reducing the current consumption during normal operation.

[0051] Figure 3 This is a circuit diagram illustrating another example of the voltage detection circuit 20 in this embodiment.

[0052] The voltage detection circuit 20 includes resistors 21 and 22 constituting a voltage divider circuit, a reference voltage circuit 23 and comparator 24 constituting an upper limit voltage detection circuit, a reference voltage circuit 25 and comparator 26 constituting a lower limit voltage detection circuit, and an SR latch circuit 27.

[0053] Resistors 21 and 22 are connected between the output terminal and the ground terminal. Comparator 24 has its output terminal FB2 (the connection point of resistors 21 and 22) connected to the voltage divider circuit at the non-inverting input terminal +, and its output terminal of the reference voltage circuit 23 connected to the inverting input terminal -, outputting an upper limit detection signal from the output terminal. Comparator 26 has its output terminal FB2 (the connection point of resistors 21 and 22) connected to the voltage divider circuit at the inverting input terminal -, and its output terminal of the reference voltage circuit 25 connected to the non-inverting input terminal +, outputting a lower limit detection signal from the output terminal. The SR latch circuit 27 has its output terminal of comparator 24 connected to the setting terminal S, and its output terminal of comparator 26 connected to the reset terminal R, outputting a detection signal Vdet from the output terminal Q.

[0054] The shunt regulator 100 configured as described herein operates as follows.

[0055] If there is a power supply voltage Vin at the input, current flows through the external resistor 110, resulting in an output voltage Vout at the output terminal. The output voltage Vout gradually increases by charging the capacitor 112 connected to the output terminal. Therefore, the voltage at the output terminal FB2 of the voltage divider circuit of the voltage detection circuit 20 also gradually increases. If the voltage at the output terminal FB2 of the non-inverting input terminal + input becomes higher than the reference voltage Vref1 of the reference voltage circuit 23, the comparator 24 outputs an upper limit detection signal of the Hi level.

[0056] If an upper limit detection signal of Hi level is input to the setting terminal S, the SR latch circuit 27 outputs a detection signal Vdet of Hi level from the output terminal Q. If a detection signal Vdet of Hi level is input to the output terminal of the voltage detection circuit 20, the memory control circuit 17 outputs a control signal Vcnt of Hi level to the input terminal of the non-volatile memory 16 from its output terminal. If the non-volatile memory 16 receives the control signal Vcnt of Hi level, it begins reading data.

[0057] Figure 3 The voltage detection circuit 20 includes a comparator 26 and a reference voltage circuit 25. The reference voltage circuit 25 is configured such that the output voltage Vout at the output terminal is not lower than the minimum read voltage of the non-volatile memory 16. Therefore, if the voltage at the output terminal FB2 of the voltage divider circuit is lower than the reference voltage Vref2, the comparator 26 outputs a lower limit detection signal of level Hi from the output terminal.

[0058] If a Hi-level lower limit detection signal is input to the reset terminal R, the SR latch circuit 27 outputs a Lo (low) level detection signal Vdet from the output terminal Q. If a Lo-level detection signal Vdet is input to the input terminal from the output terminal of the voltage detection circuit 20, the memory control circuit 17 stops outputting a Hi-level control signal Vcnt to the non-volatile memory 16. Therefore, the non-volatile memory 16 stops reading data. Here, because... Figure 3 The voltage detection circuit 20 outputs a detection signal Vdet at the Lo level based on the lower limit detection signal, so the memory control circuit 17 may not have the function of latching.

[0059] If data reading stops, the output voltage Vout at the output terminal rises. If the voltage at the output terminal FB2 of the non-inverting input terminal + input becomes higher than the reference voltage Vref1 of the reference voltage circuit 23, the comparator 24 outputs an upper limit detection signal of the Hi level. Therefore, the non-volatile memory 16 starts reading data again.

[0060] Figure 3 The voltage detection circuit 20, by repeating the aforementioned operation, enables a read operation within a voltage range where the output voltage Vout at the output terminal is not lower than the minimum read voltage of the non-volatile memory 16. Therefore, including Figure 3 The shunt regulator 100 of the voltage detection circuit 20 can also handle unexpected states such as changes in the output voltage Vout of the output terminal during the read operation of the non-volatile memory 16.

[0061] The embodiments of the present invention have been described above, but the present invention is not limited to these embodiments, and various modifications can be made without departing from the spirit of the present invention. As a circuit that flows a large current during operation, a non-volatile memory has been used as an example for description, but the invention is not limited to any circuit that is not normally in operation. Furthermore, for example… Figure 2 The voltage detection circuit 20 shown can also be derived from... Figure 4 The circuit shown is a current comparator circuit comprising a constant current circuit 28 and an NMOS transistor 29. This circuit can also be applied to... Figure 3 The voltage detection circuit 20 is shown. Furthermore, for example... Figure 3 The voltage detection circuit 20 shown only needs to output upper and lower limit detection signals to the SR latch circuit, and therefore can also be configured by sharing a reference voltage circuit and setting the output terminals of two voltage divider circuits. Moreover, it is not limited to the SR latch circuit as long as the function is met. Furthermore, for example, the upper and lower limit detection signals of the voltage detection circuit 20 are described as Hi-level detection signals, but the logic can be designed freely.

Claims

1. A shunt voltage regulator, characterized in that, include: The output terminal is connected to the power supply terminal via an external resistor; A capacitor is connected between the output terminal and the ground terminal; A voltage divider circuit is connected in series between the output terminal and the ground terminal; An output transistor is connected between the output terminal and the ground terminal; The first reference voltage circuit outputs the first reference voltage. An error amplifier controls the output transistor based on the voltage at the output terminal of the voltage divider circuit and the first reference voltage; Non-volatile memory; The memory control circuit outputs a data read signal to the non-volatile memory; as well as A voltage detection circuit detects that the voltage at the output terminal has reached a predetermined voltage that allows the data read operation of the non-volatile memory, and outputs a detection signal to the memory control circuit. The operating current of the non-volatile memory is supplied from the capacitor.

2. The shunt voltage regulator according to claim 1, characterized in that, The voltage detection circuit includes: The second voltage divider circuit is connected in series between the output terminal and the ground terminal; The second reference voltage circuit outputs a second reference voltage; and The first comparator outputs the detection signal based on the voltage at the output terminal of the second voltage divider circuit and the second reference voltage.

3. The shunt voltage regulator according to claim 1, characterized in that, The voltage detection circuit includes: The second voltage divider circuit is connected in series between the output terminal and the ground terminal; A constant current circuit, wherein one terminal is connected to the output terminal; and An N-type metal-oxide-semiconductor transistor has an output terminal of the second voltage divider circuit connected to its gate, another terminal of the constant current circuit connected to its drain, and a ground terminal connected to its source.

4. The shunt voltage regulator according to claim 1, characterized in that, The voltage detection circuit includes: The second voltage divider circuit is connected in series between the output terminal and the ground terminal; The second reference voltage circuit outputs a second reference voltage. The first comparator outputs an upper limit detection signal based on the voltage at the output terminal of the second voltage divider circuit and the second reference voltage; The third reference voltage circuit outputs the third reference voltage; and The second comparator outputs a lower limit detection signal based on the voltage at the output terminal of the second voltage divider circuit and the third reference voltage. The detection signal is output based on the upper limit detection signal and the lower limit detection signal.

5. The shunt voltage regulator according to claim 1, characterized in that, The voltage detection circuit includes: The second voltage divider circuit is connected in series between the output terminal and the ground terminal; The second reference voltage circuit outputs a second reference voltage. A first comparator outputs an upper limit detection signal based on the voltage at the first output terminal of the second voltage divider circuit and the second reference voltage; and The second comparator outputs a lower limit detection signal based on the voltage at the second output terminal of the second voltage divider circuit and the second reference voltage. The detection signal is output based on the upper limit detection signal and the lower limit detection signal.

6. The shunt voltage regulator according to claim 4 or 5, characterized in that, The voltage detection circuit includes: The latching circuit receives the upper limit detection signal at the setting terminal, the lower limit detection signal at the reset terminal, and outputs the detection signal from the output terminal.

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