Method for generating encoding circuit, system for generating encoding circuit, program for generating encoding circuit, and encoding circuit

Abstract

To provide a method for generating an encoding circuit, a system for generating an encoding circuit, a program for generating an encoding circuit, and an encoding circuit.SOLUTION: In an information processing system, an encoding circuit 8 that includes a superposition circuit 80, a coupling circuit 81, and a coefficient circuit 84 and is a quantum circuit for encoding a group of computational quantum bits composed of a plurality of computational quantum bits, comprises: a model acquisition step for acquiring a mathematical model of an analysis target, which is defined by a linear combination of n expansion functions, where the mathematical model contains information about expansion coefficients of the expansion functions; an assignment step for assigning n possible states observable from an auxiliary bit group consisting of at least one auxiliary bit to each of the expansion functions; and a circuit generation step for generating an encoding circuit based on the expansion coefficients and an expansion function generation operation that generates each expansion function for defining the mathematical model.SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] The present invention relates to a method for generating an encoding circuit, a system for generating an encoding circuit, a program for generating an encoding circuit, and an encoding circuit. [Background technology]

[0002] Patent Document 1 discloses a technique for reducing the number of gates used for decoding to reduce the scale of the quantum circuit and for improving the efficiency of quantum error correction. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2006-279889 Summary of the Invention [Problem to be solved by the invention]

[0004] However, in order to perform various quantum computations on a certain object of analysis, it is necessary to encode the object of analysis as a quantum state, which is the premise of the computation. However, there is still room for improvement in the technology for encoding more complex objects of analysis as quantum states. [Means for solving the problem]

[0005] According to one aspect of the present invention, there is provided a method for generating an encoding circuit. The encoding circuit in this method is a quantum circuit for encoding a group of computation qubits composed of a plurality of computation qubits. The method includes the following steps: In the model acquisition step, a mathematical model of an analysis target defined by a linear combination of n expansion functions is acquired. The mathematical model includes information on expansion coefficients of the expansion functions. In the assignment step, n observable states are assigned to each of the expansion functions from an ancillary bit group composed of at least one ancillary bit. In the circuit generation step, an encoding circuit is generated based on the expansion coefficients and an expansion function generation operation that generates each of the expansion functions defining the mathematical model. The encoding circuit includes a superposition circuit, a coupling circuit, and a coefficient circuit. The superposition circuit is configured to operate on the ancillary bit group to output an ancillary bit group having a superposition of n states. The coupling circuit is configured to operate on the computation qubit group based on the ancillary bit group having a superposition of n states, to output a superposition state of the computation qubit group having a state corresponding to the expansion function assigned to each of the n states. The superposition state of the computation qubit is configured to be projected onto a state of the computation qubit group representing an expansion function assigned to the observed state of the ancillary bit group by performing an observation operation on the ancillary bit group. The coefficient circuit is configured to perform a unitary transformation on the ancillary bit group output from the coupling circuit, thereby transforming each of the n states superimposed on the ancillary bit group into a state including a specific state that is one of the n states. The unitary transformation is configured to operate on the ancillary bit group so that the ratio of the probability amplitudes of the specific state derived from each of the n states superimposed on the ancillary bit group matches the ratio of the expansion coefficients.

[0006] This technology makes it possible to provide quantum circuits that can encode more complex objects of analysis as quantum states. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a configuration diagram illustrating an information processing system. [Figure 2] FIG. 1 is an activity diagram showing an overview of information processing executed in an information processing system. [Figure 3] FIG. 10 is an activity diagram illustrating an example of a process for generating an encoding circuit. [Figure 4] FIG. 2 is a diagram illustrating an example of a circuit configuration of an encoding circuit. [Figure 5] FIG. 10 is a circuit diagram showing the processing of a parameter set {θ}. [Figure 6] This is an example of a basic function generation operation corresponding to the Slater function. [Figure 7] 10 is an example of an encoding circuit when the expansion function is a Lorentz function. [Figure 8] FIG. 10 shows the observation results of the state of the computational qubit in this experiment. [Figure 9] FIG. 10 is a diagram illustrating another example of an encoding circuit. DETAILED DESCRIPTION OF THE INVENTION

[0008] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the accompanying drawings. Various features shown in the following embodiments can be combined with each other.

[0009] Incidentally, the program for realizing the software appearing in one embodiment may be provided as a non-transitory computer-readable medium, or may be provided so that it can be downloaded from an external server, or may be provided so that the program is started on an external computer and its functions are realized on a client terminal (so-called cloud computing).

[0010] Furthermore, various information processing according to an embodiment may realize input and output corresponding to the input. Here, the form of information referenced in such information processing (hereinafter referred to as reference information) is not limited as long as an output is obtained as a result of the input. The reference information may be, for example, rule-based information such as a database, a lookup table, or a predetermined function (including a decision formula such as a regression formula constructed using a statistical method), a trained model that has previously trained the correlation between input and output, or a large-scale language model that can output a desired result by inputting a prompt.

[0011] In one embodiment, a "unit" may include, for example, a combination of hardware resources implemented by a circuit in the broad sense and software information processing that can be specifically realized by these hardware resources. In one embodiment, various information is handled, and this information is represented, for example, by physical values ​​of signal values ​​representing voltage and current, high and low signal values ​​as a binary bit set consisting of 0 or 1, or quantum superposition (so-called quantum bits), and communication and calculations can be performed on a circuit in the broad sense.

[0012] Furthermore, a circuit in the broad sense is a circuit realized by at least an appropriate combination of a circuit, circuitry, processor, memory, etc. The processor may be a general-purpose processor or a dedicated circuit. That is, it includes an application specific integrated circuit (ASIC), a programmable logic device (e.g., a simple programmable logic device (SPLD), a complex programmable logic device (CPLD), and a field programmable gate array (FPGA)), etc.

[0013] 1. Hardware Configuration In this section, the hardware configuration of the information processing system 1 according to this embodiment will be described. <Information Processing System 1> FIG. 1 is a configuration diagram showing an information processing system 1. The information processing system 1 includes an information processing device 2, at least one quantum computer 3, and a user terminal 4. The information processing device 2, the quantum computer 3, and the user terminal 4 are configured to be able to communicate with each other via a telecommunications line. In one embodiment, the information processing system 1 is made up of one or more devices or components. For example, if the information processing system 1 is made up of only the information processing device 2, the information processing system 1 can be the information processing device 2. These components will be described below.

[0014] <Information processing device 2> The information processing device 2 includes a communication unit 21, a storage unit 22, and a processor 23, and these components are electrically connected via a communication bus 20 inside the information processing device 2. Each component will be further described below.

[0015] <Communications Department 21> The communication unit 21 is preferably a wired communication means such as USB, IEEE1394, Thunderbolt (registered trademark), wired LAN network communication, etc., but may also include wireless LAN network communication, mobile communication such as 3G / LTE / 5G, BLUETOOTH (registered trademark) communication, etc. as needed. In other words, it is more preferable to implement it as a collection of multiple communication means. In other words, the information processing device 2 may communicate various information from the outside via the communication unit 21 and the network.

[0016] <Storage section 22> The storage unit 22 stores various pieces of information defined above. This can be implemented, for example, as a storage device such as a solid state drive (SSD) that stores various programs and the like related to the information processing device 2 executed by the processor 23, or as a memory such as a random access memory (RAM) that stores temporarily required information (arguments, arrays, etc.) related to the program operations. The storage unit 22 stores various programs, variables, etc. related to the information processing device 2 executed by the processor 23.

[0017] <Processor 23> The processor 23 processes and controls the overall operations related to the information processing device 2. The processor 23 is, for example, a central processing unit (CPU) not shown. The processor 23 realizes various functions related to the information processing device 2 by reading out predetermined programs stored in the storage unit 22. In other words, information processing by software stored in the storage unit 22 is specifically realized by the processor 23, which is an example of hardware, and can be executed as each functional unit included in the processor 23. These will be described in more detail in the next section. Note that the processor 23 is not limited to being single, and multiple processors 23 may be provided for each function. A combination of these may also be used.

[0018] <Quantum computer 3> The quantum computer 3 has a communication unit 31, a quantum memory 32, and a quantum processor 33, and these components are connected via a communication bus 30 inside the quantum computer 3. The quantum computer 3 may include an error-tolerant quantum computer, an NISQ device, or both. The quantum computer 3 of this embodiment is a gate type. Each component will be further described below.

[0019] <Communications Department 31> The communication unit 31 is used by the quantum computer 3 to communicate information with other information processing devices (including classical computers, quantum computers, or computers that combine these) or peripheral devices.

[0020] <Quantum Memory 32> The quantum memory 32 stores various pieces of information defined above. In particular, the quantum memory 32 stores various programs that can be read by the quantum processor 33, which will be described next. The quantum memory 32 also stores, as necessary, information on the physical properties of specific materials related to the calculations of the quantum computer 3. The quantum memory 32 includes a plurality of quantum bits 320. The quantum bits 320 can be implemented using any method, such as nuclear spins, photons, ions, atoms, quantum dots, or superconducting Josephson devices. The quantum bits 320 include a computational quantum bit 321 and an ancillary bit 322. The quantum memory 32 may also include a classical memory device.

[0021] <Quantum Processor 33> The quantum processor 33 processes and controls the overall operations related to the quantum computer 3. The quantum processor 33 realizes various functions related to the quantum computer 3 by reading out a program stored in the quantum memory 32 or a predetermined program input via the communication unit 31. Note that although FIG. 1 shows a single quantum processor 33, in practice this is not limited to this, and multiple quantum processors 33 may be provided for each function. A combination of these may also be used.

[0022] Quantum processor 33 is configured to perform various quantum operations on qubits 320 that can be implemented on a quantum circuit. For example, the quantum circuit is configured to define a set of quantum operations on qubits 320. Quantum operations include, for example, quantum gate operations and observation operations. Quantum gate operations correspond to unitary operations on the quantum state of qubits 320. Observation operations correspond to projection operations on the quantum state of qubits 320.

[0023] <User terminal 4> The user terminal 4 includes a communication unit 41, a memory 42, a processor 43, a display unit 44, and an input unit 45, and these components are electrically connected via a communication bus 40 inside the user terminal 4. The description of the communication unit 41, the memory 42, and the processor 43 will be omitted as they are the same as the description of each unit in the information processing device 2.

[0024] <Display section 44> The display unit 44 may be included in the housing of the user terminal 4 or may be externally attached. The display unit 44 displays a graphical user interface (GUI) screen that can be operated by the user. This is preferably implemented by selectively using display devices such as a CRT display, a liquid crystal display, an organic EL display, or a plasma display depending on the type of user terminal 4.

[0025] <Input section 45> The input unit 45 may be included in the housing of the user terminal 4, or may be externally attached. For example, the input unit 45 may be implemented as a touch panel integrated with the display unit 44. The touch panel allows the user to input tapping, swiping, and the like. Of course, switch buttons, a mouse, a QWERTY keyboard, and the like may be used instead of the touch panel. That is, the input unit 45 accepts an operation input made by the user. The input is transferred as a command signal to the processor 43 via the communication bus 40, and the processor 43 can execute predetermined control or calculation as necessary.

[0026] 2. Information Processing In this chapter, the flow of information processing executed in the information processing system 1 described above will be explained. 2.1 Overview of information processing 2 is an activity diagram showing an overview of information processing executed in the information processing system 1. Note that the information processing may include any exception processing not shown in the activity diagram. Exception processing may include interruption of the information processing or omission of each process. Selection or input performed in the information processing may be based on a user operation or may be performed automatically without relying on a user operation.

[0027] [Activity A1] First, in activity A1, the processor 43 transmits information about the analysis target to the information processing device 2. The analysis target indicates a problem that is the subject of quantum computation by the quantum computer 3. For example, the analysis target indicates a premise object for analysis in any field of simulation, such as a population distribution, a time series change in stock prices, or a wave function of an entire multi-body system composed of multiple particle groups, in a statistical simulation, a financial engineering simulation, or a material simulation. The information about the analysis target may be defined, for example, to indicate the behavior of a response variable with respect to a vector represented by at least one input variable. The analysis target may be defined, for example, to represent the distribution of a response variable with respect to input variables. The analysis target may be implemented in any manner, such as a function or a lookup table. The information about the analysis target may be imported manually by a user or automatically at a specified timing from a predetermined information source. The information about the analysis target may also include attributes of the analysis target, such as the field to which the analysis target belongs. The attributes of the analysis object are, for example, "finance" when the analysis object represents fluctuations in financial indices, "electronic structure" when the analysis object represents measurement data on physical quantities resulting from the electronic structure of a substance (e.g., absorption spectrum, elasticity tensor, impedance characteristics, etc.), "mechanical properties" when the analysis object represents measurement data on quantities related to the mechanical properties of a substance (e.g., Young's modulus, thermal expansion coefficient, etc.), and "people flow" when the analysis object represents data on the movement of people associated with economic activities, such as people flow data. These attributes are defined, for example, so that the properties of the representative functions that indicate the behavior of the analysis object are different.

[0028] [Activity A2] Next, in activity A2, the processor 23 acquires information about the analysis target. The information about the analysis target is transmitted from the processor 43, for example.

[0029] [Activity A3] Next, in activity A3, processor 23 constructs a mathematical model of the object to be analyzed using a linear combination of multiple expansion functions. For example, if the object to be analyzed is the optical absorption spectrum of a certain material, each peak in the optical absorption spectrum can be approximately described using a Gaussian function. Therefore, processor 23 can describe the mathematical model of the object to be analyzed as a linear combination of Gaussian functions having a representative point (peak position) at one of the peak positions. The expansion functions included in such a linear combination may be specified by the user or may be set by processor 23 based on information about the object to be analyzed. For convenience of explanation, the number of expansion functions is hereinafter referred to as n2.

[0030] [Activity A4] Next, in activity A4, the processor 23 optimizes the mathematical model represented by the linear combination of n2 expansion functions constructed in activity A3 for the analysis object based on a comparison with the information about the analysis object. The processor 23 updates the parameters included in the linear combination to satisfy predetermined optimization conditions. The optimization conditions are defined, for example, so that the error between the mathematical model and the information about the analysis object is within a predetermined tolerance. The parameters included in the linear combination include, for example, the coefficients of each expansion function. For convenience of explanation, the coefficients of the expansion functions are referred to as expansion coefficients hereinafter. The parameters included in the linear combination may include values ​​characterizing each expansion function, such as a representative position, the value of the expansion function at the representative position, and the half-width of the expansion function. When the values ​​characterizing each expansion function are updated, the processor 23 reconstructs the mathematical model of the analysis object as a linear combination of the latest expansion functions. The processor 23 then outputs the optimization result of the mathematical model. The optimization result may include any information representing the relationship between the mathematical model and the expansion functions, such as the type of expansion function, each parameter of the expansion function, and each coefficient of the expansion function. The optimization algorithm in this embodiment can be executed by a classical computer.

[0031] [Activity A5] Next, in activity A5, processor 23 generates an encoding circuit based on the optimization results of activity A4. The encoding circuit is a quantum circuit for encoding a group of computational qubits composed of multiple computational qubits. Details of how the encoding circuit is generated and specific aspects of the encoding circuit will be described later.

[0032] [Activity A6] Next, in activity A6, processor 43 transmits a specification of a process for the analysis object. The specification of the analysis process for the analysis object is, for example, a specification of a quantum circuit to be applied to the state output by the encoding circuit. The quantum circuit corresponds to the content of the process for the analysis object, such as a numerical value obtained by performing quantum computing on the analysis object. For example, if the mathematical model of the analysis object represents the quantum state of a many-electron system that constitutes a certain substance, the specification of an operator corresponding to the physical quantity obtained from the quantum state to obtain the expected value of the physical quantity can correspond to the specification of the process for the analysis object.

[0033] [Activity A7] Next, in activity A7, the processor 23 acquires the specification sent in activity A6 and generates a calculation circuit according to the specified analysis process. The calculation circuit is a quantum circuit corresponding to the specification and is configured to be executed after the encoding circuit is executed. The calculation circuit is, for example, a quantum circuit corresponding to the above operator. Thereafter, the processor 23 transmits the generated encoding circuit and calculation circuit to the quantum computer 3.

[0034] [Activity A8] Next, in activity A8, quantum processor 33 performs quantum operations on each of computation qubit 321 and ancillary bit 322 based on the transmitted encoding circuit and computation circuit. This allows quantum processor 33 to implement the mathematical model of the analysis object, defined by the encoding circuit as a linear combination of expansion functions, as the quantum state of computation qubit 321. Quantum processor 33 can perform quantum operations on the implemented quantum state based on the computation circuit, thereby performing quantum computation based on processing of the analysis object.

[0035] [Activity A9] Thereafter, in activity A9, the processor 23 obtains the calculation result from the quantum processor 33 and transmits it to the user terminal 4 as the result of the analysis process.

[0036] [Activity A10] Thereafter, in activity A10, the processor 43 outputs the results of the analysis process. For example, the processor 43 presents the results of the analysis process to the user via the display unit 44. Thereafter, the information processing system 1 ends this information processing.

[0037] According to the above configuration, a complex analysis target that can be expressed as a linear combination of multiple functions can be expressed as a quantum state.

[0038] 2.2 An example of the process for generating an encoding circuit In this section, an example of a process (activity A5) for generating an encoding circuit will be described. Fig. 3 is an activity diagram showing an example of a process for generating an encoding circuit.

[0039] [Activity A101] First, in activity A101, the processor 23 sets a resolution n1 of the mathematical model. The resolution represents the number (density) of data points for expressing the mathematical model. The resolution may be set based on a specification from the user terminal 4 or based on a predetermined value.

[0040] [Activity A102] Next, in activity A102, processor 23 calculates the number N1 of computation qubits 321 based on the resolution. Each computation qubit 321 is represented using two observable states |0> and |1>. The N1 computation qubits 321 are represented as 2 when observed. N1 states are possible. Therefore, processor 23 sets the number N1 of computation qubits 321 so that N1 = log2(n1). Hereinafter, for convenience of explanation, a system configured by N1 computation qubits 321 may be referred to as a group of computation qubits.

[0041] [Activity A103] Next, in activity A103, processor 23 associates the values ​​of the input variables of the mathematical model with the states of computation qubit 321. For example, if the expansion function has one input variable, processor 23 associates each of the n1 values ​​within the domain that the input variable can take with each state of computation qubit 321. The values ​​of the n1 input variables may be equally spaced within the domain, or may be values ​​arbitrarily set by the user. If the expansion function has multiple input variables, processor 23 may associate the input variables of the expansion function with the states of computation qubit 321 by setting n1 state vectors defined by the multiple input variables.

[0042] [Activity A104] Next, in activity A104, the processor 23 acquires basis functions corresponding to each of the expansion functions. A basis function is one of functions used to mathematically express information about the analysis object. Each basis function is characterized by a representative position in a state space defined by the input variables of the basis function. Identifying a basis function is an example of acquiring at least one basis function. The basis function may include any function, such as a periodic function, a decay function, a constant function, or a linear function. In particular, the basis function is preferably a localized function localized at the representative position. This configuration facilitates analysis of an analysis object represented by multiple localized elements. A localized function is a function configured to express that one of the elements constituting the analysis object is locally present near the representative position. The localized function is, for example, a function isomorphic to an electron localized function. Examples of electron localized functions include Bloch functions, Wannier functions, delta functions, Slater functions, and Lorentz functions. The localized function may also be a function representing a statistical distribution. For example, the local function may be a function representing a Gaussian distribution or a function representing a Poisson distribution. In particular, it is preferable that the basic function is a Lorentz function. The representative position of the basic function corresponds to the origin in a state space defined by the input variables of the basic function. However, the representative position is not limited to this, and may be any point that characterizes the basic function, such as the mean value, median value, or mode value of the function.

[0043] Each of the basic functions may be associated with information about the analysis target. For example, each of the basic functions may be associated with at least one of the attributes of the analysis target. For example, a basic function may be associated with an attribute if it can be approximated to a representative function that indicates the behavior of the analysis target for that attribute within a predetermined tolerance. Note that the processor 23 may specify a predetermined function as the basic function regardless of the analysis target. In this embodiment, each of the basic functions may be configured to be convertible into at least one expansion function by translating the basic function from a representative position.

[0044] [Activity A105] Next, in activity A105, the processor 23 identifies function generation operations corresponding to each of the n2 elementary functions based on, for example, predetermined reference information. The reference information is, for example, a list that defines the correspondence between the elementary functions and the function generation operations. The function generation operation is an operation that outputs a quantum state that approximately reproduces the elementary function by inputting a predetermined state.

[0045] [Activity A106] Next, in activity A106, the processor 23 calculates, for each expansion function, a movement amount that indicates the difference between the representative position of the basic function and the representative position between the expansion functions corresponding to the basic function.

[0046] [Activity A107] Next, in activity A107, the processor 23 identifies, for each expansion function, a translation operation corresponding to each movement amount of the elementary functions. The translation operation is an operation for translating, in other words, moving the elementary functions in parallel, within a space defined by the input variables of the mathematical model. For example, the translation operation includes at least a phase gate operation and a quantum Fourier transform operation. The phase shift amount of the phase gate operation is set based on the calculated movement amount.

[0047] [Activity A108] Next, in activity A108, the processor 23 calculates the number N2 of ancillary bits 322 on which the encoding circuit acts, based on the number n2 of expansion functions. The ancillary bits 322 are expressed using two observable states |0> and |1>, similar to the computation qubit 321. Therefore, the processor 23 calculates N2 so that N2≧log2(n2). Note that N2 is merely the number of ancillary bits 322 on which the encoding circuit acts, and can be set independently of the ancillary bits 322 on which the computation circuit acts. Thereafter, the processor 23 sets the N2 ancillary bits 322 as targets of action of the encoding circuit. Hereinafter, for convenience of explanation, a system formed by the N2 ancillary bits 322 set as targets of action of the encoding circuit may be referred to as an ancillary bit group. In other words, the ancillary bit group includes N2 ancillary bits and is configured so that at least n2 different states can be observed by an observation operation. [Activity A109] Next, in activity A109, the processor 23 assigns different states of the auxiliary bit group to each of the expansion functions. For example, if four expansion functions are specified, the processor 23 sets two auxiliary bits 322 as targets of operation, and assigns to each of the four expansion functions |00>, |01>, |10>, and |11>, which are observable states of the auxiliary bit group made up of the two auxiliary bits 322. Note that |ij>=|i>×|j> (i and j are indexes indicating the state of the auxiliary bits 322 and take 0 or 1. × represents the Kronecker product).

[0048] [Activity A110] Next, in activity A110, by comparing each function generation operation, the quantum operations included in each function generation operation are classified into unique operations and common operations. Unique operations are quantum operations that are different from each other among the quantum operations included in each function generation operation. Common operations are quantum operations that are executed in all of the function generation operations. Note that "a quantum operation being a common operation" does not simply mean that the type of quantum operation is common, but also that the execution position of the quantum operations of the common type is common.

[0049] [Activity A111] Next, in activity A111, processor 23 controls and gates at least some of the quantum operations, including the eigenoperations, included in each function generation operation. As a result, the controlled and gated quantum operations are configured to act on computation qubit 321 when the group of ancillary bits takes a certain specific state. For example, processor 23 controls and gates the 2 observable quantum operations from N2 ancillary bits 322. N2 Each of the states is associated with a respective function generation circuit, and control gating is performed such that the controlled-gated quantum operation is performed on the computation qubit 321 when the state of the auxiliary bit 322 is in the associated state. For ease of explanation, the controlled-gated function generation operation will be referred to as a controlled function generation operation hereinafter. In other words, each controlled function generation operation is configured to act on the computation qubit group when the auxiliary bit group is in the state associated with the function generation operation, by control gating at least a portion of the function generation operation so that the auxiliary bit group is the control bit and the computation qubit group is the target bit.

[0050] Furthermore, the processor 23 specifies a translation circuit by controlling gated operations for at least some of the quantum operations of the translation operations corresponding to the function generation operations. For example, the processor 23 control-gates a translation operation corresponding to a certain function generation operation so that it operates when the auxiliary bit group takes on a state corresponding to the function generation operation. In this way, the processor 23 specifies a translation circuit based on the controlled-gated translation operations. Thereafter, the processor 23 specifies a translation circuit in which a translation operation that translates each of the elementary functions according to the expansion function is associated with the control function generation operation.

[0051] [Activity A112] Next, in activity A112, the processor 23, based on the classification result of the unique operations and common operations in each function generation operation, identifies the execution position of the common operation relative to the controlled gated quantum operation, for example, which unique operation a certain common operation is executed before or after.

[0052] [Activity A113] Next, in activity A113, processor 23 identifies a coupling circuit based on the results of the processing of activities A110 to A112. The coupling circuit is a quantum circuit configured to generate a linear combination of expansion functions by acting on a group of quantum bits formed by N1 computation quantum bits 321 and N2 auxiliary bits 322.

[0053] [Activity A114] Next, in activity A114, the processor 23 sets a parameter set for the N2 layer based on the expansion coefficients. For example, the parameter set for the k-th layer (2≦k≦N2) is recursively set based on the parameter set for the k-1-th layer. The method for setting the parameter set for each layer will be described in detail later.

[0054] [Activity A115] Next, in activity A115, processor 23 identifies a coefficient circuit that operates on the ancillary bit group based on the set parameter group. The coefficient circuit is configured to unitarily transform each state of the ancillary bit based on parameters included in the parameter group of N2 layers, where N2 is an integer equal to or greater than log2(n2), so that when a certain state is observed by an observation operation on the ancillary bit group, the coefficient circuit outputs the state of the computation qubit group operated by the coupling circuit and the translation circuit as a state corresponding to a linear combination weighted by the expansion coefficient. Specific aspects of the coefficient circuit will be described later.

[0055] [Activity A116] Next, in activity A116, processor 23 generates an encoding circuit based at least on the identified translation circuit, coupling circuit, and coefficient circuit. The encoding circuit is configured to operate on the group of computation qubits and the group of ancillary bits, and may include a coupling circuit, a translation circuit, and a coefficient circuit. The encoding circuit is configured to operate on the group of computation qubits and the group of ancillary bits in the order of coupling circuit, translation circuit, and coefficient circuit. Specific aspects of the encoding circuit will be described later. In this manner, processor 23 performs the processing of activity A5 and generates the encoding circuit.

[0056] 3. Encoder circuit configuration Next, the circuit configuration of the above-mentioned encoding circuit will be described. 3.1 Overview of the encoder circuit configuration 4 is a diagram showing an example of the circuit configuration of an encoding circuit. As shown in FIG. 4, encoding circuit 5 is configured to operate on N1 computational quantum bits 321 and N2 auxiliary bits 322 in an initial state. Encoding circuit 5 includes superposition circuit 50, combining circuit 51, and coefficient circuit 54. Encoding circuit 5 may also include observation operation 55 and the like. In this embodiment, encoding circuit 5 is configured so that superposition circuit 50, combining circuit 51, and observation operation 55 are executed in this order.

[0057] The superposition circuit 50 is configured to operate on the ancillary bits to output a group of ancillary bits having n2 superposition states. For example, the superposition circuit 50 is configured to operate on each of the ancillary bits 322 so that each ancillary bit 322 assumes a superposition state of |0> and |1>. The superposition circuit 50 may, for example, include a Hadamard gate operation operating on each of the ancillary bits 322. Note that the specific embodiment of the superposition circuit 50 is not limited thereto, and the superposition circuit 50 may be implemented using any unitary gate operation, such as a rotation gate operation. In this embodiment, an initial state in which all N2 ancillary bits 322 assume |0> is input to the superposition circuit 50. The superposition circuit 50, for example, converts the states of the computation quantum bits and the ancillary bits in their initial states into the states shown below.

number

[0058] However, in the formula "TIFF2025167606000003.tif44" represents the Kronecker product, which is sometimes written as "×" in the text. |0> ×N1 denotes the state of the entire set of computational qubits, and |0> ×N2 indicates the state of the entire auxiliary bit group. |k> on the right side of the equation indicates the k-th state among the n2 possible states of the auxiliary bit group. The specific correspondence between |k> and the states of the auxiliary bit group is arbitrary. Note that "having a superposition of n2 possible states" may include having a superposition of more than n2 possible states, for example, a superposition of n2+1 possible states.

[0059] The coupling circuit 51 is configured to operate on the computation qubit group based on the ancillary bit group having a superposition of n2 possible states, thereby outputting a superposition state of the computation qubit group having a state corresponding to the expansion function assigned to each of the n2 possible states. The superposition state of the computation qubit is configured to be projected onto a state of the computation qubit group representing the expansion function assigned to the observed state of the ancillary bit group by performing an observation operation on the ancillary bit group. For example, when the ancillary bit group takes the kth state out of the n2 possible states, the coupling circuit 51 is configured to operate on the computation qubit group and the ancillary bit group so that the computation qubit group takes a state corresponding to the kth expansion function out of the n2 expansion functions. For example, the coupling circuit 51 is configured to convert the state output from the superposition circuit 50 as follows:

number

[0060] However, in the formula, |ψ k > is the kth expansion function ψ k represents the state of the computation qubit group corresponding to |0>. In addition, the right-hand side of the above equation is assumed to be normalized as a whole, and the global normalization constant that applies to the entire right-hand side is omitted for convenience of notation. Similarly, in the following equations, unless explicitly stated in the equation, the notation of the global normalization constant that applies to the entire equation may be omitted. Note that |0> ×N1 From |ψ k The quantum circuit that generates the desired expansion function ψ k It can be designed appropriately depending on the situation.

[0061] Specifically, for example, the coupling circuit 51 includes an elementary function generation operation 52 and a translation circuit 53. The elementary function generation operation 52 is configured to output the state of a group of computation qubits representing an elementary function corresponding to the state of a group of ancillary bits. For example, the elementary function generation operation 52 includes n2 control function generation operations 521. Each of the n2 control function generation operations 521 is configured to input an initial state computation qubit 321 to stochastically generate a quantum state corresponding to the elementary function. The U included in each control function generation operation 521 orig (k) (where 0≦k≦n2−1) corresponds to the basic function generation operation.

[0062] The translation circuit 53 may include at least one controlled phase gate operation 531, a quantum Fourier transform operation 532, and an inverse quantum Fourier transform operation 533. For ease of explanation, quantum Fourier transform will be referred to as QFT hereinafter. The inverse QFT operation 533 is a Hermitian conjugate of the QFT operation 532. Each controlled phase gate operation 531 is configured to act on the computation qubit group when the ancillary bit group is in a state associated with the elementary function generation operation 52 corresponding to the amount of movement, by controlling the phase gate operation so that the ancillary bit group is the control bit and the computation qubit group is the target bit.

[0063] In this embodiment, the translation circuit 53 is configured with a phase gate operation 531, an inverse QFT operation 533 executed before the phase gate operation 531, and a QFT operation 532 executed after the phase gate operation 531. The amount of operation by the phase gate operation 531 is set to correspond to the amount of movement of the representative position between the elementary functions and the expansion functions. Here, all of the translation operations corresponding to each expansion function execute the inverse QFT operation 533 and the QFT operation 532 in the same order, and therefore these operations correspond to common operations among the translation operations. Therefore, in this embodiment, each of the inverse QFT operation 533 and the QFT operation 532 is not controlled by a control gate and is configured to act on the computation quantum bit 321 regardless of the state of the auxiliary bit 322. This makes it possible to prevent the processing from becoming complicated due to an increase in the number of control gate operations.

[0064] Coefficient circuit 54 is configured to perform a unitary transformation on the group of ancillary bits output from combining circuit 51, thereby transforming each of the n2 states superimposed on the group of ancillary bits into a state including a specific state that is one of the n2 states. The unitary transformation is configured to operate on the group of ancillary bits so that the ratio of the probability amplitudes of the specific state derived from each of the n2 states superimposed on the group of ancillary bits matches the ratio of the expansion coefficients. For example, coefficient circuit 54 is configured to operate on the states of the group of computation qubits and the group of ancillary bits output via combining circuit 51, thereby transforming the states as follows:

number

[0065] c in the formula lk is a complex number that represents the weight of each state, and is also called the probability amplitude. k |0> combined with > indicates a specific state of the ancillary bits. Here, the specific state is the initial state |0> of the ancillary bits. ×N2 It coincides with |ψ k The coefficient c_0k of |0>, which combines with >, is k This corresponds to the ratio of the expansion coefficients of

[0066] As an example, the coefficient circuit 54 is in the initial state |0> ×N2 is configured by a combination of rotation gate operations Ry (or controlled rotation gate operations CRy) so that the coefficient circuit 54 is in a specific state. Here, an example of the procedure for specifying the coefficient circuit 54 will be described along with the quantum mechanical theory in which a linear combination of expansion functions is formed by combining it with the coupling circuit 51.

[0067] To calculate the linear sum O of unitary operators U, the processor 23 recursively sets a parameter set {θ}. First, it is assumed that for the linear sum O of unitary operators U, whose number of terms is defined by the nth power of 2, each coefficient c is identified in order using an index represented by an n-digit binary number. This is shown in Equation 4.

number

[0068] Next, the processor 23 determines the parameter θ constituting the parameter set {θ} based on each coefficient c. λ (λ represents a sequence of 0s and 1s) is the phase factor of λ (That is, c λ =|c λ |exp(iθ λ ) In the following, c λ c λ | and start again, c λ is a positive real number. Furthermore, the parameter set {θ} is composed of n layers, and the parameter set {θ} of the kth layer is composed of 2 to the power of nk parameters θ (k) Here, as shown in Equation 5, each parameter θ (k) The tangent of depends on the ratio of a specific set of coefficients c. In other words, the processor 23 calculates the parameter θ (k) The parameter θ depends on the ratio of a particular set of coefficients c among the coefficients c. (k) Set.

number

[0069] Here, a specific set of coefficients c is two coefficients c that have different values ​​in the k-th place from the smallest index and the same values ​​in the other places. For example, for a parameter θ included in the parameter set {θ} of the first layer, θ (1) 0...00 is c 0...001 c 0...000The coefficients c depend on the value obtained by dividing the coefficients by θ, and all the digits except for the smallest one (the rightmost one) are equal and set to 0. Also, for the parameter θ included in the parameter group {θ} of the second layer, θ (2) 0...00 is c 0...010 c 0...000 The coefficients c depend on the value obtained by dividing by , and all coefficients c except the second smallest one are equal and have a value of 0 (see equation 6 below).

[0070] Figure 5 is a circuit diagram showing the processing of the parameter set {θ}. j in Figure 5 can be considered as j = k + 1. H is a Hadamard gate that performs the Hadamard transform. R is a rotation gate operation on the Bloch sphere, and Ry(-2θ) = exp(iθσ y ) where U is a unitary operator that performs a unitary transformation. When the input value of the control bit is 1, a black circle performs a specified operation on the value of the corresponding target bit (in a general sense here), and when the input value of the control bit is 0, the value of the corresponding target bit is not manipulated. When the input value of the control bit is 0, a white circle performs a specified operation on the value of the corresponding target bit, and when the input value of the control bit is 1, the value of the corresponding target bit is not manipulated. The parameter θ of the first layer (1) The coefficient c related to the parameter θ can be expressed as a gate operation by the equivalent circuit 6a. (k) The coefficient c related to the parameter θ (k-1) It is expressed as an equivalent circuit 6b using a coefficient c relating to the above. Specifically, it is defined as in Equation 6.

number

[0071] In relation to Equation 6, if the parameters θ included in the parameter set {θ} of the k-th layer are identified in order using an index represented by a binary number of nk digits, the processor 23 identifies the first parameter θ included in the parameter set {θ} of the k-th layer. (k) is a specific set of second parameters θ included in the parameter set {θ} of the k-1th layer(k-1) where the parameter θ is set to depend on the ratio of cosines of a particular set of second parameters θ (k-1) is the first parameter θ (k) are two parameters θ with indices obtained by adding 0 and 1 to the end of the indices of

[0072] The setting of such a parameter group {θ} is expressed as in Equation 7.

number

[0073] Furthermore, by expanding this recursively, when the auxiliary output values ​​of the auxiliary bit 322 are all observed to be 0, it is expressed as in Equation 8.

number

[0074] In other words, the k-th layer unitary transformation is recursively expressed by the k-1-th layer unitary transformation. More specifically, the k-th layer unitary transformation is determined as follows. Referring to FIG. 4, first, the 0th auxiliary bit 322 to the (k-1)th auxiliary bit 322 are each set to an input value of 0, and an initialization state in which 0 and 1 are superimposed as a basis is realized through a Hadamard gate. Next, when the auxiliary bit 322(k-1) is 0, a first unitary transformation in the k-1-th layer is executed on the 0th auxiliary bit 322 to the (k-2)th auxiliary bit 322 and m target bits. Subsequently, when the (k-1)th auxiliary bit 322 is 1, a second unitary transformation in the k-1-th layer is executed on the 0th auxiliary bit 322 to the (k-2)th auxiliary bit 322 and m target bits. Here, the first unitary transformation and the second unitary transformation use operators whose last index is 0 or 1, and whose other digits are the same. Finally, θ (k) A rotation transformation is performed using the rotation gate operation Ry.

[0075] The observation operation 55 is configured to observe the state of the auxiliary bit group output from the coefficient circuit 54 set in this way. As described above, by operating the coefficient circuit 54 specified by the combination of the rotation gate operation Ry set in this way on each of the auxiliary bits 322 for the state output via the combining circuit 51, |0> ×N2 (In the above number 8, |0> ×n ) is linked to the state of the computation qubit 321, which corresponds to a linear combination of the expansion functions weighted by the desired expansion coefficients. Therefore, the observation result of the ancillary bits is in a specific state (here, the initial state |0> ×N2 ), the following state transformations are performed (however, the global normalization constants in the formulas are omitted for the sake of notation):

number

[0076] In this way, a linear combination of desired expansion functions can be encoded by computation qubit 321.

[0077] 3.2 Example of encoding circuit configuration when Lorentzian functions are used as expansion functions Next, we will explain an example of the configuration of an encoding circuit when a Lorentzian function is used as the expansion function, which is a specific example of the encoding circuit mentioned in the previous section. As will become clear later, generating a Slater function has the same effect as Fourier transforming a Lorentzian. Based on this, we will first explain the operation of generating basic functions corresponding to a Slater function. Figure 6 is an example of an operation of generating basic functions 7 corresponding to a Slater function. The operation of generating basic functions 7 is configured to generate a Slater function as an expansion function corresponding to a predetermined attenuation rate α. As shown in Figure 6, the operation of generating basic functions 7 is an operation for generating a Slater function whose center position (average value) is located at 0 as a basic function, and is performed by a rotation gate operation Ry(2θ t) and a controlled NOT gate operation, where t is an integer in the range 0≦t≦N1−1 and indicates the index of the computation qubit 321. The Lorentz function is defined as follows:

number

number

[0078] Basic function generation operation U for generating Lorentz functions (L) is the basic function generation operation U for generating Slater functions. (S) and have the following relationship:

number

[0079] Next, an encoding circuit when the Lorentz function is used as the expansion function will be described. FIG. 7 shows an example of the encoding circuit 8 when the Lorentz function is used as the expansion function. As shown in FIG. 7, the encoding circuit 8 is configured to operate on N1 computational qubits 321 and N2 auxiliary bits 322 in the initial state. For convenience of explanation, a case will be described in which the mathematical model is expressed by a linear combination of two expansion functions. The encoding circuit 8 includes a coupling circuit 81 and a coefficient circuit 84. The encoding circuit 8 may further include a superposition circuit 80, an observation operation 85, and the like. In this embodiment, the encoding circuit 8 is configured to execute the superposition circuit 80, the coupling circuit 81, the coefficient circuit 84, and the observation operation 85 in this order. The superposition circuit 80 is a Hadamard gate operation similar to the superposition circuit 50 described above.

[0080] The coupling circuit 81 may include a basic function generation operation 82 and a translation circuit 83. The basic function generation operation 82 includes two control function generation operations 821. Each of the two control function generation operations 821 is composed of a controlled rotation gate operation CRy that acts on the computation qubit 321 in the initial state, and a controlled NOT gate operation 822 that serves as a common control bit for the computation qubit 321. Here, since the two expansion functions are Lorentz functions with different parameters, the rotation gate operation Ry included in each of the basic function generation operations 7 of the two expansion functions is a rotation gate operation CRy that acts on the computation qubit 321 in the initial state, and a control ... t (0) ,2θ t (1)and . On the other hand, the controlled NOT gate operation included in the two elementary function generation operations 7 is common. Therefore, the rotate gate operation Ry is an inherent operation specific to each elementary function generation operation 7, and the controlled NOT gate operation is a common operation. Therefore, in this embodiment, the processor 23 converts the rotate gate operation Ry, which is an inherent operation, into a control gate operation in which the auxiliary bit 322 is the target bit, and the controlled NOT gate operation, which is a common operation, is a gate operation in which the auxiliary bit 322 is not used as the control bit. Note that "not using the auxiliary bit 322 as the control bit" here means that the auxiliary bit 322 assigned as the target to be acted upon by the coefficient circuit 84 is not used as the control bit, and does not exclude the use of the auxiliary bit 322 originally provided in the elementary function generation operation 7 as the control bit.

[0081] The translation circuit 83 is composed of a controlled phase gate operation 831 and a QFT operation 832. In this case, it should be noted that the translation circuit 83 does not include an inverse QFT operation corresponding to the QFT operation 832. In other words, when the expansion function is a Lorentz function, the processor 23 generates the encoding circuit 8 so as to include, instead of the translation circuit 53, the translation circuit 83 as a quantum circuit that includes at least one controlled phase gate operation 831 and a quantum Fourier transform operation 832 and does not include an inverse quantum Fourier transform operation. With this configuration, it is possible to reduce the number of quantum operations when performing quantum operations on an analysis object that can be expressed using a Lorentz function.

[0082] The coefficient circuit 84 has a configuration similar to that of the coefficient circuit 54, and in this embodiment is implemented as a rotation gate operation Ry set so that the rotation angle is −2arctan(c1 / c2), where c1 and c2 are expansion coefficients of the respective expansion functions.

[0083] Observation operation 85 is similar to observation operation 55. When observation operation 85 observes an auxiliary bit 322 of |0>, a state |Ψ representing the desired linear combination coupled to the |0> state is obtained. lc > is encoded on the computation qubit 321. |Ψ lc> is formulated as follows by expressing the Lorentz functions as two expansion functions in ket form |L;a0,k0>,|L;a1,k1>.

number

[0084] In this way, by adopting this encoding method, any analysis target can be encoded as a linear combination of any expansion functions, and a mathematical model can be encoded as a quantum state. This reduces the amount of work required to design a quantum circuit for encoding compared to designing a new encoding circuit from scratch for each mathematical model.

[0085] 4. Results of encoding methods Next, as an example of the results of executing the encoding method, the observation result of the state of the computation qubit 321 of the quantum computer 3 generated based on the encoding circuit 8 shown in Fig. 7 will be described. In this chapter, |Ψ lc> onto the computation qubit 321. Note that the parameters included in Equation 13 are a0 = a1 = 0.5, k0 = 0, k1 = 8, and c0 = c1 = 1 / √2, and the parameters {θ}, {φ}, etc. included in each encoding circuit 8 are also set to correspond to the above parameters. In this experiment, the encoding circuit 8 was executed on eight quantum computers available through the IBM Quantum Platform provided by IBM: ibmq_jakarta, ibmq_lima, ibmq_manla, ibmq_quito, bim_nairobi, ibm_perth, ibmq_belem, and ibm_lagos. Of the observation results of the state of the computation qubit 321 output as a result, only the results when the observation result of the auxiliary bit 322 was |0> were extracted.

[0086] Figure 8 shows the observed results of the states of the computation qubits 321 in this experiment. j on the horizontal axis is an index assigned to the states of the four computation qubits 321. The vertical axis is a parameter (arbitrary constant) equivalent to the probability amplitude. Periodic boundary conditions are imposed so that j=16 coincides with j=0. In Figure 8, open circles indicate theoretical values, and closed circles indicate experimental values.

[0087] As shown in Figure 8, it has been observed that on both quantum computers, the state of a group of computation qubits consisting of four computation qubits 321 is generated as a state that has peaks at 0 and 8 and decays from each peak. This result indicates that the state of the group of computation qubits is the desired |Ψ lc >, suggesting that this encoding method can be applied when using an actual quantum computer3. [others]

[0088] The above embodiment may be modified as follows.

[0089] The encoding circuit 5 may have any configuration and is not limited to the above. FIG. 9 is a diagram showing another example of the encoding circuit. The encoding circuit 9 shown in FIG. 9 is another example of the encoding circuit 5 shown in FIG. 4. As shown in FIG. 9, the encoding circuit 9 includes a superposition circuit 90, a combination circuit 91, and a coefficient circuit 94. The encoding circuit 9 may also include an observation operation 95.

[0090] The function and configuration of the superposition circuit 90 are similar to those of the superposition circuit 50 (see FIG. 4) described above. Here, as an example, the superposition circuit 90 is defined by a Hadamard gate operation for each auxiliary bit 322.

[0091] Similar to the coupling circuit 51 (see FIG. 4) described above, the coupling circuit 91 is configured to operate on a group of computation qubits based on a group of auxiliary bits having a superposition of n2 possible states, thereby outputting a superposition state of a group of computation qubits having states corresponding to expansion functions assigned to each of the n2 possible states. In this embodiment, the coupling circuit 91 includes n2 expansion function generation operations 91(k) (where k=an integer between 0 and n2−1). Each expansion function generation operation 91(k) is configured to operate a k-th expansion function generation operation U(k) on a group of computation qubits when the state of the group of auxiliary bits is |k>, which is the k-th state among the n2 possible states. The expansion function generation operation U(k) converts the state of the inputted group of computation qubits into a state |ψ corresponding to the k-th expansion function. k >. The expansion function generating operations U(k) are connected in series with each other. The specific configuration of the expansion function generating operation U(k) is arbitrary, but for example, the expansion function generating operation U(k) includes one basic function generating operation 92 and a translation circuit 93.

[0092] The elementary function generation operation 92 included in the expansion function generation operation U(k) is configured to operate on a set of computation qubits to output a set of computation qubits having states indicative of the elementary function.

[0093] Similar to translation circuit 53, translation circuit 93 comprises a phase gate operation 931, a QFT operation 932, and an inverse QFT operation 933. However, unlike QFT operation 532 and inverse QFT operation 533 provided in translation circuit 53, QFT operation 932 and inverse QFT 933 provided in translation circuit 93 are controlled gates so as to act on the computation quantum bits in accordance with the state of the same ancillary bit group as phase gate operation 931.

[0094] The function and configuration example of the coefficient circuit 94 are similar to those of the coefficient circuit 54 described above (see FIG. 4).

[0095] The encoding circuit 9 may comprise an observation operation 95 on the auxiliary bits output via the coefficient circuit 94 .

[0096] The coefficient circuit described above is not limited to being implemented using the rotation gate operation Ry and the control rotation gate operation CRy as described above, but may be implemented using any operation, such as an inversion operation, an oracle operation, etc.

[0097] The information processing device 2 may be a classical computer, a quantum computer, or a combination thereof.

[0098] The information processing system 1 can be applied to various information processes related to quantum computation such as quantum measurement and quantum communication.

[0099] The above embodiment is not limited to the information processing system 1, and may be an information processing method, an encoding circuit generation method, or an information processing program. The encoding circuit generation method includes each step of the information processing system 1. The information processing program causes at least one computer to execute each step of the information processing system 1.

[0100] The information processing system 1 and the like may be provided in the following aspects.

[0101] (1) A method for generating an encoding circuit, the encoding circuit being a quantum circuit for encoding a group of computational quantum bits composed of a plurality of computational quantum bits, the method comprising the following steps: a model acquisition step for acquiring a mathematical model of an analysis target defined by a linear combination of n expansion functions, the mathematical model including information on expansion coefficients of the expansion functions; an assignment step for assigning n possible states observable from an ancillary bit group composed of at least one ancillary bit to each of the expansion functions; a circuit generation step for generating the encoding circuit based on the expansion coefficients and an expansion function generation operation for generating each of the expansion functions defining the mathematical model; the encoding circuit comprising a superposition circuit, a coupling circuit, and a coefficient circuit; the superposition circuit configured to operate on the ancillary bit group to output the ancillary bit group having a superposition of the n possible states; wherein the superposition state of the computation qubit is configured to be projected onto a state of the computation qubit group representing the expansion function assigned to the observed state of the ancillary bit group by performing an observation operation on the ancillary bit group; the coefficient circuit is configured to perform a unitary transformation on the ancillary bit group output from the coupling circuit to convert each of the n states superimposed on the ancillary bit group into a state including a specific state that is one of the n states, and the unitary transformation is configured to operate on the ancillary bit group so that a ratio of probability amplitudes of the specific state derived from each of the n states superimposed on the ancillary bit group matches a ratio of the expansion coefficients.

[0102] (2) The method according to (1) above, further comprising: in the analysis object acquisition step, acquiring information about the analysis object and at least one elementary function, wherein each of the elementary functions is characterized by a representative position in a state space defined by input variables of the elementary function, and configured to be convertible into at least one of the n expansion functions by translation from the representative position; in the optimization step, calculating the expansion coefficients and a movement amount representing a difference in the representative position between the elementary function and the expansion function by optimizing the mathematical model represented by a linear combination of the n expansion functions for the analysis object; in the identification step, identifying elementary function generation operations corresponding to each of the n elementary functions and translation operations corresponding to the movement amounts of each of the elementary functions, wherein the elementary function generation operations are configured to act on the computation quantum bits in a predetermined state to output the computation quantum bits having a state corresponding to one of the elementary functions; and the translation operation includes at least a phase gate operation and a quantum Fourier transform operation; and is set based on the amount of movement, the coupling circuit comprises an elementary function coupling circuit and a translation circuit, the elementary function coupling circuit includes n control function generation operations, each of the n control function generation operations is configured to act on the computation qubit group when the ancillary bit group is in a state associated with the elementary function generation operation by control gate operation of at least a part of the elementary function generation operation such that the ancillary bit group is a control bit and the computation qubit group is a target bit, and the translation circuit The quantum Fourier transform operation includes a controlled phase gate operation, a quantum Fourier transform operation, and an inverse quantum Fourier transform operation that is a Hermitian conjugate of the quantum Fourier transform operation, and each of the controlled phase gate operations is configured to act on the computation qubit group when the ancillary bit group takes a state associated with the elementary function generation operation corresponding to the amount of movement by controlling the phase gate operation to use the ancillary bit group as a control bit and the computation qubit group as a target bit, and the quantum Fourier transform operation is configured to act on the computation qubit group when the ancillary bit group takes a state associated with the elementary function generation operation corresponding to the amount of movement after the controlled phase gate operationand wherein the inverse quantum Fourier transform operation is configured to operate on the computation qubits without depending on the state of the ancillary bits, prior to the controlled phase gate operation.

[0103] With this configuration, a complex analysis target that can be expressed as a linear combination of multiple functions can be expressed as a quantum state.

[0104] (3) The method according to (2) above, wherein the basic function is a local function that is localized at the representative position.

[0105] This configuration makes it possible to easily analyze an analysis target represented by a plurality of localized elements.

[0106] (4) In the method according to (2) or (3) above, when the expansion function is a Lorentz function, the circuit generation step generates the encoding circuit so as to include, instead of the translation circuit, a quantum circuit that includes the at least one controlled phase gate operation and the quantum Fourier transform operation, but does not include the inverse quantum Fourier transform operation.

[0107] According to this configuration, when performing quantum operations on an analysis object that can be expressed using a Lorentz function, the number of quantum operations can be reduced.

[0108] (5) A method according to any one of (2) to (4) above, wherein the coefficient circuit is configured to unitarily transform the state of each of the auxiliary bits based on parameters included in a parameter group of N layers, the parameter group being an integer equal to or greater than log2(n), so that when the specific state is observed by an observation operation on the auxiliary bit group, the coefficient circuit outputs the state of the computation quantum bit group acted upon by the coupling circuit and the translation circuit as a state corresponding to a linear combination weighted by the expansion coefficient.

[0109] (6) A system for generating an encoding circuit, the system comprising at least one processor configured to execute a program so as to perform each step included in the method described in any one of (1) to (5) above.

[0110] (7) A program for generating an encoding circuit, the program causing at least one computer to execute each step of the method described in any one of (1) to (5) above.

[0111] (8) An encoding circuit is a quantum circuit configured to encode a quantum state corresponding to a mathematical model to be analyzed, the quantum state being defined by a linear combination of n expansion functions, for a group of computational quantum bits composed of a plurality of computational quantum bits, the mathematical model including information on expansion coefficients of the expansion functions, the encoding circuit comprising a superposition circuit, a coupling circuit, and a coefficient circuit, the superposition circuit being configured to output a group of auxiliary bits composed of a plurality of auxiliary bits and having a superposition of n states by acting on the group of auxiliary bits, the n states being assigned to each of the n expansion functions and being observable from the group of auxiliary bits composed of at least one auxiliary bit, the coupling circuit being configured to output the n states by acting on the group of computational quantum bits based on the group of auxiliary bits having the superposition of n states. and an encoding circuit configured to output a superposition state of the group of computation qubits having a state corresponding to the expansion function assigned to each of the n states of the group of ancillary bits, wherein the superposition state of the computation qubit is configured to be projected onto a state of the group of computation qubits representing the expansion function assigned to the observed state of the group of ancillary bits by performing an observation operation on the group of ancillary bits; the coefficient circuit is configured to perform a unitary transformation on the group of ancillary bits output from the coupling circuit to convert each of the n states superimposed on the group of ancillary bits into a state including a specific state that is one of the n states, and the unitary transformation is configured to operate on the group of ancillary bits such that a ratio of probability amplitudes of the specific state derived from each of the n states superimposed on the group of ancillary bits matches a ratio of the expansion coefficients. Of course, this is not the case.

[0112] Finally, while various embodiments of the present invention have been described, these are presented by way of example only and are not intended to limit the scope of the invention. The novel embodiments may be embodied in various other forms, and various omissions, substitutions, and modifications may be made without departing from the spirit of the invention. Such embodiments and modifications are intended to be included within the scope and spirit of the invention, as well as within the scope of the inventions and their equivalents as defined in the accompanying claims. [Explanation of symbols]

[0113] 1: Information processing system 2: Information processing equipment 20: Communication bus 21: Communications Department 22: Storage section 23: Processor 3:Quantum computer 30: Communication bus 31: Communications Department 32: Quantum memory 320: Quantum Bit 321: Computational qubits 322: Auxiliary bit 33: Quantum processor 4: User terminal 40: Communication bus 41: Communications Department 42: Memory 43: Processor 44: Display section 45: Input section 5: Encoder circuit 50: Matching circuit 51: Combined circuit 52: Basic function generation operations 53: Translation circuit 54: Coefficient circuit 55: Observation operation 6a: Equivalent circuit 6b: Equivalent circuit 7: Basic function generation operations 8: Encoder circuit 81: Superposition circuit 82: Combined circuit 83: Translation circuit 84: Coefficient circuit 85: Observation operation 9: Encoder circuit 90: Superposition circuit 91: Combined circuit 91(k): Expansion function generation operation 92: Basic function generation operations 93: Translation circuit 94: Coefficient circuit 95: Observation operations 521: Control function generation operation 531: Controlled Phase Gate Operation 532 :QFT operation 533: Inverse QFT operation 831: Controlled Phase Gate Operation 832 :QFT operation 931: Phase gate operation 932 :QFT operation 933: Inverse QFT operation

Claims

1. 1. A method of generating an encoding circuit, comprising: the encoding circuit is a quantum circuit for encoding a group of computation quantum bits configured by a plurality of computation quantum bits, The method comprises the steps of: In the model acquisition step, a mathematical model of the analysis target defined by a linear combination of n expansion functions is acquired, wherein the mathematical model includes information on expansion coefficients of the expansion functions; In the assignment step, n observable states are assigned to each of the expansion functions from an auxiliary bit group consisting of at least one auxiliary bit; In the circuit generation step, the encoding circuit is generated based on the expansion coefficients and an expansion function generation operation for generating each of the expansion functions defining the mathematical model; the encoding circuit comprises a superposition circuit, a combination circuit, and a coefficient circuit; the superposition circuit is configured to operate on the auxiliary bit group to output the auxiliary bit group having the n superposition states; the coupling circuit is configured to operate on the computation qubits based on the ancillary bits having a superposition of the n states, thereby outputting a superposition of the computation qubits having states corresponding to the expansion functions assigned to each of the n states, wherein: The superposition state of the computation qubit is configured to be projected onto a state of the computation qubit group representing the expansion function assigned to the observed state of the ancillary bit group by performing an observation operation on the ancillary bit group; the coefficient circuit is configured to perform a unitary transformation of each of the n states superimposed on the auxiliary bit group output from the combining circuit into a state including a specific state that is one of the n states, by operating on the auxiliary bit group output from the combining circuit; The unitary transformation is configured to operate on the group of auxiliary bits so that a ratio of probability amplitudes of the particular state derived from each of the n states superimposed on the group of auxiliary bits matches a ratio of the expansion coefficients.

2. 10. The method of claim 1, Furthermore, in the analysis object obtaining step, information about the analysis object and at least one basic function are obtained, wherein each of the basic functions is characterized by a representative position in a state space defined by input variables of the basic function, and is configured to be convertible into at least one of the n expansion functions by translation from the representative position; In the optimization step, the mathematical model represented by a linear combination of the n expansion functions is optimized for the analysis object to calculate the expansion coefficients and the movement amounts representing the difference in the representative positions between the basic functions and the expansion functions; In the specifying step, a basic function generating operation corresponding to each of the n basic functions and a translation operation corresponding to the movement amount of each of the basic functions are specified; wherein the elementary function generation operation is configured to operate on the set of computation qubits in predetermined states to output the set of computation qubits having a state corresponding to one of the elementary functions; the translation operation includes at least a phase gate operation and a quantum Fourier transform operation, and a phase shift amount of the phase gate operation is set based on the movement amount; the combining circuit comprises a basis function combining circuit and a translation circuit; the elementary function combining circuit includes n control function generation operations, each of the n control function generation operations configured to operate on the group of computation qubits when the group of auxiliary bits assumes a state associated with the elementary function generation operation by control-gating at least a portion of the elementary function generation operation such that the group of auxiliary bits is a control bit and the group of computation qubits is a target bit; the translation circuit includes at least one controlled phase gate operation, a quantum Fourier transform operation, and an inverse quantum Fourier transform operation that is a Hermitian conjugate of the quantum Fourier transform operation; each of the controlled phase gate operations is configured to operate on the computation qubit group when the ancillary bit group assumes a state associated with the elementary function generation operation corresponding to the movement amount by controlling the phase gate operation to operate on the ancillary bit group as a control bit and the computation qubit group as a target bit; the quantum Fourier transform operation is configured to operate on the computation qubits regardless of the state of the ancillary bits after the controlled phase gate operation; the inverse quantum Fourier transform operation is configured to operate on the computation qubits without regard to the states of the ancillary bits prior to the controlled phase gate operation.

3. 3. The method of claim 2, The method, wherein the basis functions are local functions localized at the representative positions.

4. 3. The method of claim 2, In the circuit generating step, when the expansion function is a Lorentzian function, the encoding circuit is generated to include, instead of the translation circuit, a quantum circuit that includes the at least one controlled phase gate operation and the quantum Fourier transform operation, but does not include the inverse quantum Fourier transform operation.

5. 3. The method of claim 2, The coefficient circuit outputs a logarithm of the state of the computation qubit group on which the coupling circuit and the translation circuit have been operated as a state corresponding to a linear combination weighted by the expansion coefficient when the specific state is observed by an observation operation on the ancillary bit group. ２ The method is configured to unitarily transform the state of each of the auxiliary bits based on parameters included in a parameter set of N layers, where N is an integer greater than or equal to (n).

6. 1. A system for generating an encoding circuit, comprising: A system comprising at least one processor configured to execute a program so as to perform each step included in the method according to any one of claims 1 to 5.

7. A program for generating an encoding circuit, A program causing at least one computer to execute each step of the method according to any one of claims 1 to 5.

8. An encoding circuit, a quantum circuit configured to encode a quantum state corresponding to a mathematical model to be analyzed, the quantum state being defined by a linear combination of n expansion functions, for a group of computational qubits composed of a plurality of computational qubits; the mathematical model includes information about expansion coefficients of the expansion function; the encoding circuit includes a superposition circuit, a combination circuit, and a coefficient circuit; the superposition circuit is configured to be composed of a plurality of auxiliary bits and to output an auxiliary bit group having n superposition states by operating on the auxiliary bit group; the n states are assigned to the n expansion functions, respectively, and are configured to be observable from an auxiliary bit group configured by at least one auxiliary bit; the coupling circuit is configured to operate on the computation qubits based on the ancillary bits having a superposition of the n states, thereby outputting a superposition of the computation qubits having states corresponding to the expansion functions assigned to each of the n states, wherein: The superposition state of the computation qubit is configured to be projected onto a state of the computation qubit group representing the expansion function assigned to the observed state of the ancillary bit group by performing an observation operation on the ancillary bit group; the coefficient circuit is configured to perform a unitary transformation of each of the n states superimposed on the auxiliary bit group output from the combining circuit into a state including a specific state that is one of the n states, by operating on the auxiliary bit group output from the combining circuit; an encoding circuit configured to operate on the group of auxiliary bits such that a ratio of probability amplitudes of the specific state derived from each of the n states superimposed on the group of auxiliary bits matches a ratio of the expansion coefficients.

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