Neural network device and membrane potential retention method

Abstract

To perform operations that imitate the behavior of a brain.SOLUTION: A neural network device according to an embodiment comprises a plurality of synapse circuits and a plurality of neuron circuits. A first neuron circuit receives synaptic current supplied to a first terminal. The first neuron circuit includes a secondary battery element, a spike generation circuit, and a reset control circuit. The secondary battery element accumulates electric charges in accordance with the synaptic current supplied to the first terminal. The spike generation circuit generates a spike signal when a membrane potential generated from the secondary battery element becomes greater than a threshold potential that is a predetermined potential. The reset control circuit releases the electric charges accumulated in the secondary battery element during a refractory period, which is a predetermined time after the spike signal has been generated.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] FIELD OF THE INVENTION The present invention relates to a neural network device and a method for maintaining a membrane potential. [Background technology]

[0002] In recent years, advances in computer hardware, such as GPUs (Graphical Processing Units), have led to rapid advances in artificial intelligence technology. For example, image recognition and classification technologies, such as CNNs (Convolutional Neural Networks), are already being used in a variety of real-world applications. Currently widely used artificial intelligence technologies are based on mathematical models that simplify the behavior of biological neural networks. For this reason, such technologies are executed using computers such as GPUs. However, executing such technologies on GPUs requires a large amount of power. In particular, the learning process, which involves extracting and storing features from large amounts of data, requires a massive amount of computation. For this reason, such learning processes require a significant amount of power, making them difficult to execute on edge devices, for example.

[0003] On the other hand, the human brain constantly learns huge amounts of data online, despite consuming only about 20 W of energy. Therefore, research is being conducted around the world into technologies that can process information by relatively faithfully reproducing brain activity using electrical circuits.

[0004] In the brain's neural network, information is transmitted from neuron (nerve cell) to neuron as signals in the form of voltage spikes. Neurons are connected by junctions called synapses. A voltage spike generated by a neuron is input to a subsequent neuron via the synapse. At this time, the strength of the voltage spike input to the subsequent neuron is adjusted by the synaptic weight, which is the connection strength of the synapse.

[0005] A synapse converts the voltage spike received from the previous neuron into a synaptic current according to the synaptic weight and provides it to the next neuron. If the synaptic weight is large, the synapse provides a large synaptic current to the next neuron, and if the synaptic weight is small, the synapse provides a small synaptic current to the next neuron.

[0006] Neurons maintain an internal electrical potential called the membrane potential. When a neuron receives a synaptic current from a synapse, it increases the membrane potential according to the magnitude of the received synaptic current. Furthermore, if no synaptic current is provided, the neuron decreases the membrane potential over time. Therefore, if a synaptic current is provided continuously for short intervals, the neuron increases its membrane potential, and if no synaptic current is provided for a long period of time, the neuron decreases the membrane potential. When the membrane potential increases and reaches the firing threshold, the neuron generates a voltage spike. The generation of a voltage spike by a neuron is called firing.

[0007] Furthermore, when a neuron fires, it returns its membrane potential to its initial potential. After returning the membrane potential to the initial potential, the neuron maintains the membrane potential at the initial potential for a certain period of time called the refractory period. In other words, during the refractory period, the neuron does not increase its membrane potential even if a synaptic current is applied. Then, after the refractory period ends, the neuron changes its membrane potential.

[0008] This type of information processing that mimics the information transmission principle of the brain's neural circuit network is called a spiking neural network. Spiking neural networks process information without performing numerical calculations, but rather by increasing or decreasing membrane potential in response to voltage spikes, generating voltage spikes, and transmitting voltage spikes through synapses. Conventional artificial intelligence required a huge amount of calculation for learning operations. In contrast, spiking neural networks do not perform numerical calculations, and are therefore thought to be able to process data efficiently. For these reasons, there has been active research in recent years into implementing spiking neural networks on semiconductor chips.

[0009] When a spiking neural network is implemented on a semiconductor chip, neurons are realized using analog circuits, including resistors, capacitors, and comparators. This circuit stores electrical charge in a capacitor according to the received synaptic current, and uses the voltage generated by the charge stored in the capacitor as the membrane potential. The brain's operating time, i.e., the neuron firing interval, is several microseconds, making it much slower than digital processing circuits such as central processing units (CPUs). Therefore, when a spiking neural network is implemented on a semiconductor chip, neurons must be realized using circuits that fire infrequently. To achieve this behavior using analog circuits, the capacitance of the capacitors must be large, and the resistance of the resistors that leak charge from the capacitors must be large. Specifically, the capacitors used in neurons must have a capacitance of 10 pF or more. The resistors that leak charge from the capacitors must have a resistance of 100 MΩ or more.

[0010] However, current CMOS (Complementary Metal Oxide Semiconductor) technology has limitations on the maximum capacitance of capacitors and the maximum value of resistors due to issues with integration area and operating speed, making it difficult to integrate sufficient capacitance and resistance to implement a spiking neural network. For this reason, in order to make a spiking neural network implemented on a semiconductor chip operate appropriately in a way that mimics the brain's behavior, it was necessary to increase the capacitance of the capacitors and the resistance values. [Prior art documents] [Non-patent literature]

[0011] [Non-Patent Document 1] Shih-Chii Liu, Tobi Delbruck, Giacomo Indiveri, Adrian Whatley, Rodney Douglas, “Event-Based Neuromorphic Systems Chapter 7 Silicon Neurons”, 26 December 2014, John Wiley & Sons, ISBN:9780470018491 Summary of the Invention [Problem to be solved by the invention]

[0012] The problem to be solved by the present invention is to provide a neural network device and a method for maintaining membrane potential that can perform operations that mimic those of the brain. [Means for solving the problem]

[0013] A neural network device according to an embodiment includes a plurality of synapse circuits and a plurality of neuron circuits. A synapse weight is set for each of the plurality of synapse circuits. Each of the plurality of neuron circuits generates a spike signal. Each of the plurality of synapse circuits acquires the spike signal from one of the plurality of neuron circuits, and when acquiring the spike signal, outputs a synapse current according to the set synapse weight. A first neuron circuit among the plurality of neuron circuits receives the synapse current from one or more first synapse circuits among the plurality of synapse circuits at a first terminal. The first neuron circuit includes a secondary battery element, a spike generation circuit, and a reset control circuit. The secondary battery element accumulates charge according to the synapse current supplied to the first terminal. The spike generation circuit generates the spike signal when a membrane potential generated by the secondary battery element is greater than a predetermined threshold potential. The reset control circuit discharges the charge stored in the secondary battery element during a refractory period, which is a predetermined time after the spike signal is generated. [Brief explanation of the drawings]

[0014] [Figure 1] FIG. 1 is a diagram illustrating the configuration of a neural network device. [Figure 2] FIG. 1 is a diagram illustrating the configuration of a reservoir computing device. [Figure 3] A diagram showing the peripheral connections of a neuron circuit. [Figure 4] Schematic diagram of the first neuron circuit. [Figure 5] FIG. 2 is a diagram showing the layer structure of a secondary battery element. [Figure 6] FIG. 10 is a configuration diagram of a first neuron circuit according to a second embodiment. [Figure 7] FIG. 2 is a diagram showing the layer structure of an electron ion resistance element. [Figure 8] FIG. 10 is a configuration diagram of a first neuron circuit according to the third embodiment. [Figure 9] FIG. 10 is a configuration diagram of a first neuron circuit according to the fourth embodiment. [Figure 10] FIG. 11 is a configuration diagram of a first neuron circuit according to the fifth embodiment. [Figure 11] FIG. 13 is a configuration diagram of a first neuron circuit according to the sixth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0015] A neural network device 10 according to an embodiment will be described below with reference to the drawings.

[0016] (First embodiment) The neural network device 10 according to the first embodiment is a spiking neural network configured by hardware. For example, the neural network device 10 is implemented in a semiconductor device by a process such as CMOS.

[0017] 1 is a diagram showing an example of the configuration of a neural network device 10. The neural network device 10 according to the first embodiment includes, as an example, M-stage (M is an integer equal to or greater than 2) layers 12 and (M−1) synapse groups 14.

[0018] Each of the (M-1) synapse groups 14 includes a plurality of synapse circuits 20. A synapse weight is set for each of the plurality of synapse circuits 20. The synapse weights set for the plurality of synapse circuits 20 are set by a learning process. For example, the synapse weights set for the plurality of synapse circuits 20 may be updated according to a predetermined update rule such as STDP (Spike Timing Dependent Plasticity) or SDSP (Spike Driven Synaptic Plasticity). Each of the M layers 12 includes a plurality of neuron circuits 22. Each of the plurality of neuron circuits 22 generates a spike signal, which is a pulse-shaped voltage signal.

[0019] The mth synapse group 14 (m is an integer greater than or equal to 1 and less than or equal to (M-1)) of the (M-1) synapse groups 14 is arranged between the mth layer 12 of the M layers 12 and the (m+1)th layer 12 of the M layers 12.

[0020] Each of the plurality of synapse circuits 20 included in the m-th synapse group 14 acquires a spike signal output from one of the plurality of neuron circuits 22 included in the m-th layer 12. When acquiring a spike signal, each of the plurality of synapse circuits 20 included in the m-th synapse group 14 outputs a synapse current according to a set synapse weight. Note that the synapse weight may be expressed as a binary value or a multi-value discrete value of three or more values. Furthermore, the synapse weight may be expressed as an analog value represented by the amount of charge stored in a capacitor or the like or the resistance value of a variable resistor.

[0021] Each of the plurality of synapse circuits 20 included in the m-th synapse group 14 provides a synapse current to one of the plurality of neuron circuits 22 included in the (m+1)-th layer 12.

[0022] Each of the neuron circuits 22 included in the (m+1)th layer 12 among the M layers 12 acquires a plurality of synaptic currents output from the mth synapse group 14 and performs a process equivalent to a product-sum operation on the acquired synaptic currents. The first layer 12 among the M layers 12 acquires a plurality of signals from an external device or an input layer. Each of the neuron circuits 22 outputs a spike signal obtained by performing a process equivalent to an activation function on the signal representing the operation result.

[0023] In such a neural network device 10, the first layer 12 receives one or more signals from an external device or an input layer. Then, the neural network device 10 outputs one or more signals representing the results of performing a neural network operation on the received one or more signals from the Mth layer 12.

[0024] The neural network device 10 may also include a separate control circuit. The control circuit controls, for example, a learning threshold used in the learning process of the synaptic weights set in each of the plurality of synapse circuits 20, based on spike signals output from each of the plurality of neuron circuits 22. The control circuit may also control the input and output of data related to the neural network device 10.

[0025] FIG. 2 is a diagram showing the configuration of the reservoir computing device 24.

[0026] The neural network device 10 is not limited to a structure that transfers signals in a forward direction as shown in Fig. 1, but may be a recurrent neural network that internally feeds back signals. When the neural network device 10 is a recurrent neural network, it can be applied to, for example, a reservoir computing device 24 as shown in Fig. 2.

[0027] The reservoir computing device 24 includes an input layer 26, a neural network device 10 that is a recurrent neural network, and an output layer 28.

[0028] The input layer 26 receives one or more signals from an external device and outputs the received one or more signals to the neural network device 10. The output layer 28 receives one or more spike signals from the neural network device 10 and outputs one or more signals to the external device.

[0029] Each of the plurality of neuron circuits 22 included in the neural network device 10 acquires a plurality of synaptic currents from some of the plurality of synapse circuits 20 included in the neural network device 10. Some of the plurality of neuron circuits 22 acquire signals from the input layer 26. Some of the plurality of neuron circuits 22 output spike signals to the output layer 28.

[0030] Each of the plurality of synapse circuits 20 acquires a spike signal output from any one of the plurality of neuron circuits 22. Each of the plurality of synapse circuits 20 outputs a synapse current to any one of the plurality of neuron circuits 22.

[0031] At least one of the multiple synapse circuits 20 feeds back a synapse current and outputs it to itself or another neuron circuit 22. That is, at least one of the multiple synapse circuits 20 outputs a synapse current to itself, the neuron circuit 22 that provided a spike signal to itself, or a neuron circuit 22 that is located in a stage preceding the neuron circuit 22 that provided a spike signal to itself.

[0032] The reservoir computing device 24 configured in this manner can function as a hardware device that performs reservoir computing.

[0033] FIG. 3 is a diagram showing the connections around the neuron circuit 22.

[0034] Each of the plurality of synapse circuits 20 acquires a spike signal from one of the plurality of neuron circuits 22. Each of the plurality of synapse circuits 20 has a current generating circuit. When each of the plurality of synapse circuits 20 acquires a spike signal, it converts the acquired spike signal using the current generating circuit into a synapse current according to the set synapse weight, and outputs the synapse current to the downstream neuron circuit 22. The larger the set synapse weight of each of the plurality of synapse circuits 20, the larger the amplitude of the output synapse current. Furthermore, for example, the larger the set synapse weight of each of the plurality of synapse circuits 20, the more frequently the synapse current is output.

[0035] Each of the multiple neuron circuits 22 generates a membrane potential V mem When the neuron circuit 22 acquires a synaptic current from any of the multiple synapse circuits 20 connected in the previous stage, it generates a membrane potential V mem Furthermore, if no synaptic current is acquired, each of the neuron circuits 22 increases the membrane potential V memTherefore, if each of the neuron circuits 22 continues to repeatedly acquire synaptic currents at short time intervals, the membrane potential V mem If synaptic current is not acquired for a long period of time, the membrane potential V mem Each of the neuron circuits 22 decreases the membrane potential V mem When the membrane potential V reaches a predetermined initial potential, mem Stop the descent.

[0036] Each of the neuron circuits 22 generates a membrane potential V mem rises and the threshold potential V th When the value reaches , it fires and outputs a spike signal to the subsequent synapse circuit 20.

[0037] Furthermore, when each of the neuron circuits 22 fires, a membrane potential V mem Each of the neuron circuits 22 does not return the membrane potential V to the initial potential during a refractory time, which is a predetermined time after firing, even if a synaptic current is applied. mem After the refractory period ends, each of the neuron circuits 22 starts accumulating electric charges according to the synaptic current. The initial electric potential is the threshold electric potential V th The initial potential and threshold potential V th is preset.

[0038] 4 is a diagram showing the configuration of a first neuron circuit 30, which is one of the plurality of neuron circuits 22. All of the plurality of neuron circuits 22 may have the same configuration as the first neuron circuit 30, or some of the plurality of neuron circuits 22 may have the same configuration as the first neuron circuit 30.

[0039] The first neuron circuit 30 is connected in a preceding stage to one or more first synapse circuits 32 among the plurality of synapse circuits 20. The first neuron circuit 30 has a first terminal 34. The first neuron circuit 30 receives a synapse current from one or more first synapse circuits 32 connected in a preceding stage to the first neuron circuit 30.

[0040] The first neuron circuit 30 includes a charge storage circuit 40, a decision circuit 42, a spike generation circuit 44, a reset control circuit 46, and a reset circuit 48.

[0041] The charge storage circuit 40 stores a charge corresponding to the synaptic current supplied to the first terminal 34. The charge storage circuit 40 generates a membrane potential V mem Therefore, the charge storage circuit 40 generates a membrane potential V at the first terminal 34 every time a synaptic current is supplied. mem Increases.

[0042] Furthermore, the charge storage circuit 40 reduces the stored charge over time. Therefore, when no synaptic current is supplied, the charge storage circuit 40 generates a membrane potential V mem is decreased over time.

[0043] In this embodiment, the charge storage circuit 40 includes a secondary battery element 50 and a leak circuit 52 .

[0044] The secondary battery element 50 is a thin-film solid-state secondary battery mounted on a semiconductor device. The secondary battery element 50 generates a voltage corresponding to the accumulated charge. When charging, the secondary battery element 50 accumulates a charge corresponding to the given synapse current. When discharging, the secondary battery element 50 releases a charge corresponding to the released current. The secondary battery element 50 is connected between the first terminal 34 and the ground terminal, and is supplied with the synapse current supplied to the first terminal 34.

[0045] The leak circuit 52 is connected in parallel between the two terminals of the secondary battery element 50. The leak circuit 52 causes a leak current to flow from the secondary battery element 50 to the ground terminal, thereby leaking the charge accumulated in the secondary battery element 50. In this embodiment, the leak circuit 52 includes a resistive element 54 mounted on the semiconductor device. The resistive element 54 is connected between the first terminal 34 and the ground terminal. The magnitude of the leak current flowing from the leak circuit 52 is determined by the resistance value of the resistive element 54 and the membrane potential V generated by the secondary battery element 50. mem The resistance element 54 has a relatively large resistance value, for example, 100 MΩ or more, and takes a sufficiently long time to release the charge accumulated in the secondary battery element 50. Alternatively, the resistance element 54 may be formed of a transistor. In this case, the leakage current value is determined by the gate voltage of the transistor.

[0046] The determination circuit 42 determines the membrane potential V generated from the secondary battery element 50. mem and a preset threshold potential V th Compared with the membrane potential V mem is the threshold potential V th The determination circuit 42 is, for example, a comparator 56 mounted on a semiconductor device. The comparator 56 has an inverting input terminal connected to a threshold potential V th is applied, and the non-inverting input terminal is connected to the first terminal 34. Then, the determination circuit 42 determines the membrane potential V mem is the threshold potential V th If it is determined to be greater than the threshold, the logic becomes H and the membrane potential V mem is the threshold potential V th If it is determined that the value is not greater than the threshold, a determination signal with logic L is output.

[0047] The spike generating circuit 44 receives the determination signal from the determination circuit 42 and calculates the membrane potential V mem is the threshold potential V th If it is determined that the first neuron circuit 30 is greater than the first neuron circuit 30, the spike generating circuit 44 generates a spike signal, which is a pulse-shaped voltage signal. The spike generating circuit 44 supplies the generated spike signal to the synapse circuit 20 connected in the subsequent stage of the first neuron circuit 30.

[0048] The reset control circuit 46 outputs a reset signal during the refractory period after the spike generation circuit 44 outputs a spike signal. The refractory period is a predetermined time from the timing of the trailing edge of the pulse-like spike signal. For example, the reset control circuit 46 outputs a reset signal that is logic H during the refractory period and logic L during periods other than the refractory period.

[0049] When a spike signal is generated, the reset circuit 48 releases the charge accumulated in the secondary battery element 50 and connects the first terminal 34 to the ground terminal during the non-refractory period. In this embodiment, when a reset signal of logic L is output from the reset control circuit 46, the reset circuit 48 disconnects the first terminal 34 from the ground terminal and shorts the first terminal 34 from the ground terminal while a reset signal of logic H is output from the reset control circuit 46. The reset circuit 48 may be realized, for example, by a MOSFET (metal-oxide-semiconductor field-effect transistor) that is turned on or off in response to the reset signal.

[0050] When a spike signal is generated, the reset circuit 48 discharges the charge accumulated in the secondary battery element 50 to the ground terminal, thereby reducing the membrane potential V mem The reset circuit 48 can return the membrane potential V generated from the secondary battery element 50 to the initial potential. In addition, the reset circuit 48 can cause the synaptic current supplied during the refractory period to flow to the ground terminal, thereby preventing charge from being accumulated in the secondary battery element 50. Furthermore, the reset circuit 48 can return the membrane potential V generated from the secondary battery element 50 to the initial potential during the refractory period. mem Alternatively, the potential of the ground terminal can be applied to the determination circuit 42 to prevent spike signals from being generated from the spike generation circuit 44. After the refractory period ends, the reset circuit 48 can stop the discharge of charge from the secondary battery element 50, allowing the secondary battery element 50 to accumulate charge corresponding to the synaptic current supplied to the first terminal 34.

[0051] FIG. 5 is a diagram showing the layer structure of the secondary battery element 50. As shown in FIG.

[0052] The secondary battery element 50 includes a first solid electrolyte layer 62, a first electrode layer 64, a second electrode layer 66, a first current collector layer 68, and a second current collector layer 70. The secondary battery element 50 has a layered structure of the first current collector layer 68, the first electrode layer 64, the first solid electrolyte layer 62, the second electrode layer 66, and the second current collector layer 70 in this order.

[0053] The first solid electrolyte layer 62 is formed of a solid electrolyte that allows ions to pass through but does not allow electrons to pass through easily. That is, the first solid electrolyte layer 62 is a solid material that allows ions to pass through but does not allow electrons to pass through easily. In this embodiment, the first solid electrolyte layer 62 is a lithium ion conductor that allows lithium ions to pass through. The first solid electrolyte layer 62 may also be a solid material that allows other ions to pass through instead of lithium ions, such as sodium ions or silver ions.

[0054] The first solid electrolyte layer 62 is made of, for example, the following materials. Li 2.9 PO 3.3 N 0.46 (LIPON) Li7La3Zr2O 12 Li 3.6 Si 0.6 P 0.4 O4 Li 1.5 Al 0.5 Ge 1.5 (PO4)3 Li 10 GeP2S 12 Li 3.25 Ge 0.25 P 0.75 S4 Li7P3S 11 Li 3.25 P 0.95 S4

[0055] The first electrode layer 64 and the second electrode layer 66 are disposed opposite each other with the first solid electrolyte layer 62 interposed therebetween. More specifically, the first electrode layer 64 and the second electrode layer 66 are disposed opposite each other in the direction of ion passage in the first solid electrolyte layer 62. Each of the first electrode layer 64 and the second electrode layer 66 is a solid material capable of containing ions that the first solid electrolyte layer 62 passes through in its lattice gaps or lattice positions. In this embodiment, each of the first electrode layer 64 and the second electrode layer 66 is a metal compound capable of containing lithium ions in its lattice gaps or lattice positions.

[0056] The first electrode layer 64 and the second electrode layer 66 have, for example, a layered structure. The first electrode layer 64 and the second electrode layer 66 may be formed of, for example, the following materials capable of containing lithium ions in the interstitial spaces: Li x TiS2(0 <x<1) Li x CoO2(0 <x<1) Li x NiO2(0 <x<1) Li x MnO2(0 <x<1) Li x Ni 0.33 Mn 0.33 Co 0.33 O2(0 <x<1) Li x Ni 0.8 Co 0.15 Al 0.05 O2(0 <x<1) Li 2-x MnO3(0 <x<1)

[0057] The first electrode layer 64 and the second electrode layer 66 may also be formed from the following materials capable of containing lithium ions at lattice sites, such as spinel: Li 1-x Mn2O4(0 <x<1) Li 1-x Co2O4(0 <x<1)

[0058] Further, the first electrode layer 64 and the second electrode layer 66 may be formed of the following materials that can contain lithium ions at lattice positions, for example, olivine. LiFePO4 LiMnPO4 LiCoPO4

[0059] Further, the first electrode layer 64 and the second electrode layer 66 may be formed of the following materials that can contain lithium ions at lattice positions, for example, tabolite. LiFeSO4F LiVPO4

[0060] Further, the first electrode layer 64 and the second electrode layer 66 may be formed of the following materials that can contain lithium ions at lattice positions, for example, rock salt spinel mixture. Li 4+3x Ti5O 12 (0<x<1)

[0061] Note that a material capable of containing lithium ions at lattice positions causes less change in lattice constant due to the entry and exit of lithium ions than a material capable of containing lithium ions in lattice gaps. In particular, Li 4+3x Ti5O 12 (0<x<1) has a lattice constant change of only a few percent between the state of x = 1 and the state of x =​​​​​​​The second current collector layer 70 is connected to the second electrode layer 66 and is made of metal. The second current collector layer 70 is formed on the surface of the second electrode layer 66 opposite to the first solid electrolyte layer 62. The second current collector layer 70 is connected to a ground terminal.

[0064] The first current collector layer 68 and the second current collector layer 70 are each formed of, for example, Au, Pt, Cu, or Ti, etc. In the following, a case will be described in which the first electrode layer 64 is a positive electrode and the second electrode layer 66 is a negative electrode.

[0065] In such a secondary battery element 50, charges move inside each of the first electrode layer 64 and the second electrode layer 66 when a synaptic current is supplied to the first terminal 34. When a synaptic current is supplied to the first terminal 34, ions contained in the first electrode layer 64 move to the second electrode layer 66 via the first solid electrolyte layer 62. As a result, the amount of accumulated charge in the secondary battery element 50 increases, and the membrane potential V mem However, if the number of ions contained in the first electrode layer 64 is zero, no ions will move even if a synaptic current is supplied to the first terminal 34, and therefore the secondary battery element 50 will not increase the membrane potential V mem Do not increase.

[0066] Furthermore, when no synaptic current is supplied to the first terminal 34 and the first current collector layer 68 and the second current collector layer 70 are connected via a short circuit or a resistor, ions move inside the first electrode layer 64 and the second electrode layer 66 in the direction opposite to that when a synaptic current is supplied to the first terminal 34. When no synaptic current is supplied to the first terminal 34 and the first current collector layer 68 and the second current collector layer 70 are connected via a short circuit or a resistor, ions contained in the second electrode layer 66 move to the first electrode layer 64 via the first solid electrolyte layer 62. As a result, the accumulated charge in the secondary battery element 50 decreases, and the membrane potential V mem Lower the

[0067] Such a secondary battery element 50 can achieve a sufficiently large effective capacitance for use in a spiking neural network, while occupying a smaller integrated area than a capacitor formed in a semiconductor device. Therefore, the neural network device 10 according to this embodiment can store a sufficiently large amount of charge and include a sufficient number of neuron circuits 22 to form a spiking neural network. Therefore, the neural network device 10 according to this embodiment can perform operations that appropriately mimic those of the brain.

[0068] (Second embodiment) Next, a neural network device 10 according to the second embodiment will be described. The neural network device 10 according to the second embodiment has substantially the same functions and configuration as the first embodiment, so the components having substantially the same functions and configurations are given the same reference numerals and descriptions thereof will be omitted except for the differences. The same applies to the third and subsequent embodiments.

[0069] FIG. 6 is a diagram showing the configuration of the first neuron circuit 30 according to the second embodiment.

[0070] The leak circuit 52 according to the second embodiment includes an electron ion resistance element 72 instead of the resistance element 54. The electron ion resistance element 72 has a layer structure similar to that of the secondary battery element 50, but is an element that does not generate electromotive force. Furthermore, the resistance value of the electron ion resistance element 72 is adjusted so that a desired current flows when connected in parallel to the secondary battery element 50. The leak circuit 52 according to the second embodiment may include the resistance element 54 and the electron ion resistance element 72.

[0071] FIG. 7 is a diagram showing the layer structure of the electron ion resistance element 72. As shown in FIG.

[0072] The electronic ion resistance element 72 includes a second solid electrolyte layer 74, a third electrode layer 76, a fourth electrode layer 78, a third current collector layer 80, and a fourth current collector layer 82. The electronic ion resistance element 72 has a layer structure in the order of the third current collector layer 80, the third electrode layer 76, the second solid electrolyte layer 74, the fourth electrode layer 78, and the fourth current collector layer 82.

[0073] The second solid electrolyte layer 74 is formed of a solid electrolyte that allows ions to pass through and hardly allows electrons to pass through. The second solid electrolyte layer 74 has the same configuration as the first solid electrolyte layer 62 of the secondary battery element 50.

[0074] The third electrode layer 76 and the fourth electrode layer 78 are provided to face each other with the second solid electrolyte layer 74 interposed therebetween. More specifically, the third electrode layer 76 and the fourth electrode layer 78 are provided to face each other with respect to the direction of ion passage in the second solid electrolyte layer 74. Each of the third electrode layer 76 and the fourth electrode layer 78 is a solid substance capable of containing the ions passed through by the second solid electrolyte layer 74 in the interstices or lattice positions of the lattice. The third electrode layer 76 has the same configuration as the first electrode layer 64 of the secondary battery element 50. The fourth electrode layer 78 has the same configuration as the second electrode layer 66 of the secondary battery element 50.

[0075] However, the third electrode layer 76 and the fourth electrode layer 78 are made of the same substance so as not to generate an electromotive force. For example, the third electrode layer 76 and the fourth electrode layer 78 are a rock salt spinel mixture, Li 4+3x Ti5O 12 (0 < x < 1).

[0076] The third current collector layer 80 is connected to the third electrode layer 76 and is formed of a metal. The third current collector layer 80 is formed on the surface of the third electrode layer 76 opposite to the second solid electrolyte layer 74. The third current collector layer 80 is connected to the first terminal 34.

[0077] The fourth current collector layer 82 is connected to the fourth electrode layer 78 and is made of metal. The fourth current collector layer 82 is formed on the surface of the fourth electrode layer 78 opposite to the second solid electrolyte layer 74. The fourth current collector layer 82 is connected to a ground terminal.

[0078] The third current collector layer 80 and the fourth current collector layer 82 are each formed of, for example, Au, Pt, Cu, or Ti.

[0079] Such an electron ion resistance element 72 can achieve a resistance value large enough for use in a spiking neural network, while occupying a smaller integration area than resistors formed in a semiconductor device. Therefore, the neural network device 10 according to this embodiment can include a sufficient number of neuron circuits 22 to constitute a spiking neural network, while keeping the leakage current of each circuit sufficiently small. Therefore, the neural network device 10 according to this embodiment can perform operations that appropriately mimic the operation of the brain.

[0080] (Third embodiment) Next, a neural network device 10 according to a third embodiment will be described.

[0081] FIG. 8 is a diagram showing the configuration of the first neuron circuit 30 according to the third embodiment.

[0082] Unlike the first embodiment, the charge storage circuit 40 according to the third embodiment does not include a leak circuit 52. Therefore, the secondary battery element 50 according to the third embodiment does not release charge during periods other than the refractory period, and the membrane potential V mem The neuron firing model includes a leak-induced membrane potential V mem There is also a model that does not consider the drop in membrane potential V due to such leakage. mem It is possible to realize a model that does not take into account the decline of

[0083] (Fourth embodiment) Next, a neural network device 10 according to a fourth embodiment will be described.

[0084] FIG. 9 is a diagram showing the configuration of the first neuron circuit 30 according to the fourth embodiment.

[0085] The first neuron circuit 30 according to the fourth embodiment further comprises a disconnection control circuit 86, a disconnection circuit 88, and a discharge circuit 90.

[0086] The disconnection control circuit 86 stops the accumulation of electric charge by the secondary battery element 50 according to the synaptic current supplied to the first terminal 34 during the period when a spike signal is generated from the spike generation circuit 44 and during the refractory period. For example, the disconnection control circuit 86 disconnects the secondary battery element 50 from the first terminal 34 during the period when a spike signal is generated from the spike generation circuit 44 and during the refractory period.

[0087] In the present embodiment, the disconnection control circuit 86 may be a NOR logic circuit 92. The NOR logic circuit 92 receives the spike signal from the spike generating circuit 44 and receives the reset signal from the reset control circuit 46. The NOR logic circuit 92 then outputs a disconnection control signal that is logic L when the spike signal is logic H or when the reset signal is logic H, and that is logic H when the spike signal is logic L and the reset signal is logic L.

[0088] The disconnection circuit 88 disconnects the first terminal 34 from the secondary battery element 50 during the period when a spike signal is generated from the spike generation circuit 44 and during the refractory period. The disconnection circuit 88 also shorts the first terminal 34 from the secondary battery element 50 when the period when a spike signal is not generated from the spike generation circuit 44 and the refractory period is not in progress. For example, the disconnection circuit 88 disconnects the first terminal 34 from the secondary battery element 50 when the disconnection control signal is at a logical L, and shorts the first terminal 34 from the secondary battery element 50 when the disconnection control signal is at a logical H. For example, the disconnection circuit 88 may be implemented by a MOSFET or the like that functions as a switch that is turned on or off in response to the disconnection control signal.

[0089] The refractory period is a predetermined time after the end of the spike signal generation. Therefore, the reset circuit 48 does not connect the first terminal 34 to the ground terminal while the spike signal is generated, i.e., while the spike signal is at logic H. Therefore, in the first embodiment, if a synapse current is supplied while the spike signal is generated, charge will accumulate in the secondary battery element 50.

[0090] In contrast, in this embodiment, the secondary battery element 50 is disconnected from the first terminal 34 during the period when a spike signal is generated. Therefore, the disconnection control circuit 86 and the disconnection circuit 88 can prevent charge from accumulating in the secondary battery element 50 even if a synaptic current is supplied during the period when a spike signal is generated. As a result, the disconnection control circuit 86 and the disconnection circuit 88 can shorten the discharge time of the secondary battery element 50.

[0091] The discharge circuit 90 discharges the charge accumulated in the secondary battery element 50 during the period when a spike signal is generated from the spike generation circuit 44 and during the refractory period. For example, when the disconnection control signal is logic H, the discharge circuit 90 connects the terminal of the secondary battery element 50 that is not connected to the ground terminal to the ground terminal. When the disconnection control signal is logic L, the discharge circuit 90 disconnects the terminal of the secondary battery element 50 that is not connected to the ground terminal from the ground terminal. The discharge circuit 90 may be realized by an inverting circuit that inverts the logic of the disconnection control signal and a MOSFET or the like that functions as a switch that turns on or off depending on the output signal of the inverting circuit.

[0092] The discharge circuit 90 may switch whether or not to release the charge accumulated in the secondary battery element 50, depending on the reset signal. For example, when the reset signal is at logic H, the discharge circuit 90 may connect the terminal of the secondary battery element 50 that is not connected to the ground terminal to the ground terminal. Furthermore, when the reset signal is at logic L, the discharge circuit 90 may disconnect the terminal of the secondary battery element 50 that is not connected to the ground terminal from the ground terminal.

[0093] Such a discharge circuit 90 can discharge the charge accumulated in the secondary battery element 50 during the period when a spike signal is generated from the spike generating circuit 44. This allows the discharge circuit 90 to discharge the charge accumulated in the secondary battery element 50 before the refractory period, thereby shortening the discharge time.

[0094] In the fourth embodiment, the charge storage circuit 40 may be configured to include the electron ion resistance element 72 as in the second embodiment, or may be configured not to include the resistance element 54 as in the third embodiment.

[0095] (Fifth embodiment) Next, a neural network device 10 according to the fifth embodiment will be described.

[0096] FIG. 10 is a diagram showing the configuration of the first neuron circuit 30 according to the fifth embodiment.

[0097] The charge storage circuit 40 according to the fifth embodiment further includes a disconnection control circuit 86, a disconnection circuit 88, a reset potential generation circuit 94, and a regulated discharge circuit 96.

[0098] The disconnection control circuit 86 and the disconnection circuit 88 according to the fifth embodiment have the same configuration as those in the fourth embodiment.

[0099] The reset potential generating circuit 94 generates a predetermined reset potential V r For example, the reset potential generating circuit 94 generates a reset potential Vr The reset potential V r is the threshold potential V th It is a voltage lower than the potential of the ground terminal.

[0100] The regulated discharge circuit 96 discharges the charge accumulated in the secondary battery element 50 during the period when the spike signal is generated from the spike generating circuit 44 and during the refractory period. At the same time, the regulated discharge circuit 96 controls the discharge of the charge generated from the secondary battery element 50 in accordance with the membrane potential V mem is the reset potential V r Stop the process when this occurs.

[0101] For example, when the disconnection control signal is at logic H, the regulated discharge circuit 96 connects the terminal of the secondary battery element 50 that is not connected to the ground terminal to a reset potential V r When the disconnection control signal is at logic L, the regulated discharge circuit 96 connects the terminal of the secondary battery element 50 that is not connected to the ground terminal to a reset potential V r For example, the regulated discharge circuit 96 may be realized by an inverting circuit that inverts the logic of the disconnection control signal and a MOSFET or the like that functions as a switch that is turned on or off by the output signal of the inverting circuit. Such a regulated discharge circuit 96 is configured to control the membrane potential V during the period when the spike signal is generated and the refractory period. mem The drop of the reset potential V r It can be stopped by.

[0102] The frequency of neuronal firing is determined by the threshold voltage V th The membrane potential V is determined by the potential difference between the initial potential and the membrane potential V, and the total current per unit time given by the synapse. Therefore, the initial potential does not have to be the potential of the ground terminal as long as it is a predetermined potential. mem The initial potential is reset to V r This allows the first neuron circuit 30 to fire at an appropriate frequency so as to mimic the operation of the brain.

[0103] The regulated discharge circuit 96 may switch whether or not to discharge the charge accumulated in the secondary battery element 50, depending on the reset signal. For example, when the reset signal is at logic H, the regulated discharge circuit 96 connects the terminal of the secondary battery element 50 that is not connected to the ground terminal to a reset potential V r When the reset signal is at logic L, the discharge circuit 90 may connect the terminal of the secondary battery element 50 that is not connected to the ground terminal to a reset potential V r may be disconnected from

[0104] In the fifth embodiment, the disconnection circuit 88 may be operated by an inverted signal of the reset signal instead of the disconnection control signal. That is, in the fifth embodiment, the disconnection circuit 88 may disconnect the first terminal 34 and the secondary battery element 50 during the refractory period.

[0105] In the fifth embodiment, the charge storage circuit 40 may be configured to include the electron ion resistance element 72 as in the second embodiment, or may be configured not to include the resistance element 54 as in the third embodiment.

[0106] (Sixth embodiment) Next, a neural network device 10 according to a sixth embodiment will be described.

[0107] FIG. 11 is a diagram showing the configuration of the first neuron circuit 30 according to the sixth embodiment.

[0108] The first neuron circuit 30 according to the sixth embodiment includes a determination circuit 42, a spike generation circuit 44, a reset control circuit 46, a reset circuit 48, a disconnection control circuit 86, N charge storage circuits 40-1 to 40-N, a selection circuit 98, N AND circuits 100-1 to 100-N, N disconnection circuits 88-1 to 88-N, a reset potential generation circuit 94, and N regulated discharge circuits 96-1 to 96-N. Note that the spike generation circuit 44, the reset control circuit 46, and the reset circuit 48 are not shown in FIG.

[0109] The disconnection control circuit 86 has the same configuration as that in the fourth embodiment.

[0110] Each of the N charge storage circuits 40-1 to 40-N has the same configuration as the charge storage circuit 40 according to any one of the first to third embodiments.

[0111] The selection circuit 98 selects any one of the N states from the first state to the Nth state.

[0112] In the first state, the potential generated by the secondary battery element 50 included in the first charge storage circuit 40-1 of the N charge storage circuits 40-1 to 40-N is set to a membrane potential V mem and accumulates the synaptic current supplied to the first terminal 34 in the secondary battery element 50 included in the first charge accumulation circuit 40-1. Furthermore, the first state is a state in which the charges accumulated in the secondary battery elements 50 included in the charge accumulation circuits 40 other than the first charge accumulation circuit 40-1 among the N charge accumulation circuits 40-1 to 40-N are released.

[0113] In the second state, the potential generated from the secondary battery element 50 included in the second charge storage circuit 40-2, which is different from the first charge storage circuit 40-1 among the N charge storage circuits 40-1 to 40-N, is set as a membrane potential V mem and accumulates the synaptic current supplied to the first terminal 34 in the secondary battery element 50 included in the second charge accumulation circuit 40-2. Furthermore, the second state is a state in which the charges accumulated in the secondary battery elements 50 included in the charge accumulation circuits 40 other than the second charge accumulation circuit 40-2 among the N charge accumulation circuits 40-1 to 40-N are released.

[0114] That is, in the n-th state (n is an integer of 1 or more and N or less) of the N states, the potential generated from the secondary battery element 50 included in the n-th charge storage circuit 40-n is set to the membrane potential V memand accumulates the synaptic current supplied to the first terminal 34 in the secondary battery element 50 included in the n-th charge accumulation circuit 40-n. Furthermore, the n-th state is a state in which the charges accumulated in the secondary battery elements 50 included in the charge accumulation circuits 40 other than the n-th charge accumulation circuit 40-n among the N charge accumulation circuits 40-1 to 40-N are released.

[0115] Such a selection circuit 98 outputs N state selection signals. The N state selection signals include a first state selection signal through an Nth state selection signal. When selecting the first state, the selection circuit 98 sets the first state selection signal to logic H, and sets the state selection signals of the N state selection signals other than the first state selection signal to logic L. When selecting the second state, the selection circuit 98 sets the second state selection signal to logic H, and sets the state selection signals of the N state selection signals other than the second state selection signal to logic L. Then, when selecting the nth state, the selection circuit 98 sets the nth state selection signal to logic H, and sets the state selection signals of the N state selection signals other than the nth state selection signal to logic L.

[0116] Each of the N AND circuits 100-1 to 100-N receives the disconnection control signal output from the disconnection control circuit 86.

[0117] The first AND circuit 100-1 of the N AND circuits 100-1 to 100-N further acquires a first state selection signal and outputs a first disconnection control signal representing the logical AND of the disconnection control signal and the first state selection signal. The second AND circuit 100-2 of the N AND circuits 100-1 to 100-N further acquires a second state selection signal and outputs a second disconnection control signal representing the logical AND of the disconnection control signal and the second state selection signal. The nth AND circuit 100-n of the N AND circuits 100-1 to 100-N further acquires an nth state selection signal and outputs an nth disconnection control signal representing the logical AND of the disconnection control signal and the nth state selection signal.

[0118] A first disconnection circuit 88-1 of the N disconnection circuits 88-1 to 88-N shorts the first terminal 34 and the secondary battery element 50 included in the first charge storage circuit 40-1 in a first state, and disconnects the first terminal 34 and the secondary battery element 50 included in the first charge storage circuit 40-1 in states other than the first state among the N states. A second disconnection circuit 88-2 of the N disconnection circuits 88-1 to 88-N shorts the first terminal 34 and the secondary battery element 50 included in the second charge storage circuit 40-2 in a second state, and disconnects the first terminal 34 and the secondary battery element 50 included in the second charge storage circuit 40-2 in states other than the second state among the N states. The nth disconnection circuit 88-n among the N disconnection circuits 88-1 to 88-N shorts the first terminal 34 and the secondary battery element 50 included in the nth charge storage circuit 40-n in the nth state, and disconnects the first terminal 34 and the secondary battery element 50 included in the nth charge storage circuit 40-n in states other than the nth state among the N states.

[0119] Furthermore, each of the N disconnecting circuits 88-1 to 88-N disconnects the first terminal 34 from the secondary battery element 50 included in the corresponding charge storage circuit 40 during the period when a spike signal is generated from the spike generating circuit 44 and during the refractory period.

[0120] For example, when the first disconnection control signal output from the first AND circuit 100-1 is logic H, the first disconnection circuit 88-1 shorts the first terminal 34 and the secondary battery element 50 included in the first charge storage circuit 40-1, and when the first disconnection control signal is logic L, the first disconnection circuit 88-1 disconnects the first terminal 34 and the secondary battery element 50 included in the first charge storage circuit 40-1. For example, when the second disconnection control signal output from the second AND circuit 100-2 is logic H, the second disconnection circuit 88-2 shorts the first terminal 34 and the secondary battery element 50 included in the second charge storage circuit 40-2, and when the second disconnection control signal is logic L, the second disconnection circuit 88-2 disconnects the first terminal 34 and the secondary battery element 50 included in the second charge storage circuit 40-2. When the nth disconnection control signal output from the nth AND circuit 100-n is H logic, the nth disconnection circuit 88-n shorts the connection between the first terminal 34 and the secondary battery element 50 included in the nth charge storage circuit 40-n, and when the nth disconnection control signal is L logic, it disconnects the connection between the first terminal 34 and the secondary battery element 50 included in the nth charge storage circuit 40-n.

[0121] The reset potential generating circuit 94 has the same configuration as that in the fourth embodiment.

[0122] The first regulating discharge circuit 96-1 of the N regulating discharge circuits 96-1 to 96-N discharges the charge accumulated in the secondary battery element 50 included in the first charge storage circuit 40-1 in a state other than the first state among the N states. At the same time, the first regulating discharge circuit 96-1 controls the discharge of the charge accumulated in the secondary battery element 50 included in the first charge storage circuit 40-1 based on the membrane potential V mem is the reset potential V r Stop the process when this occurs.

[0123] The second regulating discharge circuit 96-2 of the N regulating discharge circuits 96-1 to 96-N discharges the charge accumulated in the secondary battery element 50 included in the second charge storage circuit 40-2 in a state other than the second state among the N states. At the same time, the second regulating discharge circuit 96-2 controls the discharge of the charge accumulated in the secondary battery element 50 included in the second charge storage circuit 40-2 based on the membrane potential V mem is the reset potential V rStop the process when this occurs.

[0124] The n-th regulating discharge circuit 96-n among the N regulating discharge circuits 96-1 to 96-N discharges the charge accumulated in the secondary battery element 50 included in the n-th charge storage circuit 40-n in a state other than the n-th state among the N states. At the same time, the n-th regulating discharge circuit 96-n controls the discharge of the charge accumulated in the secondary battery element 50 included in the n-th charge storage circuit 40-n based on the membrane potential V mem is the reset potential V r Stop the process when this occurs.

[0125] Furthermore, each of the N regulated discharge circuits 96-1 to 96-N discharges the charge accumulated in the secondary battery element 50 included in the corresponding charge storage circuit 40 during the period when a spike signal is generated from the spike generation circuit 44 and during the refractory period.

[0126] For example, when the first disconnection control signal is at logic L, the first regulating discharge circuit 96-1 connects the terminal of the secondary battery element 50 included in the first charge storage circuit 40-1 that is not connected to the ground terminal to a reset potential V r When the first disconnection control signal is at logic L, the first regulating discharge circuit 96-1 connects the terminal of the secondary battery element 50 included in the first charge storage circuit 40-1 that is not connected to the ground terminal to a reset potential V r Disconnect from.

[0127] For example, when the second disconnection control signal is at logic L, the second regulating discharge circuit 96-2 connects the terminal of the secondary battery element 50 included in the second charge storage circuit 40-2 that is not connected to the ground terminal to a reset potential V r When the second disconnection control signal is at logic L, the second regulating discharge circuit 96-2 connects the terminal of the secondary battery element 50 included in the second charge storage circuit 40-2 that is not connected to the ground terminal to a reset potential V r Disconnect from.

[0128] For example, when the n-th disconnection control signal is at logic L, the n-th regulating discharge circuit 96-n connects the terminal of the secondary battery element 50 included in the n-th charge storage circuit 40-n that is not connected to the ground terminal to a reset potential V r When the n-th disconnection control signal is at logic L, the n-th regulating discharge circuit 96-n connects the terminal of the secondary battery element 50 included in the n-th charge storage circuit 40-n that is not connected to the ground terminal to the reset potential V r Disconnect from.

[0129] In the above configuration, the selection circuit 98 cyclically switches between one of the first state to the Nth state. For example, the selection circuit 98 switches the state to the second state during a refractory period after a spike signal is generated in the first state. The selection circuit 98 also switches the state to the third state during a refractory period after a spike signal is generated in the second state. The selection circuit 98 also switches the state to the (n+1)th state during a refractory period after a spike signal is generated in the nth state, where n+1 is equal to or less than N. The selection circuit 98 then switches the state to the first state during a refractory period after a spike signal is generated in the Nth state.

[0130] The first neuron circuit 30 according to the sixth embodiment configured as above selects the N charge storage circuits 40-1 to 40-N one by one in order, and stores a membrane potential V mem As a result, the first neuron circuit 30 according to the sixth embodiment can discharge each of the unselected (N-1) charge storage circuits 40 among the N charge storage circuits 40-1 to 40-N over a long period of time. Therefore, even if the capacity of the secondary battery element 50 is large, the first neuron circuit 30 can reliably generate the membrane potential V generated from the secondary battery element 50. mem Reset potential V r After the potential is decreased to , accumulation of charges according to the synaptic current can be started. As a result, the neural network device 10 according to the sixth embodiment can perform operations that mimic those of the brain.

[0131] In the sixth embodiment, the n-th regulating discharge circuit 96-n may be operated by a reset signal instead of the n-th disconnection control signal. That is, in the sixth embodiment, the n-th regulating discharge circuit 96-n discharges the charge accumulated in the secondary battery element 50 included in the n-th charge storage circuit 40-n during the refractory period, and controls the discharge of the charge generated from the secondary battery element 50 based on the membrane potential V mem is the reset potential V r It may be stopped at this point.

[0132] Although the embodiments of the present invention have been described above, the above-described embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These novel embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the inventions and their equivalents as defined in the claims.

[0133] (Addendum) The above-described embodiments can be summarized as the following technical proposals.

[0134] [Technical proposal 1] Multiple synaptic circuits, each with its own synaptic weight, Multiple neuron circuits, each generating spike signals, Equipped with each of the plurality of synapse circuits acquires the spike signal from any one of the plurality of neuron circuits, and when acquiring the spike signal, outputs a synapse current according to the set synapse weight; a first neuron circuit among the plurality of neuron circuits has a first terminal to which the synapse current is supplied from one or more first synapse circuits among the plurality of synapse circuits; The first neuron circuit comprises: a secondary battery element that accumulates electric charge according to the synapse current supplied to the first terminal; a spike generating circuit that generates the spike signal when the membrane potential generated by the secondary battery element is greater than a predetermined threshold potential; a reset control circuit that releases the charge stored in the secondary battery element during a refractory period that is a predetermined time after the spike signal is generated; A neural network device having the above.

[0135] [Technical proposal 2] The secondary battery element is a first solid electrolyte layer formed of a solid electrolyte that allows ions to pass through but does not allow electrons to pass through; a first electrode layer and a second electrode layer that are disposed opposite each other with the first solid electrolyte layer interposed therebetween and are made of a solid material that can contain the ions in interstitial spaces or lattice positions; a first current collector layer connected to the first electrode layer and made of metal; a second current collector layer connected to the second electrode layer and made of metal; The neural network device according to Technical Solution 1 includes:

[0136] [Technical proposal 3] the first current collector layer is connected to the first terminal; The second current collecting layer is connected to a ground terminal. A neural network device according to Technical Proposal 2.

[0137] [Technical proposal 4] The ions are lithium ions A neural network device according to Technical Scheme 2 or 3.

[0138] [Technical proposal 5] The secondary battery element further includes a leak circuit for leaking the charge stored in the secondary battery element. A neural network device according to any one of technical proposals 1 to 4.

[0139] [Technical proposal 6] The leakage circuit includes a resistive element connected between the first terminal and a ground terminal. A neural network device according to Technical Proposal 5.

[0140] [Technical proposal 7] the leak circuit includes an electron ion resistance element; The electron ion resistance element is a second solid electrolyte layer formed of a solid electrolyte that allows ions to pass through but does not allow electrons to pass through; a third electrode layer and a fourth electrode layer, which are disposed opposite each other with the second solid electrolyte layer interposed therebetween and are made of a solid material capable of containing the ions in interstitial spaces or lattice positions; a third current collector layer connected to the third electrode layer and made of metal; a fourth current collector layer connected to the fourth electrode layer and made of metal; Including, the third electrode layer and the fourth electrode layer are formed of the same material, the third current collector layer is connected to the first terminal; The fourth current collector layer is connected to a ground terminal. A neural network device according to Technical Solution 5 or 6.

[0141] [Technical proposal 8] The first neuron circuit includes a disconnection control circuit that stops the accumulation of electric charge corresponding to the synaptic current supplied to the first terminal by the secondary battery element during the period when the spike signal is generated and during the refractory period. The neural network device according to any one of technical solutions 1 to 7, further comprising:

[0142] [Technical proposal 9] The first neuron circuit is a regulated discharge circuit that stops the discharge of electric charges generated from the secondary battery element when the membrane potential reaches a predetermined reset potential. The neural network device according to any one of technical solutions 1 to 8, further comprising:

[0143] [Technical proposal 10] Multiple neuron circuits, each generating spike signals, Multiple synaptic circuits, each with its own synaptic weight, Equipped with each of the plurality of synapse circuits acquires the spike signal from any one of the plurality of neuron circuits, and when acquiring the spike signal, outputs a synapse current according to the set synapse weight; a first neuron circuit among the plurality of neuron circuits has a first terminal to which the synapse current is supplied from one or more first synapse circuits among the plurality of synapse circuits; The first neuron circuit comprises: N charge storage circuits (N is an integer of 2 or more) each including a secondary battery element that stores a charge corresponding to the synapse current supplied to the first terminal; a spike generating circuit that generates the spike signal when a membrane potential generated from any of the N charge storage circuits is greater than a predetermined threshold potential; a reset control circuit that releases the charges stored in the N charge storage circuits during a refractory period that is a predetermined time after the spike signal is generated; a selection circuit for selecting one of the N states; and a first state among the N states is a state in which a potential generated from the secondary battery element included in a first charge storage circuit among the N charge storage circuits is output as the membrane potential, the synaptic current supplied to the first terminal is stored in the secondary battery element included in the first charge storage circuit, and charges stored in the secondary battery elements included in charge storage circuits other than the first charge storage circuit among the N charge storage circuits are released; a second state among the N states is a state in which a potential generated from the secondary battery element included in a second charge storage circuit different from the first charge storage circuit among the N charge storage circuits is output as the membrane potential, the synaptic current supplied to the first terminal is stored in the secondary battery element included in the second charge storage circuit, and the charge stored in the secondary battery element included in the charge storage circuit other than the second charge storage circuit among the N charge storage circuits is released; The selection circuit switches to the second state after the spike signal is generated in the first state. Neural network device.

[0144] [Technical proposal 11] The selection circuit switches from the first state to the second state during the refractory period. A neural network device according to Technical Proposal 10.

[0145] [Technical proposal 12] The first neuron circuit includes a regulated discharge circuit that stops the discharge of the electric charge generated from the secondary battery element included in each of the N electric charge storage circuits when the membrane potential reaches a predetermined reset potential. The neural network device according to Technical Solution 11 further comprises:

[0146] [Technical proposal 13] The first neuron circuit includes a disconnection control circuit that disconnects the secondary battery element from the first terminal during the period when the spike signal is generated and during the refractory period. The neural network device according to any one of technical proposals 10 to 12, further comprising:

[0147] [Technical proposal 14] A method for maintaining a membrane potential in a neural network device, comprising: The neural network device comprises: Multiple synaptic circuits, each with its own synaptic weight, Multiple neuron circuits, each generating spike signals, Equipped with each of the plurality of synapse circuits acquires the spike signal from any one of the plurality of neuron circuits, and when acquiring the spike signal, outputs a synapse current according to the set synapse weight; supplying the synapse current from one or each of a plurality of first synapse circuits among the plurality of synapse circuits to a first terminal of a first neuron circuit among the plurality of neuron circuits; causing a secondary battery element to accumulate charge according to the synapse current supplied to the first terminal; generating the spike signal when the membrane potential generated by the secondary battery element is greater than a threshold potential that is a predetermined potential; During a refractory period, which is a predetermined time after the spike signal is generated, the charge stored in the secondary battery element is released. Membrane potential maintenance method. [Explanation of symbols]

[0148] 10 Neural network device 20 Synaptic Circuits 22 Neuron Circuits 30 First neuron circuit 32 First synaptic circuit 40 Charge storage circuit 42 Judgment circuit 44 Spike Generator Circuit 46 Reset control circuit 48 Reset Circuit 50 Secondary battery element 52 Leak Circuit 54 Resistor element 56 Comparator 62 First solid electrolyte layer 64 1st electrode layer 66 Second electrode layer 68 First current collector layer 70 Second current collector layer 72 Electron-ion resistance element 74 Second solid electrolyte layer 76 Third electrode layer 78 4th electrode layer 80 Third current collector layer 82 Fourth current collector layer 86 Cutting control circuit 88 Disconnect circuit 90 Discharge circuit 94 Reset potential generating circuit 96 Regulated discharge circuit

Claims

1. Multiple synaptic circuits, each with its own synaptic weight, Multiple neuron circuits, each generating spike signals, Equipped with each of the plurality of synapse circuits acquires the spike signal from any one of the plurality of neuron circuits, and when acquiring the spike signal, outputs a synapse current according to the set synapse weight; a first neuron circuit among the plurality of neuron circuits has a first terminal to which the synapse current is supplied from one or more first synapse circuits among the plurality of synapse circuits; The first neuron circuit comprises: a secondary battery element that stores electric charge according to the synapse current supplied to the first terminal; a spike generating circuit that generates the spike signal when the membrane potential generated by the secondary battery element is greater than a predetermined threshold potential; a reset control circuit that releases the charge stored in the secondary battery element during a refractory period that is a predetermined time after the spike signal is generated; A neural network device having the above.

2. The secondary battery element is a first solid electrolyte layer formed of a solid electrolyte that allows ions to pass through but does not allow electrons to pass through; a first electrode layer and a second electrode layer that are disposed opposite each other with the first solid electrolyte layer interposed therebetween and are made of a solid material that can contain the ions in interstitial spaces or lattice positions; a first current collector layer connected to the first electrode layer and made of metal; a second current collector layer connected to the second electrode layer and made of metal; 2. The neural network device of claim 1, comprising:

3. the first current collector layer is connected to the first terminal; The second current collecting layer is connected to a ground terminal.

3. The neural network device according to claim 2.

4. The ions are lithium ions 3. The neural network device according to claim 2.

5. The secondary battery element further includes a leak circuit for leaking the charge stored in the secondary battery element.

2. The neural network device according to claim 1.

6. The leakage circuit includes a resistive element connected between the first terminal and a ground terminal.

6. The neural network device according to claim 5.

7. the leak circuit includes an electron ion resistance element; The electron ion resistance element is a second solid electrolyte layer formed of a solid electrolyte that allows ions to pass through but does not allow electrons to pass through; a third electrode layer and a fourth electrode layer, which are disposed opposite each other with the second solid electrolyte layer interposed therebetween and are made of a solid material capable of containing the ions in interstitial spaces or lattice positions; a third current collector layer connected to the third electrode layer and made of metal; a fourth current collector layer connected to the fourth electrode layer and made of metal; Including, the third electrode layer and the fourth electrode layer are formed of the same material, the third current collector layer is connected to the first terminal; The fourth current collector layer is connected to a ground terminal.

6. The neural network device according to claim 5.

8. The first neuron circuit includes a disconnection control circuit that stops the accumulation of electric charge corresponding to the synaptic current supplied to the first terminal by the secondary battery element during the period when the spike signal is generated and during the refractory period.

10. The neural network device of claim 1, further comprising:

9. The first neuron circuit is a regulated discharge circuit that stops the discharge of electric charges generated from the secondary battery element when the membrane potential reaches a predetermined reset potential.

10. The neural network device of claim 1, further comprising:

10. Multiple neuron circuits, each generating spike signals, Multiple synaptic circuits, each with its own synaptic weight, Equipped with each of the plurality of synapse circuits acquires the spike signal from any one of the plurality of neuron circuits, and when acquiring the spike signal, outputs a synapse current according to the set synapse weight; a first neuron circuit among the plurality of neuron circuits has a first terminal to which the synapse current is supplied from one or more first synapse circuits among the plurality of synapse circuits; The first neuron circuit comprises: N charge storage circuits (N is an integer of 2 or more) each including a secondary battery element that stores a charge corresponding to the synapse current supplied to the first terminal; a spike generating circuit that generates the spike signal when a membrane potential generated from any of the N charge storage circuits is greater than a predetermined threshold potential; a reset control circuit that releases the charges stored in the N charge storage circuits during a refractory period that is a predetermined time after the spike signal is generated; a selection circuit for selecting one of the N states; and a first state among the N states is a state in which a potential generated from the secondary battery element included in a first charge storage circuit among the N charge storage circuits is output as the membrane potential, the synaptic current supplied to the first terminal is stored in the secondary battery element included in the first charge storage circuit, and charges stored in the secondary battery elements included in charge storage circuits other than the first charge storage circuit among the N charge storage circuits are released; a second state among the N states is a state in which a potential generated from the secondary battery element included in a second charge storage circuit different from the first charge storage circuit among the N charge storage circuits is output as the membrane potential, the synaptic current supplied to the first terminal is stored in the secondary battery element included in the second charge storage circuit, and the charge stored in the secondary battery element included in the charge storage circuit other than the second charge storage circuit among the N charge storage circuits is released; The selection circuit switches to the second state after the spike signal is generated in the first state. Neural network device.

11. The selection circuit switches from the first state to the second state during the refractory period.

11. The neural network device according to claim 10.

12. The first neuron circuit includes a regulated discharge circuit that stops the discharge of electric charges generated from the secondary battery element included in each of the N charge storage circuits when the membrane potential reaches a predetermined reset potential.

12. The neural network device of claim 11, further comprising:

13. The first neuron circuit includes a disconnection control circuit that disconnects the secondary battery element from the first terminal during the period when the spike signal is generated and during the refractory period.

11. The neural network device of claim 10, further comprising:

14. A method for maintaining a membrane potential in a neural network device, comprising: The neural network device comprises: Multiple synaptic circuits, each with its own synaptic weight, Multiple neuron circuits, each generating spike signals, Equipped with each of the plurality of synapse circuits acquires the spike signal from any one of the plurality of neuron circuits, and when acquiring the spike signal, outputs a synapse current according to the set synapse weight; supplying the synapse current from one or each of a plurality of first synapse circuits among the plurality of synapse circuits to a first terminal of a first neuron circuit among the plurality of neuron circuits; storing electric charges in the secondary battery element according to the synapse current supplied to the first terminal; generating the spike signal when the membrane potential generated by the secondary battery element is greater than a threshold potential that is a predetermined potential; During a refractory period, which is a predetermined time after the spike signal is generated, the charge stored in the secondary battery element is released. Membrane potential maintenance method.

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