Phase estimator, power controller, power conversion device and phase estimation method

Abstract

To estimate a voltage phase of AC from voltage information of a limited phase of multi-phase AC.SOLUTION: A phase estimator includes a pair signal generation unit, a reference phase angle generation unit, a coordinate conversion unit, a speed estimation calculation unit and an integrator. The pair signal generation unit generates a second signal based on an instantaneous value of a first signal based on a detection value of voltage or current of one phase of a multi-phase motor and an estimation value of a phase θ related to control of the multi-phase motor. The reference phase angle generation unit generates a reference phase θ0 based on the estimation value of the phase θ and a phase change amount Δθ generated from the estimation value of the phase θ. The coordinate conversion unit generates a signal of a rotor coordinate system from a pair signal of the first signal and the second signal of a stator coordinate system by coordinate conversion using the reference phase θ0. The speed estimation calculation unit generates a speed estimation value so as to follow a change in output of the coordinate conversion unit. The unit integrates the speed estimation value and generates the estimation value of the phase θ.SELECTED DRAWING: Figure 2A

Description

[Technical Field]

[0001] FIELD Embodiments of the present invention relate to a phase estimator, a power control device, a power conversion device, and a phase estimation method. [Background technology]

[0002] In power conversion devices that convert power and supply AC power, such as static power converters and variable speed drives, it is sometimes difficult to accurately estimate the phase (voltage phase) of the AC voltage from voltage information based on the detected value of the output AC voltage. In such cases, PLL (Phase Lock Loop) technology is used for the detected value of the AC voltage of the multiphase AC, and the phase (voltage phase) of the AC voltage can be estimated from the voltage information based on the detected value. However, when applying PLL technology to the detection value of a multi-phase AC voltage, if only voltage information for a specific phase of the multi-phase AC is available, it can be difficult to estimate the phase of that AC voltage. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2001-145398 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a phase estimator, a power control device, a power conversion device, and a phase estimation method that can estimate the voltage phase of an AC signal from voltage information of only a limited number of phases of the AC signal. [Means for solving the problem]

[0005] A phase estimator according to an embodiment includes a paired signal generator, a reference phase angle generator, a coordinate converter, a speed estimation calculator, and an integrator. The paired signal generator generates a second signal based on an instantaneous value of a first signal based on a detected voltage or current value of one phase of a multi-phase motor and an estimated value of a phase θ related to control of the multi-phase motor. The reference phase angle generator generates a reference phase θ based on the estimated value of the phase θ and a phase change amount Δθ generated from the estimated value of the phase θ. The coordinate converter generates a signal in a rotor coordinate system from a paired signal of the first signal and the second signal in a stator coordinate system by coordinate transformation using the reference phase θ. The speed estimation calculator generates a speed estimate to follow changes in the output of the coordinate converter. The integrator generates an estimated value of the phase θ by integrating the speed estimate. [Brief explanation of the drawings]

[0006] [Figure 1] 1 is a schematic configuration diagram of a power conversion device according to an embodiment; [Figure 2A] FIG. 2 is a schematic configuration diagram of a phase estimator according to an embodiment. [Figure 2B] FIG. 4 is a characteristic diagram of a filter in a phase estimator according to the embodiment. [Figure 3A] FIG. 2 is a schematic configuration diagram of a speed estimation calculation unit according to the embodiment. [Figure 3B] FIG. 2 is a schematic configuration diagram of a speed estimation calculation unit according to the embodiment. [Figure 4A] FIG. 10 is a diagram for explaining an example of a verification result according to the embodiment. [Figure 4B] FIG. 10 is a diagram for explaining an example of a verification result according to the embodiment. [Figure 4C] FIG. 10 is a diagram for explaining an example of a verification result according to the embodiment. [Figure 4D] FIG. 10 is a diagram for explaining an example of a verification result according to the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] A phase estimator, a power control device, a power conversion device, and a phase estimation method according to embodiments will be described below with reference to the drawings. In the following description, components having the same or similar functions are denoted by the same reference numerals. Duplicate descriptions of those components may be omitted. Electrical connection may simply be referred to as "connected."

[0008] (First embodiment) A power conversion device 1 including a phase estimator according to an embodiment will be described with reference to FIG. FIG. 1 is a schematic configuration diagram of a power conversion device 1 including a phase estimator according to an embodiment.

[0009] The power conversion device 1 includes, for example, an electric motor 2, an inverter 3, a power control device 4, and an instrument transformer 7.

[0010] The electric motor 2 is an example of an AC motor that is driven by a supply of polyphase AC power. More specifically, the electric motor 2 is driven by a supply of polyphase AC power having three or more phases. In the following description, a three-phase motor including the UV phases will be used as an example. However, a polyphase AC motor (electric motor) of another configuration may be used instead.

[0011] The inverter 3 converts DC power into AC power under power running control from the power control device 4. If regenerative control is possible, the inverter 3 converts AC power into DC power under regenerative control from the power control device 4.

[0012] The power control device 4 detects the state of the inverter 3 and controls the power conversion of the inverter 3 based on commands from a higher-level control device or the like.

[0013] The power control device 4 includes, for example, a power control unit 5 and a phase estimator 6 . The power control unit 5 controls the power control device 4, thereby controlling the power conversion of the inverter 3.

[0014] The phase estimator 6 performs a process of estimating the phase of the AC voltage of the inverter 3 .

[0015] Fig. 2A is a schematic diagram of a phase estimator according to an embodiment, Fig. 2B is a characteristic diagram of a filter in the phase estimator according to an embodiment, Fig. 3A and Fig. 3B are schematic diagrams of a speed estimation calculation unit according to an embodiment.

[0016] The phase estimator 6 includes, for example, a pair signal generator 61 , a reference phase angle generator 62 , a holder 63 , a coordinate converter 64 , a speed estimation calculator 65 , and an integrator 66 .

[0017] The pair signal generating unit 61 includes filter units 611 and 613 , a gain adjusting unit 612 , a phase wrapping correcting unit 614 , limiters 615 and 617 , and a divider 616 .

[0018] The filter unit 611 is configured as a first FIR filter that smoothes a signal based on the detection result (first signal, for example, the α-axis component of the αβ axis). The FIR filter in the filter unit 611 can be replaced with a differential operation by defining it using an arithmetic expression that determines the central difference value Ac of the α axis. For example, it is advisable to configure the characteristics of this FIR filter as a comb filter type (comb filter).

[0019] The filter unit 613 is configured as a second FIR filter that smoothes the estimated value of the phase θ. The FIR filter in the filter unit 613 can be replaced with a differential operation by defining it by an arithmetic expression for obtaining the central difference approximation value θc of the phase θ. For example, it is preferable to configure the characteristics of this FIR filter as a comb filter type with the same characteristics as the filter unit 611.

[0020] In the configuration of this embodiment, it is preferable that the orders of the filter unit 611 (first FIR filter) and the filter unit 613 (second FIR filter) are both second order. Specific formulas will be described later.

[0021] The gain adjustment unit 612 is connected to the output of the filter unit 611 and amplifies the output of the filter unit 611 with a predetermined gain.

[0022] The phase wrap correction unit 614 corrects the phase indicated by the output of the second FIR filter.

[0023] The limiter 615 limits the output value of the phase wrap correction unit 614 to within a predetermined range. If the output value of the phase wrap correction unit 614 exceeds the upper limit of the range, the limiter 615 outputs the upper limit. If the output value of the phase wrap correction unit 614 falls below the lower limit of the range, the limiter 615 outputs the lower limit. If the output value of the phase wrap correction unit 614 is within this range, the limiter 615 outputs the output value of the phase wrap correction unit 614. The following explanation will focus on the conditions during small amplitude operation when no restrictions are imposed by the limiter 615.

[0024] Divider 616 divides the output value of gain adjustment unit 612 by the output value of limiter 615 and outputs the quotient. In other words, assuming that the gain of gain adjustment unit 612 is 1, divider 616 can be considered to divide the output value of filter unit 611 by the output value of phase wrap correction unit 614 and output the quotient.

[0025] The limiter 617 limits the output value of the divider 616 to within a predetermined range. If the output value of divider 616 exceeds the upper limit of the range, limiter 617 outputs the upper limit. If the output value of divider 616 is below the lower limit of the range, limiter 617 outputs the lower limit. If the output value of divider 616 is within the range, limiter 617 outputs the output value of divider 616. The following explanation focuses on the conditions during small amplitude operation when no limitation by limiter 617 occurs.

[0026] In this way, the paired signal generation unit 61 converts a value based on the output of the filter unit 611 (first FIR filter) using the phase change amount Δθ due to the output of the phase wrap correction unit 614 (correction calculation unit), and outputs the result. For example, the divider 616 (conversion processing unit) of the paired signal generation unit 61 divides the value (ωβ) based on the output of the filter unit 611 (first FIR filter) by the phase change amount Δθ due to the output of the phase wrap correction unit 614 (correction calculation unit) to obtain a paired signal (second signal, for example, the β-axis component of the αβ-axis). The change amount Δθ corresponds to the velocity ω.

[0027] The above-mentioned signal pair generating unit 61 is identified as a discrete-time system. In this case, the paired signal generator 61, the reference phase angle generator 62, the coordinate converter 64, and the speed estimation calculator 65 included in the paired signal generator 61 are configured in a discrete time system. This allows the time history of the input to the coordinate converter 64 to be matched.

[0028] For example, the reference phase angle generating unit 62 generates a reference phase θ0 based on an estimated value (θest) of the phase θ and a phase change amount Δθ generated from the estimated value (θest) of the phase θ. In this case, the reference phase angle generating unit 62 may include a subtractor 621 and a phase correcting unit 622.

[0029] The subtractor 621 calculates the difference between the phase θ[n], which is the estimated value of the phase θ, and the phase change Δθ generated from the phase θ[n] by the paired signal generator 61, and defines the result as the phase θ[n-1]. The phase corrector 622 calculates a reference phase θ0 based on the phase θ[n-1] so that the difference between the phase θ[n], which is the estimated value of the phase θ, and the phase change Δθ generated from the phase θ[n] by the paired signal generator 61 becomes zero.

[0030] The holding unit 63 holds and delays the input α[n], and outputs α[n-1]. The holding unit 63 delays the instantaneous value of the first signal by one reference period. In other words, the holding unit 63 delays the instantaneous value of the first signal by one reference period, enabling it to correspond to the time history data of the input of the coordinate transformation unit 64. This allows the time history of the input of the coordinate transformation unit 64 to be matched.

[0031] The coordinate transformation unit 64 generates a signal (dq-axis component) in the rotor coordinate system from a pair of signals (αβ-axis) of the first and second signals in the stator coordinate system by coordinate transformation (conversion to dq-axis, DC value) using the reference phase θ0. The first and second signals in the stator coordinate system may be, for example, a pair of signals (αβ-axis) of α[n-1] output from the holding unit 63 and β[n-1] output from the divider 616 of the pair of signal generation unit 61. The coordinate transformation unit 64 generates voltage references Vdest and Vqest by calculation using this Park transformation.

[0032] The speed estimation calculation unit 65 calculates the speed estimation value ω so as to follow the change in the output of the coordinate conversion unit 64. * Generate. For example, the speed estimation calculation unit 65 may be configured as shown in FIG. 3A. The speed estimation calculation unit 65 includes a subtractor 621, a loop filter 652, a compensation calculation unit 653, and an oscillator 654. The subtractor 621 corrects an offset included in the output of the coordinate conversion unit 64 as necessary. The amount of correction may be zero. The loop filter 652 forms a loop filter that determines the response characteristics of the PLL, etc. The compensation calculation unit 653 performs a PI-type compensation calculation. This compensation calculation includes calculations to further optimize the characteristics of the loop filter. The application of the compensation calculation unit 653 is optional. The oscillator 654 outputs a signal of a desired frequency and calculates a phase Δω according to a control input. * For example, the oscillator 654 is an example of a digitally controlled oscillator (DCO). The speed estimation calculation unit 65 configured in this manner generates a speed estimation value ω * to follow.

[0033] The integrator 66 receives the speed estimate ω generated by the speed estimation calculation unit 65.* is integrated (numerical integration) to calculate the phase θ. The phase estimator 6 configured in this way can generate a phase θ based on a signal based on the detection result (first signal, for example, the α-axis component of the αβ axes).

[0034] The various processes performed by the phase estimator 6 will now be described in more detail.

[0035] (1) Phase estimation based on mutually orthogonal voltage waveforms derived from single-phase voltage waveforms Phase estimation using mutually orthogonal voltage waveforms (sine wave and cosine wave) derived from a single-phase voltage waveform will be explained.

[0036] When performing αβ / dq transformation (so-called Park transformation) on a single-phase voltage waveform, either a sine wave or a cosine wave, it is necessary to prepare a voltage waveform wave that is paired with this single-phase voltage waveform. For example, in the following description, the single-phase voltage waveform (input voltage waveform) is defined as a cosine wave. An example of the single-phase voltage waveform α(t) is shown in equation (1).

[0037]

number

[0038] Transforming equation (1) by analytical differentiation yields the following equation (2): Waveform β(t) is an example of a voltage waveform that pairs with the single-phase voltage waveform α(t).

[0039]

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[0040] As shown in the above equation (2), by differentiating both sides of equation (1), which shows the relationship of the single-phase voltage waveform α(t), with respect to time t, and then dividing the result of the differentiation by the angular velocity ω, the counterpart waveform (single-phase voltage waveform β(t)) can be derived. The same applies when the input waveform is changed from a cosine wave to a sine wave.

[0041] Instead of the analytical differentiation, numerical differentiation may be performed using a processing device such as a microprocessor or a DSP (Digital Signal Processor). Backward difference approximation, central difference approximation, etc. are known as numerical differentiation methods. Due to the conditions of numerical differentiation, applying the backward difference approximation may not provide the desired accuracy.

[0042] Therefore, it is advisable to reduce the error O due to numerical differentiation by applying the relatively stable central difference approximation to the numerical differentiation calculation method. The error O(h) indicates the magnitude of the error when the backward difference approximation is applied, and the error O(h 2 ) indicates the magnitude of the error when applying the central difference approximation. As shown in the following equation (3), the magnitude of the error O(h) is 2 ) is greater than

[0043]

number

[0044] In addition to the above, a high-pass filter (HPF) can be used as an analytical calculation method equivalent to a differential calculation. This HPF can be realized with an IIR (Infinite Impulse Response) filter, but it is known that the phase characteristics of an IIR filter do not become linear. To avoid this, an example will be described in which an FIR (Finite Impulse Response) filter is applied so that the phase delay characteristics after the differentiation operation become linear phase characteristics.

[0045] The following equation (4) shows an example of a central difference calculation: This equation (4) is also the equation for an FIR type HPF.

[0046]

number

[0047] In the above formula (4), the infinitesimal quantity h defined for the differential operation with respect to the time variable t may be a time corresponding to the interrupt operation period Ts of the microprocessor. Also, by defining the variable t as the current time in the above formula (4), the variable (th) becomes a past time, and the variable (t+h) becomes a future time.

[0048] Of these, the value of a future time (t+h) cannot be obtained at the current time t, and therefore cannot be used in calculations using the current time t as the reference time. Therefore, it is advisable to use a time shifted along the time axis by a predetermined amount as the reference time and approximate the current event. For example, the time obtained by adding the time (h) of one calculation cycle (one control interrupt cycle) to the reference time t of the calculation in equation (4) above is used as the reference time. The relationship of this reference time delayed by one calculation cycle is converted using the time history variable n to obtain the differential calculation result β[n], which is shown in equation (5A) below. The result of Z-transforming the relationship in equation (5A) is shown in equation (5B).

[0049]

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[0050]

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[0051] A and B in this equation (5B) are the Z-transformed versions of α[n] and β[n], respectively. As shown in this equation (5B), the result of the differential operation on the right side is also delayed by one calculation cycle. When the αβ / dq transformation is expressed as a function in the discrete time domain, it is called an AB / DQ transformation. The input signal of the coordinate transformation unit 64 that performs the AB / DQ transformation is adjusted to a value delayed by one calculation cycle. This allows the αβ / dq transformation to be converted into an arithmetic expression in the discrete time domain composed of variables that can be used for calculation processing at the current time. By performing calculations under conditions shifted in the time axis direction in this way, it becomes possible to perform calculations without using future information, and the time axis can be balanced.

[0052] Note that when performing fixed-point calculations using this arithmetic expression, there is a possibility that subtraction of the numerator will result in cancellation of significant digits, or that division by the infinitesimal sampling period Ts will result in overflow in the integer part of the quotient. In particular, the shorter the sampling period Ts, the more likely such phenomena will occur, since division will be performed by an infinitesimal value. Furthermore, if the sampling interval is not constant, it will be necessary to calculate the reciprocal of the sampling interval time each time, which will increase the calculation load. Therefore, by replacing it with the processing described below, it is possible to eliminate division using the sampling period Ts. A more specific explanation will be given below.

[0053] (2) Central difference approximation The angular velocity ω is equivalent to the derivative of the angle θ. The relationship is shown in equation (6). As mentioned above, central difference approximation is used for the arithmetic differentiation of equation (6) (equation (7A)), and equation (7A) is then Z-transformed to obtain equation (7B). The angular velocity can be derived using equation (7B).

[0054]

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[0055]

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[0056]

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[0057] Θ and Ω in this equation (7B) are the Z-transforms of θ[n] and ω[n], respectively. Dividing both sides of the above equation (5B) by both sides of equation (7B), respectively, results in the left-hand side being (B / Ω). In the division on the right-hand side, the division by the sampling period Ts in each denominator can be canceled out. This eliminates the "division by the sampling period Ts" in the calculation on the right-hand side corresponding to the calculation of (B / Ω) on the left-hand side, thereby reducing the calculation load. Furthermore, the "sampling period Ts" is no longer involved in the calculation of the right-hand side of the above formula. This means that even if the sampling period Ts changes, it is no longer necessary to recalculate the sampling period Ts each time. This also reduces the calculation load.

[0058] (3) Time alignment of variables used in AB / DQ conversion It is advisable to match the time history of the phase angle Θ used in the AB / DQ conversion with the time history of B (a time relatively delayed by one sampling period from the reference time). The relationship between the phase error Δθ and angular velocity ω is shown in the continuous time domain. The phase error Δθ at a specific time can be considered to be equal to the product of the angular velocity ω and the sampling period Ts. As mentioned above, if the differential calculation is configured using an FIR filter type arithmetic expression, the linearity of the delay tendency in the phase characteristics is guaranteed.

[0059] Here, the phase characteristic (phase delay error) can be calculated by multiplying both sides of the above equation (7B) by the sampling period Ts. The phase delay error ΔΘ due to the filter is ΩTs.

[0060]

number

[0061] In this case, Δθ is equal to the input θ passed through the following FIR filter: FIG. 2B shows an example of the frequency characteristics of the FIR filter according to the embodiment. An example of the frequency characteristic of the FIR filter of equation (9) when the sampling frequency is set to 10000 (rad / s) is shown below.

[0062]

number

[0063] FIG. 2(a) shows the gain characteristic of the FIR filter of equation (9), and FIG. 2(b) shows its phase characteristic. As shown in Figure 2(a), the gain characteristic at the center of the passband is generally flat, but the gain tends to decrease as the frequency moves away from the center frequency of the passband. The effect of this tendency for gain to decrease is minor. The gain characteristic at the stopband shows sufficient attenuation characteristics to attenuate the signal of that frequency component.

[0064] As shown in FIG. 2(b), the phase characteristic changes monotonically within the range of the passband, ensuring linearity.

[0065] Fig. 2(c) shows an example of the result of performing phase reversal correction on the phase characteristic shown in Fig. 2(b) by the phase reversal correction unit 614. By using the phase characteristic after the phase reversal correction, it is possible to prevent a sudden change in phase at the end of the passband range.

[0066] 4A to 4D show an example of the verification results of the configuration of the embodiment. 4A to 4D are diagrams for explaining an example of a verification result according to the embodiment. For example, the relationship between the input signal and the output signal of the coordinate transformation unit 64 when an FIR filter having the frequency characteristics shown in FIG. 2B is applied to the filter unit 611 will be described. The horizontal axis of Fig. 4A to Fig. 4D is assigned to the time of a common index. The vertical axis of Fig. 4A to Fig. 4D is assigned to the input signal and output signal of the coordinate conversion unit 64. More specifically, the d-axis voltage is assigned to Fig. 4A, the q-axis voltage to Fig. 4C, the α-axis voltage to Fig. 4B, and the β-axis voltage to Fig. 4D. The time axes of each diagram are aligned. This verification was carried out under the following conditions:

[0067] AC voltage sampling frequency: 10kHz Voltage amplitude peak level: 10000.0 AC output frequency: 50Hz

[0068] 4A to 4D show that the error in the estimated value (VdEst) of the d-axis component, where the expected value (VdReal) based on the actual detected value is 10,000, is approximately 8.0, and the amplitude of the ripple in this estimated value is approximately ±8.0. The vertical axis in Fig. 4A is enlarged near the expected value to make the error of this component more noticeable.

[0069] In the waveform diagram above, the superimposed ripples are emphasized due to the setting of the vertical axis display range, but as shown in Figure 4B, the difference between the actual AC waveform (cosReal) and the estimated AC waveform (cosT) is slight.

[0070] Similarly, the error in the estimated value (VqEst) of the q-axis component, whose expected value (VqReal) based on the actual detected value is 0, is nearly 0, and the amplitude of the ripple in the estimated value is approximately 0.8. The vertical axis in Figure 4C is expanded near the expected value to highlight the error in that component. Similarly, although the superimposed ripple is emphasized, the apparent difference between the actual AC waveform (sinReal) and the estimated AC waveform (sinT) is minor, as shown in FIG. 4D.

[0071] Consider the above ripple. With filter unit 611 and filter unit 613 configured as described above, ripples at twice the fundamental frequency of the AC may occur in the components on the DQ axes due to signal attenuation caused by the cutoff characteristics of the FIR filters. As described above, if the sampling frequency of the AC voltage is set sufficiently higher than the frequency of the update cycle of the signal input to the FIR filter, the influence of the ripple components can be reduced. In applications where the fundamental frequency of the AC can be fixed, the detection frequency range for the generated ripple can be specified in advance. In such cases, the ripple can be further reduced by removing the frequency (2f component) that is twice the fundamental frequency (f) of the AC using a notch filter or the like.

[0072] According to the above embodiment, the phase estimator includes a paired signal generator, a reference phase angle generator, a coordinate converter, a speed estimation calculator, and an integrator. The paired signal generator generates a second signal (e.g., a sine component of the αβ axis) based on an instantaneous value of a first signal (e.g., a cosine component of the αβ axis) based on a detected value of the voltage or current of one phase of a multi-phase motor and an estimated value of a phase θ related to control of the multi-phase motor. The reference phase angle generator generates a reference phase θ based on the estimated value of the phase θ and a phase change amount Δθ generated from the estimated value of the phase θ. The coordinate converter generates a signal (a dq-axis component) in the rotor coordinate system from the paired signal (αβ axis) of the first signal and the second signal in the stator coordinate system by coordinate transformation (transformation to dq axes, DC values) using the reference phase θ. The speed estimation calculator generates a speed estimation value that follows changes in the output of the coordinate converter. The speed estimation calculator integrates the speed estimation value to generate an estimated value of the phase θ. This makes it possible to estimate the voltage phase of the AC from voltage information of limited phases of the multi-phase AC.

[0073] (Second embodiment) 1 and other figures, the power control device 4 may include a phase estimator 6 and a power control unit 5 that controls the inverter 3 (power converter) using phase information estimated by the phase estimator 6. Such a power control device 4 can estimate phase information using the phase estimator 6 and control the inverter 3 (power converter) using the estimated phase information.

[0074] (Third embodiment) 1 and other figures, the power conversion device 1 may include an inverter 3 (power converter), a phase estimator 6, and a power control unit 5 that controls the inverter 3 (power converter) using phase information estimated by the phase estimator 6. Such a power conversion device 1 can estimate phase information using the phase estimator 6 and control the inverter 3 (power converter) using the estimated phase information.

[0075] According to at least one of the above-described embodiments, the phase estimator includes a paired signal generator, a reference phase angle generator, a coordinate converter, a speed estimation calculator, and an integrator. The paired signal generator generates a second signal (e.g., a sine component of the αβ axis) based on an instantaneous value of a first signal (e.g., a cosine component of the αβ axis) based on a detected value of the voltage or current of one phase of a multi-phase motor and an estimated value of a phase θ related to control of the multi-phase motor. The reference phase angle generator generates a reference phase θ based on the estimated value of the phase θ and a phase change amount Δθ generated from the estimated value of the phase θ. The coordinate converter generates a signal (a dq-axis component) in the rotor coordinate system from the paired signal (αβ axis) of the first signal and the second signal in the stator coordinate system by coordinate transformation (transformation to dq axes, DC values) using the reference phase θ. The speed estimation calculator generates a speed estimate to track changes in the output of the coordinate converter. The speed estimation calculator integrates the speed estimate to generate an estimated value of the phase θ. This makes it possible to estimate the voltage phase of the AC from voltage information of limited phases of the multi-phase AC.

[0076] Although several embodiments of the present invention have been described above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention and its equivalents as set forth in the claims. Furthermore, the above-described embodiments can be implemented in combination with each other. [Explanation of symbols]

[0077] 1 Power conversion device 2 electric motor 3 inverters 4 Power control device 5 Power control section 6 Phase estimator 61 Pair signal generator 62 Reference phase angle generator 63 Holding part 64 Coordinate conversion section 65 Speed ​​estimation calculation section 66 Integrator 611, 613 Filter section 614 Phase wrap correction unit 616 Divider

Claims

1. a paired signal generator that generates a second signal based on an instantaneous value of a first signal based on a detected value of a voltage or current of one phase of a polyphase motor and an estimated value of a phase θ related to control of the polyphase motor; a reference phase angle generation unit that generates a reference phase θ based on the estimated value of the phase θ and a phase change amount Δθ generated from the estimated value of the phase θ; a coordinate transformation unit that generates a signal in a rotor coordinate system from a pair of the first signal and the second signal in a stator coordinate system by coordinate transformation using the reference phase θ0; a speed estimation calculation unit that generates a speed estimation value so as to follow a change in the output of the coordinate transformation unit; an integrator that integrates the velocity estimate to generate an estimate of phase θ; A phase estimator comprising:

2. The pair signal generation unit a first FIR filter that smooths an instantaneous value of the first signal; a second FIR filter that smooths the estimate of the phase θ; a correction calculation unit that corrects the phase indicated by the output of the second FIR filter; a conversion processing unit that converts a value based on the output of the first FIR filter using a phase change amount Δθ due to the output of the correction calculation unit; The phase estimator of claim 1 , comprising:

3. The conversion processing unit Dividing a value based on the output of the first FIR filter by the phase change amount Δθ 3. The phase estimator of claim 2.

4. the first FIR filter and the second FIR filter each include central difference approximation calculation processing; 3. The phase estimator of claim 2.

5. the pair signal generating unit, the reference phase angle generating unit, the coordinate transforming unit, and the speed estimation calculating unit are configured in a discrete time system, a holding unit that delays the instantaneous value of the first signal by one reference period and associates the instantaneous value with time history data input to the coordinate transformation unit; The phase estimator of claim 1 , comprising:

6. A phase estimator according to any one of claims 1 to 5; a power control unit that controls a power converter using the phase information estimated by the phase estimator; A power control device comprising:

7. a power converter; A phase estimator according to any one of claims 1 to 5; a power control unit that controls the power converter using the phase information estimated by the phase estimator; A power conversion device comprising:

8. generating a second signal based on an instantaneous value of a first signal based on a detected value of a voltage or a current of one phase of a polyphase motor and an estimated value of a phase θ related to control of the polyphase motor; generating a reference phase θ based on the estimated value of the phase θ and a phase change amount Δθ generated from the estimated value of the phase θ; generating a signal in a rotor coordinate system from a pair of the first signal and the second signal in a stator coordinate system by coordinate transformation using the reference phase θ0; generating a speed estimate to track changes in the rotor coordinate system signal; integrating the velocity estimates to generate an estimate of phase θ; A phase estimation method comprising:

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