Display device and electronic apparatus

Abstract

To provide a display device including a driving circuit with redundancy.SOLUTION: The display device has a first layer, and a second layer positioned above the first layer. The first layer has a first driving circuit and a second driving circuit while the second layer has a first pixel region and a second pixel region. The first pixel region has a first pixel circuit while the second pixel region has a second pixel circuit. The first pixel region has a region overlapping the first circuit while the second pixel region has a region overlapping the second circuit. The first pixel circuit is electrically connected to the first driving circuit through first wiring. The second pixel circuit is electrically connected to the second driving circuit through second wiring. The first wiring is electrically connected to the second wiring through a switch.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a method for manufacturing a display device, an electronic device, and a semiconductor device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification relates to an object, a driving method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, manufacture, or a composition of matter. Therefore, more specifically, examples of the technical field of one embodiment of the present invention disclosed in this specification include semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, power storage devices, imaging devices, memory devices, signal processing devices, processors, electronic devices, systems, driving methods thereof, manufacturing methods thereof, and inspection methods thereof. [Background technology]

[0003] There is a demand for display devices that can be applied to XR (Cross Reality or Extended Reality) such as VR (Virtual Reality) and AR (Augmented Reality). Specifically, for example, in order to enhance the sense of reality and immersion, the display devices are desired to have high definition and excellent color reproducibility.

[0004] Examples of display devices that can be applied to the display include liquid crystal display devices, and light-emitting devices equipped with light-emitting devices such as organic electroluminescence (EL) devices and light-emitting diodes (LEDs: Light Emitting Diodes). Patent Document 1 discloses a high-pixel, high-definition display device equipped with a light-emitting device that includes an organic EL device. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] International Publication No. 2019 / 220278 Summary of the Invention [Problem to be solved by the invention]

[0006] As described above, devices for XR require display devices with high display quality. Furthermore, since display devices for XR need to be provided in, for example, eyeglass-type or goggle-type housings, it is preferable to reduce the size of the display device. Specifically, for example, in the case of devices for VR, the size (diagonal length) of the display device is preferably 1 inch or more and 2 inches or less. Furthermore, for example, in devices for AR, the size of the display device is preferably 3 inches or less, more preferably 2 inches or less, and even more preferably 1.5 inches or less.

[0007] On the other hand, display devices for XR devices require higher resolution to enhance the sense of realism and immersion. In this case, for example, the number of pixels within a given size can be increased by designing the display device to have a smaller pitch between pixels or between wires, or by reducing the pixel size. However, as the number of pixels in a display device increases, the amount of data per frame increases, and therefore there is a demand for faster driver circuits (such as source driver circuits and gate driver circuits) that drive the display device.

[0008] Furthermore, when the resolution of a display device is increased, the number of pixels included in the display device increases, which in turn increases the size of the drive circuit that drives the display device. Therefore, it is preferable to reduce the circuit area of ​​the drive circuit in a display device for XR devices. One way to reduce the circuit area of ​​the drive circuit is to reduce the size of circuit elements such as transistors. However, when the size of circuit elements is reduced, variations in the characteristics of the circuit elements may occur, which may cause the drive circuit to not operate properly (operational malfunctions in the drive circuit).

[0009] An object of one embodiment of the present invention is to provide a display device having a redundant driver circuit. Another object of one embodiment of the present invention is to provide a display device with a high yield. Another object of one embodiment of the present invention is to provide a display device with high display quality. Another object of one embodiment of the present invention is to provide a novel display device. Another object of one embodiment of the present invention is to provide an electronic device including any of the above-described display devices. Another object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device in which a driver circuit has redundancy. Another object of one embodiment of the present invention is to provide a method for manufacturing a novel semiconductor device.

[0010] Note that the problems of one embodiment of the present invention are not limited to the problems listed above. The problems listed above do not preclude the existence of other problems. Note that the other problems are problems not mentioned in this section, which will be described below. Problems not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be appropriately extracted from these descriptions. Note that one embodiment of the present invention solves at least one of the problems listed above and other problems. Note that one embodiment of the present invention does not necessarily solve all of the problems listed above and other problems. [Means for solving the problem]

[0011] (1) One aspect of the present invention is a display device having a first layer and a second layer located above the first layer. The first layer has a first driving circuit and a second driving circuit, and the second layer has a first pixel region and a second pixel region. The first pixel region has a first pixel circuit, and the second pixel region has a second pixel circuit. The first pixel region has an area overlapping the first circuit, and the second pixel region has an area overlapping the second circuit. The first pixel circuit is electrically connected to the first driving circuit via a first wiring, and the second pixel circuit is electrically connected to the second driving circuit via a second wiring, and the first wiring is electrically connected to the second wiring via a switch. The first driving circuit has a function of transmitting image data to the first pixel circuit when the switch is in an off state and a function of transmitting image data to the second pixel circuit when the switch is in an on state. The second driving circuit has a function of transmitting image data to the second pixel circuit when the switch is in the off state, and a function of transmitting image data to the first pixel circuit when the switch is in the on state.

[0012] (2) Alternatively, in one aspect of the present invention, in the above-mentioned (1), the switch may be included in the first layer or the second layer.

[0013] (3) Alternatively, in one embodiment of the present invention, in the above (1) or (2), the first layer may have a first substrate, and the second layer may have a second substrate. Preferably, each of the first substrate and the second substrate is a semiconductor substrate made of silicon. Preferably, channel formation regions of transistors included in the first driver circuit and the second driver circuit each contain silicon contained in the first substrate, and preferably, channel formation regions of transistors included in the first pixel region and the second pixel region each contain silicon contained in the second substrate.

[0014] (4) Alternatively, in one embodiment of the present invention, in the above (1) or (2), the first layer may have a first substrate. The first substrate is preferably a semiconductor substrate made of silicon. The transistors included in the first driver circuit and the second driver circuit are preferably transistors formed on the first substrate, and the transistors included in the first pixel region and the second pixel region are preferably transistors whose channel formation regions contain metal oxide.

[0015] (5) Another embodiment of the present invention is an electronic device including the display device described in any one of (1) to (4) above and a housing.

[0016] (6) Another embodiment of the present invention is a method for manufacturing a semiconductor device including a second substrate. In the semiconductor device, the second substrate is a semiconductor substrate made of silicon. The method for manufacturing the semiconductor device includes first to seventh steps. The first step includes forming an isolation layer in the second substrate. The second step includes forming a well in a region of the second substrate other than the region where the isolation layer is formed. The third step includes forming a first insulator in a part of the region of the second substrate above the region where the well is formed. The fourth step includes forming a first low-resistance region and a second low-resistance region in a region of the second substrate other than the region where the isolation layer and the first insulator are formed. The fifth step includes a step of transitioning to a sixth step if one of the first driver circuit and the second driver circuit included in the first substrate is malfunctioning, and a step of transitioning to a seventh step if both the first driver circuit and the second driver circuit included in the first substrate are malfunctioning. The sixth step includes removing the first insulator and forming a third low-resistance region in the region of the second substrate where the first insulator was formed. The seventh step includes forming a second insulator on the second substrate and providing openings in the second insulator in regions overlapping the separation layer, the first low-resistance region, and the second low-resistance region, and forming conductors in the openings.

[0017] In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. It also refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component that houses a chip in a package are each an example of a semiconductor device. Furthermore, a memory device, a display device, a light-emitting device, a lighting device, an electronic device, etc. may themselves be a semiconductor device or may include a semiconductor device.

[0018] Furthermore, when it is stated in this specification that X and Y are connected, it is understood that the following cases are disclosed in this specification: when X and Y are electrically connected, when X and Y are functionally connected, and when X and Y are directly connected. Therefore, it is not limited to a predetermined connection relationship, for example, a connection relationship shown in a figure or text, and it is understood that connections other than those shown in a figure or text are also disclosed in a figure or text. X and Y are understood to be objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0019] As an example of a case where X and Y are electrically connected, one or more elements (for example, a switch, a transistor, a capacitance element, an inductor, a resistance element, a diode, a display device, a light-emitting device, a load, etc.) that enable the electrical connection between X and Y can be connected between X and Y. The switch has a function of controlling on / off. In other words, the switch has a function of being in a conductive state (on state) or a non-conductive state (off state), and controls whether or not a current flows.

[0020] As an example of a case where X and Y are functionally connected, one or more circuits that enable the functional connection between X and Y (for example, logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion circuits (digital-analog conversion circuits, analog-digital conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (power supply circuits (boosting circuits, step-down circuits, etc.), level shifter circuits that change the potential level of signals, etc.), voltage sources, current sources, switching circuits, amplifier circuits (circuits that can increase signal amplitude or current, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation circuits, memory circuits, control circuits, etc.) can be connected between X and Y. As an example, even if another circuit is sandwiched between X and Y, if a signal output from X is transmitted to Y, X and Y are considered to be functionally connected.

[0021] When it is explicitly stated that X and Y are electrically connected, this includes the case where X and Y are electrically connected (i.e., when X and Y are connected with another element or circuit between them) and the case where X and Y are directly connected (i.e., when X and Y are connected without another element or circuit between them).

[0022] This specification also deals with a circuit configuration in which multiple elements are electrically connected to wiring (a wiring that supplies a constant potential or a wiring that transmits a signal). For example, if X and a wiring are directly and electrically connected, and Y and the wiring are also directly and electrically connected, this specification may state that X and Y are directly and electrically connected.

[0023] Furthermore, for example, it can be expressed as follows: "X, Y, and the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor are electrically connected to each other, and are electrically connected in the order of X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y." Or, it can be expressed as follows: "The source (or first terminal, etc.) of the transistor is electrically connected to X, and the drain (or second terminal, etc.) of the transistor is electrically connected to Y, and X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y are electrically connected in this order." Or, it can be expressed as follows: "X is electrically connected to Y via the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor, and X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y are provided in this connection order." By using expressions similar to these examples to define the order of connections in a circuit configuration, the source (or first terminal, etc.) and drain (or second terminal, etc.) of a transistor can be distinguished and the technical scope can be determined. Note that these expressions are merely examples and are not limiting. Here, X and Y are assumed to be objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0024] Note that even when independent components are shown electrically connected in a circuit diagram, one component may have the functions of multiple components. For example, if part of a wiring also functions as an electrode, one conductive film has the functions of both wiring and an electrode. Therefore, the term "electrically connected" in this specification also includes such cases where one conductive film has the functions of multiple components.

[0025] Furthermore, in this specification and the like, a "resistance element" can be, for example, a circuit element having a resistance value higher than 0Ω, or a wiring having a resistance value higher than 0Ω. Therefore, in this specification and the like, a "resistance element" is intended to include a wiring having a resistance value, a transistor in which a current flows between the source and drain, a diode, a coil, and the like. Therefore, the term "resistance element" can sometimes be replaced with terms such as "resistance," "load," or "region having a resistance value." Conversely, the terms "resistance," "load," and "region having a resistance value" can sometimes be replaced with terms such as "resistance element." The resistance value can be, for example, preferably 1 mΩ or more and 10 Ω or less, more preferably 5 mΩ or more and 5 Ω or less, and even more preferably 10 mΩ or more and 1 Ω or less. Furthermore, for example, a resistance value can be replaced with a resistance value of 1 Ω or more and 1×10 9 It may be set to Ω or less.

[0026] Furthermore, in this specification, a "capacitive element" can refer to, for example, a circuit element having a capacitance value higher than 0 F, a wiring region having a capacitance value higher than 0 F, a parasitic capacitance, a gate capacitance of a transistor, etc. Furthermore, terms such as "capacitive element," "parasitic capacitance," and "gate capacitance" can sometimes be replaced with terms such as "capacitance." Conversely, the term "capacitance" can sometimes be replaced with terms such as "capacitive element," "parasitic capacitance," and "gate capacitance." Furthermore, the term "pair of electrodes" in "capacitance" can be replaced with "pair of conductors," "pair of conductive regions," "pair of regions," etc. The value of the capacitance can be, for example, 0.05 fF or more and 10 pF or less. It can also be, for example, 1 pF or more and 10 μF or less.

[0027] In this specification, a transistor has three terminals called a gate, a source, and a drain. The gate is a control terminal that controls the conduction state of the transistor. The two terminals that function as a source or a drain are input / output terminals of the transistor. One of the two input / output terminals serves as a source and the other as a drain depending on the conductivity type (n-channel or p-channel) of the transistor and the level of the potential applied to the three terminals of the transistor. Therefore, in this specification, the terms "source" and "drain" may be interchangeable. In addition, in this specification, when describing the connection relationship of a transistor, the terms "one of the source or drain" (or first electrode or first terminal) and "the other of the source or drain" (or second electrode or second terminal) are used. Note that, depending on the structure of a transistor, a backgate may be included in addition to the three terminals described above. In this case, in this specification, one of the gate or backgate of the transistor may be referred to as a first gate, and the other of the gate or backgate of the transistor may be referred to as a second gate. Furthermore, for the same transistor, the terms "gate" and "backgate" may be interchangeable. Furthermore, when a transistor has three or more gates, the gates may be referred to as a first gate, a second gate, a third gate, and so on in this specification and the like.

[0028] For example, in this specification, a transistor having a multi-gate structure with two or more gate electrodes can be used as an example of a transistor. In a multi-gate structure, the channel formation regions are connected in series, resulting in a structure in which multiple transistors are connected in series. Therefore, the multi-gate structure can reduce the off-state current and improve the breakdown voltage (reliability) of the transistor. Furthermore, when operating in the saturation region, the multi-gate structure can provide a voltage-current characteristic with a flat slope, whereby the current between the drain and source does not change significantly even when the voltage between the drain and source changes. By utilizing a voltage-current characteristic with a flat slope, an ideal current source circuit or an active load with a very high resistance value can be realized. As a result, a differential circuit or a current mirror circuit with excellent characteristics can be realized.

[0029] Furthermore, even when a single circuit element is shown on a circuit diagram, the circuit element may include multiple circuit elements. For example, when a circuit diagram shows one resistor, this includes two or more resistors electrically connected in series. For example, when a circuit diagram shows one capacitor, this includes two or more capacitors electrically connected in parallel. For example, when a circuit diagram shows one transistor, this includes two or more transistors electrically connected in series, with the gates of the transistors electrically connected to each other. Similarly, when a circuit diagram shows one switch, this includes two or more transistors electrically connected in series or parallel, with the gates of the transistors electrically connected to each other.

[0030] Furthermore, in this specification and the like, a node can be referred to as a terminal, a wiring, an electrode, a conductive layer, a conductor, an impurity region, etc. depending on the circuit configuration, device structure, etc. Furthermore, a terminal, a wiring, etc. can be referred to as a node.

[0031] Furthermore, in this specification and the like, the terms "voltage" and "potential" can be interchanged as appropriate. "Voltage" refers to the potential difference from a reference potential. For example, if the reference potential is the ground potential (earth potential), then "voltage" can be interchanged with "potential." Note that ground potential does not necessarily mean 0 V. Furthermore, potential is relative, and as the reference potential changes, the potential applied to wiring, the potential applied to a circuit, etc., the potential output from a circuit, etc. also changes.

[0032] Furthermore, in this specification, the terms "high-level potential" and "low-level potential" do not refer to specific potentials. For example, when two wirings are both described as "functioning as wirings that supply a high-level potential," the high-level potentials provided by both wirings do not have to be equal to each other. Similarly, when two wirings are both described as "functioning as wirings that supply a low-level potential," the low-level potentials provided by both wirings do not have to be equal to each other.

[0033] Furthermore, "electric current" refers to the phenomenon of charge transfer (electrical conduction). For example, the statement "electrical conduction of positively charged bodies is occurring" can be rephrased as "electrical conduction of negatively charged bodies is occurring in the opposite direction." Therefore, in this specification, unless otherwise specified, "electric current" refers to the phenomenon of charge transfer (electrical conduction) accompanying the movement of carriers. The carriers referred to here include electrons, holes, anions, cations, complex ions, etc., and the carriers differ depending on the system through which the current flows (e.g., semiconductor, metal, electrolyte, vacuum, etc.). Furthermore, the "direction of current" in wiring, etc., refers to the direction in which positively charged carriers move and is expressed as a positive current amount. In other words, the direction in which negatively charged carriers move is opposite to the direction of current flow and is expressed as a negative current amount. Therefore, in this specification, etc., unless otherwise specified regarding the positive / negative sign of the current (or the direction of current), a statement such as "current flows from element A to element B" can be rephrased as "current flows from element B to element A," etc. Furthermore, statements such as "current is input to element A" can be rephrased as "current is output from element A" or the like.

[0034] Furthermore, in this specification, the ordinal numbers "first," "second," and "third" are used to avoid confusion between components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of the components. For example, a component referred to as "first" in one embodiment of this specification may be a component referred to as "second" in another embodiment or in the claims. Furthermore, for example, a component referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims.

[0035] Furthermore, in this specification, terms indicating position, such as "above" and "below," may be used for convenience in describing the positional relationship between components with reference to the drawings. Furthermore, the positional relationship between components changes as appropriate depending on the direction in which each component is depicted. Therefore, the terms are not limited to those used in the specification, and can be rephrased appropriately depending on the situation. For example, the expression "an insulator located on the upper surface of a conductor" can be rephrased as "an insulator located on the lower surface of a conductor" by rotating the orientation of the drawing by 180 degrees.

[0036] Furthermore, the terms "above" and "below" do not limit the positional relationship of components to being directly above or below, and being in direct contact with each other. For example, the expression "electrode B on insulating layer A" does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0037] Furthermore, in this specification, terms such as "row" and "column" may be used to describe components arranged in a matrix and their positional relationships. Furthermore, the positional relationships between components change as appropriate depending on the direction in which each component is depicted. Therefore, the terms are not limited to those used in the specification, and may be rephrased appropriately depending on the situation. For example, the expression "row direction" may be rephrased as "column direction" by rotating the orientation of the drawing by 90 degrees.

[0038] Furthermore, in this specification and the like, terms such as "film" and "layer" can be interchanged depending on the situation. For example, the term "conductive layer" may be interchanged with the term "conductive film." Or, for example, the term "insulating film" may be interchanged with the term "insulating layer." Or, in some cases or depending on the situation, terms such as "film" and "layer" may not be used and may be interchanged with other terms. For example, the terms "conductive layer" or "conductive film" may be interchanged with the term "conductor." Or, for example, the terms "insulating layer" and "insulating film" may be interchanged with the term "insulator."

[0039] Furthermore, in this specification and the like, terms such as "electrode," "wiring," and "terminal" do not functionally limit these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, the terms "electrode" and "wiring" include cases where at least one of a plurality of "electrodes" and "wiring" is integrally formed. Furthermore, for example, a "terminal" may be used as part of a "wiring" or "electrode," and vice versa. Furthermore, the term "terminal" includes cases where a plurality of "electrodes," "wiring," "terminals," and the like are integrally formed. Therefore, for example, an "electrode" can be part of a "wiring" or "terminal," and a "terminal" can be part of a "wiring" or "electrode." Furthermore, terms such as "electrode," "wiring," and "terminal" may be replaced with terms such as "region" in some cases.

[0040] Furthermore, in this specification and the like, terms such as "wiring," "signal line," and "power line" may be interchangeable depending on the circumstances. For example, the term "wiring" may be changed to the term "signal line." For example, the term "wiring" may be changed to the term "power line." Vice versa, terms such as "signal line" and "power line" may be changed to the term "wiring." A term such as "power line" may be changed to the term "signal line." Vice versa, terms such as "signal line" may be changed to the term "power line." Furthermore, the term "potential" applied to a wiring may be changed to the term "signal" depending on the circumstances. Vice versa, terms such as "signal" may be changed to the term "potential."

[0041] In this specification and the like, the term "impurities" in semiconductors refers to, for example, elements other than the main components constituting the semiconductor layer. For example, an element with a concentration of less than 0.1 atomic % is an impurity. The presence of impurities can cause, for example, an increase in the defect level density of the semiconductor, a decrease in carrier mobility, and a decrease in crystallinity. When the semiconductor is an oxide semiconductor, impurities that change the semiconductor characteristics include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components, particularly, for example, hydrogen (also contained in water), lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Specifically, when the semiconductor is a silicon layer, impurities that change the semiconductor characteristics include, for example, Group 1 elements, Group 2 elements, Group 13 elements, and Group 15 elements (excluding oxygen and hydrogen).

[0042] In this specification, a switch refers to a device that can be in a conductive state (on state) or a non-conductive state (off state) and has the function of controlling whether or not a current flows. Alternatively, a switch refers to a device that has the function of selecting and switching a path through which a current flows. Therefore, a switch may have two or more terminals for passing a current in addition to a control terminal. As an example, an electrical switch, a mechanical switch, or the like can be used. In other words, the switch is not limited to a specific type as long as it can control a current.

[0043] Examples of electrical switches include transistors (e.g., bipolar transistors, MOS transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes, diode-connected transistors, etc.), and logic circuits combining these. When a transistor is used as a switch, the "conductive state" of the transistor refers to, for example, a state in which the source electrode and drain electrode of the transistor can be considered to be electrically short-circuited, or a state in which current can flow between the source electrode and drain electrode. The "non-conductive state" of the transistor refers to a state in which the source electrode and drain electrode of the transistor can be considered to be electrically disconnected. When a transistor is operated simply as a switch, the polarity (conductivity type) of the transistor is not particularly limited.

[0044] An example of a mechanical switch is a switch that uses MEMS (microelectromechanical systems) technology. This switch has a mechanically movable electrode, and the movement of the electrode controls whether the switch is conductive or non-conductive.

[0045] In this specification, etc., a device fabricated using a metal mask or FMM (fine metal mask, high-resolution metal mask) may be referred to as a device with an MM (metal mask) structure. In this specification, etc., a device fabricated without using a metal mask or FMM may be referred to as a device with an MML (metal maskless) structure.

[0046] In this specification, a structure in which different light-emitting layers are formed or different light-emitting layers are painted for each color light-emitting device (here, blue (B), green (G), and red (R)) may be referred to as an SBS (Side By Side) structure. In this specification, a light-emitting device that can emit white light may be referred to as a white light-emitting device. In addition, a white light-emitting device can be combined with a colored layer (e.g., a color filter) to form a full-color display device.

[0047] Light-emitting devices can be broadly divided into single-structure and tandem-structure devices. A single-structure device has one light-emitting unit between a pair of electrodes, and the light-emitting unit preferably includes one or more light-emitting layers. When two light-emitting layers are used to obtain white light emission, the light-emitting layers can be selected so that the emission colors of the two light-emitting layers are complementary to each other. For example, by making the emission color of the first light-emitting layer and the emission color of the second light-emitting layer complementary to each other, a configuration in which the entire light-emitting device emits white light can be obtained. When three or more light-emitting layers are used to obtain white light emission, the emission colors of the three or more light-emitting layers can be combined to produce a configuration in which the entire light-emitting device emits white light.

[0048] A tandem-structure device preferably has two or more light-emitting units between a pair of electrodes, and each light-emitting unit preferably includes one or more light-emitting layers. To obtain white light, light from the light-emitting layers of the light-emitting units may be combined to obtain white light. The configuration for obtaining white light is the same as that of the single-structure device. In a tandem-structure device, it is preferable to provide an intermediate layer such as a charge-generating layer between the light-emitting units.

[0049] Furthermore, when comparing the above-mentioned white light-emitting device (single structure or tandem structure) with a light-emitting device having an SBS structure, the light-emitting device having an SBS structure can reduce power consumption compared to the white light-emitting device. If you want to keep power consumption low, it is preferable to use a light-emitting device having an SBS structure. On the other hand, the manufacturing process of a white light-emitting device is simpler than that of a light-emitting device having an SBS structure, so it is preferable because it can reduce manufacturing costs or increase manufacturing yields.

[0050] In this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it also includes cases where the angle is -5° or more and 5° or less. Furthermore, "substantially parallel" or "roughly parallel" refers to a state in which two straight lines are arranged at an angle of -30° or more and 30° or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes cases where the angle is 85° or more and 95° or less. Furthermore, "substantially perpendicular" or "approximately perpendicular" refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less. [Effects of the Invention]

[0051] According to one embodiment of the present invention, a display device having a redundant driver circuit can be provided. According to another embodiment of the present invention, a display device with a high yield can be provided. According to another embodiment of the present invention, a display device with high display quality can be provided. According to another embodiment of the present invention, a novel display device can be provided. According to another embodiment of the present invention, an electronic device including any of the display devices described above can be provided. According to another embodiment of the present invention, a method for manufacturing a semiconductor device having a redundant driver circuit can be provided. According to another embodiment of the present invention, a method for manufacturing a novel semiconductor device can be provided.

[0052] The effects of one embodiment of the present invention are not limited to the effects listed above. The effects listed above do not preclude the existence of other effects. The other effects are described below and are not mentioned in this section. Effects not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be extracted as appropriate from these descriptions. One embodiment of the present invention has at least one of the effects listed above and other effects. Therefore, one embodiment of the present invention may not have the effects listed above in some cases. [Brief explanation of the drawings]

[0053] [Figure 1] 1A and 1B are schematic perspective views showing a configuration example of a display device. [Figure 2] 2A and 2B are cross-sectional views showing examples of the configuration of a display device. [Figure 3] 3A and 3B are schematic plan views showing configuration examples of a display device. [Figure 4] 4A and 4B are schematic plan views showing configuration examples of a display device. [Figure 5] 5A and 5B are schematic perspective views showing configuration examples of a display device. [Figure 6] FIG. 6 is a block diagram showing an example of the configuration of a display device. [Figure 7] FIG. 7 is a timing chart showing an example of the operation of the display device. [Figure 8] FIG. 8 is a timing chart showing an example of the operation of the display device. [Figure 9] FIG. 9 is a block diagram showing an example of the configuration of a display device. [Figure 10] FIG. 10 is a timing chart showing an example of the operation of the display device. [Figure 11] FIG. 11A is a schematic plan view showing an example of the configuration of a display device, and FIG. 11B is a schematic cross-sectional view showing an example of the configuration of a display device. [Figure 12] FIG. 12A is a schematic plan view showing a configuration example of a display device, and FIG. 12B is a schematic cross-sectional view showing the configuration example of a display device. [Figure 13] FIG. 13 is a flowchart showing an example of a method for manufacturing a display device. [Figure 14] FIG. 14 is a flowchart showing an example of a method for manufacturing a display device. [Figure 15] FIG. 15A is a schematic plan view showing a configuration example of a display device, and FIG. 15B is a schematic cross-sectional view showing the configuration example of a display device. [Figure 16] FIG. 16A is a schematic plan view showing an example of the configuration of a display device, and FIG. 16B is a schematic cross-sectional view showing an example of the configuration of a display device. [Figure 17] FIG. 17 is a cross-sectional view showing a configuration example of a display device. [Figure 18] 18A to 18D are schematic diagrams showing configuration examples of light-emitting devices. [Figure 19] FIG. 19 is a cross-sectional view showing a configuration example of a display device. [Figure 20] 20A and 20B are cross-sectional views showing examples of the structure of a transistor. [Figure 21] 21A and 21B are cross-sectional schematic views showing examples of the configuration of a transistor. [Figure 22] 22A and 22B are cross-sectional schematic views showing configuration examples of a display device. [Figure 23]23A to 23D are cross-sectional views showing examples of the configuration of a display device. [Figure 24] 24A and 24B are cross-sectional schematic views showing configuration examples of a display device. [Figure 25] 25A and 25B are cross-sectional schematic views showing configuration examples of a display device. [Figure 26] FIG. 26A is a circuit diagram showing an example of the configuration of a pixel circuit included in the display device, and FIG. 26B is a schematic perspective view showing an example of the configuration of a pixel circuit included in the display device. [Figure 27] 27A to 27D are circuit diagrams showing configuration examples of pixel circuits included in a display device. [Figure 28] 28A to 28D are circuit diagrams showing configuration examples of pixel circuits included in a display device. [Figure 29] 29A and 29B are top views showing configuration examples of a light-emitting device and a light-receiving device included in a display device. [Figure 30] 30A to 30D are cross-sectional views showing examples of the configuration of a light-emitting device, a light-receiving device, and connection electrodes included in a display device. [Figure 31] 31A and 31B are diagrams showing configuration examples of a display module. [Figure 32] 32A to 32F are diagrams showing configuration examples of electronic devices. [Figure 33] 33A and 33B are diagrams showing configuration examples of a display module. [Figure 34] 34A and 34B are diagrams showing configuration examples of electronic devices. [Figure 35] 35A to 35C are diagrams showing configuration examples of electronic devices. [Figure 36] 36A to 36D are diagrams showing configuration examples of electronic devices. DETAILED DESCRIPTION OF THE INVENTION

[0054] In this specification and the like, a metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply as OSs), and the like. For example, when a metal oxide is contained in a channel formation region of a transistor, the metal oxide may be referred to as an oxide semiconductor. In other words, when a metal oxide can form a channel formation region of a transistor having at least one of an amplifying function, a rectifying function, and a switching function, the metal oxide can be referred to as a metal oxide semiconductor. Furthermore, an OS transistor can be rephrased as a transistor including a metal oxide or an oxide semiconductor.

[0055] In this specification and the like, nitrogen-containing metal oxides may also be collectively referred to as metal oxides. Nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0056] In this specification and the like, the configurations shown in each embodiment can be combined as appropriate with the configurations shown in other embodiments to form one aspect of the present invention. In addition, when multiple configuration examples are shown in one embodiment, the configuration examples can be combined as appropriate with each other.

[0057] In addition, the content (or even part of the content) described in one embodiment can be applied, combined, or replaced with at least one of another content (or even part of the content) described in that embodiment and another content (or even part of the content) described in one or more other embodiments.

[0058] The contents described in the embodiments refer to the contents described in each embodiment using various figures or the contents described using text in the specification.

[0059] Furthermore, a figure (or even a part thereof) described in one embodiment can be combined with another part of that figure, another figure (or even a part thereof) described in that embodiment, and at least one figure (or even a part thereof) described in one or more other embodiments to form even more figures.

[0060] The embodiments described in this specification are described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways, and that various changes in form and details can be made without departing from the spirit and scope of the invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments. Note that in the configuration of the invention of the embodiments, the same reference numerals are used in different drawings for the same parts or parts having similar functions, and repeated description thereof may be omitted. Also, in perspective views and the like, the description of some components may be omitted to ensure clarity of the drawings.

[0061] In addition, in the drawings of this specification, plan views may be used to explain the configuration of each embodiment. A plan view, for example, is a diagram showing the appearance of a surface (cut surface) obtained by cutting a configuration horizontally. Also, hidden lines (e.g., dashed lines) may be included in the plan view to show the positional relationship of multiple elements included in the configuration or the overlapping relationship of the multiple elements. Note that in this specification, the term "plan view" may be replaced with the terms "projection view," "top view," or "bottom view." Depending on the situation, a plan view may refer to a surface (cut surface) obtained by cutting a configuration in a direction other than the horizontal direction, rather than a surface (cut surface) obtained by cutting the configuration horizontally.

[0062] In addition, in the drawings of this specification, cross-sectional views may be used to explain the configuration of each embodiment. A cross-sectional view is, for example, a view showing the appearance of a surface (cut surface) of a configuration cut in a vertical direction. In this specification, the term "cross-sectional view" may be replaced with the terms "front view" or "side view." Depending on the situation, a cross-sectional view may refer to a surface (cut surface) of a configuration cut in a direction other than the vertical direction, rather than a surface (cut surface) cut in a vertical direction.

[0063] In this specification, when the same reference numeral is used for multiple elements, and particularly when it is necessary to distinguish between them, an identification symbol such as "_1", "[n]", "[m,n]" may be added to the reference numeral. Also, when an identification symbol such as "_1", "[n]", "[m,n]" is added to the reference numeral in the drawings, etc., the identification symbol may not be added if it is not necessary to distinguish between them in this specification.

[0064] In addition, in the drawings of this specification, the size, layer thickness, or region may be exaggerated for clarity. Therefore, the drawings are not necessarily limited to the scale. Note that the drawings are schematic illustrations of ideal examples, and are not limited to the shapes or values ​​shown in the drawings. For example, variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing differences may be included.

[0065] (Embodiment 1) In this embodiment, a display device according to one embodiment of the present invention will be described.

[0066] <Configuration example> 2A is a cross-sectional view of a display device according to one embodiment of the present invention. The display device 10 includes a pixel layer PXAL, a wiring layer LINL, and a circuit layer SICL.

[0067] The wiring layer LINL is provided on the circuit layer SICL, and the pixel layer PXAL is provided on the wiring layer LINL. The pixel layer PXAL overlaps a region including a drive circuit region DRV (described later) and a region LIA (described later).

[0068] The circuit layer SICL includes, for example, a substrate BS1, a drive circuit region DRV, and a region LIA.

[0069] The substrate BS1 can be, for example, a single-crystal substrate (e.g., a semiconductor substrate made of silicon or germanium). In addition to single-crystal substrates, the substrate BS1 can also be, for example, an SOI (Silicon-On-Insulator) substrate, a glass substrate, a quartz substrate, a plastic substrate, a sapphire glass substrate, a metal substrate, a stainless steel substrate, a substrate with stainless steel foil, a tungsten substrate, a substrate with tungsten foil, a flexible substrate, a laminated film, paper containing a fibrous material, or a base film. Examples of glass substrates include barium borosilicate glass, aluminoborosilicate glass, and soda-lime glass. Examples of flexible substrates, laminated films, and base films include the following: Plastics such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), and polytetrafluoroethylene (PTFE) are examples. Alternatively, synthetic resins such as acrylic resins are examples. Other examples include polypropylene, polyester, polyvinyl fluoride, and polyvinyl chloride. Other examples include polyamide, polyimide, aramid, epoxy resin, inorganic vapor deposition film, and paper. If the manufacturing process of the display device 10 includes a heat treatment, it is preferable to select a material with high heat resistance for the substrate BS1.

[0070] In this embodiment, the substrate BS1 is described as a semiconductor substrate made of silicon, and therefore, the transistors included in the driver circuit region DRV can be transistors having silicon in their channel formation regions (hereinafter referred to as Si transistors).

[0071] The drive circuit region DRV and the region LIA are provided on a substrate BS1.

[0072] The drive circuit region DRV has, as an example, a drive circuit for driving pixels included in a pixel layer PXAL, which will be described later. Note that a specific configuration example of the drive circuit region DRV will be described later.

[0073] As an example, wiring is provided in the region LIA. The wiring included in the region LIA may be electrically connected to wiring included in the wiring layer LINL. In this case, the display device 10 may be configured such that the circuit included in the drive circuit region DRV and the circuit included in the pixel layer PXAL are electrically connected by the wiring included in the region LIA and the wiring included in the wiring layer LINL. The display device 10 may be configured such that the circuit included in the drive circuit region DRV and the wiring or circuit included in the region LIA are electrically connected via the wiring included in the wiring layer LINL.

[0074] Furthermore, the region LIA may include, for example, a graphics processing unit (GPU). Furthermore, if the display device 10 includes a touch panel, the region LIA may include a sensor controller that controls a touch sensor included in the touch panel. Furthermore, if a light-emitting device using an EL material is used as a display element of the display device 10, the region LIA may include an EL correction circuit. The EL correction circuit has, for example, a function of appropriately adjusting the amount of current input to the light-emitting device containing the EL material. Since the luminance of the light-emitting device containing the EL material when emitting light is proportional to the current, if the characteristics of the drive transistor electrically connected to the light-emitting device are poor, the luminance of the light emitted by the light-emitting device may be lower than the desired luminance. For example, the EL correction circuit monitors the amount of current flowing through the light-emitting device, and if the amount of current is smaller than the desired amount, it increases the amount of current flowing through the light-emitting device to increase the luminance of light emitted by the light-emitting device. Conversely, if the amount of current is larger than the desired amount, it may decrease the amount of current flowing through the light-emitting device. Furthermore, when a liquid crystal element is used as the display element of the display device 10, the area LIA may include a gamma correction circuit.

[0075] As an example, wiring is provided in the wiring layer LINL. The wiring included in the wiring layer LINL functions as wiring that electrically connects, for example, a drive circuit included in the drive circuit region DRV provided below and a circuit included in the pixel layer PXAL provided above.

[0076] The pixel layer PXAL includes, for example, a substrate BS2 and a pixel array ALP. The pixel array ALP includes a plurality of pixels, and the plurality of pixels are provided on the substrate BS2. The plurality of pixels may be arranged in a matrix in the pixel array ALP.

[0077] For example, the substrate BS2 may be a substrate that can be used for the substrate BS1. In this embodiment, the substrate BS2 will be described as a semiconductor substrate made of silicon or the like. Therefore, the transistors included in the multiple pixels of the pixel array ALP may be Si transistors.

[0078] In addition, since the pixel layer PXAL is provided above the wiring layer LINL, the substrate BS2 is provided so as to be located above the wiring layer LINL. Note that the substrate BS2 and the wiring layer LINL can be joined together, for example, by a bonding process described later.

[0079] Each of the pixels included in the pixel array ALP can express one or more colors. In particular, the multiple colors can be, for example, three colors: red (R), green (G), and blue (B). Alternatively, the multiple colors can be, for example, red (R), green (G), and blue (B) plus at least one color selected from cyan, magenta, yellow, and white. Each pixel expressing a different color is called a sub-pixel, and when white is expressed by multiple sub-pixels of different colors, the multiple sub-pixels are sometimes collectively referred to as a pixel. For convenience, in this specification and other descriptions, a sub-pixel will be referred to as a pixel.

[0080] Note that the display device of one embodiment of the present invention is not limited to the configuration example illustrated in FIG. 2A . The display device of one embodiment of the present invention may be modified as appropriate within the scope of solving the problem. For example, the configuration of the display device 10 illustrated in FIG. 2A does not necessarily include the substrate BS2. FIG. 2B illustrates a configuration of the display device 10 of FIG. 2A without the substrate BS2. In the display device 10 illustrated in FIG. 2B , for example, an OS transistor can be used as the transistor included in the pixel layer PXAL. A metal oxide included in the channel formation region of the OS transistor can be formed by, for example, a sputtering method. Therefore, in the manufacturing method of the display device 10 of FIG. 2B , a step of attaching the substrate BS2 on which the transistor is formed to the wiring layer LINL of the substrate BS1, as in the display device 10 of FIG. 2A, can be omitted.

[0081] 3A is an example of a plan view of the display device 10, showing only the circuit layer SICL. The display device 10 shown in FIG. 3A has, as an example, a configuration in which a drive circuit region DRV is surrounded by a region LIA.

[0082] In FIG. 3A, the drive circuit region DRV includes, for example, a plurality of local driver circuits LD, a controller CON, and a voltage generating circuit PG.

[0083] The controller CON has, for example, a function of processing an input signal from outside the display device 10. The input signal may be, for example, an image signal, an address signal including a destination of the image signal, etc. The controller CON selects a local driver circuit LD included in the drive circuit region DRV in response to the address signal, and transmits the image signal to the selected local driver circuit LD.

[0084] Furthermore, since a plurality of local driver circuits LD are provided in the drive circuit region DRV, the controller CON may be configured to transmit image signals to the plurality of local driver circuits LD in parallel at the same time.

[0085] For example, the voltage generation circuit PG functions as a circuit that generates a power supply voltage for driving circuits included in the drive circuit region DRV (for example, a source driver circuit and a gate driver circuit, which will be described later). The voltage generation circuit PG may also have a function of generating a voltage to be supplied to pixels included in the pixel layer PXAL, which will be described later.

[0086] Each of the local driver circuits LD has a function of driving a pixel included in the pixel layer PXAL, for example. That is, for example, each of the local driver circuits LD can be configured to have a source driver circuit and a gate driver circuit. Furthermore, since there are multiple local driver circuits LD in the drive circuit region DRV, it is possible to determine the region of pixels included in the pixel layer PXAL to be driven by each local driver circuit.

[0087] For example, consider a case where the pixel array ALP included in the pixel layer PXAL in the display device 10 is divided into regions with m rows and n columns (m is an integer greater than or equal to 1, and n is an integer greater than or equal to 1). In this case, the number of local driver circuits included in the drive circuit region DRV is m×n. 3A shows, as an example, the local driver circuit LD[1,1], the local driver circuit LD[1,2], the local driver circuit LD[2,1], the local driver circuit LD[2,2], the local driver circuit LD[m-1,1], the local driver circuit LD[m-1,2], the local driver circuit LD[m,1], the local driver circuit LD[m,2], the local driver circuit LD[1,n-1], the local driver circuit LD[1,n], the local driver circuit LD[2,n-1], the local driver circuit LD[2,n], the local driver circuit LD[m-1,n-1], the local driver circuit LD[m-1,n], the local driver circuit LD[m,n-1], and the local driver circuit LD[m,n].

[0088] FIG. 3B shows pixel regions when the pixel array ALP included in the pixel layer PXAL is divided into regions of m rows and n columns. FIG. 3B is a plan view of the display device 10, and shows only the drive circuit region DRV and the pixel array ALP. In particular, in FIG. 3B, the drive circuit region DRV is indicated by a solid line, and the pixel array ALP is indicated by a dashed line. As shown in FIG. 3B, the drive circuit region DRV overlaps the pixel array ALP. In particular, in FIG. 3B, the edge of the drive circuit region DRV overlaps more inward than the edge of the pixel array ALP in a plan view. In addition, in FIG. 3B, the pixel array ALP is divided into pixel regions ARA[1,1] to ARA[m,n], as an example. In addition, in Figure 3B, as an example, the symbols for pixel area ARA[1,1], pixel area ARA[2,1], pixel area ARA[m-1,1], pixel area ARA[m,1], pixel area ARA[1,n], pixel area ARA[2,n], pixel area ARA[m-1,n], and pixel area ARA[m,n] are excerpted and shown.

[0089] As an example, if it is desired to divide the pixel array ALP into 32 regions, m = 4 and n = 8 can be applied to Figures 3A and 3B. When the resolution of the display device 10 is 8K4K, the number of pixels is 7680 x 4320 pixels. Furthermore, when the sub-pixels of the display device 10 are of three colors, red (R), green (G), and blue (B), the total number of sub-pixels is 7680 x 4320 x 3. Here, when the pixel array of the display device 10 with an 8K4K resolution is divided into 32 regions, the number of pixels per region is 960 x 1080 pixels. Furthermore, when the sub-pixels of the display device 10 are of three colors, red (R), green (G), and blue (B), the number of sub-pixels per region is 960 x 1080 x 3.

[0090] 3B, as an example, the local driver circuit LD[1,1] drives the pixels included in the pixel region ARA[1,1], and the local driver circuit LD[2,1] drives the pixels included in the pixel region ARA[2,1]. The local driver circuit LD[m-1,1] drives the pixels included in the pixel region ARA[m-1,1], and the local driver circuit LD[m,1] drives the pixels included in the pixel region ARA[m,1]. The local driver circuit LD[1,n] drives the pixels included in the pixel region ARA[1,n], and the local driver circuit LD[2,n] drives the pixels included in the pixel region ARA[2,n]. The local driver circuit LD[m-1,n] drives the pixels included in the pixel region ARA[m-1,n], and the local driver circuit LD[m,n] drives the pixels included in the pixel region ARA[m,n]. That is, although not shown in Fig. 3B, the local driver circuit LD[i,j] located in row i and column j (i is an integer between 1 and m, and j is an integer between 1 and n) drives the pixels included in the pixel area ARA[i,j]. Note that in Fig. 3B, as an example, the correspondence between the pixel area ARA and the local driver circuit LD that drives the pixels included in that pixel area ARA is shown by a thick arrow.

[0091] Note that the display device according to one embodiment of the present invention is not limited to the configuration shown in FIGS. 3A and 3B . The display device according to one embodiment of the present invention may be modified as appropriate within the scope of resolving the problem. For example, the local driver circuit LD may be provided in a region overlapping the corresponding pixel region ARA. Specifically, the display device 10 may have the configuration shown in FIGS. 4A and 4B . FIG. 4A shows an example of the configuration of the circuit layer SICL in the display device 10, and FIG. 4B shows an example of the configuration of the pixel layer PXAL in the display device 10. As shown in FIGS. 4A and 4B , the local driver circuit LD[i,j] corresponding to the pixel region ARA[i,j] is provided in a region overlapping the corresponding pixel region ARA[i,j].

[0092] The drive circuit region DRV in the circuit layer SICL in Fig. 4A can be an region in which the local driver circuits LD[1,1] to LD[m,n] are provided. The controller CON and the voltage generation circuit PG in the circuit layer SICL in Fig. 4A can be provided in a region in which the local driver circuits LD[1,1] to LD[m,n] are not provided.

[0093] Furthermore, the area LIA in the circuit layer SICL in FIG. 4A can be an area in which the local driver circuits LD[1,1] to LD[m,n], the controller CON, and the voltage generating circuit PG are not provided.

[0094] However, when the resolution of the pixel array ALP included in the pixel layer PXAL is increased, the number of pixels included in the pixel array ALP increases, which may increase the area of ​​the local driver circuit LD that drives the display device 10. Furthermore, the area of ​​the local driver circuit LD can be reduced by reducing the size of circuit elements, such as transistors, included in the local driver circuit LD. However, reducing the size of the circuit elements may increase the likelihood of variations in the characteristics of the circuit elements, which may result in the local driver circuit LD not performing the desired operation. Furthermore, even if the size of the circuit elements is not reduced, the local driver circuit LD may not perform the desired operation due to factors related to the manufacturing process of the display device 10.

[0095] Therefore, it is preferable that the display device 10 has redundancy in case the local driver circuit LD does not operate normally.

[0096] 1A is a schematic perspective view showing a configuration example of a pixel region ARA and a local driver circuit LD included in a display device according to one embodiment of the present invention. The configuration example shown in FIG. 1A is a perspective view of a portion of the plan views shown in FIGS. 4A and 4B. The configuration example of the pixel region ARA and the local driver circuit LD shown in FIG. 1A has a redundant circuit configuration in case the local driver circuit LD does not operate normally.

[0097] The configuration example in Figure 1A shows an excerpt of a local driver circuit LD[a,b] (where a is an integer greater than or equal to 1 and less than or equal to m-1, and b is an integer greater than or equal to 1 and less than or equal to n), a pixel area ARA[a,b] overlapping the local driver circuit LD[a,b], a local driver circuit LD[a+1,b], and a pixel area ARA[a+1,b] overlapping the local driver circuit LD[a+1,b].

[0098] Furthermore, each of the local driver circuits LD[a, b] and LD[a+1, b] includes a drive circuit SD.

[0099] Each of the pixel areas ARA[a,b] and ARA[a+1,b] includes a plurality of pixel circuits PX. In each of the pixel areas ARA[a,b] and ARA[a+1,b], the plurality of pixel circuits PX are arranged in a matrix, for example. In this embodiment, in each of the pixel areas ARA[a,b] and ARA[a+1,b], the plurality of pixel circuits PX are arranged in a matrix of p rows and q columns (p is an integer greater than or equal to 1, and q is an integer greater than or equal to 1).

[0100] The pixel layer PXAL also includes switches SSW(a, a+1)_1 to SSW(a, a+1)_q. The switches SSW(a, a+1)_1 to SSW(a, a+1)_q are preferably provided between the pixel regions ARA[a, b] and ARA[a+1, b].

[0101] Further, the drive circuit SD included in the local driver circuit LD[a,b] is electrically connected to, for example, wirings SL[a,b]_1 to SL[a,b]_q. Further, the wirings SL[a,b]_1 to SL[a,b]_q extend along the column direction of the pixel region ARA[a,b] via, for example, a wiring layer LINL. Similarly, the drive circuit SD included in the local driver circuit LD[a+1,b] is electrically connected to, for example, wirings SL[a+1,b]_1 to SL[a+1,b]_q. Further, the wirings SL[a+1,b]_1 to SL[a+1,b]_q extend along the column direction of the pixel region ARA[a,b] via, for example, a wiring layer LINL.

[0102] In the pixel region ARA[a,b], the wirings SL[a,b]_1 to SL[a,b]_q are electrically connected to the pixel circuits PX arranged in each column. Similarly, in the pixel region ARA[a+1,b], the wirings SL[a+1,b]_1 to SL[a+1,b]_q are electrically connected to the pixel circuits PX arranged in each column.

[0103] Furthermore, in the pixel layer PXAL (pixel regions ARA[a,b] and ARA[a+1,b]), the wirings SL[a,b]_1 to SL[a,b]_q are electrically connected to the first terminals of the switches SSW(a,a+1)_1 to SSW(a,a+1)_q, respectively, in a one-to-one relationship. Specifically, for example, in FIG. 1A, the wiring SL[a,b]_1 is electrically connected to the first terminal of the switch SSW(a,a+1)_1, and the wiring SL[a,b]_q is electrically connected to the first terminal of the switch SSW(a,a+1)_q.

[0104] Similarly, in the pixel layer PXAL (pixel regions ARA[a,b] and ARA[a+1,b]), the wirings SL[a+1,b]_1 to SL[a+1,b]_q are electrically connected to the second terminals of the switches SSW(a,a+1)_1 to SSW(a,a+1)_q in a one-to-one relationship. Specifically, for example, in FIG. 1A, the wiring SL[a+1,b]_1 is electrically connected to the second terminal of the switch SSW(a,a+1)_1, and the wiring SL[a+1,b]_q is electrically connected to the second terminal of the switch SSW(a,a+1)_q.

[0105] As an example, the drive circuit SD has a function as a source driver circuit that transmits image data to the pixel circuits PX included in the pixel array ALP.

[0106] The pixel circuit PX has, for example, a display device. The display device can be, for example, a light-emitting device. The light-emitting device described in this embodiment refers to a self-luminous light-emitting device such as an organic EL element (also called an OLED (Organic Light Emitting Diode)). Note that the light-emitting device electrically connected to the pixel circuit can be a self-luminous light-emitting device such as an LED (Light Emitting Diode), a micro LED, a QLED (Quantum-dot Light Emitting Diode), or a semiconductor laser.

[0107] The pixel circuits PX have a function of receiving image data transmitted from the drive circuit SD via the wiring SL and causing the light emitting devices to emit light with a light emission intensity according to the image data.

[0108] As the switches SSW(a, a+1)_1 to SSW(a, a+1)_q, for example, electrical switches such as analog switches and transistors can be applied. Note that, when transistors are applied as the switches SSW(a, a+1)_1 to SSW(a, a+1)_q, the transistors can be transistors with similar structures such as Si transistors and OS transistors. Furthermore, in addition to electrical switches, mechanical switches may also be applied.

[0109] 1A, when the drive circuits SD of the local driver circuit LD[a,b] and the local driver circuit LD[a+1,b] operate properly, the switches SSW(a,a+1)_1 to SSW(a,a+1)_q are each turned off. Specifically, for example, when the drive circuit SD of the local driver circuit LD[a,b] transmits image data to a plurality of pixel circuits PX included in the pixel area ARA[a,b] and the drive circuit SD of the local driver circuit LD[a+1,b] transmits image data to a plurality of pixel circuits PX included in the pixel area ARA[a+1,b], the switches SSW(a,a+1)_1 to SSW(a,a+1)_q are each turned off.

[0110] 1A, when one of the drive circuits SD of the local driver circuit LD[a,b] and the local driver circuit LD[a+1,b] does not operate properly (when a malfunction occurs in one of the drive circuits SD), each of the switches SSW(a,a+1)_1 to SSW(a,a+1)_q is turned on. Specifically, for example, when a malfunction occurs in the drive circuit SD of the local driver circuit LD[a+1,b] and image data cannot be transmitted to the plurality of pixel circuits PX included in the pixel area ARA[a+1,b], the drive circuit SD of the local driver circuit LD[a,b] transmits image data to the plurality of pixel circuits PX included in each of the pixel areas ARA[a,b] and ARA[a+1,b]. Also, for example, if a malfunction occurs in the drive circuit SD of the local driver circuit LD[a,b] and image data cannot be transmitted to the multiple pixel circuits PX included in the pixel area ARA[a,b], the drive circuit SD of the local driver circuit LD[a+1,b] transmits image data to the multiple pixel circuits PX included in each of the pixel areas ARA[a,b] and ARA[a+1,b].

[0111] 1A to the display device 10, if a malfunction occurs in one of the drive circuits SD included in each of adjacent local driver circuits LD, the other of the drive circuits SD included in each of the adjacent local driver circuits LD can transmit image data to the pixel circuits PX included in each of the pixel areas ARA[a,b] and ARA[a+1,b] by establishing a conductive state between the wiring SL[a,b] and the wiring SL[a+1,b] that extend in the same column using the switch SSW(a,a+1). Therefore, by applying the configuration example shown in FIG. 1A to the display device 10, redundancy can be imparted to the drive circuits SD included in each of the local driver circuits LD[a,b] and LD[a+1,b].

[0112] Note that, although FIG. 1A shows an example of a configuration in which redundancy is provided to the drive circuits SD included in each of the local driver circuits LD[a,b] and the local driver circuits LD[a+1,b], for example, redundancy may also be provided to the drive circuits SD included in each of the local driver circuits LD[a,b] and the local driver circuits LD[a,b+1].

[0113] Furthermore, one embodiment of the present invention is not limited to the display device to which the configuration example of Fig. 1A is applied. The display device of one embodiment of the present invention may be modified as appropriate within the scope of solving the problem.

[0114] For example, FIG. 1A shows a configuration in which switches SSW(a,a+1)_1 to SSW(a,a+1)_q are provided between pixel regions ARA[a,b] and ARA[a+1,b]. However, a display device of one embodiment of the present invention may have a configuration in which switches similar to switches SSW(a,a+1)_1 to SSW(a,a+1)_q are provided between each of three or more pixel regions ARA that are arranged in succession. 1B, in three consecutively arranged pixel regions ARA[a,b] to ARA[a+2,b] (where a is an integer between 1 and m-2), switches SSW(a,a+1)_1 to SSW(a,a+1)_q may be provided between the pixel regions ARA[a,b] and ARA[a+1,b], and switches SSW(a+1,a+2)_1 to SSW(a+1,a+2)_q may be provided between the pixel regions ARA[a+1,b] and ARA[a+2,b]. Note that in FIG. 1B, the drive circuit SD included in the local driver circuit LD[a+2,b] is electrically connected to the pixel circuit PX included in the pixel region ARA[a+2,b] via wirings SL[a+2,b]_1 to SL[a+2,b]_q.

[0115] By applying the configuration example of Figure 1B to a display device of one embodiment of the present invention, when two of the local driver circuits LD[a,b] to LD[a+2,b] malfunction, the remaining local driver circuit LD can transmit image data to the pixel circuits PX included in each of the pixel areas ARA[a,b] to ARA[a+2,b].

[0116] Similarly, switches SSW may be provided between all of the adjacent pixel areas ARA in the display device 10 of Fig. 4. In the display device 10 of Fig. 4, when the drive circuits SD included in all of the local driver circuits LD operate properly, all of the switches SSW included in the display device 10 are turned off, and when some of the drive circuits SD included in all of the local driver circuits LD do not operate properly, image data can be transmitted to the pixels included in the pixel area ARA that overlaps the drive circuit SD that does not operate properly by the drive circuit SD of a local driver circuit LD that is different from the local driver circuit LD that includes the drive circuit SD that does not operate properly.

[0117] 1A shows a configuration in which the switches SSW(a,a+1)_1 to SSW(a,a+1)_q are provided between the pixel regions ARA[a,b] and ARA[a+1,b] of the pixel layer PXAL. However, in a display device of one embodiment of the present invention, the switches SSW(a,a+1)_1 to SSW(a,a+1)_q may be provided between the local driver circuits LD[a,b] and LD[a+1,b] of the circuit layer SICL. As a specific example, such a configuration is shown in FIG. 5A. By providing the switches SSW(a,a+1)_1 to SSW(a,a+1)_q in the circuit layer SICL, an area for providing the switches SSW(a,a+1)_1 to SSW(a,a+1)_q is not required in the pixel layer PXAL. Therefore, in the pixel array ALP of the pixel layer PXAL, for example, pixel circuits can be added and arranged in an area where it is no longer necessary to provide the switches SSW(a, a+1)_1 to SSW(a, a+1)_q. In particular, by adding pixel circuits, the resolution of the display device can be increased.

[0118] 1A illustrates a configuration in which one of the driver circuits SD of the local driver circuit LD[a,b] and the local driver circuit LD[a+1,b] transmits image data to the pixel circuits PX included in the pixel areas ARA[a,b] and ARA[a+1,b], respectively. However, in a display device according to one embodiment of the present invention, a switch may be provided between the pixel areas ARA[a,b] and ARA[a,b+1] to provide redundancy to the driver circuits included in the local driver circuit LD[a,b] and the local driver circuit LD[a,b+1]. The driver circuit may be the driver circuit SD, or a driver circuit GD that transmits a selection signal to select a pixel circuit PX to which the image data is to be transmitted. Specifically, for example, in a display device according to one embodiment of the present invention, switches GSW(b,b+1)_1 to GSW(b,b+1)_p may be provided between the pixel areas ARA[a,b] and ARA[a,b+1], as illustrated in FIG.

[0119] 5B, each of the local driver circuits LD[a,b] and LD[a,b+1] includes a driver circuit GD. The driver circuit GD included in the local driver circuit LD[a,b] is electrically connected to the wirings GL[a,b]_1 to GL[a,b]_p, for example. The wirings GL[a,b]_1 to GL[a,b]_p extend along the row direction of the pixel region ARA[a,b] via a wiring layer LINL, for example. Similarly, the driver circuit GD included in the local driver circuit LD[a,b+1] is electrically connected to the wirings GL[a,b+1]_1 to GL[a,b+1]_p, for example. The wirings GL[a,b]_1 to GL[a,b+1]_p extend along the row direction of the pixel region ARA[a,b+1] via a wiring layer LINL, for example.

[0120] In the pixel region ARA[a,b], each of the wirings GL[a,b]_1 to GL[a,b]_p is electrically connected to a plurality of pixel circuits PX arranged in each row. Similarly, in the pixel region ARA[a,b+1], each of the wirings GL[a,b+1]_1 to GL[a,b+1]_p is electrically connected to a plurality of pixel circuits PX arranged in each row.

[0121] Furthermore, in the pixel layer PXAL (pixel regions ARA[a,b] and ARA[a,b+1]), the wirings GL[a,b]_1 to GL[a,b]_p are electrically connected to the first terminals of the switches GSW(b,b+1)_1 to GSW(b,b+1)_p, respectively, in a one-to-one relationship. Specifically, for example, in FIG. 5B, the wiring GL[a,b]_1 is electrically connected to the first terminal of the switch GSW(b,b+1)_1, and the wiring GL[a,b]_p is electrically connected to the first terminal of the switch GSW(b,b+1)_p.

[0122] Similarly, in the pixel layer PXAL (pixel regions ARA[a,b] and ARA[a,b+1]), the wirings GL[a,b+1]_1 to GL[a,b+1]_p are electrically connected to the second terminals of the switches GSW(b,b+1)_1 to GSW(b,b+1)_p in a one-to-one relationship. Specifically, in FIG. 5B, for example, the wiring GL[a,b+1]_1 is electrically connected to the second terminal of the switch GSW(b,b+1)_1, and the wiring GL[a,b+1]_p is electrically connected to the second terminal of the switch GSW(b,b+1)_p.

[0123] As an example, the drive circuit GD functions as a gate driver circuit that transmits a selection signal line to select a pixel circuit PX included in the pixel array ALP as a destination of image data.

[0124] As switches GSW(b, b+1)_1 to switches GSW(b, b+1)_p, for example, switches applicable to switches SSW(a, a+1)_1 to switches SSW(a, a+1)_q can be used.

[0125] 5B, when the drive circuits GD of the local driver circuit LD[a,b] and the local driver circuit LD[a,b+1] operate properly, the switches GSW(b,b+1)_1 to GSW(b,b+1)_p are each turned off. Specifically, for example, when the drive circuit GD of the local driver circuit LD[a,b] transmits selection signals to the plurality of pixel circuits PX included in the pixel area ARA[a,b] and the drive circuit GD of the local driver circuit LD[a,b+1] transmits image data to the plurality of pixel circuits PX included in the pixel area ARA[a,b+1], the switches GSW(b,b+1)_1 to SSW(b,b+1)_p are each turned off.

[0126] 5B, when one of the drive circuits GD of the local driver circuit LD[a,b] and the local driver circuit LD[a,b+1] does not operate properly (when a malfunction occurs in one of the drive circuits GD), each of the switches GSW(b,b+1)_1 to GSW(b,b+1)_p is turned on. Specifically, for example, when a malfunction occurs in the drive circuit GD of the local driver circuit LD[a,b+1] and selection signals cannot be transmitted to the plurality of pixel circuits PX included in the pixel area ARA[a,b+1], the drive circuit GD of the local driver circuit LD[a,b] transmits selection signals to the plurality of pixel circuits PX included in each of the pixel areas ARA[a,b] and ARA[a,b+1]. Furthermore, for example, if a malfunction occurs in the drive circuit GD of the local driver circuit LD[a,b] and a selection signal cannot be transmitted to the plurality of pixel circuits PX included in the pixel area ARA[a,b], the drive circuit GD of the local driver circuit LD[a,b+1] transmits a selection signal to the plurality of pixel circuits PX included in each of the pixel areas ARA[a,b] and ARA[a,b+1].

[0127] 5B, when a malfunction occurs in one of the drive circuits GD included in each of adjacent local driver circuits LD, by establishing a conductive state between the wiring GL[a, b] and the wiring GL[a, b+1] extending in the same column using the switch GSW(b, b+1), the other of the drive circuits GD included in each of the adjacent local driver circuits LD can transmit a selection signal to the pixel circuits PX included in each of the pixel areas ARA[a, b] and ARA[a, b+1]. Therefore, by configuring the display device 10 shown in FIG. 5B, redundancy can be provided to the drive circuits GD included in each of the local driver circuits LD[a, b] and LD[a, b+1].

[0128] Note that, although FIG. 5B shows a configuration example in which redundancy is provided to the drive circuits GD included in each of the local driver circuits LD[a,b] and the local driver circuit LD[a,b+1], for example, redundancy may also be provided to the drive circuits GD included in each of the local driver circuits LD[a,b] and the local driver circuit LD[a+1,b].

[0129] <Example 1> Next, a description will be given of an example of the operation of the above-described display device 10. Note that, as an example, the description will be given of an example of the operation of the display device 10A shown in FIG.

[0130] The display device 10A shown in FIG. 6 is a modified example of the configuration shown in FIG. 1A, and illustrates a display device in which a is 1 and b is 1. That is, the display device 10A has pixel regions ARA[1,1] and ARA[2,1]. The display device 10A also has pixel circuits PX[1,1] to PX[8,4] arranged in an 8-row, 4-column matrix. The pixel region ARA[1,1] has pixel circuits PX[1,1] to PX[4,4] arranged in a 4-row, 4-column matrix, and the pixel region ARA[2,1] has pixel circuits PX[5,1] to PX[8,4] arranged in a 4-row, 4-column matrix.

[0131] In the pixel region ARA[1,1], the wirings SL[1,1]_1 to SL[1,1]_4 extend in the column direction, and the wirings GL[1,1]_1 to GL[1,1]_4 extend in the row direction. In the pixel region ARA[2,1], the wirings SL[2,1]_1 to SL[2,1]_4 extend in the column direction, and the wirings GL[2,1]_1 to GL[2,1]_4 extend in the row direction.

[0132] In the pixel region ARA[1,1], the wirings SL[1,1]_1 to SL[1,1]_4 are electrically connected to the pixel circuits PX arranged in each column. For example, the wiring SL[1,1]_1 is electrically connected to the pixel circuits PX[1,1] to PX[4,1], and the wiring SL[1,1]_4 is electrically connected to the pixel circuits PX[1,4] to PX[4,4]. In addition, in the pixel region ARA[1,1], the wirings GL[1,1]_1 to GL[1,1]_4 are electrically connected to the pixel circuits PX arranged in each row. For example, the wiring GL[1,1]_1 is electrically connected to the pixel circuits PX[1,1] to PX[1,4], and the wiring GL[1,1]_4 is electrically connected to the pixel circuits PX[4,1] to PX[4,4].

[0133] In the pixel region ARA[2,1], the wirings SL[2,1]_1 to SL[2,1]_4 are electrically connected to the pixel circuits PX arranged in each column. For example, the wiring SL[2,1]_1 is electrically connected to the pixel circuits PX[5,1] to PX[8,1], and the wiring SL[2,1]_4 is electrically connected to the pixel circuits PX[5,4] to PX[8,4]. In addition, in the pixel region ARA[2,1], the wirings GL[2,1]_1 to GL[2,1]_4 are electrically connected to the pixel circuits PX arranged in each row. For example, the wiring GL[2,1]_1 is electrically connected to the pixel circuits PX[5,1] to PX[5,4], and the wiring GL[2,1]_4 is electrically connected to the pixel circuits PX[8,1] to PX[8,4].

[0134] The driver circuit SD included in the local driver circuit LD[1,1] is electrically connected to the wirings SL[1,1]_1 to SL[1,1]_4. The driver circuit GD included in the local driver circuit LD[1,1] is electrically connected to the wirings GL[1,1]_1 to GL[1,1]_4. The driver circuit SD included in the local driver circuit LD[2,1] is electrically connected to the wirings SL[2,1]_1 to SL[2,1]_4. The driver circuit GD included in the local driver circuit LD[2,1] is electrically connected to the wirings GL[2,1]_1 to GL[2,1]_4.

[0135] The display device 10A also has switches SSW(1,2)_1 to SSW(1,2)_4. First terminals of the switches SSW(1,2)_1 to SSW(1,2)_4 are electrically connected in a one-to-one relationship to the wirings SL[1,1]_1 to SL[1,1]_4 of the respective columns of the pixel region ARA[1,1], and second terminals of the switches SSW(1,2)_1 to SSW(1,2)_4 are electrically connected in a one-to-one relationship to the wirings SL[2,1]_1 to SL[2,1]_4 of the respective columns of the pixel region ARA[2,1]. Specifically, the first terminal of the switch SSW(1,2)_1 is electrically connected to the wiring SL[1,1]_1, and the second terminal of the switch SSW(1,2)_1 is electrically connected to the wiring SL[2,1]_1. Furthermore, a first terminal of the switch SSW(1,2)_4 is electrically connected to the line SL[1,1]_4, and a second terminal of the switch SSW(1,2)_4 is electrically connected to the line SL[2,1]_4.

[0136] Next, a case will be described in which the driver circuits SD and GD included in the local driver circuits LD[1,1] and LD[2,1], respectively, of the display device 10A of Fig. 6 operate properly. Fig. 7 is a timing chart showing an example of the operation of the display device 10A when the local driver circuits LD[1,1] and LD[2,1] operate properly. The timing chart of Fig. 7 shows data signals input to the wirings SL[1,1]_1 to SL[1,1]_4 and SL[2,1]_1 to SL[2,1]_4 and changes in potentials input to the wirings GL[1,1]_1 to GL[1,1]_4 and GL[2,1]_1 to GL[2,1]_4 between time T1 and time T16 and around those times.

[0137] In the operation example of the timing chart of FIG. 7, it is assumed that each of the switches SSW(1,2)_1 to SSW(1,2)_4 is in the OFF state.

[0138] In the timing chart of FIG. 7, time passes in the order of time T1, time T2, time T3, time T4, time T5, time T6, time T7, time T8, time T9, time T10, time T11, time T12, time T13, time T14, time T15, and time T16.

[0139] When a high-level potential is applied to at least one of the wirings GL[1,1]_1 to GL[1,1]_4 or the wirings GL[2,1]_1 to GL[2,1]_4, the write transistor of the pixel circuit PX electrically connected to the wiring GL to which the high-level potential is applied is turned on. In other words, during a period in which a high-level potential is applied to any one of the wirings GL[1,1]_1 to GL[1,1]_4 or the wirings GL[2,1]_1 to GL[2,1]_4, image data can be written to the pixel circuit PX electrically connected to the wiring GL to which the high-level potential is applied.

[0140] Before time T1, a low-level potential is input from the driving circuits GD of the local driver circuits LD[1,1] and LD[1,2] to the wirings GL[1,1]_1 to GL[1,1]_4 and the wirings GL[2,1]_1 to GL[2,1]_4. Note that in FIG. 7, the low-level potential is indicated as "Low." Therefore, the write transistors of the pixel circuits PX electrically connected to the wirings GL[1,1]_1 to GL[1,1]_4 and the wirings GL[2,1]_1 to GL[2,1]_4 are turned off. In other words, no image data is written to the pixel circuits PX included in the pixel areas ARA[1,1] and ARA[2,1].

[0141] Between time T1 and time T6, a high-level potential is input from the driving circuit GD of the local driver circuit LD[1,1] to the wiring GL[1,1]_1. Note that in FIG. 7, the high-level potential is indicated as "High." Therefore, between time T1 and time T6, image data can be written to the pixel circuits PX[1,1] to PX[1,4] electrically connected to the wiring GL[1,1]_1.

[0142] Between time T2 and time T5, data D[1,1], data D[1,2], data D[1,3], and data D[1,4] are sequentially input as image data from the drive circuit SD of the local driver circuit LD[1,1] to the wirings SL[1,1]_1 to SL[1,1]_4, respectively. As a result, data D[1,1] is written to the pixel circuit PX[1,1], data D[1,2] is written to the pixel circuit PX[1,2], data D[1,3] is written to the pixel circuit PX[1,3], and data D[1,4] is written to the pixel circuit PX[1,4].

[0143] After time T6, a low-level potential is input to the wiring GL[1,1]_1 from the drive circuit GD of the local driver circuit LD[1,1]. Therefore, after time T6, the write transistors of the pixel circuits PX[1,1] to PX[1,4] electrically connected to the wiring GL[1,1]_1 are turned off, and the data D[1,1] to D[1,4] written before time T6 are held in the pixel circuits PX[1,1] to PX[1,4], respectively.

[0144] Between time T3 and time T8, a high-level potential is input from the driving circuit GD of the local driver circuit LD[2,1] to the wiring GL[2,1]_1, which allows image data to be written to the pixel circuits PX[5,1] to PX[5,4] electrically connected to the wiring GL[2,1]_1.

[0145] Between time T4 and time T7, data D[5,1], data D[5,2], data D[5,3], and data D[5,4] are sequentially input as image data from the drive circuit SD of the local driver circuit LD[2,1] to the wirings SL[2,1]_1 to SL[2,1]_4, respectively. As a result, data D[5,1] is written to the pixel circuit PX[5,1], data D[5,2] is written to the pixel circuit PX[5,2], data D[5,3] is written to the pixel circuit PX[5,3], and data D[5,4] is written to the pixel circuit PX[5,4].

[0146] After time T8, a low-level potential is input to the wiring GL[2,1]_1 from the drive circuit GD of the local driver circuit LD[2,1]. Therefore, after time T8, the write transistors of the pixel circuits PX[5,1] to PX[5,4] electrically connected to the wiring GL[2,1]_1 are turned off, and the data D[5,1] to D[5,4] written before time T8 are held in the pixel circuits PX[5,1] to PX[5,4], respectively.

[0147] Between time T9 and time T14, a high-level potential is input from the drive circuit GD of the local driver circuit LD[1,1] to the wiring GL[1,1]_2, which allows image data to be written to the pixel circuits PX[2,1] to PX[2,4] electrically connected to the wiring GL[1,1]_2.

[0148] Between time T10 and time T13, data D[2,1], data D[2,2], data D[2,3], and data D[2,4] are sequentially input as image data from the drive circuit SD of the local driver circuit LD[1,1] to the wirings SL[1,1]_1 to SL[1,1]_4, respectively. As a result, data D[2,1] is written to the pixel circuit PX[2,1], data D[2,2] is written to the pixel circuit PX[2,2], data D[2,3] is written to the pixel circuit PX[2,3], and data D[2,4] is written to the pixel circuit PX[2,4].

[0149] After time T14, a low-level potential is input to the wiring GL[1,1]_2 from the drive circuit GD of the local driver circuit LD[1,1]. Therefore, after time T14, the write transistors of the pixel circuits PX[2,1] to PX[2,4] electrically connected to the wiring GL[1,1]_2 are turned off, and the pixel circuits PX[2,1] to PX[2,4] hold the data D[2,1] to D[2,4] written before time T14.

[0150] Between time T11 and time T16, a high-level potential is input from the drive circuit GD of the local driver circuit LD[2,1] to the wiring GL[2,1]_1, which allows image data to be written to the pixel circuits PX[5,1] to PX[5,4] electrically connected to the wiring GL[2,1]_1 between time T3 and time T8.

[0151] Between time T12 and time T15, data D[6,1], data D[6,2], data D[6,3], and data D[6,4] are sequentially input as image data from the drive circuit SD of the local driver circuit LD[2,1] to the wirings SL[2,1]_1 to SL[2,1]_4, respectively. As a result, data D[6,1] is written to the pixel circuit PX[6,1], data D[6,2] is written to the pixel circuit PX[6,2], data D[6,3] is written to the pixel circuit PX[6,3], and data D[6,4] is written to the pixel circuit PX[6,4].

[0152] After time T16, a low-level potential is input to the wiring GL[2,1]_2 from the drive circuit GD of the local driver circuit LD[2,1]. Therefore, after time T16, the write transistors of the pixel circuits PX[6,1] to PX[6,4] electrically connected to the wiring GL[2,1]_2 are turned off, and the data D[6,1] to D[6,4] written before time T8 are held in the pixel circuits PX[6,1] to PX[6,4], respectively.

[0153] Furthermore, from time T16 onwards, similar to the operation from time T1 to time T8 or the operation from time T9 to time T16, by sending a selection signal (by inputting a high-level potential) to any of the wirings GL[1,1]_3, GL[1,1]_4, GL[2,1]_3, and GL[2,1]_4, image data can also be written to the pixel circuits PX[3,1] to PX[4,4] included in the pixel area ARA[1,1] and the pixel circuits PX[7,1] to PX[8,4] included in the pixel area ARA[2,1].

[0154] Next, a case will be described in which one of the drive circuits SD included in each of the local driver circuits LD[1,1] and LD[2,1] does not operate properly in the display device 10A of Fig. 6. Fig. 8 is a timing chart showing an example of the operation of the display device 10A when one of the drive circuits SD included in each of the local driver circuits LD[1,1] and LD[2,1] does not operate properly. Note that the explanation of the timing chart of Fig. 7 should be referred to for the wiring, potentials, and data shown in the timing chart of Fig. 8.

[0155] In the operation example of the timing chart of Fig. 8, each of the switches SSW(1,2)_1 to SSW(1,2)_4 is assumed to be in an on state. Therefore, in the operation example of the timing chart of Fig. 8, the same data is input to the wiring SL[1,1]_1 and the wiring SL[2,1]_1. Similarly, the same data is input to the wiring SL[1,1]_2 and the wiring SL[2,1]_2, the same data is input to the wiring SL[1,1]_3 and the wiring SL[2,1]_3, and the same data is input to the wiring SL[1,1]_4 and the wiring SL[2,1]_4.

[0156] Before time T1, a low-level potential is input from the driving circuits GD of the local driver circuit LD[1,1] and the local driver circuit LD[1,2] to the wirings GL[1,1]_1 to GL[1,1]_4 and the wirings GL[2,1]_1 to GL[2,1]_4. Note that in FIG. 8, the low-level potential is indicated as "Low." Therefore, the write transistors of the pixel circuits PX electrically connected to the wirings GL[1,1]_1 to GL[1,1]_4 and the wirings GL[2,1]_1 to GL[2,1]_4 are turned off. In other words, no image data is written to the pixel circuits PX included in the pixel areas ARA[1,1] and ARA[2,1].

[0157] Between time T1 and time T6, a high-level potential is input from the driving circuit GD of the local driver circuit LD[1,1] to the wiring GL[1,1]_1. Note that in FIG. 8, the high-level potential is indicated as "High." Therefore, between time T1 and time T6, image data can be written to the pixel circuits PX[1,1] to PX[1,4] electrically connected to the wiring GL[1,1]_1.

[0158] Between time T2 and time T5, data D[1,1], data D[1,2], data D[1,3], and data D[1,4] are sequentially input as image data to the wirings SL[1,1]_1 to SL[1,1]_4 and the wirings SL[2,1]_1 to SL[2,1]_4 from the drive circuit SD of either the local driver circuit LD[1,1] or the local driver circuit LD[2,1]. As a result, data D[1,1] is written to the pixel circuit PX[1,1], data D[1,2] is written to the pixel circuit PX[1,2], data D[1,3] is written to the pixel circuit PX[1,3], and data D[1,4] is written to the pixel circuit PX[1,4].

[0159] After time T6, a low-level potential is input to the wiring GL[1,1]_1 from the drive circuit GD of the local driver circuit LD[1,1]. Therefore, after time T6, the write transistors of the pixel circuits PX[1,1] to PX[1,4] electrically connected to the wiring GL[1,1]_1 are turned off, and the pixel circuits PX[1,1] to PX[1,4] hold the data D[1,1] to D[1,4] written before time T6, respectively.

[0160] Between time T9 and time T14, a high-level potential is input from the drive circuit GD of the local driver circuit LD[2,1] to the wiring GL[2,1]_1, which allows image data to be written to the pixel circuits PX[5,1] to PX[5,4] electrically connected to the wiring GL[2,1]_1.

[0161] Between time T10 and time T13, data D[5,1], data D[5,2], data D[5,3], and data D[5,4] are sequentially input as image data to the wirings SL[1,1]_1 to SL[1,1]_4 and the wirings SL[2,1]_1 to SL[2,1]_4 from the drive circuit SD of either the local driver circuit LD[1,1] or the local driver circuit LD[2,1]. As a result, data D[5,1] is written to the pixel circuit PX[5,1], data D[5,2] is written to the pixel circuit PX[5,2], data D[5,3] is written to the pixel circuit PX[5,3], and data D[5,4] is written to the pixel circuit PX[5,4].

[0162] After time T14, a low-level potential is input to the wiring GL[2,1]_1 from the drive circuit GD of the local driver circuit LD[2,1]. Therefore, after time T14, the write transistors of the pixel circuits PX[5,1] to PX[5,4] electrically connected to the wiring GL[2,1]_1 are turned off, and the data D[5,1] to D[5,4] written before time T14 are held in the pixel circuits PX[5,1] to PX[5,4], respectively.

[0163] Furthermore, from time T14 onwards, similar to the operation from time T1 to time T6 or the operation from time T9 to time T14, by sending a selection signal (by inputting a high-level potential) to any of the wirings GL[1,1]_2, GL[1,1]_3, GL[1,1]_4, GL[2,1]_2, GL[2,1]_3, and GL[2,1]_4, image data can also be written to the pixel circuits PX[2,1] to PX[4,4] included in the pixel area ARA[1,1] and the pixel circuits PX[6,1] to PX[8,4] included in the pixel area ARA[2,1].

[0164] Furthermore, in the display device 10A, even if one of the drive circuits SD included in each of the local driver circuits LD[1,1] and LD[2,1] does not operate properly, image data can be written to each of the multiple pixel circuits PX included in the display device 10A by performing the operation example of the timing chart of Figure 8.

[0165] <Example 2> While the above describes an example of the operation of the display device 10 when one of the drive circuits SD included in the local driver circuits LD corresponding to each of adjacent pixel areas ARA does not operate properly, here we will describe an example of the operation of the display device 10 when one of the drive circuits GD included in the local driver circuits LD corresponding to each of adjacent pixel areas ARA does not operate properly. Note that here, as an example, we will describe an example of the operation of the display device 10B shown in Figure 9.

[0166] The display device 10B shown in FIG. 9 is a modified example of the display device 10 shown in FIG. 5B, and illustrates a display device in which a is 1 and b is 1. That is, the display device 10B has pixel regions ARA[1,1] and ARA[1,2]. The display device 10B also has pixel circuits PX[1,1] to PX[4,8] arranged in a matrix of 4 rows and 8 columns. The pixel region ARA[1,1] has pixel circuits PX[1,1] to PX[4,4] arranged in a matrix of 4 rows and 4 columns, and the pixel region ARA[1,2] has pixel circuits PX[1,5] to PX[4,8] arranged in a matrix of 4 rows and 4 columns.

[0167] In the pixel region ARA[1,1], the wirings SL[1,1]_1 to SL[1,1]_4 extend in the column direction, and the wirings GL[1,1]_1 to GL[1,1]_4 extend in the row direction. In the pixel region ARA[1,2], the wirings SL[1,2]_1 to SL[1,2]_4 extend in the column direction, and the wirings GL[1,2]_1 to GL[1,2]_4 extend in the row direction.

[0168] In the pixel region ARA[1,1], the wirings SL[1,1]_1 to SL[1,1]_4 are electrically connected to the pixel circuits PX arranged in each column. For example, the wiring SL[1,1]_1 is electrically connected to the pixel circuits PX[1,1] to PX[4,1], and the wiring SL[1,1]_4 is electrically connected to the pixel circuits PX[1,4] to PX[4,4]. In addition, in the pixel region ARA[1,1], the wirings GL[1,1]_1 to GL[1,1]_4 are electrically connected to the pixel circuits PX arranged in each row. For example, the wiring GL[1,1]_1 is electrically connected to the pixel circuits PX[1,1] to PX[1,4], and the wiring GL[1,1]_4 is electrically connected to the pixel circuits PX[4,1] to PX[4,4].

[0169] In the pixel region ARA[1,2], the wirings SL[1,2]_1 to SL[1,2]_4 are electrically connected to the pixel circuits PX arranged in each column. For example, the wiring SL[1,2]_1 is electrically connected to the pixel circuits PX[1,5] to PX[4,5], and the wiring SL[1,2]_4 is electrically connected to the pixel circuits PX[1,8] to PX[4,8]. In addition, in the pixel region ARA[1,2], the wirings GL[1,2]_1 to GL[1,2]_4 are electrically connected to the pixel circuits PX arranged in each row. For example, the wiring GL[1,2]_1 is electrically connected to the pixel circuits PX[1,5] to PX[1,8], and the wiring GL[1,2]_4 is electrically connected to the pixel circuits PX[4,5] to PX[4,8].

[0170] The driver circuit SD included in the local driver circuit LD[1,1] is electrically connected to the wirings SL[1,1]_1 to SL[1,1]_4. The driver circuit GD included in the local driver circuit LD[1,1] is electrically connected to the wirings GL[1,1]_1 to GL[1,1]_4. The driver circuit SD included in the local driver circuit LD[1,2] is electrically connected to the wirings SL[1,2]_1 to SL[1,2]_4. The driver circuit GD included in the local driver circuit LD[1,2] is electrically connected to the wirings GL[1,2]_1 to GL[1,2]_4.

[0171] The display device 10B also has switches GSW(1,2)_1 to GSW(1,2)_4. First terminals of the switches GSW(1,2)_1 to GSW(1,2)_4 are electrically connected in a one-to-one relationship to the wirings GL[1,1]_1 to GL[1,1]_4 of the respective columns of the pixel region ARA[1,1], and second terminals of the switches GSW(1,2)_1 to GSW(1,2)_4 are electrically connected in a one-to-one relationship to the wirings GL[1,2]_1 to GL[1,2]_4 of the respective columns of the pixel region ARA[1,2]. Specifically, the first terminal of the switch GSW(1,2)_1 is electrically connected to the wiring GL[1,1]_1, and the second terminal of the switch GSW(1,2)_1 is electrically connected to the wiring GL[1,2]_1. Furthermore, a first terminal of the switch GSW(1,2)_4 is electrically connected to the wiring GL[1,1]_4, and a second terminal of the switch GSW(1,2)_4 is electrically connected to the wiring GL[1,2]_4.

[0172] Next, a case will be described in which one of the drive circuits GD included in each of the local driver circuits LD[1,1] and LD[1,2] does not operate properly in the display device 10B of Fig. 9. Fig. 10 is a timing chart showing an example of the operation of the display device 10B when one of the drive circuits SD included in each of the local driver circuits LD[1,1] and LD[1,2] does not operate properly. Note that the wiring, potentials, and data shown in the timing chart of Fig. 10 refer to the explanation of the timing chart of Fig. 7.

[0173] 10, it is assumed that each of the switches GSW(1,2)_1 to GSW(1,2)_4 is in an on state. Therefore, in the operation example of the timing chart of FIG. 10, the same potential (signal) is input to the wiring GL[1,1]_1 and the wiring GL[1,2]_1. Similarly, the same potential (signal) is input to the wiring GL[1,1]_2 and the wiring GL[1,2]_2, the same potential (signal) is input to the wiring GL[1,1]_3 and the wiring GL[1,2]_3, and the same potential (signal) is input to the wiring GL[1,1]_4 and the wiring GL[1,2]_4.

[0174] Before time T1, a low-level potential is input to the wirings GL[1,1]_1 to GL[1,1]_4 (wirings GL[1,2]_1 to GL[1,2]_4) from the driving circuit GD of either the local driver circuit LD[1,1] or the local driver circuit LD[1,2]. Note that in FIG. 10, the low-level potential is indicated as "Low." Therefore, the write transistors of the pixel circuits PX electrically connected to the wirings GL[1,1]_1 to GL[1,1]_4 and the wirings GL[1,2]_1 to GL[1,2]_4 are turned off. In other words, no image data is written to the pixel circuits PX included in the pixel areas ARA[1,1] and ARA[1,2].

[0175] Between time T1 and time T8, a high-level potential is input to the wiring GL[1,1]_1 (wiring GL[1,2]_1) from the driving circuit GD of either the local driver circuit LD[1,1] or the local driver circuit LD[1,2]. Note that in FIG. 10, the high-level potential is indicated as High. Therefore, between time T1 and time T8, it becomes possible to write image data to the pixel circuits PX[1,1] to PX[1,4] and the pixel circuits PX[1,5] to PX[1,8] electrically connected to the wiring GL[1,1]_1 and the wiring GL[1,2]_1.

[0176] Between time T2 and time T5, data D[1,1], data D[1,2], data D[1,3], and data D[1,4] are sequentially input as image data from the drive circuit SD of the local driver circuit LD[1,1] to the wirings SL[1,1]_1 to SL[1,1]_4, respectively. As a result, data D[1,1] is written to the pixel circuit PX[1,1], data D[1,2] is written to the pixel circuit PX[1,2], data D[1,3] is written to the pixel circuit PX[1,3], and data D[1,4] is written to the pixel circuit PX[1,4].

[0177] Between time T4 and time T7, data D[1,5], data D[1,6], data D[1,7], and data D[1,8] are sequentially input as image data from the drive circuit SD of the local driver circuit LD[1,1] to the wirings SL[1,2]_1 to SL[1,2]_4, respectively. As a result, data D[1,5] is written to the pixel circuit PX[1,5], data D[1,6] is written to the pixel circuit PX[1,6], data D[1,7] is written to the pixel circuit PX[1,7], and data D[1,8] is written to the pixel circuit PX[1,8].

[0178] After time T8, a low-level potential is input to the wiring GL[1,1]_1 (wiring GL[1,2]_1) from the drive circuit GD of either the local driver circuit LD[1,1] or the local driver circuit LD[1,2]. Therefore, after time T8, the write transistors of the pixel circuits PX[1,1] to PX[1,4] and the pixel circuits PX[1,5] to PX[1,8] electrically connected to the wiring GL[1,1]_1 and the wiring GL[1,2]_1 are turned off, so that the data D[1,1] to D[1,4] and the data D[1,5] to D[1,8] written before time T8 are held in the pixel circuits PX[1,1] to PX[1,4] and the pixel circuits PX[1,5] to PX[1,8], respectively.

[0179] Between time T9 and time T16, a high-level potential is input to the wiring GL[1,1]_2 (wiring GL[1,2]_2) from the driving circuit GD of either the local driver circuit LD[1,1] or the local driver circuit LD[1,2]. Therefore, between time T9 and time T16, it becomes possible to write image data to the pixel circuits PX[2,1] to PX[2,4] and the pixel circuits PX[2,5] to PX[2,8] electrically connected to the wiring GL[1,1]_2 and the wiring GL[1,2]_2.

[0180] Between time T10 and time T13, data D[2,1], data D[2,2], data D[2,3], and data D[2,4] are sequentially input as image data from the drive circuit SD of the local driver circuit LD[1,1] to the wirings SL[1,1]_1 to SL[1,1]_4, respectively. As a result, data D[2,1] is written to the pixel circuit PX[2,1], data D[2,2] is written to the pixel circuit PX[2,2], data D[2,3] is written to the pixel circuit PX[2,3], and data D[2,4] is written to the pixel circuit PX[2,4].

[0181] Between time T12 and time T15, data D[2,5], data D[2,6], data D[2,7], and data D[2,8] are sequentially input as image data from the drive circuit SD of the local driver circuit LD[1,1] to the wirings SL[1,2]_1 to SL[1,2]_4, respectively. As a result, data D[2,5] is written to the pixel circuit PX[2,5], data D[2,6] is written to the pixel circuit PX[2,6], data D[2,7] is written to the pixel circuit PX[2,7], and data D[2,8] is written to the pixel circuit PX[2,8].

[0182] After time T16, a low-level potential is input to the wiring GL[1,1]_2 (wiring GL[1,2]_2) from the drive circuit GD of either the local driver circuit LD[1,1] or the local driver circuit LD[1,2]. Therefore, after time T16, the write transistors of the pixel circuits PX[2,1] to PX[2,4] and the pixel circuits PX[2,5] to PX[2,8] electrically connected to the wirings GL[1,1]_2 and GL[1,2]_2 are turned off, so that the data D[2,1] to D[2,4] and the data D[2,5] to D[2,8] written before time T16 are held in the pixel circuits PX[2,1] to PX[2,4] and the pixel circuits PX[2,5] to PX[2,8], respectively.

[0183] Furthermore, from time T16 onwards, similar to the operation from time T1 to time T8 or the operation from time T9 to time T16, by sending a selection signal (by inputting a high-level potential) to either the wiring GL[1,1]_3 (wiring GL[1,2]_3) or the wiring GL[1,1]_4 (wiring GL[1,2]_4), image data can also be written to the pixel circuits PX[3,1] to PX[4,4] included in the pixel area ARA[1,1] and the pixel circuits PX[3,5] to PX[4,8] included in the pixel area ARA[1,2].

[0184] Furthermore, in the display device 10B, even if one of the drive circuits GD included in each of the local driver circuits LD[1,1] and LD[1,2] does not operate properly, image data can be written to each of the multiple pixel circuits PX included in the display device 10B by performing the operation example of the timing chart of Figure 10.

[0185] 1A to the display device, it is possible to provide redundancy to the drive circuits included in the display device. Furthermore, by applying the above configuration, even if one of the two drive circuits does not operate due to, for example, a malfunction, the display device can be operated properly by using the other of the two drive circuits, thereby increasing the yield of the display device.

[0186] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0187] (Embodiment 2) In this embodiment, a structural example of a display device according to one embodiment of the present invention and an example of a manufacturing method of the display device will be described.

[0188] In the first embodiment, a display device in which redundancy is provided in the drive circuits SD (drive circuits GD) included in the local driver circuits LD was described. However, in the present embodiment, a method for manufacturing a display device will be described in which, when it is determined during the manufacturing process of the display device that some of the drive circuits SD (drive circuits GD) included in all of the local driver circuits LD are not operating properly, image data or a selection signal can be transmitted by another local driver circuit LD to a pixel circuit PX included in a pixel area ARA that overlaps with the local driver circuit LD that includes the drive circuit SD (drive circuit GD) that is not operating properly.

[0189] Note that the manufacturing method of the display device described in this embodiment is described as a manufacturing method of the pixel layer PXAL shown in Figure 2A, as an example. Furthermore, since the substrates BS1 and BS2 are bonded to each other in Figure 2A, the manufacturing method of the display device can be rephrased as a method of forming circuits and wirings on the substrate BS2. Therefore, in this specification and the like, the manufacturing method of the display device described in this embodiment can be rephrased as a manufacturing method of a semiconductor device.

[0190] Fig. 11A is a plan view showing, as an example, the wiring SL and the conductors formed around the wiring SL in the display device 10 of Fig. 2. Fig. 11B is a cross-sectional view of the display device 10 taken along the dashed dotted line X1-X2 shown in Fig. 11A. Note that Figs. 11A and 11B show only the pixel regions ARA[a,b] and ARA[a+1,b].

[0191] 11A, the wiring SL[a,b] and the wiring SL[a+1,b] each have, as an example, a conductor ERA, a conductor CNT1A, and a conductor CNT1B. The wiring SL[a,b] also has a low-resistance region LRA[a,b], and the wiring SL[a+1,b] also has a low-resistance region LRA[a+1,b]. Also, in FIGS. 11A and 11B, the pixel region ARA[a,b] and the pixel region ARA[a+1,b] each have conductors CNT2[1] to CNT2[p] and conductors ER[1] to ER[p].

[0192] In the pixel regions ARA[a,b] and ARA[a+1,b], the low-resistance regions LRA[a,b] and LRA[a+1,b] are formed in a part of the substrate BS2, for example. Therefore, the substrate BS2 is preferably a semiconductor substrate made of silicon or germanium.

[0193] Also, as an example, a semiconductor region SHA is formed on a part of the substrate BS2. Specifically, the semiconductor region SHA is formed on the substrate BS2 between the low-resistance region LRA[a,b] included in the pixel region ARA[a,b] and the low-resistance region LRA[a+1,b] included in the pixel region ARA[a+1,b].

[0194] Furthermore, as an example, an isolation layer DDL is formed on a part of the substrate BS2. The isolation layer DDL is provided, for example, to isolate a plurality of wirings formed on the substrate BS2 from each other.

[0195] An insulator MSK is formed on the semiconductor region SHA. For example, the insulator MSK functions as a mask for forming the low-resistance region LRA[a, b], the low-resistance region LRA[a+1, b], and the semiconductor region SHA on the substrate BS2.

[0196] As an example, insulators INS1, INS2, INS3, and INS4 are formed in sequence above the separation layer DDL, the low resistance region LRA[a, b], the low resistance region LRA[a+1, b], and the insulator MSK.

[0197] In addition, the insulators INS1 and INS2 have a plurality of openings formed in their respective regions overlapping the low-resistance regions LRA[a,b] and LRA[a+1,b], respectively. In addition, the insulators INS1 and INS2 have a plurality of openings formed in their respective regions overlapping the isolation layer DDL, respectively.

[0198] In each of the pixel regions ARA[a,b] and ARA[a+1,b], a plurality of openings having the low resistance region LRA[a,b] and the low resistance region LRA[a+1,b] as their bottoms are filled with the conductor CNT1B and the conductors CNT2[1] to CNT2[p]. In addition, a plurality of openings in a portion of the region overlapping the separation layer DDL are filled with the conductor CNT1A.

[0199] Note that conductor CNT1B, conductor CNT2[1] to conductor CNT2[p], conductor CNT1A, etc. function as plugs or wiring. Furthermore, for conductors that function as plugs or wiring, multiple structures may be collectively assigned the same symbol. Furthermore, in this specification, etc., the wiring and the plug connecting to the wiring may be integrated. That is, there are cases where a part of the conductor functions as wiring, and cases where a part of the conductor functions as a plug. Furthermore, conductor CNT1A is sometimes called a TSV (Through Silicon Via).

[0200] Furthermore, the insulators INS3 and INS4 have a plurality of openings. The plurality of openings are formed so as to be filled with the conductor ERA and the conductors ER[1] to ER[p]. In particular, the bottom surfaces of the openings filled with the conductor ERA include regions overlapping with the conductors CNT1A and CNT1B. Furthermore, the bottom surfaces of the openings filled with the conductors ER[1] to ER[p] each include a region overlapping with the conductors CNT2[1] to CNT2[p].

[0201] In the pixel region ARA[a,b], the conductor CNT1B and the conductors CNT2[1] to CNT2[p] are each electrically connected to the low-resistance region LRA[a,b]. In the pixel region ARA[a+1,b], the conductor CNT1B and the conductors CNT2[1] to CNT2[p] are each electrically connected to the low-resistance region LRA[a+1,b]. The conductor CNT1B is electrically connected to the conductor ERA, which is electrically connected to the conductor CNT1A. The conductors CNT2[1] to CNT2[p] are each electrically connected to the conductors ER[1] to ER[p] in a one-to-one relationship.

[0202] As an example, the conductor CNT1A is electrically connected to a circuit (local driver circuit LD[a,b] or local driver circuit LD[a,b]) included in the drive circuit region DRV formed on the substrate BS1 (not shown). In particular, the conductor CNT1A included in the pixel region ARA[a,b] is electrically connected to the drive circuit SD included in the local driver circuit LD[a,b], and the conductor CNT1A included in the pixel region ARA[a+1,b] is electrically connected to the drive circuit SD included in the local driver circuit LD[a+1,b].

[0203] Furthermore, the conductors ER[1] to ER[p] function as wirings electrically connected to, for example, pixel circuits included in the pixel area ARA[a,b] or pixel area ARA[a+1,b]. Note that Fig. 11A only shows some of the conductors ER[1] to ER[p], and does not show the electrical connection configuration with the pixel circuits.

[0204] 11A and 11B, the wiring SL[a,b] provided in the pixel region ARA[a,b] and the wiring SL[a+1,b] provided in the pixel region ARA[a+1,b] are separated by the semiconductor region SHA, not by the isolation layer DDL. Furthermore, in the configuration shown in FIGS. 11A and 11B, no conductor functioning as a gate electrode is provided around the semiconductor region SHA, so no electric field is applied to the semiconductor region SHA. Therefore, in the display device 10 shown in FIGS. 11A and 11B, no channel is formed in the semiconductor region SHA, and therefore, the wiring SL[a,b] and the wiring SL[a+1,b] are not electrically connected to each other.

[0205] Incidentally, for example, if it is determined before or during the construction of the circuit on the substrate BS2 that a malfunction has occurred in either the drive circuit SD included in the local driver circuit LD[a,b] formed on the substrate BS1 or the drive circuit SD included in the local driver circuit LD[a+1,b], the circuit configuration on the substrate BS2 may be changed to the configuration shown in the plan view of FIG. 12A and the cross-sectional view of FIG. 12B, rather than that shown in FIG. 11A and FIG. 11B.

[0206] 12A and 12B show the same configuration as in FIGS. 11A and 11B, but omitting the insulator MSK. Because the insulator MSK is not provided in FIGS. 12A and 12B, the low-resistance regions LRA[a,b], LRA[a+1,b], and LRA3 are formed on the substrate BS2, excluding the isolation layer DDL. That is, the configurations of FIGS. 12A and 12B differ from those of FIGS. 11A and 11B in that the semiconductor region SHA is not provided. Therefore, unlike the configurations of FIGS. 11A and 11B, the display device 10 shown in FIGS. 12A and 12B exhibits electrical continuity between the wiring SL[a,b] and the wiring SL[a+1,b]. As a result, if a malfunction occurs in either the drive circuit SD included in the local driver circuit LD[a,b] or the drive circuit SD included in the local driver circuit LD[a+1,b] formed on the substrate BS1, image data can be transmitted to the pixel circuits included in each of the pixel areas ARA[a,b] and ARA[a+1,b] by the other drive circuit SD included in the local driver circuit LD[a,b] or the other drive circuit SD included in the local driver circuit LD[a+1,b].

[0207] Next, a method for manufacturing the display device 10 shown in FIGS. 11A and 11B or the display device 10 shown in FIGS. 12A and 12B will be described.

[0208] Fig. 13 is an example of a flowchart showing a method for manufacturing the display device 10 shown in Fig. 11A and Fig. 11B or the display device 10 shown in Fig. 12A and Fig. 12B. The method for manufacturing the display device 10 includes steps ST1 to ST10.

[0209] Step ST1 includes, for example, a step of preparing a substrate BS2 and a step of forming a separation layer DDL on the substrate BS2.

[0210] The isolation layer DDL can be formed on the substrate BS2 by using, for example, a local oxidation of silicon (LOCOS) method, a shallow trench isolation (STI) method, or a mesa isolation method.

[0211] Step ST2 includes, for example, a step of forming a well in a region of the substrate BS2 other than the separation layer DDL.

[0212] Specifically, for example, p-type impurities (for example, boron or aluminum) or n-type impurities (for example, phosphorus or arsenic) are implanted from the upper surface of the substrate BS2.

[0213] In some cases, it is not necessary to form a well in the region of the substrate BS2.

[0214] Step ST3 includes, for example, a step of forming an insulator MSK in the region of the substrate BS2 other than the separation layer DDL.

[0215] The insulator MSK can be formed by, for example, photolithography. Therefore, a photosensitive material such as a resist can be used as the insulator MSK. Alternatively, a hard mask material can be used as the insulator MSK. Alternatively, the insulator MSK can be made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon nitride.

[0216] In this specification and elsewhere, an oxynitride refers to a material whose composition contains more oxygen than nitrogen, and a nitride oxide refers to a material whose composition contains more nitrogen than oxygen. For example, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, and silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0217] As an example, step ST4 includes a step of forming low resistance regions LRA[a, b] and low resistance regions LRA[a+1, b] in regions of the substrate BS2 other than the region of the isolation layer DDL and the region in which the insulator MSK is formed.

[0218] Specifically, for example, if a p-type well is formed in the substrate BS2, n-type impurities (e.g., phosphorus or arsenic) are implanted from the upper surface of the substrate BS2, or if an n-type well is formed in the substrate BS2, p-type impurities (e.g., boron or aluminum) are implanted from the upper surface of the substrate BS2.

[0219] At this time, since the insulator MSK is formed on the upper surface of the substrate BS2, the low-resistance region LRA[a,b] and the low-resistance region LRA[a+1,b] are formed on the upper surface of the substrate BS2 except for the region where the insulator MSK is formed. Meanwhile, the semiconductor region SHA is formed in the region of the substrate BS2 where the insulator MSK is formed. As a result, the low-resistance region LRA[a,b] and the low-resistance region LRA[a+1,b] formed on the substrate BS2 have the configuration shown in Figures 11A and 11B.

[0220] In step ST4, a material capable of forming silicide may be deposited in a region of the substrate BS2 other than the region of the isolation layer DDL and the region where the insulator MSK is formed. Examples of materials capable of forming silicide include nickel, cobalt, molybdenum, tungsten, and titanium.

[0221] In step ST5, it is determined whether the drive circuits SD included in each of the local driver circuits LD[a,b] and LD[a+1,b] formed on the substrate BS1 operate properly. Specifically, step ST5, for example, includes a step of proceeding to step ST7 if the drive circuits SD included in the local driver circuits LD[a,b] and LD[a+1,b] operate properly, and a step of proceeding to step ST6 if the drive circuit SD of either the local driver circuit LD[a,b] or the local driver circuit LD[a+1,b] does not operate properly.

[0222] Step ST6 includes, for example, a step of removing the insulator MSK and then a step of forming a low-resistance region LRA3 in the semiconductor region SHA.

[0223] Specifically, the insulator MSK is removed, and then impurities are implanted from above the substrate BS2. For example, if a p-type well is formed in the substrate BS2, n-type impurities (e.g., phosphorus or arsenic) are implanted from the upper surface of the substrate BS2. Also, for example, if an n-type well is formed in the substrate BS2, p-type impurities (e.g., boron or aluminum) are implanted from the upper surface of the substrate BS2. As a result, the low-resistance regions LRA[a,b], LRA[a+1,b], and LRA3 formed in the substrate BS2 have the configurations shown in FIGS. 12A and 12B.

[0224] In step ST6, a material capable of forming silicide may be deposited in the region on the substrate BS2 where the insulator MSK was formed. The content of step ST4 may be referred to for the material capable of forming silicide.

[0225] Step ST7 includes, for example, a step of forming an insulator above the substrate BS2.

[0226] The insulators may be, for example, the insulators INS1 and INS2 in FIGS. 11B and 12B.

[0227] Although Figures 11B and 12B show a two-layer structure of insulators INS1 and INS2, the insulator formed in step ST7 may have a one-layer structure or a three-layer or more structure.

[0228] For each of the insulators INS1 and INS2, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, or aluminum nitride can be used.

[0229] In this specification, aluminum oxynitride refers to a material having a composition in which oxygen is contained in a larger amount than nitrogen, and aluminum nitride oxide refers to a material having a composition in which nitrogen is contained in a larger amount than oxygen.

[0230] Step ST8 includes, for example, a step of providing an opening in the insulator formed in step ST7, and a step of forming a conductor in the opening.

[0231] The conductors correspond to, for example, conductor CNT1A, conductor CNT1B, and conductor CNT2[1] to conductor CNT2[p] in FIGS. 11A, 11B, 12A, and 12B.

[0232] Conductor CNT1B, Conductor CNT2[1] to Conductor CNT2[p], and Conductor CNT1A can be formed of a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material, either in a single layer or in a laminated form. Specifically, Conductor CNT1B, Conductor CNT2[1] to Conductor CNT2[p], and Conductor CNT1A are preferably formed of a high-melting-point material such as tungsten or molybdenum, which has both heat resistance and conductivity. Tungsten is particularly preferred. Alternatively, Conductor CNT1B, Conductor CNT2[1] to Conductor CNT2[p], and Conductor CNT1A are preferably formed of a low-resistance conductive material such as aluminum or copper. The use of a low-resistance conductive material can reduce wiring resistance.

[0233] Preferably, an insulator is provided on the side surface of the opening where the conductor CNT1A is formed to insulate the substrate BS2 from the conductor CNT1A. Therefore, step ST8 may include a step of forming an insulator on the side surface of the opening. Furthermore, the insulator may be, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, or aluminum nitride.

[0234] Step ST9 includes, for example, a step of forming a new insulator above the insulator formed in step ST7 and the conductor formed in step ST8.

[0235] The insulators formed in step ST9 may be, for example, the insulators INS3 and INS4 in FIGS. 11B and 12B.

[0236] Although Figures 11B and 12B show a two-layer structure of insulators INS1 and INS2, the insulator formed in step ST9 may have a one-layer structure or a three-layer or more structure.

[0237] The insulator INS3 is preferably a barrier insulating film that prevents impurities such as water and hydrogen from diffusing from the substrate 310 or the transistor 300 to a region above the insulator INS3 (e.g., a region where a transistor included in a pixel circuit or a light-emitting device is provided). Therefore, the insulator INS3 is preferably made of an insulating material that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, and water molecules (i.e., the impurities are less likely to permeate through the insulating material). Depending on the situation, the insulator INS3 is preferably made of an insulating material that has a function of suppressing the diffusion of impurities such as nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (e.g., NO, NO, and NO), or copper atoms (i.e., the oxygen is less likely to permeate through the insulating material). Alternatively, the insulator INS3 is preferably made of an insulating material that has a function of suppressing the diffusion of oxygen (e.g., oxygen atoms and / or oxygen molecules). Specifically, for example, silicon nitride can be used as the insulator INS3.

[0238] As the insulator INS4, for example, a material applicable to the insulator INS1 or the insulator INS2 can be used.

[0239] Step ST10 includes, for example, a step of providing an opening in the insulator formed in step ST9, and a step of forming a conductor in the opening.

[0240] The conductors correspond to, for example, the conductor ERA and the conductors ER[1] to ER[p] in FIGS. 11A, 11B, 12A, and 12B.

[0241] Furthermore, for conductor ERA and conductors ER[1] to ER[p], for example, materials applicable to conductor CNT1B, conductor CNT2[1] to conductor CNT2[p], and conductor CNT1A can be used. Conductor ERA and conductors ER[1] to ER[p] can have a single-layer structure or a multilayer structure having one or more materials selected from conductive materials such as metal materials, alloy materials, metal nitride materials, and metal oxide materials.

[0242] The display device 10 shown in FIGS. 11A and 11B or the display device 10 shown in FIGS. 12A and 12B can be manufactured by the manufacturing method according to the above flowchart.

[0243] Note that the operation method of the display device of one embodiment of the present invention is not limited to the operation example of the flowchart shown in Fig. 13. The operation method of the display device of one embodiment of the present invention may be modified as appropriate within the scope of solving the problem.

[0244] For example, the flowchart of Fig. 13 may be changed to the flowchart shown in Fig. 14. The operation example of the flowchart of Fig. 14 differs from the flowchart of Fig. 13 in that the operation of step ST5 is performed after step ST2 and step ST6 is not included.

[0245] In the operation example of the flowchart of Fig. 14, step ST5 is performed after step ST2. That is, after a well is formed in a region on substrate BS2, it is determined whether the drive circuits SD included in each of local driver circuits LD[a,b] and local driver circuits LD[a+1,b] formed on substrate BS1 operate properly. In addition, in the operation example of the flowchart of Fig. 14, step ST5, for example, includes a step of transitioning to step ST3 if the drive circuits SD included in local driver circuits LD[a,b] and local driver circuit LD[a+1,b] operate properly, and a step of transitioning to step ST4B if the drive circuit SD of either local driver circuit LD[a,b] or local driver circuit LD[a+1,b] does not operate properly.

[0246] In the example of operation of the flowchart of FIG. 14, when the drive circuits SD included in the local driver circuits LD[a,b] and LD[a+1,b] operate properly, step ST3 is performed followed by step ST4A, and step ST7 is performed after step ST4A. Specifically, after a well is formed in a region on the substrate BS2, an insulator MSK is formed in a region of the substrate BS2 other than the isolation layer DDL, and then step ST4A is performed. Similar to step 4 of the flowchart of FIG. 13, step ST4A includes forming low-resistance regions LRA[a,b] and LRA[a+1,b] in a region of the substrate BS2 other than the region of the isolation layer DDL and the region where the insulator MSK is formed. Furthermore, in step ST4A, silicide may be formed in the corresponding region on the substrate BS2. Furthermore, after step ST4A, step ST7 forms an insulator (insulator INS1 and insulator INS2 in FIGS. 11B and 12B) above the substrate BS2.

[0247] In the example operation of the flowchart of FIG. 14, step ST4B is performed when the local driver circuit LD[a,b] and the driver circuit SD included in the local driver circuit LD[a+1,b] do not operate properly, and step ST7 is performed after step ST4B. Step ST4B includes forming low-resistance regions LRA[a,b], LRA[a+1,b], and LRA3 in regions of the substrate BS2 other than the region of the isolation layer DDL. Since step ST3 of FIG. 14 is not performed at this time, a semiconductor region SHA is not formed between the low-resistance regions LRA[a,b] and LRA[a+1,b]. Furthermore, in step ST4B, silicide may be formed in the corresponding region on the substrate BS2. Furthermore, after step ST4B, step ST7 forms an insulator (insulator INS1 and insulator INS2 in FIGS. 11B and 12B) above the substrate BS2.

[0248] For steps ST8 to ST10 in the flowchart of FIG. 14, refer to the description of steps ST8 to ST10 in the flowchart of FIG.

[0249] The display device 10 shown in FIGS. 11A and 11B or the display device 10 shown in FIGS. 12A and 12B can be manufactured by the manufacturing method according to the flowchart in FIG.

[0250] Furthermore, the display device manufactured according to the above flowchart is not limited to the display device 10 shown in FIGS. 11A and 11B or the display device 10 shown in FIGS. 12A and 12B.

[0251] For example, a display device manufactured according to the above flowchart may have the configuration of the display device 10 shown in Figures 15A and 15B. The display device 10 in Figures 15A and 15B has a configuration that is manufactured when step ST5 in Figure 13 is followed by step ST7. The display device 10 in Figures 15A and 15B shows, as an example, pixel regions ARA[a-1,b] (where a is an integer between 2 and m-2), pixel regions ARA[a,b], pixel regions ARA[a+1,b], and pixel regions ARA[a+2,b]. Each pixel region ARA includes wiring SL[a-1,b], wiring SL[a,b], wiring SL[a+1,b], and wiring SL[a+2,b]. Also, since the process has progressed from step ST5 to step ST7, semiconductor regions SHA are provided between the wiring SL[a-1,b] and the wiring SL[a,b], between the wiring SL[a,b] and the wiring SL[a+1,b], and between the wiring SL[a+1,b] and the wiring SL[a+2,b].

[0252] 15A and 15B, as an example, the conductor CNT1A is provided at a position that is not on the dashed-dotted line X1-X2. Also, as shown in FIG. 15A, the conductor CNT1A is electrically connected to the conductor CNT1B via the conductor ERA.

[0253] In the display device 10 of Figures 15A and 15B, if a drive circuit SD included in a local driver circuit LD overlapping any one of pixel areas ARA[a-1,b] (where a is an integer between 2 and m-2), pixel area ARA[a,b], pixel area ARA[a+1,b], and pixel area ARA[a+2,b] does not operate properly, at least one of the multiple semiconductor areas SHA shown in Figures 15A and 15B is selected, and the selected semiconductor area SHA is changed to a low-resistance area LRA3 in step ST5 of the flowchart of Figure 13, thereby making it possible to transmit image data from the drive circuit SD of another local driver circuit LD to a pixel circuit included in a pixel area ARA overlapping the local driver circuit LD including the drive circuit SD that is not operating properly.

[0254] Note that the display device 10 shown in Figures 15A and 15B shows an example configuration including four pixel areas ARA arranged in succession and a semiconductor area SHA provided between each adjacent pixel area ARA, but the number of pixel areas ARA arranged in succession may be three, or may be five or more.

[0255] Furthermore, for example, a display device fabricated according to the above flowchart may have the configuration of the display device 10 shown in Figures 16A and 16B. The display device 10 of Figures 16A and 16B has a configuration fabricated, for example, by proceeding from step ST5 of Figure 13 to step ST7, in which a portion of the wiring SL[a,b] functions as either the source or the drain of each of the write transistors WTr of the plurality of pixel circuits included in the pixel region ARA[a,b], and a portion of the wiring SL[a+1,b] functions as either the source or the drain of each of the write transistors WTr of the plurality of pixel circuits included in the pixel region ARA[a+1,b]. In this case, for example, a low-resistance region LRB, a semiconductor region SHB, and a conductor GE are formed above the substrate BS2.

[0256] 16A, the low-resistance region LRB formed on the substrate BS2 functions as the other of the source and drain of the write transistor WTr included in each of the pixel regions ARA[a,b] and ARA[a+1,b]. The semiconductor region SHB formed on the substrate BS2 functions as the channel formation region of the write transistor WTr included in each of the pixel regions ARA[a,b] and ARA[a+1,b]. The conductor GE overlapping the semiconductor region SHB functions as the gate of the write transistor WTr.

[0257] 16A and 16B, a part of the low-resistance region LRA[a,b] (low-resistance region LRA[a+1,b]) included in the wiring SL[a,b] (wiring SL[a+1,b]) functions as one of the source and drain of the write transistor WTr of the pixel circuit, so that the area of ​​the pixel circuit can be made smaller than that of the pixel circuit of the display device 10 of Figures 11A, 11B, 12A, and 12B. Therefore, the resolution of the display device 10 of Figures 16A and 16B can be made higher than that of the display device 10 of Figures 11A, 11B, 12A, and 12B.

[0258] In this specification and the like, the manufacturing method shown in the flowchart is classified into each process and shown as independent steps. However, in actual processing, it is difficult to separate the manufacturing method shown in the flowchart into each process, and there may be cases where one step involves multiple steps, or where one step involves multiple steps. Therefore, the manufacturing method shown in the flowchart is not limited to each step described in the specification, and the order of steps may be changed, steps may be added, or steps may be deleted depending on the situation.

[0259] Note that one embodiment of the present invention may have a structure in which any of the structural examples of the display device described in this embodiment is combined as appropriate.

[0260] In the present embodiment, a method for manufacturing a display device has been described in which, when it is determined during the manufacturing process of the display device that some of the drive circuits SD included in all of the local driver circuits LD are not operating properly, image data can be transmitted by another local driver circuit LD to the pixel circuits PX included in the pixel area ARA that overlaps the local driver circuit LD that includes the drive circuit SD that is not operating properly. However, by taking into consideration the above-described manufacturing method of the display device, it is possible to similarly transmit a selection signal by another local driver circuit LD to the pixel circuits PX included in the pixel area ARA that overlaps the local driver circuit LD that includes the drive circuit GD that is not operating properly, not only for the drive circuits SD but also for the drive circuits GD. In that case, for example, in the above manufacturing method, the drive circuits SD can be replaced with drive circuits GD, the wiring SL can be replaced with wiring GL, and the image data can be replaced with a selection signal.

[0261] Although the substrate BS2 has been described as a semiconductor substrate in this embodiment, the manufacturing method of the display device of one embodiment of the present invention is not limited to the above. For example, a display device can be manufactured in a similar manner to the above-described method using a structure that does not use the substrate BS2, i.e., the structure of the display device shown in FIG. 2B . In this case, for example, the low-resistance region LRA[a,b] of the wiring SL[a,b], the low-resistance region LRA[a+1,b] of the wiring SL[a+1], and the semiconductor region SHA shown in FIGS. 11A and 11B may contain a metal oxide. Examples of the metal oxide include In-M-Zn oxide containing indium, element M, and zinc (element M is one or more elements selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like). In addition to the above, the metal oxide may be an In—Ga oxide, an In—Zn oxide, or an indium oxide. In particular, the metal oxide provided in the low-resistance region LRA[a,b] and the low-resistance region LRA[a+1,b] preferably has a high carrier concentration (n-type) as in the region 530ba and the region 530bb described in the third embodiment, and the metal oxide provided in the semiconductor region SHA preferably has a low carrier concentration (i-type or substantially i-type).

[0262] The metal oxide can be formed by, for example, a sputtering method, and therefore, a configuration similar to that of the display device 10 can be fabricated without using the substrate BS2 that uses a semiconductor substrate. Therefore, by applying a metal oxide with a high carrier concentration to a portion of each of the wirings SL[a, b] and SL[a+1, b] and applying a metal oxide with a low carrier concentration between the wirings SL[a, b] and SL[a+1, b], a display device having redundancy in the drive circuit, similar to the display device 10, can be fabricated even with the configuration shown in FIG. 2B.

[0263] Although this embodiment has been described with reference to a structure in which the wiring SL[a,b] includes the low-resistance region LRA[a,b] and the wiring SL[a+1,b] includes the low-resistance region LRA[a+1,b], the manufacturing method of the display device of one embodiment of the present invention is not limited to the above. In the manufacturing method of the display device of one embodiment of the present invention, for example, the semiconductors included in the low-resistance regions LRA[a,b] and LRA[a+1,b] may be changed to conductors. In this case, for example, a conductor may be formed on an insulator instead of on the substrate BS2 as a single wiring to serve as the wiring SL[a,b] and the wiring SL[a+1,b]. Furthermore, if both of the two driver circuits operate properly, the wiring may be separated into the wiring SL[a,b] and the wiring SL[a+1,b] using, for example, a laser processing machine. Furthermore, the wiring SL[a,b] and the wiring SL[a+1,b] may be separated by photolithography instead of using a laser processing machine. The above manufacturing method also makes it possible to manufacture a display device having redundancy in the driver circuit.

[0264] By manufacturing a display device using the above-described manufacturing method, it is possible to provide redundancy to the driver circuits included in the display device. Furthermore, even if one of the two driver circuits does not operate due to a malfunction or the like, the display device can be operated properly by using the other of the two driver circuits, thereby increasing the yield of the display device.

[0265] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0266] (Embodiment 3) In this embodiment, a structural example of a display device according to one embodiment of the present invention will be described.

[0267] <Example of display device configuration> 17 is a cross-sectional view illustrating an example of a display device according to one embodiment of the present invention. The display device 100 illustrated in FIG. 17 has a structure in which a pixel circuit and a driver circuit are provided over a substrate 310, for example.

[0268] Specifically, the display device 100 includes, for example, a circuit layer SICL, a wiring layer LINL, and a pixel layer PXAL. The circuit layer SICL includes, for example, a substrate 310, and a transistor 300 is formed on the substrate 310. A wiring layer LINL is provided above the transistor 300, and wiring is provided in the wiring layer LINL to electrically connect the transistor 300, a transistor 200 (described later), and light-emitting devices 150a and 150b (described later). A pixel layer PXAL is provided above the wiring layer LINL, and the pixel layer PXAL includes, for example, the transistor 200 and the light-emitting device 150 (the light-emitting device 150a and the light-emitting device 150b in FIG. 17).

[0269] The substrate 310 can be, for example, a single-crystal substrate (e.g., a semiconductor substrate made of silicon or germanium). In addition to a single-crystal substrate, the substrate 310 can also be, for example, an SOI (Silicon-On-Insulator) substrate, a glass substrate, a quartz substrate, a plastic substrate, a sapphire glass substrate, a metal substrate, a stainless steel substrate, a substrate with stainless steel foil, a tungsten substrate, a substrate with tungsten foil, a flexible substrate, a laminated film, paper containing a fibrous material, or a base film. Examples of glass substrates include barium borosilicate glass, aluminoborosilicate glass, and soda-lime glass. Examples of flexible substrates, laminated films, and base films include the following: Plastics such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), and polytetrafluoroethylene (PTFE) are examples; and synthetic resins such as acrylic resins are also examples. Other examples include polypropylene, polyester, polyvinyl fluoride, and polyvinyl chloride. Other examples include polyamide, polyimide, aramid, epoxy resin, inorganic vapor deposition film, and paper. If the manufacturing process of the display device 100 includes a heat treatment, it is preferable to select a material with high heat resistance for the substrate 310.

[0270] In this embodiment, the substrate 310 will be described as a semiconductor substrate made of silicon.

[0271] The transistor 300 is provided over a substrate 310 and includes an element isolation layer 312, a conductor 316, an insulator 315, an insulator 317, a semiconductor region 313 formed of part of the substrate 310, and low-resistance regions 314a and 314b each functioning as a source region or a drain region. Therefore, the transistor 300 is a transistor (a Si transistor) whose channel formation region contains silicon. Note that although FIG. 17 illustrates a configuration in which one of the source and drain of the transistor 300 is electrically connected to the conductor 330, the conductor 356, and the conductor 366 (described later) through the conductor 328 (described later), the electrical connection configuration of the semiconductor device of one embodiment of the present invention is not limited thereto. For example, the semiconductor device of one embodiment of the present invention may have a configuration in which the gate of the transistor 300 is electrically connected to the conductor 330, the conductor 356, and the conductor 366 through the conductor 328.

[0272] The transistor 300 can be made into a fin type by, for example, configuring the top surface and the side surfaces in the channel width direction of the semiconductor region 313 to be covered with a conductor 316 via an insulator 315 that functions as a gate insulating film. By configuring the transistor 300 as a fin type, the effective channel width can be increased, and the on-state characteristics of the transistor 300 can be improved. Furthermore, the contribution of the electric field of the gate electrode can be increased, and the off-state characteristics of the transistor 300 can be improved.

[0273] Note that the transistor 300 may be either a p-channel type or an n-channel type. Alternatively, a plurality of transistors 300 may be provided, and both p-channel and n-channel types may be used.

[0274] The region in the semiconductor region 313 where the channel is formed, the region nearby, and the low-resistance region 314a and low-resistance region 314b that will become the source or drain region preferably contain a silicon-based semiconductor, specifically, single-crystal silicon. Alternatively, each of the above-mentioned regions may be formed of a material containing, for example, germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), aluminum gallium arsenide (GaAlAs), or gallium nitride (GaN). A configuration using silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may also be used. Alternatively, the transistor 300 may be a high electron mobility transistor (HEMT) using gallium arsenide and aluminum gallium arsenide.

[0275] The conductor 316, which functions as the gate electrode, can be a semiconductor material such as silicon containing an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron or aluminum, or can be a conductive material such as a metal material, an alloy material, or a metal oxide material.

[0276] Note that the work function is determined by the material of the conductor, and therefore the threshold voltage of the transistor can be adjusted by selecting the material of the conductor. Specifically, it is preferable to use one or both of titanium nitride and tantalum nitride as the conductor. Furthermore, in order to achieve both conductivity and embeddability, it is preferable to use one or both of tungsten and aluminum as the conductor in a stacked structure, and tungsten is particularly preferable in terms of heat resistance.

[0277] The element isolation layer 312 is provided to isolate a plurality of transistors formed on the substrate 310. The element isolation layer can be formed using, for example, a local oxidation of silicon (LOCOS) method, a shallow trench isolation (STI) method, or a mesa isolation method.

[0278] 17 is just an example, and the transistor 300 is not limited to this structure, and an appropriate transistor may be used depending on the circuit configuration and driving method. For example, the transistor 300 may have a planar structure instead of a fin structure.

[0279] In the transistor 300 shown in FIG. 17, an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are stacked in this order from the substrate 310 side.

[0280] The insulators 320, 322, 324, and 326 can be formed using, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, or aluminum nitride.

[0281] The insulator 322 may function as a planarizing film that flattens steps caused by the insulator 320 and the transistor 300 covered by the insulator 322. For example, the top surface of the insulator 322 may be planarized by planarization treatment using a chemical mechanical polishing (CMP) method to improve flatness.

[0282] The insulator 324 is preferably a barrier insulating film that prevents impurities such as water and hydrogen from diffusing from the substrate 310 or the transistor 300 to regions above the insulator 324 (e.g., regions where the transistor 200, the light-emitting device 150a, the light-emitting device 150b, etc. are provided). Therefore, the insulator 324 is preferably made of an insulating material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, and water molecules (i.e., through which the impurities are less likely to permeate). Depending on the circumstances, the insulator 324 is preferably made of an insulating material that has the function of suppressing the diffusion of impurities such as nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (e.g., NO, NO, and NO), and copper atoms (i.e., through which the oxygen is less likely to permeate). Alternatively, the insulator 324 preferably has the function of suppressing the diffusion of oxygen (e.g., oxygen atoms and / or oxygen molecules).

[0283] An example of a film having barrier properties against hydrogen is silicon nitride formed by a CVD (Chemical Vapor Deposition) method.

[0284] The amount of desorbed hydrogen can be analyzed using, for example, thermal desorption spectrometry (TDS). For example, the amount of desorbed hydrogen from the insulator 324 is calculated by TDS as follows: when the surface temperature of the film is in the range of 50° C. to 500° C., the amount of desorbed hydrogen converted into hydrogen atoms is 10×10 per area of ​​the insulator 324. 15 atoms / cm 2 Less than or equal to 5 x 10 15 atoms / cm 2 The following is fine.

[0285] It is preferable that the insulator 326 has a lower dielectric constant than the insulator 324. For example, the relative dielectric constant of the insulator 326 is preferably less than 4, and more preferably less than 3. Furthermore, for example, the relative dielectric constant of the insulator 326 is preferably 0.7 times or less, and more preferably 0.6 times or less, the relative dielectric constant of the insulator 324. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance that occurs between wirings can be reduced.

[0286] Furthermore, conductors 328 and 330 are embedded in the insulators 320, 322, 324, and 326, respectively, to connect to a light-emitting device or the like disposed above the insulator 326. The conductors 328 and 330 function as plugs or wiring. Furthermore, for conductors functioning as plugs or wiring, the same reference numeral may be used to refer to multiple structures. Furthermore, in this specification and the like, the wiring and the plug connecting to the wiring may be integrated. That is, there are cases where a portion of the conductor functions as wiring, and cases where a portion of the conductor functions as a plug.

[0287] The materials for each plug and wiring (e.g., conductor 328 and conductor 330) can be a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material, and can be used in a single layer or a stacked layer. High-melting-point materials such as tungsten or molybdenum, which have both heat resistance and conductivity, are preferably used, and tungsten is preferred. Alternatively, they are preferably formed from low-resistance conductive materials such as aluminum and copper. The use of low-resistance conductive materials can reduce the wiring resistance.

[0288] A wiring layer may be provided over the insulator 326 and the conductor 330. For example, in FIG. 17 , an insulator 350, an insulator 352, and an insulator 354 are stacked in this order over the insulator 326 and the conductor 330. A conductor 356 is formed in the insulator 350, the insulator 352, and the insulator 354. The conductor 356 functions as a plug or wiring connected to the transistor 300. Note that the conductor 356 can be formed using a material similar to that of the conductor 328 and the conductor 330.

[0289] Note that, for example, the insulator 350 is preferably an insulator that has barrier properties against hydrogen, oxygen, and water, similar to the insulator 324. Similarly to the insulator 326, the insulators 352 and 354 are preferably insulators with a relatively low dielectric constant in order to reduce parasitic capacitance between wirings. The insulators 362 and 364 function as an interlayer insulating film and a planarizing film. The conductor 356 preferably includes a conductor that has barrier properties against hydrogen, oxygen, and water.

[0290] Note that, for example, tantalum nitride is preferably used as the conductor having a barrier property against hydrogen. Furthermore, by stacking tantalum nitride and highly conductive tungsten, the diffusion of hydrogen from the transistor 300 can be suppressed while maintaining the conductivity of the wiring. In this case, a structure in which the tantalum nitride layer having a barrier property against hydrogen is in contact with the insulator 350 having a barrier property against hydrogen is preferable.

[0291] In addition, an insulator 360, an insulator 362, and an insulator 364 are stacked in this order on the insulator 354 and the conductor 356.

[0292] The insulator 360 is preferably an insulator having barrier properties against impurities such as water and hydrogen, similar to the insulator 324. Therefore, the insulator 360 can be made of, for example, a material that can be used for the insulator 324.

[0293] The insulators 362 and 364 function as an interlayer insulating film and a planarizing film. As the insulators 362 and 364, it is preferable to use an insulator that has a barrier property against impurities such as water and hydrogen, similar to the insulator 324. Therefore, the insulator 362 and / or the insulator 364 can be made of a material that can be used for the insulator 324.

[0294] Openings are formed in the insulators 360, 362, and 364 in regions that overlap with part of the conductor 356, and the conductor 366 is provided to fill the openings. The conductor 366 is also formed over the insulator 362. For example, the conductor 366 functions as a plug or a wiring connected to the transistor 300. Note that the conductor 366 can be formed using a material similar to that of the conductors 328 and 330.

[0295] An insulator 370 and an insulator 372 are stacked in this order on the insulator 364 and the conductor 366 .

[0296] The insulator 370 is preferably an insulator having barrier properties against impurities such as water and hydrogen, similar to the insulator 324. Therefore, the insulator 370 can be made of, for example, a material that can be used for the insulator 324.

[0297] The insulator 372 functions as an interlayer insulating film and a planarizing film. Similarly to the insulator 324, the insulator 372 preferably has a barrier property against impurities such as water and hydrogen. Therefore, the insulator 372 can be made of a material that can be used for the insulator 324.

[0298] Furthermore, openings are formed in the insulators 370 and 372 in regions that overlap with a portion of the conductor 366, and the conductor 376 is provided to fill the openings. The conductor 376 is also formed on the insulator 372. Thereafter, the conductor 376 is patterned into a shape such as a wiring, a terminal, or a pad by etching or the like.

[0299] For example, copper, aluminum, tin, zinc, tungsten, silver, platinum, or gold can be used for the conductor 376. Note that the conductor 376 is preferably made of the same material as the conductor 216 included in the pixel layer PXAL, which will be described later.

[0300] Next, an insulator 380 is formed to cover the insulator 372 and the conductor 376, and then planarization is performed using, for example, a chemical mechanical polishing (CMP) method until the conductor 376 is exposed. This allows the conductor 376 to be formed on the substrate 310 as a wiring, terminal, or pad.

[0301] As the insulator 380, it is preferable to use, for example, a film having barrier properties that prevent the diffusion of impurities such as water and hydrogen, similar to the insulator 324. That is, it is preferable to use, for the insulator 380, a material that can be used for the insulator 324. Alternatively, as the insulator 380, it is possible to use, for example, an insulator with a relatively low dielectric constant in order to reduce parasitic capacitance that occurs between wirings, similar to the insulator 326. That is, it is possible to use, for the insulator 380, a material that can be used for the insulator 326.

[0302] The pixel layer PXAL includes, for example, a substrate 210, a transistor 200, a light-emitting device 150 (light-emitting device 150a and light-emitting device 150b in FIG. 17), and a substrate 102. The pixel layer PXAL also includes, for example, an insulator 220, an insulator 222, an insulator 226, an insulator 250, an insulator 252, an insulator 111, an insulator 112, an insulator 113, and a resin layer 161. The pixel layer PXAL also includes, for example, a conductor 216, a conductor 228, a conductor 230, a conductor 256, a conductor 121 (conductor 121a and conductor 121b in FIG. 17), and a conductor 122.

[0303] 17, for example, the insulator 202 functions as a bonding layer together with the insulator 380. The insulator 202 is preferably made of the same material as the material used for the insulator 380, for example.

[0304] The substrate 210 is provided above the insulator 202. In other words, the insulator 202 is formed on the lower surface of the substrate 210. As the substrate 210, it is preferable to use, for example, a substrate that can be used as the substrate 310. Note that in the display device 100 of FIG. 17, the substrate 310 will be described as a semiconductor substrate made of silicon.

[0305] For example, a transistor 200 is formed on the substrate 210. The transistor 200 functions as a Si transistor because it is formed on the substrate 210, which is a semiconductor substrate made of silicon. Note that the description of the transistor 300 is to be referred to for the configuration of the transistor 200.

[0306] An insulator 220 and an insulator 222 are provided above the transistor 200. The insulator 220 functions as an interlayer insulating film and a planarizing film, similar to the insulator 320. The insulator 222 functions as an interlayer insulating film and a planarizing film, similar to the insulator 322.

[0307] A plurality of openings are provided in the insulator 220 and the insulator 222. The plurality of openings are formed in regions overlapping with the source and drain of the transistor 200 and a region overlapping with the conductor 376. Of the plurality of openings, a conductor 228 is formed in the opening formed in the region overlapping with the source and drain of the transistor 200. Of the remaining openings, an insulator 214 is formed on the side surfaces of the opening formed in the region overlapping with the conductor 376, and a conductor 216 is formed in the remaining openings. In particular, the conductor 216 may be called a TSV (Through Silicon Via).

[0308] Furthermore, conductor 216 can be, for example, conductor CNT1A shown in Figure 11A, Figure 11B, Figure 12A, Figure 12B, Figure 15A, Figure 16A, or Figure 16B. Furthermore, insulator 214 can be, for example, an insulator formed on the side surface of an opening in which conductor CNT1A shown in Figure 11A, Figure 11B, Figure 12A, Figure 12B, Figure 15A, Figure 16A, or Figure 16B is embedded.

[0309] For one or both of the conductor 216 and the conductor 228, for example, a material applicable to the conductor 328 can be used. In particular, the conductor 216 is preferably formed from the same material as the conductor 376.

[0310] The insulator 214 has a function of insulating the substrate 210 from the conductor 216. Note that the insulator 214 is preferably made of a material that can be used for the insulator 320 or the insulator 324, for example.

[0311] The insulator 380 and the conductor 376 formed on the substrate 310 and the insulator 202 and the conductor 216 formed on the substrate 210 are joined together by, for example, a bonding process.

[0312] As a pre-process before the bonding process, for example, a planarization process is performed on the substrate 310 side to align the heights of the surfaces of the insulator 380 and the conductor 376. Similarly, a planarization process is performed on the substrate 210 side to align the heights of the insulator 202 and the conductor 216.

[0313] In the bonding process, when bonding insulator 380 and insulator 202, that is, bonding insulating layers together, a hydrophilic bonding method can be used, in which, for example, after polishing to achieve high flatness, surfaces that have been hydrophilically treated with oxygen plasma are brought into contact with each other to form a temporary bond, and then the final bond is achieved by dehydrating them with heat treatment. Hydrophilic bonding also produces bonds at the atomic level, resulting in mechanically excellent bonds.

[0314] Furthermore, when bonding conductor 376 and conductor 216, that is, bonding conductors together, a surface activated bonding method can be used, in which oxide films and impurity adsorption layers on the surfaces are removed by sputtering or other methods, and the cleaned and activated surfaces are brought into contact and bonded. Alternatively, a diffusion bonding method can be used, in which surfaces are bonded using a combination of temperature and pressure. Both methods involve bonding at the atomic level, resulting in excellent bonding not only electrically but also mechanically.

[0315] By carrying out the above-described bonding process, the conductor 376 on the substrate 310 side can be electrically connected to the conductor 216 on the substrate 210 side. Also, a connection with sufficient mechanical strength can be obtained between the insulator 380 on the substrate 310 side and the insulator 202 on the substrate 210 side.

[0316] When bonding substrate 310 and substrate 210, since the bonding surfaces of each substrate contain a mixture of insulating and metal layers, a surface activated bonding method and a hydrophilic bonding method may be combined. For example, a bonding method may be used in which the surfaces are polished and then cleaned, and the surface of the metal layer is subjected to an anti-oxidation treatment, followed by a hydrophilic treatment. Alternatively, the surface of the metal layer may be made of a resistant metal such as gold and then subjected to a hydrophilic treatment.

[0317] Note that bonding methods other than those described above may be used to bond the substrates 310 and 210. For example, flip-chip bonding may be used to bond the substrates 310 and 210. Furthermore, when using flip-chip bonding, connection terminals such as bumps may be provided above the conductor 376 on the substrate 310 side or below the conductor 216 on the substrate 210 side. Examples of flip-chip bonding include a method in which a resin containing anisotropic conductive particles is injected between the insulator 380 and the insulator 202 and between the conductor 376 and the conductor 216 to bond them, and a method in which silver-tin solder is used to bond them. Alternatively, when the bumps and the conductors connected to the bumps are both made of gold, ultrasonic bonding may be used. Furthermore, in addition to the flip-chip bonding method described above, an underfill agent may be injected between the insulator 380 and the insulator 202 and between the conductor 376 and the conductor 216 to reduce physical stress such as impact and thermal stress. Furthermore, for example, the substrate 310 and the substrate 210 may be bonded together using a die bonding film.

[0318] An insulator 224 and an insulator 226 are stacked in this order on the insulator 222, the insulator 214, the conductor 216, and the conductor 228.

[0319] Like the insulator 324, the insulator 224 is preferably a barrier insulating film that prevents impurities such as water and hydrogen from diffusing into a region above the insulator 224. Therefore, it is preferable to use, for example, a material that can be used for the insulator 324 as the insulator 224.

[0320] The insulator 226 is preferably an interlayer film with a low dielectric constant, similar to the insulator 326. Therefore, the insulator 226 is preferably made of a material that can be used for the insulator 326, for example.

[0321] Furthermore, a conductor 230 electrically connected to the transistor 200, the light-emitting device 150, etc. is embedded in the insulator 224 and the insulator 226. The conductor 230 functions as a plug or wiring. For the conductor 230, for example, a material applicable to the conductor 328 and the conductor 330 can be used.

[0322] On the insulators 224 and 226, the insulators 250, 252, and 111 are stacked in this order.

[0323] The insulator 250 is preferably an insulator having barrier properties against impurities such as water and hydrogen, similar to the insulator 324. Therefore, the insulator 250 can be made of, for example, a material that can be used for the insulator 324.

[0324] The insulator 352 functions as an interlayer insulating film and a planarizing film. Similarly to the insulator 324, the insulator 352 is preferably an insulator having a barrier property against impurities such as water and hydrogen. For this reason, the insulator 352 can be made of a material that can be used for the insulator 324.

[0325] The insulator 111 is preferably an insulator that has a function of suppressing diffusion of water, hydrogen, and oxygen, such as aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, or silicon nitride oxide. For example, silicon nitride, which has a higher hydrogen barrier property, is preferably used for the insulator 111. Furthermore, the insulator 111 is preferably made of aluminum oxide or magnesium oxide, which has a high function of capturing and fixing hydrogen.

[0326] A highly flat film is preferably used for the insulator 111. In this case, the insulator 111 can be made of an organic material such as an acrylic resin or polyimide.

[0327] Furthermore, openings are formed in the insulators 250, 252, and 111 in regions that overlap with part of the conductor 230, and a conductor 256 is provided to fill the openings. The conductor 256 is also formed over the insulator 352. For example, the conductor 256 functions as a plug or wiring that connects to the light-emitting device 150. Note that the conductor 256 can be provided using a material similar to that of the conductors 328 and 330.

[0328] Above the insulator 111, a light emitting device 150a and a light emitting device 150b are provided.

[0329] Here, the light emitting device 150a and the light emitting device 150b will be described.

[0330] The light-emitting device described in this embodiment refers to a self-luminous light-emitting device such as an organic light-emitting diode (OLED). The light-emitting device electrically connected to the pixel circuit can be a self-luminous light-emitting device such as an LED (Light Emitting Diode), a micro LED, a QLED (Quantum-dot Light Emitting Diode), or a semiconductor laser.

[0331] Conductors 121a and 121b, which function as pixel electrodes of the light-emitting device 150a and the light-emitting device 150b, respectively, are provided on the insulator 111. Note that in Fig. 17, there are regions on the insulator 111 where the conductors 121a and 121b are not provided. Note that in this specification and the like, the conductors 121a and 121b may be collectively referred to as the conductor 121.

[0332] The conductor 121a and the conductor 121b can be formed, for example, by forming a conductive film over the insulator 111 and performing a patterning step and an etching step on the conductive film.

[0333] The conductor 121a and the conductor 121b function as the anodes of the light emitting device 150a and the light emitting device 150b included in the display device 100, respectively, as an example.

[0334] For example, indium tin oxide (sometimes called ITO) can be used as the conductor 121a and the conductor 121b.

[0335] Furthermore, each of the conductors 121a and 121b may have a laminated structure of two or more layers instead of a single layer. For example, a conductor with high reflectivity to visible light may be used for the first layer conductor, and a conductor with high translucency may be used for the top layer conductor. Examples of conductors with high reflectivity to visible light include silver, aluminum, and an alloy film of silver (Ag), palladium (Pd), and copper (Cu) (Ag-Pd-Cu (APC) film). Examples of conductors with high translucency include the above-mentioned indium tin oxide. Examples of the conductors 121a and 121b include a laminated film of aluminum sandwiched between a pair of titanium films (a laminated film of Ti, Al, and Ti in this order), a laminated film of silver sandwiched between a pair of indium tin oxide films (a laminated film of ITO, Ag, and ITO in this order), etc.

[0336] An EL layer 141a is provided on a part of the insulator 111 and on the conductor 121a. An EL layer 141b is provided on a part of the insulator 111 and on the conductor 121b. In Fig. 17, there is a region on the insulator 111 where the EL layer 141a and the EL layer 141b are not provided.

[0337] Preferably, the EL layer 141a and the EL layer 141b each have a light-emitting layer that emits light of a different color. For example, the EL layer 141a may have a light-emitting layer that emits light of one of red (R), green (G), and blue (B), and the EL layer 141b may have a light-emitting layer that emits light of one of the remaining two. Furthermore, although not shown in FIG. 17, when an EL layer different from the EL layer 141a and the EL layer 141b is provided, the EL layer may have a light-emitting layer that emits light of the remaining one. In this way, the display device 100 may have a structure (SBS structure) in which different light-emitting layers for each color are formed on a plurality of pixel electrodes (conductors 121a and 121b).

[0338] The combination of colors emitted by the light-emitting layers included in the EL layer 141a and the EL layer 141b is not limited to the above, and may be, for example, cyan, magenta, or yellow. Although the above example shows three colors, the number of colors emitted by the light-emitting device 150 included in the display device 100 may be two, three, or four or more.

[0339] The EL layer 141a and the EL layer 141b may each have one or more of an electron injection layer, an electron transport layer, a hole injection layer, and a hole transport layer in addition to a layer containing a light-emitting organic compound (light-emitting layer).

[0340] In addition, the EL layer 141a and the EL layer 141b can be formed by a method such as a vapor deposition method (vacuum vapor deposition method, etc.), a coating method (e.g., dip coating method, die coating method, bar coating method, spin coating method, or spray coating method), or a printing method (e.g., inkjet method, screen (stencil printing) method, offset (lithographic printing) method, flexography (relief printing) method, gravure method, or microcontact method).

[0341] When a film formation method such as the coating method or printing method is used, for example, a high molecular weight compound (e.g., an oligomer, a dendrimer, and a polymer), a medium molecular weight compound (a compound in the intermediate range between a low molecular weight and a high molecular weight: a molecular weight of 400 to 4000), or an inorganic compound (e.g., a quantum dot material) can be used. The quantum dot material can be a colloidal quantum dot material, an alloy quantum dot material, a core-shell quantum dot material, or a core quantum dot material.

[0342] For example, light emitting device 150a and light emitting device 150b in FIG. 17 may be configured with multiple layers such as layer 4420, light emitting layer 4411, and layer 4430, as in light emitting device 150 shown in FIG. 18A.

[0343] The layer 4420 can have, for example, a layer containing a substance with a high electron-injecting property (electron-injecting layer) and a layer containing a substance with a high electron-transporting property (electron-transporting layer). The light-emitting layer 4411 contains, for example, a light-emitting compound. The layer 4430 can have, for example, a layer containing a substance with a high hole-injecting property (hole-injecting layer) and a layer containing a substance with a high hole-transporting property (hole-transporting layer).

[0344] A structure having a layer 4420, a light-emitting layer 4411, and a layer 4430 provided between a pair of electrodes (conductor 121 and conductor 122 described later) can function as a single light-emitting unit, and in this specification, the structure of Figure 18A is called a single structure.

[0345] 18B shows a modified example of the EL layer 141 of the light-emitting device 150 shown in Fig. 18A. Specifically, the light-emitting device 150 shown in Fig. 18B has a layer 4430-1 on the conductor 121, a layer 4430-2 on the layer 4430-1, a light-emitting layer 4411 on the layer 4430-2, a layer 4420-1 on the light-emitting layer 4411, a layer 4420-2 on the layer 4420-1, and a conductor 122 on the layer 4420-2. For example, when the conductor 121 is the anode and the conductor 122 is the cathode, the layer 4430-1 functions as a hole injection layer, the layer 4430-2 functions as a hole transport layer, the layer 4420-1 functions as an electron transport layer, and the layer 4420-2 functions as an electron injection layer. Alternatively, when the conductor 121 is used as a cathode and the conductor 122 is used as an anode, the layer 4430-1 functions as an electron injection layer, the layer 4430-2 functions as an electron transport layer, the layer 4420-1 functions as a hole transport layer, and the layer 4420-2 functions as a hole injection layer. By using such a layer structure, it is possible to efficiently inject carriers into the light-emitting layer 4411 and increase the efficiency of carrier recombination in the light-emitting layer 4411.

[0346] Note that a configuration in which a plurality of light-emitting layers (for example, a light-emitting layer 4411, a light-emitting layer 4412, and a light-emitting layer 4413) are provided between the layer 4420 and the layer 4430 as shown in FIG. 18C is also a variation of the single structure.

[0347] A laminate having multiple layers such as layer 4420, light-emitting layer 4411, and layer 4430 may be referred to as a light-emitting unit. Multiple light-emitting units may be connected in series via an intermediate layer (charge generation layer). Specifically, as shown in FIG. 18D, multiple light-emitting units, such as light-emitting unit 4400a and light-emitting unit 4400b, may be connected in series via an intermediate layer (charge generation layer) 4440. In this specification, such a structure is referred to as a tandem structure. In this specification and the like, a tandem structure may also be referred to as a stack structure. By forming a light-emitting device in a tandem structure, a light-emitting device capable of emitting light with high brightness can be obtained. By forming a light-emitting device in a tandem structure, the light-emitting efficiency and lifespan of the light-emitting device can be improved. When the light-emitting device 150 of the display device 100 of FIG. 17 has a tandem structure, the EL layer 141 can be configured to include, for example, layer 4420, light-emitting layer 4411, and layer 4430 of light-emitting unit 4400a, intermediate layer 4440, and layer 4420, light-emitting layer 4412, and layer 4430 of light-emitting unit 4400b.

[0348] Furthermore, when displaying white, the SBS structure described above can reduce power consumption compared to the single and tandem structures. Therefore, if you want to keep power consumption low, the SBS structure is preferable. On the other hand, the single and tandem structures are preferable because their manufacturing processes are easier than those of the SBS structure, allowing for lower manufacturing costs and higher manufacturing yields.

[0349] The light-emitting device 150 can emit light in red, green, blue, cyan, magenta, yellow, or white, depending on the material of the EL layer 141. Furthermore, the color purity can be further improved by providing the light-emitting device 150 with a microcavity structure.

[0350] A light-emitting device that emits white light preferably has a structure in which the light-emitting layer contains two or more light-emitting materials. To obtain white light, it is sufficient to select two or more light-emitting materials whose respective emissions are complementary colors.

[0351] The light-emitting layer preferably contains two or more light-emitting materials selected from the group consisting of R (red), G (green), B (blue), Y (yellow), and O (orange) as emission colors. Alternatively, the light-emitting layer preferably contains two or more light-emitting materials, and the light emitted by each of the light-emitting materials preferably contains spectral components of two or more colors selected from R, G, and B.

[0352] 17, a gap is provided between two EL layers between light-emitting devices of different colors. In this manner, it is preferable that the EL layer 141a and the EL layer 141b are provided so as not to contact each other. This makes it possible to effectively prevent current from flowing through two adjacent EL layers, resulting in unintended light emission (also known as crosstalk). This allows for increased contrast, resulting in a display device with high display quality.

[0353] The EL layer 141a and the EL layer 141b can be formed, for example, by a method using photolithography. For example, an EL film to become the EL layer 141a and the EL layer 141b can be formed on the insulator 111 and the conductor 121, and then the EL film can be patterned by photolithography to form the EL layer 141a and the EL layer 141b. Alternatively, the conductor 122 can be formed on the EL film, and then the EL film, including the conductor 122, can be patterned by photolithography to form the EL layer 141a and the EL layer 141b. In this case, the EL layer 141a and the EL layer 141b have the same structure. Therefore, when it is desired to perform color display with the display device 100 formed using this formation method, the light-emitting device 150a and the light-emitting device 150b, which include the EL layer 141a and the EL layer 141b, respectively, can be configured as light-emitting devices that emit white light, and the display device 100 can be configured so that light from the light-emitting devices is emitted to the outside through a colored layer (color filter).

[0354] The EL layer 141a and the EL layer 141b are formed by first depositing an EL film that will become the EL layer 141a on the insulator 111 and the conductor 121, and then forming the EL layer 141a by photolithography. Then, the EL layer 141b is formed in a predetermined region using a similar procedure. By using this method, the EL layer 141a and the EL layer 141b can be made to have different structures, and the display device 100 can have an SBS structure.

[0355] Furthermore, the above-described method can shorten the distance between adjacent pixels. This allows the number of pixels included in the display unit to be increased, thereby increasing the resolution of the display device. For example, the distance between adjacent pixels is preferably 5 μm or less, and more preferably 1 μm or less.

[0356] By configuring the display device 100 of FIG. 17 using the method described above, it is possible to realize a display device having a resolution of preferably 1000 ppi or more, more preferably 3000 ppi or more, and even more preferably 5000 ppi or more.

[0357] The EL layers 141a and 141b may be formed by a method other than photolithography, such as nanoimprinting or lift-off. Alternatively, island-shaped thin films may be directly formed by a film formation method using a shielding mask as a metal mask.

[0358] A conductor 122 is provided on the insulator 111, the EL layer 141a, and the EL layer 141b. An insulator 113 is provided on the conductor 122.

[0359] The conductor 122 functions as, for example, a common electrode for the light-emitting device 150a and the light-emitting device 150b. In order to emit light from the light-emitting device 150 upward from the display device 100, the conductor 122 preferably includes a light-transmitting conductive material.

[0360] The conductor 122 is preferably a highly conductive material that is also light-transmitting and light-reflecting (sometimes called a semi-transparent / semi-reflective electrode). For example, an alloy of silver and magnesium or indium tin oxide can be used for the conductor 122.

[0361] The insulator 113 functions as, for example, a passivation film that protects the light-emitting device 150a and the light-emitting device 150b. Therefore, the insulator 113 is preferably made of, for example, a material that prevents water from entering. For the insulator 113, for example, a material that can be used for the insulator 111 can be used. Specifically, aluminum oxide, silicon nitride, or silicon nitride oxide can be used.

[0362] A resin layer 161 is provided on the insulator 113. Furthermore, a substrate 102 is provided on the resin layer 161.

[0363] For example, a light-transmitting substrate is preferably used as the substrate 102. By using a light-transmitting substrate for the substrate 102, light emitted from the light-emitting device 150a and the light-emitting device 150b can be emitted upward from the substrate 102.

[0364] Note that the display device according to one embodiment of the present invention is not limited to the configuration of the display device 100 illustrated in Fig. 17. The configuration of the display device according to one embodiment of the present invention may be changed as appropriate within the scope of solving the problem.

[0365] For example, the transistor 200 included in the pixel layer PXAL of the display device 100 in Fig. 17 may be a transistor having a metal oxide in a channel formation region (hereinafter referred to as an OS transistor). The display device 100 shown in Fig. 19 has a configuration in which a transistor 500 (OS transistor) replacing the transistor 200 and a light-emitting device 150 are provided above the circuit layer SICL and the wiring layer LINL of the display device 100 in Fig. 17.

[0366] 19, the transistor 500 is provided over an insulator 512. The insulator 512 is provided over the insulator 364 and the conductor 366, and a substance that has a barrier property against oxygen and hydrogen is preferably used for the insulator 512. Specifically, the insulator 512 can be formed using, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, or aluminum nitride.

[0367] An example of a film having a barrier property against hydrogen is silicon nitride formed by a CVD method. Here, hydrogen diffusion into a semiconductor element having an oxide semiconductor, such as the transistor 500, may degrade the characteristics of the semiconductor element. Therefore, it is preferable to use a film that suppresses hydrogen diffusion between the transistor 500 and the transistor 300. Specifically, the film that suppresses hydrogen diffusion is a film that releases a small amount of hydrogen.

[0368] For example, the insulator 512 can be made of a material similar to that of the insulator 320. By using a material with a relatively low dielectric constant for these insulators, the parasitic capacitance between wirings can be reduced. For example, the insulator 512 can be made of a silicon oxide film or a silicon oxynitride film.

[0369] The transistor 500 will now be described in detail. 20A and 20B show an example of the configuration of the OS transistor 500. Note that FIG. 20A is a cross-sectional view of the OS transistor in the channel length direction, and FIG. 20B is a cross-sectional view of the OS transistor in the channel width direction.

[0370] As shown in FIGS. 20A and 20B, an insulator 514 and an insulator 516 are formed on the insulator 512.

[0371] The insulator 514 is preferably a film having a barrier property that prevents hydrogen and impurities from diffusing from the substrate 310 or a region where circuit elements and the like below the insulator 512 are provided to the region where the transistor 500 is provided. Therefore, the insulator 514 can be made of silicon nitride formed by a CVD method, for example.

[0372] The insulator 516 can be made of, for example, the same material as the insulator 512 .

[0373] As shown in FIGS. 20A and 20B, the transistor 500 includes an insulator 516 on an insulator 514, a conductor 503 (conductor 503a and conductor 503b) disposed so as to be embedded in the insulator 514 or the insulator 516, an insulator 522 on the insulator 516 and on the conductor 503, an insulator 524 on the insulator 522, an oxide 530a on the insulator 524, an oxide 530b on the oxide 530a, a conductor 542a on the oxide 530b, an insulator 571a on the conductor 542a, and an oxide 572a on the oxide 572b. conductor 542b on oxide 530b, insulator 571b on conductor 542b, insulator 552 on oxide 530b, insulator 550 on insulator 552, insulator 554 on insulator 550, conductor 560 (conductor 560a and conductor 560b) located on insulator 554 and overlapping part of oxide 530b, and insulator 544 arranged on insulator 522, insulator 524, oxide 530a, oxide 530b, conductor 542a, conductor 542b, insulator 571a, and insulator 571b. 20A and 20B , insulator 552 contacts the upper surface of insulator 522, the side surface of insulator 524, the side surface of oxide 530a, the side surface and upper surface of oxide 530b, the side surface of conductor 542, the side surface of insulator 571, the side surface of insulator 544, the side surface of insulator 580, and the lower surface of insulator 550. Furthermore, the upper surface of conductor 560 is disposed so as to be at approximately the same height as the upper surfaces of insulators 554, 550, 552, and 580. Furthermore, insulator 574 contacts at least a portion of the upper surface of conductor 560, 552, 550, 554, and 580.

[0374] Openings reaching the oxide 530b are provided in the insulator 580 and the insulator 544. The insulator 552, the insulator 550, the insulator 554, and the conductor 560 are disposed in the openings. In addition, the conductor 560, the insulator 552, the insulator 550, and the insulator 554 are provided between the insulator 571a and the conductor 542a and between the insulator 571b and the conductor 542b in the channel length direction of the transistor 500. The insulator 554 has a region in contact with the side surface of the conductor 560 and a region in contact with the bottom surface of the conductor 560.

[0375] The oxide 530 preferably includes an oxide 530a disposed on the insulator 524 and an oxide 530b disposed on the oxide 530a. By providing the oxide 530a below the oxide 530b, it is possible to suppress the diffusion of impurities from structures formed below the oxide 530a to the oxide 530b.

[0376] Note that although the transistor 500 has a structure in which the oxide 530 has two layers, the oxide 530a and the oxide 530b, the present invention is not limited to this. For example, the transistor 500 can have a single layer of the oxide 530b or a stacked structure of three or more layers. Alternatively, each of the oxide 530a and the oxide 530b can have a stacked structure.

[0377] The conductor 560 functions as a first gate (also referred to as a top gate) electrode, and the conductor 503 functions as a second gate (also referred to as a back gate) electrode. The insulators 552, 550, and 554 function as a first gate insulator, and the insulators 522 and 524 function as a second gate insulator. The gate insulators may also be referred to as a gate insulating layer or a gate insulating film. The conductor 542a functions as either a source or a drain, and the conductor 542b functions as the other. At least a part of a region of the oxide 530 that overlaps with the conductor 560 functions as a channel formation region.

[0378] FIG. 21A shows an enlarged view of the vicinity of the channel formation region in FIG. 20A. When oxygen is supplied to the oxide 530b, a channel formation region is formed in a region between the conductor 542a and the conductor 542b. Therefore, as shown in FIG. 21A, the oxide 530b includes a region 530bc that functions as a channel formation region of the transistor 500, and regions 530ba and 530bb that are provided on either side of the region 530bc and function as source and drain regions. At least a portion of the region 530bc overlaps with the conductor 560. In other words, the region 530bc is located in a region between the conductor 542a and the conductor 542b. The region 530ba overlaps with the conductor 542a, and the region 530bb overlaps with the conductor 542b.

[0379] The region 530bc, which functions as a channel formation region, has a smaller oxygen vacancy (in this specification, oxygen vacancy in a metal oxide is referred to as V) than the regions 530ba and 530bb. O The region 530bc is a high-resistivity region with a low carrier concentration due to its low oxygen vacancy (sometimes called oxygen vacancy) or low impurity concentration. Therefore, the region 530bc can be said to be i-type (intrinsic) or substantially i-type.

[0380] A transistor using a metal oxide has impurities or oxygen vacancies (V O ) may cause fluctuations in electrical characteristics and reduce reliability. O ) hydrogen near the oxygen vacancy (V O ) with hydrogen (hereafter referred to as V O H) and generate electrons that serve as carriers. Therefore, if oxygen vacancies are present in the region where a channel is formed in the oxide semiconductor, the transistor is likely to have normally-on characteristics (a channel exists and current flows through the transistor even when no voltage is applied to the gate electrode). Therefore, in the region where a channel is formed in the oxide semiconductor, impurities, oxygen vacancies, and V OIt is preferable that H is reduced as much as possible.

[0381] In addition, in the regions 530ba and 530bb that function as source and drain regions, oxygen vacancies (V O ) or high concentrations of impurities such as hydrogen, nitrogen, and metal elements. Therefore, the regions 530ba and 530bb can be said to be regions with increased carrier concentrations and low resistance. In other words, the regions 530ba and 530bb are n-type regions with higher carrier concentrations and lower resistance than the region 530bc.

[0382] Here, the carrier concentration of the region 530bc that functions as a channel forming region is 1×10 18 cm -3 Preferably, it is 1×10 or less. 17 cm -3 More preferably, it is less than 1×10 16 cm -3 More preferably, it is less than 1×10 13 cm -3 More preferably, it is less than 1×10 12 cm -3 The lower limit of the carrier concentration of the region 530bc that functions as a channel formation region is not particularly limited, but is preferably, for example, 1×10 -9 cm -3 It can be said that:

[0383] A region having a carrier concentration equal to or lower than that of regions 530ba and 530bb and equal to or higher than that of region 530bc may be formed between region 530bc and regions 530ba or 530bb. That is, this region functions as a junction region between region 530bc and regions 530ba or 530bb. The junction region may have a hydrogen concentration equal to or lower than that of regions 530ba and 530bb and equal to or higher than that of region 530bc. The junction region may also have oxygen vacancies equal to or lower than those of regions 530ba and 530bb and equal to or higher than those of region 530bc.

[0384] 21A shows an example in which the regions 530ba, 530bb, and 530bc are formed in the oxide 530b, but the present invention is not limited to this. For example, each of the above regions may be formed not only in the oxide 530b but also in the oxide 530a.

[0385] Furthermore, it may be difficult to clearly detect the boundaries between the regions in the oxide 530. The concentrations of metal elements and impurity elements such as hydrogen and nitrogen detected in each region may vary continuously within each region, rather than gradually varying from region to region. In other words, it is sufficient that the concentrations of metal elements and impurity elements such as hydrogen and nitrogen decrease in the region closer to the channel formation region.

[0386] In the transistor 500, the oxide 530 including the channel formation region (the oxide 530a and the oxide 530b) is preferably formed using a metal oxide that functions as a semiconductor (hereinafter also referred to as an oxide semiconductor).

[0387] The metal oxide functioning as a semiconductor preferably has a band gap of 2 eV or more, preferably 2.5 eV or more. By using such a metal oxide with a wide band gap, the off-state current of the transistor can be reduced.

[0388] For example, an In-M-Zn oxide containing indium, element M, and zinc (element M is one or more elements selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium) may be used as oxide 530. Alternatively, In-Ga oxide, In-Zn oxide, or indium oxide may be used as oxide 530.

[0389] Here, it is preferable that the atomic ratio of In to element M in the metal oxide used for oxide 530b is greater than the atomic ratio of In to element M in the metal oxide used for oxide 530a.

[0390] In this way, by disposing the oxide 530a below the oxide 530b, it is possible to suppress the diffusion of impurities and oxygen from the structure formed below the oxide 530a into the oxide 530b.

[0391] Furthermore, since the oxide 530a and the oxide 530b have a common element other than oxygen (as a main component), the defect state density at the interface between the oxide 530a and the oxide 530b can be reduced. Because the defect state density at the interface between the oxide 530a and the oxide 530b can be reduced, the effect of interface scattering on carrier conduction is reduced, and a high on-current can be obtained.

[0392] In a transistor using an oxide semiconductor, if impurities and oxygen vacancies exist in a region where a channel is formed in the oxide semiconductor, the electrical characteristics are likely to fluctuate and the reliability may be reduced. In addition, hydrogen near the oxygen vacancies may be introduced into the oxygen vacancies (hereinafter referred to as VO H) and generate electrons that serve as carriers. Therefore, if oxygen vacancies are present in the region where a channel is formed in the oxide semiconductor, the transistor is likely to have normally-on characteristics (a channel exists and current flows through the transistor even when no voltage is applied to the gate electrode). Therefore, in the region where a channel is formed in the oxide semiconductor, impurities, oxygen vacancies, and V O It is preferable that H is reduced as much as possible. In other words, it is preferable that the region in the oxide semiconductor where a channel is formed has a reduced carrier concentration and is i-type (intrinsic) or substantially i-type.

[0393] In response to this problem, an insulator containing oxygen that is released by heating (hereinafter may be referred to as excess oxygen) is provided near the oxide semiconductor, and heat treatment is performed to supply oxygen from the insulator to the oxide semiconductor, thereby eliminating oxygen vacancies and V O H can be reduced. However, if an excessive amount of oxygen is supplied to the source region or the drain region, this may cause a decrease in the on-state current or a decrease in the field-effect mobility of the transistor 500. Furthermore, if the amount of oxygen supplied to the source region or the drain region varies across the substrate surface, the characteristics of the semiconductor device having the transistor will vary.

[0394] Therefore, in the oxide semiconductor, the region 530bc that functions as a channel formation region preferably has a reduced carrier concentration and is i-type or substantially i-type, whereas the regions 530ba and 530bb that function as source and drain regions preferably have a high carrier concentration and are n-type. O It is preferable to reduce H so that an excessive amount of oxygen is not supplied to the regions 530ba and 530bb.

[0395] Therefore, in this embodiment, in a state where the conductors 542a and 542b are provided on the oxide 530b, microwave treatment is performed in an atmosphere containing oxygen to remove oxygen vacancies in the region 530bc and VO The microwave treatment here refers to a treatment using a device with a power source that generates high-density plasma using microwaves, for example.

[0396] By performing microwave processing in an atmosphere containing oxygen, oxygen gas can be converted into plasma using microwaves or high frequency waves such as RF, and the oxygen plasma can be activated. At this time, microwaves or high frequency waves such as RF can also be irradiated onto the region 530bc. The action of the plasma or microwaves can be used to irradiate the V of the region 530bc. O H is split off, hydrogen H is removed from the region 530bc, and oxygen vacancy V O can be compensated with oxygen. O H → H + V O This reaction occurs, and the hydrogen concentration in the region 530bc can be reduced. O H can be reduced to lower the carrier concentration.

[0397] Furthermore, when microwave processing is performed in an atmosphere containing oxygen, the effects of microwaves, high frequency waves such as RF, oxygen plasma, etc. are shielded by the conductors 542a and 542b and do not reach the regions 530ba and 530bb. Furthermore, the effects of oxygen plasma can be reduced by the insulators 571 and 580 that cover the oxide 530b and the conductor 542. As a result, during microwave processing, V O Since there is no reduction in H and no excessive supply of oxygen, it is possible to prevent a decrease in the carrier concentration.

[0398] Furthermore, it is preferable to perform microwave treatment in an oxygen-containing atmosphere after forming the insulating film that becomes the insulator 552 or after forming the insulating film that becomes the insulator 550. By performing microwave treatment in an oxygen-containing atmosphere through the insulator 552 or the insulator 550 in this manner, oxygen can be efficiently injected into the region 530bc. Furthermore, by arranging the insulator 552 so as to be in contact with the side surface of the conductor 542 and the surface of the region 530bc, injection of more oxygen than necessary into the region 530bc can be suppressed, thereby suppressing oxidation of the side surface of the conductor 542. Furthermore, oxidation of the side surface of the conductor 542 can be suppressed during formation of the insulating film that becomes the insulator 550.

[0399] The oxygen implanted into the region 530bc can be in various forms, such as oxygen atoms, oxygen molecules, and oxygen radicals (atoms, molecules, or ions with an unpaired electron, also known as O radicals). The oxygen implanted into the region 530bc preferably takes one or more of the above forms, and oxygen radicals are particularly preferred. Furthermore, the film quality of the insulator 552 and the insulator 550 can be improved, thereby improving the reliability of the transistor 500.

[0400] In this way, oxygen vacancies and V are selectively formed in the oxide semiconductor region 530bc. O By removing H, the region 530bc can be made i-type or substantially i-type. Furthermore, the supply of excess oxygen to the regions 530ba and 530bb, which function as source and drain regions, can be prevented, maintaining the n-type state of the regions before microwave treatment. This suppresses fluctuations in the electrical characteristics of the transistor 500 and reduces variations in the electrical characteristics of the transistor 500 within the substrate surface.

[0401] With the above-described structure, a semiconductor device (or a display device) with little variation in transistor characteristics can be provided. Furthermore, a semiconductor device (or a display device) with good reliability can be provided. Furthermore, a semiconductor device (or a display device) with good electrical characteristics can be provided.

[0402] 20B, in a cross-sectional view of the transistor 500 in the channel width direction, a curved surface may be formed between the side surface of the oxide 530b and the top surface of the oxide 530b. That is, the end portions of the side surface and the top surface may be curved (hereinafter also referred to as rounded).

[0403] The radius of curvature of the curved surface is preferably greater than 0 nm and smaller than the film thickness of the oxide 530b in the region overlapping with the conductor 542, or smaller than half the length of the region not having the curved surface. Specifically, the radius of curvature of the curved surface is greater than 0 nm and smaller than 20 nm, preferably greater than 1 nm and smaller than 15 nm, and more preferably greater than 2 nm and smaller than 10 nm. This shape can improve the coverage of the oxide 530b with the insulators 552, 550, and 554, and the conductor 560.

[0404] The oxide 530 preferably has a stacked structure of multiple oxide layers with different chemical compositions. Specifically, in the metal oxide used for the oxide 530a, the atomic ratio of the element M to the metal element that is the main component is preferably greater than the atomic ratio of the element M to the metal element that is the main component in the metal oxide used for the oxide 530b. Furthermore, in the metal oxide used for the oxide 530a, the atomic ratio of the element M to In is preferably greater than the atomic ratio of the element M to In in the metal oxide used for the oxide 530b. Furthermore, in the metal oxide used for the oxide 530b, the atomic ratio of In to the element M is preferably greater than the atomic ratio of In to the element M in the metal oxide used for the oxide 530a.

[0405] Here, the conduction band minimum changes gradually at the junction between the oxides 530a and 530b. In other words, the conduction band minimum at the junction between the oxides 530a and 530b changes continuously or forms a continuous junction. To achieve this, it is advisable to reduce the defect level density of the mixed layer formed at the interface between the oxides 530a and 530b.

[0406] Specifically, when the oxide 530a and the oxide 530b contain a common element other than oxygen as a main component, a mixed layer with a low density of defect states can be formed. For example, when the oxide 530b is an In-M-Zn oxide, the oxide 530a may be an In-M-Zn oxide, an M-Zn oxide, an oxide of element M, an In-Zn oxide, or an indium oxide.

[0407] Specifically, oxide 530a may be a metal oxide having an atomic ratio of In:M:Zn=1:3:4 or a similar composition, or an atomic ratio of In:M:Zn=1:1:0.5 or a similar composition. Oxide 530b may be a metal oxide having an atomic ratio of In:M:Zn=1:1:1 or a similar composition, or an atomic ratio of In:M:Zn=4:2:3 or a similar composition. Note that a similar composition includes a range of ±30% of the desired atomic ratio. Gallium is preferably used as element M.

[0408] When a metal oxide film is formed by sputtering, the atomic ratio is not limited to the atomic ratio of the formed metal oxide film, but may be the atomic ratio of a sputtering target used to form the metal oxide film.

[0409] 20A and other figures, providing an insulator 552 made of aluminum oxide or the like in contact with the top and side surfaces of the oxide 530 can cause indium in the oxide 530 to be unevenly distributed at and near the interface between the oxide 530 and the insulator 552. This results in an atomic ratio near the surface of the oxide 530 that is close to that of indium oxide or In-Zn oxide. The increased atomic ratio of indium near the surface of the oxide 530, particularly the oxide 530b, can improve the field-effect mobility of the transistor 500.

[0410] The oxide 530a and the oxide 530b have the above-described structure, which can reduce the defect state density at the interface between the oxide 530a and the oxide 530b. As a result, the influence of interface scattering on carrier conduction is reduced, and the transistor 500 can achieve a large on-state current and high frequency characteristics.

[0411] At least one selected from the insulators 512, 514, 544, 571, 574, 576, and 581 preferably functions as a barrier insulating film that suppresses diffusion of impurities such as water and hydrogen from the substrate side or from above the transistor 500 into the transistor 500. Therefore, at least one selected from the insulators 512, 514, 544, 571, 574, 576, and 581 is preferably an insulating material that suppresses diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (e.g., NO, NO, and NO), and copper atoms (i.e., through which the above impurities are less likely to permeate). Alternatively, it is preferable to use an insulating material that suppresses diffusion of oxygen (e.g., oxygen atoms and / or oxygen molecules) (i.e., through which the above oxygen is less likely to permeate).

[0412] For the insulators 512, 514, 544, 571, 574, 576, and 581, it is preferable to use an insulator that has the function of suppressing diffusion of oxygen and impurities such as water and hydrogen. For example, aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium-gallium-zinc oxide, silicon nitride, or silicon nitride oxide can be used. For example, silicon nitride, which has a high hydrogen barrier property, is preferably used for the insulators 512, 544, and 576. Furthermore, for example, aluminum oxide or magnesium oxide, which has a high ability to capture and fix hydrogen, is preferably used for the insulators 514, 571, 574, and 581. This can suppress diffusion of impurities such as water and hydrogen from the substrate side to the transistor 500 side through the insulators 512 and 514. Alternatively, impurities such as water and hydrogen can be prevented from diffusing toward the transistor 500 from an interlayer insulating film or the like disposed outside the insulator 581. Alternatively, oxygen contained in the insulator 524 or the like can be prevented from diffusing toward the substrate through the insulators 512 and 514. Alternatively, oxygen contained in the insulator 580 can be prevented from diffusing upward from the transistor 500 through the insulator 574. In this way, the transistor 500 is preferably surrounded by the insulators 512, 514, 571, 544, 574, 576, and 581, which have the function of preventing diffusion of impurities such as water and hydrogen and oxygen.

[0413] Here, it is preferable to use an oxide having an amorphous structure as the insulators 512, 514, 544, 571, 574, 576, and 581. For example, AlO x (x is any number greater than 0), or MgO yIt is preferable to use a metal oxide having an amorphous structure (where y is any number greater than 0). In such metal oxides having an amorphous structure, oxygen atoms have dangling bonds, and the dangling bonds may have the property of capturing or fixing hydrogen. By using such a metal oxide having an amorphous structure as a component of the transistor 500 or providing it around the transistor 500, hydrogen contained in the transistor 500 or hydrogen present around the transistor 500 can be captured or fixed. In particular, it is preferable to capture or fix hydrogen contained in the channel formation region of the transistor 500. By using a metal oxide having an amorphous structure as a component of the transistor 500 or providing it around the transistor 500, a highly reliable transistor 500 and semiconductor device can be manufactured with excellent characteristics.

[0414] Furthermore, the insulators 512, 514, 544, 571, 574, 576, and 581 preferably have an amorphous structure, but may have a polycrystalline structure in part. The insulators 512, 514, 544, 571, 574, 576, and 581 may have a multilayer structure in which an amorphous layer and a polycrystalline layer are stacked. For example, they may have a stacked structure in which a polycrystalline layer is formed on an amorphous layer.

[0415] The insulators 512, 514, 544, 571, 574, 576, and 581 can be formed by, for example, a sputtering method. Sputtering does not require the use of molecules containing hydrogen in a film formation gas, and therefore can reduce the hydrogen concentrations of the insulators 512, 514, 544, 571, 574, 576, and 581. Note that the film formation method is not limited to sputtering, and a chemical vapor deposition (CVD) method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, or an atomic layer deposition (ALD) method may also be used as appropriate.

[0416] It may also be preferable to reduce the resistivity of the insulators 512, 544, and 576. For example, it may be preferable to reduce the resistivity of the insulators 512, 544, and 576 to approximately 1×10 13 By setting the resistivity to Ωcm, the insulators 512, 544, and 576 may be able to reduce charge-up of the conductors 503, 542, and 560 in a process using plasma or the like in a semiconductor device manufacturing process. The resistivity of the insulators 512, 544, and 576 is preferably 1×10 10 Ωcm or more 1×10 15 Ωcm or less.

[0417] The insulators 516, 574, 580, and 581 preferably have a lower dielectric constant than the insulator 514. Using a material with a low dielectric constant as an interlayer film can reduce parasitic capacitance between wirings. For example, the insulators 516, 580, and 581 can be made of silicon oxide or silicon oxynitride. For example, the insulators 516, 580, and 581 can be made of silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, or silicon oxide having vacancies.

[0418] For example, the insulator 581 is preferably an insulator that functions as an interlayer film or a planarizing film.

[0419] The conductor 503 is arranged to overlap the oxide 530 and the conductor 560. Here, the conductor 503 is preferably provided by being embedded in an opening formed in the insulator 516. In addition, a part of the conductor 503 may be embedded in the insulator 514.

[0420] The conductor 503 includes a conductor 503a and a conductor 503b. The conductor 503a is provided in contact with the bottom surface and sidewall of the opening. The conductor 503b is provided so as to be embedded in a recess formed in the conductor 503a. Here, the height of the top of the conductor 503b is approximately the same as the height of the top of the conductor 503a and the height of the top of the insulator 516.

[0421] Here, the conductor 503a is preferably made of a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (e.g., NO, NO, and NO), and copper atoms, or that has the function of suppressing the diffusion of oxygen (e.g., one or more selected from oxygen atoms and oxygen molecules).

[0422] By using a conductive material that can reduce hydrogen diffusion for the conductor 503a, impurities such as hydrogen contained in the conductor 503b can be prevented from diffusing into the oxide 530 via the insulator 524. Furthermore, by using a conductive material that can suppress oxygen diffusion for the conductor 503a, it is possible to prevent the conductor 503b from being oxidized and its conductivity from decreasing. Examples of conductive materials that can suppress oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. Therefore, the conductor 503a may be formed as a single layer or a multilayer structure using the above conductive materials. For example, titanium nitride may be used for the conductor 503a.

[0423] The conductor 503b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component, for example, tungsten.

[0424] The conductor 503 may function as a second gate electrode. In this case, the threshold voltage (Vth) of the transistor 500 can be controlled by changing the potential applied to the conductor 503 independently of the potential applied to the conductor 560. In particular, applying a negative potential to the conductor 503 can increase the Vth of the transistor 500 and reduce its off-state current. Therefore, applying a negative potential to the conductor 503 can reduce the drain current when the potential applied to the conductor 560 is 0 V compared to not applying a negative potential to the conductor 503.

[0425] Note that if the oxide 530 is highly pure and intrinsic, and impurities are removed as much as possible from the oxide 530, it may be possible to make the transistor 500 normally off (to make the threshold voltage of the transistor 500 higher than 0 V) ​​without applying a potential to one or both of the conductor 503 and the conductor 560. In this case, it is preferable to connect the conductor 560 and the conductor 503 so that the same potential is applied to them.

[0426] The electrical resistivity of the conductor 503 is designed taking into consideration the potential applied to the conductor 503, and the film thickness of the conductor 503 is set to match this electrical resistivity. The film thickness of the insulator 516 is approximately the same as that of the conductor 503. Here, it is preferable to make the film thicknesses of the conductor 503 and the insulator 516 as thin as possible within the range permitted by the design of the conductor 503. By making the film thickness of the insulator 516 thin, the absolute amount of impurities such as hydrogen contained in the insulator 516 can be reduced, thereby reducing the diffusion of the impurities into the oxide 530.

[0427] Note that the conductor 503 is preferably larger than the area of ​​the oxide 530 that does not overlap with the conductors 542a and 542b when viewed from above. In particular, as shown in FIG. 20B , the conductor 503 preferably extends to an area outside the channel width direction ends of the oxides 530a and 530b. That is, outside the side surfaces of the oxide 530 in the channel width direction, the conductor 503 and the conductor 560 preferably overlap with each other via an insulator. With this structure, the channel formation region of the oxide 530 can be electrically surrounded by the electric field of the conductor 560, which functions as the first gate electrode, and the electric field of the conductor 503, which functions as the second gate electrode. In this specification, a transistor structure in which the channel formation region is electrically surrounded by the electric fields of the first and second gates is referred to as a surrounded channel (S-channel) structure.

[0428] In this specification and the like, a transistor with an S-channel structure refers to a transistor structure in which a channel formation region is electrically surrounded by the electric fields of one and the other of a pair of gate electrodes. The S-channel structure disclosed in this specification and the like differs from a fin structure and a planar structure. By adopting the S-channel structure, the transistor can be made more resistant to the short-channel effect, in other words, less susceptible to the short-channel effect.

[0429] By configuring the transistor 500 as a normally-off transistor and adopting the above-described S-Channel structure, the channel formation region can be electrically surrounded. Therefore, the transistor 500 can also be considered to have a GAA (Gate All Around) structure or an LGAA (Lateral Gate All Around) structure. By configuring the transistor 500 as an S-Channel structure, a GAA structure, or an LGAA structure, the channel formation region formed at or near the interface between the oxide 530 and the gate insulating film can be the entire bulk of the oxide 530. In other words, by configuring the transistor 500 as an S-Channel structure, a GAA structure, or an LGAA structure, the entire bulk can be used as a carrier path, making it a so-called bulk-flow type. The bulk-flow type transistor structure can increase the current density flowing through the transistor, which is expected to improve the on-state current or field-effect mobility of the transistor.

[0430] 20B, the conductor 503 is extended to function as a wiring. However, the present invention is not limited to this, and a conductor functioning as a wiring may be provided below the conductor 503. Furthermore, it is not necessary to provide one conductor 503 for each transistor. For example, the conductor 503 may be shared by multiple transistors.

[0431] Note that although the conductor 503 in the transistor 500 has a stacked structure of the conductor 503a and the conductor 503b, the present invention is not limited to this. For example, the conductor 503 may have a single layer structure or a stacked structure of three or more layers.

[0432] Insulator 522 and insulator 524 function as gate insulators.

[0433] The insulator 522 preferably has a function of suppressing the diffusion of hydrogen (e.g., hydrogen atoms and / or hydrogen molecules). The insulator 522 preferably has a function of suppressing the diffusion of oxygen (e.g., oxygen atoms and / or oxygen molecules). For example, the insulator 522 preferably has a function of suppressing the diffusion of hydrogen and / or oxygen more than the insulator 524.

[0434] The insulator 522 may be an insulator containing an oxide of one or both of aluminum and hafnium, which are insulating materials. Aluminum oxide, hafnium oxide, and an oxide containing aluminum and hafnium (hafnium aluminate) are preferably used as the insulator. When the insulator 522 is formed using such a material, the insulator 522 functions as a layer that suppresses oxygen release from the oxide 530 to the substrate and the diffusion of impurities such as hydrogen from the periphery of the transistor 500 to the oxide 530. Therefore, the insulator 522 can suppress the diffusion of impurities such as hydrogen into the transistor 500 and the generation of oxygen vacancies in the oxide 530. Furthermore, the conductor 503 can be prevented from reacting with oxygen contained in the insulator 524 or the oxide 530.

[0435] Alternatively, the insulator may contain, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide. Alternatively, these insulators may be nitrided. Furthermore, the insulator 522 may be formed by stacking silicon oxide, silicon oxynitride, or silicon nitride on these insulators.

[0436] The insulator 522 may be a single layer or a multilayer of an insulator containing a so-called high-k material, such as aluminum oxide, hafnium oxide, tantalum oxide, or zirconium oxide. As transistors become smaller and more highly integrated, thinning of the gate insulator can lead to problems such as leakage current. Using a high-k material as the gate insulator can reduce the gate potential during transistor operation while maintaining the physical film thickness. The insulator 522 may also be made of a material with a high dielectric constant, such as lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST).

[0437] The insulator 524 in contact with the oxide 530 can be formed using, for example, silicon oxide or silicon oxynitride as appropriate.

[0438] During the manufacturing process of the transistor 500, heat treatment is preferably performed with the surface of the oxide 530 exposed. The heat treatment may be performed, for example, at a temperature of 100° C. to 600° C., more preferably 350° C. to 550° C. Note that the heat treatment is performed in a nitrogen gas or inert gas atmosphere, or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. For example, the heat treatment is preferably performed in an oxygen atmosphere. This supplies oxygen to the oxide 530, thereby eliminating oxygen vacancies (V O ) can be reduced. The heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas after the heat treatment in a nitrogen gas or inert gas atmosphere to compensate for the desorbed oxygen. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas, and then the heat treatment may be performed in a nitrogen gas or inert gas atmosphere.

[0439] By subjecting the oxide 530 to oxygen addition treatment, oxygen vacancies in the oxide 530 are repaired by the supplied oxygen. In other words, OFurthermore, the reaction of the hydrogen remaining in the oxide 530 with the supplied oxygen can be removed as HO (dehydration). As a result, the hydrogen remaining in the oxide 530 recombines with the oxygen vacancies to form V O The formation of H can be suppressed.

[0440] The insulators 522 and 524 may each have a stacked structure of two or more layers. In this case, the stacked structure is not limited to a stacked structure made of the same material, and may be a stacked structure made of different materials. The insulator 524 may be formed in an island shape overlapping the oxide 530a. In this case, the insulator 544 is configured to contact the side surface of the insulator 524 and the top surface of the insulator 522.

[0441] The conductor 542a and the conductor 542b are provided in contact with the top surface of the oxide 530b. The conductor 542a and the conductor 542b function as a source electrode and a drain electrode of the transistor 500, respectively.

[0442] As the conductor 542 (conductor 542a and conductor 542b), for example, a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, or a nitride containing titanium and aluminum is preferably used. In one embodiment of the present invention, a nitride containing tantalum is particularly preferable. Also, for example, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel may be used. These materials are preferable because they are conductive materials that are resistant to oxidation or materials that maintain conductivity even when absorbing oxygen.

[0443] Note that hydrogen contained in the oxide 530b and the like may diffuse into the conductor 542a or the conductor 542b. In particular, by using a nitride containing tantalum for the conductors 542a and 542b, the hydrogen contained in the oxide 530b is likely to diffuse into the conductor 542a or the conductor 542b, and the diffused hydrogen may bond with nitrogen contained in the conductor 542a or the conductor 542b. In other words, the hydrogen contained in the oxide 530b and the like may be absorbed by the conductor 542a or the conductor 542b.

[0444] Furthermore, it is preferable that no curved surface be formed between the side surface of the conductor 542 and the top surface of the conductor 542. The conductor 542 without such a curved surface can increase the cross-sectional area of ​​the conductor 542 in the cross section in the channel width direction. This can increase the conductivity of the conductor 542 and the on-state current of the transistor 500.

[0445] The insulator 571a is provided in contact with the top surface of the conductor 542a, and the insulator 571b is provided in contact with the top surface of the conductor 542b. The insulator 571 preferably functions as a barrier insulating film against oxygen. Therefore, the insulator 571 preferably has a function of suppressing oxygen diffusion. For example, the insulator 571 preferably has a function of suppressing oxygen diffusion more than the insulator 580. For example, a nitride containing silicon, such as silicon nitride, may be used as the insulator 571. The insulator 571 preferably has a function of capturing impurities such as hydrogen. In this case, the insulator 571 may be an insulator of a metal oxide having an amorphous structure, such as aluminum oxide or magnesium oxide. In particular, using aluminum oxide having an amorphous structure or aluminum oxide having an amorphous structure as the insulator 571 is preferable because hydrogen can be more effectively captured or fixed. This enables the manufacture of a highly reliable transistor 500 and a semiconductor device with favorable characteristics.

[0446] The insulator 544 is provided to cover the insulator 524, the oxide 530a, the oxide 530b, the conductor 542, and the insulator 571. The insulator 544 preferably has a function of capturing and fixing hydrogen. In this case, the insulator 544 preferably includes an insulator such as silicon nitride or a metal oxide having an amorphous structure, such as aluminum oxide or magnesium oxide. Alternatively, for example, the insulator 544 may be a stacked film of aluminum oxide and silicon nitride on the aluminum oxide.

[0447] By providing the insulator 571 and the insulator 544 as described above, the conductor 542 can be surrounded by an insulator having a barrier property against oxygen. That is, oxygen contained in the insulators 524 and 580 can be prevented from diffusing into the conductor 542. This can prevent the conductor 542 from being directly oxidized by the oxygen contained in the insulators 524 and 580, which increases the resistivity and reduces the on-state current.

[0448] The insulator 552 functions as part of the gate insulator. The insulator 552 is preferably a barrier insulating film against oxygen. Any of the insulators that can be used for the insulator 574 may be used as the insulator 552. The insulator 552 may contain an oxide of one or both of aluminum and hafnium. Examples of the insulator include aluminum oxide, hafnium oxide, and oxides containing aluminum and hafnium (hafnium aluminate), such as oxides containing hafnium and silicon (hafnium silicate). In this embodiment, aluminum oxide is used as the insulator 552. In this case, the insulator 552 contains at least oxygen and aluminum.

[0449] As shown in FIG. 20B, the insulator 552 is provided in contact with the top surface and side surfaces of the oxide 530b, the side surfaces of the oxide 530a, the side surfaces of the insulator 524, and the top surface of the insulator 522. That is, the regions of the oxide 530a, the oxide 530b, and the insulator 524 that overlap with the conductor 560 are covered with the insulator 552 in the cross section in the channel width direction. This allows the insulator 552, which has oxygen barrier properties, to block oxygen from being released from the oxides 530a and 530b during heat treatment or the like. This reduces the formation of oxygen vacancies (Vo) in the oxides 530a and 530b. This reduces the oxygen vacancies (Vo) and V formed in the region 530bc. O H can be reduced. Therefore, the electrical characteristics of the transistor 500 can be improved, and the reliability can be improved.

[0450] Conversely, even if the insulator 580, the insulator 550, or the like contains excessive amounts of oxygen, the oxygen can be prevented from being excessively supplied to the oxide 530a and the oxide 530b. Therefore, the region 530bc can prevent the regions 530ba and 530bb from being excessively oxidized, which would cause a decrease in the on-state current or the field-effect mobility of the transistor 500.

[0451] 20A , the insulator 552 is provided in contact with the side surfaces of the conductor 542, the insulator 544, the insulator 571, and the insulator 580. This reduces the oxidation of the side surface of the conductor 542 and the formation of an oxide film on the side surface. This reduces the on-state current or field-effect mobility of the transistor 500.

[0452] The insulator 552, together with the insulator 554, the insulator 550, and the conductor 560, needs to be provided in an opening formed in the insulator 580 or the like. To miniaturize the transistor 500, the insulator 552 preferably has a small thickness. The thickness of the insulator 552 is preferably 0.1 nm or more, 0.5 nm or more, or 1.0 nm or more, and preferably 1.0 nm or less, 3.0 nm or less, or 5.0 nm or less. Note that the above-described lower and upper limits can be combined. In this case, the insulator 552 only needs to have at least a region with the above-described thickness. The thickness of the insulator 552 is preferably thinner than the thickness of the insulator 550. In this case, the insulator 552 only needs to have at least a region with a thickness thinner than the insulator 550.

[0453] To deposit the insulator 552 to a thin thickness as described above, it is preferable to use the ALD method. The ALD method alternately introduces a first source gas (e.g., a precursor, or a metal precursor) and a second source gas (e.g., a reactant, an oxidizer, or a non-metal precursor) for a reaction into a chamber, and repeats the introduction of these source gases to deposit the film. ALD methods include thermal ALD, in which the reaction between the precursor and the reactant is carried out using only thermal energy, and PEALD (Plasma Enhanced ALD), which uses a plasma-excited reactant. The PEALD method may be preferable because it utilizes plasma, enabling film deposition at lower temperatures.

[0454] The ALD method utilizes the self-regulating property of atoms to deposit atoms layer by layer, and therefore has the following advantages: it is possible to form an extremely thin film, it is possible to form a film on a structure with a high aspect ratio, it is possible to form a film with few defects such as pinholes, it is possible to form a film with excellent coverage, and it is possible to form a film at a low temperature. Therefore, the insulator 552 can be formed on the side surface of the opening formed in the insulator 580 with good coverage and with the thin film thickness described above.

[0455] Some precursors used in ALD contain carbon. Therefore, films formed by ALD may contain more impurities such as carbon than films formed by other film formation methods. Quantitative determination of impurities can be performed using secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectroscopy (XPS).

[0456] The insulator 550 functions as part of the gate insulator. The insulator 550 is preferably disposed in contact with the upper surface of the insulator 552. For example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, and silicon oxide having vacancies can be used for the insulator 550. Silicon oxide and silicon oxynitride are particularly preferred because they are stable against heat. In this case, the insulator 550 is an insulator containing at least oxygen and silicon.

[0457] Like the insulator 524, the insulator 550 preferably has a reduced concentration of impurities such as water and hydrogen. The thickness of the insulator 550 preferably has a lower limit of 1 nm or 0.5 nm and an upper limit of 15 nm or 20 nm. Note that the above-mentioned lower and upper limits can be combined. For example, the thickness of the insulator 550 is preferably 0.5 nm or more and 20 nm or less, and more preferably 1 nm or more and 15 nm or less. In this case, the insulator 550 only needs to have a region with the above-mentioned thickness in at least a portion thereof.

[0458] 20A and 20B show a configuration in which the insulator 550 is a single layer, but the present invention is not limited to this and the insulator 550 may have a laminated structure of two or more layers. For example, as shown in FIG. 21B, the insulator 550 may have a two-layer laminated structure of an insulator 550a and an insulator 550b on the insulator 550a.

[0459] As shown in FIG. 21B , when the insulator 550 has a two-layer stacked structure, the lower insulator 550a is preferably formed using an insulator that easily transmits oxygen, and the upper insulator 550b is preferably formed using an insulator that suppresses oxygen diffusion. This structure can suppress the oxygen contained in the insulator 550a from diffusing into the conductor 560. That is, it can suppress a decrease in the amount of oxygen supplied to the oxide 530. It can also suppress oxidation of the conductor 560 due to the oxygen contained in the insulator 550a. For example, the insulator 550a may be formed using a material that can be used for the insulator 550 described above, and the insulator 550b may be formed using an insulator containing an oxide of one or both of aluminum and hafnium. Examples of such insulators include aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), and an oxide containing hafnium and silicon (hafnium silicate). In this embodiment, hafnium oxide is used as the insulator 550b. In this case, the insulator 550b contains at least oxygen and hafnium. The thickness of the insulator 550b is preferably 0.5 nm or more, or 1.0 nm or more, and preferably 3.0 nm or less, or 5.0 nm or less. The above-mentioned lower and upper limits can be combined. In this case, the insulator 550b only needs to have a region with the above-mentioned thickness in at least a portion.

[0460] When silicon oxide and silicon oxynitride are used for the insulator 550a, the insulator 550b may be made of an insulating material, such as a high-k material with a high dielectric constant. By forming the gate insulator with a layered structure of the insulators 550a and 550b, a thermally stable layered structure with a high dielectric constant can be achieved. This allows the gate potential applied during transistor operation to be reduced while maintaining the physical thickness of the gate insulator. Furthermore, the equivalent oxide thickness (EOT) of the insulator functioning as the gate insulator can be reduced. This allows the dielectric strength of the insulator 550 to be increased.

[0461] The insulator 554 functions as part of the gate insulator. A barrier insulating film against hydrogen is preferably used as the insulator 554. This can prevent impurities such as hydrogen contained in the conductor 560 from diffusing into the insulator 550 and the oxide 530b. The insulator 554 can be any of the insulators that can be used for the insulator 576. For example, silicon nitride formed by a PEALD method can be used as the insulator 554. In this case, the insulator 554 contains at least nitrogen and silicon.

[0462] The insulator 554 may further have a barrier property against oxygen, which can prevent oxygen contained in the insulator 550 from diffusing into the conductor 560.

[0463] The insulator 554, together with the insulator 552, the insulator 550, and the conductor 560, needs to be provided in an opening formed in the insulator 580 or the like. To miniaturize the transistor 500, the insulator 554 preferably has a small thickness. The thickness of the insulator 554 is preferably 0.1 nm or more, 0.5 nm or more, or 1.0 nm or more, and preferably 3.0 nm or less, or 5.0 nm or less. Note that the above-described lower and upper limits can be combined. In this case, the insulator 554 only needs to have at least a region with the above-described thickness. The thickness of the insulator 554 is preferably thinner than the thickness of the insulator 550. In this case, the insulator 554 only needs to have at least a region with a thickness thinner than the insulator 550.

[0464] The conductor 560 functions as a first gate electrode of the transistor 500. The conductor 560 preferably includes a conductor 560a and a conductor 560b disposed over the conductor 560a. For example, the conductor 560a is preferably disposed so as to surround the bottom and side surfaces of the conductor 560b. As shown in FIGS. 20A and 20B, the height of the top surface of the conductor 560 roughly coincides with the height of the top of the insulator 550. Note that although the conductor 560 is shown as having a two-layer structure of the conductor 560a and the conductor 560b in FIGS. 20A and 20B, the conductor 560 may have a single-layer structure or a stacked structure of three or more layers, other than the two-layer structure.

[0465] The conductor 560a is preferably made of a conductive material that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, and copper atoms, or that has a function of suppressing the diffusion of oxygen (e.g., oxygen atoms and / or oxygen molecules).

[0466] Furthermore, since the conductor 560a has the function of suppressing oxygen diffusion, it is possible to suppress a decrease in conductivity due to oxidation of the conductor 560b caused by oxygen contained in the insulator 550. As the conductive material having the function of suppressing oxygen diffusion, it is preferable to use, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, or ruthenium oxide.

[0467] Furthermore, since the conductor 560 also functions as wiring, it is preferable to use a conductor with high conductivity. For example, the conductor 560b can be made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductor 560b can have a layered structure. Specifically, for example, the conductor 560b can have a layered structure of titanium or titanium nitride and the above-mentioned conductive material.

[0468] Furthermore, in the transistor 500, the conductor 560 is formed in a self-aligned manner so as to fill the opening formed in the insulator 580. By forming the conductor 560 in this manner, the conductor 560 can be reliably placed in the region between the conductor 542a and the conductor 542b without alignment.

[0469] 20B , in the channel width direction of the transistor 500, the height of the bottom surface of the conductor 560 in a region where the conductor 560 does not overlap with the oxide 530b is preferably lower than the height of the bottom surface of the oxide 530b when the bottom surface of the insulator 522 is used as the reference. When the conductor 560, which functions as a gate electrode, covers the side and top surfaces of the channel formation region of the oxide 530b via the insulator 550 or the like, the electric field of the conductor 560 can be easily applied to the entire channel formation region of the oxide 530b. Therefore, the on-state current of the transistor 500 can be increased, and the frequency characteristics can be improved. The difference between the height of the bottom surface of conductor 560 and the height of the bottom surface of oxide 530b in the region where oxide 530a and oxide 530b do not overlap with conductor 560, relative to the bottom surface of insulator 522, is preferably 0 nm or more, 3 nm or more, or 5 nm or more, and is preferably 20 nm or less, 50 nm or less, or 100 nm or less. Note that the above-mentioned lower limit and upper limit values ​​can be combined with each other.

[0470] The insulator 580 is provided on the insulator 544, and openings are formed in the regions where the insulator 550 and the conductor 560 are provided. The top surface of the insulator 580 may be planarized.

[0471] The insulator 580, which functions as an interlayer film, preferably has a low dielectric constant. Using a material with a low dielectric constant as the interlayer film can reduce parasitic capacitance between wirings. The insulator 580 is preferably formed using, for example, the same material as the insulator 516. In particular, silicon oxide and silicon oxynitride are preferable because they are thermally stable. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide with vacancies are preferable because they can easily form a region containing oxygen that is released by heating.

[0472] The insulator 580 preferably has a reduced concentration of impurities such as water and hydrogen. For example, the insulator 580 may be formed using an oxide containing silicon, such as silicon oxide or silicon oxynitride, as appropriate.

[0473] The insulator 574 preferably functions as a barrier insulating film that suppresses diffusion of impurities such as water and hydrogen from above into the insulator 580 and preferably has a function of capturing impurities such as hydrogen. The insulator 574 also preferably functions as a barrier insulating film that suppresses oxygen permeation. The insulator 574 may be an insulator made of a metal oxide having an amorphous structure, such as aluminum oxide. In this case, the insulator 574 contains at least oxygen and aluminum. By providing the insulator 574, which is in contact with the insulator 580 and has a function of capturing impurities such as hydrogen, in the region between the insulators 512 and 581, the insulator 574 can capture impurities such as hydrogen contained in the insulator 580 and maintain a constant amount of hydrogen in the region. In particular, using aluminum oxide having an amorphous structure as the insulator 574 is preferable because it may be able to more effectively capture or fix hydrogen. This enables the manufacture of a highly reliable transistor 500 and semiconductor device with excellent characteristics.

[0474] The insulator 576 functions as a barrier insulating film that suppresses diffusion of impurities such as water and hydrogen from above into the insulator 580. The insulator 576 is disposed over the insulator 574. The insulator 576 is preferably a nitride containing silicon, such as silicon nitride or silicon nitride oxide. For example, the insulator 576 may be a silicon nitride film formed by a sputtering method. A high-density silicon nitride film can be formed by depositing the insulator 576 by a sputtering method. Alternatively, the insulator 576 may be formed by stacking a silicon nitride film formed by a PEALD method or a CVD method on the silicon nitride film formed by a sputtering method.

[0475] One of the first and second terminals of the transistor 500 is electrically connected to a conductor 540a functioning as a plug, and the other of the first and second terminals of the transistor 500 is electrically connected to a conductor 540b. Note that the conductors 540a and 540b may function as wirings for electrically connecting to an upper light-emitting device 150 or the like. In the case of the display device 100 of FIG. 19, the conductors 540a and 540b may also function as wirings for electrically connecting to the transistor 300. Note that in this specification and the like, the conductors 540a and 540b are collectively referred to as conductors 540.

[0476] For example, conductor 540a is provided in a region overlapping with conductor 542a. Specifically, in the region overlapping with conductor 542a, openings are formed in insulators 571, 544, 580, 574, 576, and 581 shown in FIG. 20A , and conductor 540a is provided inside the openings. For example, conductor 540b is provided in a region overlapping with conductor 542b. Specifically, in the region overlapping with conductor 542b, openings are formed in insulators 571, 544, 580, 574, 576, and 581 shown in FIG. 20A , and conductor 540b is provided inside the openings.

[0477] 20A, an insulator 541a may be provided as an insulator having a barrier property against impurities between the conductor 540a and a side surface of the opening in a region overlapping with the conductor 542a. Similarly, an insulator 541b may be provided as an insulator having a barrier property against impurities between the conductor 540b and a side surface of the opening in a region overlapping with the conductor 542b. Note that in this specification and the like, the insulators 541a and 541b are collectively referred to as the insulator 541.

[0478] The conductors 540a and 540b are preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductors 540a and 540b may have a layered structure.

[0479] Furthermore, when the conductor 540 has a layered structure, it is preferable to use a conductive material that has a function of suppressing the permeation of impurities such as water or hydrogen for the insulators 574, 576, 581, 580, 544, and the first conductor disposed near the insulator 571. Examples of such conductive materials include tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, and ruthenium oxide. Furthermore, the conductive material that has a function of suppressing the permeation of impurities such as water and hydrogen may be used in a single layer or a layered structure. Furthermore, impurities such as water and hydrogen contained in layers above the insulator 576 can be prevented from being mixed into the oxide 530 through the conductors 540a and 540b.

[0480] The insulators 541a and 541b can be, for example, a barrier insulating film that can be used for the insulator 544. For example, the insulators 541a and 541b can be made of an insulator such as silicon nitride, aluminum oxide, or silicon nitride oxide. The insulators 541a and 541b are provided in contact with the insulators 574, 576, and 571, and thus can prevent impurities such as water and hydrogen contained in the insulator 580 from entering the oxide 530 through the conductors 540a and 540b. Silicon nitride is particularly suitable because it has a high blocking property against hydrogen. Furthermore, oxygen contained in the insulator 580 can be prevented from being absorbed by the conductors 540a and 540b.

[0481] When the insulators 541a and 541b are formed into a layered structure as shown in FIG. 20A, it is preferable that the first insulator in contact with the inner wall of the opening, such as the insulator 580, and the second insulator inside it are formed by combining a barrier insulating film against oxygen and a barrier insulating film against hydrogen.

[0482] For example, the first insulator may be made of aluminum oxide deposited by the ALD method, and the second insulator may be made of silicon nitride deposited by the PEALD method. This structure can suppress oxidation of the conductor 540 and reduce hydrogen contamination of the conductor 540.

[0483] Although the transistor 500 has a structure in which the first insulator of the insulator 541 and the second conductor of the insulator 541 are stacked, the present invention is not limited to this. For example, the insulator 541 may be provided as a single layer or a stacked structure of three or more layers. Furthermore, the transistor 500 has a structure in which the first conductor of the conductor 540 and the second conductor of the conductor 540 are stacked, but the present invention is not limited to this. For example, the conductor 540 may be provided as a single layer or a stacked structure of three or more layers.

[0484] Note that the structure of the transistor included in the semiconductor device of one embodiment of the present invention is not limited to the transistor 500 illustrated in Figures 20A and 20B. The structure of the transistor included in the semiconductor device of one embodiment of the present invention may be changed depending on the situation.

[0485] <Example of sealing structure for display device> Next, a sealing structure for the light emitting device 150 that can be applied to the display device 100 of FIG. 17 will be described.

[0486] Fig. 22A is a cross-sectional view showing an example of a sealing structure applicable to the display device 100 of Fig. 17. Specifically, Fig. 22A illustrates an edge of the pixel array ALP of the display device 100 of Fig. 17 and materials provided around the edge. Fig. 22A also illustrates an excerpt of only a portion of the pixel layer PXAL of the display device 100. Specifically, Fig. 22A illustrates the insulator 111, the plug connected to the transistor 200, as well as the insulator, conductor, and light-emitting device 150a located above the insulator 111.

[0487] 22A also shows a conductor 121CM that functions as a connection electrode. The connection electrode has a function of supplying a potential (for example, an anode potential or a cathode potential in the light-emitting device 150a) to the conductor 122 that functions as a common electrode. Note that the conductor 121CM can be made of a material that can be used for the conductor 121a or the conductor 121b. Furthermore, when a material that can be used for the conductor 121CM is used for the conductor 121CM, the conductor 121CM can be formed simultaneously with one or both of the conductor 121a and the conductor 121b.

[0488] 22A, an adhesive layer 164 is provided at or around an end of the pixel array ALP. Specifically, the display device 100 is configured so that the adhesive layer 164 is interposed between the insulator 111 and the substrate 102.

[0489] The adhesive layer 164 is preferably made of a material that suppresses the permeation of impurities such as moisture. By using such a material for the adhesive layer 164, the reliability of the display device 100 can be improved.

[0490] A structure in which the insulator 111 and the substrate 102 are bonded together via the resin layer 161 using the adhesive layer 164 is sometimes called a solid sealing structure. In addition, in the solid sealing structure, if the resin layer 161 has the function of bonding the insulator 111 and the substrate 102 together, similar to the adhesive layer 164, the adhesive layer 164 does not necessarily have to be provided.

[0491] On the other hand, a structure in which the insulator 111 and the substrate 102 are bonded together using the adhesive layer 164 and filled with an inert gas instead of the resin layer 161 is sometimes called a hollow sealing structure (not shown). Examples of the inert gas include nitrogen and argon.

[0492] 22A, two or more adhesive layers may be stacked. For example, as shown in FIG. 22B, an adhesive layer 165 may be further provided inside adhesive layer 164 (between adhesive layer 164 and resin layer 161). By stacking two or more adhesive layers, the permeation of impurities such as moisture can be further suppressed, thereby further improving the reliability of display device 100.

[0493] A desiccant may be mixed into the adhesive layer 165. This allows the desiccant to adsorb moisture contained in the adhesive layer 164, the resin layer 161 formed inside the adhesive layer 165, the insulator, the conductor, the EL layer, and the like, thereby improving the reliability of the display device 100.

[0494] Furthermore, although the display device 100 in FIG. 22B has a solid sealing structure, it may also have a hollow sealing structure.

[0495] 22A and 22B, an inert liquid may be filled in place of the resin layer 161. Examples of the inert liquid include a fluorine-based inert liquid.

[0496] <Modifications of the display device> However, one embodiment of the present invention is not limited to the above-described configuration, and the above-described configuration can be modified as appropriate depending on the situation. Modifications of the display device 100 in FIG. 17 will be described below with reference to FIGS. 23A to 25B. Note that FIGS. 23A to 25B illustrate only a portion of the pixel layer PXAL of the display device 100. Specifically, each of FIGS. 23A to 25B illustrates the insulator 111, the plug connected to the transistor 500, the insulator, the conductor, the light-emitting device 150a, and the light-emitting device 150b located above the insulator 111, and the light-emitting device 150c, the conductor 121c, and the EL layer 141c.

[0497] For example, the color of light emitted by the EL layer 141c may be different from the colors of light emitted by the EL layer 141a and the EL layer 141b. Furthermore, for example, the display device 100 may be configured so that the light-emitting devices 150a to 150c emit light of two colors. Furthermore, for example, the display device 100 may be configured so that the number of light-emitting devices 150 is increased to four or more colors (not shown).

[0498] 23A, the display device 100 may be configured so that the EL layers 141a to 141c are not provided on the insulator 111. That is, the EL layers 141a to 141c may be provided only in a partial region that overlaps with the conductors 121a to 121c. In other words, the region where the EL layers 141a to 141c are formed may be smaller than the region where the conductors 121a to 121c are formed.

[0499] 23B, the display device 100 may be configured such that an insulator 114 is provided between each of the conductors 121a, 121b, and 121c, which correspond to one of the pair of electrodes of the light-emitting devices. The insulator 114 is preferably made of a material that fills and flattens the recess between one of the pair of electrodes of adjacent light-emitting devices.

[0500] The insulator 114 can be, for example, an inorganic insulating film such as an insulating oxide film, a nitride insulating film, an oxynitride insulating film, or a nitride oxide insulating film. The insulator 114 can have a single-layer structure or a stacked-layer structure. Examples of the oxide insulating film include a silicon oxide film, an aluminum oxide film, a magnesium oxide film, an indium gallium zinc oxide film, a gallium oxide film, a germanium oxide film, an yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, and a tantalum oxide film. Examples of the nitride insulating film include a silicon nitride film and an aluminum nitride film. Examples of the oxynitride insulating film include a silicon oxynitride film and an aluminum oxynitride film. Examples of the nitride oxide insulating film include a silicon nitride oxide film and an aluminum nitride oxide film. The above-mentioned materials can be formed by, for example, a sputtering method, a CVD method, a PLD method, or an ALD method.

[0501] Alternatively, the insulator 114 may be made of, for example, an organic material. Examples of the organic material include acrylic resin, polyimide resin, epoxy resin, imide resin, polyamide resin, polyimideamide resin, silicone resin, siloxane resin, benzocyclobutene-based resin, phenol resin, and precursors of these resins. Alternatively, the insulator 114 may be made of an organic material such as polyvinyl alcohol (PVA), polyvinyl butyral, polyvinylpyrrolidone, polyethylene glycol, polyglycerin, pullulan, water-soluble cellulose, or alcohol-soluble polyamide resin. Alternatively, the insulator 114 may be made of a photosensitive resin. Examples of the photosensitive resin include photoresist. Examples of the photosensitive resin include positive-type materials and negative-type materials.

[0502] Note that the ends of conductor 121a, conductor 121b, and conductor 121c shown in FIG. 23B are steeper than those of conductor 121a, conductor 121b, and conductor 121c shown in FIG. 17, but may have a slope similar to that of conductor 121a, conductor 121b, and conductor 121c shown in FIG. 17.

[0503] 23C, the display device 100 may have an EL layer 142 formed on the EL layers 141a to 141c. Specifically, for example, in FIG. 18A, if the EL layers 141a to 141c include the layer 4430 and the light-emitting layer 4411, the EL layer 142 may include the layer 4420. In this case, the layer 4420 included in the EL layer 142 functions as a common layer for the light-emitting devices 150a to 150c. Similarly, in FIG. 18C, if the EL layers 141a to 141c include the layer 4430, the light-emitting layer 4411, the light-emitting layer 4412, and the light-emitting layer 4413, the EL layer 142 may include the layer 4420, so that the layer 4420 included in the EL layer 142 functions as a common layer for the light-emitting devices 150a to 150c. Furthermore, for example, in FIG. 18D, when the EL layers 141a to 141c are configured to include the layer 4430, the light-emitting layer 4412, and the layer 4420 of the light-emitting unit 4400b, the intermediate layer 4440, and the layer 4430 and the light-emitting layer 4411 of the light-emitting unit 4400a, the EL layer 142 is configured to include the layer 4420 of the light-emitting unit 4400b, so that the layer 4420 of the light-emitting unit 4400a included in the EL layer 142 functions as a common layer in each of the light-emitting devices 150a to 150c.

[0504] Furthermore, for example, in the configuration of display device 100, insulator 113 may have a stacked structure of two or more layers instead of a single layer. Insulator 113 may have a three-layer stacked structure, for example, in which an inorganic insulator is used as a first layer, an organic insulator is used as a second layer, and an inorganic insulator is used as a third layer. Fig. 23D shows a cross-sectional view of a portion of display device 100 in which insulator 113 has a multi-layer structure including insulators 113a, 113b, and 113c, in which insulator 113a is an inorganic insulator, insulator 113b is an organic insulator, and insulator 113c is an inorganic insulator.

[0505] Furthermore, for example, the display device 100 may be configured such that each of the EL layers 141a to 141c has a microcavity structure (a microresonator structure). The microcavity structure refers to a structure in which, for example, a light-transmitting and light-reflective conductive material is used for the conductor 122 that is the upper electrode (common electrode), a light-reflective conductive material is used for the conductor 121 that is the lower electrode (pixel electrode), and the distance between the lower surface of the light-emitting layer and the upper surface of the lower electrode, that is, the film thickness of the layer 4430 in FIG. 18A, is set to a thickness corresponding to the wavelength of the color of light emitted by the light-emitting layer included in the EL layer 141.

[0506] For example, light reflected by the lower electrode and returning (reflected light) significantly interferes with light directly incident on the upper electrode from the light-emitting layer (incident light). Therefore, it is preferable to adjust the optical distance between the lower electrode and the light-emitting layer to (2n-1)λ / 4 (where n is a natural number greater than or equal to 1, and λ is the wavelength of the emitted light to be amplified). By adjusting this optical distance, the phases of the reflected light and incident light, each of which has a wavelength λ, can be matched, thereby further amplifying the light emitted from the light-emitting layer. On the other hand, if the reflected light and incident light have a wavelength other than λ, they will no longer match in phase, resulting in attenuation without resonance.

[0507] In the above configuration, the EL layer may have a structure having multiple light-emitting layers or a structure having a single light-emitting layer. Furthermore, for example, in combination with the above-described tandem light-emitting device configuration, a single light-emitting device may be provided with multiple EL layers sandwiching a charge-generating layer, and each EL layer may have a single or multiple light-emitting layers.

[0508] The microcavity structure makes it possible to increase the light emission intensity of a specific wavelength in the front direction, thereby reducing power consumption. In particular, in the case of XR devices such as VR and AR, light from the light-emitting device is often incident on the eyes of the user wearing the device in the front direction, so it can be said that providing a microcavity structure in the display device of XR devices is preferable. In addition, in the case of a display device that displays images using four sub-pixels of red, yellow, green, and blue, in addition to the brightness improvement effect of yellow emission, the ability to apply a microcavity structure tailored to the wavelength of each color to all sub-pixels can result in a display device with good characteristics.

[0509] FIG. 24A shows a cross-sectional view of a portion of the display device 100 having a microcavity structure, as an example. When the light-emitting device 150a has a light-emitting layer that emits blue (B), the light-emitting device 150b has a light-emitting layer that emits green (G), and the light-emitting device 150c has a light-emitting layer that emits red (R), it is preferable to increase the thickness of the EL layer 141a, the EL layer 141b, and the EL layer 141c in that order, as shown in FIG. 24A. Specifically, the thickness of the layer 4430 included in each of the EL layers 141a, 141b, and 141c can be determined according to the color of the light emitted by each light-emitting layer. In this case, the layer 4430 included in the EL layer 141a is the thinnest, and the layer 4430 included in the EL layer 141c is the thickest.

[0510] 24B shows, as an example, a configuration in which colored layers 162a, 162b, and 162c are provided between the resin layer 161 and the substrate 102. The colored layers 162a to 162c can be formed on the substrate 102. In addition, when the light-emitting device 150a has a light-emitting layer that emits blue (B), the light-emitting device 150b has a light-emitting layer that emits green (G), and the light-emitting device 150c has a light-emitting layer that emits red (R), the colored layer 162a is blue, the colored layer 162b is green, and the colored layer 162c is red.

[0511] 24B can be constructed by bonding a substrate 102 provided with colored layers 162a to 162c to a substrate 310 on which light-emitting devices 150a to 150c have been formed, via a resin layer 161. The bonding is preferably performed so that the light-emitting device 150a and the colored layer 162a overlap, the light-emitting device 150b and the colored layer 162b overlap, and the light-emitting device 150c and the colored layer 162c overlap. By providing the colored layers 162a to 162c in the display device 100, for example, light emitted by the light-emitting device 150b does not exit above the substrate 102 via the colored layer 162a or the colored layer 162c, but exits above the substrate 102 via the colored layer 162b. In other words, since it is possible to block light from the light-emitting device 150 of the display device 100 in an oblique direction (the direction of the elevation angle when the top surface of the substrate 102 is considered to be a horizontal plane), it is possible to reduce the dependency of the display device 100 on the viewing angle, and it is possible to prevent a decrease in the display quality of the image displayed on the display device 100 when viewed from an oblique angle.

[0512] The colored layers 162a to 162c formed on the substrate 102 may be covered with a resin called an overcoat layer. Specifically, the display device 100 may be stacked in the following order (not shown): the resin layer 161, the overcoat layer, the colored layers 162a to 162c, and the substrate 102. Examples of resins used for the overcoat layer include light-transmitting thermosetting materials based on acrylic resin or epoxy resin.

[0513] Furthermore, for example, a black matrix (not shown) may be included in addition to the colored layers as part of the configuration of the display device 100. By providing a black matrix between the colored layers 162a and 162b, between the colored layers 162b and 162c, and between the colored layers 162c and 162a, it is possible to more effectively block light from the light-emitting device 150 of the display device 100 in an oblique direction (the direction of the elevation angle when the top surface of the substrate 102 is taken as a horizontal plane), thereby more effectively preventing a decrease in the display quality of an image displayed on the display device 100 when the image is viewed obliquely.

[0514] 24B, when the display device has a colored layer, the light-emitting devices 150a to 150c included in the display device may all be light-emitting devices that emit white light (not shown). The light-emitting devices may have, for example, a single structure or a tandem structure.

[0515] 25A, the display device 100 may have a configuration in which the conductors 121a to 121c are embedded in the insulator 111. For example, this configuration can be obtained by forming openings in the insulator 111 for embedding the conductors 121a to 121c, depositing conductive films to become the conductors 121a to 121c, and then performing chemical mechanical polishing (CMP) until the insulator 111 is exposed.

[0516] 25B, for example, the display device 100 may have an insulator 112 provided over the conductors 121a to 121c. Note that in FIG. 25B, there are regions over the conductors 121a, 121b, and 121c where the insulator 112 is not provided. For example, an insulating film to be the insulator 112 is formed over the insulator 111, the conductor 121a, the conductor 121b, and the conductor 121c, and the insulating film is patterned by photolithography to form openings that reach the conductors 121a, 121b, and 121c in regions of the insulating film that overlap with the conductors 121a, 121b, and 121c. This allows the insulator 112 to be provided.

[0517] For example, an insulating inorganic film can be used as the insulator 112. As the insulating inorganic film, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, or aluminum nitride can be used.

[0518] An organic film having an insulating layer may also be used as the insulator 112. Examples of organic films that can be used for the insulator 112 include polyimide.

[0519] Furthermore, the insulator 112 may have a multi-layer structure, for example, a two-layer structure in which the first layer is an insulator made of an organic material and the second layer is an insulator made of an inorganic material (not shown).

[0520] Furthermore, in the above-described configuration of the display device 100, the conductors 121a to 121c are used as anodes and the conductor 122 is used as a cathode, but the display device 100 may be configured such that the conductors 121a to 121c are used as cathodes and the conductor 122 is used as an anode. That is, in the manufacturing process described above, the stacking order of the hole injection layer, hole transport layer, light-emitting layer, electron transport layer, and electron injection layer included in the EL layers 141a to 141c and the EL layer 142 may be reversed.

[0521] The insulators, conductors, and semiconductors disclosed in this specification can be formed by PVD (Physical Vapor Deposition) or CVD. Examples of PVD include sputtering, resistance heating evaporation, electron beam evaporation, and PLD (Pulsed Laser Deposition). Examples of CVD include plasma CVD and thermal CVD. Examples of thermal CVD include MOCVD (Metal Organic Chemical Vapor Deposition) and ALD.

[0522] The thermal CVD method is a film formation method that does not use plasma, and therefore has the advantage that defects caused by plasma damage are not generated.

[0523] In the thermal CVD method, a source gas and an oxidant are simultaneously fed into a chamber, the chamber is kept at atmospheric pressure or reduced pressure, and the reaction occurs near or on a substrate, resulting in deposition on the substrate, thereby forming a film.

[0524] Alternatively, the ALD method may be used to deposit a film by sequentially introducing source gases into a chamber under atmospheric or reduced pressure and repeating this gas introduction sequence. For example, two or more source gases may be sequentially supplied to the chamber by switching between switching valves (also called high-speed valves). An inert gas (e.g., argon or nitrogen) may be introduced simultaneously with or after the first source gas to prevent mixing of the source gases, followed by the second source gas. When an inert gas is introduced simultaneously, the inert gas acts as a carrier gas, and may also be introduced simultaneously with the introduction of the second source gas. Alternatively, instead of introducing an inert gas, the first source gas may be evacuated by vacuum evacuation before the second source gas is introduced. The first source gas adsorbs onto the substrate surface to form a first thin layer, which then reacts with the second source gas introduced later, forming a thin film. Repeating this gas introduction sequence multiple times until the desired thickness is achieved allows for the formation of a thin film with excellent step coverage. The thickness of the thin film can be adjusted by changing the number of times the gas introduction sequence is repeated, allowing for precise film thickness adjustment, making this method suitable for fabricating fine FETs.

[0525] Thermal CVD methods such as MOCVD and ALD can form various films, including metal films, semiconductor films, and inorganic insulating films, as disclosed in the embodiments described above. For example, when forming an In-Ga-Zn-O film, trimethylindium (In(CH3)3), trimethylgallium (Ga(CH3)3), and dimethylzinc (Zn(CH3)2) are used. Furthermore, the combinations are not limited to these, and triethylgallium (Ga(C2H5)3) can be used instead of trimethylgallium, and diethylzinc (Zn(C2H5)2) can be used instead of dimethylzinc.

[0526] For example, when forming a hafnium oxide film using a film formation device that uses the ALD method, two types of gases are used: a source gas made by vaporizing a liquid containing a solvent and a hafnium precursor compound (hafnium alkoxide and hafnium amide such as tetrakisdimethylamidohafnium (TDMAH, Hf[N(CH3)2]4)), and ozone (O3) as an oxidizer. Other materials include, for example, tetrakis(ethylmethylamido)hafnium.

[0527] For example, when forming an aluminum oxide film using a film formation apparatus that uses the ALD method, two types of gases are used: a source gas obtained by vaporizing a liquid containing a solvent and an aluminum precursor compound (e.g., trimethylaluminum (TMA, Al(CH3)3)), and H2O as an oxidizing agent. Other materials include, for example, tris(dimethylamido)aluminum, triisobutylaluminum, and aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedionate).

[0528] For example, when forming a silicon oxide film using a film formation device that uses the ALD method, hexachlorodisilane is adsorbed onto the surface to be filmed, and radicals of oxidizing gases (O2, dinitrogen monoxide) are supplied to react with the adsorbed material.

[0529] For example, when forming a tungsten film using a film formation apparatus that uses the ALD method, WF6 gas and B2H6 gas are introduced in sequence and repeatedly to form an initial tungsten film, and then WF6 gas and H2 gas are introduced in sequence and repeatedly to form a tungsten film. Note that SiH4 gas may be used instead of B2H6 gas.

[0530] For example, when forming an In—Ga—Zn—O film as an oxide semiconductor film using a film formation apparatus using the ALD method, a precursor (generally referred to as a precursor or a metal precursor) and an oxidizer (generally referred to as a reactant, a reactant, or a non-metal precursor) are sequentially and repeatedly introduced to form the film. Specifically, for example, an In—O layer is formed by introducing precursor gas In(CH3)3 and oxidizer gas O3, followed by introducing precursor gas Ga(CH3)3 and oxidizer gas O3 to form a GaO layer, and then further introducing precursor gas Zn(CH3)2 and oxidizer gas O3 to form a ZnO layer. Note that the order of these layers is not limited to this example. Furthermore, mixed oxide layers such as an In—Ga—O layer, an In—Zn—O layer, or a Ga—Zn—O layer may be formed using these gases. Instead of O3 gas, H2O gas obtained by bubbling water with an inert gas such as Ar may be used, but it is preferable to use O3 gas that does not contain H. Also, instead of In(CH3)3 gas, In(C2H5)3 gas may be used. Also, instead of Ga(CH3)3 gas, Ga(C2H5)3 gas may be used. Also, Zn(CH3)2 gas may be used.

[0531] The aspect ratio of the display portion of the display device of one embodiment of the present invention is not particularly limited. For example, the display device can support various screen ratios such as 1:1 (square), 4:3, 16:9, and 16:10.

[0532] The shape of the display device of one embodiment of the present invention is not particularly limited. For example, the display device can be of various shapes such as a rectangular shape, a polygonal shape (for example, an octagonal shape), a circular shape, or an elliptical shape.

[0533] <Pixel circuit configuration example> Here, a configuration example of a pixel circuit that can be provided in the pixel layer PXAL will be described.

[0534] 26A and 26B show a configuration example of a pixel circuit that can be provided in the pixel layer PXAL and a light-emitting device 150 connected to the pixel circuit. Also, FIG. 26A is a diagram showing the connections of each circuit element included in a pixel circuit 400 provided in the pixel layer PXAL, and FIG. 26B is a diagram schematically showing the hierarchical relationship between a circuit layer SICL including a drive circuit 30, a layer OSL including multiple transistors of the pixel circuit, and a layer EML including a light-emitting device 150. The pixel layer PXAL of the display device 100 shown in FIG. 26B includes, as an example, a layer OSL and a layer EML. The transistor 500A, the transistor 500B, or the transistor 500C included in the layer OSL shown in FIG. 26B corresponds to the transistor 200 in FIG. 17. The light-emitting device 150 included in the layer EML shown in FIG. 26B corresponds to the light-emitting device 150a or the light-emitting device 150b in FIG. 17.

[0535] 26A and 26B includes a transistor 500A, a transistor 500B, a transistor 500C, and a capacitor 600. The transistors 500A, 500B, and 500C can be, for example, transistors applicable to the transistor 200 described above. That is, the transistors 500A, 500B, and 500C can be Si transistors. Or, the transistors 500A, 500B, and 500C can be, for example, transistors applicable to the transistor 500 described above. That is, the transistors 500A, 500B, and 500C can be OS transistors. In particular, when the transistors 500A, 500B, and 500C are OS transistors, each of the transistors 500A, 500B, and 500C preferably includes a backgate electrode. In this case, the backgate electrode may receive the same signal as the gate electrode, or a different signal from the gate electrode. Although the transistors 500A, 500B, and 500C each include a backgate electrode in FIGS. 26A and 26B, the transistors 500A, 500B, and 500C may not include a backgate electrode.

[0536] The transistor 500B includes a gate electrode electrically connected to the transistor 500A, a first electrode electrically connected to the light-emitting device 150, and a second electrode electrically connected to the wiring ANO. The wiring ANO is a wiring for applying a potential for supplying a current to the light-emitting device 150.

[0537] Transistor 500A has a first terminal electrically connected to the gate electrode of transistor 500B, a second terminal electrically connected to a wiring SL that functions as a source line, and a gate electrode that has the function of controlling the conductive state or non-conductive state based on the potential of wiring GL1 that functions as a gate line.

[0538] The transistor 500C includes a first terminal electrically connected to the wiring V0, a ​​second terminal electrically connected to the light-emitting device 150, and a gate electrode that controls the conductive state or non-conductive state based on the potential of the wiring GL2 that functions as a gate line. The wiring V0 is a wiring for applying a reference potential and a wiring for outputting the current flowing through the pixel circuit 400 to the drive circuit 30.

[0539] The capacitor 600 includes a conductive film electrically connected to the gate electrode of the transistor 500B and a conductive film electrically connected to the second electrode of the transistor 500C.

[0540] The light emitting device 150 includes a first electrode electrically connected to the first electrode of the transistor 500B and a second electrode electrically connected to a wiring VCOM. The wiring VCOM is a wiring for applying a potential for supplying a current to the light emitting device 150.

[0541] This allows the intensity of light emitted by light-emitting device 150 to be controlled in accordance with an image signal applied to the gate electrode of transistor 500B. Also, the reference potential of wiring V0 applied via transistor 500C can suppress variations in the gate-source voltage of transistor 500B.

[0542] Furthermore, a current value that can be used to set pixel parameters can be output from the wiring V0. More specifically, the wiring V0 can function as a monitor line for outputting the current flowing through the transistor 500B or the current flowing through the light-emitting device 150 to the outside. The current output to the wiring V0 can be converted into a voltage by, for example, a source follower circuit and output to the outside. Alternatively, it can be converted into a digital signal by, for example, an AD converter and output to the outside.

[0543] In the configuration shown in FIG. 26B as an example, the wiring electrically connecting the pixel circuits 400 and the driver circuit 30 can be shortened, thereby reducing the wiring resistance of the wiring. Therefore, data can be written at high speed, allowing the display device 100 to be driven at high speed. This allows a sufficient frame period to be ensured even if the display device 100 has a large number of pixel circuits 400, thereby increasing the pixel density of the display device 100. Furthermore, increasing the pixel density of the display device 100 can increase the resolution of images displayed by the display device 100. For example, the pixel density of the display device 100 can be set to 1000 ppi or more, 5000 ppi or more, or 7000 ppi or more. Therefore, the display device 100 can be used as a display device for AR or VR, for example, and can be suitably applied to electronic devices in which the display unit is close to the user, such as a head-mounted display.

[0544] 26A and 26B show an example of the pixel circuit 400 including three transistors in total, but one embodiment of the present invention is not limited to this. Below, a configuration example of a pixel circuit that can be used for the pixel circuit 400 will be described.

[0545] The pixel circuit 400A shown in Fig. 27A includes a transistor 500A, a transistor 500B, and a capacitor 600. Fig. 27A also illustrates a light-emitting device 150 connected to the pixel circuit 400A. The pixel circuit 400A is electrically connected to a wiring SL, a wiring GL, a wiring ANO, and a wiring VCOM.

[0546] The transistor 500A has a gate electrically connected to a wiring GL, one of its source and drain electrically connected to a wiring SL, and the other electrically connected to the gate of the transistor 500B and one electrode of the capacitor 600. The transistor 500B has one of its source and drain electrically connected to a wiring ANO, and the other electrically connected to the anode of the light-emitting device 150. The capacitor 600 has the other electrode electrically connected to the anode of the light-emitting device 150. The light-emitting device 150 has a cathode electrically connected to a wiring VCOM.

[0547] 27B has a configuration in which a transistor 500C is added to the pixel circuit 400A. A wiring V0 is electrically connected to the pixel circuit 400B.

[0548] The pixel circuit 400C shown in FIG. 27C is an example in which the transistors 500A and 500B in the pixel circuit 400A are transistors whose gates and back gates are electrically connected. The pixel circuit 400D shown in FIG. 27D is an example in which the same transistors are used in the pixel circuit 400B. This increases the current that the transistors can pass. While all the transistors in this example have a pair of gates electrically connected, this is not a limitation. Alternatively, a transistor having a pair of gates electrically connected to different wirings may be used. For example, reliability can be improved by using a transistor in which one of the gates is electrically connected to a source.

[0549] 28A has a configuration in which a transistor 500D is added to the pixel circuit 400B. The pixel circuit 400E is electrically connected to three wirings (a wiring GL1, a wiring GL2, and a wiring GL3) that function as gate lines.

[0550] The gate of the transistor 500D is electrically connected to a wiring GL3, one of the source and drain of the transistor 500B is electrically connected to the gate of the transistor 500B, and the other is electrically connected to a wiring V0. The gate of the transistor 500A is electrically connected to a wiring GL1, and the gate of the transistor 500C is electrically connected to a wiring GL2.

[0551] By simultaneously turning on transistors 500C and 500D, the source and gate of transistor 500B have the same potential, making it possible to turn off transistor 500B. This forcibly cuts off the current flowing through light-emitting device 150. Such a pixel circuit is suitable for use in a display method in which display periods and off periods are alternately provided.

[0552] 28B is an example in which a capacitor 600A is added to the pixel circuit 400E. The capacitor 600A functions as a storage capacitor.

[0553] 28C and 28D are examples in which transistors whose gates and back gates are electrically connected are applied to the pixel circuit 400E or 400F, respectively. Transistors whose gates and back gates are electrically connected are applied to transistors 500A, 500C, and 500D, and a transistor whose gate is electrically connected to its source is applied to transistor 500B.

[0554] <Plane and cross-sectional schematic diagram of a light-emitting device> 29A is a schematic plan view showing a configuration example in which a light-emitting device and a light-receiving device are arranged within one pixel in a display device 100 according to one embodiment of the present invention. The display device 100 has a plurality of light-emitting devices 150R that emit red light, a plurality of light-emitting devices 150G that emit green light, a plurality of light-emitting devices 150B that emit blue light, and a plurality of light-receiving devices 160. In FIG. 29A, to easily distinguish between the light-emitting devices 150, the light-emitting regions of the light-emitting devices 150 are labeled with R, G, and B. Furthermore, the light-receiving regions of the light-receiving devices 160 are labeled with PD.

[0555] The light-emitting devices 150R, 150G, 150B, and the light-receiving devices 160 are arranged in a matrix. FIG. 29A shows an example in which the light-emitting devices 150R, 150G, and 150B are arranged in the X direction, and the light-receiving devices 160 are arranged below them. FIG. 29A also shows an example in which the light-emitting devices 150 emitting light of the same color are arranged in the Y direction intersecting the X direction. In the display device 100 shown in FIG. 29A, a pixel 80 can be configured by, for example, a sub-pixel having the light-emitting device 150R, a sub-pixel having the light-emitting device 150G, a sub-pixel having the light-emitting device 150B, and a sub-pixel having the light-receiving device 160 arranged below these sub-pixels, which are arranged in the X direction.

[0556] Light-emitting device 150R, light-emitting device 150G, and light-emitting device 150B preferably use EL elements such as organic light-emitting diodes (OLEDs) or quantum-dot light-emitting diodes (QLEDs). Examples of light-emitting materials that EL elements may have include fluorescent materials, phosphorescent materials, inorganic compounds (e.g., quantum dot materials), and thermally activated delayed fluorescence (TADF) materials. Note that TADF materials may be materials that are in thermal equilibrium between a singlet excited state and a triplet excited state. Such TADF materials have a short emission lifetime (excitation lifetime), which can suppress a decrease in efficiency in the high-brightness region of light-emitting elements.

[0557] For example, a pn-type or pin-type photodiode can be used as the light-receiving device 160. The light-receiving device 160 functions as a photoelectric conversion element that detects light incident on the light-receiving device 160 and generates electric charges. The amount of electric charges generated is determined based on the amount of incident light.

[0558] In particular, it is preferable to use an organic photodiode having a layer containing an organic compound as the light-receiving device 160. Organic photodiodes can be easily made thin, lightweight, and large in area, and have a high degree of freedom in shape and design, making them applicable to a variety of display devices.

[0559] In one embodiment of the present invention, an organic EL element is used as the light-emitting device 150, and an organic photodiode is used as the light-receiving device 160. The organic EL element and the organic photodiode can be formed on the same substrate. Therefore, an organic photodiode can be built into a display device using an organic EL element. Separation of the organic EL elements and the organic photodiode is preferably performed by photolithography. This allows the spacing between the light-emitting devices and the organic photodiodes to be narrowed, thereby achieving a display device with a higher aperture ratio than when a shadow mask such as a metal mask is used.

[0560] 29A shows a conductor 122 that functions as a common electrode and a conductor 123 that functions as a connection electrode. Here, the conductor 123 is electrically connected to the conductor 122. The conductor 123 is provided outside the display section in which the light-emitting device 150 and the light-receiving device 160 are arranged. Also in FIG. 29A, the conductor 122 having an area that overlaps with the light-emitting device 150, the light-receiving device 160, and the conductor 123 is shown by dashed lines.

[0561] The conductor 123 can be provided along the periphery of the display unit. For example, it may be provided along one side of the periphery of the display unit, or it may be provided over two or more sides of the periphery of the display unit. That is, if the top surface of the display unit has a rectangular shape, the top surface of the conductor 123 can have a strip-like, L-shaped, U-shaped (square bracket-shaped), or quadrangular shape.

[0562] Fig. 29B is a schematic plan view showing a configuration example of display device 100, which is a modification of display device 100 shown in Fig. 29A. Display device 100 shown in Fig. 29B differs from display device 100 shown in Fig. 29A in that it includes light-emitting device 150IR that emits infrared light. Light-emitting device 150IR can emit, for example, near-infrared light (light with a wavelength of 750 nm or more and 1300 nm or less).

[0563] 29B, in addition to light-emitting devices 150R, 150G, and 150B, light-emitting device 150IR is arranged in the X direction, and light-receiving device 160 is arranged below light-emitting device 150IR. Furthermore, light-receiving device 160 has a function of detecting infrared light.

[0564] Fig. 30A is a cross-sectional view corresponding to dashed-dotted line A1-A2 in Fig. 29A, and Fig. 30B is a cross-sectional view corresponding to dashed-dotted line B1-B2 in Fig. 29A. Fig. 30C is a cross-sectional view corresponding to dashed-dotted line C1-C2 in Fig. 29A, and Fig. 30D is a cross-sectional view corresponding to dashed-dotted line D1-D2 in Fig. 29A. Light-emitting device 150R, light-emitting device 150G, light-emitting device 150B, and light-receiving device 160 are provided on insulator 111. When display device 100 includes light-emitting device 150IR, light-emitting device 150IR is provided on insulator 111.

[0565] In this specification and the like, for example, when it is said that "B is on A" or "B is below A," A and B do not necessarily have to have an area where they contact each other.

[0566] Fig. 30A shows an example of the cross-sectional configuration of light-emitting device 150R, light-emitting device 150G, and light-emitting device 150B in Fig. 29A. Also, Fig. 30B shows an example of the cross-sectional configuration of light-receiving device 160 in Fig. 29A.

[0567] The light-emitting device 150R has a conductor 121R functioning as a pixel electrode, a hole injection layer 85R, a hole transport layer 86R, a light-emitting layer 87R, an electron transport layer 88R, a common layer 89, and a conductor 122. The light-emitting device 150G has a conductor 121G functioning as a pixel electrode, a hole injection layer 85G, a hole transport layer 86G, a light-emitting layer 87G, an electron transport layer 88G, a common layer 89, and a conductor 122. The light-emitting device 150B has a conductor 121B functioning as a pixel electrode, a hole injection layer 85B, a hole transport layer 86B, a light-emitting layer 87B, an electron transport layer 88B, a common layer 89, and a conductor 122. The light-receiving device 160 has a conductor 121PD functioning as a pixel electrode, a hole transport layer 86PD, a light-receiving layer 90, an electron transport layer 88PD, a common layer 89, and a conductor 122.

[0568] The conductor 121R, the conductor 121G, and the conductor 121B may be, for example, the conductor 121a, the conductor 121b, and the conductor 121c shown in FIG.

[0569] The common layer 89 functions as an electron injection layer in the light-emitting device 150. On the other hand, the common layer 89 functions as an electron transport layer in the light-receiving device 160. Therefore, the light-receiving device 160 does not need to have the electron transport layer 88PD.

[0570] The hole injection layer 85, the hole transport layer 86, the electron transport layer 88, and the common layer 89 can also be referred to as functional layers.

[0571] The conductor 121, the hole injection layer 85, the hole transport layer 86, the light-emitting layer 87, and the electron transport layer 88 can be provided separately for each element. The common layer 89 and the conductor 122 are provided in common to the light-emitting device 150R, the light-emitting device 150G, the light-emitting device 150B, and the light-receiving device 160.

[0572] 30A, the light-emitting device 150 and the light-receiving device 160 may have a hole-blocking layer and an electron-blocking layer. The light-emitting device 150 and the light-receiving device 160 may have a layer containing a bipolar substance (a substance with high electron-transporting and hole-transporting properties) or the like.

[0573] Insulating layer 92 is provided to cover the end of conductor 121R, the end of conductor 121G, the end of conductor 121B, and the end of conductor 121PD. The end of insulating layer 92 is preferably tapered. Note that insulating layer 92 does not have to be provided if it is not necessary.

[0574] For example, hole injection layer 85R, hole injection layer 85G, hole injection layer 85B, and hole transport layer 86PD each have a region in contact with the upper surface of conductor 121 and a region in contact with the surface of insulating layer 92. In addition, an end of hole injection layer 85R, an end of hole injection layer 85G, an end of hole injection layer 85B, and an end of hole transport layer 86PD are located on insulating layer 92.

[0575] Furthermore, a gap is provided between the common layer 89 and the insulating layer 92. This prevents the common layer 89 from coming into contact with the side surfaces of the light-emitting layer 87, the light-receiving layer 90, the hole-transporting layer 86, and the hole-injecting layer 85. This prevents short circuits in the light-emitting device 150 and the light-receiving device 160.

[0576] The voids are more easily formed, for example, as the distance between adjacent light-emitting layers 87 becomes shorter. For example, the voids can be suitably formed when the distance is 1 μm or less, preferably 500 nm or less, and more preferably 200 nm or less, 100 nm or less, 90 nm or less, 70 nm or less, 50 nm or less, 30 nm or less, 20 nm or less, 15 nm or less, or 10 nm or less.

[0577] In addition, a protective layer 91 is provided on the conductor 122. The protective layer 91 has a function of preventing impurities such as water from diffusing from above into each light-emitting element.

[0578] The protective layer 91 may have, for example, a single-layer structure or a multilayer structure including at least an inorganic insulating film. Examples of the inorganic insulating film include oxide films such as a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, an aluminum oxide film, an aluminum oxynitride film, and a hafnium oxide film, or nitride films. Alternatively, the protective layer 91 may be made of a semiconductor material such as indium gallium oxide or indium gallium zinc oxide.

[0579] Furthermore, the protective layer 91 may be a laminated film of an inorganic insulating film and an organic insulating film. For example, it is preferable to have a configuration in which an organic insulating film is sandwiched between a pair of inorganic insulating films. Furthermore, it is preferable that the organic insulating film functions as a planarizing film. This ...

Claims

1. a first layer and a second layer located above the first layer, the first layer includes a first drive circuit, a second drive circuit, and a third drive circuit; the second layer has a first pixel region, a second pixel region, and a third pixel region; the first pixel region has a first pixel circuit; the second pixel region includes a second pixel circuit; the third pixel region includes a third pixel circuit; the first pixel region has an area overlapping with the first driving circuit, the second pixel region has an area overlapping with the second driving circuit, the third pixel region has an area overlapping with the third driving circuit, the first pixel circuit is electrically connected to the first drive circuit via a first wiring; the second pixel circuit is electrically connected to the second drive circuit via a second wiring; the third pixel circuit is electrically connected to the third drive circuit via a third wiring; the first wiring is electrically connected to the second wiring via a first switch; the second wiring is electrically connected to the third wiring via a second switch; when the first switch is in an OFF state and the second switch is in an OFF state, the first driving circuit has a function of transmitting first image data to the first pixel circuit, the second driving circuit has a function of transmitting second image data to the second pixel circuit, and the third driving circuit has a function of transmitting third image data to the third pixel circuit; When the first switch is in an on state and the second switch is in an on state, the first driving circuit has a function of transmitting the first image data to the first pixel circuit, transmitting the second image data to the second pixel circuit, and transmitting the third image data to the third pixel circuit. Display device.

2. In claim 1, the first switch is included in the first layer or the second layer; the second switch is included in the first layer or the second layer; Display device.

3. In claim 1 or claim 2, the first layer comprises a first substrate; the second layer comprises a second substrate; each of the first substrate and the second substrate is a semiconductor substrate made of silicon; a channel formation region of a transistor included in each of the first driving circuit, the second driving circuit, and the third driving circuit has silicon included in the first substrate; a channel formation region of a transistor included in each of the first pixel region, the second pixel region, and the third pixel region includes silicon included in the second substrate; Display device.

4. In claim 1 or claim 2, the first layer comprises a first substrate; the first substrate is a semiconductor substrate made of silicon, the transistors included in each of the first driving circuit, the second driving circuit, and the third driving circuit are transistors formed on the first substrate; the transistors included in each of the first pixel region, the second pixel region, and the third pixel region are transistors having a channel formation region containing a metal oxide; Display device.

5. 5. An electronic device comprising: the display device according to claim 1; and a housing.

Images