Semiconductor device and display device

Abstract

To provide a semiconductor device which suppresses a malfunction in a shift register circuit.SOLUTION: A semiconductor device includes a shift register consisting of a plurality of flip flop circuits. The flip flop circuit includes a transistor 11, a transistor 12, a transistor 13, a transistor 14, and a transistor 15. The transistor 13 or the transistor 14 is turned on in a non-selection period and potential of a node A is set, so that the node A is prevented from a floating state.SELECTED DRAWING: Figure 24

Description

[Technical Field]

[0001] The present invention relates to a driving circuit, and also to a display device having the driving circuit. The present invention relates to an electronic device having a display unit. [Background technology]

[0002] In recent years, display devices such as liquid crystal display devices and light-emitting devices have become increasingly popular due to the increasing number of large display devices such as liquid crystal televisions. In particular, transistors with semiconductor layers formed on insulating substrates are being actively developed. A pixel circuit consisting of transistors, etc., and a driver circuit (internal) including a shift register, etc. The technology of forming multiple semiconductor devices (also called circuits) on the same substrate has contributed greatly to reducing power consumption and costs. The internal circuit formed on the insulating substrate is It is connected to an external circuit including a controller IC etc. located outside the insulating substrate via C etc. Its operation is controlled.

[0003] The driver circuit (also called a scanning line driver), which is one of the internal circuits, For example, a shift register consisting of a plurality of flip-flop circuits as shown in Patent Document 1 is It is composed of [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2006-24350 Summary of the Invention [Problem to be solved by the invention]

[0005] The conventional driving circuit shown in Patent Document 1 has a transistor in a flip-flop circuit. The timing of the switching operation may deviate from the desired timing, resulting in malfunction. There is a problem that the timing of the transistor switching operation is misaligned. The reason for this is that, for example, a flip-flop circuit in the shift register is activated during the non-selection period. The gate terminal of the pull-up transistor is in a floating state, which reduces the noise generated during the non-selection period. The noise and other factors affect the potential of the gate terminal of the pull-up transistor.

[0006] Deterioration of the transistor itself is also one of the causes of timing discrepancies in switching operations. As the transistor deteriorates, the threshold voltage of the transistor changes, and the driving The semiconductor layer of the transistor is an amorphous semiconductor. When a transistor is used, the semiconductor layer of which is an amorphous semiconductor is likely to deteriorate. Therefore, malfunctions are particularly likely to occur.

[0007] In one embodiment of the present invention, a malfunction is suppressed in a circuit using a shift register. This is one of the challenges. [Means for solving the problem]

[0008] One embodiment of the present invention has a shift register including a plurality of flip-flop circuits, At least one of the flip-flop circuits is configured such that the first signal, the second signal, and the third signal are A flip-flop circuit receives an input signal and outputs an output signal. At least one of the paths has a gate terminal, a source terminal, and a drain terminal, and the gate terminal A first potential, which is the potential of a first signal, is applied to one of the source terminal and the drain terminal. a first transistor to which a first potential or a second potential is applied, a gate terminal, a source terminal, a gate terminal to which a third potential, which is the potential of the second signal, is applied; and one of the source terminal and the drain terminal of the first transistor is connected to the source terminal and the drain terminal of the second transistor. a fourth potential is applied to the other of the source terminal and the drain terminal; a second transistor connected to the source terminal and drain terminal of the first transistor; The other potential of the first transistor is controlled to be set to the first potential or the fourth potential. Whether or not the potential of the other of the source terminal and the drain terminal of the transistor is set to a fourth potential is determined. When one is on, the other is off, and when the other is on, the other is A third transistor and a fourth transistor that are turned off, a gate terminal, and a source terminal , and a drain terminal, and the gate terminal is connected to the source terminal and drain terminal of the first transistor. a potential of a third signal applied to one of the source terminal and the drain terminal; and the potential of the other of the source terminal and the drain terminal is set to the potential of the output signal. When the third transistor or the fourth transistor is in an on state, the and a fifth transistor.

[0009] One embodiment of the present invention has a shift register including a plurality of flip-flop circuits, The flip-flop circuit receives a first control signal, a second control signal, a first clock signal, and a second A flip-flop circuit receives a clock signal and outputs an output signal. The drop circuit has a gate terminal, a source terminal, and a drain terminal, and a first A first potential, which is the potential of the control signal, is applied to one of the source terminal and the drain terminal. a first transistor to which a potential of the first transistor or a second potential is applied, a gate terminal, a source terminal, and a drain terminal, and a third potential, which is the potential of the second control signal, is applied to the gate terminal. and one of the source terminal and the drain terminal of the first transistor is connected to the source terminal and the drain terminal of the second transistor. a fourth potential is applied to the other of the source terminal and the drain terminal; and a second transistor having a gate terminal, a source terminal, and a drain terminal. and one of the source terminal and the drain terminal of each transistor is connected to the is electrically connected to the other of the source terminal and the drain terminal of the first transistor, The first potential or the fourth potential is applied to the other of the source terminal and the drain terminal of the transistor. A fourth potential is applied to the other of the source terminal and the drain terminal of the other transistor. When one transistor is on, the other transistor is off, and the other A third transistor that turns one transistor off when the other transistor is on. a first transistor and a fourth transistor, each having a gate terminal, a source terminal, and a drain terminal; a source terminal electrically connected to the other of the source terminal and the drain terminal of the first transistor; A fifth potential, which is the potential of the first clock signal, is applied to one of the source terminal and the drain terminal. The potential of the other of the source terminal and the drain terminal becomes the potential of the output signal, and the third transistor a fifth transistor that is in an off state when the fourth transistor is in an on state; and a third transistor having a gate terminal, a source terminal, and a drain terminal, the gate terminal being connected to a third transistor. the other gate terminal of the fourth transistor and the other gate terminal of the fourth transistor, and One of the input terminals is electrically connected to the other of the source terminal and drain terminal of the fifth transistor. a sixth transistor connected to the first transistor and having a fourth potential applied to the other of the source terminal and the drain terminal; a gate terminal, a source terminal, and a drain terminal, and a second clock is applied to the gate terminal. A sixth potential, which is the potential of a signal, is applied, and one of the source terminal and the drain terminal is connected to the fifth transistor. The transistor is electrically connected to the other of the source terminal and the drain terminal. a seventh transistor to which a fourth potential is applied to the other drain terminal; be.

[0010] In one embodiment of the present invention, the flip-flop circuit has at least two terminals. A fifth potential is applied to one terminal of the transistor, and the other terminal of the transistor is connected to the third transistor and the fourth transistor. a first capacitance element electrically connected to the other gate terminal of the transistor; a gate terminal electrically connected to the gate terminal of the fifth transistor; and one of the source terminal and the drain terminal of the third transistor and the fourth transistor is connected to the the other gate terminal of the transistor, and the other of the source terminal and drain terminal. an eighth transistor to which a fourth potential is applied; and an eighth transistor having at least two terminals, one terminal A sixth potential is applied to the other terminal of the third transistor and the fourth transistor. a second capacitance element electrically connected to one of the gate terminals; and a drain terminal, and a gate terminal electrically connected to the gate terminal of the first transistor. and one of the source terminal and the drain terminal of the third transistor and the fourth transistor a fourth potential connected to the other of the source and drain terminals; and a ninth transistor to which

[0011] In one embodiment of the present invention, the flip-flop circuit has at least two terminals. A fifth potential is applied to one terminal of the transistor, and the other terminal of the transistor is connected to the third transistor and the fourth transistor. a first capacitance element electrically connected to the other gate terminal of the transistor; a gate terminal electrically connected to the gate terminal of the fifth transistor; and one of the source terminal and the drain terminal of the third transistor and the fourth transistor is connected to the the other gate terminal of the transistor, and the other of the source terminal and drain terminal. and an eighth transistor to which the fourth potential is applied.

[0012] In one aspect of the present invention, the flip-flop circuit has a gate terminal, a source terminal, and a first potential is applied to the gate terminal, and a second potential is applied to the source terminal and the drain terminal. One of the terminals is electrically connected to the other gate terminals of the third transistor and the fourth transistor. a tenth transistor connected to the other of the source terminal and the drain terminal thereof, and a fourth potential is applied to the other of the source terminal and the drain terminal thereof; It is also possible to have a configuration with a star.

[0013] In one embodiment of the present invention, the flip-flop circuit has a function of outputting a second output signal. the flip-flop circuit has a gate terminal, a source terminal, and a drain terminal; The gate terminal is electrically connected to one of the source terminal and the drain terminal of the first transistor. A fifth potential is applied to one of the source terminal and the drain terminal, and an eleventh transistor whose gate terminal has a potential equal to the potential of a second output signal; , a source terminal, and a drain terminal, and a gate terminal of the third transistor and the fourth transistor. a gate terminal of the transistor, and a source terminal and a drain terminal of the transistor; is electrically connected to the other of the source terminal and the drain terminal of the eleventh transistor, a twelfth transistor having the other of the source terminal and the drain terminal given a fourth potential; a gate terminal of the seventh transistor, a source terminal, and a drain terminal; the source terminal and the drain terminal of the eleventh transistor are electrically connected to the and the other of the source terminal and the drain terminal of and a thirteenth transistor to which a fourth potential is applied to the other terminal of the first transistor. do.

[0014] In one aspect of the present invention, the first control signal and the second control signal are digital signals. The absolute value of the potential difference between the high and low states of the digital signal is calculated as It can also be made larger than the absolute value of the threshold voltage of the transistor.

[0015] In one embodiment of the present invention, the fourth potential is set to the first control signal or the second control signal. or the high or low state of the first clock signal or the second clock signal. It can also be set to a value equivalent to the rank.

[0016] In one aspect of the present invention, the first clock signal and the second clock signal are out of phase with each other. The high and low states of the first and second clock signals are in an inverse relationship. The absolute value of the potential difference is made larger than the absolute value of the threshold voltage of the transistor in the flip-flop circuit. It is also possible to do so.

[0017] In one embodiment of the present invention, all the transistors in the flip-flop circuit are the same. It can also be of one conductivity type.

[0018] In one aspect of the present invention, the transistor in the flip-flop circuit has a gate voltage The gate electrode is covered with a gate insulating film, and the gate electrode is sandwiched between the gate insulating film and the gate a first semiconductor layer including a microcrystalline semiconductor layer provided on an electrode; a buffer layer formed on the buffer layer and including an impurity element; and a pair of second semiconductor layers formed on the buffer layer and including an impurity element. a source electrode provided on one of the pair of second semiconductor layers; and a drain electrode provided on the other.

[0019] One embodiment of the present invention is a scanning line driver circuit and a signal line driver circuit including any of the above driver circuits. The pixel section includes a driving circuit, a plurality of scanning lines, a plurality of signal lines, and a pixel section. The scanning line driver circuit is electrically connected to the scanning line driver circuit via one of the signal lines. The display device has a plurality of pixels electrically connected to a signal line driver circuit via a signal line driver circuit.

[0020] One embodiment of the present invention is an electronic device that includes the above-described display device in a display portion.

[0021] In this specification, a transistor is defined as a transistor having a gate terminal, a source terminal, and a drain terminal. The gate terminal is a part of the gate electrode (a conductive layer and a wiring This refers to a part of the gate electrode that is electrically connected to the gate electrode (including a line, etc.) or the gate electrode. The source terminal is a part of the source electrode (including the conductive layer and wiring) and a part of the source electrode. It refers to a part of the part (including the semiconductor layer) that is electrically connected to the electrode. The drain terminal is the part of the drain electrode (including the conductive layer and wiring) and the drain electrode It also refers to a part of the circuit (including semiconductor layers) that is electrically connected to the The transistor has a channel region between a drain region and a source region. A current can be passed through the gate and source regions.

[0022] In this specification, the source terminal and the drain terminal of a transistor are This depends on the structure and operating conditions of the device, so it is unclear which is the source terminal or the drain terminal. Therefore, it is difficult to limit the scope of the present document (specification, claims or drawings). In the case of a transistor, either the source terminal or the drain terminal is arbitrarily selected as the source terminal. The other terminal is referred to as the other of the source and drain terminals. It is written as follows.

[0023] Note that it is not explicitly stated that B is formed on A, or that B is formed on A. In the case of the above, it is not limited to B being formed on A in direct contact with it. This also includes cases where there is no object between A and B, i.e., there is another object between A and B. Here, A and B are objects (for example, devices, elements, circuits, wiring, electrodes, terminals, conductive films, or is a layer, etc.

[0024] Therefore, for example, it is not possible to explicitly state that layer B is formed on top of layer A (or on top of layer A). When described, it means that layer B is formed directly on layer A, and layer A is formed on layer B. Another layer (such as layer C or layer D) is formed directly on top of it, and layer B is formed directly on top of it. It should be noted that other layers (such as layers C and D) may be formed as follows: It may be a single layer or multiple layers.

[0025] It should be noted that it is not explicitly stated that B is formed on A or that B is formed on A. This also includes the case where B is formed diagonally above.

[0026] In this specification, terms using ordinal numbers such as first and second are used to avoid confusion of components. It should be noted that the numbers are added for the purpose of convenience and are not intended to be limiting in number. [Effects of the Invention]

[0027] According to one embodiment of the present invention, it is possible to suppress malfunction in a circuit using a shift register. This can be done. [Brief explanation of the drawings]

[0028] [Figure 1] 2 is a circuit diagram showing an example of the configuration of a drive circuit according to the first embodiment. FIG. [Figure 2] 2 is a timing chart illustrating the operation of the drive circuit shown in FIG. [Figure 3] 2 is a circuit diagram showing an example of the configuration of a drive circuit according to the first embodiment. FIG. [Figure 4] 2 is a circuit diagram showing an example of the configuration of a drive circuit according to the first embodiment. FIG. [Figure 5] 5 is a timing chart illustrating the operation of the drive circuit shown in FIG. [Figure 6] 2 is a circuit diagram showing an example of the configuration of a drive circuit according to the first embodiment. FIG. [Figure 7] FIG. 10 is a circuit diagram showing an example of the configuration of a drive circuit according to a second embodiment. [Figure 8] 8 is a timing chart illustrating the operation of the drive circuit shown in FIG. 7. [Figure 9] FIG. 10 is a circuit diagram showing an example of the configuration of a drive circuit according to a second embodiment. [Figure 10]FIG. 10 is a circuit diagram showing an example of the configuration of a drive circuit according to a second embodiment. [Figure 11] 11 is a timing chart illustrating the operation of the drive circuit shown in FIG. [Figure 12] FIG. 10 is a circuit diagram showing an example of the configuration of a drive circuit according to a second embodiment. [Figure 13] FIG. 11 is a circuit diagram showing an example of the configuration of a display device according to a third embodiment. [Figure 14] 14 is a timing chart showing the operation of the scanning line driving circuit 702 shown in FIG. 13. [Figure 15] 10A and 10B are diagrams illustrating an example of the configuration and operation of a pixel in a liquid crystal display device according to a third embodiment. [Figure 16] 10A and 10B are diagrams illustrating an example of the configuration and operation of a pixel in a liquid crystal display device according to a third embodiment. [Figure 17] 10 is a cross-sectional view schematically illustrating an example of the configuration of a transistor applicable to the driver circuit in accordance with Embodiment 4. FIG. [Figure 18] 10 is a cross-sectional view schematically illustrating an example of the configuration of a transistor applicable to the driver circuit in accordance with Embodiment 4. FIG. [Figure 19] 10A to 10C are cross-sectional views illustrating an example of a method for manufacturing a transistor that can be used in a driver circuit in Embodiment 4. [Figure 20] 10A to 10C are cross-sectional views illustrating an example of a method for manufacturing a transistor that can be used in a driver circuit in Embodiment 4. [Figure 21] 10A to 10C are cross-sectional views illustrating an example of a method for manufacturing a transistor that can be used in a driver circuit in Embodiment 4. [Figure 22] 13 is a diagram showing an example of an electronic device in which the display device in Embodiment 5 can be used as a display unit. FIG. [Figure 23] 13 is a diagram showing an example of an electronic device in which the display device in Embodiment 5 can be used as a display unit. FIG. [Figure 24] FIG. 2 is a diagram showing an example of the configuration of a drive circuit according to the first embodiment. [Figure 25] FIG. 4 is a diagram showing the results of circuit calculation of the drive circuit according to the first embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0029] An embodiment of the present invention will be described below with reference to the drawings. The present invention is not limited to the above description, and the embodiments and details thereof may be modified without departing from the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that various modifications can be made to the above. The present invention should not be construed as being limited to the description of the embodiments.

[0030] (Embodiment 1) In this embodiment, a driver circuit which is one embodiment of the present invention will be described.

[0031] The driver circuit in this embodiment is a shift register including a plurality of flip-flop circuits. It has.

[0032] An example of the circuit configuration of the flip-flop circuit will be described with reference to FIG. 4 is a circuit diagram showing an example of the circuit configuration of a flip-flop circuit in the driver circuit of this embodiment. This is a road map.

[0033] At least one of the plurality of flip-flop circuits is a flip-flop having a circuit configuration shown in FIG. The flip-flop circuit shown in FIG. The first signal, the second signal, and the third signal are inputted, and an output signal is outputted. This shall be the case.

[0034] The flip-flop circuit shown in FIG. 24 includes a transistor 11, a transistor 12, and a transistor 31. The transistor 13, the transistor 14, and the transistor 15 are included.

[0035] The transistor 11 is supplied with a first potential, which is the potential of the first signal, at its gate terminal. A first potential or a second potential is applied to one of the source terminal and the drain terminal.

[0036] The transistor 12 has one of its source and drain terminals connected to the source of the transistor 11. The transistor 12 is electrically connected to the other of the gate terminal and the drain terminal. A third potential, which is the potential of the second signal, is applied to the terminal, and the source terminal, the drain terminal, and the like are connected to the A fourth potential is applied to the other side.

[0037] The transistor 13 and the transistor 14 are connected to the source terminal of the transistor 11 and A function for controlling whether the potential of the other of the drain terminals is set to the first potential or the fourth potential. The other of the two terminals is connected to the fourth terminal. It has a function of controlling whether or not to set the potential.

[0038] The transistor 13 has a function of being turned off when the transistor 14 is turned on. and transistor 14 is in an off state when transistor 13 is in an on state. It has the function of

[0039] The transistor 15 has a gate terminal connected to the source and drain terminals of the transistor 11. The transistor 15 is electrically connected to the other of the source terminal and the drain terminal. A fifth potential, which is the potential of the third signal, is applied to one terminal, and the source terminal, the drain terminal, and the like are applied to the other terminals. The potential of the source terminal and the drain terminal of the transistor 11 is the potential of the output signal. The connection point between the other of these and the gate terminal of the transistor 15 is also referred to as node A.

[0040] Also, when the transistor 13 or the transistor 14 is in an on state, the transistor 15 It is in the off state.

[0041] With the above configuration, when the transistor 13 or the transistor 14 is in the ON state, The potential of node A, i.e., the potential of the gate terminal of transistor 15, is set to a predetermined value. Since the terminal A is not left floating, malfunction of the flip-flop circuit can be suppressed. Cut.

[0042] Furthermore, an example of the circuit configuration of the flip-flop circuit in the driver circuit of this embodiment will be described below. This will be explained with reference to FIG. 1. FIG. 1 shows the circuit of the flip-flop circuit in this embodiment. FIG. 2 is a circuit diagram showing an example of a configuration.

[0043] Each of the plurality of flip-flop circuits in the driving circuit of this embodiment is the same as that shown in FIG. The flip-flop circuit shown in FIG. The path is made up of terminals 100, 101, 102, 103, 104, and 105, a transistor 106, a transistor 107, a capacitance element 108, and a transistor a transistor 109, a transistor 110, a transistor 111, a capacitance element 112, and a transistor Transistor 113, transistor 114, transistor 115, and transistor 116 and,

[0044] In the flip-flop circuit shown in FIG. 1, the terminal 102 is a terminal 102A and a terminal 1 02B, but is not limited to this, and the flip-flop in the driver circuit of this embodiment In the drop circuit, the terminal 102A and the terminal 102B are electrically connected to each other, and one terminal 102 In the flip-flop circuit shown in FIG. 103A and terminal 103B are shown, but are not limited to these. In the flip-flop circuit in FIG. 1, the terminal 103A and the terminal 103B are electrically connected to each other. , it may be possible to use one terminal 103.

[0045] In addition, in the flip-flop circuit in the driving circuit of this embodiment, the terminal 104 is Although terminals 104A to 104G are shown, the present invention is not limited to these. In the flip-flop circuit in the circuit, terminals 104A to 104G are electrically connected It is also possible to combine them into one terminal 104.

[0046] The transistor 106 has a gate terminal electrically connected to the terminal 100 and a source terminal and One of the drain terminals is electrically connected to the gate terminal of the transistor 106 .

[0047] The transistor 107 has a gate terminal electrically connected to the terminal 101 and a source terminal and One of the drain terminals is electrically connected to the other of the source and drain terminals of transistor 106. and the other of the source terminal and the drain terminal is electrically connected to terminal 104A. Although not shown for convenience, the flip-flop circuit in the driver circuit of this embodiment In this case, the transistor 107 may not be provided. By not providing such a circuit, the circuit area can be reduced.

[0048] The capacitive element 108 has at least two terminals, one of which is electrically connected to the terminal 102A. Connected.

[0049] The transistor 109 has a gate terminal connected to the source and drain terminals of the transistor 106. One of the source terminal and the drain terminal is electrically connected to the other of the capacitor element 108. The other of the source and drain terminals is electrically connected to terminal 104B. are connected to the network.

[0050] The transistor 110 has a gate terminal connected to the source and drain terminals of the transistor 109. one of the source terminal and the drain terminal of the transistor 106 and the other of the source terminal and the drain terminal of The other end is electrically connected to terminal 104C.

[0051] The capacitance element 112 has at least two terminals, one of which is electrically connected to the terminal 103A. Connected.

[0052] The transistor 111 has a gate terminal electrically connected to the other terminal of the capacitor 112. , one of the source terminal and the drain terminal of the transistor 106 The other of the source and drain terminals is electrically connected to terminal 104D. are connected to the network.

[0053] The transistor 113 has a gate terminal connected to the source and drain terminals of the transistor 106. The other of the source terminal and drain terminal of the transistor 111 is electrically connected to the other of the source terminal and drain terminal of the transistor 111. The other of the source terminal and the drain terminal is electrically connected to the terminal 104E. are electrically connected.

[0054] The transistor 114 has a gate terminal connected to the source and drain terminals of the transistor 106. The other of the terminals is electrically connected to the terminal 103B, and one of the source terminal and the drain terminal is electrically connected to the terminal 103C. the other of the source terminal and the drain terminal is electrically connected to the terminal 105; The potential of the other of the source terminal and the drain terminal becomes the output signal and is output via the terminal 105. Note that the flip-flop circuit in the driver circuit of this embodiment mode includes the transistor 114. A separate capacitance element is provided between the gate terminal and the other of the source terminal and the drain terminal. You can also do this.

[0055] The transistor 115 has a gate terminal electrically connected to the gate terminal of the transistor 111. one of the source terminal and the drain terminal of the transistor 114 is connected to the source terminal and the drain terminal of the transistor 114. The other of the source and drain terminals is electrically connected to terminal 104. Electrically connected to F.

[0056] The transistor 116 has a gate terminal electrically connected to the terminal 102B and a source One of the source and drain terminals is the other of the source and drain terminals of the transistor 114. and the other of the source terminal and the drain terminal is electrically connected to terminal 104G. will be done.

[0057] Note that one of the source terminal and the drain terminal of the transistor 109 and the The other terminal or the connection point with the gate terminal of the transistor 110 is also called a node 118. The other of the source terminal and the drain terminal of the transistor 106 and the transistor 107 one of the source and drain terminals of the transistor 110; one of the source terminal and drain terminal of the transistor 111; The gate terminal of the transistor 114 is connected to the node 117. The gate terminal of the transistor 111, the other terminal of the capacitor 112, One of the source terminal and drain terminal of transistor 113 or the gate terminal of transistor 115 The connection point with the child is also called a node 119.

[0058] The flip-flop circuit shown in FIG. 1 receives a first control signal via a terminal 100. The first control signal is input via the terminal 101, and the second control signal is input via the terminal 102. The signals are digital signals each having two states, a high state and a low state, for example. When a digital signal is used, the input first control signal or second control signal can be When the signal is in a high state (also called a high level), The first control signal or the second control signal is a potential of a predetermined value as a first potential (also referred to as V1). When a control signal is input and the first control signal or the second control signal is in a low state (also called low level) is connected to a second potential (V2 and The first control signal is a potential lower than the predetermined potential in the high state. The potential values ​​in the high and low states are, for example, For example, it can be set appropriately taking into consideration the value of the threshold voltage of the transistor. The potential difference between the low and high states is the absolute value of the threshold voltage of the transistor in the flip-flop circuit. It is preferable to set the potential values ​​in the high and low states so that stomach.

[0059] Furthermore, the flip-flop circuit shown in FIG. A first phase clock signal (also called CK) is transmitted through the signal) or the second phase of the clock signal (second clock signal, CKB signal) The first clock signal and the inverted signal of the first clock signal are input. The second clock signal has two potential states, a high state and a low state, and when it is in the high state, When the clock signal is in the high state (also called the high level), the potential of the clock signal is V1, and when it is in the low state, In the low state (also called the low level), the potential of the clock signal is at potential V2. The potentials of the first clock signal and the second clock signal when in a high state are the first control It is preferable that the potential of the first control signal and the second control signal is equal to that of the first control signal when the first control signal is in a low state. The potentials of the first clock signal and the second clock signal are the same as those of the first control signal and the second control signal when they are in a low state. It is preferable that the potential of the second control signal is equal to that of the second control signal. The value of the potential in the MOSFET should be set appropriately, taking into consideration the threshold voltage of the transistor, for example. For example, the potential difference between the high and low states is The values ​​of the potentials in the high and low states are set so that they are greater than the absolute value of the threshold voltage of the capacitor. It is preferable to set

[0060] The first and second clock signals are in opposite phase. For example, during a predetermined period, when the first clock signal is in a high state, the second The clock signals are in a low state, and when the first clock signal is in a low state, the second clock signal is The clock signal is in a high state.

[0061] The flip-flop circuit also includes a terminal 103 (also referred to as a terminal 103A and a terminal 103B). ) through which the first clock signal or the second clock signal is input. The clock signal input via terminal 2 and the clock signal input via terminal 103 are mutually exclusive. For example, when the first clock signal is input via the terminal 102, A second clock signal is input via terminal 103, and a second clock signal is output via terminal 102. When a signal is input, the first clock signal is input via terminal 103 .

[0062] Furthermore, the flip-flop circuit shown in FIG. 1 has a terminal 104 (terminals 104A to 104B) A predetermined potential is applied via the gate electrode (also called G). At this time, the value of the predetermined potential is, for example, For example, it can be V1 or V2, i.e., a digital signal such as a clock signal or a control signal. The potential value can be set to a value equivalent to the potential value of the high or low state of the digital signal.

[0063] In the flip-flop circuit shown in FIG. The configuration in which one of the drain terminals is electrically connected to the terminal 100 has been described. The flip-flop circuit in the driver circuit of this embodiment is not limited to the above, and a separate power supply terminal and a potential V1 or V2 may be applied. can.

[0064] The transistor 106 is connected to the terminal 100 in accordance with the signal input via the terminal 100. and node 117.

[0065] The transistor 107 operates in accordance with the signal input via the terminal 101. A and node 117, and the terminal 104A and node 117 are electrically connected. By entering this state, the potential of node 117 is set to V1 or V2.

[0066] The capacitance element 108 changes in response to a signal input via the terminal 102 (terminal 102A). , the potential of the node 118 is changed by capacitive coupling. When the signal input via the terminal 102A changes from a low state to a high state, The node 108 has the function of setting the potential of the node 118 to the potential V1 by capacitive coupling. On the other hand, when the signal input via the terminal 102 changes from a high state to a low state, the capacitance element The capacitor 108 has the function of setting the potential of the node 118 to V1 or V2 by capacitive coupling. do.

[0067] The transistor 109 operates in accordance with the signal input via the terminal 100. B and node 118, and the terminal 104B and node 118 are electrically connected. This sets the potential of node 118 to V1 or V2.

[0068] The transistor 110 is connected between the terminal 104C and the node 118 according to the potential of the node 118. 7, and the terminal 104C and the node 117 are brought into a conductive state. The potential of the node 117 is set to V1 or V2 by the transistor 110. , has a function of being turned off when the transistor 111 is turned on.

[0069] The transistor 111 is connected between the terminal 104D and the node 111 according to the potential of the node 119. 7, and the terminal 104D and the node 117 are brought into a conductive state. The potential of the node 117 is set to V1 or V2 by the transistor 111. has a function of being turned off when the transistor 110 is turned on.

[0070] The capacitance element 112 is connected to the capacitor through capacitive coupling in accordance with the signal input via the terminal 103A. For example, the potential of the node 119 is changed by the input through the terminal 103A. When the signal applied to the capacitor 112 changes from a low state to a high state, the capacitor 112 The potential of the node 119 is set to V1. On the other hand, the signal input via the terminal 103A is When the state changes from high to low, the capacitance element 112 The potential is set to V2.

[0071] The transistor 113 has a function of controlling conduction between the terminal 104E and the node 119. When the terminal 104E and the node 119 are brought into a conductive state, the potential of the node 119 becomes V1 Or set to V2.

[0072] The transistor 114 is connected to the terminal 103B and the terminal 105 according to the potential of the node 117. By controlling the conduction between terminal 103B and terminal 105, the conduction between terminal 103B and terminal 105 is established. The potential of the signal input via terminal 3B is equal to the potential of the signal output via terminal 105. It has the function of setting the value to

[0073] The transistor 114 is, for example, an N-type transistor, and the potential of the node 117 is When V1, the signal input through terminal 103B changes from a low state to a high state. As the potential at the connection point with the terminal 105 rises, the potential at the node 117 rises. This is what is called a bootstrap. However, the bootstrap The parasitic capacitance between the gate terminal of the transistor 114 and the other of the source terminal and drain terminal is So it is often done.

[0074] The transistor 115 is connected to the terminal 104F and the terminal 105 according to the potential of the node 119. When the terminal 104F and the terminal 105 are brought into a conductive state, As a result, the potential of the signal output via the terminal 105 is set to V1 or V2.

[0075] The transistor 116 operates in accordance with the signal input via the terminal 102B. The terminal 104G has a function of controlling the electrical continuity between the terminal 104G and the terminal 105, and the terminal 104G and the terminal 105 are electrically connected. and has a function of setting the potential of the signal output via the terminal 105 to V1 or V2. do.

[0076] The driver circuit in this embodiment is composed of transistors of the same conductivity type. Therefore, the manufacturing process can be simplified. Furthermore, it is possible to reduce costs and improve yields. In the driving circuit of this embodiment, all the transistors The transistors are either N-type conductivity type transistors (also called N-type transistors) or P-type conductivity type transistors. It should be noted that in this specification, the same This also includes those that are substantially identical.

[0077] Next, the operation of the driving circuit shown in FIG. 1 will be explained with reference to FIG. 2. 10 is a timing chart showing an example of the operation of the driver circuit. A second clock signal is input via terminal 102, and a first clock signal is input via terminal 103. A clock signal is input. Here, one of the operations of the driving circuit shown in FIG. For example, if all the transistors in a flip-flop circuit are N-type transistors, I will explain.

[0078] The operation of the drive circuit shown in FIG. 1 is such that a predetermined operation is repeated for a certain period of time as shown in FIG. The fixed period is mainly divided into a selection period and a non-selection period, and the selection period The selection period and non-selection period are the first period, the second period, the third period, the fourth period, and the fifth period. In FIG. 2, the first period, the third period, the fourth period, and the fifth period are The first period is a non-selection period, and the second period is a selection period.

[0079] First, in the first period, a first control signal 201 in a high state is input via the terminal 100. A second control signal 208 in a low state is input via the terminal 101, and a second control signal 208 in a low state is input via the terminal 102. A second clock signal 203 in a high state is input via When the first clock signal 202 in the ON state is input, the transistors 106 and The transistor 109 and the transistor 116 are turned on, and the transistor 107 is turned off. It becomes a state of 'fu'.

[0080] When the transistor 106 is turned on, the potential 204 of the node 117 begins to rise. At this time, the potential of the node 117 is changed from the potential V1 of the first control signal 201 to the potential of the transistor 106. The threshold voltage (Vth 106 (also called) V1-Vth 106 Until V1-Vth 106When this occurs, the transistor 106 is turned off.

[0081] Furthermore, the potential 204 of the node 117 is V1-Vth 106 Then, transistor 113 At this time, the potential 206 of the node 119 is applied via the terminal 104E. The potential V2 becomes equal to the potential V1.

[0082] Furthermore, when the potential 206 of the node 119 becomes V2, the transistors 111 and 112 The inverter 115 is turned off.

[0083] When the transistor 109 is turned on, the potential 205 of the node 118 is The potential V2 is equal to the potential V2 applied via O4B.

[0084] Furthermore, when the potential 205 of the node 118 becomes V2, the transistor 110 is turned off. do.

[0085] Furthermore, as described above, transistor 106, transistor 107, and transistor 110 , and when the transistor 111 is turned off, the potential of the node 117 is V1-Vth1 06 The object is kept floating while remaining at this temperature.

[0086] Also, the potential 204 of the node 117 is V1-Vth 106 Then, transistor 114 is turned on.

[0087] Furthermore, at this time, the potential of the output signal 207 outputted through the terminal 105 is or a potential V2 equivalent to the potential V2 applied through terminal 104G. The above is the operation in the first period.

[0088] Next, in the second period, the first control signal 201 in the low state is input via the terminal 100. A second control signal 208 in a low state is input via the terminal 101, and a second control signal 208 in a low state is input via the terminal 102. A second clock signal 203 in a low state is input via the At this time, the first clock signal 202 is input. The transistor 109 and the transistor 116 are turned off, and the transistor 107 is turned off. It remains in that state.

[0089] The transistor 109 receives the second clock signal 20 input via the terminal 102A. In many cases, the input is turned off after the input 3 goes low. The first control signal 201 is often delayed from the second clock signal 203. This is because the transistor 109 turns on after the second clock signal 203 goes low. By this, node 118 is kept at potential V2 and is in a floating state. Transistor 110 remains in the off state.

[0090] The capacitance element 108 receives the second clock signal 20 input via the terminal 102A. 3 and the potential 205 of node 118, that is, the second clock in the low state. The potential difference between the potential of the signal 203 and the potential V2 applied via the terminal 104B is maintained. .

[0091] As described above, the transistors 106, 107, and 11 When Vth is in the off state, the potential 204 of the node 117 is V1-Vth 106 remains .

[0092] Furthermore, the potential 204 of the node 117 is V1-Vth 106 When this is the case, transistor 11 3 remains on, and when transistor 113 remains on, node 1 The potential 206 of the transistor 19 remains at V2, and the transistor 111 and the transistor 115 are turned on. It remains in the OFF state.

[0093] The potential 204 of the node 117 is V1-Vth 106 The transistor 114 remains The potential of one of the source terminal and the drain terminal becomes the potential V1 of the first clock signal 202. When this occurs, the potential of the output signal 207 output via the terminal 105 rises. 7 is floating, the potential 204 of the node 117 is The output is capacitively coupled by the parasitic capacitance between the output terminal and the other of the source and drain terminals. It rises in accordance with the potential of the force signal 207. This is the so-called bootstrap.

[0094] The potential 204 of the node 117 is the potential V1 of the first clock signal 202 and the potential V2 of the transistor The threshold voltage (Vth 114 (also called) and V1 +Vth 114 +Va (Va is any positive value). At this time, transistor 11 4 remains on.

[0095] Furthermore, at this time, the potential of the output signal 207 outputted through the terminal 105 is The voltage V1 becomes equal to the potential V2 given via the potential V3. The above is the operation in the second period.

[0096] Next, in the third period, the first control signal 201 in the low state is input via the terminal 100. A second control signal 208 in a high state is input via terminal 101, and a second control signal 208 in a high state is input via terminal 102. A second clock signal 203 in a high state is input via At this time, the first clock signal 202 is input. The transistor 116 is turned on, and the transistors 106 and 109 are turned off. It remains in that state.

[0097] When the transistor 107 is turned on, the potential 204 of the node 117 is applied to the terminal 104A. The potential V2 is equal to the potential V1 applied via the

[0098] Furthermore, the potential 205 of the node 118 becomes V2+Vb due to the capacitive coupling of the capacitor 108. Vb is preferably greater than the threshold voltage of transistor 110, and V1-V2 It is preferable that it is smaller than

[0099] Furthermore, when the potential 205 of the node 118 becomes V2+Vb, the transistor 110 turns on. Furthermore, when the transistor 110 is turned on, the potential 204 of the node 117 becomes equal to the potential V2 applied via the terminal 104C.

[0100] Furthermore, when the potential 204 of the node 117 becomes the potential V2, the transistors 113 and 114 The transistor 113 is turned off by the input through the terminal 103A. In many cases, the first clock signal 202 goes low and then goes off. If so, the potential 204 of the node 117 is delayed or stale relative to the first clock signal 202. This is because the first clock signal 202 is often in a low state. When the resistor 113 is turned off, a voltage equal to the potential V2 applied via the terminal 104E is applied. is maintained and node 119 becomes floating.

[0101] Furthermore, when node 119 is floating, transistors 111 and 11 5 remains in the off state.

[0102] Furthermore, the capacitance element 112 receives the first clock signal 20 input via the terminal 103A. 2 and the potential 206 of node 119, that is, the first clock The potential difference between the potential of the clock signal 202 and the potential V2 applied via the terminal 104E is maintained. do.

[0103] Furthermore, at this time, the potential of the output signal 207 outputted through the terminal 105 is The value of the potential V2 is equal to the potential V1 given via the potential V2. The above is the operation in the third period.

[0104] Next, in the fourth period, the first control signal 201 in the low state is input via the terminal 100. A second control signal 208 in a low state is input via the terminal 101, and a second control signal 208 in a low state is input via the terminal 102. A second clock signal 203 in a low state is input via the At this time, the first clock signal 202 is input. The transistor 116 is turned off, and the transistors 106 and 109 are turned off. It remains in that state.

[0105] At this time, the potential 205 of the node 118 becomes V2 due to the capacitive coupling of the capacitor 108. Therefore, transistor 110 is turned off.

[0106] The potential 206 of the node 119 is V2+Vc due to the capacitive coupling of the capacitor 112. Vc is greater than the threshold voltage of the transistor 111 or the threshold voltage of the transistor 115. It is preferably larger and is preferably smaller than V1-V2.

[0107] Furthermore, when the potential 206 of the node 119 becomes V2+Vc, the transistors 111 and 112 The transistor 115 is turned on.

[0108] Furthermore, when the transistor 111 is turned on, the potential 204 of the node 117 is The potential V2 is equal to the potential V2 applied via 4D.

[0109] Furthermore, when the potential 204 of the node 117 becomes V2, the transistors 113 and 114 The inverter 114 is turned off.

[0110] When the transistor 115 is turned on, the output signal is output via the terminal 105. The potential of signal 207 is equal to the potential V2 applied via terminal 104F. This is the operation in the fourth period.

[0111] Next, in the fifth period, the first control signal 201 in the low state is input via the terminal 100. A second control signal 208 in a low state is input via the terminal 101, and a second control signal 208 in a low state is input via the terminal 102. A second clock signal 203 in a high state is input via The first clock signal 202 is input. At this time, the transistor 116 is turned on. state, and the transistors 106, 107, and 109 are turned off. It remains in that state.

[0112] At this time, the potential of the node 118 becomes V2+Vb due to the capacitive coupling of the capacitor 108. Furthermore, when the potential of the node 118 becomes V2+Vb, the transistor 110 is turned on. Furthermore, when the transistor 110 is turned on, the potential 204 of the node 117 is This is equivalent to the potential V2 given via 4C.

[0113] The potential 206 of the node 119 becomes V2 due to the capacitive coupling of the capacitor 112. Furthermore, when the potential 206 of the node 119 becomes V2, the transistor 111 and the transistor 115 is in the off state.

[0114] Furthermore, when the potential 204 of the node 117 becomes V2, the transistors 113 and 114 The inverter 114 is turned off.

[0115] Furthermore, at this time, the potential of the output signal 207 outputted through the terminal 105 is The value of the potential V2 is equal to the potential V1 given via the potential V2. The above is the operation in the fifth period.

[0116] As described above, the driving circuit in this embodiment is configured to During the selection period, the operations of the fourth and fifth periods are repeated multiple times. Since a predetermined potential is applied to the node 117 during any period of the non-selection period, This can prevent the node 117 from being in a floating state, thereby reducing the influence of noise. This can reduce the number of pulses, thereby suppressing malfunctions.

[0117] In the operation of the driving circuit in this embodiment, in the fourth period and the fifth period, By turning on different transistors, a predetermined value of potential is applied to node 117. Therefore, it is possible to reduce the number of transistors that are prone to deterioration, such as transistors whose semiconductor layer is made of amorphous semiconductor. Even when transistors are used, it is possible to suppress the deterioration of each transistor. This reduces the timing discrepancy of the transistor switching operation due to deterioration. Therefore, malfunctions can be suppressed.

[0118] In the fourth and fifth periods shown in FIG. In the conventional drive circuit, only one transistor of the transistor 111 is provided to control the potential of the node 117. In the case of the circuit, both the transistor 110 and the transistor 111 are provided. The result of circuit calculation for the case of a driver circuit according to one embodiment of the present invention, which controls the potential of the node 117 by The calculation was performed using a SPICE circuit simulator. As an example, let's assume that all the transistors in the flip-flop circuit are N-type transistors, and V 2=0V.

[0119] 25A shows the state of the transistor 11 in the fourth and fifth periods. 0 and transistor 111 are used to control node 117. 25(B) is a diagram showing a change in the potential (voltage) of the node 117 during the fourth period. In the fifth period, both the transistors 110 and 111 1 shows the change in the potential (voltage) of node 117 when node 117 is controlled using a In addition, in Fig. 25(A) and Fig. 25(B), the unit of voltage is an arbitrary unit ( AU: Arbitrary Unit).

[0120] The noise generated in the fourth and fifth periods after the reset period is mainly the noise shown in Figure 1. The parasitic capacitance of the transistor 114 affects the node 117. In this circuit, the transistors are controlled using signals synchronized with a single clock signal. After the lock period, the floating state is entered during either the fourth period or the fifth period. When this happens, noise is added to the normal potential, and as shown in Figure 25(A), In FIG. 25(A), the potential (voltage) of the node 117 fluctuates by about 0.4 every fifth period. cormorant.

[0121] On the other hand, in a driving circuit according to one aspect of the present invention, two clock signals having opposite phases are used. The transistors 110 and 111 are controlled using signals synchronized with the respective signals. Therefore, the predetermined potential is applied without being in a floating state during both the fourth period and the fifth period. Therefore, as shown in FIG. 25(B), the change in the potential of the node 117 is 0.2 or less. This shows that there is little fluctuation, that is, the influence of noise is small. In each of the fourth and fifth periods, the transistor 110 or the transistor By turning on the node 111, a predetermined potential is applied to the node 117. It can be seen that the influence of noise can be reduced.

[0122] Furthermore, in this embodiment, a driver circuit according to one embodiment of the present invention is configured using a structure different from that shown in FIG. Another configuration of the driver circuit in this embodiment will be described with reference to FIG. 3 is a circuit diagram showing an example of the configuration of the drive circuit of this embodiment.

[0123] Another configuration of the driver circuit in this embodiment shown in FIG. 3 is, in addition to the circuit configuration shown in FIG. It has a transistor 120 and a terminal 104H.

[0124] 3, the same reference numerals as in FIG. 1 are used to denote the drive circuits in FIG. 1. Since it is the same as the above, the explanation will be omitted.

[0125] The transistor 120 has a gate terminal electrically connected to the terminal 100 and a source terminal and One of the drain terminals is electrically connected to the gate terminal of the transistor 111, and the other of the source terminals is The other of the drain terminals is electrically connected to terminal 104H.

[0126] The same potential as that of the terminals 104A to 104G in FIG. 1 is applied via the terminal 104H. 1 is used to refer to the explanation of FIG. 1. 104.

[0127] The transistor 120 is connected to the terminal 104H in accordance with the signal input via the terminal 100. The terminal 104H and the node 119 are electrically connected to each other. By setting the potential of node 119 to V1 or V2.

[0128] Next, the operation of the drive circuit shown in Fig. 3 will be described. Regarding the operation of the transistor 120, only the operation of the transistor 120 will be described, and the operation of the elements of the driving circuit shown in FIG. The same parts will be referred to as appropriate in the description of FIG. 1. As an example of the operation of a circuit, the transistors in a flip-flop circuit are all N-type transistors. The following describes the case where:

[0129] In the first period, a first control signal 201 in a high state is input via the terminal 100. At this time, the transistor 120 is turned on.

[0130] When the transistor 120 is turned on, the potential of the node 119 is Therefore, the potential V2 is equal to the potential V1 of the transistor 111. 5 is in the OFF state.

[0131] Then, during the second to fifth periods, the first control signal, which is in a low state, is transmitted via the terminal 100. A signal 201 is input, and at this time, the transistor 120 is turned off.

[0132] As described above, the driving circuit shown in FIG. 3 has the effect of the first During this period, the first control signal 201 is input directly to the transistor 120, and the transistor 1 By turning on the transistor 20, the potential of the node 119 is more reliably maintained during the first period. can be set to a potential V2.

[0133] Furthermore, in this embodiment, a configuration different from that shown in FIGS. 1 and 3 is used to implement the present invention. Another configuration of the drive circuit in this embodiment is shown in FIG. 4 is a circuit diagram showing an example of the circuit configuration of the drive circuit in this embodiment. be.

[0134] The configuration of the drive circuit shown in FIG. 4 includes terminals 103C, 104I, and and terminal 104J, terminal 121, transistor 122, transistor 123, and transistor It has sta 124.

[0135] In FIG. 4, the elements having the same reference numerals as those in FIG. 1 are the same as those in FIG. 1. Since the elements are the same as those in the operation circuit, the explanation in FIG. 1 is used.

[0136] The transistor 122 has a gate terminal connected to the source and drain terminals of the transistor 106. The other of the terminals is electrically connected to the terminal 103C, and one of the source terminal and the drain terminal is electrically connected to the terminal 103D. The other of the source terminal and the drain terminal is electrically connected to terminal 121.

[0137] The gate terminal of the transistor 123 is electrically connected to the gate terminal of the transistor 111. one of the source and drain terminals of the transistor 122 is connected to the source and drain terminals of the transistor 122. The other of the source and drain terminals is electrically connected to terminal 104. Electrically connected to I.

[0138] The transistor 124 has a gate terminal electrically connected to the terminal 102B and a source terminal One of the source and drain terminals of the transistor 122 is connected to the other of the source and drain terminals of the transistor 122. The other of the source terminal and the drain terminal is electrically connected to terminal 104J. can be.

[0139] The same signals as those input through terminals 103A and 103B in FIG. 1 are input through terminal 103C. 1 is used for the purpose of illustration. , and can be connected to form a single terminal 103.

[0140] Terminals 104A to 104J in FIG. Since the same potential as that applied via G is applied, the explanation in FIG. The terminals 104A to 104G, and the terminals 104I and 104J are electrically connected. It is also possible to combine them into one terminal 104.

[0141] The flip-flop circuit also receives the signal generated in the flip-flop circuit via a terminal 121. The generated signal is output.

[0142] The transistor 122 is connected between the terminal 103C and the terminal 121 in accordance with the potential of the node 117. and the potential of the signal input through terminal 103C and the potential of the signal output through terminal 121 are brought into a conductive state. In particular, when the potential of node 117 is V1 In this case, when the signal input via the terminal 103C changes from a low state to a high state, The transistor 122 is turned on as the potential of the signal output via the terminal 121 rises. It has the function of raising the potential of the node 117. This is what is called bootstrap. The bootstrap is connected to the gate terminal of the transistor 122, the source terminal, and the drain terminal. This is often done by parasitic capacitance between the terminals.

[0143] The transistor 123 is connected between the terminal 104I and the terminal 121 in accordance with the potential of the node 119. By bringing the terminal 104I and the terminal 121 into a conductive state, As a result, the potential of the signal output via the terminal 121 is set to V1 or V2.

[0144] The transistor 124 is connected to the terminal 102B in accordance with the signal input via the terminal 102B. The terminal 104J has a function of controlling the conduction between the terminal 104J and the terminal 121, and the terminal 104J and the terminal 121 are electrically connected. By setting the terminal 121 to this state, the potential of the signal output via the terminal 121 is set to V1 or V2. will be done.

[0145] Next, the operation of the driving circuit in Fig. 4 will be described with reference to Fig. 5. Fig. 5 shows the present embodiment. 4 is a timing chart showing an example of the operation of the drive circuit in FIG. The operation of the drive circuit is as follows: transistor 122, transistor 123, and transistor 1 Only the operation of 24 will be explained, and the parts that are the same as the operation of the elements of the drive circuit shown in Figure 1 will be explained. The explanation of the operation of the driving circuit in Fig. 1 will be used as appropriate. Here, the first clock signal is input. As an example of the operation of a circuit, the transistors in a flip-flop circuit are all N-type transistors. The following describes the case where:

[0146] During the first period, in addition to the operation of the circuit shown in FIG. 1, a low state is output via the terminal 103C. The first clock signal 202 is input. At this time, the transistor 124 is turned on. .

[0147] At this time, the potential 204 of the node 117 is V1-Vth 106 and transistor 113 Furthermore, when the transistor 113 is turned on, the transistor 123 It will be in the off state.

[0148] Also, the potential 204 of the node 117 is V1-Vth 106 When the transistor 122 It will be in the on state.

[0149] Furthermore, at this time, the potential of the output signal 209 outputted through the terminal 121 is The potential V2 of the first clock signal applied via terminal 104J or the potential V3 of the first clock signal applied via terminal 104J The potential V1 becomes equal to the potential V2 that is applied to the transistor 1. The above is the operation in the first period.

[0150] Next, in the second period, in addition to the operation of the circuit shown in FIG. 1, A first clock signal 202 is input. At this time, the transistor 124 is in the off state. become.

[0151] At this time, the potential 204 of the node 117 is V1-Vth 106 The transistor When transistor 113 is in the on state, transistor The inverter 123 remains in the off state.

[0152] Furthermore, at this time, the node 117 remains in a floating state, and the potential 204 of the node 117 is V1-Vth 106 It remains as it is.

[0153] Furthermore, the potential 204 of the node 117 is V1-Vth 106 remains the same, and transistor 1 The potential of one of the source terminal and drain terminal of 22 is equal to the potential V1 of the first clock signal 202. When this occurs, the potential 204 of the node 117 is boosted to the potential of the transistor 122 by bootstrap. The capacitance coupling due to the parasitic capacitance between the gate terminal and the other of the source and drain terminals Therefore, the potential 204 of the node 117 rises in accordance with the potential of the output signal 209. , the sum of the potential V1 of the first clock signal 202 and the threshold voltage of the transistor 114, and is the potential V1 of the first clock signal 202 and the threshold voltage (Vth 12 2), that is, V1 + Vth 114 +Va, or V1+Vth 122 It rises to +Va (Va is any positive value).

[0154] Furthermore, the potential 204 of the node 117 is V1+Vth 114 +Va, or V1+Vth1 22 When +Va, transistor 122 remains on.

[0155] Furthermore, at this time, the potential of the output signal 209 outputted through the terminal 121 is The potential V1 of the first clock signal 202 input via the It is an operation during a period.

[0156] Next, in the third period, in addition to the operation of the circuit shown in FIG. 1, A first clock signal 202 is input. At this time, the transistor 124 is turned on. become.

[0157] At this time, the potential 205 of the node 118 becomes V2+Vb, and the transistor 110 is turned on. The potential 204 of the node 117 becomes equal to the potential V2. When 204 is at potential V2, transistor 122 is turned off.

[0158] Furthermore, the potential 206 of the node 119 remains equal to the potential V2. When the potential 206 is V2, the node 119 is floating. When , transistor 123 remains in the off state.

[0159] Furthermore, at this time, the potential of the output signal 209 outputted through the terminal 121 is The voltage V1 becomes equal to the potential V2 applied via the potential V2. The above is the operation in the third period.

[0160] Next, in the fourth period, in addition to the operation of the circuit shown in FIG. 1, a high state is output via the terminal 103C. At this time, the transistor 116 is turned off. do.

[0161] At this time, the potential 206 of the node 119 becomes V2+Vc, and the potential 206 of the node 119 becomes When V2+Vc, the transistor 123 is turned on.

[0162] Furthermore, the potential 204 of the node 117 becomes the potential V2 given via the terminal 104D. When the potential of the node 117 becomes V2, the transistor 122 is turned off.

[0163] Furthermore, at this time, the potential of the output signal 209 outputted through the terminal 121 is The value of the potential V2 is equal to the potential V1 given via the potential V2. The above is the operation in the fourth period.

[0164] Next, in the fifth period, in addition to the operation of the circuit shown in FIG. 1, A first clock signal 202 is input. At this time, the transistor 124 is turned on. become.

[0165] At this time, the potential of the node 118 becomes V2+Vb, and the transistor 110 is turned on. When the transistor 110 is turned on, the potential 204 of the node 117 is connected to the terminal 104C. The potential V2 is equal to the potential V2 applied via the

[0166] Furthermore, when the potential 204 of the node 117 becomes V2, the transistor 122 is turned off. .

[0167] In addition, the potential 206 of the node 119 becomes V2, and the transistor 123 is turned off. .

[0168] Furthermore, at this time, the potential of the output signal 209 outputted through the terminal 121 is The voltage V1 becomes equal to the potential V2 applied via the resistor R1. The above is the operation in the fifth period.

[0169] As mentioned above, the drive circuit in Figure 4 has the effect of the circuit configuration shown in Figure 1, as well as the output By using multiple signals, one output signal is sent to the next flip-flop circuit. The other output signal is output to the gate terminal of the transistor of the pixel, This allows output signals with small deviations to be sent to the drop circuit, thereby suppressing malfunctions. Cut.

[0170] Furthermore, in this embodiment, a configuration in which the configuration in FIG. 3 and the configuration in FIG. 4 are combined is provided. Another configuration of the driver circuit in this embodiment will be described with reference to FIG. 6 is a circuit diagram showing another configuration of the drive circuit of the present embodiment.

[0171] Another configuration of the driving circuit in this embodiment shown in FIG. 6 is, in addition to the circuit configuration shown in FIG. Terminal 103D, terminal 104K, terminal 104L, terminal 104M, terminal 125, transistor 126, a transistor 127, a transistor 128, and a transistor 129.

[0172] In FIG. 6, elements having the same reference numerals as those in FIG. 1 are the same as those in the driving circuit in FIG. Since the elements are the same as those in the circuit, the explanation of each element in FIG. 1 is used.

[0173] 6, the terminal 103D corresponds to the terminal 103C in FIG. 4, and the terminal 104K corresponds to the terminal 103C in FIG. corresponds to the terminal 104H in FIG. 3, and the terminal 104L corresponds to the terminal 104I in FIG. 4. The terminal 104M corresponds to the terminal 104J in FIG. 3. The transistor 126 corresponds to the transistor 120 in FIG. The transistor 127 corresponds to the transistor 122 in FIG. 4, and transistor 129 corresponds to transistor 123 in FIG. The explanation of each element is given in the explanation of each element in FIG. Using Ming as a reference.

[0174] The operation of the drive circuit in FIG. 6 is the same as that of the drive circuits in FIGS. 3 and 4. Since this is a combination, the explanation of the operation of the drive circuit in FIGS. 3 and 4 is used.

[0175] By using the configuration shown in FIG. 6, the effectiveness of the drive circuits shown in FIGS. 3 and 4 can be improved. The same effect can be obtained.

[0176] (Embodiment 2) In this embodiment, a driver circuit having a different configuration from that of the first embodiment will be described.

[0177] The driving circuit in this embodiment is a shift register consisting of a plurality of flip-flop circuits. It has a

[0178] Furthermore, an example of the circuit configuration of the flip-flop circuit in the driver circuit of this embodiment will be described. This will be explained with reference to Fig. 7. Fig. 7 shows a flip-flop circuit in the driver circuit of this embodiment. FIG. 2 is a circuit diagram showing an example of a circuit configuration of the

[0179] The flip-flop circuit shown in FIG. 7 includes a terminal 500, a terminal 501, a terminal 502, and a terminal terminal 503, terminal 504, terminal 505, transistor 506, and transistor 507 , a transistor 508, a transistor 509, a capacitor 510, and a transistor 5 11, a transistor 512, a transistor 513, and a transistor 514. do.

[0180] In this embodiment, terminals 502A and 502B are shown as terminals 502. However, the present invention is not limited to this, and the terminal 502A and the terminal 502B may be electrically connected to each other to form a single In this embodiment, the terminal 503 may be the terminal 502. 3A and terminal 503B are shown, but are not limited thereto, and terminal 503A and terminal 503 B can be electrically connected to form one terminal 503.

[0181] In this embodiment, the terminals 504 are terminals 504A to 504E. However, the present invention is not limited to this, and the terminals 504A to 504E may be electrically connected to each other to form a single It can also be the terminal 504.

[0182] Transistor 506 has a gate terminal electrically connected to terminal 502A and a source terminal One of the drain terminals is electrically connected to terminal 500 .

[0183] The transistor 507 has a gate terminal electrically connected to the terminal 500 and a source terminal and one of the drain terminals is electrically connected to the gate terminal of the transistor 507, The other of the source and drain terminals is the other of the source and drain terminals of the transistor 506. Although not shown for convenience, in this embodiment, the transistor By adopting a configuration in which the capacitor 507 is not provided, the circuit area can be reduced.

[0184] The transistor 508 has a gate terminal electrically connected to the terminal 501 and a source terminal and drain terminals of the transistor 507. The other of the source terminal and the drain terminal is electrically connected to terminal 504A. Although not shown for convenience, the flip-flop circuit in the driver circuit of this embodiment In the circuit, the transistor 508 is not provided, thereby reducing the circuit area. It is also possible.

[0185] The capacitive element 510 has at least two terminals, one of which is electrically connected to the terminal 503A. Connected.

[0186] The gate terminal of the transistor 509 is electrically connected to the other terminal of the capacitor 510. and one of the source and drain terminals is connected to the source and drain terminals of transistor 506. The other of the source and drain terminals is electrically connected to terminal 504B. are electrically connected.

[0187] The gate terminal of the transistor 511 is connected to the source and drain terminals of the transistor 506. The other of the source and drain terminals is electrically connected to the transistor 5. 09, and the other of the source terminal and the drain terminal is connected to terminal 504. C is electrically connected.

[0188] The gate terminal of transistor 512 is connected to the source and drain terminals of transistor 506. The other of the source and drain terminals is electrically connected to terminal 503B. The other of the source terminal and the drain terminal is electrically connected to the terminal 505. Although not shown for convenience, the flip-flop circuit in the driver circuit of this embodiment A separate path is provided between the gate terminal of transistor 512 and the other of the source and drain terminals. A capacitance element may also be provided along the line.

[0189] The gate terminal of the transistor 513 is electrically connected to the gate terminal of the transistor 509. one of the source and drain terminals of the transistor 512 is connected to the source and drain terminals of the transistor 513. The other of the source and drain terminals is electrically connected to terminal 504. Electrically connected to D.

[0190] The transistor 514 has a gate terminal electrically connected to the terminal 502B and a source terminal One of the source and drain terminals of the transistor 512 is connected to the other of the source and drain terminals of the transistor 512. The other of the source terminal and the drain terminal is electrically connected to terminal 504E. can be.

[0191] The other of the source terminal and the drain terminal of the transistor 506 and the transistor 50 7, transistor 508, transistor 509, transistor 511, and transistor The connection point between the capacitor element 510 and the transistor 512 is called a node 515. The connection point between 509, transistor 511, and transistor 513 is called node 516. cormorant.

[0192] The flip-flop circuit receives a first control signal via a terminal 500. The second control signal is input via 501. The first control signal and the second control signal are Digital signals each having two potential states, a high state and a low state, can be used. When a digital signal is used, the first control signal or the second control signal is high. When in the high state (also called the high level), the first voltage is applied via the terminal 500 or the terminal 501. The first control signal or the second control signal is a potential of a predetermined value as a potential (also referred to as V1). When the first control signal or the second control signal is inputted and inputted, the first control signal or the second control signal is in a low state (low level The second potential (also referred to as V2) is connected to the terminal 500 or the terminal 501. a first control signal having a potential lower than the predetermined potential in the high state; The second control signal is input. The potential values ​​in the high and low states are determined by, for example, The threshold voltage of the resistor can be appropriately set in consideration of the value of the high state and the low state. The potential difference between the state is greater than the absolute value of the threshold voltage of the transistor in the flip-flop circuit. It is preferable to set the potential values ​​in the high and low states so that

[0193] 7, the flip-flop circuit shown in FIG. A first phase clock signal (also called CK) is transmitted through the signal) or a second phase clock signal (also called a second clock signal, or CK The first clock signal and the second clock signal are respectively It has two potential values, high and low, and when it is in the high state (also called the high level), When a clock signal having a first potential (also referred to as V1) is input and the clock signal is in a low state (low level), A clock signal at a second potential (also called V2) is input to the first potential (also called V3). The potentials of the first clock signal and the second clock signal when in a high state are It is preferable that the potentials of the first control signal and the second control signal are equal to each other. The potentials of the first clock signal and the second clock signal in the low state are It is preferable that the potential of the first control signal and the second control signal is equal to each other. The value of the potential in the low state is determined appropriately in consideration of, for example, the threshold voltage of the transistor. For example, the potential difference between the high state and the low state is set to a value that is appropriate for the flip-flop circuit. In the high and low states, the absolute value of the threshold voltage of the transistor in It is preferable to set the value of the potential at

[0194] The first clock signal and the second clock signal have different phases. are in a reciprocal relationship, and for example, when the first clock signal is in a high state during a predetermined period, When the second clock signal is in a low state and the first clock signal is in a low state, The second clock signal is in a high state.

[0195] The flip-flop circuit also includes a terminal 503 (also referred to as a terminal 503A and a terminal 503B). ) through which the first clock signal or the second clock signal is input. The clock signal input via terminal 2 and the clock signal input via terminal 503 are For example, when the first clock signal is input via terminal 502, A second clock signal is input via terminal 503, and a second clock signal is output via terminal 502. When a signal is input, the first clock signal is input via terminal 503 .

[0196] The flip-flop circuit also includes a terminal 504 (also referred to as terminals 504A to 504E). At this time, the potential of the predetermined value is given via, for example, V1 or can be V2, i.e., the high side of a digital signal such as a clock signal or a control signal. The potential can be set to a value equivalent to the potential in the high or low state.

[0197] The transistor 506 operates in accordance with the signal input via the terminal 502A. 0 and node 515, and By turning on the terminal 500, the potential of the signal input through the terminal 500 and the node 515 The potential of the transistor 506 is set to a value equal to that of the transistor 509. It has the function of turning off when in the on state.

[0198] The transistor 507 is connected to the terminal 500 in accordance with the signal input via the terminal 500. and a function of controlling the conduction between the terminal 500 and the node 515. By setting the state, the potential of node 515 is set to V1 or V2, and then the non-conductive By going into the on state, node 515 goes into a floating state.

[0199] The transistor 508 operates in accordance with the signal input via the terminal 501. A and node 515, and By setting the state, the potential of node 515 is set to V1 or V2.

[0200] The transistor 509 connects the terminal 504B and the node 511B according to the potential of the node 516. 5, and brings the terminal 504B and the node 515 into a conductive state. The potential of the node 515 is set to V1 or V2 by the transistor 509. has the function of being turned off when the transistor 506 is turned on.

[0201] The capacitance element 510 is connected to the capacitor through capacitive coupling in accordance with the signal input via the terminal 503A. For example, the potential of the node 516 is changed by the input through the terminal 503A. When the signal applied to the capacitor 510 changes from a low state to a high state, the capacitor 510 The potential of the node 516 is set to V1. On the other hand, the signal input via the terminal 503A is When the capacitor 510 goes from a high state to a low state, the capacitor 510 The potential is set to V1 or V2.

[0202] The transistor 511 connects the terminal 504C and the node 51D according to the potential of the node 515. 6, and brings the terminal 504C and the node 516 into a conductive state. sets the potential of node 516 to V1 or V2.

[0203] The transistor 512 is connected to the terminal 503B and the terminal 505 according to the potential of the node 515. By bringing terminal 503B and terminal 505 into a conductive state, Therefore, the potential of the signal input via the terminal 503B and the potential of the signal output via the terminal 505 The potential of the transistor 512 is set to a value equivalent to that of the N-type transistor. When the potential of the node 515 is V1, the signal input through the terminal 503B is When the state changes from low to high, the potential of the signal output via terminal 505 rises. Therefore, it has the function of increasing the potential of the node 515. This is called bootstrap. However, the bootstrap is connected between the gate terminal and the source terminal of the transistor 512. This is often achieved by a parasitic capacitance between the drain terminal and the other.

[0204] The transistor 513 is connected to the terminal 504D and the terminal 505D according to the potential of the node 516. By bringing terminal 504D and terminal 505 into a conductive state, As a result, the potential of the signal output via the terminal 505 is set to V1 or V2.

[0205] The transistor 514 is connected to the terminal 502B in accordance with the signal input via the terminal 502B. and a function of controlling the conduction between terminal 504E and terminal 505. By setting the terminal 505 to this state, the potential of the signal output via the terminal 505 is set to V1 or V2. It is determined.

[0206] The driver circuit in this embodiment is composed of transistors of the same conductivity type. Therefore, the manufacturing process can be simplified. Furthermore, it is possible to reduce the number of semiconductor devices and improve the yield. In the driving circuit of this embodiment shown in FIG. The transistors can be N-type or P-type transistors.

[0207] Next, the operation of the driving circuit shown in FIG. 7 will be described with reference to FIG. 10 is a timing chart showing the operation of the operation circuit. A first clock signal is input via terminal 3, and a second clock signal is input via terminal 502. Here, as an example of the operation of the driving circuit shown in FIG. This section explains the case where all the transistors in a flip-flop circuit are N-type transistors. do.

[0208] As shown in FIG. 8, the operation of the driving circuit in FIG. 7 is such that a predetermined operation is performed for a certain period of time. This is repeated. The period is mainly divided into a selection period and a non-selection period. The period and non-selection period are the first period, the second period, the third period, the fourth period, and the fifth period. In FIG. 8, the first period, the third period, the fourth period, and the fifth period are is a non-selection period, and the second period is a selection period.

[0209] First, in the first period, a first control signal 601 in a high state is input via the terminal 500. A second control signal 607 in a low state is input via the terminal 501, and a second control signal 607 in a low state is input via the terminal 502. A second clock signal 603 in a high state is input via When the first clock signal 602 is input, the transistor 506 The transistor 507 and the transistor 514 are turned on, and the transistor 508 is turned off. It becomes a state of 'fu'.

[0210] When the transistor 506 and the transistor 507 are turned on, the potential 6 of the node 515 04 is input via the terminal 502A to the potential V1 of the second clock signal 603. The threshold voltage (Vth 506 (also called) V1-Vth5 06 or the potential V1 of the first control signal 601 input via the terminal 500 to the The threshold voltage (Vth 507 (also called) V1-Vth5 07 The potential at node 515 rises until it reaches V1-Vth. 506 or V1-Vth 507 When the threshold voltage of the transistor 506 is It is preferable that the value voltage of the transistor 507 and the threshold voltage of the transistor 507 are equal to each other. For example, the potential of the node 515 in the second period is V1-Vth 507 Explained as do.

[0211] Furthermore, the potential 604 of the node 515 is V1-Vth 507 Then, transistor 511 And transistor 512 is turned on.

[0212] Furthermore, when the transistor 511 is turned on, the potential 605 of the node 516 is The potential of node 516 becomes equal to the potential V2 given via C. Then, the transistor 509 and the transistor 513 are turned off.

[0213] Furthermore, at this time, the potential of the output signal 606 outputted through the terminal 505 is The potential V2 of the first clock signal 602 input via the terminal 504B or the potential V3 of the first clock signal 602 input via the terminal 504C is This has a value equivalent to the potential V2 obtained from the first period. The above is the operation in the first period.

[0214] Next, in the second period, the first control signal 601 in the low state is input via the terminal 500. A second control signal 607 in a low state is input via the terminal 501, and a second control signal 607 in a low state is input via the terminal 502. A second clock signal 603 in a low state is input via the terminal 503A and the terminal 503B. A first clock signal 602 in a high state is input via 03B. Transistor 506, transistor 507, and transistor 514 are turned off. Register 508 remains in the off state.

[0215] At this time, the potential 604 of the node 515 is V1-Vth 507 The transistor 511 remains in the ON state. Furthermore, the potential 604 of the node 515 is V1-Vth 507 When the potential 605 of the node 516 remains at the potential V 2, and transistor 509 and transistor 513 remain off.

[0216] Furthermore, as described above, transistor 506, transistor 507, transistor 508 When the transistors 509 and 513 are off, the node 515 The potential 604 of node 515 is left floating and is V1-Vth 507 remains .

[0217] Furthermore, the potential 604 of the node 515 is V1-Vth 507 remains, and transistor 5 The potential of one of the source terminal and drain terminal of the first clock signal 602 is V1 When this occurs, the potential of the output signal 606 output via the terminal 505 rises. Since node 515 is floating, the potential 604 of node 515 is , a parasitic voltage between the gate terminal of the transistor 512 and the other of the source and drain terminals The potential rises in accordance with the potential of the output signal 606 due to capacitive coupling.

[0218] The potential 604 of the node 515 is the potential V1 of the first clock signal 602 and the potential V2 of the transistor 512 threshold voltage (Vth 512 (also called) and V1 +Vth 512+Va (Va is any positive value). At this time, transistor 51 2 remains on.

[0219] Furthermore, at this time, the potential of the output signal 606 outputted through the terminal 505 is The value of the potential V1 input via the MOS transistor 11 is equal to the value of the potential V1 input via the MOS transistor 11. The above is the operation in the second period.

[0220] Next, in the third period, the first control signal 601 in the low state is input via the terminal 500. A second control signal 607 in a high state is input via the terminal 501, and a second control signal 607 in a high state is input via the terminal 502. A second clock signal 603 in a high state is input via terminals 502A and 502B, and a second clock signal 603 in a high state is input via terminals 502B and 502C. A first clock signal 602 in a low state is input via terminals 503A and 503B. At this time, the transistors 506, 508, and 514 are in the ON state. and transistor 507 remains off.

[0221] When the transistor 506 and the transistor 508 are turned on, the potential of the node 515 The potential V2 of the first control signal 601 input via the terminal 500 or the terminal 504A The potential V2 is equal to the potential V1 applied via the

[0222] Furthermore, when the potential 604 of the node 515 becomes V2, the transistors 511 and 512 The transistor 512 is turned off. In many cases, the first clock signal 602 goes low and then goes off. Therefore, the potential 604 of the node 515 is delayed or corrupted compared to the first clock signal 602. This is because the transition occurs after the first clock signal 602 goes low. When the switch 511 is turned off, a value equivalent to the potential V2 applied via the terminal 504C is applied. Node 516 is left floating while being held.

[0223] Furthermore, when node 516 is floating, transistor 509 and transistor 51 3 remains in the off state.

[0224] Furthermore, the capacitance element 510 receives the first clock signal 60 input via the terminal 503A. The potential difference between the potential at node 2 and the potential at node 516, i.e., the first clock signal in a low state, A potential difference is maintained between the potential of signal 602 and potential V2 applied via terminal 504C.

[0225] Furthermore, at this time, the potential of the output signal 606 outputted through the terminal 505 is The value of the potential V2 is equal to the potential V1 given via the potential V2. The above is the operation in the third period.

[0226] Next, in the fourth period, the first control signal 601 in the low state is input via the terminal 500. A second control signal 607 in a low state is input via the terminal 501, and a second control signal 607 in a low state is input via the terminal 502. A second clock signal 603 in a low state is input via terminals A and 502B, and a terminal A first clock signal 602 in a high state is input via terminals 503A and 503B. At this time, the transistors 506, 508, and 514 are turned off. state, and transistor 507 remains off.

[0227] At this time, the potential 605 of the node 516 is V2+Vb due to the capacitive coupling of the capacitor 510. Vb is greater than the threshold voltage of the transistor 509 or the threshold voltage of the transistor 513. It is preferable that V is larger than V1-V2.

[0228] Furthermore, when the potential 605 of the node 516 becomes V2+Vc, the transistor 509 and the transistor The transistor 513 is turned on, and the transistors 509 and 513 are turned on. When this occurs, the potential 604 of the node 515 becomes the potential V2 provided via the terminal 504B, becomes equal to the potential V2 applied via terminal 504D.

[0229] Furthermore, when the potential 604 of the node 515 becomes V2, the transistor 511 and the transistor 512 goes to the off state.

[0230] Furthermore, at this time, the potential of the output signal 606 outputted through the terminal 505 is The value of the potential V2 is equal to the potential V1 given via the potential V2. The above is the operation in the fourth period.

[0231] Next, in the fifth period, the first control signal 601 in the low state is input via the terminal 500. A second control signal 607 in a low state is input via the terminal 501, and a second control signal 607 in a low state is input via the terminal 502. A second clock signal 603 in a high state is input via terminals 502A and 502B, and a second clock signal 603 in a high state is input via terminals 502B and 502C. A first clock signal 602 in a high state is input via terminals 503A and 503B. At this time, the transistors 506 and 514 are turned on. Transistor 507 and transistor 508 remain in the off state.

[0232] At this time, the potential 605 of the node 516 becomes V2 due to the capacitive coupling of the capacitor 510. Furthermore, when the potential 605 of the node 516 becomes V2, the transistor 509 and the transistor 513 goes to the off state.

[0233] Furthermore, when the potential 604 of the node 515 becomes V2, the transistors 511 and 512 The inverter 512 is turned off.

[0234] Furthermore, at this time, the potential of the output signal 606 outputted through the terminal 505 is The voltage V1 becomes equal to the potential V2 applied via the resistor R1. The above is the operation in the fifth period.

[0235] In the operation of the driving circuit in this embodiment, the fourth period and the fifth period are as follows: This is repeated multiple times during the non-selection period after the third period. In either period, a predetermined potential is applied to the node 515, so that the node 515 This can prevent the capacitor from floating, thereby reducing the effects of noise. This makes it possible to suppress malfunctions.

[0236] In the operation of the driving circuit in this embodiment, in the fourth period and the fifth period, Different transistors (in this embodiment, the transistors 506 and 509) By turning on the node 515, a predetermined potential can be applied. Even when a transistor having an amorphous semiconductor semiconductor layer is used, This can suppress the deterioration of the transistors. Since the noise can be reduced, malfunctions can be suppressed.

[0237] Furthermore, the driver circuit in this embodiment has fewer elements than the configuration of the above embodiment. Therefore, the circuit area can be reduced.

[0238] Furthermore, in this embodiment, a driver circuit according to one embodiment of the present invention is used with a configuration different from that shown in FIG. Another configuration of the driver circuit in this embodiment will be described with reference to FIG. 9 is a circuit diagram showing an example of the configuration of a drive circuit in this embodiment.

[0239] The driving circuit shown in FIG. 9 has the circuit configuration shown in FIG. 7, and further includes a terminal 504F and a transistor It has a transistor 517.

[0240] In the drive circuit shown in FIG. 9, the same reference numerals as those in the drive circuit shown in FIG. 7 are used. The above is the same as the drive circuit shown in FIG. 7, and therefore the description thereof will be omitted.

[0241] The transistor 517 has a gate terminal electrically connected to the terminal 500 and a source terminal and One of the drain terminals is electrically connected to the gate terminal of the transistor 509, and the other of the source terminals is The other of the drain terminals is electrically connected to terminal 504F.

[0242] In the driving circuit shown in FIG. 9, the terminals 504A to 504F shown in FIG. A potential equivalent to that of 504E is applied to the terminals 504A to 504F. It is also possible to combine them into one terminal 504.

[0243] The transistor 517 is connected to the terminal 504F according to the signal input through the terminal 500. and the terminal 504F and the node 516 are electrically connected to each other. This sets the potential of node 516 to V1 or V2.

[0244] Next, the operation of the drive circuit shown in Fig. 9 will be described. Regarding the operation of the transistor 517, only the operation of the transistor 517 will be explained. The operation is the same as that of the driving circuit shown in FIG. 7, so the explanation will be omitted. As an example of the operation of the driving circuit shown in Figure 9, the transistors in the flip-flop circuit are all N. The case of a MOSFET transistor will be described.

[0245] In the first period, a first control signal 601 in a high state is input via the terminal 500. At this time, the transistor 517 is turned on.

[0246] When the transistor 517 is turned on, the potential of the node 516 is applied via the terminal 504F. The potential V2 obtained by the voltage drop is equal to the potential V2.

[0247] Then, during the second to fifth periods, the first control signal, which is in a low state, is transmitted via the terminal 500. A signal 601 is input, and the transistor 517 is turned off.

[0248] As described above, the driving circuit shown in FIG. 9 has the following advantages in addition to the advantages of the circuit configuration shown in FIG. In the first period, the first control signal 601 is input directly to the transistor 517. By turning on the transistor 517, the potential of the node 516 is more securely maintained during the first period. In fact, it can be set to potential V2.

[0249] Furthermore, in this embodiment, a configuration different from that shown in FIGS. 7 and 9 is used to implement the present invention. Another configuration of the drive circuit in this embodiment is shown in FIG. 10 is a circuit diagram showing an example of the circuit configuration of the driver circuit in this embodiment. Figure.

[0250] The configuration of the drive circuit shown in FIG. 10 includes the terminal 503C, the terminal 50 4G, terminal 504H, terminal 518, transistor 519, transistor 520, and transistor The sensor has a transistor 521.

[0251] 10, the elements having the same reference numerals as those in FIG. 7 are the same as those in FIG. Since the elements are the same as those in the operating circuit, the explanation of each element in FIG. 7 is used.

[0252] The transistor 519 has a gate terminal connected to the source and drain terminals of the transistor 506. The other of the terminals is electrically connected to the terminal 503B, and one of the source terminal and the drain terminal is electrically connected to the terminal 503C. are connected to the network.

[0253] The gate terminal of the transistor 520 is electrically connected to the gate terminal of the transistor 509. one of the source and drain terminals of the transistor 519 is connected to the source and drain terminals of the transistor 519. The other of the source and drain terminals is electrically connected to terminal 504. Electrically connected to G.

[0254] The gate terminal of the transistor 521 is electrically connected to the gate terminal of the transistor 514. one of the source and drain terminals of the transistor 519 is connected to the source and drain terminals of the transistor 519. The other of the source and drain terminals is electrically connected to terminal 504. Electrically connected to H.

[0255] The transistor 519 connects the terminal 503C and the terminal 518 in accordance with the potential of the node 515. and the potential of the signal input through terminal 503C and the potential of the signal output through terminal 518 are set in a conductive state. In particular, when the potential of node 515 is V1 In this case, the potential of the signal input via the terminal 503C changes from a low state to a high state. Then, the transistor 519 is connected to the other of the source terminal and drain terminal of the transistor 519. The potential of the node 515 increases in accordance with the increase in the potential of the The bootstrap is a voltage between the gate terminal of transistor 519 and the source terminal of transistor 519. This is often done by the parasitic capacitance between the source and drain terminals.

[0256] Transistor 520 switches terminal 504G and terminal 518 according to the potential of node 516. and set the potential of the signal output via terminal 518 to V1 or V2. It has a function.

[0257] The transistor 521 is connected to the terminal 502B in accordance with a signal input via the terminal 502B. 4H and the terminal 518 are brought into a conductive state, and the potential of the signal output via the terminal 518 is set to V1 or has the ability to set it to V2.

[0258] Next, the operation of the driving circuit in FIG. 10 will be explained with reference to FIG. 11. 10 is a timing chart showing an example of the operation of the driving circuit in this embodiment. Regarding the operation of the driver circuit in this case, transistors 519, 520, and Only the operation of the resistor 521 will be explained, and only the parts that are the same as the operation of the elements of the driving circuit shown in FIG. In this regard, the explanation of the operation of the drive circuit in FIG. 7 will be used as appropriate. The following description will be given assuming that the first clock signal is input to 503C. As an example of the operation of the driving circuit, the transistors in the flip-flop circuit are all N-type transistors. The case of a transistor will be described.

[0259] During the first period, in addition to the operation of the circuit shown in FIG. 7, a low state is output via the terminal 503C. The first clock signal 602 is input. At this time, the transistor 521 is turned on. .

[0260] At this time, the potential 604 of the node 515 is V1-Vth 507 and transistor 511 Furthermore, when the transistor 511 is turned on, the transistor 520 It will be in the off state.

[0261] Also, the potential 604 of the node 515 is V1-Vth 507 Then, transistor 512 is in the ON state.

[0262] Furthermore, at this time, the potential of the output signal 608 outputted through the terminal 518 is The potential V2 of the first clock signal input via the terminal 504H is The value of the potential V2 is equal to the potential V3 at the first period.

[0263] Next, in the second period, in addition to the operation of the circuit shown in FIG. 7, a high state is output via terminal 503C. A first clock signal 602 is input. At this time, the transistor 521 is in the off state. become.

[0264] At this time, the potential 604 of the node 515 is V1-Vth 507 The transistor 511 remains on. Furthermore, when transistor 511 remains on, , transistor 520 remains off.

[0265] Furthermore, at this time, the node 515 remains in a floating state, and the potential 604 of the node 515 is V1-Vth 507 It remains as it is.

[0266] Furthermore, the potential 604 of the node 515 is V1-Vth 507 The source terminal and When the potential of one of the drain terminals becomes the potential V1 of the first clock signal 602, the transistor The capacitance due to the parasitic capacitance between the gate terminal of 519 and the other of the source terminal and drain terminal The coupling causes the potential 604 of node 515 to rise to match the potential of output signal 608 . At this time, the potential 604 of the node 515 is equal to the potential V1 of the first clock signal 602 and the potential V2 of the The threshold voltage (Vth 512 ) or the first clock signal 6 The potential V1 of the transistor 519 and the threshold voltage (Vth 519 (also called) is also a larger value, i.e., V1+Vth 512 +Va, or V1+Vth 519 +V a (Va is any positive value).

[0267] Furthermore, the potential 604 of the node 515 becomes V1+Vth 512 +Va or V1+Vth 51 When 9+Va, transistor 519 remains on.

[0268] Furthermore, at this time, the value of the output signal 608 outputted through the terminal 518 is The potential V1 of the first clock signal 602 inputted as a result of the second period is equal to the potential V1 of the first clock signal 602 inputted as a result of the second period. It is an action in between.

[0269] Next, in the third period, in addition to the operation of the circuit shown in FIG. 7, A first clock signal 602 is input. At this time, the transistor 521 is turned on. become.

[0270] At this time, the potential 605 of the node 516 remains at a value equivalent to the potential V2. When the potential 605 of the node 516 is V2, the node 516 is in a floating state. When in this state, transistor 520 remains off.

[0271] Furthermore, at this time, the potential of the output signal 608 outputted through the terminal 518 is The value of the potential V2 is equal to the potential V3 applied via the transistor V1. The above is the operation in the third period.

[0272] Next, in the fourth period, in addition to the operation of the circuit shown in FIG. 7, a high state is output via terminal 503C. A first clock signal 602 is input. At this time, the transistor 521 is in the off state. become.

[0273] At this time, the potential 605 of the node 516 becomes V2+Vb, and the potential 605 of the node 516 becomes When V2+Vb, transistor 520 turns on.

[0274] Furthermore, the potential 604 of the node 515 is equal to the potential V2 applied via the terminal 504B. When the potential 604 of the node 515 becomes V2, the transistor 519 is turned off. do.

[0275] Furthermore, at this time, the potential of the output signal 608 outputted through the terminal 518 is The value of the potential V2 applied via the transistor 11 is equal to the value of the potential V3 applied via the transistor 11. The above is the operation in the fourth period.

[0276] Next, in the fifth period, in addition to the operation of the circuit shown in FIG. 7, A first clock signal 602 is input. At this time, the transistor 521 is turned on. become.

[0277] At this time, when the potential 604 of the node 515 becomes V2, the transistor 519 is turned off. do.

[0278] Also, when the potential 605 of the node 516 becomes V2, the transistor 520 is turned off. .

[0279] Furthermore, at this time, the potential of the output signal 608 outputted through the terminal 518 is The value of the potential V2 applied via the potential V1 is equal to the value of the potential V2 applied via the potential V2. The above is the operation in the fifth period.

[0280] As described above, the flip-flop circuit in the driver circuit shown in FIG. By using a number of flip-flops, one output signal is output to the next flip-flop circuit, and the other By outputting the output signal to the gate terminal of the pixel transistor, a flip-flop circuit It is possible to output an output signal with little deviation to the path, and to suppress malfunctions.

[0281] Furthermore, the flip-flop circuit in the driver circuit of this embodiment has the same configuration as that shown in FIG. The configuration in FIG. 10 can also be combined. Another configuration of the flip-flop circuit in this embodiment will be described with reference to FIG. FIG. 10 is a circuit diagram showing another configuration of the flip-flop circuit in the drive circuit according to the embodiment.

[0282] Another configuration of the driver circuit of the flip-flop circuit in this embodiment shown in FIG. In addition to the circuit configuration shown in FIG. 7, terminals 503D, 504I, 504J, and 504K are provided. Terminal 522, transistor 523, transistor 524, transistor 525, and transistor The sensor has a transistor 526.

[0283] In FIG. 12, the elements having the same reference numerals as those in FIG. 7 are the same as those in FIG. Since the elements are the same as those in the circuit, the explanation of each element in FIG. 7 will be used as appropriate.

[0284] 12, terminal 503D corresponds to terminal 503C in FIG. 9, and terminal 504J corresponds to terminal 504F in FIG. 10. 10, the terminal 504K corresponds to the terminal 504H in FIG. 10, and the terminal 522 corresponds to the terminal 504G in FIG. 9. The transistor 523 corresponds to the transistor 517 in FIG. 10, and transistor 524 corresponds to transistor 519 in FIG. 10. Transistor 525 corresponds to transistor 520 in FIG. 10. Transistor 526 corresponds to transistor 520 in FIG. 9 and 10. The description of each element in 10 is incorporated herein by reference.

[0285] The operation of the drive circuit in FIG. 12 is the same as that of the drive circuits in FIGS. 9 and 10. 9 and 10. To quote.

[0286] As described above, by using the configuration shown in FIG. 12, the driving circuits shown in FIGS. Each effect can be obtained.

[0287] This embodiment mode can be combined with other embodiment modes as appropriate.

[0288] (Embodiment 3) In this embodiment, a structure of a display device using a driver circuit according to one embodiment of the present invention will be described. Reveal.

[0289] First, the configuration of the display device of this embodiment will be described with reference to FIG. 1 is a block diagram showing an example of a configuration of a display device according to an embodiment.

[0290] The display device shown in FIG. 13 includes a pixel portion 700, a signal line driver circuit 701, and a scanning line driver circuit 702, a control circuit 703, a clock signal generating circuit 704, a signal line 705A, and a signal Line 705B, scan line 706A, scan line 706B, scan line 706C, and scan line 706 D, clock signal line 707, and clock signal line 708. In the display device, the scanning line 706A, the scanning line 706B, the scanning line 706C, or the scanning line 7 06D is also simply referred to as a scanning line 706. In the display device shown in FIG. A or signal line 705B is also simply referred to as signal line 705. In addition, in FIG. Although four signal lines and four scanning lines are shown in the figure, the display device of this embodiment has a number of signal lines and scanning lines. The number of signal lines and scanning lines is not particularly limited, and other numbers of signal lines and scanning lines may be used. By increasing the number of scanning lines, the display operation can be performed even when the number of pixels is increased. It is possible.

[0291] Furthermore, the pixel section 700 has a plurality of pixels 709. In FIG. 13, the pixels 709 are arranged in eight rows. However, the display device of this embodiment is not limited to this and may be configured with other numbers. For example, if the pixel area is the same, increasing the number of pixels will improve clarity. The display can be made on the

[0292] In addition, the pixel 709 in the pixel section 700 is connected to any one of the plurality of signal lines 705. The signal line driver circuit 701 is electrically connected to the signal line driver circuit 701 via the signal line 705, and the plurality of scanning lines 70 6, which are electrically connected to the scanning line driving circuit 702 via one of the scanning lines 706. can be.

[0293] Furthermore, the scanning line driver circuit 702 has a shift register. A flip-flop that becomes a flip-flop circuit (also called the first stage flip-flop circuit) The circuit 710A and the second flip-flop circuit (also called the second-stage flip-flop circuit) ) and a third flip-flop circuit 710B (third stage flip-flop circuit a fourth flip-flop circuit 710C, which is also called a flip-flop circuit; Flip-flop circuit 71 (also called the fourth-stage flip-flop circuit) 0D. Note that the flip-flop circuit 710A and the flip-flop circuit 710 B, flip-flop circuit 710C or flip-flop circuit 710D is simply flipped. It is also referred to as a flip-flop circuit 710. The number of flip-flop circuits is not limited to the number of flip-flop circuits shown in FIG. 13, and may be other numbers (N stages ( N can be a natural number. For example, increasing the number of flip-flop circuits This is effective when increasing the area of ​​the pixel section because it can control more signal lines. It is effective.

[0294] In the display device of this embodiment mode, the flip-flop circuit 710 is The configuration of the flip-flop circuit according to any one of Embodiments 1 to 3 can be applied. In the display device shown in FIG. 13, as an example, when the flip-flop circuit of the configuration shown in FIG. 1 is applied, In the display device shown in FIG. 13, the scanning line driver circuit includes a However, the present invention is not limited to this example. In a display device, a driver circuit according to one embodiment of the present invention can be applied to a signal line driver circuit. can be done.

[0295] For example, in the case of a configuration having N-stage (N is a natural number of 2 or more) flip-flop circuits 710, In the first stage flip-flop circuit, the terminal 100 shown in FIG. 1 is electrically connected to the pixel 709 via the first scanning line 706. To be continued.

[0296] The flip-flop circuit 710 at the Nth stage is the flip-flop circuit at the N-1th stage when the terminal 100 shown in FIG. The terminal 105 of the flip-flop circuit 710 is electrically connected to the terminal 105 shown in FIG. Electrically connected to the terminal 101 shown in FIG. 1 of the flip-flop circuit 710 in the (N-1)th stage and electrically connected to the pixel 709 via the Kth scan line 706 .

[0297] In addition, the odd-numbered flip-flop circuits 710 have a terminal 102 shown in FIG. 1. The clock signal generator 704 is electrically connected to the clock signal generator 704 via a line 708. 03 is electrically connected to the clock signal generating circuit 704 via the clock signal line 707 .

[0298] In addition, the flip-flop circuits 710 at the even stages have terminals 102 shown in FIG. 1 that receive clock signals. 1. The clock signal generating circuit 704 is electrically connected to the clock signal generating circuit 704 via a line 707. 03 is electrically connected to the clock signal generating circuit 704 via a clock signal line 708 .

[0299] The configuration of the scanning line driving circuit 702 shown in FIG. 13 will be further described in detail.

[0300] Furthermore, in the scanning line driving circuit 702 shown in FIG. 13, the flip-flop circuit 710A 1 is electrically connected to the control circuit 703, and the terminal 102 shown in FIG. It is electrically connected to the clock signal generating circuit 704 via a clock signal line 708, and is shown in FIG. The terminal 103 shown in FIG. 1 is electrically connected to the clock signal generating circuit 704 via the clock signal line 707. 1 is electrically connected to the pixel 709 via the scanning line 706A. can be.

[0301] The flip-flop circuit 710B has a terminal 100 shown in FIG. 1 is electrically connected to the terminal 105 of the clock signal line 70. 7, and the terminal 103 shown in FIG. The clock signal is electrically connected to the clock signal generating circuit 704 via a clock signal line 708. The terminal 105 is electrically connected to the terminal 101 shown in FIG. 1 of the flip-flop circuit 710A. and is electrically connected to pixel 709 via scan line 706B.

[0302] The flip-flop circuit 710C has a terminal 100 shown in FIG. 1 is electrically connected to terminal 105 of 710B, and terminal 102 shown in FIG. The clock signal generating circuit 704 is electrically connected to the terminal 10 shown in FIG. 3 is electrically connected to the clock signal generating circuit 704 via the clock signal line 707, and 1 is connected to the terminal 101 shown in FIG. 1 of the flip-flop circuit 710B. 706C and electrically connected to pixel 709 via scan line 706C.

[0303] The flip-flop circuit 710D has a terminal 100 shown in FIG. 1 is electrically connected to terminal 105 of 710C, and terminal 102 shown in FIG. The clock signal generating circuit 704 is electrically connected to the terminal 10 shown in FIG. 3 is electrically connected to the clock signal generating circuit 704 via a clock signal line 708, and 1 is connected to the terminal 101 shown in FIG. 1 of the flip-flop circuit 710C. 706D and electrically connected to pixel 709 via scan line 706D.

[0304] The clock signal generating circuit 704 outputs a first clock signal via a clock signal line 707. and outputs a second clock signal via a clock signal line 708. The clock signal and the second clock signal are the same as those in the first embodiment. Since the first and second clock signals are the same as those in the first embodiment, the description of the first embodiment will be omitted. To quote.

[0305] The control circuit 703 outputs a first control signal which starts the operation of the flip-flop circuit. The start signal is outputted by the first control Since this signal is the same as the first control signal, the description of the first control signal in the first embodiment is also applicable. The control circuit 703 may be electrically connected to the signal line driver circuit 701. By electrically connecting the signal control circuit 703 and the signal line driver circuit 701, The line driver circuit 701 can also perform a desired operation using a control signal.

[0306] Next, the operation of the display device shown in FIG. 13 will be described.

[0307] First, the operation of the scanning line driving circuit 702 will be described with reference to FIG. 10 is a timing chart showing an example of the operation of the scanning line driving circuit in the display device shown in FIG. Here, as an example, let us consider the case where a flip-flop circuit is configured using N-type transistors. and explain.

[0308] The operation of the scanning line driving circuit 702 shown in FIG. 13 is performed in accordance with the number N of stages of the flip-flop circuit. It is divided into T periods (T is a natural number). Here, as an example, T=8, and the time is shown in Figure 13. The four flip-flop circuits 710A to 710D shown in FIG. The operation of the RIP circuit will now be described.

[0309] First, in the first period, the control circuit 703 outputs a flip-flop to the flip-flop circuit 710A. A start signal 801 in a high state is input via terminal 100 of drop circuit 710A. A second clock signal 803 in a high state is input via terminal 102, and a second clock signal 803 in a high state is input via terminal 10 The first clock signal 802 in the low state is input via the first clock signal 802. This operation corresponds to the operation in the first period of the timing chart shown in FIG. 2 in the first embodiment. is equivalent to

[0310] Next, in the second period, the control circuit 703 outputs a flip-flop to the flip-flop circuit 710A. A start signal 801 in a low state is input via a terminal 100 in the drop circuit 710A. A low-state second clock 803 signal is input via terminal 102, and a low-state second clock 803 signal is input via terminal 10. A first clock signal 802 in a high state is input via terminal 105. The terminal 100 of the flip-flop circuit 710B and the scanning line 706A are connected in a high state via the An output signal 804 is output.

[0311] In the second period, the flip-flop circuit 710B is connected to the flip-flop 710C via the terminal 100. The output signal 804 of the drop circuit 710A is input and the high-state signal is transmitted via the terminal 102. The first clock signal 802 is input, and the second clock signal 803 is in a low state via the terminal 103. A signal 803 is input.

[0312] Next, in the third period, the flip-flop circuit 710B is set in a low state via the terminal 100. When an output signal 804 is input, a first clock signal in a low state is output via terminal 102. 802 is input, and a second clock signal 803 in a high state is input via terminal 103. At this time, the terminal 100 of the flip-flop circuit 710C, the flip-flop A high output signal is applied to terminal 101 of flip-flop circuit 710A and to scan line 706B. Outputs 805.

[0313] In the third period, the flip-flop circuit 710C is set to a high state via the terminal 100. A certain output signal 805 is input, and a second clock signal in a high state is input via terminal 102. 803 is input, and the first clock signal 802 in the low state is input via the terminal 103. will be done.

[0314] Next, in the fourth period, the flip-flop circuit 710C is set to a low state via the terminal 100. When a certain output signal 805 is input, a second clock signal in a low state is output via the terminal 102. 803 is input, and the first clock signal 802 in a high state is input via the terminal 103. At this time, the terminal 100 of the flip-flop circuit 710D, the flip-flop The output signal 806 is output to the terminal 101 of the flip-flop circuit 710B and the scanning line 706C. do.

[0315] In the fourth period, the flip-flop circuit 710D is set in a high state via the terminal 100. An output signal 806 is input as a first control signal and is sent via terminal 102 in a high state. A first clock signal 802 in a low state is input, and a second clock signal 803 in a low state is output via a terminal 103. A clock signal 803 is input.

[0316] Next, in the fifth period, the flip-flop circuit 710D is set to a low state via the terminal 100. A certain output signal 806 is input as a first control signal and is set to a low state via a terminal 102. A first clock signal in a high state is input, and a second clock signal in a high state is output via a terminal 103. At this time, a signal is input to the terminal 10 of the next stage flip-flop circuit via the terminal 105. 0, the terminal 101 of the flip-flop circuit 710C, and the output signal 807 to the scanning line 706D. The above is the operation of the scanning line driving circuit.

[0317] Next, the operation of the pixel section will be described.

[0318] First, one of the plurality of scanning lines 706 is selected by the scanning line driving circuit 702. The pixels 709 electrically connected to the scanning lines 706 are supplied with signals by the signal line driver circuit 701. A signal is input via a line 705, and a predetermined potential is applied to the display element, thereby performing a display operation. Further, other scanning lines 706 are selected in sequence, and other pixels perform display operations in the same manner. The above is the operation in the pixel section.

[0319] As described above, the display device in this embodiment uses the driver circuit according to one embodiment of the present invention. By using it as a scanning line driver, after the flip-flop circuit is reset, This can prevent the signal value from changing, thereby preventing malfunctions. In addition, a desired potential can be maintained in each scanning line, improving reliability. It is possible.

[0320] Furthermore, as the display device of this embodiment, for example, a liquid crystal display device can be applied. The application of this invention to a liquid crystal display device will be described below.

[0321] The operation mode of the liquid crystal element applicable to the liquid crystal display device of this embodiment is TN (Twisted Nematic) mode, IPS (In-Plane-Switch ing) mode, FFS (Fringe Field Switching) mode, M VA (Multi-domain Vertical Alignment) mode, P VA(Patterned Vertical Alignment) mode, ASM( Axially Symmetrically aligned Micro-cell) mode , OCB (Optical Compensated Birefringence) mode, FLC (Ferroelectric Liquid Crystal) mode, AFLC (AntiFerroelectric Liquid Crystal) mode etc. can be used.

[0322] Next, the configuration and operation of a pixel applicable to the liquid crystal display device of this embodiment will be described. I will explain.

[0323] First, a pixel configuration applicable to the liquid crystal display device of this embodiment will be described with reference to FIG. 15A shows the configuration of a pixel portion of a liquid crystal display device according to this embodiment. FIG. 1 is a circuit diagram showing an example of the circuit shown in FIG.

[0324] The pixel portion shown in FIG. 15(A) includes a pixel 750, a wiring 754, a wiring 755, a wiring 756, and The pixel 750 includes a transistor 751, a liquid crystal element 752, and a capacitor. It has child 753.

[0325] The transistor 751 has a gate terminal electrically connected to a wiring 755 and a source terminal and a One of the drain terminals is electrically connected to a wiring 754 .

[0326] The liquid crystal element 752 has a first terminal, a second terminal, and a liquid crystal layer. The first terminal is a transistor. The second terminal is electrically connected to the other of the source terminal and the drain terminal of the wiring 751. is electrically connected to

[0327] The capacitor 753 has at least two terminals. One terminal is connected to the first terminal of the liquid crystal element 752. The other terminal is electrically connected to a wiring 756 .

[0328] The wiring 754 can function as, for example, a signal line. The wiring is for transmitting a data signal, which is a predetermined potential input from the pixel 750, to the pixel 750.

[0329] The wiring 755 can function as a scan line. This is wiring for controlling the on and off states.

[0330] The wiring 756 can function as a capacitor line. This is wiring for applying a specified voltage to the

[0331] The transistor 751 can function as a switch.

[0332] The capacitor 753 can function as a storage capacitor. When the resistor 751 is in the OFF state, the voltage applied to the liquid crystal element 752 is maintained for a certain period. It is a capacitance element for

[0333] The wiring 757 can function as a counter electrode of the liquid crystal element 752. , which are wirings for applying a predetermined voltage to the liquid crystal element 752.

[0334] The functions of each wiring are not limited to these, and various other functions can be added. For example, by changing the potential applied to the wiring functioning as a capacitance line, the liquid crystal element 752 The voltage applied to the

[0335] In addition, since the transistor 751 only needs to function as a switch, the transistor 751 The polarity of may be P-type or N-type.

[0336] Further, other pixel configurations applicable to the liquid crystal display device of this embodiment are shown in FIG. 15B) will be used to explain the pixel area of ​​the liquid crystal display device according to this embodiment. FIG. 10 is a circuit diagram showing an example of another configuration.

[0337] The configuration of the pixel section shown in FIG. 15(B) has a layout different from the configuration of the pixel section shown in FIG. 15(A). The line 757 is omitted, and the terminal of the liquid crystal element 752 and the terminal of the capacitor element 753 are electrically connected. The pixel section has the same configuration as that shown in FIG. 15(A) except for the connection points. The pixel portion shown in FIG. 15(B) is particularly suitable for a liquid crystal element in a horizontal electric field mode (IPS mode, FFS mode). It is preferable to apply this method when the liquid crystal element is a lateral electric field mode. In the case of the mode, the electrodes which are part of the terminals of the liquid crystal element 752 and the terminals of the capacitor 753 Since the electrodes of the liquid crystal element 752 and the electrodes of the liquid crystal element 752 can be formed on the same substrate, This is because it is easy to electrically connect the electrode of the capacitor 753. By using the pixel portion shown in FIG. 5(B), the wiring 757 can be omitted, and the manufacturing process can be simplified. This can reduce the manufacturing cost.

[0338] The pixel section shown in FIG. 15(A) or 15(B) has a plurality of pixels arranged in a matrix. In this way, a display unit of a liquid crystal display device can be formed, and various Various images can be displayed.

[0339] The structure of a pixel portion having a plurality of pixels will be described with reference to FIG. 1C) is a circuit diagram showing an example of the configuration of a pixel section of a liquid crystal display device according to the present embodiment.

[0340] The pixel section shown in FIG. 15(C) has a plurality of pixels 750 shown in FIG. 15(A) arranged in a matrix. In FIG. 15C, four pixels out of the plurality of pixels in the pixel section are arranged in a The pixel located in the i-th column and j-th row (i and j are natural numbers) is designated as pixel 750_i,j. In the pixel portion shown in FIG. 15C, the pixel 750_i,j is connected to the wiring 754_ i, wiring 755_j, and wiring 756_j are electrically connected to the pixel 750_i+1,j. The wiring 754_i+1, the wiring 755_j, and the wiring 756_j are electrically connected to the pixel 750. _i, j+1 is electrically connected to wiring 754_i, wiring 755_j+1, and wiring 756_j+1. The pixel 750_i+1, j+1 is connected to a wiring 754_i+1, a wiring 755_j+1, The pixel portion 756 is electrically connected to the wiring 756_j+1. Each wiring can be shared by multiple pixels in the same column or row. In the pixel portion shown in FIG. 1, the wiring 757 is a counter electrode, and the counter electrode is Since it is common, wiring 757 is not represented by natural numbers i or j. In the liquid crystal display device of this embodiment, the structure of the pixel portion shown in FIG. Therefore, even if the wiring 757 is shown in the configuration, the wiring 757 is not required. Instead, it can be omitted by sharing it with other wiring.

[0341] The pixels of the pixel portion shown in FIG. 15(C) can be driven by various methods. In particular, by driving it using a method called AC driving, the deterioration of the liquid crystal element ( The pixel of the pixel part shown in FIG. 15(C) is driven by AC. The operation when the sensor is driven by the sensor shown in FIG. 1 will be described with reference to FIG. 15(D). 5(C) is a timing chart showing the operation of the pixel of the pixel unit shown in FIG. As the operation of the pixel of the pixel section shown in FIG. 15(C), dot inversion driving, which is one of AC driving, is used. By using dot inversion driving, the operation that occurs in the case of AC driving is This can suppress the flicker that occurs.

[0342] In the pixel of the pixel portion shown in FIG. 15C, The switch in the pixel is in the selected state (on) during the j-th gate selection period in one frame period. In the jth gate, the jth gate is in a non-selected state (off state) and in the other periods it is in a non-selected state (off state). After the j+1 gate selection period, the j+1 gate selection period is provided. As a result, all pixels are selected in sequence within one frame period. In the timing chart, for example, when the potential is in a high state (high state), the pixel The switch at the This is the case when the transistor in each pixel is N-type, and When N-type transistors are used, the relationship between voltage and select state is the opposite of that for N-type transistors. .

[0343] In the timing chart shown in FIG. 15(D), the first pulse in the k-th frame (k is a natural number) During the j gate selection period, a positive potential is applied to the wiring 754_i used as a signal line. A negative potential is applied to the wiring 754_i+1. During the port selection period, a negative potential is applied to the wiring 754_i, and a positive potential is applied to the wiring 754_i+1. After that, the polarity of each signal line is inverted for each gate selection period. As a result, in the k-th frame, the pixel 750_i,j a positive potential to pixel 750_i+1,j, a negative potential to pixel 750_i,j+1, and a negative potential to pixel 750_i,j+2. A positive potential is applied to the pixel 750_i+1, j+1. Then, in the k+1th frame, for each pixel, As a result, the potential of the k+1th frame is written with the opposite polarity to the potential written in the previous frame. In the frame, the pixel 750_i,j is applied with a negative potential, and the pixel 750_i+1,j is applied with a positive potential. potential, a positive potential for pixel 750_i,j+1, and a negative potential for pixel 750_i+1,j+1 In this way, adjacent pixels in the same frame are given Each pixel is given a potential of a different polarity, and each pixel Dot inversion driving is a driving method in which the polarity of the potential is inverted. , while suppressing deterioration of the liquid crystal element, when the whole or part of the displayed image is uniform, It is possible to reduce flicker caused by the wiring 756_j and the wiring 756_j+1. The voltage applied to all the wirings 756 including the wiring 756 can be a constant voltage. The timing chart of 754 only shows the polarity of the potential, but in reality, The polarity shown can take on various potential values. However, the present invention is not limited to this, and the polarity may be reversed for each of a plurality of pixels. For example, the polarity of the potential written can be reversed every two gate selection periods. This reduces the power consumption required for writing the potential. It is also possible to invert the polarity (source line inversion), and to invert the polarity for each row. This is also possible (gate line inversion).

[0344] Note that a constant voltage is applied to the capacitor 753 in the pixel 750 during one frame period. Here, the signal given to the wiring 755 used as the scanning line is 1 frame. Since it is in the low state for most of the frame period and a nearly constant voltage is applied, The other terminal of the capacitor 753 in the pixel 750 may be connected to a wiring 755. The other terminal of the element 753 is electrically connected to the wiring 755 as shown in FIG. show.

[0345] The pixel configuration of the pixel section shown in FIG. 15(E) is different from the pixel configuration of the pixel section shown in FIG. 15(C). In this case, the wiring 756 is omitted, and the terminal of the capacitor 753 in the pixel 750 and the terminal of the immediately preceding pixel 751 are connected to each other. Specifically, the pixel 750_i,j is electrically connected to the wiring 755 in the row. The terminals of the capacitors 753 in the pixels 750_i+1,j+1 and 750_i+1,j+1 are connected to the wirings 755_ j. In this way, the terminal of the capacitor element 753 in the pixel 750 and the By electrically connecting the wiring 755 in the row, the wiring 756 can be omitted. Since the number of wirings can be reduced, the aperture ratio of the pixel can be improved. The terminal of 753 is not connected to the wire 755 in the previous row, but to the wire in another row. 755. The driving method of the pixel of the pixel portion shown in FIG. 15(E) is the same as that shown in FIG. A method similar to that of the pixel portion shown in FIG.

[0346] Note that the capacitor 753 and the wiring electrically connected to the other terminal of the capacitor 753 are By using this, the voltage applied to the wiring 754 used as a signal line can be reduced. The configuration and driving method of the pixel section will be explained using Figures 15(F) and 15(G). Reveal.

[0347] The configuration of the pixel section shown in FIG. 15(F) has a wiring configuration different from that of the pixel section shown in FIG. 15(A). 756 are provided in two per pixel column, and the terminals of the capacitance elements 753 in the pixels 750 are connected to the The feature of this method is that the electrical connections are made alternately between adjacent pixels. The wiring 756 will be referred to as wiring 756-1 and wiring 756-2, respectively. In the range shown in FIG. 15(F), the capacitance of the pixel 750_i,j The terminal of the element 753 is electrically connected to the wiring 756-1_j, and the pixel 750_i+1,j The terminal of the capacitor 753 in the pixel 750 is electrically connected to the wiring 756-2_j. The terminal of the capacitor 753 in the first row of the first-row capacitor _i,j+1 is electrically connected to the wiring 756-2_j+1. The terminal of the capacitor 753 in the pixel 750_i+1,j+1 is connected to the wiring 756-1_ j+1 is electrically connected to the

[0348] Also, for example, as shown in FIG. 15(G), in the k-th frame, When a positive polarity potential is written, the wiring 756-1_j is After the j-th gate selection period ends, it is changed to a high state. It remains in a high state during the jth gate selection period in the k+1th frame. After a negative potential is written to the line 756-1_j, the line 756-1_j is changed to a low state. In this way, after a positive potential is written to the pixel, the other terminal of the capacitor 753 is electrically connected. By changing the potential of the wiring connected to the liquid crystal element in the positive direction, the potential applied to the liquid crystal element The voltage written to the pixel can be changed by a predetermined amount in the positive direction. This reduces the power consumption required for signal writing. In addition, when a negative voltage is written in the j-th gate selection period, the negative voltage After the voltage of the wiring electrically connected to the other terminal of the capacitor 753 is written to the pixel, By changing the potential in the negative direction, the potential applied to the liquid crystal element is changed by a predetermined amount in the negative direction. As a result, the voltage written to the pixel can be reduced, just as in the case of positive polarity. That is, the wiring electrically connected to the other terminal of the capacitor 753 can be In the same row of the same frame, there are pixels to which a positive potential is applied and pixels to which a negative potential is applied. It is preferable that the wirings for the pixel to be obtained are different from each other.

[0349] The pixel section shown in FIG. 15(F) is a pixel to which a positive polarity potential is written in the k-th frame. The wiring 756-1 is electrically connected to the element, and a negative polarity potential is written in the k-th frame. In this example, the wiring 756-2 is electrically connected to the pixel that is inserted. For example, there are pixels to which a positive potential is written and pixels to which a negative potential is written. In the case of a driving method in which the voltages of the wirings 756-1 and 756-2 are It is also preferable that the electrical connection is performed alternately every two pixels. In some cases, the same polarity potential is written (gate line inversion), but in that case, 756 may be one per row. In other words, in the pixel configuration of the pixel section shown in FIG. Also, as explained with reference to FIGS. 15(F) and 15(G), the voltage written to the pixel can be reduced. A driving method that reduces the amount of light can be used.

[0350] Next, the liquid crystal element is a vertical alignment (VA) mode, represented by MVA mode or PVA mode. A pixel configuration and a driving method that are particularly preferable for the VA mode will be described. The LCD panel has many advantages, such as no rubbing process required during manufacturing, minimal light leakage during black display, and low driving voltage. However, the image quality deteriorates when the screen is viewed from an angle (narrow viewing angle). To widen the viewing angle in VA mode, it is necessary to have multiple sub-pixels (sub-pixels) per pixel. It is effective to have a pixel configuration with multiple sub-pixels in one pixel. The pixel configuration will be described with reference to FIGS. 16(A) and 16(B). 16(B) shows an example of a pixel configuration applicable to the liquid crystal display device of this embodiment. FIG.

[0351] The pixel 750 of the pixel portion in the liquid crystal display device shown in FIGS. 16(A) and 16(B) is This shows an example of a case where two sub-pixels (sub-pixel 750-1 and sub-pixel 750-2) are included. The number of sub-pixels in one pixel is not limited to two, and various numbers of sub-pixels can be used. The larger the number of sub-pixels, the wider the viewing angle can be. The sub-pixels can have the same circuit configuration. In this case, all the sub-pixels have the same circuit configuration as shown in FIG. ) is the same as the circuit configuration shown in FIG. The device has a transistor 751-1, a liquid crystal element 752-1, and a capacitance element 753-1. The connections of these components are in accordance with the circuit configuration shown in FIG. The element 750-2 includes a transistor 751-2, a liquid crystal element 752-2, and a capacitor element 753-2. The connections between the components are in accordance with the circuit configuration shown in FIG. 15(A). .

[0352] The pixel section shown in FIG. 16(A) uses a scanning line for two sub-pixels that make up one pixel. The wiring 755 has two wirings (wiring 755-1 and wiring 755-2) that are used as signal lines. The wiring 754 is a capacitor line, and the wiring 756 is a capacitor line. By sharing the signal line and the capacitance line between two sub-pixels, the aperture ratio can be improved. Furthermore, the signal line driver circuit can be simplified, which reduces manufacturing costs. In addition, the number of connections between the liquid crystal panel and the driver circuit can be reduced, improving yield. .

[0353] The pixel section shown in FIG. 16(B) has two sub-pixels that make up one pixel, and each sub-pixel is used as a scanning line. The wiring 754 has one wiring 755 used as a signal line, and two wirings 754 (wiring 754-1, wiring 754-2) The wiring 754-2 is provided, and one wiring 756 is provided as a capacitance line. In addition, the aperture ratio can be improved by sharing the scanning line and the capacitance line between two sub-pixels. Furthermore, the total number of scanning lines can be reduced, so even high-resolution LCD panels can be used with The gate line selection period per pixel can be made sufficiently long, and an appropriate voltage can be applied to each pixel. can be written.

[0354] Next, the liquid crystal element 752 in the pixel portion shown in FIG. 16(B) is 16(C) and 16(D) are examples in which the electrical connection state of each element is shown in a schematic manner. 6(D) will be used to explain.

[0355] In FIG. 16(C) and FIG. 16(D), electrode 758-1 represents the first pixel electrode, The electrode 758-2 represents the second pixel electrode. -1 corresponds to the second terminal of the liquid crystal element 752-1 in FIG. 16(B), and the electrode 758-2 corresponds to the terminal of the liquid crystal element 752-2 in FIG. -1 is electrically connected to either the source terminal or the drain terminal of the transistor 751-1. The electrode 758-2 is connected to one of the source terminal or drain terminal of the transistor 751-2. On the other hand, in FIG. 16(D), the pixel electrode and the transistor are electrically connected. The connection relationship is reversed, i.e., electrode 758-1 is connected to the source terminal of transistor 751-2. The electrode 758-2 is electrically connected to one of the drain terminals of the transistor 751. -1 is electrically connected to either the source terminal or the drain terminal of

[0356] In addition, the pixels shown in FIG. 16(C) and FIG. 16(D) are alternately arranged in a matrix. By placing the pixel in this position, a special effect can be obtained. An example of the method will be described with reference to Figures 16(E) and 16(F). In the timing chart shown in FIG. 1, as an example, the potential is in a high state (high state). The switch in the pixel is in a selected state, and the potential is in a low state (low state). It will be in the selected state

[0357] The configuration of the pixel section shown in FIG. 16(E) includes pixels 750_i,j and 750_i+1, The part corresponding to j+1 is configured as shown in FIG. 16C, and the pixel 750_i+1,j and the pixel 750_i+1,j are The part corresponding to element 750_i,j+1 has the configuration shown in FIG. In this configuration, when driven as shown in the timing chart of FIG. 16(F), During the j-th gate selection period of the system, the first pixel electrode of the pixel 750_i,j and the pixel 75 A positive polarity potential is written to the second pixel electrode of pixel 750_i+1,j, A negative potential is applied to the second pixel electrode and the first pixel electrode of the pixel 750_i+1,j. Furthermore, in the j+1-th gate selection period of the k-th frame, the pixel 750_i,j +1 and the first pixel electrode of the pixel 750_i+1,j+1. A potential is applied to the first pixel electrode of pixel 750_i,j+1 and the second pixel electrode of pixel 750_i+1, A negative potential is applied to the j+1 second pixel electrode. The polarity of the voltage is inverted in each pixel. While realizing a drive equivalent to dot inversion drive in Since the same value can be set within one frame period, the time required for writing data to the pixel is The power consumption can be significantly reduced. The potential applied to all the wirings 756 including the wiring 756 can be set to a constant potential.

[0358] Furthermore, the pixel configuration and driving method shown in FIG. 16(G) and FIG. 16(H) This allows the magnitude of the potential written to the pixel to be reduced. The capacitance lines electrically connected to the plurality of sub-pixels of a pixel are made different for each sub-pixel. That is, the configuration of the pixel section and the driving method thereof shown in FIG. 16(G) and FIG. 16(H) By this method, for sub-pixels to which the same polarity is written in the same frame, For sub-pixels that share a common capacitance line and have different polarities written in the same frame, The capacitance lines are different within the same row. Then, when writing to each row is completed, The potential of the capacitance line is changed in the positive direction for the sub-pixel to which a positive voltage is written, and in the negative direction for the By changing the written subpixel in the negative direction, the magnitude of the voltage written to the pixel Specifically, the wiring 756 used as the capacitance line is set to two ( The first pixel electrode of the pixel 750_i,j and the wiring 756-1_j is electrically connected to the second pixel 750_i,j through a capacitance element. The pixel electrode and the wiring 756-2_j are electrically connected via a capacitor element, and the pixel 750 The first pixel electrode of pixel _i+1,j and the wiring 756-1_j are electrically connected via a capacitor. The second pixel electrode of the pixel 750_i+1,j and the wiring 756-2_j are connected to each other. The first pixel electrode of the pixel 750_i,j+1 is electrically connected to the wiring 75 through the element. 6-2_j+1 is electrically connected to the first pixel of the pixel 750_i,j+1 through a capacitance element. The pixel electrode of the pixel 2 is electrically connected to the wiring 756-1_j+1 through a capacitor. The first pixel electrode of the pixel 750_i+1,j+1 and the wiring 756-2_j+1 form a capacitor element , and the second pixel electrode of the pixel 750_i+1,j+1 and the wiring 75 6-1_j+1 are electrically connected via a capacitance element. However, this is just an example. For example, there are two pixels to which a voltage of positive polarity is written and two pixels to which a voltage of negative polarity is written. In the case of a driving method in which the voltage appears for each pixel, the electrical It is preferable that the connections are made alternately every two pixels. In some cases, the same polarity potential is written to all pixels in a row (gate line inversion). In this case, one wiring 756 is sufficient for one row. 16(G) and 16(H), the pixel is written A driving method that reduces the voltage can be used.

[0359] Note that this embodiment mode can be combined with other embodiment modes as appropriate.

[0360] (Fourth embodiment) In this embodiment, a transistor applicable to a driver circuit according to one embodiment of the present invention will be described. The structure of the transistor will be described.

[0361] First, a transistor configuration applicable to a transistor constituting a driver circuit of this embodiment will be described. This will be explained with reference to Fig. 17. Fig. 17 shows a transistor applicable to the driving circuit of this embodiment. 17(A) is a cross-sectional view showing the structure of a top-gate transistor. FIG. 17(B) shows an example of the structure of a bottom-gate transistor. vinegar.

[0362] The transistor shown in FIG. 17A has a substrate 900 and a transistor provided over the substrate 900. A semiconductor layer 902 having an impurity region 901 and a gate insulating film provided to cover the semiconductor layer 902. A gate insulating film 903 is provided on a part of the semiconductor layer 902 with the gate insulating film 903 sandwiched therebetween. a gate electrode 904 formed on the gate electrode 904 and the gate insulating film 903; and an interlayer insulating film 906 having the same, and a gate insulating film 908 provided in contact with the impurity region 901 through an opening. The electrode 905 has a pair of electrodes, namely, an electrode 905a and an electrode 905b.

[0363] The transistor shown in FIG. 17B has a structure including a substrate 907 and a transistor provided over the substrate 907. a gate electrode 908 formed thereon and a gate insulating film 910 provided to cover the gate electrode 908; and a semiconductor layer formed on a portion of the gate insulating film 910 where the gate electrode 908 is not formed. a pair of semiconductor layers having n-type conductivity provided on the semiconductor layer 911; The semiconductor layer 912a and the semiconductor layer 912b are connected to each other, and one of the pair of semiconductor layers, i.e., the semiconductor layer Electrode 913a is provided on 912a, and the other of the pair of semiconductor layers, i.e., semiconductor layer 9 and an electrode 913b provided on the substrate 12b.

[0364] The substrate 900 and the substrate 907 may be, for example, a glass substrate, a quartz substrate, a silicon substrate, or a gold substrate. A metal substrate, a stainless steel substrate, or the like can be used. A flexible substrate can also be used. The term "substrate" refers to a substrate made of, for example, polycarbonate, polyarylate, or polyethylene. The substrate 900 and the substrate 910 may be made of a plastic material such as polysulfone. The plate 907 may be, for example, a laminated film (polypropylene, polyester, vinyl , polyvinyl fluoride, vinyl chloride, etc.), paper made of fibrous materials, base film Materials such as polyester, polyamide, inorganic vapor deposition film, and paper can also be used. .

[0365] The semiconductor layer 902 and the semiconductor layer 911 may be, for example, an amorphous semiconductor film or a single crystal semiconductor film. , polycrystalline semiconductor film, or microcrystalline (also called microcrystalline or semi-amorphous) c) It can be formed by using a semiconductor film or the like, and can be formed by stacking these semiconductor films. The semiconductor layer can also be an oxide semiconductor (e.g., IGZO (InGaZn The semiconductor layer can be formed by, for example, sputtering, LPCV, etc. The amorphous semiconductor film can be formed by the D method, the plasma CVD method, or the like. By known techniques (solid phase growth method, laser crystallization method, crystallization method using catalytic metal, etc.) A semiconductor film (crystalline semiconductor film) having a crystalline structure formed by crystallization, such as polycrystalline silicon A bare membrane can also be used.

[0366] The gate insulating film 903 and the gate insulating film 910 may be, for example, a nitride insulating film or an oxide insulating film. For example, a silicon oxynitride film or a nitrogen-containing oxide insulating film can be used. The silicon oxynitride film is a film containing more than nitrogen as a composition. The oxygen content is the highest, with a concentration range of 55 to 65 atomic % oxygen and 1 atomic % nitrogen. ~20 atomic %, silicon 25-35 atomic %, hydrogen 0.1-10 atomic % The silicon nitride oxide film is a film whose composition contains more nitrogen than oxygen. The concentration range is 15 to 30 atomic % for oxygen and 20 to 35 atomic % for nitrogen. It refers to a material containing 25 to 35 atomic % silicon and 15 to 25 atomic % hydrogen.

[0367] The semiconductor layers 912a and 912b have n-type conductivity and are doped with an impurity element. A semiconductor layer containing phosphorus or the like can be used.

[0368] The gate electrode 904 and the gate electrode 908 may be made of, for example, gold, silver, platinum, nickel, Silicon, tungsten, chromium, molybdenum, iron, cobalt, copper, palladium, carbon, An element selected from aluminum, manganese, titanium, tantalum, etc., or the corresponding Materials made of alloys containing multiple elements can be used, and they can be used as single layers or laminated layers. The alloy containing a plurality of the above elements can be formed by, for example, aluminum and Titanium-containing alloys, aluminum, titanium, and carbon-containing alloys, aluminum and Alloys containing nickel, alloys containing aluminum and carbon, aluminum, nickel, and carbon-containing alloys, or aluminum and molybdenum-containing alloys, etc. Indium tin oxide (ITO) and indium tin oxide containing silicon oxide can also be used. Use of transparent materials such as indium zinc oxide (ITSO) or indium zinc oxide (IZO) The gate electrodes 904 and 908 can be formed by evaporation, sputtering, CV The conductive film can be formed by a droplet ejection method, a printing method, or a droplet discharge method.

[0369] The interlayer insulating film 906 may be, for example, a nitride insulating film, an oxide insulating film, or an oxide insulating film containing nitrogen. etc. can be applied.

[0370] The electrodes 905a and 905b, and the electrodes 913a and 913b are source electrodes. The electrode 905a and the electrode 905b, and the electrode 913 The electrodes 913a and 913b may be made of, for example, gold, silver, platinum, nickel, silicon, or tungsten. , chromium, molybdenum, iron, cobalt, copper, palladium, carbon, aluminum, manganese , titanium, tantalum, etc., or an alloy containing multiple of the elements. The material may be a single layer or a laminate. Examples of alloys containing multiple of the above elements include alloys containing aluminum and titanium, Alloys containing aluminum, titanium, and carbon, alloys containing aluminum and nickel, Alloys containing aluminum and carbon, alloys containing aluminum, nickel, and carbon, Alternatively, an alloy containing aluminum and molybdenum can be used. Indium tin oxide (ITO), indium tin oxide with silicon oxide (ITSO), or oxide A light-transmitting material such as indium zinc oxide (IZO) can be used. The electrodes 905a and 905b, and the electrodes 913a and 913b are made of different materials. In addition, the electrodes 905a and 905b, and the electrodes 913a and 913b can be formed. The electrode 913b is formed by using a vapor deposition method, a sputtering method, a CVD method, a printing method, or a droplet discharge method. It can be achieved.

[0371] As described above, one embodiment of the present invention can be realized by applying any of the transistors having the above structures. A variety of drive circuits can be configured.

[0372] Next, a bottom-gate transistor can be used as a transistor applicable to a driver circuit according to one embodiment of the present invention. Another configuration of the transistor will be described with reference to FIG. 18. FIG. 18 shows the transistor configuration of this embodiment. Schematic cross-sectional view showing an example of a structure of a transistor applicable to a transistor included in a driver circuit; Figure.

[0373] The transistor shown in FIG. 18 has a substrate 1000 and a gate electrode formed on the substrate 1000. A gate electrode 1001 and a gate insulating film 1002 provided to cover the gate electrode 1001. and a microcrystalline semiconductor layer 1002 formed on the gate electrode 1001 with a gate insulating film 1002 sandwiched therebetween. 1003, a buffer layer 1004 provided on the microcrystalline semiconductor layer 1003, and a buffer layer 1005 provided on the microcrystalline semiconductor layer 1003. A pair of semiconductor layers, 1005a and 1005b, are provided on the substrate 1004. and an electrode 1006 provided on one of the pair of semiconductor layers, i.e., the semiconductor layer 1005a. a and the other of the pair of semiconductor layers, i.e., the electrode 100 provided on the semiconductor layer 1005b. 6b and

[0374] The substrate 1000 may be a substrate applicable to the substrate 900 and the substrate 907 in FIG. A plate can be used.

[0375] The gate electrode 1001 is the same as the gate electrode 904 and the gate electrode 905 in FIG. Materials and configurations applicable to 08 can be applied.

[0376] The gate insulating film 1002 is the same as the gate insulating film 903 and the gate insulating film 904 shown in FIG. Any suitable material can be applied to the velum 910 .

[0377] The microcrystalline semiconductor layer 1003 has an intermediate structure between an amorphous structure and a crystalline structure (including single crystal and polycrystal). This semiconductor has a third stable state in terms of free energy. Conductive, crystalline with short-range order and lattice distortion, with a grain size of 0.5 to Columnar or needle-like crystals of 50 nm, preferably 1 nm to 20 nm, are formed in the normal direction to the substrate surface. The microcrystalline semiconductor layer 1003 is made of, for example, microcrystalline silicon. etc. can be applied.

[0378] In addition, an impurity element is intentionally added to the microcrystalline semiconductor layer 1003 for the purpose of controlling valence electrons. When not in use, it exhibits weak n-type electrical conductivity, so it is used as the channel formation region of a thin film transistor. The microcrystalline semiconductor film that functions as a p-type semiconductor is doped with an impurity element that imparts p-type conductivity at the same time as the film is formed or It is preferable to add impurities after the film formation to control the threshold voltage Vth. A typical example of the element is boron, and impurity gases such as B2H6 and BF3 are added at 1 ppm. by mixing it with silicon hydride at a ratio of 1 to 1000 ppm, preferably 1 to 100 ppm. It is preferable to form a boron layer having a concentration of, for example, 1×10 14 ~6×10 16 a toms / cm 3 It is preferable to set the following.

[0379] The oxygen concentration of the microcrystalline semiconductor layer 1003 is 1×10 19 cm -3 Below, preferably 5×10 18 cm -3 The following nitrogen and carbon concentrations are 5×10 18 cm -3 The following is preferably is 1 x 10 18 cm -3 It is preferable that the following conditions be satisfied: By reducing the concentrations of oxygen, nitrogen, and carbon in the microcrystalline semiconductor layer 1003, a channel can be formed. This prevents the region from becoming an n-type semiconductor. If there is variation between the elements, the threshold voltage Vth will vary. This makes it possible to reduce variations in threshold voltage Vth within the substrate.

[0380] In addition, the microcrystalline semiconductor layer 1003 has a higher carrier mobility than the buffer layer 1004. Therefore, as a transistor in a driver circuit of a display device, When a thin film transistor made of a microcrystalline semiconductor is used, the area of ​​the channel formation region, i.e. It is possible to reduce the area of ​​the thin film transistor. Therefore, the area of ​​the circuit can be reduced. This allows the frame to be narrower.

[0381] The buffer layer 1004 is provided over the microcrystalline semiconductor layer 1003, thereby The value of the off-state current can be made lower than that in the case of the single-layer structure of the microcrystalline semiconductor layer 1003. The buffer layer 1004 may be made of, for example, amorphous silicon.

[0382] The semiconductor layer 1005a and the semiconductor layer 1005b are formed of impurities having n-type or p-type conductivity. The semiconductor layer containing impurity elements is, for example, an amorphous semiconductor layer. As for impurity elements, for example, phosphorus is added in the case of n-type. In the case of p-type, boron may be added. The 005b can be formed using a microcrystalline semiconductor material or an amorphous semiconductor material. The semiconductor layer 1005a and the semiconductor layer 1005b are formed to a thickness of 2 nm to 50 nm. It is preferable to form the semiconductor layer 1005a and the semiconductor layer 1005b thinly. This can improve throughput.

[0383] The electrode 1006a and the electrode 1006b function as a source electrode and a drain electrode, The electrodes 1006a and 1006b are the same as the electrodes 905a and 905b in FIG. 905b, and electrodes 913a and 913b can be made of applicable materials. do.

[0384] Next, a manufacturing method of the transistor shown in FIG. 18 will be described with reference to FIGS. 19 to 21. 19 to 21 are cross-sectional views illustrating a method for manufacturing a transistor of this embodiment. It should be noted that thin film transistors having a microcrystalline semiconductor film have higher mobility when they are n-type than when they are p-type. If all thin film transistors formed on the same substrate are standardized to the same polarity, the number of processes can be reduced. Therefore, in this embodiment, a method for manufacturing an n-type transistor is This article explains:

[0385] First, as shown in FIG. 19(A), a conductive film 1007 is formed on a substrate 1000. In this embodiment, a laminated film of an aluminum film and a molybdenum film is formed as the conductive film 1007. The conductive film 1007 can be formed by, for example, sputtering or vacuum deposition. Cut.

[0386] Next, as shown in FIG. 19(B), a part of the conductive film 1007 is etched to form the gate electrode 1 More specifically, the gate electrode 1001 is formed by photolithography on the conductive film 1007. A resist is formed by lithography or inkjet printing, and the resist is used as a mask. The conductive film 1007 can be selectively etched to form the insulating film 1008. In this process, for example, scanning lines (such as scanning line 706 in FIG. 13) can also be formed at the same time. The resist is preferably removed after etching.

[0387] The end of the gate electrode 1001 formed by etching has a tapered shape. By forming the tapered shape, it is possible to form a layer on the tapered shape in a later process. This can improve the coverage of the layer to be applied.

[0388] Next, as shown in FIG. 19(C), a gate insulating film 100 is formed to cover the gate electrode 1001. The gate insulating film 1002 is formed by using, for example, a CVD method or a sputtering method. In this embodiment, as an example, a nitride film or a nitride oxide film and an oxide film are used. The gate insulating film 1002 is formed by forming a laminated film of a nitride film or an oxynitride film.

[0389] Furthermore, a microcrystalline semiconductor film 1008 is formed on the gate insulating film 1002. The film 1008 is formed by, for example, a high frequency plasma CVD method with a frequency of several tens to several hundreds of MHz, or Alternatively, it can be formed using a microwave plasma CVD apparatus with a frequency of 1 GHz or more. The plasma generated by a microwave plasma CVD device with a frequency of 1 GHz or more is Since the density is high and many radicals are generated from the source gas and supplied to the substrate 1000, The radical reaction on the substrate surface is promoted, and the deposition rate of the microcrystalline semiconductor film 1008 is increased. Furthermore, a microwave generator consisting of a plurality of microwave generators and a plurality of dielectric plates can be used. The plasma CVD device can stably generate plasma over a large area. It is possible to form films with high uniformity in film quality even on large-area substrates. In this embodiment, as an example, the fine grain The following describes the case where microcrystalline silicon is used as a crystalline semiconductor film. A specific method for producing the film 1008 will be described.

[0390] The microcrystalline semiconductor film 1008 is formed by diluting silicon hydride such as SiH4 or Si2H6 with hydrogen. or silicon hydride and hydrogen, plus helium, argon, krypton, and neon. The dilution can be performed by diluting the silicon hydride with one or more rare gas elements. The flow rate ratio of hydrogen to nitrogen is 5 to 200 times, preferably 50 to 150 times, More preferably, it is 100 times. Instead of silicon hydride, SiH2Cl2, SiH Cl3, SiCl4, SiF4, or the like can be used.

[0391] When the microcrystalline semiconductor film 1008 is formed, crystals grow from the bottom to the top of the film. This is because the crystal grows so that the crystal faces become larger. However, even in the case of such crystal growth, the rate at which the microcrystalline semiconductor layer is formed is The rate is about 1% to 10% of the rate at which the amorphous semiconductor layer is formed.

[0392] Furthermore, in this embodiment mode, after the microcrystalline semiconductor film 1008 is formed, The laser process (LP) is a process of irradiating the surface of 1008 with laser light. The LP treatment is specifically described below.

[0393] In the LP process, the laser beam has an energy density that does not melt the microcrystalline semiconductor film 1008. That is, the LP treatment is preferably performed by irradiating the microcrystalline semiconductor film 100 with radiation heating. This is due to solid-phase crystal growth without melting the deposited microcrystalline semiconductor. This utilizes the critical region where the conductive film 1008 does not become liquid. It can also be called "global growth."

[0394] The laser light acts on the interface between the microcrystalline semiconductor film 1008 and the gate insulating film 1002. As a result, the crystals on the surface side of the microcrystalline semiconductor film 1008 can be used as seeds. Then, solid phase crystal growth proceeds from the surface toward the interface with the gate insulating film 1002, forming approximately columnar crystals. The solid phase crystal growth by LP treatment does not increase the grain size, but This improves the crystallinity in the thickness direction.

[0395] In addition, the above LP process focuses the light into a long rectangular shape (shaping it into a linear laser beam), For example, the microcrystalline semiconductor film 1008 on a glass substrate of 730 mm x 920 mm is laser beamed once. This can be done by processing with a muscan. In this case, a linear laser beam is superimposed. The overlapping ratio is set to 0 to 90%, preferably 0 to 67%. This reduces the processing time per substrate, improving productivity. However, the shape of the laser beam is not limited to a linear shape, and a planar shape can also be used for processing. In addition, the LP process is not limited to the size of the glass substrate, and can be used for substrates of various sizes. By performing LP treatment, the microcrystalline semiconductor film 1008 and the gate insulating film The crystallinity of the interface region with 1002 is improved, and the current of the transistor with bottom gate structure is improved. The thermal properties can be improved.

[0396] This "critical growth" eliminates the surface irregularities ( No convex structures called ridges are formed, and the surface of the semiconductor film remains smooth after LP processing. .

[0397] Therefore, the microcrystalline semiconductor film 1008 obtained by directly applying laser light after film formation is Conventional microcrystalline semiconductor films as deposited and microcrystalline semiconductor films modified by conductive heating after deposition are The growth mechanism and the quality of the film formed are clearly different from those of crystalline semiconductor films. become.

[0398] Next, as shown in FIG. 20(D), an amorphous semiconductor film 1009 is formed on the microcrystalline semiconductor film 1008. Form.

[0399] The amorphous semiconductor film 1009 is formed by plasma annealing using silicon hydrides such as SiH4 and Si2H6. The silicon hydride can be formed by using a CVD method. It may be diluted with one or more rare gas elements selected from the group consisting of fluorine, krypton, and neon. The flow rate of the silicon hydride is 1 to 20 times, preferably 1 The flow rate of hydrogen is preferably from 1 to 10 times, more preferably from 1 to 5 times, and An amorphous semiconductor film 1009 can be formed. By using ammonia, an amorphous semiconductor film 1009 containing nitrogen can be formed. In addition, the above silicon hydride and a gas containing fluorine, chlorine, bromine or iodine (F2, C I2, Br2, I2, HF, HCl, HBr, HI, etc.) to The amorphous semiconductor film 1009 containing bromine or iodine can be formed. Instead of silicon dioxide, SiH2Cl2, SiHCl2, SiCl2, SiF2, etc. can be used. The thickness of the amorphous semiconductor film 1009 is 100 nm or more and 500 nm or less. The thickness is preferably 150 nm to 400 nm, and more preferably 200 nm to 300 nm. At this time, hydrogen is supplied to the microcrystalline semiconductor film 1008. That is, by depositing the amorphous semiconductor film 1009 on the microcrystalline semiconductor film 1008, Hydrogen can be diffused into the crystalline semiconductor film 1008 to terminate the dangling bonds.

[0400] The amorphous semiconductor film 1009 is formed by using an amorphous semiconductor as a target. It can also be formed by sputtering in a rare gas. By including nitrogen or N2O in the atmosphere, an amorphous semiconductor film containing nitrogen is formed. In addition, the atmosphere may contain gases containing fluorine, chlorine, bromine, or iodine (F2, C By incorporating fluorine, An amorphous semiconductor film containing chlorine, bromine, or iodine can be formed.

[0401] After the amorphous semiconductor film 1009 is formed, the surface of the amorphous semiconductor film 1009 is subjected to hydrogen precipitation. The amorphous semiconductor film 1009 is treated with a plasma, a nitrogen plasma, or a halogen plasma. The surface of the amorphous semiconductor film 1009 may be hydrogenated, nitrided, or halogenated. The surface is treated with helium plasma, neon plasma, argon plasma, krypton plasma, etc. It may also be processed.

[0402] It is also preferable that the amorphous semiconductor film 1009 does not contain crystal grains. is a high frequency plasma CVD method with a frequency of several tens to several hundreds of MHz or a microwave plasma CVD method. In the case of forming the amorphous semiconductor film 1009, the film forming conditions are adjusted so that the amorphous semiconductor film 1009 does not contain crystal grains. It is preferable to control

[0403] The amorphous semiconductor film 1009 contains impurities such as phosphorus and boron that impart one conductivity type. In particular, the microcrystalline semiconductor film 1008 is formed so as not to be doped with a fluorine atom in order to control the threshold voltage. It is preferable that boron or phosphorus does not get mixed into the amorphous semiconductor film 1009. For example, When the amorphous semiconductor film 1009 contains phosphorus, the microcrystalline semiconductor layer 1003 and the amorphous semiconductor film 1009 are A PN junction is formed between the amorphous semiconductor film 1009 and the amorphous semiconductor film 1009. In the case where the amorphous semiconductor film 1009 and the semiconductor layer 1005a and the semiconductor layer 1005b are included, A PN junction is formed between the two. Or, if both boron and phosphorus are mixed in, recombination occurs. The amorphous semiconductor film 1009 provides one conductivity type. By not including these impurities, the area where leakage current occurs is eliminated, and the leakage current is reduced. In addition, the semiconductor layer 1005a and the semiconductor layer 1005b are Impurities such as phosphorus or boron that impart one conductivity type are not added between the conductive layer 1003 and the insulating layer 1004. By having the amorphous semiconductor film 1009, the microcrystalline semiconductor layer 10 03, the semiconductor layer 1005a and the semiconductor layer 100 which will be a part of the source region and the drain region 5b, the diffusion of impurities contained therein can be prevented.

[0404] Furthermore, a semiconductor film 1010 is formed on the amorphous semiconductor film 1009. When phosphorus is added, an impurity element such as phosphorus is added. Phosphorus can be added by adding a gas such as PH3 to silicon hydride. To impart p-type conductivity, boron or the like is added as an impurity element. When adding boron, boron is added by adding impurity gas such as B2H6 to silicon hydride. can be added.

[0405] In this embodiment mode, the gate insulating film 1002, the microcrystalline semiconductor film 1008, and the non- It is preferable to form the gate insulating film 1009 continuously. film 1002, a microcrystalline semiconductor film 1008, an amorphous semiconductor film 1009, and a semiconductor film 1010 By forming the films successively, each film is prevented from coming into contact with the atmosphere. Therefore, the interface between each layer is formed without being contaminated by atmospheric components or impurity elements floating in the air. Therefore, the electrical characteristics of thin film transistors formed using each film can be reduced. This allows for reduced adhesion, and enables highly reliable drive circuits to be manufactured with a high yield. .

[0406] Next, the microcrystalline semiconductor film 1008, the amorphous semiconductor film 1009, and the semiconductor film 1010 are selectively Etch.

[0407] Specifically, first, a resist is formed on a part of the semiconductor film 1010. The resist is, for example, The film is formed by using a photolithography technique, an ink jet method, or the like.

[0408] Next, a microcrystalline semiconductor film 1008, an amorphous semiconductor film 1009, and The semiconductor film 1010 is selectively etched. At this time, the etching results in the formation of a thin film as shown in FIG. As shown in FIG. 1, a microcrystalline semiconductor layer 1003 is formed. Note that the resist is removed after etching. It is preferable that

[0409] In this etching process, the microcrystalline semiconductor film, the amorphous semiconductor film, and the impurity semiconductor film It is preferable to perform etching so that the end of the laminated layer has a tapered shape. The taper angle is limited to a range of 30° to 90°, preferably 40° to 80°. By etching the end portion so that it has a tapered shape, The conductive film 1010 and the microcrystalline semiconductor film 1008 can be prevented from being in direct contact with each other. Furthermore, the distance between these layers at the end can be sufficiently secured, and the The peak current can be reduced.

[0410] Furthermore, by tapering the end portions, the covering of the layer formed on them in a later process can be improved. This can improve the covering ability.

[0411] Next, as shown in FIG. 20(F), a conductive film 1011 is formed on the semiconductor film 1010.

[0412] The conductive film 1011 is formed by using, for example, a sputtering method or a vacuum deposition method. The conductive film 1011 can be made of conductive nanopaste such as silver, gold, or copper. It can also be formed by discharging the material using a screen printing method or an ink jet method, and then baking it. Cut.

[0413] Next, the conductive film 1011 is etched. Specifically, first, a selective lithography is performed on the conductive film 1011. Next, the conductive film 1011 is etched using the resist as a mask. At this time, a pair of electrodes 1006a and 1006b is formed as shown in FIG. 21(G).

[0414] Next, the semiconductor film 1010 and the amorphous semiconductor film 1009 are etched. As shown in FIG. 21(H), the buffer layer 1004 and the pair of semiconductor layers 1005a and A semiconductor layer 1005b is formed.

[0415] At this time, the formed buffer layer 1004 is partially etched to form a recess. However, it is preferable to form the amorphous semiconductor film 1009 so that a part of the amorphous semiconductor film 1009 overlapping the recess remains. The thickness of the remaining etched portion (the portion overlapping the recess) after etching is preferably It is preferable that the thickness of the film before etching is about half of the thickness of the film before etching. As mentioned above, the thickness is 100 nm or more and 500 nm or less, preferably 150 nm or more and 40 The thickness of the buffer layer 100 is preferably 200 nm or more and 300 nm or less. The reference numeral 4 functions as an etching stopper for the microcrystalline semiconductor layer 1003 .

[0416] In this embodiment, the ends of the electrodes 1006a and 1006b and the semiconductor layer 10 The edges of the semiconductor layer 1005a and the semiconductor layer 1005b may not coincide with each other. As a result, the distance between the ends of the electrodes 1006a and 1006b increases, and the source electrode or the drain electrode The distance between one of the input electrodes and the other of the source and drain electrodes is sufficiently large. This reduces the leakage current and prevents short circuits. The ends of the electrodes 1006a and 1006b and the ends of the semiconductor layers 1005a and 1005b Since the shapes of the electrodes 1006a and 1006b do not match, the ends of the electrodes 1006a and 1006b and the semiconductor Electric field concentration is unlikely to occur at the ends of the layer 1005a and the semiconductor layer 1005b. Therefore, it is possible to manufacture a thin film transistor that is highly reliable, has a small off-state current, and has a high withstand voltage. can be done.

[0417] Through the above steps, the thin film transistor shown in FIG. 18 can be manufactured.

[0418] As shown in FIG. 18 as an example, a transistor including a microcrystalline semiconductor layer is Since the reliability is higher than that of a transistor using only a semiconductor layer, By applying this to a driving circuit, malfunctions can be suppressed.

[0419] Note that this embodiment mode can be combined with other embodiment modes as appropriate.

[0420] (Embodiment 5) In this embodiment, an electronic device using a display device according to one embodiment of the present invention as a display portion will be described. explain.

[0421] The display device according to one embodiment of the present invention can be used as a display portion of various electronic devices. Examples of electronic devices to which the display device according to one embodiment of the present invention can be applied include a video camera, Cameras such as digital cameras, goggle-type displays (head-mounted displays) , navigation systems, sound reproduction devices (car audio, audio components, etc.), Notebook personal computers, game devices, mobile phones, portable information terminals (mobile computers) computer, portable music player, portable game console, e-book, or computer (including those with multiple functions due to multiple data processing functions built in) or Image reproduction device equipped with a recording medium (specifically, Digital Versatile Digital A device equipped with a display that can play back recording media such as DVDs and display the images. Specific examples of these electronic devices are explained using Figures 22 and 23. 22 and 23 are diagrams showing an example of the configuration of an electronic device according to this embodiment. .

[0422] FIG. 22A shows a display device, which includes a housing 1101, a support base 1102, a display unit 11, and a display section 11. 1103, a speaker unit 1104, a video input terminal 1105, etc. A display device having such a configuration can be used for the display portion 1103. This includes all display devices for personal computers, TV broadcast reception, advertising displays, etc. It can be enjoyed.

[0423] FIG. 22B shows a digital still camera, which includes a main body 1111, a display unit 1112, an image receiving unit, and a display unit 1113. 1113, operation keys 1114, external connection port 1115, shutter button 1116, etc. The display device which is one embodiment of the present invention can be used for the display portion 1112.

[0424] FIG. 22C shows a notebook personal computer, which includes a main body 1121 and a housing 1122. , a display unit 1123, a keyboard 1124, an external connection port 1125, a pointing device The display device of one embodiment of the present invention can be used for the display portion 1123. This can be done.

[0425] FIG. 22(D) shows a mobile computer, which includes a main body 1131, a display unit 1132, a switch, and The device includes a touch panel 1133, operation keys 1134, an infrared port 1135, etc. Such a display device can be used as the display portion 1132.

[0426] FIG. 22(E) shows a portable image playback device (specifically, a DVD playback device) equipped with a recording medium. a main body 1141, a housing 1142, a display unit A 1143, a display unit B 1144, a recording medium It includes a reading unit 1145 (such as a DVD), operation keys 1146, a speaker unit 1147, and the like. The display unit A 1143 mainly displays image information, and the display unit B 1144 mainly displays text information. The display device according to one embodiment of the present invention has the display portion A1143 and the display portion B11 44. In addition, image playback devices equipped with recording media include home game consoles. Also included are:

[0427] Figure 22(F) shows a goggle-type display (head-mounted display), The display device according to one embodiment of the present invention includes a display portion 1151, a display portion 1152, and an arm portion 1153. , can be used for the display unit 1152.

[0428] FIG. 22(G) shows a video camera, which includes a main body 1161, a display unit 1162, a housing 1163, External connection port 1164, remote control receiver 1165, image receiver 1166, battery 116 7, a voice input unit 1168, operation keys 1169, an eyepiece unit 1170, etc. Any of various display devices can be used for the display portion 1162.

[0429] FIG. 22(H) shows a mobile phone, which includes a main body 1171, a housing 1172, a display unit 1173, and an audio Input unit 1174, audio output unit 1175, operation keys 1176, external connection port 1177, The display device according to one embodiment of the present invention includes a display portion 1173. The display unit 1173 displays white characters on a black background, making it easy to see the contents of a mobile phone. This can reduce the current consumption of the mobile phone.

[0430] FIG. 23 shows an example of a portable information terminal having multiple functions. 23(B) is a front view of the portable information terminal, FIG. 23(C) is a rear view of the portable information terminal. The portable information terminal shown in FIG. 23 can have multiple functions. For example, in addition to telephone functions, it may have a built-in computer and various data processing functions. It can also be done as follows.

[0431] The portable information terminal shown in FIG. 23 is composed of two housings, a housing 1180 and a housing 1181. The housing 1180 includes a display unit 1182, a speaker 1183, a microphone 1184, and a microphone 1185. 184, operation keys 1185, pointing device 1186, camera lens 1187 , an external connection terminal 1188, an earphone terminal 1189, etc., and the housing 1181 is Card 1190, external memory slot 1191, camera lens 1192, light 1193 The antenna is built into the housing 1181.

[0432] In addition to the above configuration, a contactless IC chip, a small recording device, etc. may be built in. .

[0433] The display device which is one embodiment of the present invention can be used for the display portion 1182 depending on the usage mode. The display direction changes accordingly. 87, it is possible to make a video call. Also, the display unit 1182 is The camera lens 1192 and light 1193 allow for still and moving images to be taken. The speaker 1183 and microphone 1184 are not limited to voice calls, but also for video calls and recording. The operation keys 1185 are used for simple operations such as making and receiving calls and sending e-mails. It is possible to input information, scroll the screen, move the cursor, etc. The housing 1180 and the housing 1181 (FIG. 23(A)) slide and unfold as shown in FIG. 23(C). In this case, the keyboard 1190, the pointing device, Smooth operation is possible using a vice 1186. The external connection terminal 1188 is an AC adapter. It can be connected to various cables such as USB cables for charging and personal computer use. It is also possible to insert a recording medium into the external memory slot 1191. It can accommodate larger amounts of data storage and transfer.

[0434] In addition to the above functions, it also has infrared communication functions, TV reception functions, etc. Good too.

[0435] As described above, the display device which is one embodiment of the present invention can be used for displaying various electronic devices. It can be applied as part.

[0436] Note that this embodiment mode can be combined with other embodiment modes as appropriate. [Explanation of symbols]

[0437] 11 Transistor 12 transistors 13 Transistor 14 Transistor 15 transistors 100 terminals 101 terminal 102 terminals 102A terminal 102B terminal 103 terminal 103A terminal 103B terminal 103C terminal 103D terminal 104 terminals 104A terminal 104B terminal 104C terminal 104D terminal 104E terminal 104F terminal 104G terminal 104H terminal 104I terminal 104J terminal 104K terminal 104L terminal 104M terminal 105 terminal 106 transistors 107 Transistor 108 Capacitor 109 Transistor 110 Transistor 111 Transistor 112 Capacitor element 113 Transistor 114 transistors 115 transistors 116 transistors 117 nodes 118 nodes 119 nodes 120 transistors 121 terminal 122 transistors 123 Transistor 124 transistors 125 terminals 126 transistors 127 transistors 128 transistors 129 transistors 201 Control Signal 202 Clock Signal 203 Clock Signal 204 Potential 205 Potential 206 Potential 207 Output Signal 208 Control Signal 209 Output Signal 500 terminals 501 terminal 502 terminal 502A terminal 502B terminal 503 terminal 503A terminal 503B terminal 503C terminal 503D terminal 504 terminal 504A terminal 504B terminal 504C terminal 504D Terminal 504E terminal 504F terminal 504G terminal 504H terminal 504I terminal 504J terminal 504K terminal 505 terminal 506 Transistor 507 Transistor 508 Transistor 509 Transistor 510 Capacitor element 511 Transistor 512 transistors 513 Transistor 514 Transistor 515 nodes 516 nodes 517 Transistor 518 terminals 519 Transistor 520 transistor 521 Transistor 522 terminal 523 Transistor 524 transistors 525 transistor 526 Transistor 601 Control Signal 602 Clock Signal 603 Clock Signal 604 Potential 605 Potential 606 Output Signal 607 Control Signal 608 Output Signal 700 pixel unit 701 Signal line driver circuit 702 Scanning line driving circuit 703 Control Circuit 704 Clock signal generation circuit 705 Signal Line 705A signal line 705B signal line 706 scan lines 706A Scan Line 706B scan line 706C Scan Line 706D Scanning Line 707 Clock signal line 708 Clock signal line 709 pixels 710 Flip-Flop Circuit 710A Flip-Flop Circuit 710B flip-flop circuit 710C Flip-Flop Circuit 710D Flip-Flop Circuit 750 pixels 751 Transistor 752 Liquid crystal elements 753 Capacitor 754 Wiring 755 Wiring 756 Wiring 757 Wiring 758 Electrode 801 start signal 802 clock signal 803 Clock Signal 804 output signal 805 output signal 806 Output Signal 807 Output Signal 900 boards 901 Impurity region 902 Semiconductor layer 903 Gate insulating film 904 Gate electrode 905a electrode 905b electrode 906 Interlayer insulating film 907 Circuit Board 908 Gate electrode 910 Gate insulating film 911 Semiconductor layer 912 Semiconductor layer 912a Semiconductor layer 912b Semiconductor layer 913a electrode 913b electrode 1000 boards 1001 gate electrode 1002 Gate insulating film 1003 Microcrystalline semiconductor layer 1004 buffer layer 1005a Semiconductor layer 1005b Semiconductor layer 1006a electrode 1006b electrode 1007 Conductive film 1008 Microcrystalline semiconductor film 1009 Amorphous semiconductor film 1010 Semiconductor film 1011 Conductive film 1101 Case 1102 Support stand 1103 Display section 1104 Speaker section 1105 Video input terminal 1111 Main unit 1112 Display section 1113 Image receiving unit 1114 Operation key 1115 External connection port 1116 Shutter button 1121 Main unit 1122 Case 1123 Display section 1124 keyboard 1125 External connection port 1126 Pointing Device 1131 Main unit 1132 Display section 1133 Switch 1134 Operation key 1135 Infrared port 1141 Main unit 1142 Case 1143 Display part A 1144 Display part B 1145 Reading section 1146 Operation Key 1147 Speaker section 1151 Main unit 1152 Display section 1153 Arm 1161 Main unit 1162 Display section 1163 Case 1164 external connection port 1165 Remote control receiver 1166 Image receiving unit 1167 Battery 1168 Audio Input Unit 1169 Operation Key 1170 Eyepiece 1171 Main Unit 1172 Case 1173 Display section 1174 Audio Input Unit 1175 Audio output section 1176 Operation Key 1177 External connection port 1178 Antenna 1180 chassis 1181 Case 1182 Display section 1183 Speaker 1184 Microphone 1185 Operation Key 1186 Pointing Device 1187 Camera Lenses 1188 External connection terminal 1189 earphone jack 1190 keyboard 1191 External memory slot 1192 Camera Lenses 1193 Light

Claims

1. having first to ninth transistors, one of the source and the drain of the first transistor is always electrically connected to a first clock signal line; the other of the source and the drain of the first transistor is always electrically connected to an output signal line; one of the source and the drain of the second transistor is always electrically connected to the output signal line; the gate of the second transistor is always electrically connected to the first signal line; one of the source and the drain of the third transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the third transistor is always electrically connected to a second signal line; a gate of the third transistor is always electrically connected to the second signal line; one of the source and the drain of the fourth transistor is always electrically connected to a power supply line; the other of the source and the drain of the fourth transistor is always electrically connected to the gate of the first transistor; one of the source and the drain of the fifth transistor is always electrically connected to the power supply line; the other of the source and the drain of the fifth transistor is always electrically connected to the gate of the fourth transistor; a gate of the fifth transistor is always electrically connected to the second signal line; one of the source and the drain of the sixth transistor is always electrically connected to the power supply line; the other of the source and the drain of the sixth transistor is always electrically connected to the gate of the first transistor; the gate of the sixth transistor is always electrically connected to the third signal line; one of the source and the drain of the seventh transistor is always electrically connected to the power supply line; the other of the source and the drain of the seventh transistor is always electrically connected to the output signal line; one of the source and the drain of the eighth transistor is always electrically connected to the power supply line; the other of the source and the drain of the eighth transistor is always electrically connected to the gate of the first transistor; a gate of the eighth transistor is always electrically connected to a gate of the seventh transistor; one of the source and the drain of the ninth transistor is always electrically connected to the power supply line; the other of the source and the drain of the ninth transistor is always electrically connected to the gate of the seventh transistor; a gate of the ninth transistor is always electrically connected to the second signal line; when the other of the source or the drain of the second transistor is in a conductive state with the output signal line via at least a channel formation region of the second transistor, a potential of the other of the source or the drain of the second transistor is input to the output signal line via at least a channel formation region of the second transistor, A semiconductor device in which the signal on the first signal line is not input to the gate of the fourth transistor or the other of the source and drain of the fifth transistor.

2. having first to ninth transistors, one of the source and the drain of the first transistor is always electrically connected to a first clock signal line; the other of the source and the drain of the first transistor is always electrically connected to an output signal line; one of the source and the drain of the second transistor is always electrically connected to the output signal line; the gate of the second transistor is always electrically connected to the first signal line; one of the source and the drain of the third transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the third transistor is always electrically connected to a second signal line; a gate of the third transistor is always electrically connected to the second signal line; one of the source and the drain of the fourth transistor is always electrically connected to a power supply line; the other of the source and the drain of the fourth transistor is always electrically connected to the gate of the first transistor; one of the source and the drain of the fifth transistor is always electrically connected to the power supply line; the other of the source and the drain of the fifth transistor is always electrically connected to the gate of the fourth transistor; a gate of the fifth transistor is always electrically connected to the second signal line; one of the source and the drain of the sixth transistor is always electrically connected to the power supply line; the other of the source and the drain of the sixth transistor is always electrically connected to the gate of the first transistor; the gate of the sixth transistor is always electrically connected to the third signal line; one of the source and the drain of the seventh transistor is always electrically connected to the power supply line; the other of the source and the drain of the seventh transistor is always electrically connected to the output signal line; one of the source and the drain of the eighth transistor is always electrically connected to the power supply line; the other of the source and the drain of the eighth transistor is always electrically connected to the gate of the first transistor; a gate of the eighth transistor is always electrically connected to a gate of the seventh transistor; one of the source and the drain of the ninth transistor is always electrically connected to the power supply line; the other of the source and the drain of the ninth transistor is always electrically connected to the gate of the seventh transistor; a gate of the ninth transistor is always electrically connected to the second signal line; when the other of the source or the drain of the second transistor is in a conductive state with the output signal line via at least a channel formation region of the second transistor, a potential of the other of the source or the drain of the second transistor is input to the output signal line via at least a channel formation region of the second transistor, a signal on the first signal line is not input to the gate of the fourth transistor and the other of the source and drain of the fifth transistor; At least one of the first to ninth transistors is a first conductive layer having a region that functions as a gate electrode; a first insulating layer having a region located above the first conductive layer and functioning as a gate insulating film; an oxide semiconductor layer having a region located above the first insulating layer and functioning as a channel formation region; a second conductive layer having a region located above the oxide semiconductor layer and functioning as a source electrode; a third conductive layer having a region located above the oxide semiconductor layer and functioning as a drain electrode, the first conductive layer comprises titanium and copper; the first insulating layer includes oxygen and silicon; The second conductive layer and the third conductive layer include titanium and copper.

3. A semiconductor device comprising: the semiconductor device according to claim 1; and a pixel; the pixel has a tenth transistor; one of the source and the drain of the tenth transistor is always electrically connected to the liquid crystal element; the other of the source and the drain of the tenth transistor is always electrically connected to a fourth signal line; the gate of the tenth transistor is always electrically connected to the output signal line; A display device in which the liquid crystal element is driven in an FFS mode.

Images