Semiconductor device

Abstract

To suppress fluctuation in electric characteristics in a transistor including an oxide semiconductor film.SOLUTION: A transistor comprises a first gate electrode, a first insulation film on the first gate electrode, an oxide semiconductor film on the first insulation film, a source electrode on the oxide semiconductor film, a drain electrode on the oxide semiconductor film, second insulation films on the oxide semiconductor film, the source electrode, and the drain electrode, and second gate electrodes on the second insulation films. The first insulation film includes a first opening, and a connection electrode electrically connected to the first gate electrode via the first opening is formed on the first insulation film. The second insulation film includes a second opening reaching the connection electrode. The second gate electrode includes an oxide conductive film and a metal film on the oxide conductive film. The connection electrode and the second gate electrode are electrically connected using the metal film.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] One embodiment of the present invention is a semiconductor device including an oxide semiconductor film and a display device including the semiconductor device. Another embodiment of the present invention relates to a method for manufacturing a semiconductor device including an oxide semiconductor film. Regarding the law.

[0002] Note that one embodiment of the present invention is not limited to the above technical fields. The technical field of one aspect of the present invention relates to an article, a method, or a manufacturing method. is a process, machine, manufacture, or composition of matter. In particular, one embodiment of the present invention relates to a semiconductor device, a display device, a light-emitting device, a power storage device, , a storage device, a driving method thereof, or a manufacturing method thereof.

[0003] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. Refers to devices in general, including semiconductor elements such as transistors, semiconductor circuits, arithmetic units, and memory The device is one aspect of a semiconductor device. Optical devices, power generation devices (including thin-film solar cells, organic thin-film solar cells, etc.), and electronic devices The device may include a semiconductor device. [Background technology]

[0004] A transistor (field-effect transistor) is made using a semiconductor thin film formed on a substrate with an insulating surface. The technology that makes up the field-effect transistor (FET) or thin-film transistor (TFT) is attracting attention. The transistor is used in integrated circuits (ICs) and image display devices (display devices). It is widely used in electronic devices. Silicon is a semiconductor thin film that can be used in transistors. Semiconductor materials, such as silicon, are widely known, but oxide semiconductors are also attracting attention. It is being watched.

[0005] For example, a transistor with a dual gate structure in which an oxide semiconductor film is provided between two gate electrodes is used. By using a transistor, the formation of a parasitic channel due to gate BT stress is suppressed. A semiconductor device is disclosed (see Patent Document 1). [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2014-241404 Summary of the Invention [Problem to be solved by the invention]

[0007] As a transistor using an oxide semiconductor film for the channel region, It is preferable that the mobility (or μFE) is high. As shown in the figure, a transistor with a dual gate structure in which an oxide semiconductor film is provided between two gate electrodes is used. By using a transistor, it is possible to increase the on-state current and field-effect mobility of the transistor. can.

[0008] In addition, when a transistor with a dual gate structure is used, one gate electrode and the other gate It is preferable that the connection resistance with the gate electrode is low. The problem is that the electrical characteristics are unstable.

[0009] In addition, as a transistor using an oxide semiconductor film for a channel region, The oxygen vacancies formed in the semiconductor layer are problematic because they affect transistor characteristics. When oxygen vacancies are formed in the oxide semiconductor film, hydrogen bonds to the oxygen vacancies to supply carriers. When a carrier supply source is generated in the oxide semiconductor film, The electrical characteristics of the transistor change, typically the threshold voltage shift. Therefore, the electrical characteristics of each transistor vary. In the channel region, the fewer oxygen vacancies the better.

[0010] In view of the above problems, one embodiment of the present invention provides a transistor including an oxide semiconductor film, One of the objectives is to suppress fluctuations in electrical characteristics and improve reliability. One aspect of the present invention is a transistor having a dual gate structure having two gate electrodes. In this case, the connection resistance between one gate electrode and the other gate electrode is reduced, resulting in stable electrical characteristics. Another object of the present invention is to provide a semiconductor device having It is an object of the present invention to provide a semiconductor device with reduced power consumption. An object of the present invention is to provide a novel semiconductor device. One of the objects of the present invention is to provide a novel display device.

[0011] The above description of the problem does not preclude the existence of other problems. The embodiment does not necessarily have to solve all of these problems. Problems other than those mentioned above can be solved by the specification. It is clear from the description of the specification, etc. that the problems other than those mentioned above cannot be extracted from the description of the specification, etc. It is possible to issue it. [Means for solving the problem]

[0012] One embodiment of the present invention is a semiconductor device including a transistor, the transistor comprising: a gate electrode, a first insulating film on the first gate electrode, and an oxide semiconductor on the first insulating film; a source electrode on the oxide semiconductor film; a drain electrode on the oxide semiconductor film; a second insulating film on the conductor film, the source electrode, and the drain electrode; and a second gate insulating film on the second insulating film. a gate electrode, the first insulating film having a first opening, and a first insulating film having a first opening and a first A connection electrode is formed which is electrically connected to the first gate electrode through the opening, and a second insulating film is formed. The insulating film has a second opening that reaches the connection electrode, and the second gate electrode includes an oxide conductive film and a metal film on the oxide conductive film, and the connection electrode and the second gate electrode are formed using the metal film. The semiconductor device is electrically connected.

[0013] Another embodiment of the present invention is a semiconductor device including a transistor, The gate electrode includes a first gate electrode, a first insulating film on the first gate electrode, and an oxide film on the first insulating film. a source electrode on the oxide semiconductor film; and a drain electrode on the oxide semiconductor film. a second insulating film on the oxide semiconductor film, the source electrode, and the drain electrode; a second gate electrode, the first insulating film having a first opening, and a a connection electrode electrically connected to the first gate electrode through the first opening is formed on the The second insulating film has a second opening that reaches the connection electrode and a second opening that reaches either the source electrode or the drain electrode. and a third opening reaching either one of the first gate electrode and the second gate electrode. a metal film on the oxide conductive film, and a conductive film having the same composition as the metal film is formed in the third opening. The connection electrode and the second gate electrode are electrically connected using a metal film. is.

[0014] In the above embodiment, the source electrode and the drain electrode are respectively made of a first metal film and a first a second metal film in contact with the first metal film, and a third metal film in contact with the second metal film, The second metal film contains copper, and the first metal film and the third metal film each suppress copper diffusion. The first metal film has an edge that is located outside the edge of the second metal film. The third metal film covers the top and side surfaces of the second metal film and is in contact with the first metal film. It is preferable that the region has a

[0015] In the above-mentioned embodiment, the metal film, the conductive film, the first metal film, and the third metal film are Each of them is independently selected from titanium, tungsten, tantalum, and molybdenum. It is preferable to have one or more.

[0016] In the above embodiment, the oxide conductive film contains a metal element contained in the oxide semiconductor film less. It is preferable to have one of both.

[0017] In the above embodiment, the oxide semiconductor film contains In and M (M is Al, Ga, Y, or In the above embodiment, the oxide semiconductor film preferably contains Sn and Zn. It is preferable that the crystal portion has a c-axis orientation.

[0018] Another aspect of the present invention is a semiconductor device comprising: a display; Another embodiment of the present invention is a display device including the display device and a touch sensor. Another aspect of the present invention is a display module having any of the above aspects. a semiconductor device, the display device, or the display module according to any one of the preceding claims, and an operation key or is an electronic device having a battery. [Effects of the Invention]

[0019] According to one embodiment of the present invention, a transistor including an oxide semiconductor film can be manufactured by changing electrical characteristics. Furthermore, the present invention can suppress the vibration and improve the reliability. In a transistor having a dual gate structure with two gate electrodes, one of the gates Semiconductor device having stable electrical characteristics by reducing the connection resistance between an electrode and the other gate electrode According to one embodiment of the present invention, a semiconductor device with reduced power consumption can be provided. According to one embodiment of the present invention, a novel semiconductor device can be provided. According to one embodiment of the present invention, a novel display device can be provided. Cut.

[0020] The description of these effects does not preclude the existence of other effects. An embodiment does not necessarily have to have all of these effects. The above will be made clear from the description, drawings, claims, etc. It is possible to extract other effects from the descriptions in the aspects and claims. [Brief explanation of the drawings]

[0021] [Figure 1] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 2] FIG. 1 is a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 3] FIG. 1 is a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 4] FIG. 1 is a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 5] FIG. 1 is a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 6] FIG. 1 is a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 7] 1A to 1C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device. [Figure 8] 1A to 1C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device. [Figure 9] 1A to 1C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device. [Figure 10] 1A to 1C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device. [Figure 11] 1A to 1C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device. [Figure 12] 1A to 1C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device. [Figure 13] FIG. 10 is a diagram illustrating the range of the atomic ratio of an oxide semiconductor. [Figure 14] A diagram explaining the InMZnO4 crystal. [Figure 15] FIG. 1 is a band diagram of a stacked structure of oxide semiconductors. [Figure 16] 1A and 1B are diagrams illustrating structural analysis of a CAAC-OS and a single-crystal oxide semiconductor by XRD, and selected-area electron diffraction patterns of a CAAC-OS. [Figure 17] Cross-sectional TEM image of CAAC-OS, as well as planar TEM image and its image analysis image. [Figure 18] Electron diffraction pattern of nc-OS and cross-sectional TEM image of nc-OS. [Figure 19] Cross-sectional TEM image of a-like OS. [Figure 20] FIG. 1 shows the change in the crystalline part of an In-Ga-Zn oxide due to electron irradiation. [Figure 21] FIG. 1 is a top view illustrating one embodiment of a display device. [Figure 22] FIG. 1 is a cross-sectional view illustrating one embodiment of a display device. [Figure 23] FIG. 1 is a cross-sectional view illustrating one embodiment of a display device. [Figure 24] FIG. 1 is a cross-sectional view illustrating one embodiment of a display device. [Figure 25]FIG. 1 is a cross-sectional view illustrating one embodiment of a display device. [Figure 26] FIG. 1 is a cross-sectional view illustrating one embodiment of a display device. [Figure 27] FIG. 1 is a cross-sectional view illustrating one embodiment of a display device. [Figure 28] 1A and 1B are a block diagram and a circuit diagram illustrating a display device. [Figure 29] 1A and 1B are a circuit diagram and a timing chart illustrating one embodiment of the present invention. [Figure 30] 1A and 1B are graphs and circuit diagrams illustrating one embodiment of the present invention. [Figure 31] 1A and 1B are a circuit diagram and a timing chart illustrating one embodiment of the present invention. [Figure 32] 1A and 1B are a circuit diagram and a timing chart illustrating one embodiment of the present invention. [Figure 33] 1A to 1C are a block diagram, a circuit diagram, and waveform diagrams illustrating one embodiment of the present invention. [Figure 34] 1A and 1B are a circuit diagram and a timing chart illustrating one embodiment of the present invention. [Figure 35] FIG. 1 is a circuit diagram illustrating one embodiment of the present invention. [Figure 36] FIG. 1 is a circuit diagram illustrating one embodiment of the present invention. [Figure 37] FIG. 2 is a diagram illustrating a display module. [Figure 38] 1A to 1C illustrate electronic devices. [Figure 39] 1A to 1C illustrate electronic devices. [Figure 40] FIG. 1 is a perspective view illustrating a display device. DETAILED DESCRIPTION OF THE INVENTION

[0022] Hereinafter, embodiments will be described with reference to the drawings. It is understood that the present invention may be embodied in various different forms without departing from its spirit and scope. It will be readily apparent to those skilled in the art that various modifications may be made to the embodiments and details of the present invention. However, the present invention should not be construed as being limited to the description of the following embodiments.

[0023] Also, in the drawings, the size, thickness of layers, or areas are exaggerated for clarity. Therefore, the scale is not necessarily limited to that shown. The drawings are merely schematic illustrations and are not limited to the shapes or values ​​shown in the drawings.

[0024] In addition, the ordinal numbers "first," "second," and "third" used in this specification refer to the number of components. It should be noted that this is added to avoid confusion and is not intended to limit the number.

[0025] In addition, in this specification, the terms "above" and "below" that indicate the position of components are used to indicate the position of components. The positional relationship is used for convenience in describing the configuration with reference to the drawings. The relationship between the two components changes depending on the direction in which each component is depicted. The phrases are not limited to those used above, but can be rephrased appropriately depending on the situation.

[0026] In this specification, a transistor includes a gate, a drain, and a source. It is an element having at least three terminals including a drain (drain terminal, drain Between the drain electrode and the source terminal The semiconductor device has a channel region therein, and a current flows through the drain, the channel region, and the source. In this specification and the like, the channel region is a region where a current mainly flows. The flow area.

[0027] The functions of the source and drain may differ depending on whether transistors with different polarities are used or whether the circuit This may happen when the direction of the current changes during operation. In the specification, the terms source and drain may be used interchangeably. do.

[0028] In addition, in this specification, "electrically connected" means "something that has some kind of electrical effect." This includes cases where the device is connected via a "of" is not subject to any particular restrictions as long as it allows the transmission and reception of electrical signals between connected objects. For example, "things that have some kind of electrical action" include electrodes, wiring, and transistors. It has various functions such as switching elements, resistors, inductors, capacitors, etc. This includes elements such as:

[0029] In this specification, "parallel" means that two straight lines are at an angle of -10° or more and 10° or less. Therefore, it includes cases where the angle is between -5° and 5°. "Perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, this also includes cases where the angle is between 85° and 95°.

[0030] In addition, in this specification and the like, the terms "film" and "layer" are interchangeable. For example, the term "conductive layer" can be changed to the term "conductive film." Alternatively, for example, the term "insulating film" may be changed to "insulating layer" It may be possible to change the term to

[0031] Unless otherwise specified, in this specification and the like, the off-state current refers to the current that flows when a transistor is off. This refers to the drain current when the device is in a non-conducting state (also known as a cut-off state). Unless otherwise specified, for an n-channel transistor, the voltage V between the gate and source When gs is lower than the threshold voltage Vth, the gate and This refers to the state in which the voltage Vgs between the n-channel and n-channel transistors is higher than the threshold voltage Vth. The off-state current of a transistor is the voltage between the gate and source, Vgs, that is, the threshold voltage, Vt It may refer to the drain current when it is lower than h.

[0032] The off-state current of a transistor may depend on Vgs. The off-state current is I or less if there is a Vgs value at which the off-state current of the transistor is I or less. The off-state current of a transistor is the current that flows through it in the off state at a given Vgs. , an off-state at Vgs within a predetermined range or a sufficiently reduced off-current is obtained. It may refer to the off-state current at Vgs.

[0033] As an example, when the threshold voltage Vth is 0.5V and Vgs is 0.5V, The on-current is 1×10 -9 A, and the drain current at Vgs of 0.1 V is 1×10 -1 3 A, and the drain current at Vgs = -0.5 V is 1 × 10 -19 A and Vg The drain current at s = -0.8V is 1×10 -22 A n-channel transistor The drain current of the transistor is as follows when Vgs is -0.5V: , or 1×10 when Vgs is in the range of -0.5V to -0.8V -19 A or below Therefore, the off-state current of the transistor is 1×10 -19 It may be said that it is below A. The drain current of the transistor is 1×10 -22 A or less Vgs exists. Therefore, the off-state current of the transistor is 1×10 -22 It may be said that it is below A.

[0034] In this specification and the like, the off-state current of a transistor having a channel width W is calculated based on the It is sometimes expressed as the current value that flows per watt. In the latter case, the unit of the off-state current is current / length. It may be expressed in units with an element (e.g., A / μm).

[0035] The off-state current of a transistor may depend on temperature. Unless otherwise specified, the values ​​are measured at room temperature, 60°C, 85°C, 95°C, or 125°C. It may also represent the current that is generated when the reliability of a semiconductor device that includes the transistor is guaranteed. or the temperature at which a semiconductor device containing the transistor is used (e.g. For example, the off-state current at any temperature between 5°C and 35°C. The off-state current of the transistor is I or less at room temperature, 60°C, 85°C, 95°C, 125°C, The temperature at which the reliability of the semiconductor device including the transistor is guaranteed, or The temperature at which the semiconductor device containing the transistor is used (for example, any one of 5°C to 35°C) (temperature), there exists a value of Vgs at which the off-state current of the transistor is less than I. It may point to.

[0036] The off-state current of a transistor can depend on the voltage Vds between the drain and source In this specification, unless otherwise specified, the off-state current is measured when Vds is 0.1 V, 0.8 V, 1V, 1.2V, 1.8V, 2.5V, 3V, 3.3V, 10V, 12V, 16V, or In some cases, the value represents the off-state current at 20 V. Alternatively, the value represents the off-state current of the semiconductor containing the transistor. Vds that guarantees the reliability of semiconductor devices, or semiconductor devices that include the transistor The off-state current of a transistor at Vds is sometimes used in The current is I or less when Vds is 0.1V, 0.8V, 1V, 1.2V, 1.8V, 2.5V, 3V, 3.3V, 10V, 12V, 16V, 20V, transistors included Vds that guarantees the reliability of the semiconductor device in which the transistor is used, or the semiconductor Vds used in semiconductor devices, etc., where the off-state current of the transistor is I or less It may refer to the existence of a gs value.

[0037] In the above description of the off-state current, the drain may be read as the source. Current may also refer to the current through the source when the transistor is in the off state.

[0038] In this specification and the like, the term "leak current" may be used to mean the same thing as "off-state current." In this specification, the off-state current is, for example, the current when a transistor is in an off state. , may refer to the current flowing between the source and drain.

[0039] In addition, even when the term "semiconductor" is used in this specification, for example, a material having electrical conductivity is also included. If the dielectric constant is low enough, it may have the properties of an "insulator." The boundary between "insulator" and "insulator" is vague and it may not be possible to strictly distinguish them. The term "semiconductor" in the above may be replaced with "insulator." The term "insulator" in the specification etc. may be replaced with "semiconductor." In some cases, the term "insulator" used in this specification can be rephrased as "semi-insulator." .

[0040] In addition, even when the term "semiconductor" is used in this specification, for example, a material having electrical conductivity is also included. If the electrical conductivity is sufficiently high, it may have the properties of a "conductor." The boundary between "conductor" and "electroconductor" is vague and it may not be possible to strictly distinguish them. The term "semiconductor" in the above may be replaced with "conductor." The term "conductor" in the specification etc. may be replaced with "semiconductor" in some cases.

[0041] In this specification, impurities in a semiconductor refer to substances other than the main components that constitute the semiconductor film. For example, elements with a concentration of less than 0.1 atomic percent are impurities. This can cause the formation of DOS (Density of States) in semiconductors and The rear mobility and crystallinity may decrease. In the case of an oxide semiconductor, impurities that change the properties of the semiconductor include, for example, Group 1 impurities. There are elements, group 2 elements, group 14 elements, group 15 elements, transition metals other than the main component, etc. hydrogen (also found in water), lithium, sodium, silicon, boron, phosphorus, carbon, In the case of oxide semiconductors, oxygen vacancies can occur due to the inclusion of impurities such as hydrogen. In addition, when the semiconductor contains silicon, the properties of the semiconductor may be changed. Examples of impurities include oxygen, Group 1 elements excluding hydrogen, Group 2 elements, Group 13 elements, Group 15 elements, etc.

[0042] (Embodiment 1) In this embodiment, a semiconductor device and a manufacturing method of the semiconductor device according to one embodiment of the present invention will be described. The description will be made with reference to FIGS.

[0043] <1-1. Configuration example 1 of semiconductor device> FIG. 1A is a top view of a transistor 100 which is a semiconductor device of one embodiment of the present invention. 1(B) corresponds to a cross-sectional view of the cut surface taken along the dashed line X1-X2 shown in FIG. 1(A). 1(C) is a cross-sectional view taken along the dashed line Y1-Y2 in FIG. 1(A). In FIG. 1A, in order to avoid complication, the transistor 100 Some of the components (such as the insulating film that functions as the gate insulating film) are omitted in the illustration. The dashed line X1-X2 direction is the channel length direction, and the dashed line Y1-Y2 direction is the channel width direction. In the top view of the transistor, 1(A), some of the components may be omitted.

[0044] The transistor 100 includes a conductive film 104 on a substrate 102 and a conductive film 104. an insulating film 106 on the insulating film 106; an insulating film 107 on the insulating film 106; and an oxide semiconductor on the insulating film 107. the oxide semiconductor film 108, the conductive film 112a on the oxide semiconductor film 108, and the conductive film 112b on the oxide semiconductor film 108. the conductive film 112b, and the insulating films over the oxide semiconductor film 108, the conductive film 112a, and the conductive film 112b. The insulating film 114, the insulating film 116 on the insulating film 114, the conductive film 120a on the insulating film 116, and the insulating film 120b are formed on the insulating film 114. and a conductive film 120b on the insulating film 116.

[0045] The insulating film 106 and the insulating film 107 have an opening 151. On the film 107, a conductive film 112 electrically connected to the conductive film 104 through the opening 151 is formed. The insulating film 114 and the insulating film 116 have an opening that reaches the conductive film 112b. The conductive film 112c has a portion 152a and an opening 152b that reaches the conductive film 112c.

[0046] The oxide semiconductor film 108 includes an oxide semiconductor film 108b on the conductive film 104 side and an oxide and an oxide semiconductor film 108c on the oxide semiconductor film 108b. The oxide semiconductor film 8b and the oxide semiconductor film 108c are made of In and M (M is Al, Ga, Y, or It has Sn) and Zn.

[0047] For example, the oxide semiconductor film 108b may have a region in which the atomic ratio of In is larger than the atomic ratio of M. The oxide semiconductor film 108c preferably has a SiO 2 layer. It is preferable to have a region where the number of In atoms is smaller than that of b.

[0048] the oxide semiconductor film 108b has a region in which the atomic ratio of In is higher than the atomic ratio of M; This can increase the field effect mobility of the transistor 100. The field-effect mobility of the diode 100 is 10 cm 2 / Vs, more preferably The field effect mobility of Star 100 is 30 cm 2 / Vs can be exceeded.

[0049] For example, the above-mentioned high field effect mobility transistor is used as a gate driver for generating a gate signal. driver (especially, the demux connected to the output terminal of the shift register of the gate driver) By using it in a semiconductor device or display device with a narrow frame width (also called a narrow frame), Locations can be provided.

[0050] On the other hand, the oxide semiconductor film 108b has a region in which the atomic ratio of In is larger than the atomic ratio of M. In this case, the electrical characteristics of the transistor 100 are likely to fluctuate when irradiated with light. In the semiconductor device of one embodiment of the present invention, an oxide semiconductor film 108b is formed on the oxide semiconductor film 108c. The oxide semiconductor film 108c is thicker than the oxide semiconductor film 108b. Since the oxide semiconductor film 108 has a region with a low atomic ratio of In, Eg is larger than that of the oxide semiconductor film 108b. Therefore, the stacked structure of the oxide semiconductor film 108b and the oxide semiconductor film 108c The oxide semiconductor film 108 can improve resistance to a negative bias stress test using light. This becomes:

[0051] In addition, the oxide semiconductor film 108, particularly the channel region of the oxide semiconductor film 108b, Impurities such as hydrogen and moisture are problematic because they affect transistor characteristics. Therefore, in the channel region of the oxide semiconductor film 108b, hydrogen, moisture, and the like are present. The fewer the impurities, the better. The oxygen vacancies that occur are problematic because they affect transistor characteristics. When oxygen vacancies are formed in the channel region of the membrane 108b, hydrogen bonds to the oxygen vacancies, A carrier supply source is generated in the channel region of the oxide semiconductor film 108b. When the oxide semiconductor film 108b is formed, the electric characteristics of the transistor 100 including the oxide semiconductor film 108b are changed. Generally, a shift in the threshold voltage occurs. In the hole region, the fewer oxygen deficiencies the better.

[0052] In view of this, in one embodiment of the present invention, an insulating film in contact with the oxide semiconductor film 108, specifically The insulating films 114 and 116 formed above the oxide semiconductor film 108 contain excess oxygen. Oxygen or excess oxygen is introduced from the insulating films 114 and 116 to the oxide semiconductor film 108. By moving the oxygen atoms, oxygen vacancies in the oxide semiconductor film can be reduced.

[0053] In one embodiment of the present invention, the insulating films 114 and 116 contain excess oxygen. Specifically, the conductive film 120a is formed by stacking the conductive films 120a and 120b. and a metal film 120a_2 on the oxide conductive film 120a_1. The conductive film 120b is formed by an oxide conductive film 120b_1 and a metal film on the oxide conductive film 120b_1. and a film 120b_2.

[0054] With the above structure, for example, the oxide conductive film 120a_1 and the oxide conductive film 120 In the process of forming b_1, a sputtering method is used, and an oxygen gas is added in an atmosphere containing oxygen. By forming the oxide conductive film, oxygen or In addition, the metal film 120a_2 and the metal film 120b By having the insulating film 102, light emitted from above is irradiated onto the oxide semiconductor film 108. can be suppressed.

[0055] The conductive film 112c and the conductive film 120a are electrically connected using a metal film 120a_2. The conductive film 112b and the conductive film 120b are electrically connected using a metal film 120b_2. To be continued.

[0056] For example, when the conductive film 120a is formed of only the oxide conductive film 120a_1, In this configuration, the conductive film 120b_1 is connected to the conductive film 112c. The contact resistance between the conductive film 120a and the conductive film 12c may increase. In this case, the metal film 120a_2 is used to connect to the conductive film 112c. This makes it possible to reduce the connection resistance between the film 112c and the conductive film 120a.

[0057] Similarly, when the conductive film 120b is formed only from the oxide conductive film 120b_1, In this configuration, the conductive film 120b_1 is connected to the conductive film 112b. On the other hand, in one embodiment of the present invention, the connection resistance between the conductive film 12b and the conductive film 120b may increase. In this case, the metal film 120b_2 is used to connect to the conductive film 120b. This makes it possible to reduce the connection resistance between the film 112b and the conductive film 120b.

[0058] The metal film 120a_2 of the conductive film 120a and the metal film 120a_3 of the conductive film 120b are 120b_2 are formed by processing the same metal film. A metal film 120b_2 having the same composition as the metal film 120a_2 is formed on the substrate 120a_1.

[0059] An insulating film 118 is provided over the transistor 100. It is formed to cover the insulating film 116, the conductive film 120a, and the conductive film 120b.

[0060] In the transistor 100, the insulating films 106 and 107 are The insulating films 114 and 116 function as a first gate insulating film. The insulating film 118 functions as a second gate insulating film for protecting the transistor 100. In the transistor 100, the conductive film 104 functions as an insulating film. The conductive film 120a functions as a first gate electrode, and the conductive film 120b functions as a second gate electrode. The conductive film 120b functions as a pixel electrode used in a display device. In the transistor 100, the conductive film 112a functions as a source electrode. The gate electrode 112b functions as a drain electrode. The conductive film 112c functions as a connection electrode. The insulating films 114 and 116 are the second insulating film, and the insulating film 118 is the first insulating film. are sometimes referred to as the third insulating film.

[0061] The conductive film 112a is made up of a metal film 112a_1 and a metal film in contact with the metal film 112a_1. The metal film 112a_3 is in contact with the metal film 112a_2. In addition, the conductive film 120b is formed by a metal film 112b_1 and a metal film 112b_2 that is in contact with the metal film 112b_1. The metal film 112b_2 has a metal film 112b_3 on the metal film 112b_2.

[0062] The metal film 112a_2 and the metal film 112b_2 each contain copper. 1, the metal film 112b_1, the metal film 112a_3, and the metal film 112b_3 are each made of copper. The metal film 112a_1 includes a material that suppresses the diffusion of the metal film 112a_2. The metal film 112a_3 has a region located outside the end of the metal film 112a_2. The metal film 112a_1 covers the upper surface and the side surface and has a region in contact with the metal film 112a_1. The end of the metal film 2b_1 has a region located outside the end of the metal film 112b_2, The metal film 112b_3 covers the upper surface and side surfaces of the metal film 112b_2 and is connected to the metal film 112b_1. The end of the metal film 112c_1 is closer to the end of the metal film 112c_2 than the end of the metal film 112c_2. The metal film 112c_3 has an area located outside the upper surface of the metal film 112c_2 and It covers the side surface and has a region in contact with the metal film 112c_1.

[0063] By configuring the conductive films 112a and 112b as described above, wiring resistance can be reduced. In addition, the copper element contained in the conductive films 112a and 112b can be prevented from diffusing to the outside. Therefore, it is possible to provide a semiconductor device having stable electrical characteristics. can.

[0064] As shown in FIG. 1C, the conductive film 120a functioning as the second gate electrode is The conductive film 112c serving as a connection electrode is sandwiched between the first gate electrode and the second gate electrode. The conductive film 104 is electrically connected to the conductive film 104. Therefore, the conductive film 104 and the conductive film 120a are The same potential is applied.

[0065] As shown in FIG. 1C, the oxide semiconductor film 108 functions as a first gate electrode. and a conductive film 120a that functions as a second gate electrode. The conductive film 120 is positioned facing each other and is sandwiched between two films that function as gate electrodes. The length of the conductive film 120a in the channel length direction and the length of the conductive film 120a in the channel width direction are The length of the oxide semiconductor film 108 in the channel length direction and the length of the oxide semiconductor film 108 in the channel width direction The entire oxide semiconductor film 108 is conductive through the insulating films 114 and 116. It is covered with a conductive film 120a.

[0066] In other words, in the channel width direction of the transistor 100, The conductive film 104 functioning as the first gate electrode and the conductive film 120a functioning as the second gate electrode are The insulating films 106 and 107 function as gate insulating films, and the insulating film 108 function as a second gate insulating film. The oxide semiconductor film 108 is surrounded by insulating films 114 and 116 interposed therebetween.

[0067] With such a structure, the oxide semiconductor film 108 included in the transistor 100 The conductive film 104 functions as a first gate electrode and the conductive film 105 functions as a second gate electrode. The conductive film 120a can electrically surround the transistor 100. The electric field of the first gate electrode and the second gate electrode causes the oxide film to form a channel region. The device structure of the transistor that electrically surrounds the semiconductor film is called Surrounded c This can be called a channel (S-channel) structure.

[0068] Since the transistor 100 has an S-channel structure, the first gate electrode The conductive film 104 functions as a gate electrode, and the electric field for inducing the channel is effectively applied to the oxide semiconductor. This allows the voltage to be applied to the body film 108, improving the current driving capability of the transistor 100. It is possible to obtain high on-current characteristics. It is also possible to increase the on-current. Therefore, it is possible to miniaturize the transistor 100. The conductive film 104 functions as a first gate electrode and the conductive film 105 functions as a second gate electrode. Since the transistor 100 has a structure surrounded by the conductive film 120a, the mechanical strength of the transistor 100 is increased. It can be done.

[0069] As described above, in the semiconductor device according to one embodiment of the present invention, the second gate electrode The conductive film to be used as the second gate electrode is formed as a stacked structure of an oxide conductive film and a metal film. Oxygen is added to the surface of the conductive film that functions as a conductive film, and the metal film is used for connection to the connection electrode. By using this, the connection resistance can be reduced. A semiconductor device in which fluctuations are suppressed can be realized.

[0070] <1-2. Components of semiconductor device> The components included in the semiconductor device of this embodiment will be described in detail below.

[0071] [substrate] There is no particular restriction on the material of the substrate 102, but it should be strong enough to withstand the subsequent heat treatment. For example, glass substrates, ceramic substrates, quartz substrates, and A fire substrate or the like may be used as the substrate 102. Also, silicon or silicon carbide may be used as the material. Single crystal semiconductor substrates, polycrystalline semiconductor substrates, compound semiconductors such as silicon germanium, etc. It is also possible to apply a substrate, an SOI substrate, etc., and a semiconductor element is provided on these substrates. The substrate 102 may be a glass substrate. If you are using 6th generation (1500mm x 1850mm), 7th generation (1870mm x 220 0mm), 8th generation (2200mm x 2400mm), 9th generation (2400mm x 280 By using large area substrates such as 10th generation (2950mm x 3400mm), Larger display devices can be fabricated.

[0072] In addition, a flexible substrate is used as the substrate 102, and the transistor 10 is directly formed on the flexible substrate. Alternatively, a peeling layer may be provided between the substrate 102 and the transistor 100. The release layer is preferably removed from the substrate 102 after a semiconductor device is partially or completely completed thereon. The transistor 100 can be separated and transferred to another substrate. It can also be transferred to substrates with poor thermal properties or flexible substrates.

[0073] [Conductive film] The conductive film 104 functions as a first gate electrode, and the conductive film 11 functions as a source electrode. 2a, a conductive film 112b functioning as a drain electrode, and a conductive film 11 functioning as a connection electrode. 2c, a conductive film 120a functioning as a second gate electrode, and a conductive film 120b functioning as a pixel electrode. The conductive film 120b may be made of chromium (Cr), copper (Cu), aluminum (Al), or gold (Au ), silver (Ag), zinc (Zn), molybdenum (Mo), tantalum (Ta), titanium (Ti ), tungsten (W), manganese (Mn), nickel (Ni), iron (Fe), cobalt (Co), or an alloy containing the above-mentioned metal element as a component, or Each of these can be formed using an alloy or the like that combines metal elements.

[0074] In addition, the conductive films 104, 112a, 112b, 112c, 120a, and 120b are oxides containing tungsten and indium, oxides containing tungsten and indium, oxides containing titanium, indium, and zinc; oxides containing titanium and indium; oxides containing indium and tin, oxides containing indium and zinc, oxides containing silicon and indium, Oxides such as oxides containing indium and tin, oxides containing indium, gallium and zinc A material conductor may also be applied.

[0075] In particular, the oxide conductive film 120a_1 included in the conductive film 120a and the oxide conductive film 120a_2 included in the conductive film 120b are The oxide conductive film 120b_1 can be preferably made of the above-mentioned oxide conductor. In addition, the oxide conductive films 120a_1 and 120b_1 and the oxide semiconductor film 108 (oxide semiconductor The oxide semiconductor film 108b and the oxide semiconductor film 108c preferably contain the same metal element. By adopting this configuration, it is possible to reduce manufacturing costs.

[0076] Here, the oxide conductor will be described. In this specification and the like, the oxide conductor is referred to as OC (Oxide Conductor). Examples of oxide conductors include When oxygen vacancies are formed in an oxide semiconductor and hydrogen is added to the oxygen vacancies, donors are formed in the vicinity of the conduction band. As a result, the oxide semiconductor becomes electrically conductive. The oxide semiconductor thus obtained can be called an oxide conductor. , and has a large energy gap, so it is transparent to visible light. The oxide conductor is an oxide semiconductor having a donor level near the conduction band. The effect of absorption due to donor levels is small, and the transparency to visible light is comparable to that of oxide semiconductors. It has sexuality.

[0077] The conductive films 104, 112a, 112b, 112c, 120a, and 120b are made of Cu. -X alloy film (X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti) is applied. By using a Cu-X alloy film, it can be processed by a wet etching process. Therefore, it is possible to reduce manufacturing costs.

[0078] In particular, the metal film 112a_2 of the conductive film 112a and the metal film 112a_1 of the conductive film 112b are The conductive film 112c includes a metal film 112b_2 and a metal film 112c_2 of the conductive film 112c. As the Cu-X alloy film, a Cu-Mn alloy film is particularly preferable. However, in one embodiment of the present invention, the present invention is not limited to this, and the metal film 112b_2 and the metal The metal film 112c_2 only needs to contain at least copper.

[0079] In addition, the metal films 112a_1 and 112a_3 and the conductive film 112b_ The metal films 112b_1 and 112b_3 included in the conductive film 112c and the metal film 112 Among the above metal elements, C_1 and C_3 contain titanium, tungsten, and tungsten. It is preferable that the alloy contains one or more selected from the group consisting of aluminum, tungsten, and molybdenum. Metal film 112a_1, 112a_3, 112b_1, 112b_3, 112c_1, 11 2c_3 is any one selected from titanium, tungsten, tantalum, and molybdenum; When one or more of the metal films 112a_2 and 112b_2 are provided, the copper in the metal films 112a_2 and 112b_2 can be diffused outward. That is, the metal films 112a_1, 112a_3, 112b_ 1, 112b_3, 112c_1, and 112c_3 function as a barrier metal. do.

[0080] Metal films 112a_1, 112a_3, metal films 112b_1, 112b_3, and 112 For c_1 and 112c_3, it is preferable to use a so-called tantalum nitride film containing nitrogen and tantalum. The tantalum nitride film has electrical conductivity and high barrier properties against copper or hydrogen. Furthermore, tantalum nitride film releases less hydrogen from itself, so it is As a metal film in contact with the oxide semiconductor film 108 or a metal film in the vicinity of the oxide semiconductor film 108 can be most preferably used.

[0081] The metal films 112a_3 and 112b_3 are made of titanium, tungsten, tantalum, and molybdenum. By using a structure having one or more selected from among ribdenum, the metal film 1 The connection resistance between the metal film 120a and the metal film 120b can be reduced. _2, 120b_2 are made of the same material as the metal films 112a_3, 112b_3, This is preferable because the resistance can be further reduced.

[0082] [Insulating film functioning as first gate insulating film] The insulating films 106 and 107 functioning as the first gate insulating film of the transistor 100 are Plasma Enhanced Chemical Vapor Deposition (PECVD) Oxidation is performed by the ical vapor deposition method, sputtering method, etc. Silicon film, silicon oxynitride film, silicon nitride oxide film, silicon nitride film, aluminum oxide hafnium oxide film, yttrium oxide film, zirconium oxide film, gallium oxide film , tantalum oxide film, magnesium oxide film, lanthanum oxide film, cerium oxide film and ne oxide film The insulating film 106 and the insulating film 107 may be formed of an oxynitride film or an oxynitride film. Instead of the laminated structure of 107, a single insulating film selected from the above materials or three or more layers An insulating film may also be used.

[0083] The insulating film 106 also functions as a blocking film that suppresses oxygen permeation. For example, the insulating films 107, 114, and 116 and / or the oxide semiconductor film 108 may contain excess acid. When oxygen is supplied, the insulating film 106 can suppress oxygen permeation.

[0084] Note that the oxide semiconductor film 108, which functions as a channel region of the transistor 100, is in contact with the oxide semiconductor film 108. The insulating film 107 is preferably an oxide insulating film, and the oxide content is in excess of the stoichiometric composition. It is more preferable that the insulating film 1 has a region containing oxygen (an oxygen-excess region). The insulating film 107 is an insulating film capable of releasing oxygen. To provide the insulating film 107, for example, the insulating film 107 may be formed in an oxygen atmosphere. The insulating film 107 is then heat-treated in an oxygen atmosphere.

[0085] Furthermore, when hafnium oxide is used as the insulating film 107, the following effects are achieved. Hafnium has a higher dielectric constant than silicon oxide and silicon oxynitride. Compared to the case where silicon oxide is used, the thickness of the insulating film 107 can be made larger, so that the tunnel This reduces the leakage current due to the current flowing through the transistor. Furthermore, hafnium oxide, which has a crystalline structure, can be used to form amorphous structures. Therefore, the off-state current is small. To form a transistor, it is preferable to use hafnium oxide having a crystalline structure. Examples of the crystal structure include monoclinic and cubic crystals. The types are not limited to these.

[0086] In this embodiment, a silicon nitride film is formed as the insulating film 106, and the insulating film 107 The silicon nitride film has a lower dielectric constant than the silicon oxide film. The film thickness required to obtain the same capacitance as a silicon oxide film is large, so The gate insulating film of the transistor 100 can be made thick by including a silicon nitride film. Therefore, the decrease in the dielectric strength voltage of the transistor 100 can be suppressed, and further, the dielectric strength voltage can be increased. This can improve the resistance of the transistor 100 and suppress electrostatic breakdown of the transistor 100.

[0087] [Oxide semiconductor film] The oxide semiconductor film 108 can be formed using the above-described materials.

[0088] When the oxide semiconductor film 108b is an In-M-Zn oxide, the In-M-Zn oxide is deposited. The atomic ratio of the metal elements in the sputtering target used for this purpose satisfies In>M. It is preferable that the atomic ratio of the metal elements in such a sputtering target is I n:M:Zn=2:1:3, In:M:Zn=3:1:2, In:M:Zn=4:2:4 .1 etc.

[0089] In addition, when the oxide semiconductor film 108c is an In-M-Zn oxide, The atomic ratio of the metal elements in the sputtering target used to form the film is In≦M. It is preferable that the atomic ratio of the metal elements in such a sputtering target is In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn= 1:3:2, In:M:Zn=1:3:4, In:M:Zn=1:3:6, etc. do.

[0090] The oxide semiconductor film 108b and the oxide semiconductor film 108c are each an In-MZ In the case of n-oxides, polycrystalline In-M-Zn oxides are used as sputtering targets. It is preferable to use a target containing polycrystalline In-M-Zn oxide. By using the oxide semiconductor film 108b, the oxide semiconductor film 108c having crystallinity can be formed. Note that the oxide semiconductor film 108b and the oxide semiconductor film 108c are easily formed. The atomic ratios of the metal elements contained in the sputtering target are For example, the sputtering of the oxide semiconductor film 108b When the atomic ratio of In:Ga:Zn=4:2:4.1 is used as the target, the film formation The atomic ratio of the oxide semiconductor film 108b is approximately In:Ga:Zn=4:2:3. There are cases where this happens.

[0091] The oxide semiconductor film 108 has an energy gap of 2 eV or more, preferably 2.5 eV or more. eV or more, more preferably 3 eV or more. By using a nitride semiconductor, the off-state current of the transistor 100 can be reduced. The oxide semiconductor film 108b has an energy gap of 2 eV or more, preferably 2 eV or more. The oxide semiconductor film 108c has an energy It is preferable to use an oxide semiconductor film having a gap of 2.5 eV or more and 3.5 eV or less. In addition, the energy gap of the oxide semiconductor film 108c is larger than that of the oxide semiconductor film 108b. It is preferable to do so.

[0092] The oxide semiconductor film 108b and the oxide semiconductor film 108c each have a thickness of 3n m or more and 200 nm or less, preferably 3 nm or more and 100 nm or less, and more preferably 3 nm or more and 200 nm or less. The thickness is set to 50 nm or more.

[0093] The oxide semiconductor film 108c is an oxide semiconductor film with low carrier density. For example, the second oxide semiconductor film 108c has a carrier density of 1×10 17 cm -3 below , preferably 1 x 10 15 cm -3 or less, more preferably 1 × 10 13 cm -3 below, More preferably 1×10 11 cm -3 The following applies.

[0094] However, the semiconductor characteristics and electrical characteristics (field effect) of the required transistors are not limited to these. It is sufficient to use an appropriate composition depending on the required properties (e.g., the mobility, threshold voltage, etc.). In order to obtain semiconductor characteristics of the transistor, the oxide semiconductor film 108b and the oxide semiconductor The carrier density, impurity concentration, defect density, atomic ratio of metal elements to oxygen, interatomic ratio, It is preferable to set the distance, density, etc. appropriately.

[0095] Note that the oxide semiconductor films 108b and 108c each contain impurities. By using an oxide semiconductor film with a low concentration of impurities and a low density of defect states, it is possible to obtain even better electrical properties. In this case, the impurity concentration is low, and A low density of defect levels (low oxygen vacancies) is called high purity intrinsic or substantially high purity intrinsic. A highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a carrier generation source. Therefore, the carrier density can be reduced. The transistor in which the hole region is formed has electrical characteristics in which the threshold voltage is negative (normal It is also called "on." It is rare for it to become a high-purity intrinsic or substantially high-purity intrinsic In some oxide semiconductor films, the density of defect states is low, and therefore the density of trap states may also be low. Furthermore, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a significantly low off-state current. The channel width is 1×10 6 Even if the element has a channel length L of 10 μm, When the voltage between the source electrode and the drain electrode (drain voltage) is in the range of 1V to 10V, The off-state current is below the measurement limit of the semiconductor parameter analyzer, i.e., 1×10 -13 After A The following characteristics can be obtained.

[0096] Therefore, the high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor film is provided with a channel. The transistors in which the regions are formed have small fluctuations in electrical characteristics and are highly reliable. Note that charges trapped in the trap states of the oxide semiconductor film are lost. It takes a long time for the charge to dissipate, and it can behave as if it were a fixed charge. A transistor in which a channel region is formed in an oxide semiconductor film with a high density of trap states has Impurities include hydrogen, nitrogen, alkali metals, or Alkaline earth metals, etc.

[0097] The hydrogen contained in the oxide semiconductor film reacts with oxygen that is bonded to metal atoms to form water. The oxygen vacancies are formed in the lattice from which oxygen is desorbed (or in the portions from which oxygen is desorbed). When hydrogen enters the electron carrier, it can generate electrons. It can bond with oxygen, which bonds with metal atoms, to generate electrons, which are carriers. A transistor using an oxide semiconductor film containing hydrogen has normally-on characteristics. Therefore, it is preferable that the amount of hydrogen in the oxide semiconductor film 108 be reduced as much as possible. Specifically, the hydrogen concentration in the oxide semiconductor film 108 obtained by SIMS analysis is degrees, 2 x 10 20 atoms / cm 3 Less than or equal to 5 x 10 19 atoms / cm 3 Less than 1×10, more preferably 19 atoms / cm 3 Below, 5 x 10 18 atoms / cm 3 Less than 1 × 10 18 atoms / cm 3 Less than or equal to 5x1, more preferably 0 17 atoms / cm 3 or less, more preferably 1 × 10 16 atoms / cm 3 below Let's say.

[0098] The oxide semiconductor film 108b has a region with a lower hydrogen concentration than the oxide semiconductor film 108c. The oxide semiconductor film 108b preferably has a region where the oxide semiconductor film 108c has a larger thickness than the oxide semiconductor film 108b. By having a region with a low hydrogen concentration, a highly reliable semiconductor device can be obtained.

[0099] In addition, silicon and carbon, which are Group 14 elements, are contained in the oxide semiconductor film 108b. If the oxide semiconductor film 108b contains oxygen, oxygen vacancies increase in the oxide semiconductor film 108b, causing the oxide semiconductor film 108b to become n-type. Therefore, the concentrations of silicon and carbon in the oxide semiconductor film 108b and the oxide semiconductor film 10 The concentration of silicon and carbon near the interface with 8b (concentration obtained by SIMS analysis) is 2× 10 18 atoms / cm 3 Less than or equal to 2 x 10 17 atoms / cm 3The following do.

[0100] In addition, in the oxide semiconductor film 108b, the alkali metal or or alkaline earth metal concentration is 1×10 18 atoms / cm 3 Below, preferably 2x 10 16 atoms / cm 3 The alkali metals and alkaline earth metals are oxides. When bonded to a semiconductor, carriers may be generated, increasing the off-state current of the transistor. For this reason, the alkali metal or alkaline earth metal in the oxide semiconductor film 108b is It is preferable to reduce the concentration of metalloids.

[0101] When nitrogen is contained in the oxide semiconductor film 108b, electrons serving as carriers are generated. The carrier density increases and the oxide semiconductor film containing nitrogen is easily converted to n-type. A transistor using the oxide semiconductor film tends to be normally on. In the present invention, it is preferable that the nitrogen content is reduced as much as possible. For example, it is possible to determine by SIMS analysis that the nitrogen content is reduced as much as possible. The resulting nitrogen concentration is 5 x 10 18 atoms / cm 3 It is preferable to do the following:

[0102] The oxide semiconductor film 108b and the oxide semiconductor film 108c each have a non-single-crystal structure. The non-single crystal structure may be, for example, a CAAC-OS (C Axis Aliphatic Crystal) structure, which will be described later. gned Crystalline Oxide Semiconductor), polyconductor The non-single crystalline structure includes a crystalline structure, a microcrystalline structure, or an amorphous structure. The defect density of CAAC-OS is the lowest.

[0103] [Insulating film functioning as second gate insulating film] The insulating films 114 and 116 function as a second gate insulating film of the transistor 100 . The insulating films 114 and 116 have a function of supplying oxygen to the oxide semiconductor film 108 . That is, the insulating films 114 and 116 contain oxygen. The insulating film 114 is an insulating film that can form an insulating film 116 to be formed later. The oxide semiconductor film 108 also functions as a film for reducing damage to the oxide semiconductor film 108 during the formation of the oxide semiconductor film 108.

[0104] The insulating film 114 has a thickness of 5 nm to 150 nm, preferably 5 nm to 50 Silicon oxide, silicon oxynitride, etc., having a thickness of 1 nm or less can be used.

[0105] Furthermore, it is preferable that the insulating film 114 has a small number of defects. The spin density of the signal at g=2.001 originating from the silicon dangling bond is 3 x 10 17 spins / cm 3 This is because the insulating film 114 is preferably If the density of defects contained is high, oxygen will be bonded to the defects, and the oxygen in the insulating film 114 will The amount of transmission of light decreases.

[0106] In the insulating film 114, all the oxygen that has entered the insulating film 114 from the outside is Some oxygen does not move to the outside of the insulating film 114 and remains in the insulating film 114. At the same time, oxygen contained in the insulating film 114 moves to the outside of the insulating film 114, Oxygen may move in the film 114. When the oxide insulating film capable of forming the insulating film 114 is formed, the insulating film 116 and the insulating film 116 are formed on the insulating film 114. The desorbed oxygen can be transferred to the oxide semiconductor film 108 through the insulating film 114. .

[0107] The insulating film 114 is formed using an oxide insulating film with a low density of states due to nitrogen oxides. Note that the density of states due to the nitrogen oxide can be determined by the valence Energy of the top of the electronic band (Ev_os) and energy of the bottom of the conduction band of the oxide semiconductor film The oxide insulating film may be formed between the gate electrode and the gate electrode of the nitride semiconductor layer. Silicon oxynitride film with low emission or aluminum oxynitride film with low nitrogen oxide emission For example, a silicon film or the like can be used.

[0108] In addition, a silicon oxynitride film that emits a small amount of nitrogen oxides can be analyzed by thermal desorption spectroscopy. This membrane releases more ammonia than nitrogen oxides, and typically releases ammonia. The amount of emission is 1×10 18 molecule / cm 3 5x10 or more 19 molecule / cm 3 The following is the case. The amount of ammonia released is controlled when the surface temperature of the membrane is 50°C or higher and 650°C or lower, preferably 50°C or higher. The amount released by heat treatment at 550°C or less.

[0109] Nitrogen oxides (NO x , x is more than 0 and not more than 2, preferably 1 or more and not more than 2), typically NO or NO forms a level in the insulating film 114 or the like. Therefore, the nitrogen oxide is located in the energy gap of the insulating film 114 and When the oxide semiconductor film 108 diffuses to the interface, the level attracts electrons on the insulating film 114 side. As a result, the trapped electrons may be trapped in the insulating film 114 and the oxide semiconductor. Since the electrons remain near the interface of the semiconductor film 108, the threshold voltage of the transistor is shifted in the positive direction. It makes me feel unwell.

[0110] Nitrogen oxide reacts with ammonia and oxygen during heat treatment. The nitrogen oxide contained in the insulating film 116 reacts with the ammonia contained in the insulating film 116 during the heat treatment. Therefore, the nitrogen oxide contained in the insulating film 114 is reduced. Electrons are less likely to be trapped at the interface between the oxide semiconductor film 106 and the oxide semiconductor film 108.

[0111] By using the oxide insulating film as the insulating film 114, the threshold voltage of the transistor can be reduced. It is possible to reduce the shift in the electrical characteristics of the transistor. can.

[0112] Note that the heat treatment in the manufacturing process of a transistor is typically performed at a temperature of 300° C. or higher and lower than 350° C. By the heat treatment, the insulating film 114 shows the following characteristics in the spectrum obtained by ESR measurement at 100K or less. The first signal has a g value of 2.037 or more and 2.039 or less, and the second signal has a g value of 2.001 or more. A second signal less than .003 and a third signal with a g value between 1.964 and 1.966. The split width of the first signal and the second signal, and the The split width of the second signal and the third signal is about 5 in the X-band ESR measurement. mT. The first signal has a g value of 2.037 or more and 2.039 or less, and the g value is 2. A second signal between 0.001 and 2.003, and a g value between 1.964 and 1.966 The total spin density of the third signal is 1×10 18spins / cm 3 Less than Typically, it is 1×10 17 spins / cm 3 More than 1×10 18 spins / cm 3 Not yet It is full.

[0113] In the ESR spectrum below 100K, the g value is between 2.037 and 2.039. The first signal below, the second signal with a g-value between 2.001 and 2.003, and the g-value The sum of the spin densities of the third signal, where is between 1.964 and 1.966, is the nitrogen oxide Monster (NO x x is greater than 0 and less than or equal to 2, preferably greater than or equal to 1 and less than or equal to 2) Typical examples of nitrogen oxides include nitrogen monoxide and nitrogen dioxide. First signal between 2.037 and 2.039, g between 2.001 and 2.003 and the third signal with a g value of 1.964 or more and 1.966 or less. The lower the total density of pins, the lower the nitrogen oxide content in the oxide insulating film. Yes.

[0114] The oxide insulating film has a nitrogen concentration of 6×10 as measured by SIMS. 20 atoms / cm 3 The following is the result.

[0115] The substrate temperature is between 220℃ and 350℃, and PEC using silane and nitrous oxide is used. By forming the oxide insulating film using a VD method, a dense and hard film can be obtained. It can be formed.

[0116] The insulating film 116 is an oxide insulating film containing more oxygen than the oxygen required for the stoichiometric composition. The oxide insulating film containing more oxygen than the oxygen that satisfies the stoichiometric composition is formed using When heated, some of the oxygen is released. The oxygen content is greater than the stoichiometric ratio. The oxide insulating film had a desorption of 1.0 x 10 oxygen atoms in TDS analysis. 1 9 atoms / cm 3 or more, preferably 3.0 × 10 20 atoms / cm 3 That's all The surface temperature of the film in the above TDS is 100°C or higher and 70°C or lower. A temperature of 0°C or lower, or a temperature in the range of 100°C to 500°C is preferred.

[0117] The insulating film 116 has a thickness of 30 nm to 500 nm, preferably 50 nm or more. Silicon oxide, silicon oxynitride, etc., of 400 nm or less can be used.

[0118] Furthermore, it is preferable that the insulating film 116 has a small number of defects. The spin density of the signal at g=2.001 originating from the silicon dangling bond is 1.5 x 10 18 spins / cm 3 Less than, or even 1×10 18 spins / cm 3 It is preferable that the insulating film 116 has a higher oxide semiconductor content than the insulating film 114. Since it is separated from the insulating film 108, it may have a higher defect density than the insulating film 114.

[0119] In addition, the insulating films 114 and 116 can be made of the same material, so that the insulating film In some cases, the interface between the film 114 and the insulating film 116 cannot be clearly identified. In this embodiment, the interface between the insulating film 114 and the insulating film 116 is shown by a broken line. In the embodiment, the two-layer structure of the insulating film 114 and the insulating film 116 has been described. However, the present invention is not limited to this, and may be applied to, for example, a single layer structure of the insulating film 114 or a laminated structure of three or more layers. Good too.

[0120] [Insulating film functioning as a protective insulating film] The insulating film 118 functions as a protective insulating film for the transistor 100.

[0121] The insulating film 118 contains either hydrogen or nitrogen, or both. The insulating film 118 contains nitrogen and silicon. The insulating film 118 contains oxygen, hydrogen, water, and alkali. The insulating film 118 has a function of blocking metals, alkaline earth metals, etc. As a result, oxygen diffuses from the oxide semiconductor film 108 to the outside, and oxygen contained in the insulating films 114 and 116 is The diffusion of oxygen from the oxide semiconductor film 108 to the outside and the penetration of hydrogen, water, and the like from the outside into the oxide semiconductor film 108 are prevented. It can be prevented.

[0122] The insulating film 118 may be, for example, a nitride insulating film. Examples include silicon nitride, silicon nitride oxide, aluminum nitride, and aluminum nitride oxide. etc.

[0123] The various films described above, such as the conductive film, insulating film, oxide semiconductor film, and metal film, can be formed by sputtering. It can be formed by a quartz deposition method or a PECVD method, but other methods, such as thermal CV It may also be formed by a Chemical Vapor Deposition (D) method. As an example of thermal CVD, MOCVD (Metal Organic Chemical Vapor Deposition) Sporadic Deposition (SPD) method or Atomic Layer Deposition (ALD) method Examples include the (position) method.

[0124] The thermal CVD method is a film formation method that does not use plasma, so defects can occur due to plasma damage. This has the advantage that no further processing is required.

[0125] In the thermal CVD method, the source gas and oxidant are simultaneously fed into a chamber, and the chamber is heated to atmospheric pressure. Alternatively, a film is formed by reacting the material near or on the substrate under reduced pressure and depositing the material on the substrate. You may go.

[0126] In addition, in the ALD method, the pressure inside the chamber is atmospheric or reduced, and the source gas for the reaction is The gases may be introduced into the chamber in sequence, and the film may be formed by repeating this gas introduction sequence.

[0127] Thermal CVD methods such as MOCVD and ALD can be used to form conductive films, insulating films, and oxides in the above-described embodiments. It can form various films such as semiconductor films and metal oxide films. For example, In-Ga-Zn When forming an O film, trimethylindium, trimethylgallium, and dimethylzinc are used. Lead is used. The chemical formula for trimethylindium is In(CH3)3. The chemical formula for trimethylgallium is Ga(CH3)3. The chemical formula for dimethylzinc is The compound is Zn(CH3)2. The compound is not limited to these combinations, and may be trimethylgalactose. Triethylgallium (chemical formula Ga(C2H5)3) can be used instead of diethylgallium. Diethylzinc (chemical formula Zn(C2H5)2) can also be used instead of methylzinc.

[0128] For example, when forming a hafnium oxide film using a film forming apparatus that uses ALD, the solvent and liquids containing hafnium precursor compounds (hafnium alkoxides, tetrakisdimethyl The raw material gas is vaporized hafnium amide (such as TDMAH) and acid Two types of gases are used: tetrakisdimethylamide (TDMA) and ozone (O3) as a chlorine gas. The chemical formula for Hf is Hf[N(CH3)2]4. Other materials include tetrahydrofuran, Examples include rakis(ethylmethylamido) hafnium.

[0129] For example, when forming an aluminum oxide film using an ALD film forming device, A liquid containing a catalyst and an aluminum precursor compound (e.g., trimethylaluminum (TMA)) is added. Two types of gases are used: vaporized source gas and H2O as an oxidizing agent. The chemical formula for aluminum is Al(CH3)3. Other liquid materials include Tris( dimethylamido)aluminum, triisobutylaluminum, aluminum tris(2 ,2,6,6-tetramethyl-3,5-heptanedionate).

[0130] For example, when forming a silicon oxide film using a film forming device that uses ALD, Chlorodisilane is adsorbed onto the surface to be coated, removing the chlorine contained in the adsorbed material, and the oxidizing gas (O 2. Nitrous oxide (NO) radicals are supplied to react with the adsorbed material.

[0131] For example, when forming a tungsten film using an ALD deposition system, WF6 The initial tungsten film was formed by sequentially introducing BH gas and BH gas. The tungsten film is formed using B2H6 gas and H2 gas. iH4 gas may also be used.

[0132] For example, an oxide semiconductor film, such as In-Ga-ZnO, can be formed using a film formation device that uses ALD. When forming a film, In(CH3)3 gas and O3 gas are introduced in sequence and repeatedly to form an In- An O layer is formed, and then a GaO layer is formed using Ga(CH3)3 gas and O3 gas. After that, a ZnO layer is formed using Zn(CH3)2 gas and O3 gas. The order of these layers is not limited to this example. In addition, by mixing these gases, an In-Ga-O layer or an In It is also possible to form a mixed compound layer such as a Zn-O layer or a Ga-Zn-O layer. Instead of this, HO gas obtained by bubbling with an inert gas such as Ar may be used. It is preferable to use O3 gas that does not contain In. (C2H5)3 gas may be used. Also, instead of Ga(CH3)3 gas, Ga(C2 H5)3 gas may be used, or Zn(CH3)2 gas may be used.

[0133] <1-3. Configuration example 2 of semiconductor device> Next, modifications of the transistor 100 shown in FIGS. 1A, 1B, and 1C will be described with reference to FIGS. This will be explained using Figure 6.

[0134] 2A and 2B show a transistor which is a modification of the transistor 100 shown in FIGS. 1B and 1C. 3A and 3B are cross-sectional views of the transistor 100A. 4(B) is a cross-sectional view of a transistor 100B, which is a modification of the transistor 100. A) and (B) are transistors that are modifications of the transistor 100 shown in FIGS. 1(B) and 1(C). 5(A) and (B) are cross-sectional views of the transistor 100C shown in FIG. 1(B) and (C). 6(A) and 6(B) are cross-sectional views of a transistor 100D, which is a modified example of the transistor 100. ) is a transistor 100E, which is a modification of the transistor 100 shown in FIGS. FIG.

[0135] The transistor 100A shown in FIGS. 2A and 2B is a transistor having a structure similar to that shown in FIGS. The oxide semiconductor film 108 included in the capacitor 100 has a three-layer structure. The oxide semiconductor film 108 included in the transistor 100A includes an oxide semiconductor film 108a and an oxide semiconductor film 108b. The oxide semiconductor film 108b on the oxide semiconductor film 108a and the oxide semiconductor film 108b and a compound semiconductor film 108c.

[0136] The transistor 100B shown in FIGS. 3A and 3B is a transistor having a structure similar to that shown in FIGS. The oxide semiconductor film 108 of the transistor 100 has a single-layer structure. The transistor 100B includes an oxide semiconductor film 108b.

[0137] The transistor 100C shown in FIGS. 4A and 4B is a transistor having a structure similar to that shown in FIGS. The shape of the oxide semiconductor film 108 in the transistor 100 is different. In the drawing, the oxide semiconductor film 108c included in the semiconductor device 100 is separated from the conductive films 112a and 112b. In other words, the thickness of the exposed region is small. On the other hand, the oxide semiconductor film 108c included in the transistor 100C is In the drawing, the thickness of the regions exposed from the conductive films 112a and 112b is not reduced. As a result, a part of the oxide semiconductor film does not have a recess.

[0138] The transistor 100D shown in FIGS. 5A and 5B is a transistor having a structure similar to that shown in FIGS. The structures of the conductive films 112a, 112b, and 112c of the capacitor 100 are different. The conductive films 112a, 112b, and 112c of the transistor 100D have a single-layer structure. be.

[0139] The transistor 100E shown in FIGS. 6A and 6B is a so-called channel protection type transistor. An insulating film 115 functioning as a channel protective film is provided over the oxide semiconductor film 108. The insulating film 115 can be formed using the same material as the insulating film 114. In the case where the insulating film 115 is provided, the insulating film 114 is not provided, and the conductive films 112a and 11 2b, an insulating film 116 may be provided on the insulating film 115.

[0140] As described above, the semiconductor device of the present invention includes a stacked structure of oxide semiconductor films, an oxide semiconductor It is possible to apply the present invention even if the shape of the film or the laminated structure of the conductive film is different. The transistor according to this embodiment can be freely combined with each of the above structures. is possible.

[0141] <1-4. Manufacturing method of semiconductor device> Next, a method for manufacturing the transistor 100, which is a semiconductor device of one embodiment of the present invention, will be described with reference to FIGS. 7 to 12.

[0142] 7(A) to 7(C), 8(A) to 8(C), 9(A) to 9(C), C), Figs. 10(A) to 10(C), Figs. 11(A) to 11(C), and Fig. 12 are 7A to 7C and 8 are cross-sectional views illustrating a method for manufacturing a semiconductor device. (A) to (C), Fig. 9(A) to (C), Fig. 10(A) to (C), Fig. 11(A) to 11(C) and 12, the left side is a cross-sectional view in the channel length direction. The right side is a cross-sectional view in the channel width direction.

[0143] First, a conductive film is formed on the substrate 102, and the conductive film is then subjected to a lithography process and an etching process. Then, a conductive film 104 is formed, which functions as a first gate electrode. On the conductive film 104, insulating films 106 and 107 are formed to function as a first gate insulating film (see FIG. 7(A)).

[0144] In this embodiment, a glass substrate is used as the substrate 102, and a gate electrode is formed on the substrate 102. The conductive film 104 is made of a titanium film having a thickness of 50 nm and a copper film having a thickness of 200 nm. The insulating film 106 is formed by a nitride film having a thickness of 400 nm. A silicon film is formed by the PECVD method, and a silicon oxide nitride film having a thickness of 50 nm is formed as the insulating film 107. The silicon film is formed by PECVD.

[0145] The insulating film 106 may have a stacked structure of silicon nitride films. The insulating film 106 is made of a first silicon nitride film, a second silicon nitride film, and a third silicon nitride film. A three-layer laminated structure with a silicon film can be formed. An example of the three-layer laminated structure is as follows: It can be formed as follows.

[0146] The first silicon nitride film is formed by, for example, silane at a flow rate of 200 sccm, PE-CV was performed using nitrogen at a flow rate of 100 sccm and ammonia gas at a flow rate of 100 sccm as source gases. The pressure in the reaction chamber was controlled to 100 Pa, and a 27.12 MHz high frequency was generated. If a power of 2000 W is supplied using a frequency power supply and the thickness is formed to be 50 nm, good.

[0147] For the second silicon nitride film, silane at a flow rate of 200 sccm and 2000 sccm The PECVD equipment was operated using nitrogen at a flow rate of 2000 sccm and ammonia gas at a flow rate of 2000 sccm as raw material gases. The pressure in the reaction chamber was controlled to 100 Pa, and a 27.12 MHz high frequency power supply A power of 2000 W may be supplied using a heater to form the film to a thickness of 300 nm.

[0148] The third silicon nitride film was formed using silane at a flow rate of 200 sccm and silane at a flow rate of 5000 sccm. The pressure in the reaction chamber was adjusted to 100 The thickness was measured by controlling the temperature to 50 Pa and supplying 2000 W of power using a 27.12 MHz high frequency power supply. It is sufficient to form it so that the thickness is 50 nm.

[0149] The first silicon nitride film, the second silicon nitride film, and the third silicon nitride film The substrate temperature during the formation can be 350° C. or less.

[0150] By forming the insulating film 106 as a three-layered structure of silicon nitride films, for example, the conductive film 10 When a conductive film containing copper is used for 4, the following effects are achieved.

[0151] The first silicon nitride film can suppress the diffusion of copper elements from the conductive film 104. The second silicon nitride film has a function of releasing hydrogen and acts as an insulating film that functions as a gate insulating film. The third silicon nitride film can improve the breakdown voltage of the film. The hydrogen released from the second silicon nitride film is small, and the diffusion of the hydrogen released from the second silicon nitride film is suppressed. It is possible.

[0152] The insulating film 107 is formed by a method using an oxide semiconductor film 108 (more specifically, an oxide In order to improve the interface characteristics with the oxide semiconductor film 108b), the insulating film is formed of an oxygen-containing insulating film. After the insulating film 107 is formed, oxygen may be added to the insulating film 107. The oxygen to be added to the film 107 may be oxygen radicals, oxygen atoms, oxygen atomic ions, or oxygen molecules. The methods of addition include ion doping, ion implantation, and plasma There are methods such as ma processing.

[0153] Next, an oxide semiconductor film 108b_0 and an oxide semiconductor film 108c_0 are formed over the insulating film 107. (See Figures 7(B) and (C)).

[0154] Note that FIG. 7B shows a process for forming the oxide semiconductor film 108b_0 over the insulating film 107. FIG. 7(B) is a cross-sectional view of the inside of the film forming device. The target 191 is installed inside the sputtering device. 1 and a plasma 192 formed below the plasma 192 are shown schematically.

[0155] First, when the oxide semiconductor film 108b_0 is formed, a plasma is generated in an atmosphere containing oxygen gas. At this time, the insulating film 107, which is the surface on which the oxide semiconductor film 108b_0 is to be formed, is When the oxide semiconductor film 108b_0 is formed, oxygen is added to the oxide semiconductor film 108b_0. In addition, inert gases (e.g., helium gas, argon gas, xenon gas, etc.) are mixed. It is also acceptable to do so.

[0156] The oxygen gas contained in the oxide semiconductor film 108b_0 is The ratio of oxygen gas to the total deposition gas when the oxide semiconductor film 108b_0 is formed may be The ratio is more than 0% and not more than 100%, preferably 10% or more and not more than 100%, and more preferably 10% or more and not more than 100%. Preferably, it is 30% or more and 100% or less.

[0157] In FIG. 7B, oxygen or excess oxygen added to the insulating film 107 is schematically shown. It is indicated by a dashed arrow.

[0158] Note that the substrate temperature during the formation of the oxide semiconductor film 108b_0 and the oxide semiconductor film 108c_0 was However, the thickness of the oxide semiconductor film 108b_0 and the thickness of the oxide semiconductor film 108b_1 may be the same or different. By making the substrate temperature the same as that of the conductive film 108c_0, the manufacturing cost can be reduced. This is preferable because it can be

[0159] For example, the substrate temperature when the oxide semiconductor film 108 is formed is set to a temperature higher than room temperature and lower than 340° C. Preferably, the temperature is from room temperature to 300°C, more preferably from 100°C to 250°C. The temperature is preferably 100° C. or higher and 200° C. or lower. By doing so, the crystallinity of the oxide semiconductor film 108 can be improved. Therefore, when using a large glass substrate (for example, 6th to 10th generations), oxide semiconductor When the substrate temperature during the deposition of the solid film 108 is set to 150° C. or higher and lower than 340° C., the substrate 102 Therefore, when using a large glass substrate, In this case, the substrate temperature during the formation of the oxide semiconductor film 108 is set to 100° C. or higher and lower than 150° C. By doing so, deformation of the glass substrate can be suppressed.

[0160] In addition, the sputtering gas must be highly purified. The oxygen gas and argon gas used in this process have a dew point of -40°C or less, preferably -80°C or less, and Preferably, the gas is purified to a temperature of -100°C or lower, more preferably -120°C or lower. By using the oxide semiconductor film, it is possible to prevent moisture and the like from being taken into the oxide semiconductor film as much as possible. .

[0161] In addition, when the oxide semiconductor film is formed by sputtering, The chamber is cladded to remove as much water as possible, which is an impurity for the oxide semiconductor film. A high vacuum (e.g., 5×10) is created using an adsorption-type vacuum pump such as an ion pump. -7 Pa From 1×10 -4 It is preferable to evacuate the gas to a level of about 100 Pa. Alternatively, a turbo molecular pump may be used. A cold trap is used to extract gases, especially carbon or hydrogen, from the exhaust system into the chamber. It is preferable to prevent the gas contained therein from flowing backward.

[0162] After the oxide semiconductor film 108b_0 is formed, the oxide semiconductor film 108c The oxide semiconductor film 108c_0 is formed on the oxide semiconductor film 108b. The conditions for forming the oxide semiconductor film 108b_0 can be the same as those for forming the oxide semiconductor film 108b_0. However, the formation conditions of the oxide semiconductor film 108b_0 and the shape of the oxide semiconductor film 108c_0 are different. The synthesis conditions may be the same or different.

[0163] In this embodiment, an In-Ga-Zn metal oxide target (In:Ga:Zn=4: 2:4.1 [atomic ratio]) by sputtering, 0 was formed, and then successively in vacuum, an In-Ga-Zn metal oxide target (In: The oxide semiconductor was deposited by sputtering using Ga:Zn=1:1:1.2 (atomic ratio). The conductive film 108c_0 is formed. In addition, the substrate temperature during the formation of the oxide semiconductor film 108b_0 is The substrate temperature during the formation of the oxide semiconductor film 108c_0 is set to 170° C. The oxide semiconductor film 108b_0 was formed using an oxygen gas at a flow rate of 60 sccm. The oxide semiconductor film 108 was formed by the argon gas at a flow rate of 140 sccm. The deposition gas for forming c_0 was oxygen gas at a flow rate of 100 sccm and cm of argon gas is used.

[0164] Next, the oxide semiconductor film 108b_0 and the oxide semiconductor film 108c_ are processed into desired shapes. By this, island-shaped oxide semiconductor films 108b and 108c are formed. In this embodiment, the oxide semiconductor film 108b and the oxide semiconductor film 10 The oxide semiconductor film 108 is formed from 8c (see FIG. 8A).

[0165] After the oxide semiconductor film 108 is formed, heat treatment (hereinafter referred to as first heat treatment) is performed. The first heat treatment is preferably performed to remove hydrogen contained in the oxide semiconductor film 108. It is possible to reduce the amount of water and the like. Note that the heat treatment for the purpose of reducing hydrogen, water, and the like is The first heat treatment may be performed before processing the semiconductor film 108 into an island shape. This is one of the processes for purifying conductive films.

[0166] The first heat treatment is carried out at a temperature of, for example, 150° C. or higher and lower than the distortion point of the substrate, preferably 200° C. The heating temperature can be set to 250°C or higher and 450°C or lower, and more preferably 250°C or higher and 350°C or lower.

[0167] The first heat treatment can be performed using an electric furnace, an RTA device, or the like. By using this, it is possible to perform heat treatment at a temperature above the strain point of the substrate for a short period of time. Therefore, the heating time can be shortened. Dry air (water content less than 20 ppm, preferably less than 1 ppm, preferably less than 10 ppm) The reaction can be carried out under an atmosphere of air (air below 100°C) or a rare gas (argon, helium, etc.). It is preferable that the nitrogen, oxygen, ultra-dry air, or rare gas does not contain hydrogen, water, etc. In addition, after heat treatment in a nitrogen or rare gas atmosphere, heating in an oxygen or ultra-dry air atmosphere As a result, hydrogen, water, and the like contained in the oxide semiconductor film are released, and the oxide semiconductor film is desorbed. As a result, oxygen contained in the oxide semiconductor film can be supplied to the oxide semiconductor film. Oxygen deficiency can be reduced.

[0168] Next, openings 151 are formed in desired regions of the insulating film 106 and the insulating film 107. The opening 151 reaches the conductive film 104 (see FIG. 8B).

[0169] The opening 151 is formed by either dry etching or wet etching. In this embodiment, the dry etching method is used. The opening 151 is formed by a coating method.

[0170] Next, a conductive film 112_1 is formed over the insulating film 107, the oxide semiconductor film 108, and the conductive film 104. , 112_2 are formed (see FIG. 8(C)).

[0171] In this embodiment, a titanium film having a thickness of 30 nm is formed by sputtering as the conductive film 112_1. A copper film having a thickness of 200 nm is formed as the conductive film 112_2 by sputtering. The film is formed by the ring method.

[0172] Next, masks 141a, 141b, and 141c are formed in desired regions on the conductive film 112_2. Subsequently, the conductive film 112_2 is processed using masks 141a, 141b, and 141c. By doing so, the island-shaped metal film 112a_2, the island-shaped metal film 112b_2, and the island-shaped metal film 112c_2 (see FIG. 9(A)).

[0173] In this embodiment, the conductive film 112_2 is formed by using a wet etching apparatus. However, the method for processing the conductive film 112_2 is not limited to this, and may be, for example, A dry etching device may also be used.

[0174] Next, the masks 141a, 141b, and 141c are removed. and forming a conductive film 112_3 on the metal films 112a_2, 112b_2, and 112c_2. (See Figure 9(B)).

[0175] In this embodiment, a titanium film having a thickness of 10 nm is formed by sputtering as the conductive film 112_3. The conductive film 112_3 is formed by a coating method. 112b_2 and 112c_2 are structures surrounded by the conductive film 112_1 and the conductive film 112_3. The conductive film 112_1 and the conductive film 112_3 form metal films 112a_2, 112b_2, By configuring the metal films 112a_2, 112b_2, and 112c_2 to surround each other, 2 is prevented from diffusing to the outside, particularly into the oxide semiconductor film 108. This can be done.

[0176] Next, masks 142a, 142b, and 142c are formed in desired regions on the conductive film 112_3. Subsequently, the conductive film 112_1 and the conductive film 112_2 are formed using masks 142a, 142b, and 142c. By processing the metal film 112_3, an island-shaped metal film 112a_1 and an island-shaped metal film 112b _1, an island-shaped metal film 112c_1, an island-shaped metal film 112a_3, and an island-shaped metal film 11 By performing this process, the metal film 2b_3 and the island-shaped metal film 112c_3 are formed. a conductive film 112a having a metal film 112a_1, a metal film 112a_2, and a metal film 112a_3; , a conductive film 112b_1, a metal film 112b_2, and a metal film 112b_3 12b, and a metal film 112c_1, a metal film 112c_2, and a metal film 112c_3. A conductive film 112c is formed (see FIG. 9C).

[0177] In this embodiment, a dry etching apparatus is used to form the conductive films 112_1 and The conductive film 112_3 is processed. However, the processing method of the conductive film 112_1 and the conductive film 112_3 is The method is not limited to this, and for example, a wet etching device may be used.

[0178] After the conductive films 112a and 112b are formed, the oxide semiconductor film 108 (more specifically, The surface (back channel side) of the oxide semiconductor film 108c may be cleaned. For example, cleaning using a chemical solution such as phosphoric acid can be used. By performing the cleaning, impurities (for example, impurities adhering to the surface of the conductive film 108c) are removed. The cleaning process can remove elements contained in 112a and 112b. In some cases, cleaning may not be necessary.

[0179] In addition, either one of the steps of forming the conductive films 112a and 112b and the cleaning step may be performed. In either case, the region of the oxide semiconductor film 108 exposed from the conductive films 112a and 112b is However, it may become thinner.

[0180] Next, the insulating film 114 and the insulating layer 116 are formed over the oxide semiconductor film 108 and the conductive films 112a and 112b. The velum 116 is formed (see FIG. 10(A)).

[0181] After the insulating film 114 is formed, the insulating film 116 is successively formed without exposure to the air. After the insulating film 114 is formed, it is preferable to control the flow rate, pressure, and temperature of the source gas without exposing the insulating film 114 to the atmosphere. By adjusting one or more of the frequency power and the substrate temperature, the insulating film 116 is continuously formed. The concentration of impurities derived from atmospheric components can be reduced at the interface between the insulating film 114 and the insulating film 116. can.

[0182] For example, a silicon oxynitride film is formed as the insulating film 114 by using a PECVD method. In this case, the source gas may be a deposition gas containing silicon and an oxidizing gas. It is preferable to use the following gases. Typical examples of deposition gases containing silicon include silane, disilane, and the like. Examples of oxidizing gases include nitrous oxide, nitrous dioxide, etc. In addition, the flow rate of the oxidizing gas is set to 20 times or more than 50 times the flow rate of the deposition gas. 00-fold or less, preferably 40-fold to 100-fold.

[0183] In this embodiment, the insulating film 114 is formed by heating the substrate 102 at a temperature of 220°C. Silane at a flow rate of 50 sccm and dinitrogen monoxide at a flow rate of 2000 sccm were used as source gases. The pressure in the processing chamber was set to 20 Pa, and the high frequency power supplied to the parallel plate electrodes was set to 13.56 M. Hz, 100W (power density is 1.6 x 10 -2 W / cm2 ) PECVD method A silicon oxynitride film is formed using the silicon oxynitride film.

[0184] The insulating film 116 is formed by depositing a substrate placed in a vacuum-evacuated processing chamber of a PECVD device. The temperature is kept at 180°C or higher and 350°C or lower, and the raw material gas is introduced into the processing chamber to increase the pressure in the processing chamber. is set to 100 Pa or more and 250 Pa or less, more preferably 100 Pa or more and 200 Pa or less. , 0.17 W / cm to the electrode installed in the processing chamber 2 More than 0.5W / cm 2 Below are some more good ones: Preferably 0.25W / cm 2 More than 0.35W / cm 2 The following high frequency power supply conditions are met: In this way, a silicon oxide film or a silicon oxynitride film is formed.

[0185] The conditions for forming the insulating film 116 are as follows: a high frequency voltage of the above power density in a reaction chamber of the above pressure; By supplying power, the decomposition efficiency of the source gas in the plasma increases, and oxygen radicals increase. As the oxidation of the source gas progresses, the oxygen content in the insulating film 116 becomes higher than the stoichiometric composition. On the other hand, in the film formed at the above substrate temperature, the bonding strength between silicon and oxygen is As a result, the stoichiometric amount of oxygen in the film is reduced by the heat treatment in the subsequent process. Oxides that contain more oxygen than the stoichiometric composition and lose some of the oxygen when heated An insulating film can be formed.

[0186] In the step of forming the insulating film 116, the insulating film 114 serves as a protection film for the oxide semiconductor film 108. Therefore, the power density can be reduced while reducing damage to the oxide semiconductor film 108. The insulating film 116 can be formed using high radio frequency power.

[0187] In the film formation conditions for the insulating film 116, a deposition gas containing silicon is mixed with an oxidizing gas. By increasing the flow rate of the gas, it is possible to reduce the number of defects in the insulating film 116. In the ESR measurement, the g value of 2.001, which is due to the dangling bond of silicon, The spin density of the signal is 6×10 17 spins / cm 3 Less than 3 x 10 17 spins / cm 3 Less than or equal to 1.5 × 10 17 spins / cm 3 The following is a missing An oxide insulating film with few defects can be formed. As a result, the signal quality of the transistor 100 can be improved. It can increase reliability.

[0188] After the insulating films 114 and 116 are formed, heat treatment (hereinafter referred to as second heat treatment) is performed. The second heat treatment is preferably performed to remove nitrogen oxides contained in the insulating films 114 and 116. Alternatively, the second heat treatment can reduce the amount of oxides in the insulating films 114 and 116. Part of the oxygen contained in the oxide semiconductor film 108 is transferred to the oxide semiconductor film 108. This can reduce oxygen deficiency.

[0189] The temperature of the second heat treatment is typically less than 400°C, preferably less than 375°C, and The second heat treatment is preferably performed at a temperature of 150° C. or higher and 350° C. or lower. Dry air (water content is 20 ppm or less, preferably 1 ppm or less, preferably 10 ppb The reaction may be carried out under an atmosphere of air (see below) or a rare gas (argon, helium, etc.). It is preferable that the nitrogen, oxygen, ultra-dry air, or rare gas does not contain hydrogen, water, etc. The heat treatment can be performed using an electric furnace, RTA, or the like.

[0190] Next, an oxide conductive film 120_1 is formed over the insulating film 116 (see FIGS. 10B and 10C). ).

[0191] 10B shows a film formation process when the oxide conductive film 120_1 is formed on the insulating film 116. FIG. 10(B) is a cross-sectional view of the inside of the device. The target 193 is installed inside the sputtering device. 19 and the plasma 194 formed below.

[0192] First, when forming the oxide conductive film 120_1, plasma is generated in an atmosphere containing oxygen gas. At this time, an oxide conductive film 120_1 is formed on the insulating film 116, and an oxide conductive film 120_2 is formed on the insulating film 116. When forming the oxide conductive film 120_1, in addition to oxygen gas, inactive A reactive gas (e.g., helium gas, argon gas, xenon gas, etc.) may be mixed. .

[0193] The oxygen gas may be any gas that is contained at least when the oxide conductive film 120_1 is formed. The ratio of oxygen gas to the total film-forming gas when forming the oxide conductive film 120_1 is often The ratio is more than 0% and not more than 100%, preferably 10% or more and not more than 100%, and more preferably is between 30% and 100%.

[0194] In FIG. 10B, oxygen or excess oxygen added to the insulating film 116 is schematically shown. are indicated by dashed arrows.

[0195] In this embodiment, an In-Ga-Zn metal oxide target (In:Ga:Zn=4: 2:4.1 [atomic ratio]) by sputtering, Form.

[0196] In this embodiment, when the oxide conductive film 120_1 is formed, the insulating film 116 is not subjected to oxidation. However, the present invention is not limited to this. For example, the oxide conductive film 120 After forming the insulating film 116, oxygen may be further added to the insulating film 116.

[0197] The method of adding oxygen to the insulating film 116 is, for example, to add indium, tin, and silicon. and an oxide (also called ITSO) target (In2O3:SnO2:SiO2= 85:10:5 [wt %]) to form a 5 nm thick ITSO film. Form as 1.

[0198] In this case, the thickness of the oxide conductive film 120_1 is 1 nm or more and 20 nm or less, or When the thickness is 2 nm or more and 10 nm or less, oxygen can be suitably transmitted and oxygen release can be suppressed. After that, oxygen is added to the insulating film 116 by passing through the oxide conductive film 120_1. Oxygen can be added by ion doping, ion implantation, plasma treatment, etc. In addition, when adding oxygen, applying a bias voltage to the substrate side is effective. In addition, oxygen can be added to the insulating film 116. As the bias voltage, for example, The power density of the bias voltage applied to the substrate side of the ashing device was set to 1. W / cm 2 More than 5W / cm 2 The substrate temperature when adding oxygen is set to 0.055°C or less. In this case, the temperature is set to be between room temperature and 300°C, preferably between 100°C and 250°C. Oxygen can be efficiently added to the insulating film 116.

[0199] Next, a mask is formed on the oxide conductive film 120_1 by a lithography process. Openings 152a and 152b are formed in desired regions of the conductive film 120_1 and the insulating films 114 and 116. The opening 152a is formed so as to reach the conductive film 112b. The film 52b is formed to reach the conductive film 112c (see FIG. 11A).

[0200] The openings 152a and 152b are formed by dry etching and wet etching. In this embodiment, the driver circuit can be formed by using either one or both of the driver circuit and the driver circuit. The openings 152a and 152b are formed by dry etching.

[0201] Next, a metal film 12 is formed on the oxide conductive film 120_1, the conductive film 112b, and the conductive film 112c. 0_2 (see FIG. 11(B)).

[0202] In this embodiment, the metal film 120_2 is formed by sputtering to a thickness of 100 nm. A titanium film of 1000 nm is formed.

[0203] Next, a mask is formed on the metal film 120_2 by lithography, and then the metal film 12 0_2 and the oxide conductive film 120_1 are processed into a desired shape, thereby forming an island-shaped conductive film 12 The conductive film 120a is formed of an oxide film having an island shape and a conductive film 120b having an island shape. The conductive film 120a_1 and the island-shaped metal film 120a_2 are included. The insulating film 120b has an oxide conductive film 120b_1 and an island-shaped metal film 120b_2 (see FIG. 11(C)). see).

[0204] Next, an insulating film 118 is formed on the insulating film 116 and the conductive films 120a and 120b (FIG. 12).

[0205] The insulating film 118 contains either hydrogen or nitrogen, or both. For example, a silicon nitride film is preferably used as the insulating film 118. For example, it can be formed by using a sputtering method or a PECVD method. When the insulating film 118 is formed by the PECVD method, the substrate temperature is set to be less than 400° C., preferably 375° C. The temperature is preferably less than 180° C., and more preferably 180° C. or more and 350° C. or less. In this case, it is preferable to set the substrate temperature within the above range, since a dense film can be formed. By setting the substrate temperature in the above range when forming the insulating film 118, the insulating films 114 and 1 Oxygen or excess oxygen in the oxide semiconductor film 106 can be transferred to the oxide semiconductor film 108.

[0206] In addition, when a silicon nitride film is formed as the insulating film 118 by the PECVD method, silicon It is preferable to use a deposition gas containing ammonium, nitrogen, and ammonia as source gases. By using a small amount of ammonia compared to the amount of oxygen, the ammonia dissociates in the plasma and becomes active. The activated species are formed by bonding silicon and hydrogen contained in the silicon-containing deposition gas. This breaks the triple bond between silicon and nitrogen, promoting the bonding of silicon and nitrogen. It is possible to form a dense silicon nitride film with few silicon and hydrogen bonds and few defects. On the other hand, if the amount of ammonia relative to nitrogen is high, the deposition gas containing silicon and nitrogen The decomposition of the silicon does not proceed, and silicon and hydrogen bonds remain, resulting in increased defects and roughness. For these reasons, the source gas is not suitable for ammonia. It is preferable that the flow rate ratio of nitrogen to oxygen is 5 times or more and 50 times or less, or 10 times or more and 50 times or less.

[0207] In this embodiment, the insulating film 118 is formed by depositing silane, nitrogen, and the like using a PECVD apparatus. A silicon nitride film with a thickness of 50 nm is formed using nitrogen and ammonia as source gases. The flow rates were 50 sccm for silane, 5000 sccm for nitrogen, and 1000 sccm for ammonia. The pressure in the processing chamber was 100 Pa, the substrate temperature was 350°C, and the flow rate was 27.12 Mpa. A high-frequency power supply of 1000 W was used to supply high-frequency power to the parallel plate electrodes. The device has an electrode area of ​​6000 cm 2 It is a parallel plate type PECVD device, and the supplied voltage The force can be converted to power per unit area (power density) as 1.7 x 10 -1 W / cm 2 is .

[0208] After the insulating film 118 is formed, the insulating film 118 is subjected to the same heat treatment as the first and second heat treatments described above. A heat treatment (hereinafter referred to as a third heat treatment) may be performed.

[0209] By performing the third heat treatment, the oxide conductive film 120_1 is added to the insulating film 116 during the formation of the oxide conductive film 120_1. The added oxygen moves into the oxide semiconductor film 108 (particularly the oxide semiconductor film 108b) and is oxidized. The oxygen vacancies in the compound semiconductor film 108 are compensated for.

[0210] Through the above steps, the transistor 100 illustrated in FIGS.

[0211] In addition, in all the manufacturing steps of the transistor 100, the substrate temperature is preferably less than 400° C. or less than 375°C, and more preferably between 180°C and 350°C. This is preferable because it is possible to minimize deformation (distortion or warpage) of the substrate even when using such a substrate. In the manufacturing process of the transistor 100, the substrate temperature is increased. Typically, the substrate temperature during the formation of the insulating films 106 and 107 is less than 400° C., preferably the substrate temperature during deposition of the oxide semiconductor film 108 (room temperature or higher, 3 Less than 40°C, preferably 100°C or more and 200°C or less, more preferably 100°C or more and 15 0°C), the substrate temperature during the formation of the insulating films 116 and 118 (less than 400°C, preferably 37 5°C or less, more preferably 180°C or more and 350°C or less), the first heating treatment, the second heating or a third heat treatment (less than 400°C, preferably less than 375°C, more preferably (180°C or higher and 350°C or lower)

[0212] Note that the structures and methods described in this embodiment mode may be combined as appropriate with structures and methods described in other embodiment modes. They can be used in combination.

[0213] (Embodiment 2) In this embodiment, a composition of an oxide semiconductor that can be used in one embodiment of the present invention will be described. The structure of the oxide semiconductor and the like will be described with reference to FIGS.

[0214] <2-1. Composition of oxide semiconductor> First, the composition of the oxide semiconductor will be described.

[0215] The oxide semiconductor preferably contains at least indium or zinc. In addition to these, aluminum, gallium, It is preferable that yttrium or tin is contained. Also, boron, silicon, Titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium , neodymium, hafnium, tantalum, tungsten, magnesium, etc. One or more of these may be included.

[0216] Here, a case where the oxide semiconductor contains indium, an element M, and zinc is considered. The element M is aluminum, gallium, yttrium, or tin. The elements that can be used for M include boron, silicon, titanium, iron, nickel, and germanium. Zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum However, the element M may be a combination of multiple of the above elements. It's okay to combine them.

[0217] First, with reference to FIGS. 13(A), 13(B), and 13(C), the oxidation method according to the present invention will be described. The preferred range of the atomic ratio of indium, element M, and zinc contained in the compound semiconductor will be explained. Note that the atomic ratio of oxygen is not shown in FIG. 13. The atomic ratios of indium, element M, and zinc are expressed as [In], [M], and and [Zn].

[0218] In Figures 13(A), 13(B), and 13(C), the dashed lines indicate the ratio of [In]:[M ]:[Zn]=(1+α):(1-α):1 atomic ratio (-1≦α≦1), The line where the atomic ratio of [In]:[M]:[Zn]=(1+α):(1-α):2, [ The line where the atomic ratio of In]:[M]:[Zn]=(1+α):(1-α):3 is n]:[M]:[Zn]=(1+α):(1-α):4, and The line where the atomic ratio of [In]:[M]:[Zn]=(1+α):(1-α):5 is shown. vinegar.

[0219] The dashed line indicates the atomic ratio of [In]:[M]:[Zn]=1:1:β (β≧0). The line where the atomic ratio of [In]:[M]:[Zn]=1:2:β, the line where [In ]:[M]:[Zn]=1:3:β, the atomic ratio is [In]:[M]:[Zn ]=1:4:β, and the atomic ratio of [In]:[M]:[Zn]=2:1:β. The line where the atomic ratio is [In]:[M]:[Zn]=5:1:β Represents in.

[0220] The dashed double-dashed line indicates the atomic number of [In]:[M]:[Zn]=(1+γ):2:(1-γ). The ratio (-1≦γ≦1) is shown. Oxide semiconductors with an atomic ratio of [n] = 0:2:1 or a value close to that have a spinel-type crystal structure Easy to take.

[0221] 13A and 13B show the in-situ structure of the oxide semiconductor of one embodiment of the present invention. 1 shows an example of a preferred range of the atomic ratio of sodium, the element M, and zinc.

[0222] As an example, FIG. 14 shows InMZn where [In]:[M]:[Zn]=1:1:1. Figure 14 shows the crystal structure of InMZ when observed from a direction parallel to the b axis. The crystal structure of nO4 is shown in FIG. 14. The layer having M, Zn, and oxygen (hereinafter referred to as (M, The metal element in the (Zn) layer represents element M or zinc. The ratio of lead is equal. The element M and zinc are interchangeable and the arrangement is random. do.

[0223] InMZnO4 has a layered crystal structure (also called a layered structure), as shown in Figure 14. The layer containing element M, zinc, and oxygen (hereinafter referred to as the In layer) is 1. The (M,Zn) layer containing oxygen becomes 2.

[0224] In addition, indium and element M can be substituted for each other. Therefore, the element of the (M, Zn) layer The element M can be replaced with indium, and the layer can be expressed as (In,M,Zn). In this case, In It has a layered structure with one layer and two (In, M, Zn) layers.

[0225] In the oxide semiconductor with the atomic ratio of [In]:[M]:[Zn]=1:1:2, the In layer It has a layered structure with 1 (M,Zn) layer and 3 (M,Zn) layers. On the other hand, when [Zn] becomes large, when the oxide semiconductor crystallizes, the (M, Z The proportion of n) layers increases.

[0226] However, in the oxide semiconductor, the number of In layers is 1 and the number of (M, Zn) layers is a non-integer. In this case, there may be multiple types of layered structures in which the number of In layers is 1 and the number of (M, Zn) layers is an integer. For example, when [In]:[M]:[Zn]=1:1:1.5, the In layer is 1:1:1. The layered structure with two (M, Zn) layers and the layered structure with three (M, Zn) layers are mixed. This may result in a layered structure.

[0227] For example, when forming an oxide semiconductor film using a sputtering device, the atomic ratio of the target In particular, depending on the substrate temperature during film formation, the target The [Zn] of the film may be smaller than the [Zn] of the substrate.

[0228] Furthermore, multiple phases may coexist in an oxide semiconductor (such as two-phase coexistence or three-phase coexistence). For example, at an atomic ratio close to the atomic ratio of [In]:[M]:[Zn]=0:2:1, In [In], two phases, a spinel-type crystal structure and a layered crystal structure, tend to coexist. At atomic ratios close to the atomic ratio of [M]:[Zn]=1:0:0, Two phases, a crystalline structure with a layered structure and a crystalline structure with a crystalline structure with a layered structure, tend to coexist. When these coexist, grain boundaries form between different crystal structures. may be formed.

[0229] In addition, by increasing the indium content, the carrier mobility (electron transfer rate) of the oxide semiconductor can be improved. This is because the oxide semiconductor containing indium, element M, and zinc can In conductors, the s orbitals of heavy metals mainly contribute to carrier conduction, and the indium content By increasing the indium content, the overlapping area of ​​the s orbitals becomes larger. Oxide semiconductors with a high indium content have a higher carrier mobility than oxide semiconductors with a low indium content. This is because the

[0230] On the other hand, when the content of indium and zinc in the oxide semiconductor is low, the carrier mobility Therefore, the atomic ratio of [In]:[M]:[Zn]=0:1:0, and In the atomic ratios near this value (for example, region C shown in FIG. 13(C)), the insulating properties become high. .

[0231] Therefore, the oxide semiconductor of one embodiment of the present invention has high carrier mobility and few grain boundaries. It is preferable that the atomic ratio be that shown in region A in FIG. 13(A), which is likely to form a layered structure with a good atomic ratio. It's nice.

[0232] In addition, in the region B shown in FIG. 13(B), [In]:[M]:[Zn]=4:2:3 to 4 .1 and its neighboring values. For example, the atomic ratio [In]:[M ]:[Zn]=5:3:4. Oxide semiconductors having the atomic ratio shown in region B is an excellent oxide semiconductor having particularly high crystallinity and high carrier mobility.

[0233] The condition for an oxide semiconductor to form a layered structure is not uniquely determined by the atomic ratio. The difficulty of forming a layered structure varies depending on the atomic ratio. However, depending on the forming conditions, a layered structure may or may not be formed. Therefore, the illustrated region is a region showing the atomic ratio in which the oxide semiconductor has a layered structure, and the region The boundaries between areas A and C are not strict.

[0234] <2-2. Structure using oxide semiconductor in transistor> Next, a structure in which an oxide semiconductor is used for a transistor will be described.

[0235] Note that the use of an oxide semiconductor in a transistor reduces carrier scattering at grain boundaries. This allows for a reduction in the amount of charge, making it possible to realize a transistor with high field effect mobility. Furthermore, a highly reliable transistor can be realized.

[0236] In addition, an oxide semiconductor with low carrier density is used for the channel region of a transistor. For example, the oxide semiconductor preferably has a carrier density of 8×10 11 / cm 3Less than, good Preferably 1 x 10 11 / cm 3 less than 1×10 10 / cm 3 is less than , 1×10 -9 / cm 3 That's all there is to it.

[0237] Note that a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor has a carrier generation source. In addition, the carrier density can be reduced because the Intrinsic oxide semiconductors have a low density of defect states, and therefore a low density of trap states. There are cases where this happens.

[0238] In addition, the time required for the charges trapped in the trap levels of the oxide semiconductor to disappear is Therefore, the trap level density is high. A transistor in which a channel region is formed in a thin oxide semiconductor may have unstable electrical characteristics. There is a match.

[0239] Therefore, in order to stabilize the electrical characteristics of a transistor, the impurity concentration in the oxide semiconductor In order to reduce the impurity concentration in the oxide semiconductor, it is effective to reduce It is preferable to reduce the impurity concentration in the adjacent film. These include alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0240] Here, the influence of each impurity in an oxide semiconductor will be described.

[0241] When oxide semiconductors contain silicon or carbon, which are elements of Group 14, they are oxidized. Defect levels are formed in semiconductors, which is why defects in silicon and carbon in oxide semiconductors The concentration of silicon and carbon near the interface with the oxide semiconductor (secondary ion mass spectrometry) (SIMS: Secondary Ion Mass Spectrometry) The concentration obtained is 2 x 10 18 atoms / cm 3 Less than or equal to 2 x 10 17 a toms / cm 3 The following applies.

[0242] In addition, when an oxide semiconductor contains an alkali metal or an alkaline earth metal, the defect level is Therefore, alkali metals or alkaline earth metals A transistor using an oxide semiconductor containing such a compound tends to be normally on. Therefore, it is possible to reduce the concentration of alkali metals or alkaline earth metals in the oxide semiconductor. Specifically, it is preferable to use an alkali metal or The concentration of alkaline earth metals is 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 16 atoms / cm 3 Do the following:

[0243] In addition, when nitrogen is contained in an oxide semiconductor, electrons that serve as carriers are generated, and As a result, the oxide semiconductor containing nitrogen is easily converted into an n-type semiconductor. Therefore, the transistor used in the oxide semiconductor tends to be normally on. In this case, it is preferable that the nitrogen content is reduced as much as possible. For example, the nitrogen content in the oxide semiconductor is The concentration is 5×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm3 Less than 1×10, more preferably 18 atoms / cm 3 Below, More preferably 5×10 17 atoms / cm 3 The following applies.

[0244] In addition, hydrogen contained in oxide semiconductors reacts with oxygen that bonds with metal atoms to form water. When hydrogen enters the oxygen vacancy, the electron carrier In addition, some of the hydrogen atoms may bond with the oxygen atoms that bond with the metal atoms, forming chiral ions. Therefore, it is necessary to use an oxide semiconductor containing hydrogen. Therefore, the hydrogen in the oxide semiconductor tends to cause a transistor to be normally on. It is preferable that the amount of Si in the oxide semiconductor is as small as possible. The hydrogen concentration obtained by MS was 1×10 20 atoms / cm 3 Less than 1x, preferably 10 19 atoms / cm 3 less than 5 × 10 18 atoms / cm 3 less than , and more preferably 1 × 10 18 atoms / cm 3 Less than.

[0245] By using an oxide semiconductor with sufficiently reduced impurities for a channel formation region of a transistor, This makes it possible to impart stable electrical properties.

[0246] The oxide semiconductor film has an energy gap of 2 eV or more, or 2.5 eV or more. Alternatively, it is preferably 3 eV or more.

[0247] The thickness of the oxide semiconductor film is 3 nm to 200 nm, preferably 3 nm to 100 nm. 00 nm or less, and more preferably 3 nm or more and 60 nm or less.

[0248] In addition, when the oxide semiconductor film is an In-M-Zn oxide, the In-M-Zn oxide is deposited. The atomic ratio of the metal elements in the sputtering target used for this purpose is In:M:Zn. =1:1:0.5, In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, I n:M:Zn=2:1:1.5, In:M:Zn=2:1:2.3, In:M:Zn=2 :1:3, In:M:Zn=3:1:2, In:M:Zn=4:2:4.1, In:M: Zn=5:1:7, etc. is preferred.

[0249] The atomic ratio of the metal elements in the oxide semiconductor film to be formed is determined by the above sputtering method. The atomic ratio of the metal elements contained in the target varies by approximately ±40%. For example, a sputtering target with an atomic ratio of In:Ga:Zn=4: When 2:4.1 is used, the atomic ratio of the oxide semiconductor film to be formed is In:Ga:Zn= In some cases, the atomic ratio is around 4:2:3. When In:Ga:Zn=5:1:7 is used, the atomic ratio of the oxide semiconductor film to be formed is In some cases, the ratio is approximately In:Ga:Zn=5:1:6.

[0250] <2-3. Oxide Semiconductor Stack Structure> Next, a stacked structure of oxide semiconductors will be described.

[0251] Here, the oxide semiconductor layer has a two-layer structure or a three-layer structure. The case where the oxide semiconductor S1, the oxide semiconductor S2, and the oxide semiconductor S The band diagram of the insulator in contact with the stacked structure of S3 and the product of the oxide semiconductor S2 and the oxide semiconductor S3 are shown in Fig. The band diagram of the insulator in contact with the layer structure will be explained with reference to FIG.

[0252] FIG. 15(A) shows an insulator I1, an oxide semiconductor S1, an oxide semiconductor S2, and an oxide semiconductor S 15 is an example of a band diagram in the thickness direction of a stacked structure having an insulator I2 and an insulator I3. (B) has an insulator I1, an oxide semiconductor S2, an oxide semiconductor S3, and an insulator I2 1 is an example of a band diagram in the film thickness direction of a laminated structure. Insulator I1, oxide semiconductor S1, oxide semiconductor S2, oxide semiconductor S3, and insulator I2 The energy level (Ec) at the bottom of the conduction band of

[0253] The oxide semiconductors S1 and S3 have lower energy at the bottom of the conduction band than the oxide semiconductor S2. The energy level is close to the vacuum level, and typically, the energy level at the bottom of the conduction band of the oxide semiconductor S2 is The difference between the energy level of the oxide semiconductor S1 and the energy level of the oxide semiconductor S3 at the bottom of the conduction band is 0 0.15eV or more, or 0.5eV or more and 2eV or less, or 1eV or less That is, it is preferable that the electron affinities of the oxide semiconductors S1 and S3 and the oxide semiconductors The difference between the electron affinity of conductor S2 is 0.15 eV or more, or 0.5 eV or more and 2 eV It is preferably 1 eV or less, or 1 eV or less.

[0254] As shown in FIGS. 15A and 15B, the oxide semiconductor S1 and the oxide semiconductor S2 In the oxide semiconductor S3, the energy level at the bottom of the conduction band changes gradually. This can be said to be a continuous change or a continuous junction. In order to have such a property, the interface between the oxide semiconductor S1 and the oxide semiconductor S2 or the oxide semiconductor S The defect level density of the mixed layer formed at the interface between the oxide semiconductor S2 and the oxide semiconductor S3 is preferably reduced. stomach.

[0255] Specifically, the oxide semiconductor S1 and the oxide semiconductor S2, the oxide semiconductor S2 and the oxide semiconductor S3, S3 has a common element other than oxygen (as the main component), which results in a mixed structure with a low defect level density. For example, when the oxide semiconductor S2 is an In-Ga-Zn oxide semiconductor, an alloy layer can be formed. In the case of the body, the oxide semiconductor S1 and the oxide semiconductor S3 are In-Ga-Zn oxide semiconductors. , Ga—Zn oxide semiconductor, gallium oxide, etc. may be used.

[0256] At this time, the main carrier path is the oxide semiconductor S2. Defects at the interface with oxide semiconductor S2 and at the interface between oxide semiconductor S2 and oxide semiconductor S3 Since the level density can be reduced, the effect of interface scattering on carrier conduction is small. A high on-current can be obtained.

[0257] When electrons are captured in the trap level, the captured electrons behave like fixed charges. Therefore, the threshold voltage of the transistor shifts in the positive direction. By providing the oxide semiconductor S3, the trap level is located farther from the oxide semiconductor S2. This structure allows the threshold voltage of the transistor to be shifted in the positive direction. This can prevent the device from being damaged.

[0258] The oxide semiconductors S1 and S3 have sufficient conductivity compared to the oxide semiconductor S2. In this case, the oxide semiconductor S2 and the oxide semiconductor S3 are used. The interface between the oxide semiconductor S1 and the oxide semiconductor S2 and the oxide semiconductor S3 is mainly the channel region. For example, the oxide semiconductor S1 and the oxide semiconductor S3 have the following functions: Therefore, it is sufficient to use an oxide semiconductor having an atomic ratio shown in region C where the insulating property is high. Region C shown in 3(C) is [In]:[M]:[Zn]=0:1:0 or its neighboring values. The atomic ratio is shown as follows:

[0259] In particular, when an oxide semiconductor having an atomic ratio shown in region A is used for the oxide semiconductor S2, The compound semiconductor S1 and the oxide semiconductor S3 have an [M] / [In] ratio of 1 or more, preferably 2 or more. It is preferable to use an oxide semiconductor having a sufficient conductivity. Oxide semiconductors with [M] / ([Zn]+[In]) of 1 or more that can provide high insulation It is preferable to use a conductor.

[0260] <2-4. Structure of oxide semiconductors> Next, the structure of the oxide semiconductor will be described.

[0261] Oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. As a non-single-crystal oxide semiconductor, CAAC-OS (c-axis-aligned d crystalline oxide semiconductor), polycrystalline oxide Semiconductor, nc-OS (nanocrystalline oxide semiconductor) conductor), pseudo-amorphous oxide semiconductor (a-like OS: amorphous- amorphous oxide semiconductors and amorphous oxide semiconductors. do.

[0262] From another point of view, oxide semiconductors are classified into amorphous oxide semiconductors and other crystalline oxides. Crystalline oxide semiconductors are divided into single-crystal oxide semiconductors, CAAC -OS, polycrystalline oxide semiconductor, and nc-OS.

[0263] Amorphous structures are generally isotropic and have no heterogeneous structure, and are characterized by the arrangement of atoms in a metastable state. The position is not fixed, the bond angle is flexible, and there is short-range order but no long-range order. It is said that there is no such thing.

[0264] That is, a stable oxide semiconductor is transformed into a completely amorphous In addition, it is not isotropic (for example, in a microscopic region, An oxide semiconductor having a periodic structure cannot be called a completely amorphous oxide semiconductor. -like OS is not isotropic but has an unstable structure with voids. In terms of instability, a-like OS is physically an amorphous oxide semiconductor. Close to.

[0265] [CAAC-OS] First, let me explain about CAAC-OS.

[0266] CAAC-OS is an oxide having multiple crystal parts (also called pellets) aligned along the c-axis. It is a type of semiconductor.

[0267] CAAC-OS was analyzed by X-ray diffraction (XRD). For example, InGaZnO4, which is classified into the space group R-3m, The structure of CAAC-OS with crystal structure was analyzed by the out-of-plane method. As shown in FIG. 16(A), a peak appears at a diffraction angle (2θ) of approximately 31°. The peak is attributed to the (009) plane of the InGaZnO4 crystal, so it is In this case, the crystal has a c-axis orientation, and the c-axis is the surface on which the CAAC-OS film is to be formed (also referred to as the surface on which the film is to be formed). It can be confirmed that the direction is perpendicular to the surface, or approximately perpendicular to the upper surface. In addition to the peak around 2θ of 36°, a peak may also appear around 2θ of 36°. The nearby peak is due to a crystal structure classified into the space group Fd-3m. It is preferable that the C-OS does not exhibit such a peak.

[0268] On the other hand, in-pl X-ray irradiation is performed on CAAC-OS in a direction parallel to the surface to be formed. When structural analysis is performed using the ane method, a peak appears at 2θ around 56°. This peak is It is attributed to the (110) plane of the InGaZnO4 crystal. And, 2θ is fixed at around 56°. The sample is then rotated around the normal vector of the sample surface as the axis (φ axis) for analysis (φ scan). Even if this is done, no clear peak appears as shown in Figure 16(B). When 2θ is fixed at around 56° and φ is scanned for ZnO4, the As shown, six peaks attributable to the crystal plane equivalent to the (110) plane are observed. Structural analysis using XRD revealed that the orientation of the a-axis and b-axis of CAAC-OS is irregular. It can be confirmed that:

[0269] Next, we will explain the CAAC-OS analyzed by electron diffraction. For CAAC-OS with ZnO4 crystals, the process was performed parallel to the surface on which the CAAC-OS was formed. When an electron beam with a probe diameter of 300 nm is incident, a diffraction pattern ( This diffraction pattern may contain I The spots due to the (009) plane of the nGaZnO4 crystal are included. Diffraction also shows that the pellets contained in the CAAC-OS have a c-axis orientation, and the c-axis is formed On the other hand, for the same sample, the direction of the sample surface is perpendicular to the sample surface. The diffraction pattern when an electron beam with a probe diameter of 300 nm was incident perpendicularly to the ) is shown. From Figure 16(E), a ring-shaped diffraction pattern is confirmed. Electron diffraction using an electron beam with a beam diameter of 300 nm also revealed that the pea contained in CAAC-OS It can be seen that the a-axis and b-axis of the slits do not have any orientation. The ring is thought to be due to the (010) and (100) planes of the InGaZnO4 crystal. In addition, the second ring in Figure 16(E) is thought to be due to the (110) plane. can be obtained.

[0270] In addition, a transmission electron microscope (TEM) Combined analysis of bright-field images and diffraction patterns of CAAC-OS using a microscope When observing the image (also called a high-resolution TEM image), multiple pellets can be confirmed. On the other hand, even in high-resolution TEM images, the boundaries between pellets, i.e., grain boundaries (grain boundaries), are not clearly visible. It may not be possible to clearly identify the boundary. It can be said that C-OS is less susceptible to the decrease in electron mobility caused by grain boundaries.

[0271] Figure 17(A) shows a high-resolution image of a cross section of CAAC-OS observed from a direction approximately parallel to the sample surface. The TEM image is shown. For high-resolution TEM observation, spherical aberration correction (SCA) was used. The spherical aberration correction function was used. A high-resolution TEM image is specifically called a Cs-corrected high-resolution TEM image. For example, an atomic resolution analytical electron microscope JEM-ARM200F manufactured by JEOL Ltd. Therefore, it can be observed.

[0272] From Figure 17(A), it is possible to confirm the pellet, which is the region where metal atoms are arranged in layers. The size of a single pellet can be over 1 nm or over 3 nm. Therefore, the pellets can be called nanocrystals (nc). CAAC-OS can also be used as a C-Axis Aligned Navigator (CANC). The pellets can also be called oxide semiconductors with CAA It reflects the unevenness of the surface on which the C-OS is formed or the top surface, and the unevenness of the surface on which the CAAC-OS is formed or It is parallel to the top surface.

[0273] 17(B) and 17(C) show the CAAC images observed from a direction approximately perpendicular to the sample surface. Figures 17(D) and 17(E) show Cs-corrected high-resolution TEM images of the -OS surface. These are the images obtained by processing the images in Figures 17(B) and 17(C), respectively. First, we will explain the method of transforming the image in FIG. 17(B) using the Fast Fourier Transform (FFT). Then, the FFT image is obtained by performing the FFT (Fourier Transform) process. 2.8 nm based on the origin in the FFT image -1 to 5.0 nm -1Leave the range between Next, the masked FFT image is subjected to inverse fast Fourier transform (IFFT). Image processing by using Fast Fourier Transform (FFT) The image obtained in this way is called an FFT filtered image. The tarring image is an image in which the periodic components are extracted from a Cs-corrected high-resolution TEM image, and the lattice arrangement This shows:

[0274] In Figure 17(D), the area where the lattice arrangement is disturbed is indicated by a dashed line. The area indicated by the broken line is the connection between the pellets. The broken line indicates the hexagonal shape of the pellet. The shape of the let is not limited to a regular hexagon, but is often a non-regular hexagon.

[0275] In FIG. 17(E), a grid is formed between a region with a uniform lattice arrangement and a region with a different uniform lattice arrangement. The dotted lines indicate the changes in the orientation of the child array, and the dashed lines indicate the changes in the orientation of the lattice array. Even near the dotted line, no clear grain boundaries can be seen. When connecting the surrounding lattice points around the center, a distorted hexagon, pentagon, and / or heptagon is formed. In other words, it was found that the formation of grain boundaries was suppressed by distorting the lattice arrangement. This is because the atomic arrangement of CAAC-OS is not dense in the ab-plane direction and The substitution of metal elements changes the bond distance between atoms, allowing for distortion. This is thought to be because it is possible to

[0276] As described above, the CAAC-OS has a c-axis orientation and is Multiple pellets (nanocrystals) are connected to form a distorted crystal structure. AAC-OS, CAA crystal(c-axis-aligned abp It can also be called an oxide semiconductor with lane-anchored crystals. Cut.

[0277] CAAC-OS is an oxide semiconductor with high crystallinity. CAAC-OS is designed to be free from impurities and defects. It can also be said to be an oxide semiconductor with few defects (such as oxygen vacancies).

[0278] The impurities are elements other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, and transition metals. For example, metal elements such as silicon are more oxidative than metal elements that constitute oxide semiconductors. Elements with strong bonding strength with the oxide semiconductor remove oxygen from the oxide semiconductor, which changes the atomic arrangement of the oxide semiconductor. In addition, heavy metals such as iron and nickel, argon, Carbon dioxide and other molecules have a large atomic radius (or molecular radius), so the atomic arrangement of oxide semiconductors This disrupts the structure and reduces the crystallinity.

[0279] When an oxide semiconductor has impurities or defects, its characteristics may change due to light, heat, etc. For example, impurities contained in oxide semiconductors can act as carrier traps or For example, oxygen vacancies in oxide semiconductors can act as carrier traps. In some cases, the SiO 2 traps hydrogen and becomes a carrier generation source.

[0280] CAAC-OS, which has few impurities and oxygen vacancies, is an oxide semiconductor with low carrier density. Specifically, 8×10 11cm -3 Less than 1 x 10 11 cm -3 Less than, More preferably, 1×10 10 cm -3 Less than 1 x 10 -9 cm -3 More than a career Such an oxide semiconductor can be a highly pure intrinsic or CAAC-OS is essentially a highly pure intrinsic oxide semiconductor. The state density is low, that is, the oxide semiconductor has stable characteristics.

[0281] [nc-OS] Next, we will explain nc-OS.

[0282] We will explain the analysis of nc-OS by XRD. However, when structural analysis was performed using the out-of-plane method, no peaks indicating orientation appeared. That is, the crystals of the nc-OS do not have any orientation.

[0283] For example, an nc-OS having InGaZnO4 crystals was thinned to a thickness of 34 nm. When an electron beam with a probe diameter of 50 nm is incident parallel to the surface to be formed on the region of m, the A ring-shaped diffraction pattern (nanobeam electron diffraction pattern) as shown in 8(A) was observed. In addition, the diffraction pattern ( The nanobeam electron diffraction pattern is shown in Figure 18(B). Therefore, the nc-OS probe diameter is 50 nm. However, when an electron beam with a probe diameter of 1 nm is incident, the order is not observed. Order is confirmed by injecting light.

[0284] In addition, when an electron beam with a probe diameter of 1 nm is incident on an area with a thickness of less than 10 nm, As shown in FIG. 18(C), an electron diffraction pattern was observed in which the spots were arranged in a substantially regular hexagonal shape. Therefore, it is possible to assume that the nc-OS is ordered in the range of thickness less than 10 nm. It can be seen that the crystals have highly ordered regions, i.e., crystals. Therefore, there are some areas where a regular electron diffraction pattern is not observed.

[0285] FIG. 18(D) shows the Cs-corrected height of the cross section of the nc-OS observed from a direction approximately parallel to the surface on which the film is formed. The nc-OS is shown in the high-resolution TEM image, with the areas indicated by the auxiliary lines. How to identify the crystal areas and areas where no clear crystal areas can be identified The crystal parts contained in the nc-OS have a size of 1 nm to 10 nm. The size of the crystal is often between 1 nm and 3 nm. An oxide semiconductor with a size of greater than 10 nm and less than 100 nm is called a microcrystalline oxide semiconductor (microcrystalline oxide semiconductor). It is called a crystalline oxide semiconductor. In the case of nc-OS, for example, the grain boundaries cannot be clearly identified in high-resolution TEM images. It is possible that the nanocrystals originate from the same source as the pellets in CAAC-OS. Therefore, the crystalline part of nc-OS may be referred to as a pellet below.

[0286] In this way, nc-OS can be used in microscopic regions (e.g., regions between 1 nm and 10 nm, especially The atomic arrangement has periodicity in the region of 1 nm to 3 nm. In the case of the SiO2 film, there is no regularity in the crystal orientation between different pellets. Therefore, depending on the analytical method, nc-OS may be classified as a-like OS or amorphous OS. In some cases, it may be difficult to distinguish them from solid oxide semiconductors.

[0287] In addition, since there is no regularity in the crystal orientation between the pellets (nanocrystals), nc-OS , oxidation with RANC (Random Aligned nanocrystals) semiconductors or NANC (Non-Aligned nanocrystals) The oxide semiconductor may also be called an oxide semiconductor.

[0288] The nc-OS is an oxide semiconductor with higher order than an amorphous oxide semiconductor. The nc-OS has a lower density of defect states than the a-like OS and amorphous oxide semiconductors. However, in nc-OS, there is no regularity in the crystal orientation between different pellets. Therefore, the nc-OS has a higher density of defect states than the CAAC-OS.

[0289] [a-like OS] The a-like OS is an oxide semiconductor with a structure between the nc-OS and amorphous oxide semiconductor. It is a semiconductor.

[0290] Figure 19 shows a high-resolution cross-sectional TEM image of the a-like OS. is a high-resolution cross-sectional TEM image of the a-like OS at the start of electron irradiation. B) is 4.3 x 10 8 e - / nm 2 electrons (e - ) a-like OS after irradiation High-resolution cross-sectional TEM images. Figures 19(A) and 19(B) show that a-like OS It can be seen that bright striped regions extending in the vertical direction are observed from the start of electron irradiation. It can be seen that the bright areas change shape after electron irradiation. It is estimated to be in the degree range.

[0291] Because of the porosity, the a-like OS has an unstable structure. e) To demonstrate that the OS has an unstable structure compared to the CAAC-OS and nc-OS. , showing the structural changes caused by electron irradiation.

[0292] As samples, a-like OS, nc-OS, and CAAC-OS are prepared. The sample is also an In-Ga-Zn oxide.

[0293] First, high-resolution cross-sectional TEM images of each sample are acquired. All of the materials have crystalline parts.

[0294] The unit cell of the InGaZnO4 crystal has three In-O layers and one Ga-Zn It is known that the structure has a total of nine layers, six of which are -O layers, stacked in layers along the c-axis. The distance between these adjacent layers is determined by the lattice spacing (also called the d value) of the (009) plane. The value is about the same, and is calculated to be 0.29 nm from crystal structure analysis. In the following, the area where the lattice spacing is 0.28 nm or more and 0.30 nm or less is referred to as InGaZ. The lattice fringes correspond to the ab plane of the InGaZnO4 crystal. do.

[0295] Figure 20 shows an example of investigating the average size of the crystal parts (22 to 30 locations) of each sample. The length of the lattice fringes mentioned above is the size of the crystal part. e The crystal part of the OS grows in size according to the cumulative amount of electron irradiation used to obtain the TEM image. From Figure 20, it can be seen that in the early stages of TEM observation, the size of the particles is about 1.2 nm. The part of the crystal that was left behind (also called the initial nucleus) is filled with electrons (e - ) cumulative exposure is 4.2 × 10 8 e - / nm 2 On the other hand, it can be seen that the size of the crystals grows to about 1.9 nm in the case of n For c-OS and CAAC-OS, the cumulative electron irradiation dose was 4.2 × 10 8 e - / nm 2 It can be seen that there is no change in the size of the crystals within the range of Therefore, the size of the crystalline parts of nc-OS and CAAC-OS is the same regardless of the cumulative dose of electron irradiation. The thicknesses of the electron beam irradiation and T The EM observation was performed using a Hitachi transmission electron microscope H-9000NAR. The electron beam irradiation conditions were The voltage was 300 kV and the current density was 6.7 × 10 5 e - / (nm 2 s), the diameter of the irradiated area was set to 230 nm.

[0296] In this way, the growth of crystalline parts can be observed in a-like OS due to electron irradiation. On the other hand, in the case of nc-OS and CAAC-OS, the growth of the crystals by electron irradiation is almost nonexistent. In other words, the a-like OS is inferior to the nc-OS and CAAC-OS. It is clear that this is a stable structure.

[0297] In addition, due to its porosity, a-like OS is more flexible than nc-OS and CAAC-OS. Specifically, the density of a-like OS is lower than that of a single crystal with the same composition. The density of nc-OS and CAAC- The density of OS is 92.3% or more but less than 100% of the density of a single crystal of the same composition. It is difficult to form a film of an oxide semiconductor having a density of less than 78%.

[0298] For example, in an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, The density of single-crystal InGaZnO4 with a rhombohedral crystal structure is 6.357 g / cm 3 That is it. For example, in an oxide semiconductor that satisfies the atomic ratio of In:Ga:Zn=1:1:1, The density of a-like OS is 5.0 g / cm 3 More than 5.9g / cm 3 It is less than For example, in an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, The densities of nc-OS and CAAC-OS are 5.9 g / cm 3 More than 6.3g / cm 3 is less than.

[0299] If single crystals of the same composition do not exist, single crystals of different compositions can be combined in any ratio. By combining these, it is possible to estimate the density equivalent to a single crystal of a desired composition. The density corresponding to a single crystal of a desired composition is calculated based on the ratio of the single crystals of different compositions combined. However, the density can be estimated by using as few types of single crystals as possible. It is preferable to estimate them together.

[0300] As described above, oxide semiconductors have various structures, each of which has various characteristics. The oxide semiconductor may be, for example, an amorphous oxide semiconductor, an a-like OS, or an nc-OS. The film may be a laminated film having two or more of the above-mentioned compounds.

[0301] Note that the configuration shown in this embodiment may be appropriately combined with configurations shown in other embodiments or examples. , can be used in combination.

[0302] (Embodiment 3) In this embodiment, a display device including the transistor described in the previous embodiment will be described. An example will be described below with reference to FIGS.

[0303] 21 is a top view showing an example of a display device. The display device 700 shown in FIG. A pixel portion 702 is provided on the first substrate 701, and a source driver 703 is provided on the second substrate 701. The pixel section 702, the source driver circuit section 704, the gate driver circuit section 706, a sealant 712 disposed to surround the path portion 704 and the gate driver circuit portion 706; and a second substrate 705 provided so as to face the first substrate 701. The first substrate 701 and the second substrate 705 are sealed with a sealant 712. That is, the pixel section 702, the source driver circuit section 704, and the gate driver circuit section 706 are The first substrate 701, the sealant 712, and the second substrate 705 seal the entire structure. Although not shown in FIG. 21, a display element is provided between the first substrate 701 and the second substrate 705. It can be done.

[0304] The display device 700 is surrounded by a sealant 712 on the first substrate 701. In a region different from the region, a pixel section 702, a source driver circuit section 704, a gate driver circuit section FPC terminals electrically connected to the wiring portion 706 and the gate driver circuit portion 706, respectively. A sub-unit 708 (FPC: Flexible printed circuit) is provided. In addition, an FPC 716 is connected to the FPC terminal portion 708, and the FPC 716 Various signals are sent to the source driver circuit section 702, the source driver circuit section 704, and the gate driver circuit section 706. Also, a pixel section 702, a source driver circuit section 704, a gate driver circuit section A signal line 710 is connected to each of the path portion 706 and the FPC terminal portion 708. Various signals supplied by 716 are transmitted to the pixel section 702, the source driver 716, and the like via signal lines 710. 704, the gate driver circuit section 706, and the FPC terminal section 708. do.

[0305] The display device 700 may be provided with a plurality of gate driver circuits 706. The device 700 includes a source driver circuit section 704 and a gate driver circuit section 706. Although an example in which the pixel portion 702 is formed on the same first substrate 701 is shown, the present invention is not limited to this configuration. For example, only the gate driver circuit section 706 may be formed on the first substrate 701. Alternatively, only the source driver circuit portion 704 may be formed on the first substrate 701. In this case, the substrate on which the source driver circuit or the gate driver circuit etc. is formed (for example, A driving circuit board formed of a crystalline semiconductor film or a polycrystalline semiconductor film is formed on a first substrate 701. The method of connecting the separately formed drive circuit board is not particularly limited. Instead of COG (Chip On Glass) method, wire bonding method, etc. can be used.

[0306] The display device 700 also includes a pixel section 702, a source driver circuit section 704, and a gate The driver circuit portion 706 includes a plurality of transistors. A transistor having a specific position can be applied.

[0307] The display device 700 can also include various elements, such as: For example, electroluminescence (EL) elements (EL elements including organic and inorganic materials, organic EL elements, inorganic EL elements, LEDs, etc.), light-emitting transistor elements (which emit light according to the current) transistors), electron emission elements, liquid crystal elements, electronic ink elements, electrophoretic elements, Low-wetting element, plasma display panel (PDP), MEMS (micro- Electro-mechanical systems) displays (e.g., grating light bulbs) GLV (Glass Laser Diode), Digital Micromirror Device (DMD), Digital Microshaft Distributed Membrane Switching (DMS) element, Interferometric Modulation (IMOD) element ), piezoelectric ceramic displays, etc.

[0308] An example of a display device using an EL element is an EL display. An example of a display device using emission elements is a field emission display (FE D) or SED type flat panel display (SED: Surface-conductive n Electron-emitter Display) etc. An example of such a display device is a liquid crystal display (transmissive liquid crystal display, semi-transmissive liquid crystal display, etc.). Displays, reflective LCD displays, direct-view LCD displays, projection LCD displays Examples of display devices using electronic ink elements or electrophoretic elements include: There are also semi-transmissive LCD displays and reflective LCD displays. In this case, a part or all of the pixel electrode should function as a reflective electrode. For example, a part or the whole of the pixel electrode may be made of aluminum, silver, etc. In this case, a memory circuit such as an SRAM may be provided under the reflective electrode. This can further reduce power consumption.

[0309] The display method of the display device 700 may be a progressive method or an interlace method. In addition, the color elements controlled by pixels when displaying colors include R It is not limited to the three colors GB (R stands for red, G stands for green, B stands for blue). For example, It may be composed of four pixels: a pixel, a B pixel, and a W (white) pixel. Like the column, two colors of RGB make up one color element, and two different colors are created by the color element. Alternatively, you can select one or more colors such as yellow, cyan, magenta, etc. for RGB. The size of the display area may be different for each dot of the color element. However, the disclosed invention is not limited to color display devices, but also to monochrome display devices. The present invention can also be applied to display devices such as those shown in the accompanying drawings.

[0310] Also, white light is emitted from the backlight (organic EL element, inorganic EL element, LED, fluorescent lamp, etc.) In order to display full color using (W), a colored layer (also called a color filter) is used. The colored layer may be, for example, red (R), green (G), blue (B), or the like. ), yellow (Y), etc. can be used in combination as appropriate. In this case, the color reproducibility can be improved compared to when no color layer is used. By disposing a region having a colored layer and a region not having a colored layer, The white light in the region may be directly used for display. By placing the color layer in the display, the decrease in brightness caused by the color layer can be reduced during bright display, and power consumption can be reduced by 2. However, it may be possible to reduce the emission by approximately 100% to 30%. When using optical elements to display full color, R, G, B, Y, and W are emitted by each color. By using a self-luminous element, it is possible to make the light emitted from a colored layer. In some cases, power consumption can be further reduced.

[0311] In addition, as a colorization method, a part of the light emitted from the above-mentioned white light is passed through a color filter. In addition to the color filter method, which converts red, green, and blue by filtering, A method that uses each color of light (three-color method), or a method that uses part of the light emitted from the blue light to emit red or A method of converting to green (color conversion method, quantum dot method) may also be applied.

[0312] In this embodiment, a liquid crystal element and an EL element are used as display elements. 22 and 24. Note that FIG. 22 shows the area indicated by the dashed line QR in FIG. 21. 24 is a cross-sectional view of the liquid crystal display device, which uses a liquid crystal element as a display element. 21 is a cross-sectional view taken along the dashed line QR, and shows a configuration in which an EL element is used as a display element. is.

[0313] First, the common parts shown in Figures 22 and 24 will be explained, and then the different parts will be explained. This will be explained below.

[0314] <3-1. Explanation of common parts of display devices> The display device 700 shown in FIGS. 22 and 24 includes a wiring portion 711, a pixel portion 702, and a , a source driver circuit section 704, and an FPC terminal section 708. The line portion 711 includes a signal line 710. The pixel portion 702 includes a transistor 750 and The source driver circuit portion 704 includes a transistor 752. Has.

[0315] Transistor 750 and transistor 752 are similar to transistor 100 shown above. The structures of the transistors 750 and 752 are the same as those described above. Any of the other transistors shown in the embodiment modes may be used.

[0316] The transistor used in this embodiment is made of a highly purified oxide in which the formation of oxygen vacancies is suppressed. The transistor has a semiconductor film. The off-state current of the transistor can be reduced. This allows for longer retention times for electrical signals such as signals, and the write interval can also be extended when the power is on. Therefore, the frequency of refresh operations can be reduced, resulting in reduced power consumption. It has the effect of suppressing force.

[0317] In addition, the transistor used in this embodiment has a relatively high field-effect mobility. For example, a transistor capable of such high speed driving can be used in a liquid crystal display. By using this in a display device, the switching transistor in the pixel section and the driver circuit section can be In other words, the driver transistor can be formed on the same substrate as a separate driver circuit. Therefore, it is not necessary to use a semiconductor device formed from a silicon wafer or the like. The number of components can be reduced. By using a register, high quality images can be provided.

[0318] The capacitor 790 includes a conductive film which functions as a first gate electrode of the transistor 750. The lower electrode formed through a process of processing the same conductive film and the Through a process of processing the same conductive film as the conductive film that functions as the source electrode and the drain electrode, and an upper electrode formed on the lower electrode. A step of forming an insulating film identical to the insulating film that functions as the first gate insulating film of 750. That is, the capacitor 790 is formed by forming an insulating film between a pair of electrodes. It has a laminated structure in which an insulating film that functions as a conductive film is sandwiched.

[0319] 22 and 24, the transistor 750, the transistor 752, and the capacitor A planarization insulating film 770 is provided on the capacitor 790 .

[0320] The planarization insulating film 770 may be made of a polyimide resin, an acrylic resin, or a polyimide amide resin. Heat-resistant organic materials such as benzocyclobutene resin, polyamide resin, and epoxy resin It should be noted that by stacking multiple insulating films made of these materials, Alternatively, the planarization insulating film 770 may be formed. That's fine.

[0321] 22 and 24, the transistor 750 and the The transistor 752 in the source driver circuit portion 704 has the same structure as the transistor 752 in the source driver circuit portion 704. However, the present invention is not limited to this. For example, the pixel section 702 and the source A transistor different from that of the driver circuit section 704 may be used. 02 is a staggered transistor, and the source driver circuit portion 704 is In the pixel portion 702, an inverted staggered transistor is used. Inverted staggered transistors are used, and the source driver circuit section 704 is provided with staggered transistors. The source driver circuit section 704 may be configured as a gate driver. It may also be read as a driver circuit section.

[0322] The signal line 710 is connected to the source and drain electrodes of the transistors 750 and 752. The signal line 710 is formed through the same process as the conductive film that functions as the signal line 710. When materials containing ZnO are used, signal delays caused by wiring resistance are minimal, making it possible to display on a large screen. It becomes Noh.

[0323] The FPC terminal portion 708 includes a connection electrode 760, an anisotropic conductive film 780, and an FPC 71. 6. The connection electrode 760 is connected to the source and drain electrodes of the transistors 750 and 752. The connection electrode 760 is formed through the same process as the conductive film that functions as the drain electrode. , and is electrically connected to a terminal of the FPC 716 via an anisotropic conductive film 780 .

[0324] The first substrate 701 and the second substrate 705 may be made of, for example, glass. In addition, the first substrate 701 and the second substrate 705 may be flexible substrates. The flexible substrate may be, for example, a plastic substrate. do.

[0325] In addition, a structure 778 is provided between the first substrate 701 and the second substrate 705. The structure 778 is a columnar spacer obtained by selectively etching an insulating film. The distance (cell gap) between the first substrate 701 and the second substrate 705 is controlled. It should be noted that the structures 778 may be spherical spacers.

[0326] On the second substrate 705 side, there is a light-shielding film 738 that functions as a black matrix, A colored film 736 that functions as a color filter, a light-shielding film 738, and a film that contacts the colored film 736 An insulating film 734 is provided.

[0327] <3-2. Configuration example of a display device using a liquid crystal element> The display device 700 shown in FIG. 22 includes a liquid crystal element 775. The liquid crystal element 775 includes a conductive film The conductive film 774 is formed on the second substrate 705. The display device 700 shown in FIG. The alignment state of the liquid crystal layer 776 changes depending on the voltage applied to the conductive film 772 and the conductive film 774. This controls whether light is transmitted or not, allowing images to be displayed.

[0328] The conductive film 772 serves as a source electrode and a drain electrode of the transistor 750. The conductive film 772 is formed over the planarization insulating film 770. The conductive film 772 functions as a pixel electrode, that is, one electrode of a display element. The display device 700 shown in FIG. 72 reflects light and displays it through the colored film 736, so-called reflective color liquid crystal display device. be.

[0329] The conductive film 772 may be a conductive film that transmits visible light or a conductive film that reflects visible light. A conductive film having a light-transmitting property in visible light can be used. For example, a material containing one of the elements selected from indium (In), zinc (Zn), and tin (Sn) As a conductive film that is reflective in visible light, for example, aluminum In this embodiment, the conductive film 772 may be formed using a material containing silver or silver. A conductive film that is reflective in visible light is used.

[0330] 22, the conductive film 772 functions as a drain electrode of the transistor 750. However, the present invention is not limited to this. For example, the structure shown in FIG. As shown in FIG. 1, a conductive film 772 is sandwiched between conductive films 777 serving as connection electrodes. The conductive film may be electrically connected to the drain electrode of the transistor 750. Note that the conductive film 777 functions as a second gate electrode of the transistor 750. Since it is formed through the same process as the conductive film used, there is no need to add any additional manufacturing steps. It can be formed.

[0331] The display device 700 shown in FIG. 22 is a reflective color liquid crystal display device. However, the conductive film 772 is not limited to this. For example, the conductive film 772 may be a conductive film that transmits visible light. Alternatively, a reflective color liquid crystal display device may be used. A so-called semi-transmissive color liquid crystal display is a combination of a transmissive color liquid crystal display and a transmissive color liquid crystal display. It may also be a liquid crystal display device.

[0332] An example of a transmissive color liquid crystal display device is shown in FIG. 25. This is a cross-sectional view taken along the dashed line QR, and shows a configuration in which a liquid crystal element is used as the display element. In addition, the display device 700 shown in FIG. 25 uses a horizontal electric field method (for example, F In the configuration shown in FIG. 25, the pixel electrode functions as a An insulating film 773 is provided over a conductive film 772, and a conductive film 774 is provided over the insulating film 773. In this case, the conductive film 774 functions as a common electrode. An electric field generated between the conductive film 772 and the conductive film 774 through the insulating film 773 causes the liquid The orientation of the crystal layer 776 can be controlled.

[0333] Although not shown in FIGS. 22 and 25, either the conductive film 772 or the conductive film 774 An alignment film is provided on either one or both of the surfaces of the substrate 771 and the liquid crystal layer 776. 22 and 25, a polarizing member, a phase difference member, a reflecting member, etc. may be used. Optical members (optical substrates) such as a polarizing substrate and a positioning member may be provided as appropriate. Circularly polarized light produced by a retardation substrate may also be used. Either may be used.

[0334] When liquid crystal elements are used as display elements, thermotropic liquid crystals, low molecular weight liquid crystals, polymer liquid crystals, The liquid crystals that can be used include polymer dispersed liquid crystals, ferroelectric liquid crystals, and antiferroelectric liquid crystals. Depending on the conditions, the liquid crystal material can be in a cholesteric phase, a smectic phase, a cubic phase, or a chiral phase. It shows nematic phase, isotropic phase, etc.

[0335] In addition, when the in-plane switching method is adopted, a liquid crystal that exhibits a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases, and when the temperature of cholesteric liquid crystal is increased, the cholesteric The blue phase appears just before the transition from the black phase to the isotropic phase. Therefore, in order to improve the temperature range, a liquid crystal composition containing a chiral agent of several weight percent or more is used. The liquid crystal composition containing the liquid crystal exhibiting the blue phase and the chiral agent is used in the liquid crystal layer. Since the liquid crystal display has a short rotational speed and is optically isotropic, no alignment treatment is required. Since the rubbing process is unnecessary, electrostatic damage caused by the rubbing process is eliminated. This can prevent defects and damage to the liquid crystal display device during the manufacturing process. Furthermore, liquid crystal materials exhibiting a blue phase have little viewing angle dependency.

[0336] When a liquid crystal element is used as a display element, a TN (Twisted Nematic) ) mode, IPS (In-Plane-Switching) mode, FFS (Frin ge Field Switching) mode, ASM (Axially Symme tric aligned Micro-cell) mode, OCB(Optical Compensated Birefringence mode, FLC (Ferrero) lectric Liquid Crystal) mode, AFLC (AntiFerr It can be used in dielectric liquid crystal mode. .

[0337] Furthermore, normally black type liquid crystal display devices, such as those employing vertical alignment (VA) mode, The vertical alignment mode may be a transmission type liquid crystal display device. For example, MVA (Multi-Domain Vertical Alignment) ) mode, PVA (Patterned Vertical Alignment) mode Mode, ASV mode, etc. can be used.

[0338] <3-3. Display devices using light-emitting elements> The display device 700 shown in FIG. 24 includes a light-emitting element 782. The light-emitting element 782 is made of a conductive film The display device 700 shown in FIG. The EL layer 786 of the light element 782 emits light, thereby displaying an image. The EL layer 786 includes an organic compound or an inorganic compound such as quantum dots.

[0339] Materials that can be used for the organic compound include fluorescent materials and phosphorescent materials. In addition, materials that can be used for quantum dots include colloidal quantum dots. materials, alloy-type quantum dot materials, core-shell-type quantum dot materials, core-type quantum dot materials, Also, the elements of the 12th and 16th families, the 13th and 15th families, or the 14th and 16th families Materials containing the element group may also be used. Alternatively, cadmium (Cd), selenium (Se), Zinc (Zn), sulfur (S), phosphorus (P), indium (In), tellurium (Te), lead (P b) Quantum atoms with elements such as gallium (Ga), arsenic (As), and aluminum (Al). Dot material may also be used.

[0340] 24. In addition, the display device 700 shown in FIG. An insulating film 730 is provided. The insulating film 730 covers part of the conductive film 772. 782 has a top emission structure. Therefore, the conductive film 788 has a light transmitting property, and It transmits light emitted by the L layer 786. In this embodiment, the top emission The structure is exemplified, but is not limited to, for example, a bottom emission structure in which light is emitted to both the conductive film 772 and the conductive film 788; It can also be applied to al-emission structures.

[0341] A colored film 736 is provided at a position overlapping the light-emitting element 782, and a colored film 736 is provided at a position overlapping the insulating film 730. A light-shielding film 738 is provided in the position where the light-shielding film 738 is to be drawn, the wiring portion 711, and the source driver circuit portion 704. The colored film 736 and the light-shielding film 738 are covered with an insulating film 734. In addition, the space between the light emitting element 782 and the insulating film 734 is filled with a sealing film 732. In the display device 700 shown in FIG. 1, a configuration in which a colored film 736 is provided is exemplified. For example, when the EL layer 786 is formed by coloring, The film 736 may not be provided.

[0342] <3-4. Example of a configuration in which an input / output device is provided in a display device> Furthermore, the display device 700 shown in FIGS. 24 and 25 may be provided with an input / output device. An example of the force device is a touch panel.

[0343] 26 and 27 show a configuration in which a touch panel 791 is provided in the display device 700 shown in FIGS. 24 and 25. and Figure 27.

[0344] FIG. 26 is a cross-sectional view of a configuration in which a touch panel 791 is provided on the display device 700 shown in FIG. 27 is a cross-sectional view of a configuration in which a touch panel 791 is provided on the display device 700 shown in FIG. be.

[0345] First, the touch panel 791 shown in FIGS. 26 and 27 will be described below.

[0346] The touch panel 791 shown in FIGS. 26 and 27 is provided between the substrate 705 and the colored film 736. The touch panel 791 is a so-called in-cell type touch panel. 736 and may be formed on the substrate 705 side before the colored film 736 is formed.

[0347] The touch panel 791 includes a light-shielding film 738, an insulating film 792, an electrode 793, and an electrode 794, an insulating film 795, an electrode 796, and an insulating film 797. When a detection object such as a stylus approaches, the mutual capacitance between electrode 793 and electrode 794 changes. It is possible to detect the change.

[0348] 26 and 27, an electrode 793 and The electrode 796 is formed through an opening in the insulating film 795. 26. The electrode 794 is electrically connected to the two electrodes 793 on either side of the electrode 794 via the electrodes 793. 27 illustrates a configuration in which the region where the electrode 796 is provided is provided in the pixel portion 702. However, the present invention is not limited to this, and may be formed in the source driver circuit section 704, for example.

[0349] The electrodes 793 and 794 are provided in a region overlapping with the light-shielding film 738. As shown in FIG. 1, the electrode 793 is preferably provided so as not to overlap with the light-emitting element 782. 27, the electrode 793 is provided so as not to overlap with the liquid crystal element 775. In other words, the electrode 793 overlaps with the light-emitting element 782 and the liquid crystal element 775. In other words, the electrode 793 has a mesh shape. By configuring the electrode 793 in this manner, the electrode 793 does not block the light emitted from the light emitting element 782. Alternatively, the electrode 793 may have a structure that does not block light that passes through the liquid crystal element 775. Therefore, the reduction in brightness due to the placement of the touch panel 791 is extremely small. Since the number of pixels is small, a display device with high visibility and reduced power consumption can be realized. The pole 794 may have a similar configuration.

[0350] In addition, since the electrodes 793 and 794 do not overlap with the light-emitting element 782, The electrode 794 can be made of a metal material with low transmittance for visible light. Since the electrodes 793 and 794 do not overlap with the liquid crystal element 775, For example, a metal material having low transmittance of visible light can be used.

[0351] Therefore, compared with electrodes using oxide materials with high visible light transmittance, The resistance of the electrode 794 can be reduced, improving the sensor sensitivity of the touch panel. It is possible.

[0352] For example, the electrodes 793, 794, and 796 may be made of conductive nanowires. The nanowires have an average diameter of 1 nm to 100 nm, preferably 5 nm to 50 nm. The size of the nanoparticles may be 5 nm or less, more preferably 5 nm or more and 25 nm or less. The wires may be metal nanowires such as Ag nanowires, Cu nanowires, or Al nanowires. For example, the electrodes 664, 665 may be made of wires or carbon nanotubes. When Ag nanowires are used for either 65 or 667, or both, the The light transmittance is 89% or more, and the sheet resistance is 40Ω / □ or more and 100Ω / □ or less. can.

[0353] 26 and 27 show examples of the configuration of an in-cell type touch panel. For example, a so-called on-cell type transistor formed on the display device 700 may be used. a touch panel or a so-called out-cell type touch panel that is attached to the display device 700 It may also be possible to use the following.

[0354] In this way, the display device of one embodiment of the present invention can be used in combination with various types of touch panels. It can be used.

[0355] Note that the structure described in this embodiment mode may be used in appropriate combination with structures described in other embodiments. It is possible.

[0356] (Fourth embodiment) In this embodiment, a display device including a semiconductor device of one embodiment of the present invention will be described with reference to FIG. This will be used to explain.

[0357] <4. Circuit configuration of display device> The display device shown in FIG. 28(A) has a region having pixels of a display element (hereinafter referred to as a pixel portion 502). ) and a circuit section ( hereinafter referred to as a drive circuit section 504), and a circuit having a function of protecting the element (hereinafter referred to as a protection circuit 50 6) and a terminal portion 507. Note that the protection circuit 506 is not provided. That's fine.

[0358] A part or the whole of the driver circuit portion 504 is formed on the same substrate as the pixel portion 502. This makes it possible to reduce the number of parts and terminals. When a part or all of the pixel portion 502 is not formed on the same substrate, the driving circuit A part or the whole of the path portion 504 is COG or TAB (Tape Automated Bearing). It can be implemented by

[0359] The pixel section 502 is arranged in X rows (X is a natural number of 2 or more) and Y columns (Y is a natural number of 2 or more). The display device has a circuit for driving a plurality of display elements (hereinafter referred to as pixel circuit 501), The path section 504 is a circuit (hereinafter referred to as a gate driver) that outputs a signal (scanning signal) for selecting a pixel. 504a), for supplying signals (data signals) for driving the display elements of the pixels. The source driver 504b includes a driving circuit such as the circuit (hereinafter referred to as a source driver 504b).

[0360] The gate driver 504a includes a shift register and the like. A signal for driving the shift register is inputted through the terminal section 507, and a signal for outputting the shift register is outputted. For example, the gate driver 504a receives a start pulse signal, a clock signal, etc. The gate driver 504a receives a scanning signal and outputs a pulse signal. The gate has a function of controlling the potential of the scanning lines GL_1 to GL_X. A plurality of drivers 504a are provided, and the plurality of gate drivers 504a drive the scanning lines GL_1 to Alternatively, the gate driver 504a may control the GL_X by dividing it into the initialization signal However, the gate driver 50 has a function of supplying 4a may also provide other signals.

[0361] The source driver 504b includes a shift register and the like. Through the terminal section 507, signals for driving the shift register as well as the source of the data signal are transmitted. The source driver 504b receives a signal (image signal) that is to be output from the pixel circuit The source driver 504b has a function of generating a data signal to be written to the source driver 501. A data signal is generated in accordance with a pulse signal obtained by inputting a start pulse, a clock signal, etc. The source driver 504b has a function of controlling the output of a data signal. The data lines DL_1 to DL_Y are connected to the data lines DL_2 through DL_Y. Alternatively, the source driver 504b may have a function of supplying an initialization signal. However, the present invention is not limited to this, and the source driver 504b may also supply other signals. It is possible.

[0362] The source driver 504b is configured using, for example, a plurality of analog switches. The source driver 504b sequentially turns on a plurality of analog switches, The image signal can be time-divided and output as a data signal. The source driver 504b may be configured using the same.

[0363] Each of the plurality of pixel circuits 501 is connected to one of the plurality of scanning lines GL to which a scanning signal is applied. A pulse signal is input via the data line DL, and a data signal is given via one of the data lines DL. Each of the pixel circuits 501 is connected to a gate driver 504a controls writing and holding of data of the data signal. The second pixel circuit 501 is connected to a gate driver GL_m (where m is a natural number equal to or less than X) via a scanning line GL_m. A pulse signal is input from 504a, and the data line DL_n ( A data signal is input from the source driver 504b via the input terminal 504a (n is a natural number equal to or less than Y).

[0364] The protection circuit 506 shown in FIG. 28(A) is, for example, a gate driver 504a and a pixel circuit 5 01. Alternatively, the protection circuit 506 is connected to the scanning line GL, which is the wiring between the source driver The data line DL is connected between the driver 504b and the pixel circuit 501. The protection circuit 506 can be connected to the wiring between the gate driver 504a and the terminal section 507. Alternatively, the protection circuit 506 may be formed by wiring between the source driver 504b and the terminal section 507. The terminal section 507 can be connected to a power supply and a line from an external circuit to the display device. This refers to the part where terminals for inputting control signals and image signals are provided.

[0365] When a potential outside a certain range is applied to the wiring to which the protection circuit 506 is connected, the protection circuit 506 This is a circuit that brings one wire into electrical continuity with another wire.

[0366] As shown in FIG. 28A, a pixel section 502 and a driver circuit section 504 are provided with a protection circuit 50. 6, ESD (Electro Static Discharge: This can improve the resistance of the display device to overcurrents caused by electrostatic discharges and the like. However, the configuration of the protection circuit 506 is not limited to this. For example, A configuration in which a protection circuit 506 is connected, or a configuration in which the protection circuit 506 is connected to the source driver 504b Alternatively, a configuration in which a protection circuit 506 is connected to the terminal portion 507 may be used. It can also be done as follows.

[0367] In FIG. 28(A), the gate driver 504a and the source driver 504b Therefore, although an example in which the driver circuit portion 504 is formed is shown, the present invention is not limited to this configuration. For example, only the gate driver 504a is formed, and a separately prepared source driver circuit is formed. A substrate (for example, a drive circuit substrate formed of a single crystal semiconductor film or a polycrystalline semiconductor film) is implemented. It may also be configured to be equipped with

[0368] Furthermore, the plurality of pixel circuits 501 shown in FIG. 28(A) may be, for example, a configuration shown in FIG. 28(B). It can be said that:

[0369] The pixel circuit 501 shown in FIG. 28B includes a liquid crystal element 570, a transistor 550, and a capacitor. The transistor 550 may be any of the transistors described in the previous embodiments. can be applied.

[0370] The potential of one of the pair of electrodes of the liquid crystal element 570 is set appropriately according to the specifications of the pixel circuit 501. The orientation state of the liquid crystal element 570 is set by the written data. A common potential is applied to one of a pair of electrodes of the liquid crystal element 570 included in each of the pixel circuits 501. In addition, a pair of liquid crystal elements 570 of the pixel circuits 501 in each row may be applied with a common potential. One of the electrodes may be given a different potential.

[0371] For example, the display device including the liquid crystal element 570 can be driven in a TN mode, an STN mode, or the like. Mode, VA mode, ASM (Axially Symmetric Aligned Mode) Micro-cell mode, OCB (Optically Compensated Birefringence mode, FLC (Ferroelectric Liquid Crystal id Crystal) mode, AFLC (AntiFerroelectric Li Quid Crystal) mode, MVA mode, PVA (Patterned Ve Vertical Alignment mode, IPS mode, FFS mode, or TBA (Transverse Bend Alignment) mode may also be used. In addition to the above-mentioned driving method, the display device can also be driven by an ECB (Electric Carrier Board) or the like. Ally Controlled Birefringence mode, PDLC (P Polymer Dispersed Liquid Crystal (PNLC) mode (Polymer Network Liquid Crystal) mode, guest However, there are various types of liquid crystal elements and their driving methods, and they are not limited to these. A variety of materials can be used.

[0372] In the pixel circuit 501 in the mth row and the nth column, the source electrode or the drain electrode of the transistor 550 One of the electrodes is electrically connected to the data line DL_n, and the other is connected to a pair of electrodes of the liquid crystal element 570. The gate electrode of the transistor 550 is electrically connected to the other of the electrodes of the scan line G. L_m. The transistor 550 can be turned on or off. This provides a function of controlling the writing of data signals.

[0373] One of the pair of electrodes of the capacitor 560 is connected to a wiring to which a potential is supplied (hereinafter, a potential supply line VL ) and the other is electrically connected to the other of the pair of electrodes of the liquid crystal element 570. The value of the potential of the potential supply line VL is set appropriately according to the specifications of the pixel circuit 501. The capacitor 560 functions as a storage capacitor for storing written data.

[0374] For example, in a display device having the pixel circuit 501 of FIG. 28(B), The pixel circuits 501 in each row are sequentially selected by the gate driver 504a shown in FIG. 550 is turned on and data of the data signal is written.

[0375] The pixel circuit 501 in which data has been written is turned off by turning off the transistor 550. By repeating this process for each row, an image can be displayed.

[0376] Furthermore, the plurality of pixel circuits 501 shown in FIG. 28(A) may be, for example, a configuration shown in FIG. 28(C). It can be said that:

[0377] The pixel circuit 501 shown in FIG. 28C includes transistors 552 and 554 and a capacitor. The transistor 552 and the transistor 554 The transistor described in the above embodiment can be used for either one or both of the above. .

[0378] One of the source and drain electrodes of the transistor 552 is supplied with a data signal. The transistor 55 is electrically connected to a wiring (hereinafter referred to as a signal line DL_n). The gate electrode 2 is electrically connected to the wiring to which the gate signal is given (hereinafter referred to as the scanning line GL_m). are connected to the network.

[0379] Transistor 552 is turned on or off to transfer the data of the data signal. It has the function of controlling the writing of data.

[0380] One of the pair of electrodes of the capacitor 562 is connected to a wiring to which a potential is applied (hereinafter, a potential supply line VL _a), and the other is electrically connected to the source electrode and drain electrode of the transistor 552. The second electrode is electrically connected to the other of the first and second electrodes.

[0381] The capacitor 562 functions as a storage capacitor for holding written data.

[0382] One of the source electrode and the drain electrode of the transistor 554 is connected to the potential supply line VL_a. Furthermore, the gate electrode of transistor 554 is electrically connected to the It is electrically connected to the other of the source electrode and the drain electrode.

[0383] One of the anode and cathode of the light emitting element 572 is electrically connected to the potential supply line VL_b. The other is electrically connected to the other of the source electrode and drain electrode of the transistor 554. will be done.

[0384] The light emitting element 572 may be, for example, an organic electroluminescence element (also known as an organic EL element). However, the light emitting element 572 is not limited to this. Alternatively, an inorganic EL element made of an inorganic material may be used.

[0385] A high power supply potential VDD is applied to one of the potential supply lines VL_a and VL_b. and the other is supplied with a low power supply potential VSS.

[0386] In a display device having the pixel circuit 501 of FIG. 28(C), for example, The pixel circuits 501 in each row are sequentially selected by the gate driver 504a, and the transistors 552 are turned on. The data signal is written by turning it on.

[0387] The pixel circuit 501 to which the data has been written is turned off by turning off the transistor 552. Furthermore, the transistor 554 is held in a holding state in response to the potential of the written data signal. The amount of current flowing between the source electrode and the drain electrode is controlled, and the light emitting element 572 The light is emitted at a brightness that corresponds to the flow rate. By repeating this process row by row, an image can be displayed.

[0388] Note that the structure described in this embodiment mode may be used in appropriate combination with structures described in other embodiments. It is possible.

[0389] (Embodiment 5) In this embodiment, the transistors described in the above embodiments can be applied to a circuit configuration. An example will be described with reference to FIGS.

[0390] Note that in this embodiment, the transistor including the oxide semiconductor described in the above embodiment In the following description, the OS transistor is referred to as an OS transistor.

[0391] <5. Inverter circuit configuration example> FIG. 29(A) shows a circuit that can be applied to a shift register, a buffer, etc. included in a driver circuit. 8 shows a circuit diagram of an inverter 800 that can convert the logic of a signal applied to an input terminal IN. The inverter 800 outputs an inverted signal to the output terminal OUT. Signal S BG is a signal that can switch the electrical properties of an OS transistor. The number is.

[0392] FIG. 29B shows an example of an inverter 800. The inverter 800 is an OS transistor. The inverter 800 includes an n-channel Since it can be fabricated using only CMOS (Complementary Metal Oxide Semiconductor) transistors, CMOS inverter (CMOS inverter) It can be manufactured at a lower cost than manufacturing a conventional inverter.

[0393] The inverter 800 having OS transistors is made up of Si transistors. The inverter 800 can be placed on the CMOS circuit. Therefore, it is possible to suppress an increase in the circuit area due to the addition of the inverter 800.

[0394] The OS transistors 810 and 820 have a first gate that functions as a front gate and a back gate. The second gate acts as a lock gate and the first gate acts as either a source or a drain. It has one terminal and a second terminal that functions as the other of the source or drain.

[0395] The first gate of OS transistor 810 is connected to the second terminal. The second gate of 10 is the signal S BG The OS transistor 810 is connected to a wiring that supplies The first terminal of the OS transistor 810 is connected to a wiring that supplies a voltage VDD. The terminal is connected to the output terminal OUT.

[0396] A first gate of the OS transistor 820 is connected to the input terminal IN. The second gate of the OS transistor 820 is connected to the input terminal IN. The second terminal of the OS transistor 820 is connected to the output terminal OUT. is connected to the wiring that gives

[0397] FIG. 29C is a timing chart for explaining the operation of the inverter 800. In the timing chart of Figure 29(C), the signal waveform of the input terminal IN and the signal waveform of the output terminal OUT are Signal waveform, signal S BG and the change in the threshold voltage of the OS transistor 810. This shows the following.

[0398] signal S BG to the second gate of the OS transistor 810. The threshold voltage of 810 can be controlled.

[0399] signal S BG is the voltage V for shifting the threshold voltage negatively. BG_A ,threshold Voltage V for shifting the voltage to plus BG_B The second gate has a voltage V BG_A By providing TH_A negative shift to Also, the second gate can be connected to the voltage V BG_B By providing The threshold voltage V TH_B can be shifted positively to

[0400] To visualize the above explanation, Figure 30(A) shows one of the electrical characteristics of a transistor. 1 shows an Id-Vg curve.

[0401] The electrical characteristics of the OS transistor 810 described above are as follows: BG_A of By increasing the value of the curve, the curve is shifted to the curve indicated by the dashed line 840 in FIG. 30(A). The electrical characteristics of the OS transistor 810 can be expressed as follows: Voltage V BG_BBy making it smaller, the curve represented by the solid line 841 in FIG. 30(A) As shown in FIG. 30A, the OS transistor 810 signal S BG voltage V BG_A Or voltage V BG_B By switching like this, The threshold voltage can be shifted positively or negatively.

[0402] The threshold voltage is V TH_B By shifting the OS transistor The capacitor 810 can be set to a state where it is difficult for current to flow. Visualize and show.

[0403] As shown in FIG. 30B, the current I B Extremely small Therefore, when the signal applied to the input terminal IN is high level, the OS When the resistor 820 is in the ON state (ON), it causes the voltage at the output terminal OUT to drop sharply. can be done.

[0404] As shown in FIG. 30B, the current flowing through the OS transistor 810 is difficult. Therefore, the output terminal in the timing chart shown in FIG. The signal waveform 831 can be changed sharply. Since it is possible to reduce the through current flowing between the wiring that supplies S, it is possible to achieve low power consumption. The action can be performed.

[0405] Also, the threshold voltage is V TH_A By shifting it negatively, the OS The transistor 810 can be made to be in a state where a current can easily flow. The state is visualized as shown in Figure 30(C). At this time, the current I A Less At least current I B Therefore, the signal applied to the input terminal IN can be made larger than When the OS transistor 820 is in an OFF state at a low level, the voltage at the output terminal OUT As shown in FIG. 30(C), the OS transistor Since the current flowing through 810 can be made to flow easily, the type shown in FIG. This allows the signal waveform 832 at the output terminal in the timing chart to be changed sharply.

[0406] In addition, signal S BG The control of the threshold voltage of the OS transistor 810 by It is preferable to perform this before the state of register 820 changes, that is, before time T1 or T2. For example, as shown in FIG. 29(C), when the signal given to the input terminal IN is high level, Before the time T1 when the transistor switches to the TH_A From the threshold voltage V TH _B It is preferable to change the threshold voltage of the OS transistor 810. As shown in FIG. 9(C), the signal applied to the input terminal IN is switched to a low level at time T Before 2, the threshold voltage V TH_B to threshold voltage V TH_A OS transistor It is preferable to switch the threshold voltage of 810.

[0407] In the timing chart of FIG. 29(C), the signal changes depending on the signal applied to the input terminal IN. No. S BG However, other configurations may be used. For example, the threshold voltage The control voltage is applied to the second gate of the OS transistor 810 in a floating state. An example of a circuit configuration that can realize this configuration is shown in FIG. Shown in (A).

[0408] 31A, in addition to the circuit configuration shown in FIG. 29B, an OS transistor 850 The first terminal of OS transistor 850 is connected to the second gate of OS transistor 810. The second terminal of the OS transistor 850 is connected to a voltage V BG_B (or electricity Pressure V BG_A The first gate of the OS transistor 850 is connected to a wiring that provides a signal No. S F The second gate of the OS transistor 850 is connected to a line that supplies a voltage V BG _B (or voltage V BG_A ) is connected to the wire that gives

[0409] The operation of FIG. 31(A) will be described using the timing chart of FIG. 31(B).

[0410] The voltage for controlling the threshold voltage of the OS transistor 810 is applied to the input terminal IN. Before time T3 when the signal connected to the second gate of OS transistor 810 is switched to a high level, The signal S F is set to a high level to turn on the OS transistor 850. In this state, node N BG Voltage V to control the threshold voltage BG_B Give.

[0411] Node N BG is the voltage V BG_B After this, the OS transistor 850 is turned off. The OS transistor 850 has an extremely small off-state current and can be kept in an off state. So, once node N BG The threshold voltage V BG_B It is possible to maintain Therefore, the second gate of the OS transistor 850 is supplied with a voltage V BG_B The number of actions that give Therefore, the voltage V BG_B Therefore, the power consumption required for rewriting the data can be reduced.

[0412] In the circuit configurations of FIGS. 29B and 31A, the second We have shown a configuration in which the voltage applied to the gate is controlled externally, but we will also consider other configurations. For example, a voltage for controlling the threshold voltage may be applied to the input terminal IN. and may be provided to the second gate of the OS transistor 810. An example of a circuit configuration that can realize this configuration is shown in FIG.

[0413] In FIG. 32(A), the input terminal IN and the OS transistor are connected in the circuit configuration shown in FIG. 29(B). A CMOS inverter 860 is provided between the second gate of the transistor 810 and the CMOS inverter 860. The input terminal of the CMOS inverter 860 is connected to the input terminal IN. The output terminal is connected to the second gate of OS transistor 810 .

[0414] The operation of FIG. 32(A) will be explained using the timing chart of FIG. 32(B). In the timing chart of Figure 32(B), the signal waveform of the input terminal IN and the signal waveform of the output terminal OUT are 8, the output waveform IN_B of the CMOS inverter 860, and the output waveform IN_B of the OS transistor 810. The change in threshold voltage is shown.

[0415] The output waveform IN_B, which is the inverted signal of the signal applied to the input terminal IN, is This signal can be used to control the threshold voltage of the transistor 810. As described in FIGS. 30A to 30C, the threshold voltage of the OS transistor 810 is controlled. For example, at time T4 in FIG. 32(B), the signal applied to the input terminal IN is When the signal is at a high level, the OS transistor 820 is turned on. B is at a low level. Therefore, the OS transistor 810 is in a state where it is difficult for current to flow. This allows the voltage at the output terminal OUT to drop sharply from a rising state.

[0416] At time T5 in FIG. 32(B), the signal applied to the input terminal IN becomes low level. At this time, the OS transistor 820 is turned off. Therefore, the OS transistor 810 can be made to be in a state where current easily flows. This allows the voltage at the output terminal OUT to rise sharply.

[0417] As described above, in the configuration of this embodiment, the inverter having the OS transistor The back gate voltage is switched according to the logic of the signal at the input terminal IN. By using this configuration, the threshold voltage of the OS transistor can be controlled. The threshold voltage of the OS transistor is controlled by the signal given to IN. The OUT voltage can be changed sharply. This allows for a reduction in current, thereby enabling lower power consumption.

[0418] Note that the structure described in this embodiment mode may be used in appropriate combination with structures described in other embodiments. It is possible.

[0419] (Sixth embodiment) In this embodiment, the transistor including the oxide semiconductor described in the above embodiment ( An example of a semiconductor device using an OS transistor in a plurality of circuits is shown in FIGS. 6 will be used to explain.

[0420] <6. Circuit configuration example of semiconductor device> 33A is a block diagram of a semiconductor device 900. The semiconductor device 900 is A circuit 901, a circuit 902, a voltage generating circuit 903, a circuit 904, a voltage generating circuit 905, and a circuit It has a path 906.

[0421] The power supply circuit 901 supplies a reference voltage V ORG This is a circuit that generates a voltage V ORG teeth, Instead of a single voltage, multiple voltages may be used. Voltage V ORG is external to the semiconductor device 900. The semiconductor device 900 can generate the voltage V based on the voltage V0 given from the external The voltage V ORG Therefore, the semiconductor device 900 can generate It can operate without applying multiple power supply voltages from the outside.

[0422] The circuits 902, 904, and 906 are circuits that operate on different power supply voltages. The power supply voltage of the circuit 902 is V ORG and voltage V SS (V ORG >V SS ) and applied by For example, the power supply voltage of the circuit 904 is a voltage V POG and voltage V SS ( V POG >V ORG ) and the voltage applied by the power supply of the circuit 906. The voltage is V ORGand voltage V NEG (V ORG >V SS >V NEG ) and applied by The voltage V SS is the same potential as the ground (GND), the power supply circuit The number of types of voltages generated by 901 can be reduced.

[0423] The voltage generating circuit 903 generates a voltage V POG The voltage generating circuit 903 is a circuit that generates The voltage V given by the power supply circuit 901 ORG Based on the voltage V POG can be generated. The semiconductor device 900 having the circuit 904 operates based on a single power supply voltage applied from the outside. It can be made.

[0424] The voltage generating circuit 905 generates a voltage V NEG The voltage generating circuit 905 is a circuit that generates The voltage V given by the power supply circuit 901 ORG Based on the voltage V NEG can be generated. The semiconductor device 900 having the circuit 906 operates based on a single power supply voltage applied from the outside. It can be made.

[0425] Figure 33(B) shows the voltage V POG 33C shows an example of a circuit 904 that operates in the 10 is an example of a waveform of a signal for operating the

[0426] FIG. 33B shows a transistor 911. The applied signal is, for example, a voltage V POG and voltage V SS The signal is generated based on the When transistor 911 is in the conducting state, the voltage V POG , the voltage when operating in a non-conducting state VSS Voltage V POG As shown in Figure 33(C), the voltage V ORG Bigger Therefore, the transistor 911 is in a conductive state between the source (S) and the drain (D). As a result, the circuit 904 can operate more reliably. The circuit can be made as follows.

[0427] Figure 33(D) shows the voltage V NEG FIG. 33(E) shows an example of a circuit 906 that operates in the 10 is an example of a waveform of a signal for operating the

[0428] FIG. 33D shows a transistor 912 having a back gate. The signal applied to the gate of the gate electrode 912 is, for example, a voltage V ORG and voltage V SS Generated based on This signal is applied to the transistor 911 at the time of turning on the transistor 911. ORG , non-guided When the voltage V SS Also, the back gate of the transistor 912 is The voltage that can be applied is V NEG It is generated based on the voltage V NEG is illustrated in FIG. So, the voltage V SS (GND). Therefore, the threshold voltage of transistor 912 is Therefore, the transistor 912 can be controlled to shift in a positive direction. It can be reliably put into a non-conducting state, and the current flowing between the source (S) and the drain (D) As a result, the circuit 906 can reduce malfunctions and achieve low power consumption. The circuit can be made as follows.

[0429] In addition, the voltage V NEGcan also be applied directly to the back gate of the transistor 912. Alternatively, the voltage V ORG and voltage V NEG Based on this, a voltage is applied to the gate of the transistor 912. Alternatively, a signal that corresponds to the voltage Vref may be generated and applied to the back gate of the transistor 912. good.

[0430] Also, FIGS. 34(A) and (B) show modified examples of FIGS. 33(D) and (E).

[0431] In the circuit diagram shown in FIG. 34(A), a control circuit is provided between the voltage generating circuit 905 and the circuit 906. The transistor 922 has a conduction state that can be controlled by a path 921. is an n-channel OS transistor. BG is a signal that controls the conduction state of the transistor 922. Transistors 912A and 912B are OS transistors like transistor 922.

[0432] In the timing chart of FIG. 34(B), the control signal S BG and transistor 912A, The state of the potential of the back gate of 912B is BG The control signal S B G When the voltage at the node N BG is the voltage V N EG Then, the control signal S BG When is low, node N BG is electrically flow Since the transistor 922 is an OS transistor, its off-state current is low. Therefore, node N BG Even if the voltage V is electrically floating, NEG can be held.

[0433] FIG. 35A shows an example of a circuit configuration applicable to the voltage generating circuit 903 described above. The voltage generating circuit 903 shown in FIG. 35A includes diodes D1 to D5, a capacitor The five-stage charge pump includes C1 to C5 and an inverter INV. The signal CLK is applied to the capacitors C1 to C5 either directly or through an inverter INV. The power supply voltage of the inverter INV is V ORG and voltage V SS and is applied by voltage V ORG is boosted to a positive voltage five times higher than the The voltage V POG The forward voltage of the diodes D1 to D5 is 0V. In addition, by changing the number of stages in the charge pump, the desired voltage V POG get It is possible.

[0434] FIG. 35B shows an example of a circuit configuration applicable to the voltage generating circuit 905. The voltage generating circuit 905 shown in FIG. 35B includes diodes D1 to D5, a capacitor The four-stage charge pump includes C1 to C5 and an inverter INV. The signal CLK is applied to the capacitors C1 to C5 either directly or through an inverter INV. The power supply voltage of the inverter INV is V ORG and voltage V SS and is applied by If the voltage is a clock signal, CLK will cause the SS Electric power Pressure V ORG The voltage V is stepped down to a negative voltage four times that of NEGIt can be obtained. The forward voltage of the nodes D1 to D5 is set to 0 V. In addition, the number of stages of the charge pump is changed. This allows the desired voltage V NEG can be obtained.

[0435] The circuit configuration of the voltage generating circuit 903 described above is the same as the circuit configuration shown in FIG. For example, modified examples of the voltage generating circuit 903 are shown in FIGS. The voltage generating circuit 903 may be modified as shown in FIGS. In the circuits 903A to 903C, the voltage applied to each wiring may be changed, or the elements This can be achieved by changing the arrangement of the

[0436] The voltage generating circuit 903A shown in FIG. 36A includes transistors M1 to M10, a capacitor The clock signal CLK is supplied to the inverters C11 to C14 and the inverter INV1. The voltage Vcc is applied directly to the gates of the transistors M1 to M10 or via an inverter INV1. The clock signal CLK generates a voltage V ORG The voltage V is boosted to a positive voltage four times higher than the PO G By changing the number of stages, the desired voltage V POG to get The voltage generating circuit 903A shown in FIG. 36A uses transistors M1 to M10 as By using S transistors, the off-state current can be reduced, and the capacitors C11 to C14 Therefore, the leakage of the charge can be suppressed efficiently. ORG to voltage V POG Ascension to Pressure can be measured.

[0437] The voltage generating circuit 903B shown in FIG. 36B includes transistors M11 to M14, The clock signal CLK is generated by the capacitors C15 and C16 and the inverter INV2. , directly to the gates of transistors M11 to M14 or via inverter INV2 The clock signal CLK generates a voltage V ORG The voltage boosted to twice the positive voltage Pressure V POG The voltage generating circuit 903B shown in FIG. By using OS transistors as the transistors M11 to M14, the off-state current can be reduced. This can suppress leakage of the charge held in the capacitors C15 and C16. ORG to voltage V POG It is possible to boost the voltage to

[0438] Also, the voltage generating circuit 903C shown in FIG. 36(C) includes an inductor Ind1, a transistor The transistor M15 has a diode D6 and a capacitor C17. The conduction state is controlled by the control signal EN. ORG but The boosted voltage V POG The voltage generating circuit 903C shown in FIG. Since the inductor Ind1 is used to boost the voltage, the voltage is boosted with high conversion efficiency. It is possible to do so.

[0439] As described above, in the configuration of this embodiment, the voltage required for the circuit of the semiconductor device is Therefore, the semiconductor device can reduce the number of power supply voltages that need to be applied externally. It can be reduced.

[0440] Note that the structure shown in this embodiment mode may be used in appropriate combination with structures shown in other embodiment modes. You can be there.

[0441] (Embodiment 7) In this embodiment, a display module and an electronic device including a semiconductor device according to one embodiment of the present invention will be described. This will be explained using FIGS. 37 to 40.

[0442] <7-1. Display module> The display module 7000 shown in FIG. 37 includes an upper cover 7001 and a lower cover 7002. Between them, touch panel 7004 connected to FPC7003 and A display panel 7006, a backlight 7007, a frame 7009, a printed circuit board 701 0, has battery 7011.

[0443] The semiconductor device of one embodiment of the present invention can be used for the display panel 7006, for example.

[0444] The upper cover 7001 and the lower cover 7002 are connected to the touch panel 7004 and the display panel The shape and dimensions can be changed as needed to fit the size of the 7006.

[0445] The touch panel 7004 is a resistive or capacitive touch panel. The display panel 7006 can be used by overlapping it with the opposing substrate (sealing substrate) of the display panel 7006. It is also possible to provide the display panel 7 with a touch panel function. It is also possible to provide an optical sensor in each pixel of 006 to make it an optical touch panel.

[0446] The backlight 7007 has a light source 7008. In FIG. Although the configuration in which the light source 7008 is disposed on the base 7007 has been described as an example, the present invention is not limited to this. For example, a light source 7008 is arranged at the end of a backlight 7007, and a light diffusion plate is further used. In addition, when a self-luminous light emitting element such as an organic EL element is used, or when a reflective In the case of a flat panel or the like, the backlight 7007 may not be provided.

[0447] The frame 7009 not only protects the display panel 7006 but also prevents the movement of the printed circuit board 7010. It also functions as an electromagnetic shield to block electromagnetic waves generated by the operation of the The frame 7009 may also function as a heat sink.

[0448] The printed circuit board 7010 includes a power supply circuit, a signal circuit for outputting a video signal and a clock signal. The power supply circuit is provided with a signal processing circuit. Alternatively, the power source may be a battery 7011 provided separately. This can be omitted if a commercial power source is used.

[0449] The display module 7000 also includes components such as a polarizing plate, a retardation plate, and a prism sheet. It may also be provided in addition.

[0450] <7-2.Electronic equipment 1> Next, examples of electronic devices are shown in FIGS. 38(A) to 38(E).

[0451] FIG. 38(A) shows the appearance of the camera 8000 with the viewfinder 8100 attached. This is a diagram.

[0452] The camera 8000 includes a housing 8001, a display unit 8002, operation buttons 8003, and a shutter. The camera 8000 has a button 8004 and the like. The camera 8000 also has a detachable lens 8006. It is attached.

[0453] Here, the camera 8000 is assumed to have a lens 8006 that is detached from the housing 8001 and replaced. However, the lens 8006 and the housing may be integrated.

[0454] The camera 8000 can capture an image by pressing the shutter button 8004. The display unit 8002 also functions as a touch panel. It is also possible to take an image by

[0455] The housing 8001 of the camera 8000 has a mount with electrodes, and a finder 810 In addition to the 0, strobe devices etc. can also be connected.

[0456] The finder 8100 includes a housing 8101, a display unit 8102, buttons 8103, etc. .

[0457] The housing 8101 has a mount that engages with the mount of the camera 8000, The mount can be attached to the camera 8000. The image received from the camera 8000 through the electrode is displayed on the display unit 8102. It can be done.

[0458] The button 8103 functions as a power button. The 8102 display can be switched on and off.

[0459] The display unit 8002 of the camera 8000 and the display unit 8102 of the viewfinder 8100 are The display device according to one embodiment of the present invention can be applied.

[0460] In FIG. 38(A), the camera 8000 and the finder 8100 are separate electronic devices. These are configured to be detachable, but the housing 8001 of the camera 8000 is equipped with a display device. The camera may have a built-in viewfinder.

[0461] FIG. 38B is a diagram showing the appearance of the head mounted display 8200.

[0462] The head-mounted display 8200 includes a mounting part 8201, a lens 8202, and a main body 82 8203, a display unit 8204, a cable 8205, etc. It has a built-in 8206 battery.

[0463] A cable 8205 supplies power from a battery 8206 to the main body 8203. 03 is equipped with a wireless receiver and the like, and image information such as received image data is displayed on a display unit 8204. In addition, the camera installed in the main body 8203 can record the movements of the user's eyeballs and eyelids. By capturing the user's viewpoint and calculating the coordinates of the user's viewpoint based on that information, It can be used as an input means.

[0464] Furthermore, the wearing unit 8201 may be provided with a plurality of electrodes at positions that come into contact with the user. The main body 8203 detects the current flowing through the electrodes in accordance with the movement of the user's eyeballs, The device may have a function to recognize the user's point of view. By doing so, the attachment unit 820 may have a function of monitoring the pulse of the user. The sensor 1 may have various sensors such as a temperature sensor, a pressure sensor, an acceleration sensor, etc. The device may have a function to display the user's biological information on the display unit 8204. The image displayed on the display unit 8204 is changed according to the movement of the part. Good too.

[0465] The display device of one embodiment of the present invention can be applied to the display portion 8204.

[0466] 38(C), (D), and (E) are diagrams showing the appearance of the head-mounted display 8300. The head mounted display 8300 includes a housing 8301, a display portion 8302, and a backlight. The lens 8302 has a braided fixture 8304 and a pair of lenses 8305 .

[0467] A user can view the display on the display unit 8302 through the lens 8305 . It is preferable to arrange the display portion 8302 in a curved state. By doing so, the user can feel a high sense of realism. Although the configuration in which one display unit 8302 is provided has been illustrated, the present invention is not limited to this. For example, In this case, one display is provided for each eye of the user. If the configuration is such that the display section is arranged, it will be possible to perform 3D display using parallax. .

[0468] Note that the display device of one embodiment of the present invention can be applied to the display portion 8302. A display device including the semiconductor device of one embodiment of this invention has extremely high definition. Even if the image is enlarged using the lens 8305, the pixels are not visible to the user, and the image is displayed more clearly. This makes it possible to display images with a higher sense of reality.

[0469] <7-3.Electronic equipment 2> Next, an example of an electronic device different from the electronic devices shown in FIGS. 38(A) to 38(E) will be described with reference to FIG. 9(A) to 39(G).

[0470] The electronic devices shown in FIGS. 39A to 39G include a housing 9000, a display portion 9001, a screen Speaker 9003, operation keys 9005 (including a power switch or an operation switch), connection terminal Child 9006, sensor 9007 (force, displacement, position, velocity, acceleration, angular velocity, number of rotations, distance, Light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, (including functions to measure flow rate, humidity, gradient, vibration, odor or infrared rays), It has 9008, etc.

[0471] The electronic devices shown in FIGS. 39A to 39G have various functions. Function to display various information (still images, videos, text images, etc.) on the display, touch panel function , calendar, date or time display functions, various software (programs) a function for controlling processing by wireless communication, a function for controlling various computers by wireless communication, Functions for connecting to a network and transmitting or receiving various data using wireless communication functions The function of reading out the program or data recorded on the recording medium and displaying it on the display unit. The electronic devices shown in FIGS. The functions that can be possessed by the device are not limited to these, and the device can have a variety of functions. Although not shown in FIGS. 39(A) to 39(G), the electronic device may have a plurality of display units. The electronic device may be provided with a camera or the like to take still images. , the function to shoot videos, and save the captured images to a recording medium (external or built-in to the camera) The image capturing device may have a function of capturing an image, a function of displaying a captured image on a display unit, and the like.

[0472] The electronic devices shown in FIGS. 39(A) to 39(G) will be described in detail below.

[0473] FIG. 39(A) is a perspective view showing a television device 9100. 100 is a display unit 9001 having a large screen, for example, 50 inches or more, or 100 inches or more. It is possible to incorporate a display unit 9001 such as the one shown in FIG.

[0474] 39(B) is a perspective view showing a portable information terminal 9101. For example, the device has one or more functions selected from a telephone, a notebook, an information viewing device, etc. Specifically, it can be used as a smartphone. A speaker 9003, a connection terminal 9006, a sensor 9007, etc. may be provided. The information terminal 9101 can display text and image information on multiple screens. Two operation buttons 9050 (also called operation icons or simply icons) are provided on the display unit 9001. In addition, information 9051 shown in a dashed rectangle can be displayed on one side of the display unit 900. 1. An example of the information 9051 is an email or Displays to notify you of incoming calls and SNS (social networking services), Subject of email or SNS, sender name of email or SNS, date and time, time, The remaining battery power, antenna reception strength, etc. Or, information 9051 is displayed. In place of the information 9051, operation buttons 9050 or the like may be displayed.

[0475] 39(C) is a perspective view showing a portable information terminal 9102. The portable information terminal 9102 is , and has the function of displaying information on three or more surfaces of the display unit 9001. An example is shown in which information 9053 and information 9054 are displayed on different sides. The user of the portable information terminal 9102 stores the portable information terminal 9102 in the breast pocket of his / her clothes. In this state, the display (information 9053 in this case) can be confirmed. The telephone number or name of the caller is displayed in a position that can be observed from above the mobile information terminal 9102. The user can view the display without taking the mobile information terminal 9102 out of his pocket. You can check the call and decide whether to accept it or not.

[0476] 39(D) is a perspective view showing a wristwatch-type portable information terminal 9200. The 9200 is suitable for mobile phone calls, e-mail, document browsing and writing, music playback, and internet communications. It is possible to run various applications such as computer games. The display surface of the display unit 9001 is curved, and the display is performed along the curved display surface. In addition, the portable information terminal 9200 can perform short-distance wireless communication according to a communication standard. For example, by communicating with a wireless headset, handset The mobile information terminal 9200 also has a connection terminal 9006. It has a connector and can directly exchange data with other information terminals. Charging can also be performed via the connection terminal 9006. It may also be possible to supply power wirelessly without going through 6.

[0477] 39(E), (F), and (G) are perspective views showing a foldable portable information terminal 9201. FIG. 39(E) is a perspective view of the portable information terminal 9201 in an unfolded state, and FIG. (F) shows the mobile information terminal 9201 being changed from one of the unfolded state and the folded state to the other. 39(G) is a perspective view of the portable information terminal 9201 in a folded state. The portable information terminal 9201 is highly portable when folded, and is easily portable when unfolded. When the display is turned on, the seamless, wide display area provides excellent visibility of the display. The display unit 9001 of the display device 01 is made up of three housings 9000 connected by hinges 9055. The two housings 9000 are supported by the hinge 9055. This allows the portable information terminal 9201 to be reversibly transformed from an unfolded state to a folded state. For example, the portable information terminal 9201 can be bent with a radius of curvature of 1 mm or more and 150 mm or less. It can be done.

[0478] Next, the electronic devices shown in FIGS. 38(A) to 38(E) and the electronic devices shown in FIGS. 39(A) to 39(E) will be described. An example of an electronic device different from the electronic device shown in (G) is shown in Figures 40(A) and (B). (B) is a perspective view of a display device having a plurality of display panels. FIG. 40(B) is a perspective view of a state in which a plurality of display panels are rolled up. FIG. 1 is a perspective view of the roll in an unfolded state.

[0479] The display device 9500 shown in FIGS. 40(A) and 40(B) includes a plurality of display panels 9501 and a shaft portion 9 511 and a bearing portion 9512. The plurality of display panels 9501 have a display area 9502 and a light-transmitting region 9503.

[0480] The display panels 9501 are flexible. The filters 9501 are arranged so that they partially overlap each other. The light-transmitting region 9503 of the display panel 9501 can be overlapped. By using the display panel 9501, a large screen display device can be provided. The display panel 9501 can be rolled up depending on the situation, making it a versatile display. It can be a display device.

[0481] 40(A) and 40(B), the display area 9502 is located on the adjacent display panel 950. 1 shows a state in which the display panels are spaced apart, but this is not limited to this. For example, the display panels 9 By overlapping the display areas 9502 of the 501 without any gaps, a continuous display area 9502 is created. You may do so.

[0482] The electronic device described in this embodiment has a display unit for displaying some information. However, the semiconductor device of one embodiment of the present invention is an electronic device that does not have a display portion. It can also be applied to vessels.

[0483] Note that the structure described in this embodiment mode may be used in appropriate combination with structures described in other embodiments. It is possible. [Explanation of symbols]

[0484] 100 transistors 100A transistor 100B transistor 100C transistor 100D transistor 100E transistor 102 Circuit Board 104 Conductive film 106 insulating film 107 Insulating film 108 Oxide semiconductor film 108a Oxide semiconductor film 108b Oxide semiconductor film 108b_0 Oxide semiconductor film 108c Oxide semiconductor film 108c_ Oxide semiconductor film 108c_0 Oxide semiconductor film 112_1 Conductive film 112_2 Conductive film 112_3 Conductive film 112a Conductive film 112a_1 Metal film 112a_2 Metal film 112a_3 Metal film 112b Conductive film 112b_ Conductive film 112b_1 Metal film 112b_2 Metal film 112b_3 Metal film 112c conductive film 112c_1 Metal film 112c_2 Metal film 112c_3 Metal film 114 insulating film 115 insulating film 116 Insulating film 118 insulating film 120_1 Oxide conductive film 120_2 Metal Film 120a Conductive film 120a_1 Oxide conductive film 120a_2 Metal film 120b Conductive film 120b_1 Oxide conductive film 120b_2 Metal film 141a Mask 141b Mask 141c Mask 142a Mask 142b Mask 142c Mask 151 Opening 152a opening 152b opening 191 Target 192 Plasma 193 Target 194 Plasma 501 pixel circuit 502 pixel section 504 Drive circuit section 504a Gate Driver 504b source driver 506 Protection circuit 507 Terminal section 550 transistors 552 transistor 554 Transistor 560 Capacitor 562 Capacitor 570 Liquid Crystal Devices 572 Light-emitting element 664 Electrode 665 Electrode 667 Electrode 700 Display device 701 PCB 702 pixel section 704 Source driver circuit section 705 PCB 706 Gate driver circuit section 708 FPC terminal section 710 Signal Line 711 Wiring section 712 Sealing material 716 FPC 730 insulating film 732 Sealing film 734 Insulating Film 736 Colored film 738 Light-shielding film 750 transistors 752 transistors 760 connecting electrode 770 Planarization insulating film 772 Conductive film 773 insulating film 774 Conductive film 775 Liquid Crystal Elements 776 Liquid Crystal Layer 777 Conductive Film 778 Structure 780 Anisotropic Conductive Film 782 Light-emitting element 786 EL layer 788 Conductive Film 790 Capacitor 791 Touch Panel 792 insulating film 793 Electrode 794 Electrode 795 insulating film 796 Electrode 797 Insulating Film 800 inverter 810 OS transistor 820 OS transistor 831 Signal Waveform 832 signal waveform 840 dashed line 841 solid line 850 OS transistor 860 CMOS inverter 900 Semiconductor device 901 Power supply circuit 902 circuits 903 Voltage Generation Circuit 903A Voltage Generation Circuit 903B Voltage Generator Circuit 903C Voltage Generation Circuit 904 circuits 905 Voltage Generation Circuit 906 Circuit 911 Transistor 912 Transistor 912A Transistor 912B transistor 921 Control circuit 922 Transistor 7000 Display Module 7001 Top cover 7002 Lower cover 7003 FPC 7004 Touch Panel 7005 FPC 7006 Display Panel 7007 Backlight 7008 Light source 7009 Frame 7010 Printed Circuit Board 7011 Battery 8000 Camera 8001 Case 8002 Display section 8003 Operation button 8004 Shutter button 8006 Lens 8100 Finder 8101 Housing 8102 Display section 8103 Button 8200 Head Mounted Display 8201 Mounting part 8202 Lens 8203 Main unit 8204 Display section 8205 Cable 8206 Battery 8300 Head Mounted Display 8301 Housing 8302 Display section 8304 Fixtures 8305 Lens 9000 chassis 9001 Display section 9003 Speaker 9005 Operation key 9006 Connection terminal 9007 Sensor 9008 Microphone 9050 Operation button 9051 Information 9052 Information 9053 Information 9054 Information 9055 Hinge 9100 Television equipment 9101 Mobile Information Terminal 9102 Mobile Information Terminal 9200 Mobile Information Terminal 9201 Mobile Information Terminal 9500 display device 9501 Display Panel 9502 Display area 9503 area 9511 Shaft 9512 Bearing section

Claims

1. a first conductive film having a function as a gate electrode; a first insulating film having a region located above the first conductive film and functioning as a gate insulating film; an oxide semiconductor film having a region located above the first insulating film and having a channel formation region; a second insulating film having a region located above the oxide semiconductor film; a second conductive film having a region in contact with an upper surface of the second insulating film and functioning as a source electrode or a drain electrode; a third conductive film having a region in contact with an upper surface of the second insulating film; a third insulating film having a region located above the second conductive film; a fourth conductive film having a region located above the third insulating film, the fourth conductive film is always electrically connected to the first conductive film via the third conductive film; A semiconductor device, wherein a region where the fourth conductive film and the third conductive film are in contact with each other has a region that overlaps a region where the third conductive film and the first conductive film are in contact with each other.

2. a first conductive film having a function as a gate electrode; a first insulating film having a region located above the first conductive film and functioning as a gate insulating film; an oxide semiconductor film having a region located above the first insulating film and having a channel formation region; a second insulating film having a region located above the oxide semiconductor film; a second conductive film having a region in contact with an upper surface of the second insulating film and functioning as a source electrode or a drain electrode; a third conductive film having a region in contact with an upper surface of the second insulating film; a third insulating film having a region located above the second conductive film; a fourth conductive film having a region located above the third insulating film, the fourth conductive film has a region overlapping with the oxide semiconductor film, the fourth conductive film is always electrically connected to the first conductive film via the third conductive film; A semiconductor device, wherein a region where the fourth conductive film and the third conductive film are in contact with each other has a region that overlaps a region where the third conductive film and the first conductive film are in contact with each other.

Images