Image forming device

Abstract

To suppress a positional deviation of an image and deterioration of image quality caused by a positional deviation of an exposure device.SOLUTION: An image forming device (1) includes: a photoreceptor (102); an exposure head (106) which has a plurality of light-emitting elements (602) and exposes the photoreceptor (102) by the plurality of light-emitting elements to form an image; and an image controller (700) which transmits, to the exposure head (106), binary image data configured to include a plurality of lines of data indicating one line of an image in a main scanning direction in a sub-scanning direction so that the exposure head (106) forms, on the photoreceptor (102), an image corresponding to the binary image data. The image controller (700) divides one line in the main scanning direction into a plurality of segments, and corrects a deviation for each segment on the basis of information representing a deviation of an exposure position of the photoreceptor (102) by the exposure head (106).SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] The present invention relates to an image forming apparatus equipped with an exposure device having a plurality of light-emitting elements. [Background technology]

[0002] An electrophotographic image forming apparatus forms an image by exposing a rotating photosensitive member to light and forming an electrostatic latent image, which is then developed with toner. Patent Document 1 discloses an image forming apparatus that exposes a photosensitive member using an exposure device having a plurality of light-emitting chips, each of which has a plurality of light-emitting elements arranged in a plane. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2021-35765 Summary of the Invention [Problem to be solved by the invention]

[0004] The positioning of the exposure device may deviate from the ideal position relative to the photosensitive member. Such misalignment can result in misalignment of the image and degradation of image quality. Misalignment can occur due to, for example, an assembly error that causes the exposure device to deviate from the ideal assembly position when assembled into the main body of the image forming apparatus, or deformation of the substrate itself on which the light-emitting chip is mounted.

[0005] SUMMARY OF THE INVENTION In view of the above-mentioned problems, it is a primary object of the present invention to provide an image forming apparatus that suppresses image misalignment and degradation in image quality caused by misalignment of an exposure device. [Means for solving the problem]

[0006] The image forming apparatus of the present invention comprises a photosensitive member, an exposure means having a plurality of light-emitting elements and exposing the photosensitive member to the plurality of light-emitting elements to form an image, and a control means for transmitting image data to the exposure means that includes data representing an image of one line in a first direction and includes a plurality of lines in a second direction perpendicular to the first direction, and for forming an image on the photosensitive member according to the image data by the exposure means, wherein the control means divides one line in the first direction into a plurality of segments, and for each segment, corrects the deviation based on information representing the deviation of the exposure position of the photosensitive member by the exposure means, and transmits the image data to the exposure means. [Effects of the Invention]

[0007] According to the present invention, it is possible to suppress image misalignment and degradation of image quality caused by misalignment of an exposure device. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a diagram illustrating the configuration of an image forming apparatus. [Figure 2] 1A and 1B are explanatory diagrams of a photosensitive member and an exposure head. [Figure 3] (a) and (b) are explanatory diagrams of a printed circuit board. [Figure 4] FIG. [Figure 5] FIG. [Figure 6] Cross section AA of Figure 5. [Figure 7] FIG. 3 is a diagram illustrating the configuration of an image controller. [Figure 8] 10 is a timing chart for writing control data. [Figure 9] 10 is a timing chart for transmitting print image data. [Figure 10] Detailed functional diagram of one light-emitting chip. [Figure 11] FIG. [Figure 12] 5A and 5B are explanatory diagrams of output control by a light emission control unit. [Figure 13]5A and 5B are explanatory diagrams of output control by a light emission control unit. [Figure 14] FIG. 4 is an explanatory diagram of output control of a light emission control unit. [Figure 15] FIG. 2 is a diagram illustrating the configuration of an image data processing unit. [Figure 16] Detailed block diagram of the DMA controller. [Figure 17] FIG. [Figure 18] A partial enlarged view of the scanning line. [Figure 19] An explanatory diagram of the operation of the DMA controller. [Figure 20] 1 is a flowchart showing the operation of a DMA controller. [Figure 21] 10A and 10B are diagrams illustrating the effect of misregistration correction. [Figure 22] 10A and 10B are diagrams illustrating the effect of misregistration correction. DETAILED DESCRIPTION OF THE INVENTION

[0009] Preferred embodiments of the present invention will be described below with reference to the accompanying drawings. Note that the following embodiments do not limit the scope of the invention claimed. Although multiple features are described in the embodiments, not all of these multiple features are necessarily essential to the invention, and multiple features may be combined arbitrarily. Furthermore, in the accompanying drawings, the same reference numerals are used to designate the same or similar components, and redundant explanations will be omitted.

[0010] (Image forming device) 1 is a diagram showing the configuration of an image forming apparatus according to this embodiment. Image forming apparatus 1 includes a reading unit 100, an image creating unit 103, a fixing unit 104, and a conveying unit 105. Reading unit 100 optically reads an original placed on a platen to generate read image data. Image creating unit 103 forms an image on a sheet based on the read image data generated by reading unit 100 or print image data acquired from an external device via a network. Such image forming apparatus 1 may be realized by, for example, a copier, a multifunction peripheral, or an MFP (Multi Function Peripheral).

[0011] The image forming unit 103 has multiple image forming units 101a, 101b, 101c, and 101d, a transfer belt 111 that transports sheets, and an optical sensor 113. The image forming units 101a, 101b, 101c, and 101d are used to form toner images of black (K), yellow (Y), magenta (M), and cyan (C), respectively. The image forming units 101a, 101b, 101c, and 101d have the same configuration, and will hereinafter be collectively referred to as image forming unit 101.

[0012] The image forming unit 101 includes a photoconductor 102, a charger 107, an exposure head 106, and a developing unit 108. The photoconductor 102 is a drum-shaped image carrier having a photosensitive layer on its surface. The photoconductor 102 is driven to rotate clockwise in FIG. 1 around the drum axis. The charger 107 uniformly charges the surface of the rotating photoconductor 102 to a predetermined potential with a predetermined polarity. The exposure head 106 is an exposure device that exposes the uniformly charged surface of the photoconductor 102 to light to form an electrostatic latent image on the surface of the photoconductor 102. As will be described in detail later, the exposure head 106 of this embodiment has a configuration in which multiple light-emitting elements are arranged in a plane.

[0013] The developing unit 108 develops the electrostatic latent image formed on the photoconductor 102 with a developer (e.g., toner) to form a toner image on the surface of the photoconductor 102. The toner images formed on the surface of the photoconductor 102 are sequentially transferred to a sheet transported on a transfer belt 111. The toner images of the four photoconductors 102 are superimposed and transferred to the sheet. As a result, a color image containing four color components, black, yellow, magenta, and cyan, is formed on the sheet. The optical sensor 113 optically reads the adjustment image formed on the transfer belt 111 by the image forming unit 101.

[0014] The conveying unit 105 controls the feeding of sheets. Sheets can be fed from the internal storage units 109a and 109b, the external storage unit 109c, and the manual feed unit 109d. The conveying unit 105 feeds a sheet from any one of the internal storage units 109a and 109b, the external storage unit 109c, and the manual feed unit 109d to the conveying path. Registration rollers 110 are provided on the conveying path. The fed sheet is conveyed to the registration rollers 110.

[0015] Registration rollers 110 correct any skew of the sheet and transport the sheet onto transfer belt 111 at the appropriate timing so that the toner images on each photoconductor 102 are transferred to the predetermined positions on the sheet. As described above, the toner images are transferred onto the sheet while it is transported on transfer belt 111. Fixing unit 104 fixes the toner images onto the sheet by applying heat and pressure to the sheet onto which the toner images have been transferred. After the toner images have been fixed, the sheet is discharged outside image forming apparatus 1 by discharge rollers 112.

[0016] Inside the image forming apparatus 1, there is provided an image controller (described below) that performs various image processing such as color space conversion, filtering, magnification, resolution conversion, and quantization on the scanned image data and print image data. The image controller processes the scanned image data and print image data to generate print image data (hereinafter sometimes simply referred to as "image data") for image formation by the image creating unit 103. The image controller includes an image processing module that performs the various image processing described above.

[0017] Although a configuration has been described here in which a toner image is directly transferred from each photoconductor 102 to a sheet on the transfer belt 111, the toner image may also be indirectly transferred from each photoconductor 102 to a sheet via an intermediate transfer body. Also, although an example in which a color image is formed using toner of multiple colors has been described here, the technology according to this embodiment can also be applied to an image forming apparatus that forms a monochrome image using toner of a single color.

[0018] (Exposure head) 2 is an explanatory diagram of the photoconductor 102 and the exposure head 106. Fig. 2(a) is a perspective view of the photoconductor 102 and the exposure head 106. Fig. 2(b) is an explanatory diagram of the exposure position. The exposure head 106 has a light emitting element array 201 having a plurality of light emitting elements, a printed circuit board 202 on which the light emitting element array 201 is mounted, a rod lens array 203, and a housing 204 that holds the rod lens array 203 and the printed circuit board 202.

[0019] As described above, the photoconductor 102 has a drum shape. The exposure head 106 is disposed so that its longitudinal direction is parallel to the drum axis direction D1 of the photoconductor 102 and the mounting surface of the rod lens array 203 faces the surface of the photoconductor 102. While the photoconductor 102 rotates in the circumferential direction D2, the light-emitting element array 201 (light-emitting elements) of the exposure head 106 emits light, and the rod lens array 203 focuses the light on the surface of the photoconductor 102. The surface of the photoconductor 102 is uniformly charged by the charger 107, and the potential at the position where the light is focused is displaced. The position where the potential is displaced becomes an electrostatic latent image.

[0020] The light-emitting element array 201 has a plurality of light-emitting elements arranged in a plane. The light-emitting elements may be, for example, organic electroluminescence (EL) elements or light-emitting diodes (LEDs). The drum axial direction D1 is the main scanning direction, and the circumferential direction D2 is the sub-scanning direction perpendicular to the main scanning direction.

[0021] FIG. 3 is an explanatory diagram of the printed circuit board 202. A connector 305 and a light emitting element array 201 are mounted on different surfaces of the printed circuit board 202. FIG. 3(a) shows the surface of the printed circuit board 202 on which the connector 305 is mounted. FIG. 3(b) shows the surface of the printed circuit board 202 on which the light emitting element array 201 is mounted. The light emitting element array 201 includes a plurality of light emitting chips 400, each having a plurality of light emitting elements. In this embodiment, there are 20 light emitting chips 400 (light emitting chips 400-1 to 400-20). The light emitting chips 400-1 to 400-20 are arranged in a staggered pattern in the main scanning direction.

[0022] 3(b), the area occupied by all of the 20 light-emitting chips 400-1 to 400-20 in the main scanning direction is wider than the area occupied by the maximum width W0 of the image represented by the print image data. Therefore, some of the light-emitting elements located at both ends in the main scanning direction do not need to be used to expose the photosensitive element 102 unless image misalignment is detected. Each light-emitting chip 400 on the printed circuit board 202 is connected to an image controller (described later) via a connector 305.

[0023] For ease of explanation, the side with the smaller branch number of the light-emitting chips 400-1 to 400-20 arranged in the main scanning direction may be referred to as the "left" and the side with the larger branch number as the "right." For example, the light-emitting chip 400-1 is the leftmost light-emitting chip 400, and the light-emitting chip 400-20 is the rightmost light-emitting chip. In FIG. 4, the two rightmost light-emitting chips 400-n and 400-n+1 are illustrated.

[0024] FIG. 4 is an explanatory diagram of the light-emitting chip 400. The light-emitting element array 201 of this embodiment includes a plurality of light-emitting elements arranged in N columns in the main scanning direction and M rows in the sub-scanning direction as a whole. M and N are integers equal to or greater than 2. The number J (J=N / 20) of light-emitting elements 602 arranged in each row (main scanning direction) of one light-emitting chip 400 is, for example, 748 (J=748). The number M of light-emitting elements 602 arranged in each column (sub-scanning direction) of one light-emitting chip 400 is, for example, 4 (M=4). That is, in this example of this embodiment, the light-emitting chip 400 has 748 light-emitting elements 602 in the main scanning direction and 4 light-emitting elements in the sub-scanning direction, for a total of 2992 (=748×4) light-emitting elements 602.

[0025] The distance PC between the center points of adjacent light-emitting elements 602 in the sub-scanning direction is approximately 21.16 μm when the resolution is 1200 dpi, for example. The distance between the center points of adjacent light-emitting elements 602 in the main scanning direction is also approximately 21.16 μm. In this case, the length of the 748 light-emitting elements 602 in the main scanning direction is approximately 15.8 mm.

[0026] 4 shows an example in which the light emitting elements 602 of each light emitting chip 400 are arranged in a complete grid pattern for convenience, but in reality, M (M=4) light emitting elements 602 in each row are arranged in a staircase pattern, as will be described later.

[0027] 5 is a plan view of the light-emitting chip 400. A plurality of light-emitting elements 602 are formed on a light-emitting substrate 402, which is, for example, a silicon substrate. A circuit unit 406 for driving the plurality of light-emitting elements 602 is mounted on the light-emitting substrate 402. The light-emitting substrate 402 is provided with pads 408-1 to 408-9 to which signal lines for communicating with an image controller, power lines for connecting to a power source, and ground lines for grounding are connected. The signal lines, power lines, and ground lines are wires made of, for example, Au.

[0028] Figure 6 is a cross-sectional view taken along the line AA in Figure 5. A plurality of lower electrodes 504 are formed on the light-emitting substrate 402. A gap of length d is provided between two adjacent lower electrodes 504. A light-emitting layer 506 is provided on the lower electrodes 504, and an upper electrode 508 is provided on the light-emitting layer 506. The upper electrode 508 is a common electrode for the plurality of lower electrodes 504.

[0029] When a potential difference occurs between the lower electrode 504 and the upper electrode 508, a current flows from the lower electrode 504 to the upper electrode 508, causing the light-emitting layer 506 to emit light. Therefore, one lower electrode 504 and a partial region of the light-emitting layer 506 and upper electrode 508 corresponding to that lower electrode 504 constitute one light-emitting element 602. In this way, a plurality of light-emitting elements 602 are formed on the light-emitting substrate 402.

[0030] The light-emitting layer 506 may be made of, for example, an organic EL film. The upper electrode 508 is made of, for example, a transparent electrode such as indium tin oxide (ITO) so as to transmit the wavelength of light (emission wavelength) emitted from the light-emitting layer 506. In this embodiment, the entire upper electrode 508 transmits the emission wavelength of the light-emitting layer 506, but it is not necessary for the entire upper electrode 508 to transmit the emission wavelength. Specifically, it is sufficient that a partial region through which light from each light-emitting element 602 passes transmits the emission wavelength.

[0031] Although the light-emitting layer 506 of the present embodiment is formed as a single continuous light-emitting layer 506, a plurality of light-emitting layers 506 each having a width equal to the width W of the lower electrode 504 may be formed on the lower electrode 504, respectively. Furthermore, a first plurality of lower electrodes 504 of the lower electrodes 504 of each light-emitting chip 400 may be covered with a first light-emitting layer 506, and a second plurality of lower electrodes 504 may be covered with a second light-emitting layer 506. Furthermore, a first upper electrode 508 may be commonly formed corresponding to the first plurality of lower electrodes 504 of the lower electrodes 504 of each light-emitting chip 400, and a second upper electrode 508 may be commonly formed corresponding to the second plurality of lower electrodes 504. Even in such a configuration, one lower electrode 504 and the region of the light-emitting layer 506 and upper electrode 508 corresponding to the lower electrode 504 constitute one light-emitting element 602.

[0032] (Image controller of exposure head 106) 7 is a configuration diagram of an image controller that controls the turning on and off of the light-emitting chip 400. The image controller 700 can communicate with the printed circuit board 202 via multiple signal lines (wires). The image controller 700 has a CPU (Central Processing Unit) 701, a clock generation unit 702, an image data processing unit 703, a register access unit 704, a light emission control unit 705, a synchronization signal generation unit 706, and a memory 707.

[0033] The light-emitting control unit 705, together with the exposure head 106, constitutes an exposure device. The light-emitting control unit 705 terminates the signal line between it and the printed circuit board 202. The n-th light-emitting chip 400-n on the printed circuit board 202 is connected to the light-emitting control unit 705 by a signal line DATAn and a signal line WRITEn. The signal line DATAn transmits print image data from the image controller 700 to the light-emitting chip 400-n. The signal line WRITEn is a signal line that allows the image controller 700 to write control data to a register of the light-emitting chip 400-n.

[0034] One signal line CLK, one signal line SYNC, and one signal line EN are further provided between the light-emitting control unit 705 and each light-emitting chip 400. The signal line CLK transmits a clock signal for data transmission via the signal lines DATAn and WRITEn. The clock generation unit 702 generates a reference clock signal and transmits it to each unit of the image controller 700. The light-emitting control unit 705 transmits a clock signal generated based on the reference clock signal obtained from the clock generation unit 702 to each light-emitting chip 400 via the signal line CLK.

[0035] The synchronization signal generation unit 706 generates and outputs a synchronization signal synchronized with the reference clock signal obtained from the clock generation unit 702. The synchronization signal is a reference signal for the output timing of print image data from the output unit in the image data processing unit 703, and serves as a reference signal for the timing of sending print image data from the light emission control unit 705 to each light-emitting chip 400. The synchronization signal generation unit 706 outputs print image data from the light emission control unit 705 while coordinating with the image formation operation by the image creation unit 103, and generates the synchronization signal based on an image formation operation start signal (referred to as a "TOP signal" in this embodiment) from the image creation unit 103.

[0036] The CPU 701 controls the overall operation of the image forming apparatus 1. The memory 707 stores various data for controlling the overall operation of the image forming apparatus 1. For example, the memory 707 stores profile information that indicates the unique characteristics of the image forming apparatus 1. The image data processing unit 703 performs predetermined image processing on read image data and print image data obtained from the reading unit 100 or an external device. By performing image processing, the image data processing unit 703 generates binary image data (print image data) for controlling the light emission of the light emitting element 602 of the light emitting chip 400 on the printed circuit board 202.

[0037] The image processing performed by the image data processing unit 703 includes, for example, raster conversion, tone correction, color conversion, and halftone processing. The image data processing unit 703 transmits the generated binary image data (print image data) to the light emission control unit 705. The register access unit 704 receives control data to be written to the register in each light-emitting chip 400 from the CPU 701 and transmits it to the light emission control unit 705.

[0038] The image forming apparatus 1 has an exposure head 106 in each of the image forming units 101a to 101d. That is, in this embodiment, four printed circuit boards 202 are provided. The image controller 700 is connected to these four printed circuit boards 202, and controls the lighting of the multiple light-emitting elements 602 mounted on each of the four printed circuit boards 202.

[0039] FIG. 8 is a timing chart when control data is written to the register of each light-emitting chip 400. FIG. 8 shows the transition of the signal level of each signal line when control data is written to the register of the light-emitting chip 400. An enable signal, which is at a high level during communication and indicates that communication is in progress, is transmitted to the signal line EN. The light-emitting control unit 705 transmits a start bit to the signal line WRITEn in synchronization with the rising edge of the enable signal. Next, the light-emitting control unit 705 transmits a write identification bit, which indicates a write operation, to the signal line WRITEn, and then transmits the address (4 bits in this case) of the register to which the control data is to be written and the control data (8 bits in this case). When writing to the register, the light-emitting control unit 705 sets the frequency of the clock signal transmitted on the signal line CLK to, for example, 3 MHz.

[0040] 9 is a timing chart illustrating the transition of the signal level of each signal line when print image data is transmitted to each light-emitting chip 400. A periodic line synchronization signal indicating the exposure timing of each line on the photosensitive element 102 is transmitted to the signal line SYNC. If the peripheral speed of the photosensitive element 102 is 200 [mm / s] and the peripheral resolution is 1200 [dpi] (approximately 21.16 [μm]), the line synchronization signal is output at a period of approximately 105.8 [μs].

[0041] The light emission control unit 705 transmits print image data via signal lines DATA1 to DATA20 in synchronization with the rising edge of the line synchronization signal. Since each light emitting chip 400 in this embodiment has 2992 light emitting elements 602, it is necessary to transmit print image data to each light emitting chip 400 within a cycle of approximately 105.8 [μs] to control the light emission (illumination) of each of the 2992 light emitting elements 602. Therefore, in this embodiment, as shown in FIG. 9, when transmitting print image data, the light emission control unit 705 sets the frequency of the clock signal transmitted via the signal line CLK to 30 [MHz].

[0042] 10 is a detailed functional configuration diagram of one (n-th light-emitting chip 400-n) of the light-emitting chip 400. The circuit unit 406 includes a register 1102, a transfer unit 1103, latch units 1004-001 to 1004-748, and a current driver 1104.

[0043] As described in FIG. 5, the light-emitting chip 400 has nine pads 408-1 to 408-9. A power supply voltage VCC is applied to the pads 408-1 and 408-2 via a power supply line. The power supply voltage VCC is applied to each part of the circuit unit 406 of the light-emitting chip 400 via the pads 408-1 and 408-2. The pads 408-3 and 408-4 are grounded via a ground line. Each part of the circuit unit 406 and the upper electrode 508 are grounded via the pads 408-3 and 408-4.

[0044] The pad 408-5 is connected to a signal line CLK. The signal line CLK is connected to the transfer unit 1103, the register 1102, and the latch units 1004-001 to 1004-748 via the pad 408-5. The pad 408-6 is connected to a signal line SYNC. The pad 408-7 is connected to a signal line DATAn. The signal lines SYNC and DATAn are connected to the transfer unit 1103 via the pads 408-6 and 408-7. The pad 408-8 is connected to a signal line EN. The pad 408-9 is connected to a signal line WRITEn. The signal lines EN and WRITEn are connected to the register 1102 via the pads 408-8 and 408-9. The register 1102 stores control data indicating, for example, the light emission intensity of the light emitting element 602.

[0045] The transfer unit 1103 starts with a line synchronization signal obtained from the signal line SYNC, and synchronizes with a clock signal obtained from the signal line CLK to obtain print image data from the signal line DATAn, the print image data including a series of pixel values ​​each indicating the lighting or extinguishing of one light-emitting element 602. The transfer unit 1103 performs serial-to-parallel conversion on the series of pixel values ​​serially obtained from the signal line DATAn in units of M (for example, M=4).

[0046] For example, the transfer unit 1103 has four cascade-connected D flip-flops. The transfer unit 1103 parallelizes pixel values ​​DATA-1, DATA-2, DATA-3, and DATA-4 input over a period of four clocks and sequentially transmits them to the latch units 1004-001 to 1004-748. The transfer unit 1103 also has four D flip-flops for delaying the line synchronization signal. The transfer unit 1103 outputs a first latch signal to the latch unit 1004-001 via the signal line LAT1 with a delay of four clocks from the input of the line synchronization signal. The first latch signal is, for example, a signal obtained by delaying the line synchronization signal by four clocks.

[0047] The kth latch unit 1004-k (k is an integer from 1 to 748) latches four pixel values ​​DATA-1, DATA-2, DATA-3, and DATA-4 input from the transfer unit 1103 simultaneously with the input of the kth latch signal. Except for the last-stage latch unit 1004-748, the kth latch unit 1004-k delays the kth latch signal by four clocks and outputs the (k+1)th latch signal to the latch unit 1004-(k+1) via the signal line LAT(k+1). The kth latch unit 1004-k continues to output drive signals based on the four latched pixel values ​​to the current drive unit 1104 during the signal period of the kth latch signal.

[0048] For example, there is a delay of four clocks between the timing at which the first latch signal is input to latch unit 1004-001 and the timing at which the second latch signal is input to latch unit 1004-002. Therefore, latch unit 1004-001 outputs a drive signal based on the first to fourth pixel values ​​to current driver 1104, while latch unit 1004-002 outputs a drive signal based on the fifth to eighth pixel values ​​to current driver 1104.

[0049] Generally speaking, the latch unit 1004-k outputs drive signals based on the (4k-3)th to (4k)th pixel values ​​to the current driver 1104. Therefore, in Fig. 10, 748 latch units 1004-001 to 1004-748 output 2992 drive signals in approximately parallel to the current driver 1104 for controlling the driving of 2992 (=748 × 4) light-emitting elements 602. Each drive signal is a binary signal indicating a high or low level.

[0050] The current driver 1104 has 2992 light-emitting drive circuits corresponding to the 2992 light-emitting elements 602, each of which includes a partial region of the light-emitting layer 506. While the drive signal is at a high level, which means that the light-emitting element 602 is on (lit), each light-emitting drive circuit applies a drive voltage corresponding to the light-emitting intensity indicated by the control data in the register 1102 to the light-emitting layer 506 of the corresponding light-emitting element 602. This causes a current to flow through the light-emitting layer 506, causing the light-emitting element 602 to emit light. The control data may indicate one individual light-emitting intensity for each light-emitting element 602, one light-emitting intensity for each group of light-emitting elements 602, or one light-emitting intensity common to all light-emitting elements 602.

[0051] (Multiple exposure control) 4 shows an example in which the light-emitting elements 602 of each light-emitting chip 400 are arranged in a grid pattern, but in reality, the M light-emitting elements 602 in each row are arranged in a stepped pattern at a constant pitch. Fig. 11 is an explanatory diagram of multiple exposure using the light-emitting elements 602 arranged in a stepped pattern. Fig. 11 partially illustrates an example of the arrangement of the light-emitting elements 602 of the light-emitting chip 400-1 when M=4.

[0052] Rj_m (j = {0, 1, ..., 747}, m = {0, 1, 2, 3}) indicates the light-emitting element 602 that is in the jth column from the left in the main scanning direction and the mth row from the top in the sub-scanning direction. The pitch PC of the light-emitting elements in the sub-scanning direction is determined by the size of the light-emitting elements 602 and is, for example, approximately 21.16 μm as described above. The interval in the main scanning direction between two adjacent light-emitting elements of the M light-emitting elements in each column, i.e., the pitch PA of the light-emitting elements 602 in the main scanning direction, is, for example, approximately 5 μm in the case of a resolution of 4800 dpi.

[0053] By arranging the four light-emitting elements 602 in each column in a stepped manner in this way, any two adjacent light-emitting elements 602 of the four light-emitting elements 602 have areas that partially overlap in the main scanning direction. While the photoconductor 102 is rotating, the four light-emitting elements 602 in the column corresponding to each pixel position of the print image data sequentially emit light, forming spots corresponding to each pixel position on the surface of the photoconductor 102.

[0054] In the example of FIG. 11, when the pixel value at the left end of the ith line of the print image data indicates lighting (ON), light-emitting elements R0_0, R0_1, R0_2, and R0_3 sequentially emit light at the timings at which they respectively face line Li on the surface of the photoconductor 102. As a result, the spot area at the left end of line Li is multiply exposed to form spot SP0. Similarly, when the jth pixel value from the left of the ith line of the print image data indicates lighting (ON), light-emitting elements Rj_0, Rj_1, Rj_2, and Rj_3 sequentially emit light at the timings at which they respectively face line Li on the surface of the photoconductor 102. As a result, the jth spot area from the left of line Li is multiply exposed to form a corresponding spot SPj.

[0055] In this manner, in this embodiment, the light-emitting elements in two rows adjacent to each other in the fast scanning direction occupy areas that partially overlap in the fast scanning direction. Similarly, of the two light-emitting chips 400 adjacent to each other in the fast scanning direction, the light-emitting elements in the rightmost row of the left light-emitting chip 400 and the light-emitting elements in the leftmost row of the right light-emitting chip 400 also occupy areas that partially overlap in the fast scanning direction (see FIG. 3(b)).

[0056] The pitch PA of the light-emitting elements 602 in the main scanning direction is constant (approximately 5 μm) across all 20 light-emitting chips 400. When the four light-emitting elements in each row of these light-emitting chips 400 emit light sequentially at appropriate timing, a smooth line of an electrostatic latent image is formed on the surface of the photoconductor 102, consisting of a series of spots that partially overlap each other at regular intervals. When such lines are formed continuously in the sub-scanning direction, a two-dimensional electrostatic latent image is generated on the surface of the photoconductor 102.

[0057] Figures 12, 13, and 14 are explanatory diagrams of output control by the light emission control unit 705 based on print image data. Figures 12(a), 12(b), 13(a), and 13(b) each show a case where the line synchronization signal shown in Figure 9 is received four times, starting from the first line of print image data IM1. Figure 14 shows a case where a line synchronization signal for outputting the final line of print image data IM1 is received.

[0058] 12(a), 12(b), 13(a), and the left diagram of FIG. 14, the order in which the light emission control unit 705 reads out the print image data IM1 is indicated by dashed lines. Rj-m within the dashed lines indicates the print image data output to the light emitting elements shown in FIG. 11. The order in which the print image data is output is as shown in the timing chart in FIG. 9. The light emission control unit 705 sequentially outputs the print image data in the order of R0-0 → R0-1 → R0-2 → R0-3 → R1-0 → R1-1.

[0059] The right diagrams of Figures 12(a), 12(b), 13(a), and 14 show a printout printed by the light emission control unit 705 sending the first four lines of the image of the print image data IM1 to the exposure head 106, where the printout is printed as a valid image. The shaded areas show the state where the image corresponding to the print image data IM1 is actually printed. The right diagrams of Figures 12(a), 12(b), 13(a), and 14 show that one line of image is formed by the light emission control unit 705 receiving the line synchronization signal four times.

[0060] 12(a), 12(b), 13(a), and 14, there are portions where there is no print image data IM1 to be output to the light-emitting element Rj_m. When there is no print image data IM1 corresponding to the image to be output, the light-emitting control unit 705 outputs "0" indicating "turn off."

[0061] (Image data processing unit) FIG. 15 is a configuration diagram of the image data processing unit 703. As described above, the image data processing unit 703 operates in synchronization with the synchronization signal input from the synchronization signal generation unit 706, and performs processing on image data in accordance with the control of the CPU 701. The image data processing unit 703 includes a scan I / F unit 1301, a host I / F unit 1302, a print data processing unit 1303, an image memory 1304, a DMA (Direct Memory Access) controller 1305, and an exposure head correction unit 1307. The scan I / F unit 1301, the host I / F unit 1302, the print data processing unit 1303, the image memory 1304, and the DMA controller 1305 are connected to each other via a bus 1311 so as to be able to communicate with each other. The bus 1311 includes an address bus and a data bus. The exposure head correction unit 1307 is connected to the DMA controller 1305.

[0062] The scan I / F unit 1301 is an interface that acquires scanned image data from the reading unit 100. The scan I / F unit 1301 performs predetermined processing on the acquired scanned image data and transmits it to a print data processing unit 1303. The scanned image data after the predetermined processing is multi-value bitmap data.

[0063] The host I / F unit 1302 is an interface that acquires image data for printing from an external device. The image data for printing is, for example, PDL (Page Description Language) data. The host I / F unit 1302 performs predetermined processing on the image data for printing to generate multi-value bitmap data and transmits it to the print data processing unit 1303.

[0064] The print data processing unit 1303 performs quantization processing, such as pseudo-halftoning using a dither pattern or error diffusion, on multi-value bitmap data acquired from the scan I / F unit 1301 or host I / F unit 1302. The print data processing unit 1303 generates binary image data from the bitmap data through quantization processing, for image formation by the image creating unit 103. The image represented by the binary image data has, for example, a resolution of 4800 dpi in the main scanning direction and 1200 dpi in the sub-scanning direction.

[0065] The print data processing unit 1303 stores the generated binary image data in an image memory 1304. The binary image data stored in the image memory 1304 is read out and controlled by a DMA controller 1305. The DMA controller 1305 controls the reading of the binary image data in accordance with instructions from the CPU 701. The DMA controller 1305 sequentially transmits the binary image data read out from the image memory 1304 to an exposure head correction unit 1307.

[0066] The exposure head correction unit 1307 performs digital correction on the binary image data obtained from the DMA controller 1305 in accordance with the characteristics of the exposure head 106. Through digital correction, the exposure head correction unit 1307 suppresses the effects of manufacturing variations in the components within the exposure head 106, such as differences in light intensity of the rod lens array 203 and the light-emitting chips 400-1 to 400-20. The exposure head correction unit 1307 transmits the corrected binary image data to the light-emission control unit 705 in synchronization with a synchronization signal obtained from the synchronization signal generation unit 706.

[0067] 16 is a detailed configuration diagram of the DMA controller 1305. The DMA controller 1305 includes a register unit 1401, an address generation unit 1402, a bus I / F unit 1403, a FIFO (Fast In Fast Out) 1404, and a DMA output I / F unit 1405.

[0068] The register unit 1401 has a plurality of registers. Instructions from the CPU 701 to the DMA controller 1305 are issued by writing appropriate values ​​to each register of the register unit 1401. The address generation unit 1402 generates an address signal indicating an address for reading binary image data from the image memory 1304 based on the values ​​set in each register of the register unit 1401. In response to a request signal (req) transmitted from the bus I / F unit 1403, the address generation unit 1402 transmits to the bus I / F unit 1403 an address signal (addr) and a length signal (length) indicating the length to be read starting from the address.

[0069] The bus I / F unit 1403 is an interface for accessing the image memory 1304 via the bus 1311. The bus I / F unit 1403 acquires an address signal and a length signal from the address generation unit 1402 and issues a read transaction to the bus 1311. For example, if the data bus width of the bus 1311 is 32 bits, the bus I / F unit 1403 resolves the address signal and the length signal into 32-bit signals and issues a read transaction. The read transaction is transmitted to the image memory 1304 via the bus 1311.

[0070] When the bus I / F unit 1403 completes processing for one set of address signal and length signal, it notifies the address generation unit 1402 of the completion of processing by using an acknowledge signal (ack). Upon receiving the acknowledge signal, the address generation unit 1402 waits for the next request signal from the bus I / F unit 1403. In response to the address signal and length signal specified in the read transaction, the image memory 1304 transmits to the bus I / F unit 1403 binary image data starting from the address specified by the address signal up to the address located at the length specified by the length signal.

[0071] The bus I / F unit 1403 temporarily stores the binary image data read from the image memory 1304 in the FIFO 1404. Even if there is a period when the exposure head correction unit 1307 is temporarily unable to acquire data, the DMA controller 1305 can wait until acquisition becomes possible by storing the binary image data in the FIFO 1404. This allows the binary image data to be immediately sent from the FIFO 1404 to the exposure head correction unit 1307 when it becomes possible for the exposure head correction unit 1307 to acquire data.

[0072] When the FIFO 1404 runs out of storage space for saving data (full state), it sends a FIFO full signal (full) to the bus I / F unit indicating that there is no storage space. The bus I / F unit 1403 monitors the FIFO full signal output from the FIFO 1404. When the FIFO 1404 is full, the bus I / F unit 1403 does not issue a read transaction and waits for the full state to be released.

[0073] The DMA output I / F unit 1405 is an interface for transmitting the binary image data stored in the FIFO 1404 to the exposure head correction unit 1307. When the FIFO 1404 does not store any binary image data, it transmits a FIFO empty signal (empty) indicating that there is no binary image data in the DMA output I / F unit 1405. The DMA output I / F unit 1405 monitors the FIFO empty signal output from the FIFO 1404.

[0074] If the FIFO 1404 is not empty and the exposure head correction unit 1307 is ready to acquire data, the DMA output I / F unit 1405 reads binary image data from the FIFO 1404 and transmits it to the exposure head correction unit 1307. The DMA controller 1305 may read the binary image data that will actually be used from the image memory 1304 in an overlapping manner (equivalent to reading it twice). In this case, the DMA output I / F unit 1405 can also discard the binary image data that has been read in an overlapping manner, depending on whether or not the binary image data that has been read in an overlapping manner will be used in subsequent processing (here, the exposure head correction unit 1307).

[0075] (Registration error) The exposure head 106 may be mounted in a position that is offset from the ideal position relative to the photoconductor 102. The exposure head 106 may also be mounted with the printed circuit board 202 in a position that is offset from the ideal position. These offsets cause deviations in the exposure position when the photoconductor 102 is exposed in the main scanning direction. The exposure position offset also occurs in the sub-scanning direction. The exposure position offset causes deviations in the position of the formed image, degrading image quality. Such exposure position offset is called "registration offset."

[0076] FIG. 17 is an explanatory diagram of misregistration. The photosensitive element 102 is ideally exposed linearly in the main scanning direction by the exposure head 106. The linear exposure position by the exposure head 106 is called a scanning line. The upper diagram in FIG. 17 shows a state in which the scanning line is bent in the sub-scanning direction due to misregistration. Such misregistration is detected, for example, during the manufacture of the image forming apparatus 1 by inspecting the characteristics of the image forming apparatus 1. For example, misregistration is detected by forming various images on a sheet using the image forming apparatus 1. The detected misregistration is stored in the memory 707, for example, as one piece of profile information for the image forming apparatus 1.

[0077] As described above, binary image data is transmitted from the image data processing unit 703 to the light emission control unit 705. At this time, the image data processing unit 703 divides one line in the main scanning direction into multiple segments and transmits binary image data for each segment. The address signal and length signal specify, for example, the binary image data for each segment. In this embodiment, the line is switched for each segment depending on the curvature of the scanning line, and the binary image data is transmitted from the image data processing unit 703 to the light emission control unit 705. The binary image data is configured so that one line's worth of image in the main scanning direction includes multiple lines in the sub-scanning direction. By switching the line, binary image data for a different line is transmitted. The line to be switched is determined based on the profile information of the image forming apparatus 1. By switching the line for each segment and transmitting binary image data, an image in which the curvature of the scanning line has been corrected is formed.

[0078] In FIG. 17, n lines, (n-1) lines, (n-2) lines, (n-3) lines, (n-4) lines, (n-3) lines, (n-2) lines, (n-1) lines, n lines, (n+1) lines, n lines, and (n-1) lines are specified for each segment. The image data processing unit 703 reads binary image data from the image memory 1304 while switching the lines of binary image data for each segment in the main scanning direction in the specified order. The image data processing unit 703 transmits the binary image data of the lines specified for each segment in the main scanning direction to the light emission control unit 705. In this way, the binary image data is input to the light emission control unit 705 for each segment while switching the lines according to the curvature of the scanning line, thereby suppressing misalignment and degradation of image quality in the final image.

[0079] Fig. 18 is an enlarged view of a portion of the scanning line in Fig. 17. Since the lines of binary image data to be transmitted for each segment are set, the DMA controller 1305 of the image data processing unit 703 generates addresses to read from the image memory 1304 in accordance with the curve of the scanning line.

[0080] Fig. 19 is a diagram for explaining the operation of the DMA controller 1305. Fig. 19 is a diagram for explaining a method for correcting the curvature of a scanning line (registration error correction) in the DMA controller 1305.

[0081] A register RegSegLen that specifies the length of a segment in the main scanning direction is provided in the register unit 1401 of the DMA controller 1305. The register unit 1401 is provided with a necessary number of register groups RegUpDown[i] that specify whether or not to switch lines of binary image data transmitted in adjacent segments in accordance with the curve of the scanning line, and if so, the direction of switching.

[0082] There are three possible values ​​for the register group RegUpDown[i]. Here, the register group RegUpDown[i] is set to "00" or "01" if the line is not to be switched, "10" if the line is to be switched up, and "11" if the line is to be switched down. "i" is a value greater than or equal to 0 that indicates the interval between segments.

[0083] The register unit 1401 is provided with a register RegOverlapLen that specifies the length to be read before and after the line switching portion when lines switch between adjacent segments. The register unit 1401 is set with a register RegStartAddr that specifies the start address of the binary image data stored in the image memory 1304. The register unit 1401 is set with a register RegLineLen that indicates the line length of the binary image data. The register unit 1401 is set with a register RegLineOffset that specifies the offset value of the addresses of adjacent lines of the binary image data. The register unit 1401 is set with RegBeams that specifies the number of lines to be sent to the exposure head correction unit 1307.

[0084] In the example of Figure 19, between the first and second segments the line does not switch. Therefore, register group RegUpDown[0] is set to "00". Between the second and third segments the line switches up. Therefore, register group RegUpDown[1] is set to "10". Between the third and fourth segments the line switches up. Therefore, register group RegUpDown[2] is set to "10". Between the fourth and fifth segments the line switches down. Therefore, register group RegUpDown[3] is set to "11". Between the fifth and sixth segments the line does not switch. Therefore, register group RegUpDown[4] is set to "00".

[0085] The above register settings are performed by the CPU 701 in the register unit 1401. After the CPU 701 has completed the above register settings, a start register is set in the register unit 1401 to start DMA operation.

[0086] 20 is a flowchart showing the operation of the DMA controller 1305. An address generator 1402 generates an address of binary image data to be read for each segment from the image memory 1304. The address is determined according to the degree of curvature of the scanning line.

[0087] S100: When DMA operation is started in response to an instruction from the CPU 701, the DMA controller 1305 initializes a signal line_start_addr, which stores the start address of each line in the register unit 1401, with the value of the register RegStartAddr. The DMA controller 1305 also initializes a signal line_cnt, which indicates the number of lines sent to the exposure head correction unit 1307, to zero.

[0088] S101: The DMA controller 1305 performs initialization for each line. The initialization for each line includes the following: The signal seg_addr, which indicates the start address of the segment, is initialized with the value of the signal line_start_addr. The signal line_data_cnt, which counts the amount of data processed in the line, is initialized to zero. The signal up_down_front, which indicates a line switch at the front of the segment, is initialized to "00". This indicates that there is no line switch at the front of the segment at the beginning of the line. The signal index, which indicates the index of the register group RegUpDown[i] to be referenced, is initialized to zero.

[0089] S102: The DMA controller 1305 performs initialization for each segment. The initialization for each segment includes the following: The address signal and length signal (addr and length) indicating the address and length to be requested from the bus I / F unit 1403 are initialized with the signal seg_addr indicating the start address of the segment and the value of the register RegSegLen, respectively. These signals may be changed in subsequent processing. The line switching signal up_down_back indicating line switching at the end of the segment is set to the value of the register group RegUpDown[i].

[0090] S103: The DMA controller 1305 determines whether there is a line switch at the front of the segment based on the value of the up_down_front signal. If there is a line switch at the front of the segment, the DMA controller 1305 subtracts the value of RegOverwrapLen from the address signal (addr) and adds the value of RegOverwrapLen to the length signal (length). This achieves overlap in the reading of binary image data at the front of the segment. If there is no line switch at the front of the segment, this process is not performed.

[0091] S104: The DMA controller 1305 determines whether there is a line switch at the end of the segment based on the value of the line switch signal up_down_back. If there is a line switch at the end of the segment, the DMA controller 1305 adds the value of RegOverwrapLen to the length signal (length). This allows the reading of binary image data at the end of the segment to overlap. If there is no line switch at the end of the segment, this process is not performed.

[0092] S105: The DMA controller 1305 issues a read request to the bus I / F unit 1403 using an address signal (addr) and a length signal (length).

[0093] S106: The DMA controller 1305 determines whether there is a line switch after the current segment in order to update the signal seg_addr indicating the start address of the segment to the start address of the next segment. Whether there is a line switch after the current segment is determined based on the value of the line switch signal up_down_back. When switching to an upper line, the DMA controller 1305 subtracts the value of the register RegLineOffset from the signal seg_addr to switch the starting address of the segment to the upper line.When switching to a lower line, the DMA controller 1305 adds the value of the register RegLineOffset to the signal seg_addr to switch the starting address of the segment to the lower line.

[0094] S107: If there is no line switching after the segment, or after updating the signal seg_addr, the DMA controller 1305 updates each signal for processing the next segment. The updating of each signal includes the following: The signal seg_addr is incremented by the value of the register RegSegLen. The signal line_data_cnt, which counts the amount of processing in the line, is incremented by the value of the register RegSegLen. The signal up_down_back, which indicates whether or not to switch lines after the current segment, becomes the switching signal for the front side of the next segment. For this reason, the signal up_down_front is set to the value of the signal up_down_back. The signal index is incremented by 1 to advance the referenced register group RegUpDown[i] by one.

[0095] S108: The DMA controller 1305 compares the value of the register RegLineLen minus the value of the signal line_data_cnt with the value of the register RegSegLen to determine the end of processing one line. If the comparison result shows that the difference is greater than the value of the register RegSegLen, there are two or more segments to process. Therefore, the DMA controller 1305 returns to S102 and repeats processing the segments. If the difference is less than the value of the register RegSegLen, the DMA controller 1305 performs the following processing to process the last segment in the line.

[0096] S109: The DMA controller 1305 starts processing the last segment in the line and performs fractional processing at the end of one line. The DMA controller 1305 updates the address signal and length signal (addr and length) that indicate the address and length to be requested from the bus I / F unit 1403. The address signal and length signal (addr and length) are set to values ​​obtained by subtracting the value of the signal line_data_cnt from the values ​​of the signal seg_addr and register RegLineLen, which indicate the start address of the segment, respectively.

[0097] Next, the DMA controller 1305 determines whether there is a line change at the front of the segment based on the value of the up_down_front signal. Note that for the last segment in a line, only the line change signal up_down_front at the front of the segment is referenced. If there is a line change at the front of the segment, the DMA controller 1305 subtracts the value of RegOverwrapLen from addr and adds the value of RegOverwrapLen to length. This achieves overlap in the reading of binary image data at the front of the segment.

[0098] If there is no line switching at the front of the segment, or if the address signal and length signal are updated, the DMA controller 1305 issues a read request to the bus I / F unit 1403 in response to the address signal and length signal.

[0099] S110: The DMA controller 1305 updates each signal for processing the next line. The DMA controller 1305 adds the value of the register RegLineOffset to the signal line_start_addr, which indicates the start address of each line, and updates the signal line_start_addr to the start address of the next line. The DMA controller 1305 increments the signal line_cnt, which indicates the number of lines sent to the exposure head correction unit 1307, by 1.

[0100] S111: The DMA controller 1305 compares the signal line_cnt with the value of the register RegBeams to determine the end of the page. If the value of the signal line_cnt is less than the value of the register RegBeams, there are still lines to be processed, so the DMA controller 1305 returns to the process of S101 and repeats the process. If the value of the signal line_cnt is equal to or greater than the value of the register RegBeams, the DMA controller 1305 ends the DMA process. When the DMA process ends, the DMA controller 1305 sends an interrupt signal to the CPU 701. The CPU 701 receives the interrupt signal to detect the end of the DMA process.

[0101] Figures 21 and 22 are explanatory diagrams of the effect of registration error correction. The left diagrams of Figures 21(a), 21(b), 22(a), and 22(b) illustrate examples of the state of print image data IM1 when registration error correction is not performed by the DMA controller 1305. The right diagrams of Figures 21(a), 21(b), 22(a), and 22(b) illustrate examples of the state of print image data IM1 when registration error correction is performed by the DMA controller 1305.

[0102] Regardless of whether misregistration correction has been performed or not, the light emission control unit 705 sequentially outputs multiple lines of print image data IM1. However, if misregistration correction has been performed, line data corresponding to the misregistration is output for each segment in the main scanning direction. For this reason, the light emission control unit 705 outputs binary image data for each line for each segment.

[0103] As described above, in the image forming apparatus 1 of this embodiment, even if the exposure head 106 is attached at a position that is shifted from the ideal position relative to the photosensitive member 102, image data for a line corresponding to the shift of the exposure head 106 for each segment in the main scanning direction is transmitted to the exposure head 106. This makes it possible to suppress misalignment of the image on the sheet and degradation of image quality that occurs due to the shift of the exposure head 106.

[0104] The specific numerical values ​​used in the above description are merely examples, and the present invention is not limited to the numerical values ​​used in the embodiments. For example, the number of light-emitting chips 400 mounted on one printed circuit board 202 is not limited to 20, as long as it is one or more. The number of light-emitting elements 602 included in each light-emitting chip 400 is also not limited to 2992. In this embodiment, one light-emitting chip 400 is configured with four sets of 748 light-emitting elements 602 arranged along the main scanning direction, but the number of sets may be one or more. The light-emitting elements 602 are arranged in the main scanning direction at a pitch of approximately 21.16 μm, which corresponds to a resolution of 1200 dpi. However, the arrangement interval of the light-emitting elements 602 may be set according to the resolution and number of light-emitting elements 602. The number and arrangement interval of the light-emitting elements 602 included in the exposure head 106 may be determined based on the resolution and image size of the image formed by the image forming apparatus 1.

[0105] In the above explanation, misregistration is corrected by determining, for each segment, the line from which binary image data is read from the image memory 1304. Misregistration can also be corrected by correcting the binary image data itself. For example, when the print data processing unit 1303 performs quantization processing on multi-value bitmap data, the image data processing unit 703 can correct misregistration by shifting the data for each segment in the sub-scanning direction.

[0106] The print data processing unit 1303 corrects, for example, the multi-value bitmap data shown in the right diagram of FIG. 22(a) to the multi-value bitmap data shown in the left diagram of FIG. 22(b) based on the registration error in the profile information. This corrects the registration error. The print data processing unit 1303 stores binary image data generated by quantizing the bitmap data after the registration error correction in the image memory 1304. When reading the binary image data from the image memory 1304, the DMA controller 1305 reads the binary image data one line at a time and transmits it to the exposure head correction unit 1307 without switching the lines to be read for each segment. This results in an image with the registration error corrected. Alternatively, the registration error may be corrected by combining the correction of the multi-value bitmap data with switching the lines to be read for each segment of the binary image data.

Claims

1. A photoreceptor; an exposure unit having a plurality of light-emitting elements and exposing the photosensitive member to the light-emitting elements to form an image; a control means for transmitting image data including data representing an image of one line in a first direction for a plurality of lines in a second direction perpendicular to the first direction to the exposure means, and for forming an image corresponding to the image data on the photosensitive member by the exposure means; the control means divides one line in the first direction into a plurality of segments, corrects the deviation for each segment based on information representing the deviation of the exposure position of the photosensitive member by the exposure means, and transmits the image data to the exposure means. Image forming device.

2. the control means transmits line image data based on the information to the exposure means for each segment.

2. The image forming apparatus according to claim 1.

3. the control means determines a line of image data to be transmitted to the exposure means for each segment based on the information.

3. The image forming apparatus according to claim 2.

4. The control means includes: a storage means for storing the image data; reading means for reading the image data from the storage means; The reading means determines an address from which the image data is read from the storage means in accordance with the information.

3. The image forming apparatus according to claim 2.

5. the control means has a register in which a value indicating whether or not to switch lines for each segment is set based on the information; an address for reading out the image data from the storage means is determined based on the value set in the register; 5. The image forming apparatus according to claim 4.

6. The value indicating whether or not to switch the line for each segment includes a value indicating a direction of switching if the line is to be switched.

6. The image forming apparatus according to claim 5.

7. the control means reads image data from the storage means without switching lines if the value set for each segment does not represent a line change, and reads image data of a line in the direction of the line change from the storage means if the value represents a line change.

7. The image forming apparatus according to claim 6.

8. the control means transmits image data corrected based on the information to the exposure means for each segment.

2. The image forming apparatus according to claim 1.

9. the control means includes: a storage means for storing the corrected image data; a readout means for reading out the corrected image data from the storage means, the corrected image data read by the reading means is transmitted to the exposure means.

9. The image forming apparatus according to claim 8.

10. Further comprising a storage means for storing the information.

2. The image forming apparatus according to claim 1.

11. the exposure means has a plurality of light-emitting chips, each of which has a plurality of light-emitting elements mounted thereon; The plurality of light emitting chips are arranged in a staggered pattern in the first direction.

2. The image forming apparatus according to claim 1.

Images